Loading...
1
2/*
3 * Texas Instruments AM35x "glue layer"
4 *
5 * Copyright (c) 2010, by Texas Instruments
6 *
7 * Based on the DA8xx "glue layer" code.
8 * Copyright (c) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
9 *
10 * This file is part of the Inventra Controller Driver for Linux.
11 *
12 * The Inventra Controller Driver for Linux is free software; you
13 * can redistribute it and/or modify it under the terms of the GNU
14 * General Public License version 2 as published by the Free Software
15 * Foundation.
16 *
17 * The Inventra Controller Driver for Linux is distributed in
18 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
19 * without even the implied warranty of MERCHANTABILITY or
20 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
21 * License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with The Inventra Controller Driver for Linux ; if not,
25 * write to the Free Software Foundation, Inc., 59 Temple Place,
26 * Suite 330, Boston, MA 02111-1307 USA
27 *
28 */
29
30#include <linux/module.h>
31#include <linux/clk.h>
32#include <linux/err.h>
33#include <linux/io.h>
34#include <linux/platform_device.h>
35#include <linux/dma-mapping.h>
36#include <linux/usb/usb_phy_generic.h>
37#include <linux/platform_data/usb-omap.h>
38
39#include "musb_core.h"
40
41/*
42 * AM35x specific definitions
43 */
44/* USB 2.0 OTG module registers */
45#define USB_REVISION_REG 0x00
46#define USB_CTRL_REG 0x04
47#define USB_STAT_REG 0x08
48#define USB_EMULATION_REG 0x0c
49/* 0x10 Reserved */
50#define USB_AUTOREQ_REG 0x14
51#define USB_SRP_FIX_TIME_REG 0x18
52#define USB_TEARDOWN_REG 0x1c
53#define EP_INTR_SRC_REG 0x20
54#define EP_INTR_SRC_SET_REG 0x24
55#define EP_INTR_SRC_CLEAR_REG 0x28
56#define EP_INTR_MASK_REG 0x2c
57#define EP_INTR_MASK_SET_REG 0x30
58#define EP_INTR_MASK_CLEAR_REG 0x34
59#define EP_INTR_SRC_MASKED_REG 0x38
60#define CORE_INTR_SRC_REG 0x40
61#define CORE_INTR_SRC_SET_REG 0x44
62#define CORE_INTR_SRC_CLEAR_REG 0x48
63#define CORE_INTR_MASK_REG 0x4c
64#define CORE_INTR_MASK_SET_REG 0x50
65#define CORE_INTR_MASK_CLEAR_REG 0x54
66#define CORE_INTR_SRC_MASKED_REG 0x58
67/* 0x5c Reserved */
68#define USB_END_OF_INTR_REG 0x60
69
70/* Control register bits */
71#define AM35X_SOFT_RESET_MASK 1
72
73/* USB interrupt register bits */
74#define AM35X_INTR_USB_SHIFT 16
75#define AM35X_INTR_USB_MASK (0x1ff << AM35X_INTR_USB_SHIFT)
76#define AM35X_INTR_DRVVBUS 0x100
77#define AM35X_INTR_RX_SHIFT 16
78#define AM35X_INTR_TX_SHIFT 0
79#define AM35X_TX_EP_MASK 0xffff /* EP0 + 15 Tx EPs */
80#define AM35X_RX_EP_MASK 0xfffe /* 15 Rx EPs */
81#define AM35X_TX_INTR_MASK (AM35X_TX_EP_MASK << AM35X_INTR_TX_SHIFT)
82#define AM35X_RX_INTR_MASK (AM35X_RX_EP_MASK << AM35X_INTR_RX_SHIFT)
83
84#define USB_MENTOR_CORE_OFFSET 0x400
85
86struct am35x_glue {
87 struct device *dev;
88 struct platform_device *musb;
89 struct platform_device *phy;
90 struct clk *phy_clk;
91 struct clk *clk;
92};
93
94/*
95 * am35x_musb_enable - enable interrupts
96 */
97static void am35x_musb_enable(struct musb *musb)
98{
99 void __iomem *reg_base = musb->ctrl_base;
100 u32 epmask;
101
102 /* Workaround: setup IRQs through both register sets. */
103 epmask = ((musb->epmask & AM35X_TX_EP_MASK) << AM35X_INTR_TX_SHIFT) |
104 ((musb->epmask & AM35X_RX_EP_MASK) << AM35X_INTR_RX_SHIFT);
105
106 musb_writel(reg_base, EP_INTR_MASK_SET_REG, epmask);
107 musb_writel(reg_base, CORE_INTR_MASK_SET_REG, AM35X_INTR_USB_MASK);
108
109 /* Force the DRVVBUS IRQ so we can start polling for ID change. */
110 musb_writel(reg_base, CORE_INTR_SRC_SET_REG,
111 AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT);
112}
113
114/*
115 * am35x_musb_disable - disable HDRC and flush interrupts
116 */
117static void am35x_musb_disable(struct musb *musb)
118{
119 void __iomem *reg_base = musb->ctrl_base;
120
121 musb_writel(reg_base, CORE_INTR_MASK_CLEAR_REG, AM35X_INTR_USB_MASK);
122 musb_writel(reg_base, EP_INTR_MASK_CLEAR_REG,
123 AM35X_TX_INTR_MASK | AM35X_RX_INTR_MASK);
124 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
125 musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
126}
127
128#define portstate(stmt) stmt
129
130static void am35x_musb_set_vbus(struct musb *musb, int is_on)
131{
132 WARN_ON(is_on && is_peripheral_active(musb));
133}
134
135#define POLL_SECONDS 2
136
137static struct timer_list otg_workaround;
138
139static void otg_timer(unsigned long _musb)
140{
141 struct musb *musb = (void *)_musb;
142 void __iomem *mregs = musb->mregs;
143 u8 devctl;
144 unsigned long flags;
145
146 /*
147 * We poll because AM35x's won't expose several OTG-critical
148 * status change events (from the transceiver) otherwise.
149 */
150 devctl = musb_readb(mregs, MUSB_DEVCTL);
151 dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
152 usb_otg_state_string(musb->xceiv->otg->state));
153
154 spin_lock_irqsave(&musb->lock, flags);
155 switch (musb->xceiv->otg->state) {
156 case OTG_STATE_A_WAIT_BCON:
157 devctl &= ~MUSB_DEVCTL_SESSION;
158 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
159
160 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
161 if (devctl & MUSB_DEVCTL_BDEVICE) {
162 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
163 MUSB_DEV_MODE(musb);
164 } else {
165 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
166 MUSB_HST_MODE(musb);
167 }
168 break;
169 case OTG_STATE_A_WAIT_VFALL:
170 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
171 musb_writel(musb->ctrl_base, CORE_INTR_SRC_SET_REG,
172 MUSB_INTR_VBUSERROR << AM35X_INTR_USB_SHIFT);
173 break;
174 case OTG_STATE_B_IDLE:
175 devctl = musb_readb(mregs, MUSB_DEVCTL);
176 if (devctl & MUSB_DEVCTL_BDEVICE)
177 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
178 else
179 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
180 break;
181 default:
182 break;
183 }
184 spin_unlock_irqrestore(&musb->lock, flags);
185}
186
187static void am35x_musb_try_idle(struct musb *musb, unsigned long timeout)
188{
189 static unsigned long last_timer;
190
191 if (timeout == 0)
192 timeout = jiffies + msecs_to_jiffies(3);
193
194 /* Never idle if active, or when VBUS timeout is not set as host */
195 if (musb->is_active || (musb->a_wait_bcon == 0 &&
196 musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)) {
197 dev_dbg(musb->controller, "%s active, deleting timer\n",
198 usb_otg_state_string(musb->xceiv->otg->state));
199 del_timer(&otg_workaround);
200 last_timer = jiffies;
201 return;
202 }
203
204 if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
205 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n");
206 return;
207 }
208 last_timer = timeout;
209
210 dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
211 usb_otg_state_string(musb->xceiv->otg->state),
212 jiffies_to_msecs(timeout - jiffies));
213 mod_timer(&otg_workaround, timeout);
214}
215
216static irqreturn_t am35x_musb_interrupt(int irq, void *hci)
217{
218 struct musb *musb = hci;
219 void __iomem *reg_base = musb->ctrl_base;
220 struct device *dev = musb->controller;
221 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
222 struct omap_musb_board_data *data = plat->board_data;
223 struct usb_otg *otg = musb->xceiv->otg;
224 unsigned long flags;
225 irqreturn_t ret = IRQ_NONE;
226 u32 epintr, usbintr;
227
228 spin_lock_irqsave(&musb->lock, flags);
229
230 /* Get endpoint interrupts */
231 epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_REG);
232
233 if (epintr) {
234 musb_writel(reg_base, EP_INTR_SRC_CLEAR_REG, epintr);
235
236 musb->int_rx =
237 (epintr & AM35X_RX_INTR_MASK) >> AM35X_INTR_RX_SHIFT;
238 musb->int_tx =
239 (epintr & AM35X_TX_INTR_MASK) >> AM35X_INTR_TX_SHIFT;
240 }
241
242 /* Get usb core interrupts */
243 usbintr = musb_readl(reg_base, CORE_INTR_SRC_MASKED_REG);
244 if (!usbintr && !epintr)
245 goto eoi;
246
247 if (usbintr) {
248 musb_writel(reg_base, CORE_INTR_SRC_CLEAR_REG, usbintr);
249
250 musb->int_usb =
251 (usbintr & AM35X_INTR_USB_MASK) >> AM35X_INTR_USB_SHIFT;
252 }
253 /*
254 * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
255 * AM35x's missing ID change IRQ. We need an ID change IRQ to
256 * switch appropriately between halves of the OTG state machine.
257 * Managing DEVCTL.SESSION per Mentor docs requires that we know its
258 * value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
259 * Also, DRVVBUS pulses for SRP (but not at 5V) ...
260 */
261 if (usbintr & (AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT)) {
262 int drvvbus = musb_readl(reg_base, USB_STAT_REG);
263 void __iomem *mregs = musb->mregs;
264 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
265 int err;
266
267 err = musb->int_usb & MUSB_INTR_VBUSERROR;
268 if (err) {
269 /*
270 * The Mentor core doesn't debounce VBUS as needed
271 * to cope with device connect current spikes. This
272 * means it's not uncommon for bus-powered devices
273 * to get VBUS errors during enumeration.
274 *
275 * This is a workaround, but newer RTL from Mentor
276 * seems to allow a better one: "re"-starting sessions
277 * without waiting for VBUS to stop registering in
278 * devctl.
279 */
280 musb->int_usb &= ~MUSB_INTR_VBUSERROR;
281 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
282 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
283 WARNING("VBUS error workaround (delay coming)\n");
284 } else if (drvvbus) {
285 MUSB_HST_MODE(musb);
286 otg->default_a = 1;
287 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
288 portstate(musb->port1_status |= USB_PORT_STAT_POWER);
289 del_timer(&otg_workaround);
290 } else {
291 musb->is_active = 0;
292 MUSB_DEV_MODE(musb);
293 otg->default_a = 0;
294 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
295 portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
296 }
297
298 /* NOTE: this must complete power-on within 100 ms. */
299 dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
300 drvvbus ? "on" : "off",
301 usb_otg_state_string(musb->xceiv->otg->state),
302 err ? " ERROR" : "",
303 devctl);
304 ret = IRQ_HANDLED;
305 }
306
307 /* Drop spurious RX and TX if device is disconnected */
308 if (musb->int_usb & MUSB_INTR_DISCONNECT) {
309 musb->int_tx = 0;
310 musb->int_rx = 0;
311 }
312
313 if (musb->int_tx || musb->int_rx || musb->int_usb)
314 ret |= musb_interrupt(musb);
315
316eoi:
317 /* EOI needs to be written for the IRQ to be re-asserted. */
318 if (ret == IRQ_HANDLED || epintr || usbintr) {
319 /* clear level interrupt */
320 if (data->clear_irq)
321 data->clear_irq();
322 /* write EOI */
323 musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
324 }
325
326 /* Poll for ID change */
327 if (musb->xceiv->otg->state == OTG_STATE_B_IDLE)
328 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
329
330 spin_unlock_irqrestore(&musb->lock, flags);
331
332 return ret;
333}
334
335static int am35x_musb_set_mode(struct musb *musb, u8 musb_mode)
336{
337 struct device *dev = musb->controller;
338 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
339 struct omap_musb_board_data *data = plat->board_data;
340 int retval = 0;
341
342 if (data->set_mode)
343 data->set_mode(musb_mode);
344 else
345 retval = -EIO;
346
347 return retval;
348}
349
350static int am35x_musb_init(struct musb *musb)
351{
352 struct device *dev = musb->controller;
353 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
354 struct omap_musb_board_data *data = plat->board_data;
355 void __iomem *reg_base = musb->ctrl_base;
356 u32 rev;
357
358 musb->mregs += USB_MENTOR_CORE_OFFSET;
359
360 /* Returns zero if e.g. not clocked */
361 rev = musb_readl(reg_base, USB_REVISION_REG);
362 if (!rev)
363 return -ENODEV;
364
365 musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
366 if (IS_ERR_OR_NULL(musb->xceiv))
367 return -EPROBE_DEFER;
368
369 setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
370
371 /* Reset the musb */
372 if (data->reset)
373 data->reset();
374
375 /* Reset the controller */
376 musb_writel(reg_base, USB_CTRL_REG, AM35X_SOFT_RESET_MASK);
377
378 /* Start the on-chip PHY and its PLL. */
379 if (data->set_phy_power)
380 data->set_phy_power(1);
381
382 msleep(5);
383
384 musb->isr = am35x_musb_interrupt;
385
386 /* clear level interrupt */
387 if (data->clear_irq)
388 data->clear_irq();
389
390 return 0;
391}
392
393static int am35x_musb_exit(struct musb *musb)
394{
395 struct device *dev = musb->controller;
396 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
397 struct omap_musb_board_data *data = plat->board_data;
398
399 del_timer_sync(&otg_workaround);
400
401 /* Shutdown the on-chip PHY and its PLL. */
402 if (data->set_phy_power)
403 data->set_phy_power(0);
404
405 usb_put_phy(musb->xceiv);
406
407 return 0;
408}
409
410/* AM35x supports only 32bit read operation */
411static void am35x_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
412{
413 void __iomem *fifo = hw_ep->fifo;
414 u32 val;
415 int i;
416
417 /* Read for 32bit-aligned destination address */
418 if (likely((0x03 & (unsigned long) dst) == 0) && len >= 4) {
419 readsl(fifo, dst, len >> 2);
420 dst += len & ~0x03;
421 len &= 0x03;
422 }
423 /*
424 * Now read the remaining 1 to 3 byte or complete length if
425 * unaligned address.
426 */
427 if (len > 4) {
428 for (i = 0; i < (len >> 2); i++) {
429 *(u32 *) dst = musb_readl(fifo, 0);
430 dst += 4;
431 }
432 len &= 0x03;
433 }
434 if (len > 0) {
435 val = musb_readl(fifo, 0);
436 memcpy(dst, &val, len);
437 }
438}
439
440static const struct musb_platform_ops am35x_ops = {
441 .quirks = MUSB_DMA_INVENTRA | MUSB_INDEXED_EP,
442 .init = am35x_musb_init,
443 .exit = am35x_musb_exit,
444
445 .read_fifo = am35x_read_fifo,
446#ifdef CONFIG_USB_INVENTRA_DMA
447 .dma_init = musbhs_dma_controller_create,
448 .dma_exit = musbhs_dma_controller_destroy,
449#endif
450 .enable = am35x_musb_enable,
451 .disable = am35x_musb_disable,
452
453 .set_mode = am35x_musb_set_mode,
454 .try_idle = am35x_musb_try_idle,
455
456 .set_vbus = am35x_musb_set_vbus,
457};
458
459static const struct platform_device_info am35x_dev_info = {
460 .name = "musb-hdrc",
461 .id = PLATFORM_DEVID_AUTO,
462 .dma_mask = DMA_BIT_MASK(32),
463};
464
465static int am35x_probe(struct platform_device *pdev)
466{
467 struct musb_hdrc_platform_data *pdata = dev_get_platdata(&pdev->dev);
468 struct platform_device *musb;
469 struct am35x_glue *glue;
470 struct platform_device_info pinfo;
471 struct clk *phy_clk;
472 struct clk *clk;
473
474 int ret = -ENOMEM;
475
476 glue = kzalloc(sizeof(*glue), GFP_KERNEL);
477 if (!glue) {
478 dev_err(&pdev->dev, "failed to allocate glue context\n");
479 goto err0;
480 }
481
482 phy_clk = clk_get(&pdev->dev, "fck");
483 if (IS_ERR(phy_clk)) {
484 dev_err(&pdev->dev, "failed to get PHY clock\n");
485 ret = PTR_ERR(phy_clk);
486 goto err3;
487 }
488
489 clk = clk_get(&pdev->dev, "ick");
490 if (IS_ERR(clk)) {
491 dev_err(&pdev->dev, "failed to get clock\n");
492 ret = PTR_ERR(clk);
493 goto err4;
494 }
495
496 ret = clk_enable(phy_clk);
497 if (ret) {
498 dev_err(&pdev->dev, "failed to enable PHY clock\n");
499 goto err5;
500 }
501
502 ret = clk_enable(clk);
503 if (ret) {
504 dev_err(&pdev->dev, "failed to enable clock\n");
505 goto err6;
506 }
507
508 glue->dev = &pdev->dev;
509 glue->phy_clk = phy_clk;
510 glue->clk = clk;
511
512 pdata->platform_ops = &am35x_ops;
513
514 glue->phy = usb_phy_generic_register();
515 if (IS_ERR(glue->phy))
516 goto err7;
517 platform_set_drvdata(pdev, glue);
518
519 pinfo = am35x_dev_info;
520 pinfo.parent = &pdev->dev;
521 pinfo.res = pdev->resource;
522 pinfo.num_res = pdev->num_resources;
523 pinfo.data = pdata;
524 pinfo.size_data = sizeof(*pdata);
525
526 glue->musb = musb = platform_device_register_full(&pinfo);
527 if (IS_ERR(musb)) {
528 ret = PTR_ERR(musb);
529 dev_err(&pdev->dev, "failed to register musb device: %d\n", ret);
530 goto err8;
531 }
532
533 return 0;
534
535err8:
536 usb_phy_generic_unregister(glue->phy);
537
538err7:
539 clk_disable(clk);
540
541err6:
542 clk_disable(phy_clk);
543
544err5:
545 clk_put(clk);
546
547err4:
548 clk_put(phy_clk);
549
550err3:
551 kfree(glue);
552
553err0:
554 return ret;
555}
556
557static int am35x_remove(struct platform_device *pdev)
558{
559 struct am35x_glue *glue = platform_get_drvdata(pdev);
560
561 platform_device_unregister(glue->musb);
562 usb_phy_generic_unregister(glue->phy);
563 clk_disable(glue->clk);
564 clk_disable(glue->phy_clk);
565 clk_put(glue->clk);
566 clk_put(glue->phy_clk);
567 kfree(glue);
568
569 return 0;
570}
571
572#ifdef CONFIG_PM_SLEEP
573static int am35x_suspend(struct device *dev)
574{
575 struct am35x_glue *glue = dev_get_drvdata(dev);
576 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
577 struct omap_musb_board_data *data = plat->board_data;
578
579 /* Shutdown the on-chip PHY and its PLL. */
580 if (data->set_phy_power)
581 data->set_phy_power(0);
582
583 clk_disable(glue->phy_clk);
584 clk_disable(glue->clk);
585
586 return 0;
587}
588
589static int am35x_resume(struct device *dev)
590{
591 struct am35x_glue *glue = dev_get_drvdata(dev);
592 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
593 struct omap_musb_board_data *data = plat->board_data;
594 int ret;
595
596 /* Start the on-chip PHY and its PLL. */
597 if (data->set_phy_power)
598 data->set_phy_power(1);
599
600 ret = clk_enable(glue->phy_clk);
601 if (ret) {
602 dev_err(dev, "failed to enable PHY clock\n");
603 return ret;
604 }
605
606 ret = clk_enable(glue->clk);
607 if (ret) {
608 dev_err(dev, "failed to enable clock\n");
609 return ret;
610 }
611
612 return 0;
613}
614#endif
615
616static SIMPLE_DEV_PM_OPS(am35x_pm_ops, am35x_suspend, am35x_resume);
617
618static struct platform_driver am35x_driver = {
619 .probe = am35x_probe,
620 .remove = am35x_remove,
621 .driver = {
622 .name = "musb-am35x",
623 .pm = &am35x_pm_ops,
624 },
625};
626
627MODULE_DESCRIPTION("AM35x MUSB Glue Layer");
628MODULE_AUTHOR("Ajay Kumar Gupta <ajay.gupta@ti.com>");
629MODULE_LICENSE("GPL v2");
630module_platform_driver(am35x_driver);
1/*
2 * Texas Instruments AM35x "glue layer"
3 *
4 * Copyright (c) 2010, by Texas Instruments
5 *
6 * Based on the DA8xx "glue layer" code.
7 * Copyright (c) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
8 *
9 * This file is part of the Inventra Controller Driver for Linux.
10 *
11 * The Inventra Controller Driver for Linux is free software; you
12 * can redistribute it and/or modify it under the terms of the GNU
13 * General Public License version 2 as published by the Free Software
14 * Foundation.
15 *
16 * The Inventra Controller Driver for Linux is distributed in
17 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
18 * without even the implied warranty of MERCHANTABILITY or
19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
20 * License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with The Inventra Controller Driver for Linux ; if not,
24 * write to the Free Software Foundation, Inc., 59 Temple Place,
25 * Suite 330, Boston, MA 02111-1307 USA
26 *
27 */
28
29#include <linux/init.h>
30#include <linux/module.h>
31#include <linux/clk.h>
32#include <linux/io.h>
33#include <linux/platform_device.h>
34#include <linux/dma-mapping.h>
35
36#include <plat/usb.h>
37
38#include "musb_core.h"
39
40/*
41 * AM35x specific definitions
42 */
43/* USB 2.0 OTG module registers */
44#define USB_REVISION_REG 0x00
45#define USB_CTRL_REG 0x04
46#define USB_STAT_REG 0x08
47#define USB_EMULATION_REG 0x0c
48/* 0x10 Reserved */
49#define USB_AUTOREQ_REG 0x14
50#define USB_SRP_FIX_TIME_REG 0x18
51#define USB_TEARDOWN_REG 0x1c
52#define EP_INTR_SRC_REG 0x20
53#define EP_INTR_SRC_SET_REG 0x24
54#define EP_INTR_SRC_CLEAR_REG 0x28
55#define EP_INTR_MASK_REG 0x2c
56#define EP_INTR_MASK_SET_REG 0x30
57#define EP_INTR_MASK_CLEAR_REG 0x34
58#define EP_INTR_SRC_MASKED_REG 0x38
59#define CORE_INTR_SRC_REG 0x40
60#define CORE_INTR_SRC_SET_REG 0x44
61#define CORE_INTR_SRC_CLEAR_REG 0x48
62#define CORE_INTR_MASK_REG 0x4c
63#define CORE_INTR_MASK_SET_REG 0x50
64#define CORE_INTR_MASK_CLEAR_REG 0x54
65#define CORE_INTR_SRC_MASKED_REG 0x58
66/* 0x5c Reserved */
67#define USB_END_OF_INTR_REG 0x60
68
69/* Control register bits */
70#define AM35X_SOFT_RESET_MASK 1
71
72/* USB interrupt register bits */
73#define AM35X_INTR_USB_SHIFT 16
74#define AM35X_INTR_USB_MASK (0x1ff << AM35X_INTR_USB_SHIFT)
75#define AM35X_INTR_DRVVBUS 0x100
76#define AM35X_INTR_RX_SHIFT 16
77#define AM35X_INTR_TX_SHIFT 0
78#define AM35X_TX_EP_MASK 0xffff /* EP0 + 15 Tx EPs */
79#define AM35X_RX_EP_MASK 0xfffe /* 15 Rx EPs */
80#define AM35X_TX_INTR_MASK (AM35X_TX_EP_MASK << AM35X_INTR_TX_SHIFT)
81#define AM35X_RX_INTR_MASK (AM35X_RX_EP_MASK << AM35X_INTR_RX_SHIFT)
82
83#define USB_MENTOR_CORE_OFFSET 0x400
84
85struct am35x_glue {
86 struct device *dev;
87 struct platform_device *musb;
88 struct clk *phy_clk;
89 struct clk *clk;
90};
91#define glue_to_musb(g) platform_get_drvdata(g->musb)
92
93/*
94 * am35x_musb_enable - enable interrupts
95 */
96static void am35x_musb_enable(struct musb *musb)
97{
98 void __iomem *reg_base = musb->ctrl_base;
99 u32 epmask;
100
101 /* Workaround: setup IRQs through both register sets. */
102 epmask = ((musb->epmask & AM35X_TX_EP_MASK) << AM35X_INTR_TX_SHIFT) |
103 ((musb->epmask & AM35X_RX_EP_MASK) << AM35X_INTR_RX_SHIFT);
104
105 musb_writel(reg_base, EP_INTR_MASK_SET_REG, epmask);
106 musb_writel(reg_base, CORE_INTR_MASK_SET_REG, AM35X_INTR_USB_MASK);
107
108 /* Force the DRVVBUS IRQ so we can start polling for ID change. */
109 if (is_otg_enabled(musb))
110 musb_writel(reg_base, CORE_INTR_SRC_SET_REG,
111 AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT);
112}
113
114/*
115 * am35x_musb_disable - disable HDRC and flush interrupts
116 */
117static void am35x_musb_disable(struct musb *musb)
118{
119 void __iomem *reg_base = musb->ctrl_base;
120
121 musb_writel(reg_base, CORE_INTR_MASK_CLEAR_REG, AM35X_INTR_USB_MASK);
122 musb_writel(reg_base, EP_INTR_MASK_CLEAR_REG,
123 AM35X_TX_INTR_MASK | AM35X_RX_INTR_MASK);
124 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
125 musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
126}
127
128#define portstate(stmt) stmt
129
130static void am35x_musb_set_vbus(struct musb *musb, int is_on)
131{
132 WARN_ON(is_on && is_peripheral_active(musb));
133}
134
135#define POLL_SECONDS 2
136
137static struct timer_list otg_workaround;
138
139static void otg_timer(unsigned long _musb)
140{
141 struct musb *musb = (void *)_musb;
142 void __iomem *mregs = musb->mregs;
143 u8 devctl;
144 unsigned long flags;
145
146 /*
147 * We poll because AM35x's won't expose several OTG-critical
148 * status change events (from the transceiver) otherwise.
149 */
150 devctl = musb_readb(mregs, MUSB_DEVCTL);
151 dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
152 otg_state_string(musb->xceiv->state));
153
154 spin_lock_irqsave(&musb->lock, flags);
155 switch (musb->xceiv->state) {
156 case OTG_STATE_A_WAIT_BCON:
157 devctl &= ~MUSB_DEVCTL_SESSION;
158 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
159
160 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
161 if (devctl & MUSB_DEVCTL_BDEVICE) {
162 musb->xceiv->state = OTG_STATE_B_IDLE;
163 MUSB_DEV_MODE(musb);
164 } else {
165 musb->xceiv->state = OTG_STATE_A_IDLE;
166 MUSB_HST_MODE(musb);
167 }
168 break;
169 case OTG_STATE_A_WAIT_VFALL:
170 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
171 musb_writel(musb->ctrl_base, CORE_INTR_SRC_SET_REG,
172 MUSB_INTR_VBUSERROR << AM35X_INTR_USB_SHIFT);
173 break;
174 case OTG_STATE_B_IDLE:
175 if (!is_peripheral_enabled(musb))
176 break;
177
178 devctl = musb_readb(mregs, MUSB_DEVCTL);
179 if (devctl & MUSB_DEVCTL_BDEVICE)
180 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
181 else
182 musb->xceiv->state = OTG_STATE_A_IDLE;
183 break;
184 default:
185 break;
186 }
187 spin_unlock_irqrestore(&musb->lock, flags);
188}
189
190static void am35x_musb_try_idle(struct musb *musb, unsigned long timeout)
191{
192 static unsigned long last_timer;
193
194 if (!is_otg_enabled(musb))
195 return;
196
197 if (timeout == 0)
198 timeout = jiffies + msecs_to_jiffies(3);
199
200 /* Never idle if active, or when VBUS timeout is not set as host */
201 if (musb->is_active || (musb->a_wait_bcon == 0 &&
202 musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
203 dev_dbg(musb->controller, "%s active, deleting timer\n",
204 otg_state_string(musb->xceiv->state));
205 del_timer(&otg_workaround);
206 last_timer = jiffies;
207 return;
208 }
209
210 if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
211 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n");
212 return;
213 }
214 last_timer = timeout;
215
216 dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
217 otg_state_string(musb->xceiv->state),
218 jiffies_to_msecs(timeout - jiffies));
219 mod_timer(&otg_workaround, timeout);
220}
221
222static irqreturn_t am35x_musb_interrupt(int irq, void *hci)
223{
224 struct musb *musb = hci;
225 void __iomem *reg_base = musb->ctrl_base;
226 struct device *dev = musb->controller;
227 struct musb_hdrc_platform_data *plat = dev->platform_data;
228 struct omap_musb_board_data *data = plat->board_data;
229 struct usb_otg *otg = musb->xceiv->otg;
230 unsigned long flags;
231 irqreturn_t ret = IRQ_NONE;
232 u32 epintr, usbintr;
233
234 spin_lock_irqsave(&musb->lock, flags);
235
236 /* Get endpoint interrupts */
237 epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_REG);
238
239 if (epintr) {
240 musb_writel(reg_base, EP_INTR_SRC_CLEAR_REG, epintr);
241
242 musb->int_rx =
243 (epintr & AM35X_RX_INTR_MASK) >> AM35X_INTR_RX_SHIFT;
244 musb->int_tx =
245 (epintr & AM35X_TX_INTR_MASK) >> AM35X_INTR_TX_SHIFT;
246 }
247
248 /* Get usb core interrupts */
249 usbintr = musb_readl(reg_base, CORE_INTR_SRC_MASKED_REG);
250 if (!usbintr && !epintr)
251 goto eoi;
252
253 if (usbintr) {
254 musb_writel(reg_base, CORE_INTR_SRC_CLEAR_REG, usbintr);
255
256 musb->int_usb =
257 (usbintr & AM35X_INTR_USB_MASK) >> AM35X_INTR_USB_SHIFT;
258 }
259 /*
260 * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
261 * AM35x's missing ID change IRQ. We need an ID change IRQ to
262 * switch appropriately between halves of the OTG state machine.
263 * Managing DEVCTL.SESSION per Mentor docs requires that we know its
264 * value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
265 * Also, DRVVBUS pulses for SRP (but not at 5V) ...
266 */
267 if (usbintr & (AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT)) {
268 int drvvbus = musb_readl(reg_base, USB_STAT_REG);
269 void __iomem *mregs = musb->mregs;
270 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
271 int err;
272
273 err = is_host_enabled(musb) && (musb->int_usb &
274 MUSB_INTR_VBUSERROR);
275 if (err) {
276 /*
277 * The Mentor core doesn't debounce VBUS as needed
278 * to cope with device connect current spikes. This
279 * means it's not uncommon for bus-powered devices
280 * to get VBUS errors during enumeration.
281 *
282 * This is a workaround, but newer RTL from Mentor
283 * seems to allow a better one: "re"-starting sessions
284 * without waiting for VBUS to stop registering in
285 * devctl.
286 */
287 musb->int_usb &= ~MUSB_INTR_VBUSERROR;
288 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
289 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
290 WARNING("VBUS error workaround (delay coming)\n");
291 } else if (is_host_enabled(musb) && drvvbus) {
292 MUSB_HST_MODE(musb);
293 otg->default_a = 1;
294 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
295 portstate(musb->port1_status |= USB_PORT_STAT_POWER);
296 del_timer(&otg_workaround);
297 } else {
298 musb->is_active = 0;
299 MUSB_DEV_MODE(musb);
300 otg->default_a = 0;
301 musb->xceiv->state = OTG_STATE_B_IDLE;
302 portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
303 }
304
305 /* NOTE: this must complete power-on within 100 ms. */
306 dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
307 drvvbus ? "on" : "off",
308 otg_state_string(musb->xceiv->state),
309 err ? " ERROR" : "",
310 devctl);
311 ret = IRQ_HANDLED;
312 }
313
314 if (musb->int_tx || musb->int_rx || musb->int_usb)
315 ret |= musb_interrupt(musb);
316
317eoi:
318 /* EOI needs to be written for the IRQ to be re-asserted. */
319 if (ret == IRQ_HANDLED || epintr || usbintr) {
320 /* clear level interrupt */
321 if (data->clear_irq)
322 data->clear_irq();
323 /* write EOI */
324 musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
325 }
326
327 /* Poll for ID change */
328 if (is_otg_enabled(musb) && musb->xceiv->state == OTG_STATE_B_IDLE)
329 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
330
331 spin_unlock_irqrestore(&musb->lock, flags);
332
333 return ret;
334}
335
336static int am35x_musb_set_mode(struct musb *musb, u8 musb_mode)
337{
338 struct device *dev = musb->controller;
339 struct musb_hdrc_platform_data *plat = dev->platform_data;
340 struct omap_musb_board_data *data = plat->board_data;
341 int retval = 0;
342
343 if (data->set_mode)
344 data->set_mode(musb_mode);
345 else
346 retval = -EIO;
347
348 return retval;
349}
350
351static int am35x_musb_init(struct musb *musb)
352{
353 struct device *dev = musb->controller;
354 struct musb_hdrc_platform_data *plat = dev->platform_data;
355 struct omap_musb_board_data *data = plat->board_data;
356 void __iomem *reg_base = musb->ctrl_base;
357 u32 rev;
358
359 musb->mregs += USB_MENTOR_CORE_OFFSET;
360
361 /* Returns zero if e.g. not clocked */
362 rev = musb_readl(reg_base, USB_REVISION_REG);
363 if (!rev)
364 return -ENODEV;
365
366 usb_nop_xceiv_register();
367 musb->xceiv = usb_get_transceiver();
368 if (!musb->xceiv)
369 return -ENODEV;
370
371 if (is_host_enabled(musb))
372 setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
373
374 /* Reset the musb */
375 if (data->reset)
376 data->reset();
377
378 /* Reset the controller */
379 musb_writel(reg_base, USB_CTRL_REG, AM35X_SOFT_RESET_MASK);
380
381 /* Start the on-chip PHY and its PLL. */
382 if (data->set_phy_power)
383 data->set_phy_power(1);
384
385 msleep(5);
386
387 musb->isr = am35x_musb_interrupt;
388
389 /* clear level interrupt */
390 if (data->clear_irq)
391 data->clear_irq();
392
393 return 0;
394}
395
396static int am35x_musb_exit(struct musb *musb)
397{
398 struct device *dev = musb->controller;
399 struct musb_hdrc_platform_data *plat = dev->platform_data;
400 struct omap_musb_board_data *data = plat->board_data;
401
402 if (is_host_enabled(musb))
403 del_timer_sync(&otg_workaround);
404
405 /* Shutdown the on-chip PHY and its PLL. */
406 if (data->set_phy_power)
407 data->set_phy_power(0);
408
409 usb_put_transceiver(musb->xceiv);
410 usb_nop_xceiv_unregister();
411
412 return 0;
413}
414
415/* AM35x supports only 32bit read operation */
416void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
417{
418 void __iomem *fifo = hw_ep->fifo;
419 u32 val;
420 int i;
421
422 /* Read for 32bit-aligned destination address */
423 if (likely((0x03 & (unsigned long) dst) == 0) && len >= 4) {
424 readsl(fifo, dst, len >> 2);
425 dst += len & ~0x03;
426 len &= 0x03;
427 }
428 /*
429 * Now read the remaining 1 to 3 byte or complete length if
430 * unaligned address.
431 */
432 if (len > 4) {
433 for (i = 0; i < (len >> 2); i++) {
434 *(u32 *) dst = musb_readl(fifo, 0);
435 dst += 4;
436 }
437 len &= 0x03;
438 }
439 if (len > 0) {
440 val = musb_readl(fifo, 0);
441 memcpy(dst, &val, len);
442 }
443}
444
445static const struct musb_platform_ops am35x_ops = {
446 .init = am35x_musb_init,
447 .exit = am35x_musb_exit,
448
449 .enable = am35x_musb_enable,
450 .disable = am35x_musb_disable,
451
452 .set_mode = am35x_musb_set_mode,
453 .try_idle = am35x_musb_try_idle,
454
455 .set_vbus = am35x_musb_set_vbus,
456};
457
458static u64 am35x_dmamask = DMA_BIT_MASK(32);
459
460static int __devinit am35x_probe(struct platform_device *pdev)
461{
462 struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data;
463 struct platform_device *musb;
464 struct am35x_glue *glue;
465
466 struct clk *phy_clk;
467 struct clk *clk;
468
469 int ret = -ENOMEM;
470
471 glue = kzalloc(sizeof(*glue), GFP_KERNEL);
472 if (!glue) {
473 dev_err(&pdev->dev, "failed to allocate glue context\n");
474 goto err0;
475 }
476
477 musb = platform_device_alloc("musb-hdrc", -1);
478 if (!musb) {
479 dev_err(&pdev->dev, "failed to allocate musb device\n");
480 goto err1;
481 }
482
483 phy_clk = clk_get(&pdev->dev, "fck");
484 if (IS_ERR(phy_clk)) {
485 dev_err(&pdev->dev, "failed to get PHY clock\n");
486 ret = PTR_ERR(phy_clk);
487 goto err2;
488 }
489
490 clk = clk_get(&pdev->dev, "ick");
491 if (IS_ERR(clk)) {
492 dev_err(&pdev->dev, "failed to get clock\n");
493 ret = PTR_ERR(clk);
494 goto err3;
495 }
496
497 ret = clk_enable(phy_clk);
498 if (ret) {
499 dev_err(&pdev->dev, "failed to enable PHY clock\n");
500 goto err4;
501 }
502
503 ret = clk_enable(clk);
504 if (ret) {
505 dev_err(&pdev->dev, "failed to enable clock\n");
506 goto err5;
507 }
508
509 musb->dev.parent = &pdev->dev;
510 musb->dev.dma_mask = &am35x_dmamask;
511 musb->dev.coherent_dma_mask = am35x_dmamask;
512
513 glue->dev = &pdev->dev;
514 glue->musb = musb;
515 glue->phy_clk = phy_clk;
516 glue->clk = clk;
517
518 pdata->platform_ops = &am35x_ops;
519
520 platform_set_drvdata(pdev, glue);
521
522 ret = platform_device_add_resources(musb, pdev->resource,
523 pdev->num_resources);
524 if (ret) {
525 dev_err(&pdev->dev, "failed to add resources\n");
526 goto err6;
527 }
528
529 ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
530 if (ret) {
531 dev_err(&pdev->dev, "failed to add platform_data\n");
532 goto err6;
533 }
534
535 ret = platform_device_add(musb);
536 if (ret) {
537 dev_err(&pdev->dev, "failed to register musb device\n");
538 goto err6;
539 }
540
541 return 0;
542
543err6:
544 clk_disable(clk);
545
546err5:
547 clk_disable(phy_clk);
548
549err4:
550 clk_put(clk);
551
552err3:
553 clk_put(phy_clk);
554
555err2:
556 platform_device_put(musb);
557
558err1:
559 kfree(glue);
560
561err0:
562 return ret;
563}
564
565static int __devexit am35x_remove(struct platform_device *pdev)
566{
567 struct am35x_glue *glue = platform_get_drvdata(pdev);
568
569 platform_device_del(glue->musb);
570 platform_device_put(glue->musb);
571 clk_disable(glue->clk);
572 clk_disable(glue->phy_clk);
573 clk_put(glue->clk);
574 clk_put(glue->phy_clk);
575 kfree(glue);
576
577 return 0;
578}
579
580#ifdef CONFIG_PM
581static int am35x_suspend(struct device *dev)
582{
583 struct am35x_glue *glue = dev_get_drvdata(dev);
584 struct musb_hdrc_platform_data *plat = dev->platform_data;
585 struct omap_musb_board_data *data = plat->board_data;
586
587 /* Shutdown the on-chip PHY and its PLL. */
588 if (data->set_phy_power)
589 data->set_phy_power(0);
590
591 clk_disable(glue->phy_clk);
592 clk_disable(glue->clk);
593
594 return 0;
595}
596
597static int am35x_resume(struct device *dev)
598{
599 struct am35x_glue *glue = dev_get_drvdata(dev);
600 struct musb_hdrc_platform_data *plat = dev->platform_data;
601 struct omap_musb_board_data *data = plat->board_data;
602 int ret;
603
604 /* Start the on-chip PHY and its PLL. */
605 if (data->set_phy_power)
606 data->set_phy_power(1);
607
608 ret = clk_enable(glue->phy_clk);
609 if (ret) {
610 dev_err(dev, "failed to enable PHY clock\n");
611 return ret;
612 }
613
614 ret = clk_enable(glue->clk);
615 if (ret) {
616 dev_err(dev, "failed to enable clock\n");
617 return ret;
618 }
619
620 return 0;
621}
622
623static struct dev_pm_ops am35x_pm_ops = {
624 .suspend = am35x_suspend,
625 .resume = am35x_resume,
626};
627
628#define DEV_PM_OPS &am35x_pm_ops
629#else
630#define DEV_PM_OPS NULL
631#endif
632
633static struct platform_driver am35x_driver = {
634 .probe = am35x_probe,
635 .remove = __devexit_p(am35x_remove),
636 .driver = {
637 .name = "musb-am35x",
638 .pm = DEV_PM_OPS,
639 },
640};
641
642MODULE_DESCRIPTION("AM35x MUSB Glue Layer");
643MODULE_AUTHOR("Ajay Kumar Gupta <ajay.gupta@ti.com>");
644MODULE_LICENSE("GPL v2");
645
646static int __init am35x_init(void)
647{
648 return platform_driver_register(&am35x_driver);
649}
650module_init(am35x_init);
651
652static void __exit am35x_exit(void)
653{
654 platform_driver_unregister(&am35x_driver);
655}
656module_exit(am35x_exit);