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1/*
2 * linux/drivers/video/omap2/dss/venc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * VENC settings from TI's DSS driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#define DSS_SUBSYS_NAME "VENC"
23
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/clk.h>
27#include <linux/err.h>
28#include <linux/io.h>
29#include <linux/mutex.h>
30#include <linux/completion.h>
31#include <linux/delay.h>
32#include <linux/string.h>
33#include <linux/seq_file.h>
34#include <linux/platform_device.h>
35#include <linux/regulator/consumer.h>
36#include <linux/pm_runtime.h>
37#include <linux/of.h>
38#include <linux/component.h>
39
40#include <video/omapdss.h>
41
42#include "dss.h"
43#include "dss_features.h"
44
45/* Venc registers */
46#define VENC_REV_ID 0x00
47#define VENC_STATUS 0x04
48#define VENC_F_CONTROL 0x08
49#define VENC_VIDOUT_CTRL 0x10
50#define VENC_SYNC_CTRL 0x14
51#define VENC_LLEN 0x1C
52#define VENC_FLENS 0x20
53#define VENC_HFLTR_CTRL 0x24
54#define VENC_CC_CARR_WSS_CARR 0x28
55#define VENC_C_PHASE 0x2C
56#define VENC_GAIN_U 0x30
57#define VENC_GAIN_V 0x34
58#define VENC_GAIN_Y 0x38
59#define VENC_BLACK_LEVEL 0x3C
60#define VENC_BLANK_LEVEL 0x40
61#define VENC_X_COLOR 0x44
62#define VENC_M_CONTROL 0x48
63#define VENC_BSTAMP_WSS_DATA 0x4C
64#define VENC_S_CARR 0x50
65#define VENC_LINE21 0x54
66#define VENC_LN_SEL 0x58
67#define VENC_L21__WC_CTL 0x5C
68#define VENC_HTRIGGER_VTRIGGER 0x60
69#define VENC_SAVID__EAVID 0x64
70#define VENC_FLEN__FAL 0x68
71#define VENC_LAL__PHASE_RESET 0x6C
72#define VENC_HS_INT_START_STOP_X 0x70
73#define VENC_HS_EXT_START_STOP_X 0x74
74#define VENC_VS_INT_START_X 0x78
75#define VENC_VS_INT_STOP_X__VS_INT_START_Y 0x7C
76#define VENC_VS_INT_STOP_Y__VS_EXT_START_X 0x80
77#define VENC_VS_EXT_STOP_X__VS_EXT_START_Y 0x84
78#define VENC_VS_EXT_STOP_Y 0x88
79#define VENC_AVID_START_STOP_X 0x90
80#define VENC_AVID_START_STOP_Y 0x94
81#define VENC_FID_INT_START_X__FID_INT_START_Y 0xA0
82#define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X 0xA4
83#define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y 0xA8
84#define VENC_TVDETGP_INT_START_STOP_X 0xB0
85#define VENC_TVDETGP_INT_START_STOP_Y 0xB4
86#define VENC_GEN_CTRL 0xB8
87#define VENC_OUTPUT_CONTROL 0xC4
88#define VENC_OUTPUT_TEST 0xC8
89#define VENC_DAC_B__DAC_C 0xC8
90
91struct venc_config {
92 u32 f_control;
93 u32 vidout_ctrl;
94 u32 sync_ctrl;
95 u32 llen;
96 u32 flens;
97 u32 hfltr_ctrl;
98 u32 cc_carr_wss_carr;
99 u32 c_phase;
100 u32 gain_u;
101 u32 gain_v;
102 u32 gain_y;
103 u32 black_level;
104 u32 blank_level;
105 u32 x_color;
106 u32 m_control;
107 u32 bstamp_wss_data;
108 u32 s_carr;
109 u32 line21;
110 u32 ln_sel;
111 u32 l21__wc_ctl;
112 u32 htrigger_vtrigger;
113 u32 savid__eavid;
114 u32 flen__fal;
115 u32 lal__phase_reset;
116 u32 hs_int_start_stop_x;
117 u32 hs_ext_start_stop_x;
118 u32 vs_int_start_x;
119 u32 vs_int_stop_x__vs_int_start_y;
120 u32 vs_int_stop_y__vs_ext_start_x;
121 u32 vs_ext_stop_x__vs_ext_start_y;
122 u32 vs_ext_stop_y;
123 u32 avid_start_stop_x;
124 u32 avid_start_stop_y;
125 u32 fid_int_start_x__fid_int_start_y;
126 u32 fid_int_offset_y__fid_ext_start_x;
127 u32 fid_ext_start_y__fid_ext_offset_y;
128 u32 tvdetgp_int_start_stop_x;
129 u32 tvdetgp_int_start_stop_y;
130 u32 gen_ctrl;
131};
132
133/* from TRM */
134static const struct venc_config venc_config_pal_trm = {
135 .f_control = 0,
136 .vidout_ctrl = 1,
137 .sync_ctrl = 0x40,
138 .llen = 0x35F, /* 863 */
139 .flens = 0x270, /* 624 */
140 .hfltr_ctrl = 0,
141 .cc_carr_wss_carr = 0x2F7225ED,
142 .c_phase = 0,
143 .gain_u = 0x111,
144 .gain_v = 0x181,
145 .gain_y = 0x140,
146 .black_level = 0x3B,
147 .blank_level = 0x3B,
148 .x_color = 0x7,
149 .m_control = 0x2,
150 .bstamp_wss_data = 0x3F,
151 .s_carr = 0x2A098ACB,
152 .line21 = 0,
153 .ln_sel = 0x01290015,
154 .l21__wc_ctl = 0x0000F603,
155 .htrigger_vtrigger = 0,
156
157 .savid__eavid = 0x06A70108,
158 .flen__fal = 0x00180270,
159 .lal__phase_reset = 0x00040135,
160 .hs_int_start_stop_x = 0x00880358,
161 .hs_ext_start_stop_x = 0x000F035F,
162 .vs_int_start_x = 0x01A70000,
163 .vs_int_stop_x__vs_int_start_y = 0x000001A7,
164 .vs_int_stop_y__vs_ext_start_x = 0x01AF0000,
165 .vs_ext_stop_x__vs_ext_start_y = 0x000101AF,
166 .vs_ext_stop_y = 0x00000025,
167 .avid_start_stop_x = 0x03530083,
168 .avid_start_stop_y = 0x026C002E,
169 .fid_int_start_x__fid_int_start_y = 0x0001008A,
170 .fid_int_offset_y__fid_ext_start_x = 0x002E0138,
171 .fid_ext_start_y__fid_ext_offset_y = 0x01380001,
172
173 .tvdetgp_int_start_stop_x = 0x00140001,
174 .tvdetgp_int_start_stop_y = 0x00010001,
175 .gen_ctrl = 0x00FF0000,
176};
177
178/* from TRM */
179static const struct venc_config venc_config_ntsc_trm = {
180 .f_control = 0,
181 .vidout_ctrl = 1,
182 .sync_ctrl = 0x8040,
183 .llen = 0x359,
184 .flens = 0x20C,
185 .hfltr_ctrl = 0,
186 .cc_carr_wss_carr = 0x043F2631,
187 .c_phase = 0,
188 .gain_u = 0x102,
189 .gain_v = 0x16C,
190 .gain_y = 0x12F,
191 .black_level = 0x43,
192 .blank_level = 0x38,
193 .x_color = 0x7,
194 .m_control = 0x1,
195 .bstamp_wss_data = 0x38,
196 .s_carr = 0x21F07C1F,
197 .line21 = 0,
198 .ln_sel = 0x01310011,
199 .l21__wc_ctl = 0x0000F003,
200 .htrigger_vtrigger = 0,
201
202 .savid__eavid = 0x069300F4,
203 .flen__fal = 0x0016020C,
204 .lal__phase_reset = 0x00060107,
205 .hs_int_start_stop_x = 0x008E0350,
206 .hs_ext_start_stop_x = 0x000F0359,
207 .vs_int_start_x = 0x01A00000,
208 .vs_int_stop_x__vs_int_start_y = 0x020701A0,
209 .vs_int_stop_y__vs_ext_start_x = 0x01AC0024,
210 .vs_ext_stop_x__vs_ext_start_y = 0x020D01AC,
211 .vs_ext_stop_y = 0x00000006,
212 .avid_start_stop_x = 0x03480078,
213 .avid_start_stop_y = 0x02060024,
214 .fid_int_start_x__fid_int_start_y = 0x0001008A,
215 .fid_int_offset_y__fid_ext_start_x = 0x01AC0106,
216 .fid_ext_start_y__fid_ext_offset_y = 0x01060006,
217
218 .tvdetgp_int_start_stop_x = 0x00140001,
219 .tvdetgp_int_start_stop_y = 0x00010001,
220 .gen_ctrl = 0x00F90000,
221};
222
223static const struct venc_config venc_config_pal_bdghi = {
224 .f_control = 0,
225 .vidout_ctrl = 0,
226 .sync_ctrl = 0,
227 .hfltr_ctrl = 0,
228 .x_color = 0,
229 .line21 = 0,
230 .ln_sel = 21,
231 .htrigger_vtrigger = 0,
232 .tvdetgp_int_start_stop_x = 0x00140001,
233 .tvdetgp_int_start_stop_y = 0x00010001,
234 .gen_ctrl = 0x00FB0000,
235
236 .llen = 864-1,
237 .flens = 625-1,
238 .cc_carr_wss_carr = 0x2F7625ED,
239 .c_phase = 0xDF,
240 .gain_u = 0x111,
241 .gain_v = 0x181,
242 .gain_y = 0x140,
243 .black_level = 0x3e,
244 .blank_level = 0x3e,
245 .m_control = 0<<2 | 1<<1,
246 .bstamp_wss_data = 0x42,
247 .s_carr = 0x2a098acb,
248 .l21__wc_ctl = 0<<13 | 0x16<<8 | 0<<0,
249 .savid__eavid = 0x06A70108,
250 .flen__fal = 23<<16 | 624<<0,
251 .lal__phase_reset = 2<<17 | 310<<0,
252 .hs_int_start_stop_x = 0x00920358,
253 .hs_ext_start_stop_x = 0x000F035F,
254 .vs_int_start_x = 0x1a7<<16,
255 .vs_int_stop_x__vs_int_start_y = 0x000601A7,
256 .vs_int_stop_y__vs_ext_start_x = 0x01AF0036,
257 .vs_ext_stop_x__vs_ext_start_y = 0x27101af,
258 .vs_ext_stop_y = 0x05,
259 .avid_start_stop_x = 0x03530082,
260 .avid_start_stop_y = 0x0270002E,
261 .fid_int_start_x__fid_int_start_y = 0x0005008A,
262 .fid_int_offset_y__fid_ext_start_x = 0x002E0138,
263 .fid_ext_start_y__fid_ext_offset_y = 0x01380005,
264};
265
266const struct omap_video_timings omap_dss_pal_timings = {
267 .x_res = 720,
268 .y_res = 574,
269 .pixelclock = 13500000,
270 .hsw = 64,
271 .hfp = 12,
272 .hbp = 68,
273 .vsw = 5,
274 .vfp = 5,
275 .vbp = 41,
276
277 .interlace = true,
278
279 .hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
280 .vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
281 .data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
282 .de_level = OMAPDSS_SIG_ACTIVE_HIGH,
283 .sync_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE,
284};
285EXPORT_SYMBOL(omap_dss_pal_timings);
286
287const struct omap_video_timings omap_dss_ntsc_timings = {
288 .x_res = 720,
289 .y_res = 482,
290 .pixelclock = 13500000,
291 .hsw = 64,
292 .hfp = 16,
293 .hbp = 58,
294 .vsw = 6,
295 .vfp = 6,
296 .vbp = 31,
297
298 .interlace = true,
299
300 .hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
301 .vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
302 .data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
303 .de_level = OMAPDSS_SIG_ACTIVE_HIGH,
304 .sync_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE,
305};
306EXPORT_SYMBOL(omap_dss_ntsc_timings);
307
308static struct {
309 struct platform_device *pdev;
310 void __iomem *base;
311 struct mutex venc_lock;
312 u32 wss_data;
313 struct regulator *vdda_dac_reg;
314
315 struct clk *tv_dac_clk;
316
317 struct omap_video_timings timings;
318 enum omap_dss_venc_type type;
319 bool invert_polarity;
320
321 struct omap_dss_device output;
322} venc;
323
324static inline void venc_write_reg(int idx, u32 val)
325{
326 __raw_writel(val, venc.base + idx);
327}
328
329static inline u32 venc_read_reg(int idx)
330{
331 u32 l = __raw_readl(venc.base + idx);
332 return l;
333}
334
335static void venc_write_config(const struct venc_config *config)
336{
337 DSSDBG("write venc conf\n");
338
339 venc_write_reg(VENC_LLEN, config->llen);
340 venc_write_reg(VENC_FLENS, config->flens);
341 venc_write_reg(VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr);
342 venc_write_reg(VENC_C_PHASE, config->c_phase);
343 venc_write_reg(VENC_GAIN_U, config->gain_u);
344 venc_write_reg(VENC_GAIN_V, config->gain_v);
345 venc_write_reg(VENC_GAIN_Y, config->gain_y);
346 venc_write_reg(VENC_BLACK_LEVEL, config->black_level);
347 venc_write_reg(VENC_BLANK_LEVEL, config->blank_level);
348 venc_write_reg(VENC_M_CONTROL, config->m_control);
349 venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data |
350 venc.wss_data);
351 venc_write_reg(VENC_S_CARR, config->s_carr);
352 venc_write_reg(VENC_L21__WC_CTL, config->l21__wc_ctl);
353 venc_write_reg(VENC_SAVID__EAVID, config->savid__eavid);
354 venc_write_reg(VENC_FLEN__FAL, config->flen__fal);
355 venc_write_reg(VENC_LAL__PHASE_RESET, config->lal__phase_reset);
356 venc_write_reg(VENC_HS_INT_START_STOP_X, config->hs_int_start_stop_x);
357 venc_write_reg(VENC_HS_EXT_START_STOP_X, config->hs_ext_start_stop_x);
358 venc_write_reg(VENC_VS_INT_START_X, config->vs_int_start_x);
359 venc_write_reg(VENC_VS_INT_STOP_X__VS_INT_START_Y,
360 config->vs_int_stop_x__vs_int_start_y);
361 venc_write_reg(VENC_VS_INT_STOP_Y__VS_EXT_START_X,
362 config->vs_int_stop_y__vs_ext_start_x);
363 venc_write_reg(VENC_VS_EXT_STOP_X__VS_EXT_START_Y,
364 config->vs_ext_stop_x__vs_ext_start_y);
365 venc_write_reg(VENC_VS_EXT_STOP_Y, config->vs_ext_stop_y);
366 venc_write_reg(VENC_AVID_START_STOP_X, config->avid_start_stop_x);
367 venc_write_reg(VENC_AVID_START_STOP_Y, config->avid_start_stop_y);
368 venc_write_reg(VENC_FID_INT_START_X__FID_INT_START_Y,
369 config->fid_int_start_x__fid_int_start_y);
370 venc_write_reg(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X,
371 config->fid_int_offset_y__fid_ext_start_x);
372 venc_write_reg(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y,
373 config->fid_ext_start_y__fid_ext_offset_y);
374
375 venc_write_reg(VENC_DAC_B__DAC_C, venc_read_reg(VENC_DAC_B__DAC_C));
376 venc_write_reg(VENC_VIDOUT_CTRL, config->vidout_ctrl);
377 venc_write_reg(VENC_HFLTR_CTRL, config->hfltr_ctrl);
378 venc_write_reg(VENC_X_COLOR, config->x_color);
379 venc_write_reg(VENC_LINE21, config->line21);
380 venc_write_reg(VENC_LN_SEL, config->ln_sel);
381 venc_write_reg(VENC_HTRIGGER_VTRIGGER, config->htrigger_vtrigger);
382 venc_write_reg(VENC_TVDETGP_INT_START_STOP_X,
383 config->tvdetgp_int_start_stop_x);
384 venc_write_reg(VENC_TVDETGP_INT_START_STOP_Y,
385 config->tvdetgp_int_start_stop_y);
386 venc_write_reg(VENC_GEN_CTRL, config->gen_ctrl);
387 venc_write_reg(VENC_F_CONTROL, config->f_control);
388 venc_write_reg(VENC_SYNC_CTRL, config->sync_ctrl);
389}
390
391static void venc_reset(void)
392{
393 int t = 1000;
394
395 venc_write_reg(VENC_F_CONTROL, 1<<8);
396 while (venc_read_reg(VENC_F_CONTROL) & (1<<8)) {
397 if (--t == 0) {
398 DSSERR("Failed to reset venc\n");
399 return;
400 }
401 }
402
403#ifdef CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET
404 /* the magical sleep that makes things work */
405 /* XXX more info? What bug this circumvents? */
406 msleep(20);
407#endif
408}
409
410static int venc_runtime_get(void)
411{
412 int r;
413
414 DSSDBG("venc_runtime_get\n");
415
416 r = pm_runtime_get_sync(&venc.pdev->dev);
417 WARN_ON(r < 0);
418 return r < 0 ? r : 0;
419}
420
421static void venc_runtime_put(void)
422{
423 int r;
424
425 DSSDBG("venc_runtime_put\n");
426
427 r = pm_runtime_put_sync(&venc.pdev->dev);
428 WARN_ON(r < 0 && r != -ENOSYS);
429}
430
431static const struct venc_config *venc_timings_to_config(
432 struct omap_video_timings *timings)
433{
434 if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0)
435 return &venc_config_pal_trm;
436
437 if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0)
438 return &venc_config_ntsc_trm;
439
440 BUG();
441 return NULL;
442}
443
444static int venc_power_on(struct omap_dss_device *dssdev)
445{
446 enum omap_channel channel = dssdev->dispc_channel;
447 u32 l;
448 int r;
449
450 r = venc_runtime_get();
451 if (r)
452 goto err0;
453
454 venc_reset();
455 venc_write_config(venc_timings_to_config(&venc.timings));
456
457 dss_set_venc_output(venc.type);
458 dss_set_dac_pwrdn_bgz(1);
459
460 l = 0;
461
462 if (venc.type == OMAP_DSS_VENC_TYPE_COMPOSITE)
463 l |= 1 << 1;
464 else /* S-Video */
465 l |= (1 << 0) | (1 << 2);
466
467 if (venc.invert_polarity == false)
468 l |= 1 << 3;
469
470 venc_write_reg(VENC_OUTPUT_CONTROL, l);
471
472 dss_mgr_set_timings(channel, &venc.timings);
473
474 r = regulator_enable(venc.vdda_dac_reg);
475 if (r)
476 goto err1;
477
478 r = dss_mgr_enable(channel);
479 if (r)
480 goto err2;
481
482 return 0;
483
484err2:
485 regulator_disable(venc.vdda_dac_reg);
486err1:
487 venc_write_reg(VENC_OUTPUT_CONTROL, 0);
488 dss_set_dac_pwrdn_bgz(0);
489
490 venc_runtime_put();
491err0:
492 return r;
493}
494
495static void venc_power_off(struct omap_dss_device *dssdev)
496{
497 enum omap_channel channel = dssdev->dispc_channel;
498
499 venc_write_reg(VENC_OUTPUT_CONTROL, 0);
500 dss_set_dac_pwrdn_bgz(0);
501
502 dss_mgr_disable(channel);
503
504 regulator_disable(venc.vdda_dac_reg);
505
506 venc_runtime_put();
507}
508
509static int venc_display_enable(struct omap_dss_device *dssdev)
510{
511 struct omap_dss_device *out = &venc.output;
512 int r;
513
514 DSSDBG("venc_display_enable\n");
515
516 mutex_lock(&venc.venc_lock);
517
518 if (!out->dispc_channel_connected) {
519 DSSERR("Failed to enable display: no output/manager\n");
520 r = -ENODEV;
521 goto err0;
522 }
523
524 r = venc_power_on(dssdev);
525 if (r)
526 goto err0;
527
528 venc.wss_data = 0;
529
530 mutex_unlock(&venc.venc_lock);
531
532 return 0;
533err0:
534 mutex_unlock(&venc.venc_lock);
535 return r;
536}
537
538static void venc_display_disable(struct omap_dss_device *dssdev)
539{
540 DSSDBG("venc_display_disable\n");
541
542 mutex_lock(&venc.venc_lock);
543
544 venc_power_off(dssdev);
545
546 mutex_unlock(&venc.venc_lock);
547}
548
549static void venc_set_timings(struct omap_dss_device *dssdev,
550 struct omap_video_timings *timings)
551{
552 DSSDBG("venc_set_timings\n");
553
554 mutex_lock(&venc.venc_lock);
555
556 /* Reset WSS data when the TV standard changes. */
557 if (memcmp(&venc.timings, timings, sizeof(*timings)))
558 venc.wss_data = 0;
559
560 venc.timings = *timings;
561
562 dispc_set_tv_pclk(13500000);
563
564 mutex_unlock(&venc.venc_lock);
565}
566
567static int venc_check_timings(struct omap_dss_device *dssdev,
568 struct omap_video_timings *timings)
569{
570 DSSDBG("venc_check_timings\n");
571
572 if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0)
573 return 0;
574
575 if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0)
576 return 0;
577
578 return -EINVAL;
579}
580
581static void venc_get_timings(struct omap_dss_device *dssdev,
582 struct omap_video_timings *timings)
583{
584 mutex_lock(&venc.venc_lock);
585
586 *timings = venc.timings;
587
588 mutex_unlock(&venc.venc_lock);
589}
590
591static u32 venc_get_wss(struct omap_dss_device *dssdev)
592{
593 /* Invert due to VENC_L21_WC_CTL:INV=1 */
594 return (venc.wss_data >> 8) ^ 0xfffff;
595}
596
597static int venc_set_wss(struct omap_dss_device *dssdev, u32 wss)
598{
599 const struct venc_config *config;
600 int r;
601
602 DSSDBG("venc_set_wss\n");
603
604 mutex_lock(&venc.venc_lock);
605
606 config = venc_timings_to_config(&venc.timings);
607
608 /* Invert due to VENC_L21_WC_CTL:INV=1 */
609 venc.wss_data = (wss ^ 0xfffff) << 8;
610
611 r = venc_runtime_get();
612 if (r)
613 goto err;
614
615 venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data |
616 venc.wss_data);
617
618 venc_runtime_put();
619
620err:
621 mutex_unlock(&venc.venc_lock);
622
623 return r;
624}
625
626static void venc_set_type(struct omap_dss_device *dssdev,
627 enum omap_dss_venc_type type)
628{
629 mutex_lock(&venc.venc_lock);
630
631 venc.type = type;
632
633 mutex_unlock(&venc.venc_lock);
634}
635
636static void venc_invert_vid_out_polarity(struct omap_dss_device *dssdev,
637 bool invert_polarity)
638{
639 mutex_lock(&venc.venc_lock);
640
641 venc.invert_polarity = invert_polarity;
642
643 mutex_unlock(&venc.venc_lock);
644}
645
646static int venc_init_regulator(void)
647{
648 struct regulator *vdda_dac;
649
650 if (venc.vdda_dac_reg != NULL)
651 return 0;
652
653 if (venc.pdev->dev.of_node)
654 vdda_dac = devm_regulator_get(&venc.pdev->dev, "vdda");
655 else
656 vdda_dac = devm_regulator_get(&venc.pdev->dev, "vdda_dac");
657
658 if (IS_ERR(vdda_dac)) {
659 if (PTR_ERR(vdda_dac) != -EPROBE_DEFER)
660 DSSERR("can't get VDDA_DAC regulator\n");
661 return PTR_ERR(vdda_dac);
662 }
663
664 venc.vdda_dac_reg = vdda_dac;
665
666 return 0;
667}
668
669static void venc_dump_regs(struct seq_file *s)
670{
671#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, venc_read_reg(r))
672
673 if (venc_runtime_get())
674 return;
675
676 DUMPREG(VENC_F_CONTROL);
677 DUMPREG(VENC_VIDOUT_CTRL);
678 DUMPREG(VENC_SYNC_CTRL);
679 DUMPREG(VENC_LLEN);
680 DUMPREG(VENC_FLENS);
681 DUMPREG(VENC_HFLTR_CTRL);
682 DUMPREG(VENC_CC_CARR_WSS_CARR);
683 DUMPREG(VENC_C_PHASE);
684 DUMPREG(VENC_GAIN_U);
685 DUMPREG(VENC_GAIN_V);
686 DUMPREG(VENC_GAIN_Y);
687 DUMPREG(VENC_BLACK_LEVEL);
688 DUMPREG(VENC_BLANK_LEVEL);
689 DUMPREG(VENC_X_COLOR);
690 DUMPREG(VENC_M_CONTROL);
691 DUMPREG(VENC_BSTAMP_WSS_DATA);
692 DUMPREG(VENC_S_CARR);
693 DUMPREG(VENC_LINE21);
694 DUMPREG(VENC_LN_SEL);
695 DUMPREG(VENC_L21__WC_CTL);
696 DUMPREG(VENC_HTRIGGER_VTRIGGER);
697 DUMPREG(VENC_SAVID__EAVID);
698 DUMPREG(VENC_FLEN__FAL);
699 DUMPREG(VENC_LAL__PHASE_RESET);
700 DUMPREG(VENC_HS_INT_START_STOP_X);
701 DUMPREG(VENC_HS_EXT_START_STOP_X);
702 DUMPREG(VENC_VS_INT_START_X);
703 DUMPREG(VENC_VS_INT_STOP_X__VS_INT_START_Y);
704 DUMPREG(VENC_VS_INT_STOP_Y__VS_EXT_START_X);
705 DUMPREG(VENC_VS_EXT_STOP_X__VS_EXT_START_Y);
706 DUMPREG(VENC_VS_EXT_STOP_Y);
707 DUMPREG(VENC_AVID_START_STOP_X);
708 DUMPREG(VENC_AVID_START_STOP_Y);
709 DUMPREG(VENC_FID_INT_START_X__FID_INT_START_Y);
710 DUMPREG(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X);
711 DUMPREG(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y);
712 DUMPREG(VENC_TVDETGP_INT_START_STOP_X);
713 DUMPREG(VENC_TVDETGP_INT_START_STOP_Y);
714 DUMPREG(VENC_GEN_CTRL);
715 DUMPREG(VENC_OUTPUT_CONTROL);
716 DUMPREG(VENC_OUTPUT_TEST);
717
718 venc_runtime_put();
719
720#undef DUMPREG
721}
722
723static int venc_get_clocks(struct platform_device *pdev)
724{
725 struct clk *clk;
726
727 if (dss_has_feature(FEAT_VENC_REQUIRES_TV_DAC_CLK)) {
728 clk = devm_clk_get(&pdev->dev, "tv_dac_clk");
729 if (IS_ERR(clk)) {
730 DSSERR("can't get tv_dac_clk\n");
731 return PTR_ERR(clk);
732 }
733 } else {
734 clk = NULL;
735 }
736
737 venc.tv_dac_clk = clk;
738
739 return 0;
740}
741
742static int venc_connect(struct omap_dss_device *dssdev,
743 struct omap_dss_device *dst)
744{
745 enum omap_channel channel = dssdev->dispc_channel;
746 int r;
747
748 r = venc_init_regulator();
749 if (r)
750 return r;
751
752 r = dss_mgr_connect(channel, dssdev);
753 if (r)
754 return r;
755
756 r = omapdss_output_set_device(dssdev, dst);
757 if (r) {
758 DSSERR("failed to connect output to new device: %s\n",
759 dst->name);
760 dss_mgr_disconnect(channel, dssdev);
761 return r;
762 }
763
764 return 0;
765}
766
767static void venc_disconnect(struct omap_dss_device *dssdev,
768 struct omap_dss_device *dst)
769{
770 enum omap_channel channel = dssdev->dispc_channel;
771
772 WARN_ON(dst != dssdev->dst);
773
774 if (dst != dssdev->dst)
775 return;
776
777 omapdss_output_unset_device(dssdev);
778
779 dss_mgr_disconnect(channel, dssdev);
780}
781
782static const struct omapdss_atv_ops venc_ops = {
783 .connect = venc_connect,
784 .disconnect = venc_disconnect,
785
786 .enable = venc_display_enable,
787 .disable = venc_display_disable,
788
789 .check_timings = venc_check_timings,
790 .set_timings = venc_set_timings,
791 .get_timings = venc_get_timings,
792
793 .set_type = venc_set_type,
794 .invert_vid_out_polarity = venc_invert_vid_out_polarity,
795
796 .set_wss = venc_set_wss,
797 .get_wss = venc_get_wss,
798};
799
800static void venc_init_output(struct platform_device *pdev)
801{
802 struct omap_dss_device *out = &venc.output;
803
804 out->dev = &pdev->dev;
805 out->id = OMAP_DSS_OUTPUT_VENC;
806 out->output_type = OMAP_DISPLAY_TYPE_VENC;
807 out->name = "venc.0";
808 out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT;
809 out->ops.atv = &venc_ops;
810 out->owner = THIS_MODULE;
811
812 omapdss_register_output(out);
813}
814
815static void venc_uninit_output(struct platform_device *pdev)
816{
817 struct omap_dss_device *out = &venc.output;
818
819 omapdss_unregister_output(out);
820}
821
822static int venc_probe_of(struct platform_device *pdev)
823{
824 struct device_node *node = pdev->dev.of_node;
825 struct device_node *ep;
826 u32 channels;
827 int r;
828
829 ep = omapdss_of_get_first_endpoint(node);
830 if (!ep)
831 return 0;
832
833 venc.invert_polarity = of_property_read_bool(ep, "ti,invert-polarity");
834
835 r = of_property_read_u32(ep, "ti,channels", &channels);
836 if (r) {
837 dev_err(&pdev->dev,
838 "failed to read property 'ti,channels': %d\n", r);
839 goto err;
840 }
841
842 switch (channels) {
843 case 1:
844 venc.type = OMAP_DSS_VENC_TYPE_COMPOSITE;
845 break;
846 case 2:
847 venc.type = OMAP_DSS_VENC_TYPE_SVIDEO;
848 break;
849 default:
850 dev_err(&pdev->dev, "bad channel propert '%d'\n", channels);
851 r = -EINVAL;
852 goto err;
853 }
854
855 of_node_put(ep);
856
857 return 0;
858err:
859 of_node_put(ep);
860
861 return 0;
862}
863
864/* VENC HW IP initialisation */
865static int venc_bind(struct device *dev, struct device *master, void *data)
866{
867 struct platform_device *pdev = to_platform_device(dev);
868 u8 rev_id;
869 struct resource *venc_mem;
870 int r;
871
872 venc.pdev = pdev;
873
874 mutex_init(&venc.venc_lock);
875
876 venc.wss_data = 0;
877
878 venc_mem = platform_get_resource(venc.pdev, IORESOURCE_MEM, 0);
879 if (!venc_mem) {
880 DSSERR("can't get IORESOURCE_MEM VENC\n");
881 return -EINVAL;
882 }
883
884 venc.base = devm_ioremap(&pdev->dev, venc_mem->start,
885 resource_size(venc_mem));
886 if (!venc.base) {
887 DSSERR("can't ioremap VENC\n");
888 return -ENOMEM;
889 }
890
891 r = venc_get_clocks(pdev);
892 if (r)
893 return r;
894
895 pm_runtime_enable(&pdev->dev);
896
897 r = venc_runtime_get();
898 if (r)
899 goto err_runtime_get;
900
901 rev_id = (u8)(venc_read_reg(VENC_REV_ID) & 0xff);
902 dev_dbg(&pdev->dev, "OMAP VENC rev %d\n", rev_id);
903
904 venc_runtime_put();
905
906 if (pdev->dev.of_node) {
907 r = venc_probe_of(pdev);
908 if (r) {
909 DSSERR("Invalid DT data\n");
910 goto err_probe_of;
911 }
912 }
913
914 dss_debugfs_create_file("venc", venc_dump_regs);
915
916 venc_init_output(pdev);
917
918 return 0;
919
920err_probe_of:
921err_runtime_get:
922 pm_runtime_disable(&pdev->dev);
923 return r;
924}
925
926static void venc_unbind(struct device *dev, struct device *master, void *data)
927{
928 struct platform_device *pdev = to_platform_device(dev);
929
930 venc_uninit_output(pdev);
931
932 pm_runtime_disable(&pdev->dev);
933}
934
935static const struct component_ops venc_component_ops = {
936 .bind = venc_bind,
937 .unbind = venc_unbind,
938};
939
940static int venc_probe(struct platform_device *pdev)
941{
942 return component_add(&pdev->dev, &venc_component_ops);
943}
944
945static int venc_remove(struct platform_device *pdev)
946{
947 component_del(&pdev->dev, &venc_component_ops);
948 return 0;
949}
950
951static int venc_runtime_suspend(struct device *dev)
952{
953 if (venc.tv_dac_clk)
954 clk_disable_unprepare(venc.tv_dac_clk);
955
956 dispc_runtime_put();
957
958 return 0;
959}
960
961static int venc_runtime_resume(struct device *dev)
962{
963 int r;
964
965 r = dispc_runtime_get();
966 if (r < 0)
967 return r;
968
969 if (venc.tv_dac_clk)
970 clk_prepare_enable(venc.tv_dac_clk);
971
972 return 0;
973}
974
975static const struct dev_pm_ops venc_pm_ops = {
976 .runtime_suspend = venc_runtime_suspend,
977 .runtime_resume = venc_runtime_resume,
978};
979
980static const struct of_device_id venc_of_match[] = {
981 { .compatible = "ti,omap2-venc", },
982 { .compatible = "ti,omap3-venc", },
983 { .compatible = "ti,omap4-venc", },
984 {},
985};
986
987static struct platform_driver omap_venchw_driver = {
988 .probe = venc_probe,
989 .remove = venc_remove,
990 .driver = {
991 .name = "omapdss_venc",
992 .pm = &venc_pm_ops,
993 .of_match_table = venc_of_match,
994 .suppress_bind_attrs = true,
995 },
996};
997
998int __init venc_init_platform_driver(void)
999{
1000 return platform_driver_register(&omap_venchw_driver);
1001}
1002
1003void venc_uninit_platform_driver(void)
1004{
1005 platform_driver_unregister(&omap_venchw_driver);
1006}
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2009 Nokia Corporation
4 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
5 *
6 * VENC settings from TI's DSS driver
7 */
8
9#define DSS_SUBSYS_NAME "VENC"
10
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/clk.h>
14#include <linux/err.h>
15#include <linux/io.h>
16#include <linux/mutex.h>
17#include <linux/completion.h>
18#include <linux/delay.h>
19#include <linux/string.h>
20#include <linux/seq_file.h>
21#include <linux/platform_device.h>
22#include <linux/regulator/consumer.h>
23#include <linux/pm_runtime.h>
24#include <linux/of.h>
25#include <linux/of_graph.h>
26#include <linux/component.h>
27#include <linux/sys_soc.h>
28
29#include "omapdss.h"
30#include "dss.h"
31
32/* Venc registers */
33#define VENC_REV_ID 0x00
34#define VENC_STATUS 0x04
35#define VENC_F_CONTROL 0x08
36#define VENC_VIDOUT_CTRL 0x10
37#define VENC_SYNC_CTRL 0x14
38#define VENC_LLEN 0x1C
39#define VENC_FLENS 0x20
40#define VENC_HFLTR_CTRL 0x24
41#define VENC_CC_CARR_WSS_CARR 0x28
42#define VENC_C_PHASE 0x2C
43#define VENC_GAIN_U 0x30
44#define VENC_GAIN_V 0x34
45#define VENC_GAIN_Y 0x38
46#define VENC_BLACK_LEVEL 0x3C
47#define VENC_BLANK_LEVEL 0x40
48#define VENC_X_COLOR 0x44
49#define VENC_M_CONTROL 0x48
50#define VENC_BSTAMP_WSS_DATA 0x4C
51#define VENC_S_CARR 0x50
52#define VENC_LINE21 0x54
53#define VENC_LN_SEL 0x58
54#define VENC_L21__WC_CTL 0x5C
55#define VENC_HTRIGGER_VTRIGGER 0x60
56#define VENC_SAVID__EAVID 0x64
57#define VENC_FLEN__FAL 0x68
58#define VENC_LAL__PHASE_RESET 0x6C
59#define VENC_HS_INT_START_STOP_X 0x70
60#define VENC_HS_EXT_START_STOP_X 0x74
61#define VENC_VS_INT_START_X 0x78
62#define VENC_VS_INT_STOP_X__VS_INT_START_Y 0x7C
63#define VENC_VS_INT_STOP_Y__VS_EXT_START_X 0x80
64#define VENC_VS_EXT_STOP_X__VS_EXT_START_Y 0x84
65#define VENC_VS_EXT_STOP_Y 0x88
66#define VENC_AVID_START_STOP_X 0x90
67#define VENC_AVID_START_STOP_Y 0x94
68#define VENC_FID_INT_START_X__FID_INT_START_Y 0xA0
69#define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X 0xA4
70#define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y 0xA8
71#define VENC_TVDETGP_INT_START_STOP_X 0xB0
72#define VENC_TVDETGP_INT_START_STOP_Y 0xB4
73#define VENC_GEN_CTRL 0xB8
74#define VENC_OUTPUT_CONTROL 0xC4
75#define VENC_OUTPUT_TEST 0xC8
76#define VENC_DAC_B__DAC_C 0xC8
77
78struct venc_config {
79 u32 f_control;
80 u32 vidout_ctrl;
81 u32 sync_ctrl;
82 u32 llen;
83 u32 flens;
84 u32 hfltr_ctrl;
85 u32 cc_carr_wss_carr;
86 u32 c_phase;
87 u32 gain_u;
88 u32 gain_v;
89 u32 gain_y;
90 u32 black_level;
91 u32 blank_level;
92 u32 x_color;
93 u32 m_control;
94 u32 bstamp_wss_data;
95 u32 s_carr;
96 u32 line21;
97 u32 ln_sel;
98 u32 l21__wc_ctl;
99 u32 htrigger_vtrigger;
100 u32 savid__eavid;
101 u32 flen__fal;
102 u32 lal__phase_reset;
103 u32 hs_int_start_stop_x;
104 u32 hs_ext_start_stop_x;
105 u32 vs_int_start_x;
106 u32 vs_int_stop_x__vs_int_start_y;
107 u32 vs_int_stop_y__vs_ext_start_x;
108 u32 vs_ext_stop_x__vs_ext_start_y;
109 u32 vs_ext_stop_y;
110 u32 avid_start_stop_x;
111 u32 avid_start_stop_y;
112 u32 fid_int_start_x__fid_int_start_y;
113 u32 fid_int_offset_y__fid_ext_start_x;
114 u32 fid_ext_start_y__fid_ext_offset_y;
115 u32 tvdetgp_int_start_stop_x;
116 u32 tvdetgp_int_start_stop_y;
117 u32 gen_ctrl;
118};
119
120/* from TRM */
121static const struct venc_config venc_config_pal_trm = {
122 .f_control = 0,
123 .vidout_ctrl = 1,
124 .sync_ctrl = 0x40,
125 .llen = 0x35F, /* 863 */
126 .flens = 0x270, /* 624 */
127 .hfltr_ctrl = 0,
128 .cc_carr_wss_carr = 0x2F7225ED,
129 .c_phase = 0,
130 .gain_u = 0x111,
131 .gain_v = 0x181,
132 .gain_y = 0x140,
133 .black_level = 0x3B,
134 .blank_level = 0x3B,
135 .x_color = 0x7,
136 .m_control = 0x2,
137 .bstamp_wss_data = 0x3F,
138 .s_carr = 0x2A098ACB,
139 .line21 = 0,
140 .ln_sel = 0x01290015,
141 .l21__wc_ctl = 0x0000F603,
142 .htrigger_vtrigger = 0,
143
144 .savid__eavid = 0x06A70108,
145 .flen__fal = 0x00180270,
146 .lal__phase_reset = 0x00040135,
147 .hs_int_start_stop_x = 0x00880358,
148 .hs_ext_start_stop_x = 0x000F035F,
149 .vs_int_start_x = 0x01A70000,
150 .vs_int_stop_x__vs_int_start_y = 0x000001A7,
151 .vs_int_stop_y__vs_ext_start_x = 0x01AF0000,
152 .vs_ext_stop_x__vs_ext_start_y = 0x000101AF,
153 .vs_ext_stop_y = 0x00000025,
154 .avid_start_stop_x = 0x03530083,
155 .avid_start_stop_y = 0x026C002E,
156 .fid_int_start_x__fid_int_start_y = 0x0001008A,
157 .fid_int_offset_y__fid_ext_start_x = 0x002E0138,
158 .fid_ext_start_y__fid_ext_offset_y = 0x01380001,
159
160 .tvdetgp_int_start_stop_x = 0x00140001,
161 .tvdetgp_int_start_stop_y = 0x00010001,
162 .gen_ctrl = 0x00FF0000,
163};
164
165/* from TRM */
166static const struct venc_config venc_config_ntsc_trm = {
167 .f_control = 0,
168 .vidout_ctrl = 1,
169 .sync_ctrl = 0x8040,
170 .llen = 0x359,
171 .flens = 0x20C,
172 .hfltr_ctrl = 0,
173 .cc_carr_wss_carr = 0x043F2631,
174 .c_phase = 0,
175 .gain_u = 0x102,
176 .gain_v = 0x16C,
177 .gain_y = 0x12F,
178 .black_level = 0x43,
179 .blank_level = 0x38,
180 .x_color = 0x7,
181 .m_control = 0x1,
182 .bstamp_wss_data = 0x38,
183 .s_carr = 0x21F07C1F,
184 .line21 = 0,
185 .ln_sel = 0x01310011,
186 .l21__wc_ctl = 0x0000F003,
187 .htrigger_vtrigger = 0,
188
189 .savid__eavid = 0x069300F4,
190 .flen__fal = 0x0016020C,
191 .lal__phase_reset = 0x00060107,
192 .hs_int_start_stop_x = 0x008E0350,
193 .hs_ext_start_stop_x = 0x000F0359,
194 .vs_int_start_x = 0x01A00000,
195 .vs_int_stop_x__vs_int_start_y = 0x020701A0,
196 .vs_int_stop_y__vs_ext_start_x = 0x01AC0024,
197 .vs_ext_stop_x__vs_ext_start_y = 0x020D01AC,
198 .vs_ext_stop_y = 0x00000006,
199 .avid_start_stop_x = 0x03480078,
200 .avid_start_stop_y = 0x02060024,
201 .fid_int_start_x__fid_int_start_y = 0x0001008A,
202 .fid_int_offset_y__fid_ext_start_x = 0x01AC0106,
203 .fid_ext_start_y__fid_ext_offset_y = 0x01060006,
204
205 .tvdetgp_int_start_stop_x = 0x00140001,
206 .tvdetgp_int_start_stop_y = 0x00010001,
207 .gen_ctrl = 0x00F90000,
208};
209
210static const struct venc_config venc_config_pal_bdghi = {
211 .f_control = 0,
212 .vidout_ctrl = 0,
213 .sync_ctrl = 0,
214 .hfltr_ctrl = 0,
215 .x_color = 0,
216 .line21 = 0,
217 .ln_sel = 21,
218 .htrigger_vtrigger = 0,
219 .tvdetgp_int_start_stop_x = 0x00140001,
220 .tvdetgp_int_start_stop_y = 0x00010001,
221 .gen_ctrl = 0x00FB0000,
222
223 .llen = 864-1,
224 .flens = 625-1,
225 .cc_carr_wss_carr = 0x2F7625ED,
226 .c_phase = 0xDF,
227 .gain_u = 0x111,
228 .gain_v = 0x181,
229 .gain_y = 0x140,
230 .black_level = 0x3e,
231 .blank_level = 0x3e,
232 .m_control = 0<<2 | 1<<1,
233 .bstamp_wss_data = 0x42,
234 .s_carr = 0x2a098acb,
235 .l21__wc_ctl = 0<<13 | 0x16<<8 | 0<<0,
236 .savid__eavid = 0x06A70108,
237 .flen__fal = 23<<16 | 624<<0,
238 .lal__phase_reset = 2<<17 | 310<<0,
239 .hs_int_start_stop_x = 0x00920358,
240 .hs_ext_start_stop_x = 0x000F035F,
241 .vs_int_start_x = 0x1a7<<16,
242 .vs_int_stop_x__vs_int_start_y = 0x000601A7,
243 .vs_int_stop_y__vs_ext_start_x = 0x01AF0036,
244 .vs_ext_stop_x__vs_ext_start_y = 0x27101af,
245 .vs_ext_stop_y = 0x05,
246 .avid_start_stop_x = 0x03530082,
247 .avid_start_stop_y = 0x0270002E,
248 .fid_int_start_x__fid_int_start_y = 0x0005008A,
249 .fid_int_offset_y__fid_ext_start_x = 0x002E0138,
250 .fid_ext_start_y__fid_ext_offset_y = 0x01380005,
251};
252
253enum venc_videomode {
254 VENC_MODE_UNKNOWN,
255 VENC_MODE_PAL,
256 VENC_MODE_NTSC,
257};
258
259static const struct drm_display_mode omap_dss_pal_mode = {
260 .hdisplay = 720,
261 .hsync_start = 732,
262 .hsync_end = 796,
263 .htotal = 864,
264 .vdisplay = 574,
265 .vsync_start = 579,
266 .vsync_end = 584,
267 .vtotal = 625,
268 .clock = 13500,
269
270 .flags = DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_NHSYNC |
271 DRM_MODE_FLAG_NVSYNC,
272};
273
274static const struct drm_display_mode omap_dss_ntsc_mode = {
275 .hdisplay = 720,
276 .hsync_start = 736,
277 .hsync_end = 800,
278 .htotal = 858,
279 .vdisplay = 482,
280 .vsync_start = 488,
281 .vsync_end = 494,
282 .vtotal = 525,
283 .clock = 13500,
284
285 .flags = DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_NHSYNC |
286 DRM_MODE_FLAG_NVSYNC,
287};
288
289struct venc_device {
290 struct platform_device *pdev;
291 void __iomem *base;
292 struct mutex venc_lock;
293 struct regulator *vdda_dac_reg;
294 struct dss_device *dss;
295
296 struct dss_debugfs_entry *debugfs;
297
298 struct clk *tv_dac_clk;
299
300 const struct venc_config *config;
301 enum omap_dss_venc_type type;
302 bool invert_polarity;
303 bool requires_tv_dac_clk;
304
305 struct omap_dss_device output;
306};
307
308#define dssdev_to_venc(dssdev) container_of(dssdev, struct venc_device, output)
309
310static inline void venc_write_reg(struct venc_device *venc, int idx, u32 val)
311{
312 __raw_writel(val, venc->base + idx);
313}
314
315static inline u32 venc_read_reg(struct venc_device *venc, int idx)
316{
317 u32 l = __raw_readl(venc->base + idx);
318 return l;
319}
320
321static void venc_write_config(struct venc_device *venc,
322 const struct venc_config *config)
323{
324 DSSDBG("write venc conf\n");
325
326 venc_write_reg(venc, VENC_LLEN, config->llen);
327 venc_write_reg(venc, VENC_FLENS, config->flens);
328 venc_write_reg(venc, VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr);
329 venc_write_reg(venc, VENC_C_PHASE, config->c_phase);
330 venc_write_reg(venc, VENC_GAIN_U, config->gain_u);
331 venc_write_reg(venc, VENC_GAIN_V, config->gain_v);
332 venc_write_reg(venc, VENC_GAIN_Y, config->gain_y);
333 venc_write_reg(venc, VENC_BLACK_LEVEL, config->black_level);
334 venc_write_reg(venc, VENC_BLANK_LEVEL, config->blank_level);
335 venc_write_reg(venc, VENC_M_CONTROL, config->m_control);
336 venc_write_reg(venc, VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data);
337 venc_write_reg(venc, VENC_S_CARR, config->s_carr);
338 venc_write_reg(venc, VENC_L21__WC_CTL, config->l21__wc_ctl);
339 venc_write_reg(venc, VENC_SAVID__EAVID, config->savid__eavid);
340 venc_write_reg(venc, VENC_FLEN__FAL, config->flen__fal);
341 venc_write_reg(venc, VENC_LAL__PHASE_RESET, config->lal__phase_reset);
342 venc_write_reg(venc, VENC_HS_INT_START_STOP_X,
343 config->hs_int_start_stop_x);
344 venc_write_reg(venc, VENC_HS_EXT_START_STOP_X,
345 config->hs_ext_start_stop_x);
346 venc_write_reg(venc, VENC_VS_INT_START_X, config->vs_int_start_x);
347 venc_write_reg(venc, VENC_VS_INT_STOP_X__VS_INT_START_Y,
348 config->vs_int_stop_x__vs_int_start_y);
349 venc_write_reg(venc, VENC_VS_INT_STOP_Y__VS_EXT_START_X,
350 config->vs_int_stop_y__vs_ext_start_x);
351 venc_write_reg(venc, VENC_VS_EXT_STOP_X__VS_EXT_START_Y,
352 config->vs_ext_stop_x__vs_ext_start_y);
353 venc_write_reg(venc, VENC_VS_EXT_STOP_Y, config->vs_ext_stop_y);
354 venc_write_reg(venc, VENC_AVID_START_STOP_X, config->avid_start_stop_x);
355 venc_write_reg(venc, VENC_AVID_START_STOP_Y, config->avid_start_stop_y);
356 venc_write_reg(venc, VENC_FID_INT_START_X__FID_INT_START_Y,
357 config->fid_int_start_x__fid_int_start_y);
358 venc_write_reg(venc, VENC_FID_INT_OFFSET_Y__FID_EXT_START_X,
359 config->fid_int_offset_y__fid_ext_start_x);
360 venc_write_reg(venc, VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y,
361 config->fid_ext_start_y__fid_ext_offset_y);
362
363 venc_write_reg(venc, VENC_DAC_B__DAC_C,
364 venc_read_reg(venc, VENC_DAC_B__DAC_C));
365 venc_write_reg(venc, VENC_VIDOUT_CTRL, config->vidout_ctrl);
366 venc_write_reg(venc, VENC_HFLTR_CTRL, config->hfltr_ctrl);
367 venc_write_reg(venc, VENC_X_COLOR, config->x_color);
368 venc_write_reg(venc, VENC_LINE21, config->line21);
369 venc_write_reg(venc, VENC_LN_SEL, config->ln_sel);
370 venc_write_reg(venc, VENC_HTRIGGER_VTRIGGER, config->htrigger_vtrigger);
371 venc_write_reg(venc, VENC_TVDETGP_INT_START_STOP_X,
372 config->tvdetgp_int_start_stop_x);
373 venc_write_reg(venc, VENC_TVDETGP_INT_START_STOP_Y,
374 config->tvdetgp_int_start_stop_y);
375 venc_write_reg(venc, VENC_GEN_CTRL, config->gen_ctrl);
376 venc_write_reg(venc, VENC_F_CONTROL, config->f_control);
377 venc_write_reg(venc, VENC_SYNC_CTRL, config->sync_ctrl);
378}
379
380static void venc_reset(struct venc_device *venc)
381{
382 int t = 1000;
383
384 venc_write_reg(venc, VENC_F_CONTROL, 1<<8);
385 while (venc_read_reg(venc, VENC_F_CONTROL) & (1<<8)) {
386 if (--t == 0) {
387 DSSERR("Failed to reset venc\n");
388 return;
389 }
390 }
391
392#ifdef CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET
393 /* the magical sleep that makes things work */
394 /* XXX more info? What bug this circumvents? */
395 msleep(20);
396#endif
397}
398
399static int venc_runtime_get(struct venc_device *venc)
400{
401 int r;
402
403 DSSDBG("venc_runtime_get\n");
404
405 r = pm_runtime_get_sync(&venc->pdev->dev);
406 WARN_ON(r < 0);
407 return r < 0 ? r : 0;
408}
409
410static void venc_runtime_put(struct venc_device *venc)
411{
412 int r;
413
414 DSSDBG("venc_runtime_put\n");
415
416 r = pm_runtime_put_sync(&venc->pdev->dev);
417 WARN_ON(r < 0 && r != -ENOSYS);
418}
419
420static int venc_power_on(struct venc_device *venc)
421{
422 u32 l;
423 int r;
424
425 r = venc_runtime_get(venc);
426 if (r)
427 goto err0;
428
429 venc_reset(venc);
430 venc_write_config(venc, venc->config);
431
432 dss_set_venc_output(venc->dss, venc->type);
433 dss_set_dac_pwrdn_bgz(venc->dss, 1);
434
435 l = 0;
436
437 if (venc->type == OMAP_DSS_VENC_TYPE_COMPOSITE)
438 l |= 1 << 1;
439 else /* S-Video */
440 l |= (1 << 0) | (1 << 2);
441
442 if (venc->invert_polarity == false)
443 l |= 1 << 3;
444
445 venc_write_reg(venc, VENC_OUTPUT_CONTROL, l);
446
447 r = regulator_enable(venc->vdda_dac_reg);
448 if (r)
449 goto err1;
450
451 r = dss_mgr_enable(&venc->output);
452 if (r)
453 goto err2;
454
455 return 0;
456
457err2:
458 regulator_disable(venc->vdda_dac_reg);
459err1:
460 venc_write_reg(venc, VENC_OUTPUT_CONTROL, 0);
461 dss_set_dac_pwrdn_bgz(venc->dss, 0);
462
463 venc_runtime_put(venc);
464err0:
465 return r;
466}
467
468static void venc_power_off(struct venc_device *venc)
469{
470 venc_write_reg(venc, VENC_OUTPUT_CONTROL, 0);
471 dss_set_dac_pwrdn_bgz(venc->dss, 0);
472
473 dss_mgr_disable(&venc->output);
474
475 regulator_disable(venc->vdda_dac_reg);
476
477 venc_runtime_put(venc);
478}
479
480static void venc_display_enable(struct omap_dss_device *dssdev)
481{
482 struct venc_device *venc = dssdev_to_venc(dssdev);
483
484 DSSDBG("venc_display_enable\n");
485
486 mutex_lock(&venc->venc_lock);
487
488 venc_power_on(venc);
489
490 mutex_unlock(&venc->venc_lock);
491}
492
493static void venc_display_disable(struct omap_dss_device *dssdev)
494{
495 struct venc_device *venc = dssdev_to_venc(dssdev);
496
497 DSSDBG("venc_display_disable\n");
498
499 mutex_lock(&venc->venc_lock);
500
501 venc_power_off(venc);
502
503 mutex_unlock(&venc->venc_lock);
504}
505
506static int venc_get_modes(struct omap_dss_device *dssdev,
507 struct drm_connector *connector)
508{
509 static const struct drm_display_mode *modes[] = {
510 &omap_dss_pal_mode,
511 &omap_dss_ntsc_mode,
512 };
513 unsigned int i;
514
515 for (i = 0; i < ARRAY_SIZE(modes); ++i) {
516 struct drm_display_mode *mode;
517
518 mode = drm_mode_duplicate(connector->dev, modes[i]);
519 if (!mode)
520 return i;
521
522 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
523 drm_mode_set_name(mode);
524 drm_mode_probed_add(connector, mode);
525 }
526
527 return ARRAY_SIZE(modes);
528}
529
530static enum venc_videomode venc_get_videomode(const struct drm_display_mode *mode)
531{
532 if (!(mode->flags & DRM_MODE_FLAG_INTERLACE))
533 return VENC_MODE_UNKNOWN;
534
535 if (mode->clock == omap_dss_pal_mode.clock &&
536 mode->hdisplay == omap_dss_pal_mode.hdisplay &&
537 mode->vdisplay == omap_dss_pal_mode.vdisplay)
538 return VENC_MODE_PAL;
539
540 if (mode->clock == omap_dss_ntsc_mode.clock &&
541 mode->hdisplay == omap_dss_ntsc_mode.hdisplay &&
542 mode->vdisplay == omap_dss_ntsc_mode.vdisplay)
543 return VENC_MODE_NTSC;
544
545 return VENC_MODE_UNKNOWN;
546}
547
548static void venc_set_timings(struct omap_dss_device *dssdev,
549 const struct drm_display_mode *mode)
550{
551 struct venc_device *venc = dssdev_to_venc(dssdev);
552 enum venc_videomode venc_mode = venc_get_videomode(mode);
553
554 DSSDBG("venc_set_timings\n");
555
556 mutex_lock(&venc->venc_lock);
557
558 switch (venc_mode) {
559 default:
560 WARN_ON_ONCE(1);
561 /* Fall-through */
562 case VENC_MODE_PAL:
563 venc->config = &venc_config_pal_trm;
564 break;
565
566 case VENC_MODE_NTSC:
567 venc->config = &venc_config_ntsc_trm;
568 break;
569 }
570
571 dispc_set_tv_pclk(venc->dss->dispc, 13500000);
572
573 mutex_unlock(&venc->venc_lock);
574}
575
576static int venc_check_timings(struct omap_dss_device *dssdev,
577 struct drm_display_mode *mode)
578{
579 DSSDBG("venc_check_timings\n");
580
581 switch (venc_get_videomode(mode)) {
582 case VENC_MODE_PAL:
583 drm_mode_copy(mode, &omap_dss_pal_mode);
584 break;
585
586 case VENC_MODE_NTSC:
587 drm_mode_copy(mode, &omap_dss_ntsc_mode);
588 break;
589
590 default:
591 return -EINVAL;
592 }
593
594 drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V);
595 drm_mode_set_name(mode);
596 return 0;
597}
598
599static int venc_dump_regs(struct seq_file *s, void *p)
600{
601 struct venc_device *venc = s->private;
602
603#define DUMPREG(venc, r) \
604 seq_printf(s, "%-35s %08x\n", #r, venc_read_reg(venc, r))
605
606 if (venc_runtime_get(venc))
607 return 0;
608
609 DUMPREG(venc, VENC_F_CONTROL);
610 DUMPREG(venc, VENC_VIDOUT_CTRL);
611 DUMPREG(venc, VENC_SYNC_CTRL);
612 DUMPREG(venc, VENC_LLEN);
613 DUMPREG(venc, VENC_FLENS);
614 DUMPREG(venc, VENC_HFLTR_CTRL);
615 DUMPREG(venc, VENC_CC_CARR_WSS_CARR);
616 DUMPREG(venc, VENC_C_PHASE);
617 DUMPREG(venc, VENC_GAIN_U);
618 DUMPREG(venc, VENC_GAIN_V);
619 DUMPREG(venc, VENC_GAIN_Y);
620 DUMPREG(venc, VENC_BLACK_LEVEL);
621 DUMPREG(venc, VENC_BLANK_LEVEL);
622 DUMPREG(venc, VENC_X_COLOR);
623 DUMPREG(venc, VENC_M_CONTROL);
624 DUMPREG(venc, VENC_BSTAMP_WSS_DATA);
625 DUMPREG(venc, VENC_S_CARR);
626 DUMPREG(venc, VENC_LINE21);
627 DUMPREG(venc, VENC_LN_SEL);
628 DUMPREG(venc, VENC_L21__WC_CTL);
629 DUMPREG(venc, VENC_HTRIGGER_VTRIGGER);
630 DUMPREG(venc, VENC_SAVID__EAVID);
631 DUMPREG(venc, VENC_FLEN__FAL);
632 DUMPREG(venc, VENC_LAL__PHASE_RESET);
633 DUMPREG(venc, VENC_HS_INT_START_STOP_X);
634 DUMPREG(venc, VENC_HS_EXT_START_STOP_X);
635 DUMPREG(venc, VENC_VS_INT_START_X);
636 DUMPREG(venc, VENC_VS_INT_STOP_X__VS_INT_START_Y);
637 DUMPREG(venc, VENC_VS_INT_STOP_Y__VS_EXT_START_X);
638 DUMPREG(venc, VENC_VS_EXT_STOP_X__VS_EXT_START_Y);
639 DUMPREG(venc, VENC_VS_EXT_STOP_Y);
640 DUMPREG(venc, VENC_AVID_START_STOP_X);
641 DUMPREG(venc, VENC_AVID_START_STOP_Y);
642 DUMPREG(venc, VENC_FID_INT_START_X__FID_INT_START_Y);
643 DUMPREG(venc, VENC_FID_INT_OFFSET_Y__FID_EXT_START_X);
644 DUMPREG(venc, VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y);
645 DUMPREG(venc, VENC_TVDETGP_INT_START_STOP_X);
646 DUMPREG(venc, VENC_TVDETGP_INT_START_STOP_Y);
647 DUMPREG(venc, VENC_GEN_CTRL);
648 DUMPREG(venc, VENC_OUTPUT_CONTROL);
649 DUMPREG(venc, VENC_OUTPUT_TEST);
650
651 venc_runtime_put(venc);
652
653#undef DUMPREG
654 return 0;
655}
656
657static int venc_get_clocks(struct venc_device *venc)
658{
659 struct clk *clk;
660
661 if (venc->requires_tv_dac_clk) {
662 clk = devm_clk_get(&venc->pdev->dev, "tv_dac_clk");
663 if (IS_ERR(clk)) {
664 DSSERR("can't get tv_dac_clk\n");
665 return PTR_ERR(clk);
666 }
667 } else {
668 clk = NULL;
669 }
670
671 venc->tv_dac_clk = clk;
672
673 return 0;
674}
675
676static int venc_connect(struct omap_dss_device *src,
677 struct omap_dss_device *dst)
678{
679 return omapdss_device_connect(dst->dss, dst, dst->next);
680}
681
682static void venc_disconnect(struct omap_dss_device *src,
683 struct omap_dss_device *dst)
684{
685 omapdss_device_disconnect(dst, dst->next);
686}
687
688static const struct omap_dss_device_ops venc_ops = {
689 .connect = venc_connect,
690 .disconnect = venc_disconnect,
691
692 .enable = venc_display_enable,
693 .disable = venc_display_disable,
694
695 .check_timings = venc_check_timings,
696 .set_timings = venc_set_timings,
697
698 .get_modes = venc_get_modes,
699};
700
701/* -----------------------------------------------------------------------------
702 * Component Bind & Unbind
703 */
704
705static int venc_bind(struct device *dev, struct device *master, void *data)
706{
707 struct dss_device *dss = dss_get_device(master);
708 struct venc_device *venc = dev_get_drvdata(dev);
709 u8 rev_id;
710 int r;
711
712 venc->dss = dss;
713
714 r = venc_runtime_get(venc);
715 if (r)
716 return r;
717
718 rev_id = (u8)(venc_read_reg(venc, VENC_REV_ID) & 0xff);
719 dev_dbg(dev, "OMAP VENC rev %d\n", rev_id);
720
721 venc_runtime_put(venc);
722
723 venc->debugfs = dss_debugfs_create_file(dss, "venc", venc_dump_regs,
724 venc);
725
726 return 0;
727}
728
729static void venc_unbind(struct device *dev, struct device *master, void *data)
730{
731 struct venc_device *venc = dev_get_drvdata(dev);
732
733 dss_debugfs_remove_file(venc->debugfs);
734}
735
736static const struct component_ops venc_component_ops = {
737 .bind = venc_bind,
738 .unbind = venc_unbind,
739};
740
741/* -----------------------------------------------------------------------------
742 * Probe & Remove, Suspend & Resume
743 */
744
745static int venc_init_output(struct venc_device *venc)
746{
747 struct omap_dss_device *out = &venc->output;
748 int r;
749
750 out->dev = &venc->pdev->dev;
751 out->id = OMAP_DSS_OUTPUT_VENC;
752 out->type = OMAP_DISPLAY_TYPE_VENC;
753 out->name = "venc.0";
754 out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT;
755 out->ops = &venc_ops;
756 out->owner = THIS_MODULE;
757 out->of_ports = BIT(0);
758 out->ops_flags = OMAP_DSS_DEVICE_OP_MODES;
759
760 r = omapdss_device_init_output(out);
761 if (r < 0)
762 return r;
763
764 omapdss_device_register(out);
765
766 return 0;
767}
768
769static void venc_uninit_output(struct venc_device *venc)
770{
771 omapdss_device_unregister(&venc->output);
772 omapdss_device_cleanup_output(&venc->output);
773}
774
775static int venc_probe_of(struct venc_device *venc)
776{
777 struct device_node *node = venc->pdev->dev.of_node;
778 struct device_node *ep;
779 u32 channels;
780 int r;
781
782 ep = of_graph_get_endpoint_by_regs(node, 0, 0);
783 if (!ep)
784 return 0;
785
786 venc->invert_polarity = of_property_read_bool(ep, "ti,invert-polarity");
787
788 r = of_property_read_u32(ep, "ti,channels", &channels);
789 if (r) {
790 dev_err(&venc->pdev->dev,
791 "failed to read property 'ti,channels': %d\n", r);
792 goto err;
793 }
794
795 switch (channels) {
796 case 1:
797 venc->type = OMAP_DSS_VENC_TYPE_COMPOSITE;
798 break;
799 case 2:
800 venc->type = OMAP_DSS_VENC_TYPE_SVIDEO;
801 break;
802 default:
803 dev_err(&venc->pdev->dev, "bad channel propert '%d'\n",
804 channels);
805 r = -EINVAL;
806 goto err;
807 }
808
809 of_node_put(ep);
810
811 return 0;
812
813err:
814 of_node_put(ep);
815 return r;
816}
817
818static const struct soc_device_attribute venc_soc_devices[] = {
819 { .machine = "OMAP3[45]*" },
820 { .machine = "AM35*" },
821 { /* sentinel */ }
822};
823
824static int venc_probe(struct platform_device *pdev)
825{
826 struct venc_device *venc;
827 struct resource *venc_mem;
828 int r;
829
830 venc = kzalloc(sizeof(*venc), GFP_KERNEL);
831 if (!venc)
832 return -ENOMEM;
833
834 venc->pdev = pdev;
835
836 platform_set_drvdata(pdev, venc);
837
838 /* The OMAP34xx, OMAP35xx and AM35xx VENC require the TV DAC clock. */
839 if (soc_device_match(venc_soc_devices))
840 venc->requires_tv_dac_clk = true;
841
842 mutex_init(&venc->venc_lock);
843
844 venc->config = &venc_config_pal_trm;
845
846 venc_mem = platform_get_resource(venc->pdev, IORESOURCE_MEM, 0);
847 venc->base = devm_ioremap_resource(&pdev->dev, venc_mem);
848 if (IS_ERR(venc->base)) {
849 r = PTR_ERR(venc->base);
850 goto err_free;
851 }
852
853 venc->vdda_dac_reg = devm_regulator_get(&pdev->dev, "vdda");
854 if (IS_ERR(venc->vdda_dac_reg)) {
855 r = PTR_ERR(venc->vdda_dac_reg);
856 if (r != -EPROBE_DEFER)
857 DSSERR("can't get VDDA_DAC regulator\n");
858 goto err_free;
859 }
860
861 r = venc_get_clocks(venc);
862 if (r)
863 goto err_free;
864
865 r = venc_probe_of(venc);
866 if (r)
867 goto err_free;
868
869 pm_runtime_enable(&pdev->dev);
870
871 r = venc_init_output(venc);
872 if (r)
873 goto err_pm_disable;
874
875 r = component_add(&pdev->dev, &venc_component_ops);
876 if (r)
877 goto err_uninit_output;
878
879 return 0;
880
881err_uninit_output:
882 venc_uninit_output(venc);
883err_pm_disable:
884 pm_runtime_disable(&pdev->dev);
885err_free:
886 kfree(venc);
887 return r;
888}
889
890static int venc_remove(struct platform_device *pdev)
891{
892 struct venc_device *venc = platform_get_drvdata(pdev);
893
894 component_del(&pdev->dev, &venc_component_ops);
895
896 venc_uninit_output(venc);
897
898 pm_runtime_disable(&pdev->dev);
899
900 kfree(venc);
901 return 0;
902}
903
904static int venc_runtime_suspend(struct device *dev)
905{
906 struct venc_device *venc = dev_get_drvdata(dev);
907
908 if (venc->tv_dac_clk)
909 clk_disable_unprepare(venc->tv_dac_clk);
910
911 return 0;
912}
913
914static int venc_runtime_resume(struct device *dev)
915{
916 struct venc_device *venc = dev_get_drvdata(dev);
917
918 if (venc->tv_dac_clk)
919 clk_prepare_enable(venc->tv_dac_clk);
920
921 return 0;
922}
923
924static const struct dev_pm_ops venc_pm_ops = {
925 .runtime_suspend = venc_runtime_suspend,
926 .runtime_resume = venc_runtime_resume,
927};
928
929static const struct of_device_id venc_of_match[] = {
930 { .compatible = "ti,omap2-venc", },
931 { .compatible = "ti,omap3-venc", },
932 { .compatible = "ti,omap4-venc", },
933 {},
934};
935
936struct platform_driver omap_venchw_driver = {
937 .probe = venc_probe,
938 .remove = venc_remove,
939 .driver = {
940 .name = "omapdss_venc",
941 .pm = &venc_pm_ops,
942 .of_match_table = venc_of_match,
943 .suppress_bind_attrs = true,
944 },
945};