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1/*
2 * linux/drivers/video/omap2/dss/venc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * VENC settings from TI's DSS driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#define DSS_SUBSYS_NAME "VENC"
23
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/clk.h>
27#include <linux/err.h>
28#include <linux/io.h>
29#include <linux/mutex.h>
30#include <linux/completion.h>
31#include <linux/delay.h>
32#include <linux/string.h>
33#include <linux/seq_file.h>
34#include <linux/platform_device.h>
35#include <linux/regulator/consumer.h>
36#include <linux/pm_runtime.h>
37#include <linux/of.h>
38#include <linux/component.h>
39
40#include <video/omapdss.h>
41
42#include "dss.h"
43#include "dss_features.h"
44
45/* Venc registers */
46#define VENC_REV_ID 0x00
47#define VENC_STATUS 0x04
48#define VENC_F_CONTROL 0x08
49#define VENC_VIDOUT_CTRL 0x10
50#define VENC_SYNC_CTRL 0x14
51#define VENC_LLEN 0x1C
52#define VENC_FLENS 0x20
53#define VENC_HFLTR_CTRL 0x24
54#define VENC_CC_CARR_WSS_CARR 0x28
55#define VENC_C_PHASE 0x2C
56#define VENC_GAIN_U 0x30
57#define VENC_GAIN_V 0x34
58#define VENC_GAIN_Y 0x38
59#define VENC_BLACK_LEVEL 0x3C
60#define VENC_BLANK_LEVEL 0x40
61#define VENC_X_COLOR 0x44
62#define VENC_M_CONTROL 0x48
63#define VENC_BSTAMP_WSS_DATA 0x4C
64#define VENC_S_CARR 0x50
65#define VENC_LINE21 0x54
66#define VENC_LN_SEL 0x58
67#define VENC_L21__WC_CTL 0x5C
68#define VENC_HTRIGGER_VTRIGGER 0x60
69#define VENC_SAVID__EAVID 0x64
70#define VENC_FLEN__FAL 0x68
71#define VENC_LAL__PHASE_RESET 0x6C
72#define VENC_HS_INT_START_STOP_X 0x70
73#define VENC_HS_EXT_START_STOP_X 0x74
74#define VENC_VS_INT_START_X 0x78
75#define VENC_VS_INT_STOP_X__VS_INT_START_Y 0x7C
76#define VENC_VS_INT_STOP_Y__VS_EXT_START_X 0x80
77#define VENC_VS_EXT_STOP_X__VS_EXT_START_Y 0x84
78#define VENC_VS_EXT_STOP_Y 0x88
79#define VENC_AVID_START_STOP_X 0x90
80#define VENC_AVID_START_STOP_Y 0x94
81#define VENC_FID_INT_START_X__FID_INT_START_Y 0xA0
82#define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X 0xA4
83#define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y 0xA8
84#define VENC_TVDETGP_INT_START_STOP_X 0xB0
85#define VENC_TVDETGP_INT_START_STOP_Y 0xB4
86#define VENC_GEN_CTRL 0xB8
87#define VENC_OUTPUT_CONTROL 0xC4
88#define VENC_OUTPUT_TEST 0xC8
89#define VENC_DAC_B__DAC_C 0xC8
90
91struct venc_config {
92 u32 f_control;
93 u32 vidout_ctrl;
94 u32 sync_ctrl;
95 u32 llen;
96 u32 flens;
97 u32 hfltr_ctrl;
98 u32 cc_carr_wss_carr;
99 u32 c_phase;
100 u32 gain_u;
101 u32 gain_v;
102 u32 gain_y;
103 u32 black_level;
104 u32 blank_level;
105 u32 x_color;
106 u32 m_control;
107 u32 bstamp_wss_data;
108 u32 s_carr;
109 u32 line21;
110 u32 ln_sel;
111 u32 l21__wc_ctl;
112 u32 htrigger_vtrigger;
113 u32 savid__eavid;
114 u32 flen__fal;
115 u32 lal__phase_reset;
116 u32 hs_int_start_stop_x;
117 u32 hs_ext_start_stop_x;
118 u32 vs_int_start_x;
119 u32 vs_int_stop_x__vs_int_start_y;
120 u32 vs_int_stop_y__vs_ext_start_x;
121 u32 vs_ext_stop_x__vs_ext_start_y;
122 u32 vs_ext_stop_y;
123 u32 avid_start_stop_x;
124 u32 avid_start_stop_y;
125 u32 fid_int_start_x__fid_int_start_y;
126 u32 fid_int_offset_y__fid_ext_start_x;
127 u32 fid_ext_start_y__fid_ext_offset_y;
128 u32 tvdetgp_int_start_stop_x;
129 u32 tvdetgp_int_start_stop_y;
130 u32 gen_ctrl;
131};
132
133/* from TRM */
134static const struct venc_config venc_config_pal_trm = {
135 .f_control = 0,
136 .vidout_ctrl = 1,
137 .sync_ctrl = 0x40,
138 .llen = 0x35F, /* 863 */
139 .flens = 0x270, /* 624 */
140 .hfltr_ctrl = 0,
141 .cc_carr_wss_carr = 0x2F7225ED,
142 .c_phase = 0,
143 .gain_u = 0x111,
144 .gain_v = 0x181,
145 .gain_y = 0x140,
146 .black_level = 0x3B,
147 .blank_level = 0x3B,
148 .x_color = 0x7,
149 .m_control = 0x2,
150 .bstamp_wss_data = 0x3F,
151 .s_carr = 0x2A098ACB,
152 .line21 = 0,
153 .ln_sel = 0x01290015,
154 .l21__wc_ctl = 0x0000F603,
155 .htrigger_vtrigger = 0,
156
157 .savid__eavid = 0x06A70108,
158 .flen__fal = 0x00180270,
159 .lal__phase_reset = 0x00040135,
160 .hs_int_start_stop_x = 0x00880358,
161 .hs_ext_start_stop_x = 0x000F035F,
162 .vs_int_start_x = 0x01A70000,
163 .vs_int_stop_x__vs_int_start_y = 0x000001A7,
164 .vs_int_stop_y__vs_ext_start_x = 0x01AF0000,
165 .vs_ext_stop_x__vs_ext_start_y = 0x000101AF,
166 .vs_ext_stop_y = 0x00000025,
167 .avid_start_stop_x = 0x03530083,
168 .avid_start_stop_y = 0x026C002E,
169 .fid_int_start_x__fid_int_start_y = 0x0001008A,
170 .fid_int_offset_y__fid_ext_start_x = 0x002E0138,
171 .fid_ext_start_y__fid_ext_offset_y = 0x01380001,
172
173 .tvdetgp_int_start_stop_x = 0x00140001,
174 .tvdetgp_int_start_stop_y = 0x00010001,
175 .gen_ctrl = 0x00FF0000,
176};
177
178/* from TRM */
179static const struct venc_config venc_config_ntsc_trm = {
180 .f_control = 0,
181 .vidout_ctrl = 1,
182 .sync_ctrl = 0x8040,
183 .llen = 0x359,
184 .flens = 0x20C,
185 .hfltr_ctrl = 0,
186 .cc_carr_wss_carr = 0x043F2631,
187 .c_phase = 0,
188 .gain_u = 0x102,
189 .gain_v = 0x16C,
190 .gain_y = 0x12F,
191 .black_level = 0x43,
192 .blank_level = 0x38,
193 .x_color = 0x7,
194 .m_control = 0x1,
195 .bstamp_wss_data = 0x38,
196 .s_carr = 0x21F07C1F,
197 .line21 = 0,
198 .ln_sel = 0x01310011,
199 .l21__wc_ctl = 0x0000F003,
200 .htrigger_vtrigger = 0,
201
202 .savid__eavid = 0x069300F4,
203 .flen__fal = 0x0016020C,
204 .lal__phase_reset = 0x00060107,
205 .hs_int_start_stop_x = 0x008E0350,
206 .hs_ext_start_stop_x = 0x000F0359,
207 .vs_int_start_x = 0x01A00000,
208 .vs_int_stop_x__vs_int_start_y = 0x020701A0,
209 .vs_int_stop_y__vs_ext_start_x = 0x01AC0024,
210 .vs_ext_stop_x__vs_ext_start_y = 0x020D01AC,
211 .vs_ext_stop_y = 0x00000006,
212 .avid_start_stop_x = 0x03480078,
213 .avid_start_stop_y = 0x02060024,
214 .fid_int_start_x__fid_int_start_y = 0x0001008A,
215 .fid_int_offset_y__fid_ext_start_x = 0x01AC0106,
216 .fid_ext_start_y__fid_ext_offset_y = 0x01060006,
217
218 .tvdetgp_int_start_stop_x = 0x00140001,
219 .tvdetgp_int_start_stop_y = 0x00010001,
220 .gen_ctrl = 0x00F90000,
221};
222
223static const struct venc_config venc_config_pal_bdghi = {
224 .f_control = 0,
225 .vidout_ctrl = 0,
226 .sync_ctrl = 0,
227 .hfltr_ctrl = 0,
228 .x_color = 0,
229 .line21 = 0,
230 .ln_sel = 21,
231 .htrigger_vtrigger = 0,
232 .tvdetgp_int_start_stop_x = 0x00140001,
233 .tvdetgp_int_start_stop_y = 0x00010001,
234 .gen_ctrl = 0x00FB0000,
235
236 .llen = 864-1,
237 .flens = 625-1,
238 .cc_carr_wss_carr = 0x2F7625ED,
239 .c_phase = 0xDF,
240 .gain_u = 0x111,
241 .gain_v = 0x181,
242 .gain_y = 0x140,
243 .black_level = 0x3e,
244 .blank_level = 0x3e,
245 .m_control = 0<<2 | 1<<1,
246 .bstamp_wss_data = 0x42,
247 .s_carr = 0x2a098acb,
248 .l21__wc_ctl = 0<<13 | 0x16<<8 | 0<<0,
249 .savid__eavid = 0x06A70108,
250 .flen__fal = 23<<16 | 624<<0,
251 .lal__phase_reset = 2<<17 | 310<<0,
252 .hs_int_start_stop_x = 0x00920358,
253 .hs_ext_start_stop_x = 0x000F035F,
254 .vs_int_start_x = 0x1a7<<16,
255 .vs_int_stop_x__vs_int_start_y = 0x000601A7,
256 .vs_int_stop_y__vs_ext_start_x = 0x01AF0036,
257 .vs_ext_stop_x__vs_ext_start_y = 0x27101af,
258 .vs_ext_stop_y = 0x05,
259 .avid_start_stop_x = 0x03530082,
260 .avid_start_stop_y = 0x0270002E,
261 .fid_int_start_x__fid_int_start_y = 0x0005008A,
262 .fid_int_offset_y__fid_ext_start_x = 0x002E0138,
263 .fid_ext_start_y__fid_ext_offset_y = 0x01380005,
264};
265
266const struct omap_video_timings omap_dss_pal_timings = {
267 .x_res = 720,
268 .y_res = 574,
269 .pixelclock = 13500000,
270 .hsw = 64,
271 .hfp = 12,
272 .hbp = 68,
273 .vsw = 5,
274 .vfp = 5,
275 .vbp = 41,
276
277 .interlace = true,
278
279 .hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
280 .vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
281 .data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
282 .de_level = OMAPDSS_SIG_ACTIVE_HIGH,
283 .sync_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE,
284};
285EXPORT_SYMBOL(omap_dss_pal_timings);
286
287const struct omap_video_timings omap_dss_ntsc_timings = {
288 .x_res = 720,
289 .y_res = 482,
290 .pixelclock = 13500000,
291 .hsw = 64,
292 .hfp = 16,
293 .hbp = 58,
294 .vsw = 6,
295 .vfp = 6,
296 .vbp = 31,
297
298 .interlace = true,
299
300 .hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
301 .vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
302 .data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
303 .de_level = OMAPDSS_SIG_ACTIVE_HIGH,
304 .sync_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE,
305};
306EXPORT_SYMBOL(omap_dss_ntsc_timings);
307
308static struct {
309 struct platform_device *pdev;
310 void __iomem *base;
311 struct mutex venc_lock;
312 u32 wss_data;
313 struct regulator *vdda_dac_reg;
314
315 struct clk *tv_dac_clk;
316
317 struct omap_video_timings timings;
318 enum omap_dss_venc_type type;
319 bool invert_polarity;
320
321 struct omap_dss_device output;
322} venc;
323
324static inline void venc_write_reg(int idx, u32 val)
325{
326 __raw_writel(val, venc.base + idx);
327}
328
329static inline u32 venc_read_reg(int idx)
330{
331 u32 l = __raw_readl(venc.base + idx);
332 return l;
333}
334
335static void venc_write_config(const struct venc_config *config)
336{
337 DSSDBG("write venc conf\n");
338
339 venc_write_reg(VENC_LLEN, config->llen);
340 venc_write_reg(VENC_FLENS, config->flens);
341 venc_write_reg(VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr);
342 venc_write_reg(VENC_C_PHASE, config->c_phase);
343 venc_write_reg(VENC_GAIN_U, config->gain_u);
344 venc_write_reg(VENC_GAIN_V, config->gain_v);
345 venc_write_reg(VENC_GAIN_Y, config->gain_y);
346 venc_write_reg(VENC_BLACK_LEVEL, config->black_level);
347 venc_write_reg(VENC_BLANK_LEVEL, config->blank_level);
348 venc_write_reg(VENC_M_CONTROL, config->m_control);
349 venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data |
350 venc.wss_data);
351 venc_write_reg(VENC_S_CARR, config->s_carr);
352 venc_write_reg(VENC_L21__WC_CTL, config->l21__wc_ctl);
353 venc_write_reg(VENC_SAVID__EAVID, config->savid__eavid);
354 venc_write_reg(VENC_FLEN__FAL, config->flen__fal);
355 venc_write_reg(VENC_LAL__PHASE_RESET, config->lal__phase_reset);
356 venc_write_reg(VENC_HS_INT_START_STOP_X, config->hs_int_start_stop_x);
357 venc_write_reg(VENC_HS_EXT_START_STOP_X, config->hs_ext_start_stop_x);
358 venc_write_reg(VENC_VS_INT_START_X, config->vs_int_start_x);
359 venc_write_reg(VENC_VS_INT_STOP_X__VS_INT_START_Y,
360 config->vs_int_stop_x__vs_int_start_y);
361 venc_write_reg(VENC_VS_INT_STOP_Y__VS_EXT_START_X,
362 config->vs_int_stop_y__vs_ext_start_x);
363 venc_write_reg(VENC_VS_EXT_STOP_X__VS_EXT_START_Y,
364 config->vs_ext_stop_x__vs_ext_start_y);
365 venc_write_reg(VENC_VS_EXT_STOP_Y, config->vs_ext_stop_y);
366 venc_write_reg(VENC_AVID_START_STOP_X, config->avid_start_stop_x);
367 venc_write_reg(VENC_AVID_START_STOP_Y, config->avid_start_stop_y);
368 venc_write_reg(VENC_FID_INT_START_X__FID_INT_START_Y,
369 config->fid_int_start_x__fid_int_start_y);
370 venc_write_reg(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X,
371 config->fid_int_offset_y__fid_ext_start_x);
372 venc_write_reg(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y,
373 config->fid_ext_start_y__fid_ext_offset_y);
374
375 venc_write_reg(VENC_DAC_B__DAC_C, venc_read_reg(VENC_DAC_B__DAC_C));
376 venc_write_reg(VENC_VIDOUT_CTRL, config->vidout_ctrl);
377 venc_write_reg(VENC_HFLTR_CTRL, config->hfltr_ctrl);
378 venc_write_reg(VENC_X_COLOR, config->x_color);
379 venc_write_reg(VENC_LINE21, config->line21);
380 venc_write_reg(VENC_LN_SEL, config->ln_sel);
381 venc_write_reg(VENC_HTRIGGER_VTRIGGER, config->htrigger_vtrigger);
382 venc_write_reg(VENC_TVDETGP_INT_START_STOP_X,
383 config->tvdetgp_int_start_stop_x);
384 venc_write_reg(VENC_TVDETGP_INT_START_STOP_Y,
385 config->tvdetgp_int_start_stop_y);
386 venc_write_reg(VENC_GEN_CTRL, config->gen_ctrl);
387 venc_write_reg(VENC_F_CONTROL, config->f_control);
388 venc_write_reg(VENC_SYNC_CTRL, config->sync_ctrl);
389}
390
391static void venc_reset(void)
392{
393 int t = 1000;
394
395 venc_write_reg(VENC_F_CONTROL, 1<<8);
396 while (venc_read_reg(VENC_F_CONTROL) & (1<<8)) {
397 if (--t == 0) {
398 DSSERR("Failed to reset venc\n");
399 return;
400 }
401 }
402
403#ifdef CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET
404 /* the magical sleep that makes things work */
405 /* XXX more info? What bug this circumvents? */
406 msleep(20);
407#endif
408}
409
410static int venc_runtime_get(void)
411{
412 int r;
413
414 DSSDBG("venc_runtime_get\n");
415
416 r = pm_runtime_get_sync(&venc.pdev->dev);
417 WARN_ON(r < 0);
418 return r < 0 ? r : 0;
419}
420
421static void venc_runtime_put(void)
422{
423 int r;
424
425 DSSDBG("venc_runtime_put\n");
426
427 r = pm_runtime_put_sync(&venc.pdev->dev);
428 WARN_ON(r < 0 && r != -ENOSYS);
429}
430
431static const struct venc_config *venc_timings_to_config(
432 struct omap_video_timings *timings)
433{
434 if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0)
435 return &venc_config_pal_trm;
436
437 if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0)
438 return &venc_config_ntsc_trm;
439
440 BUG();
441 return NULL;
442}
443
444static int venc_power_on(struct omap_dss_device *dssdev)
445{
446 enum omap_channel channel = dssdev->dispc_channel;
447 u32 l;
448 int r;
449
450 r = venc_runtime_get();
451 if (r)
452 goto err0;
453
454 venc_reset();
455 venc_write_config(venc_timings_to_config(&venc.timings));
456
457 dss_set_venc_output(venc.type);
458 dss_set_dac_pwrdn_bgz(1);
459
460 l = 0;
461
462 if (venc.type == OMAP_DSS_VENC_TYPE_COMPOSITE)
463 l |= 1 << 1;
464 else /* S-Video */
465 l |= (1 << 0) | (1 << 2);
466
467 if (venc.invert_polarity == false)
468 l |= 1 << 3;
469
470 venc_write_reg(VENC_OUTPUT_CONTROL, l);
471
472 dss_mgr_set_timings(channel, &venc.timings);
473
474 r = regulator_enable(venc.vdda_dac_reg);
475 if (r)
476 goto err1;
477
478 r = dss_mgr_enable(channel);
479 if (r)
480 goto err2;
481
482 return 0;
483
484err2:
485 regulator_disable(venc.vdda_dac_reg);
486err1:
487 venc_write_reg(VENC_OUTPUT_CONTROL, 0);
488 dss_set_dac_pwrdn_bgz(0);
489
490 venc_runtime_put();
491err0:
492 return r;
493}
494
495static void venc_power_off(struct omap_dss_device *dssdev)
496{
497 enum omap_channel channel = dssdev->dispc_channel;
498
499 venc_write_reg(VENC_OUTPUT_CONTROL, 0);
500 dss_set_dac_pwrdn_bgz(0);
501
502 dss_mgr_disable(channel);
503
504 regulator_disable(venc.vdda_dac_reg);
505
506 venc_runtime_put();
507}
508
509static int venc_display_enable(struct omap_dss_device *dssdev)
510{
511 struct omap_dss_device *out = &venc.output;
512 int r;
513
514 DSSDBG("venc_display_enable\n");
515
516 mutex_lock(&venc.venc_lock);
517
518 if (!out->dispc_channel_connected) {
519 DSSERR("Failed to enable display: no output/manager\n");
520 r = -ENODEV;
521 goto err0;
522 }
523
524 r = venc_power_on(dssdev);
525 if (r)
526 goto err0;
527
528 venc.wss_data = 0;
529
530 mutex_unlock(&venc.venc_lock);
531
532 return 0;
533err0:
534 mutex_unlock(&venc.venc_lock);
535 return r;
536}
537
538static void venc_display_disable(struct omap_dss_device *dssdev)
539{
540 DSSDBG("venc_display_disable\n");
541
542 mutex_lock(&venc.venc_lock);
543
544 venc_power_off(dssdev);
545
546 mutex_unlock(&venc.venc_lock);
547}
548
549static void venc_set_timings(struct omap_dss_device *dssdev,
550 struct omap_video_timings *timings)
551{
552 DSSDBG("venc_set_timings\n");
553
554 mutex_lock(&venc.venc_lock);
555
556 /* Reset WSS data when the TV standard changes. */
557 if (memcmp(&venc.timings, timings, sizeof(*timings)))
558 venc.wss_data = 0;
559
560 venc.timings = *timings;
561
562 dispc_set_tv_pclk(13500000);
563
564 mutex_unlock(&venc.venc_lock);
565}
566
567static int venc_check_timings(struct omap_dss_device *dssdev,
568 struct omap_video_timings *timings)
569{
570 DSSDBG("venc_check_timings\n");
571
572 if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0)
573 return 0;
574
575 if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0)
576 return 0;
577
578 return -EINVAL;
579}
580
581static void venc_get_timings(struct omap_dss_device *dssdev,
582 struct omap_video_timings *timings)
583{
584 mutex_lock(&venc.venc_lock);
585
586 *timings = venc.timings;
587
588 mutex_unlock(&venc.venc_lock);
589}
590
591static u32 venc_get_wss(struct omap_dss_device *dssdev)
592{
593 /* Invert due to VENC_L21_WC_CTL:INV=1 */
594 return (venc.wss_data >> 8) ^ 0xfffff;
595}
596
597static int venc_set_wss(struct omap_dss_device *dssdev, u32 wss)
598{
599 const struct venc_config *config;
600 int r;
601
602 DSSDBG("venc_set_wss\n");
603
604 mutex_lock(&venc.venc_lock);
605
606 config = venc_timings_to_config(&venc.timings);
607
608 /* Invert due to VENC_L21_WC_CTL:INV=1 */
609 venc.wss_data = (wss ^ 0xfffff) << 8;
610
611 r = venc_runtime_get();
612 if (r)
613 goto err;
614
615 venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data |
616 venc.wss_data);
617
618 venc_runtime_put();
619
620err:
621 mutex_unlock(&venc.venc_lock);
622
623 return r;
624}
625
626static void venc_set_type(struct omap_dss_device *dssdev,
627 enum omap_dss_venc_type type)
628{
629 mutex_lock(&venc.venc_lock);
630
631 venc.type = type;
632
633 mutex_unlock(&venc.venc_lock);
634}
635
636static void venc_invert_vid_out_polarity(struct omap_dss_device *dssdev,
637 bool invert_polarity)
638{
639 mutex_lock(&venc.venc_lock);
640
641 venc.invert_polarity = invert_polarity;
642
643 mutex_unlock(&venc.venc_lock);
644}
645
646static int venc_init_regulator(void)
647{
648 struct regulator *vdda_dac;
649
650 if (venc.vdda_dac_reg != NULL)
651 return 0;
652
653 if (venc.pdev->dev.of_node)
654 vdda_dac = devm_regulator_get(&venc.pdev->dev, "vdda");
655 else
656 vdda_dac = devm_regulator_get(&venc.pdev->dev, "vdda_dac");
657
658 if (IS_ERR(vdda_dac)) {
659 if (PTR_ERR(vdda_dac) != -EPROBE_DEFER)
660 DSSERR("can't get VDDA_DAC regulator\n");
661 return PTR_ERR(vdda_dac);
662 }
663
664 venc.vdda_dac_reg = vdda_dac;
665
666 return 0;
667}
668
669static void venc_dump_regs(struct seq_file *s)
670{
671#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, venc_read_reg(r))
672
673 if (venc_runtime_get())
674 return;
675
676 DUMPREG(VENC_F_CONTROL);
677 DUMPREG(VENC_VIDOUT_CTRL);
678 DUMPREG(VENC_SYNC_CTRL);
679 DUMPREG(VENC_LLEN);
680 DUMPREG(VENC_FLENS);
681 DUMPREG(VENC_HFLTR_CTRL);
682 DUMPREG(VENC_CC_CARR_WSS_CARR);
683 DUMPREG(VENC_C_PHASE);
684 DUMPREG(VENC_GAIN_U);
685 DUMPREG(VENC_GAIN_V);
686 DUMPREG(VENC_GAIN_Y);
687 DUMPREG(VENC_BLACK_LEVEL);
688 DUMPREG(VENC_BLANK_LEVEL);
689 DUMPREG(VENC_X_COLOR);
690 DUMPREG(VENC_M_CONTROL);
691 DUMPREG(VENC_BSTAMP_WSS_DATA);
692 DUMPREG(VENC_S_CARR);
693 DUMPREG(VENC_LINE21);
694 DUMPREG(VENC_LN_SEL);
695 DUMPREG(VENC_L21__WC_CTL);
696 DUMPREG(VENC_HTRIGGER_VTRIGGER);
697 DUMPREG(VENC_SAVID__EAVID);
698 DUMPREG(VENC_FLEN__FAL);
699 DUMPREG(VENC_LAL__PHASE_RESET);
700 DUMPREG(VENC_HS_INT_START_STOP_X);
701 DUMPREG(VENC_HS_EXT_START_STOP_X);
702 DUMPREG(VENC_VS_INT_START_X);
703 DUMPREG(VENC_VS_INT_STOP_X__VS_INT_START_Y);
704 DUMPREG(VENC_VS_INT_STOP_Y__VS_EXT_START_X);
705 DUMPREG(VENC_VS_EXT_STOP_X__VS_EXT_START_Y);
706 DUMPREG(VENC_VS_EXT_STOP_Y);
707 DUMPREG(VENC_AVID_START_STOP_X);
708 DUMPREG(VENC_AVID_START_STOP_Y);
709 DUMPREG(VENC_FID_INT_START_X__FID_INT_START_Y);
710 DUMPREG(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X);
711 DUMPREG(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y);
712 DUMPREG(VENC_TVDETGP_INT_START_STOP_X);
713 DUMPREG(VENC_TVDETGP_INT_START_STOP_Y);
714 DUMPREG(VENC_GEN_CTRL);
715 DUMPREG(VENC_OUTPUT_CONTROL);
716 DUMPREG(VENC_OUTPUT_TEST);
717
718 venc_runtime_put();
719
720#undef DUMPREG
721}
722
723static int venc_get_clocks(struct platform_device *pdev)
724{
725 struct clk *clk;
726
727 if (dss_has_feature(FEAT_VENC_REQUIRES_TV_DAC_CLK)) {
728 clk = devm_clk_get(&pdev->dev, "tv_dac_clk");
729 if (IS_ERR(clk)) {
730 DSSERR("can't get tv_dac_clk\n");
731 return PTR_ERR(clk);
732 }
733 } else {
734 clk = NULL;
735 }
736
737 venc.tv_dac_clk = clk;
738
739 return 0;
740}
741
742static int venc_connect(struct omap_dss_device *dssdev,
743 struct omap_dss_device *dst)
744{
745 enum omap_channel channel = dssdev->dispc_channel;
746 int r;
747
748 r = venc_init_regulator();
749 if (r)
750 return r;
751
752 r = dss_mgr_connect(channel, dssdev);
753 if (r)
754 return r;
755
756 r = omapdss_output_set_device(dssdev, dst);
757 if (r) {
758 DSSERR("failed to connect output to new device: %s\n",
759 dst->name);
760 dss_mgr_disconnect(channel, dssdev);
761 return r;
762 }
763
764 return 0;
765}
766
767static void venc_disconnect(struct omap_dss_device *dssdev,
768 struct omap_dss_device *dst)
769{
770 enum omap_channel channel = dssdev->dispc_channel;
771
772 WARN_ON(dst != dssdev->dst);
773
774 if (dst != dssdev->dst)
775 return;
776
777 omapdss_output_unset_device(dssdev);
778
779 dss_mgr_disconnect(channel, dssdev);
780}
781
782static const struct omapdss_atv_ops venc_ops = {
783 .connect = venc_connect,
784 .disconnect = venc_disconnect,
785
786 .enable = venc_display_enable,
787 .disable = venc_display_disable,
788
789 .check_timings = venc_check_timings,
790 .set_timings = venc_set_timings,
791 .get_timings = venc_get_timings,
792
793 .set_type = venc_set_type,
794 .invert_vid_out_polarity = venc_invert_vid_out_polarity,
795
796 .set_wss = venc_set_wss,
797 .get_wss = venc_get_wss,
798};
799
800static void venc_init_output(struct platform_device *pdev)
801{
802 struct omap_dss_device *out = &venc.output;
803
804 out->dev = &pdev->dev;
805 out->id = OMAP_DSS_OUTPUT_VENC;
806 out->output_type = OMAP_DISPLAY_TYPE_VENC;
807 out->name = "venc.0";
808 out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT;
809 out->ops.atv = &venc_ops;
810 out->owner = THIS_MODULE;
811
812 omapdss_register_output(out);
813}
814
815static void venc_uninit_output(struct platform_device *pdev)
816{
817 struct omap_dss_device *out = &venc.output;
818
819 omapdss_unregister_output(out);
820}
821
822static int venc_probe_of(struct platform_device *pdev)
823{
824 struct device_node *node = pdev->dev.of_node;
825 struct device_node *ep;
826 u32 channels;
827 int r;
828
829 ep = omapdss_of_get_first_endpoint(node);
830 if (!ep)
831 return 0;
832
833 venc.invert_polarity = of_property_read_bool(ep, "ti,invert-polarity");
834
835 r = of_property_read_u32(ep, "ti,channels", &channels);
836 if (r) {
837 dev_err(&pdev->dev,
838 "failed to read property 'ti,channels': %d\n", r);
839 goto err;
840 }
841
842 switch (channels) {
843 case 1:
844 venc.type = OMAP_DSS_VENC_TYPE_COMPOSITE;
845 break;
846 case 2:
847 venc.type = OMAP_DSS_VENC_TYPE_SVIDEO;
848 break;
849 default:
850 dev_err(&pdev->dev, "bad channel propert '%d'\n", channels);
851 r = -EINVAL;
852 goto err;
853 }
854
855 of_node_put(ep);
856
857 return 0;
858err:
859 of_node_put(ep);
860
861 return 0;
862}
863
864/* VENC HW IP initialisation */
865static int venc_bind(struct device *dev, struct device *master, void *data)
866{
867 struct platform_device *pdev = to_platform_device(dev);
868 u8 rev_id;
869 struct resource *venc_mem;
870 int r;
871
872 venc.pdev = pdev;
873
874 mutex_init(&venc.venc_lock);
875
876 venc.wss_data = 0;
877
878 venc_mem = platform_get_resource(venc.pdev, IORESOURCE_MEM, 0);
879 if (!venc_mem) {
880 DSSERR("can't get IORESOURCE_MEM VENC\n");
881 return -EINVAL;
882 }
883
884 venc.base = devm_ioremap(&pdev->dev, venc_mem->start,
885 resource_size(venc_mem));
886 if (!venc.base) {
887 DSSERR("can't ioremap VENC\n");
888 return -ENOMEM;
889 }
890
891 r = venc_get_clocks(pdev);
892 if (r)
893 return r;
894
895 pm_runtime_enable(&pdev->dev);
896
897 r = venc_runtime_get();
898 if (r)
899 goto err_runtime_get;
900
901 rev_id = (u8)(venc_read_reg(VENC_REV_ID) & 0xff);
902 dev_dbg(&pdev->dev, "OMAP VENC rev %d\n", rev_id);
903
904 venc_runtime_put();
905
906 if (pdev->dev.of_node) {
907 r = venc_probe_of(pdev);
908 if (r) {
909 DSSERR("Invalid DT data\n");
910 goto err_probe_of;
911 }
912 }
913
914 dss_debugfs_create_file("venc", venc_dump_regs);
915
916 venc_init_output(pdev);
917
918 return 0;
919
920err_probe_of:
921err_runtime_get:
922 pm_runtime_disable(&pdev->dev);
923 return r;
924}
925
926static void venc_unbind(struct device *dev, struct device *master, void *data)
927{
928 struct platform_device *pdev = to_platform_device(dev);
929
930 venc_uninit_output(pdev);
931
932 pm_runtime_disable(&pdev->dev);
933}
934
935static const struct component_ops venc_component_ops = {
936 .bind = venc_bind,
937 .unbind = venc_unbind,
938};
939
940static int venc_probe(struct platform_device *pdev)
941{
942 return component_add(&pdev->dev, &venc_component_ops);
943}
944
945static int venc_remove(struct platform_device *pdev)
946{
947 component_del(&pdev->dev, &venc_component_ops);
948 return 0;
949}
950
951static int venc_runtime_suspend(struct device *dev)
952{
953 if (venc.tv_dac_clk)
954 clk_disable_unprepare(venc.tv_dac_clk);
955
956 dispc_runtime_put();
957
958 return 0;
959}
960
961static int venc_runtime_resume(struct device *dev)
962{
963 int r;
964
965 r = dispc_runtime_get();
966 if (r < 0)
967 return r;
968
969 if (venc.tv_dac_clk)
970 clk_prepare_enable(venc.tv_dac_clk);
971
972 return 0;
973}
974
975static const struct dev_pm_ops venc_pm_ops = {
976 .runtime_suspend = venc_runtime_suspend,
977 .runtime_resume = venc_runtime_resume,
978};
979
980static const struct of_device_id venc_of_match[] = {
981 { .compatible = "ti,omap2-venc", },
982 { .compatible = "ti,omap3-venc", },
983 { .compatible = "ti,omap4-venc", },
984 {},
985};
986
987static struct platform_driver omap_venchw_driver = {
988 .probe = venc_probe,
989 .remove = venc_remove,
990 .driver = {
991 .name = "omapdss_venc",
992 .pm = &venc_pm_ops,
993 .of_match_table = venc_of_match,
994 .suppress_bind_attrs = true,
995 },
996};
997
998int __init venc_init_platform_driver(void)
999{
1000 return platform_driver_register(&omap_venchw_driver);
1001}
1002
1003void venc_uninit_platform_driver(void)
1004{
1005 platform_driver_unregister(&omap_venchw_driver);
1006}
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2009 Nokia Corporation
4 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
5 *
6 * VENC settings from TI's DSS driver
7 */
8
9#define DSS_SUBSYS_NAME "VENC"
10
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/clk.h>
14#include <linux/err.h>
15#include <linux/io.h>
16#include <linux/completion.h>
17#include <linux/delay.h>
18#include <linux/string.h>
19#include <linux/seq_file.h>
20#include <linux/platform_device.h>
21#include <linux/regulator/consumer.h>
22#include <linux/pm_runtime.h>
23#include <linux/of.h>
24#include <linux/of_graph.h>
25#include <linux/component.h>
26#include <linux/sys_soc.h>
27
28#include <drm/drm_bridge.h>
29
30#include "omapdss.h"
31#include "dss.h"
32
33/* Venc registers */
34#define VENC_REV_ID 0x00
35#define VENC_STATUS 0x04
36#define VENC_F_CONTROL 0x08
37#define VENC_VIDOUT_CTRL 0x10
38#define VENC_SYNC_CTRL 0x14
39#define VENC_LLEN 0x1C
40#define VENC_FLENS 0x20
41#define VENC_HFLTR_CTRL 0x24
42#define VENC_CC_CARR_WSS_CARR 0x28
43#define VENC_C_PHASE 0x2C
44#define VENC_GAIN_U 0x30
45#define VENC_GAIN_V 0x34
46#define VENC_GAIN_Y 0x38
47#define VENC_BLACK_LEVEL 0x3C
48#define VENC_BLANK_LEVEL 0x40
49#define VENC_X_COLOR 0x44
50#define VENC_M_CONTROL 0x48
51#define VENC_BSTAMP_WSS_DATA 0x4C
52#define VENC_S_CARR 0x50
53#define VENC_LINE21 0x54
54#define VENC_LN_SEL 0x58
55#define VENC_L21__WC_CTL 0x5C
56#define VENC_HTRIGGER_VTRIGGER 0x60
57#define VENC_SAVID__EAVID 0x64
58#define VENC_FLEN__FAL 0x68
59#define VENC_LAL__PHASE_RESET 0x6C
60#define VENC_HS_INT_START_STOP_X 0x70
61#define VENC_HS_EXT_START_STOP_X 0x74
62#define VENC_VS_INT_START_X 0x78
63#define VENC_VS_INT_STOP_X__VS_INT_START_Y 0x7C
64#define VENC_VS_INT_STOP_Y__VS_EXT_START_X 0x80
65#define VENC_VS_EXT_STOP_X__VS_EXT_START_Y 0x84
66#define VENC_VS_EXT_STOP_Y 0x88
67#define VENC_AVID_START_STOP_X 0x90
68#define VENC_AVID_START_STOP_Y 0x94
69#define VENC_FID_INT_START_X__FID_INT_START_Y 0xA0
70#define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X 0xA4
71#define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y 0xA8
72#define VENC_TVDETGP_INT_START_STOP_X 0xB0
73#define VENC_TVDETGP_INT_START_STOP_Y 0xB4
74#define VENC_GEN_CTRL 0xB8
75#define VENC_OUTPUT_CONTROL 0xC4
76#define VENC_OUTPUT_TEST 0xC8
77#define VENC_DAC_B__DAC_C 0xC8
78
79struct venc_config {
80 u32 f_control;
81 u32 vidout_ctrl;
82 u32 sync_ctrl;
83 u32 llen;
84 u32 flens;
85 u32 hfltr_ctrl;
86 u32 cc_carr_wss_carr;
87 u32 c_phase;
88 u32 gain_u;
89 u32 gain_v;
90 u32 gain_y;
91 u32 black_level;
92 u32 blank_level;
93 u32 x_color;
94 u32 m_control;
95 u32 bstamp_wss_data;
96 u32 s_carr;
97 u32 line21;
98 u32 ln_sel;
99 u32 l21__wc_ctl;
100 u32 htrigger_vtrigger;
101 u32 savid__eavid;
102 u32 flen__fal;
103 u32 lal__phase_reset;
104 u32 hs_int_start_stop_x;
105 u32 hs_ext_start_stop_x;
106 u32 vs_int_start_x;
107 u32 vs_int_stop_x__vs_int_start_y;
108 u32 vs_int_stop_y__vs_ext_start_x;
109 u32 vs_ext_stop_x__vs_ext_start_y;
110 u32 vs_ext_stop_y;
111 u32 avid_start_stop_x;
112 u32 avid_start_stop_y;
113 u32 fid_int_start_x__fid_int_start_y;
114 u32 fid_int_offset_y__fid_ext_start_x;
115 u32 fid_ext_start_y__fid_ext_offset_y;
116 u32 tvdetgp_int_start_stop_x;
117 u32 tvdetgp_int_start_stop_y;
118 u32 gen_ctrl;
119};
120
121/* from TRM */
122static const struct venc_config venc_config_pal_trm = {
123 .f_control = 0,
124 .vidout_ctrl = 1,
125 .sync_ctrl = 0x40,
126 .llen = 0x35F, /* 863 */
127 .flens = 0x270, /* 624 */
128 .hfltr_ctrl = 0,
129 .cc_carr_wss_carr = 0x2F7225ED,
130 .c_phase = 0,
131 .gain_u = 0x111,
132 .gain_v = 0x181,
133 .gain_y = 0x140,
134 .black_level = 0x3B,
135 .blank_level = 0x3B,
136 .x_color = 0x7,
137 .m_control = 0x2,
138 .bstamp_wss_data = 0x3F,
139 .s_carr = 0x2A098ACB,
140 .line21 = 0,
141 .ln_sel = 0x01290015,
142 .l21__wc_ctl = 0x0000F603,
143 .htrigger_vtrigger = 0,
144
145 .savid__eavid = 0x06A70108,
146 .flen__fal = 0x00180270,
147 .lal__phase_reset = 0x00040135,
148 .hs_int_start_stop_x = 0x00880358,
149 .hs_ext_start_stop_x = 0x000F035F,
150 .vs_int_start_x = 0x01A70000,
151 .vs_int_stop_x__vs_int_start_y = 0x000001A7,
152 .vs_int_stop_y__vs_ext_start_x = 0x01AF0000,
153 .vs_ext_stop_x__vs_ext_start_y = 0x000101AF,
154 .vs_ext_stop_y = 0x00000025,
155 .avid_start_stop_x = 0x03530083,
156 .avid_start_stop_y = 0x026C002E,
157 .fid_int_start_x__fid_int_start_y = 0x0001008A,
158 .fid_int_offset_y__fid_ext_start_x = 0x002E0138,
159 .fid_ext_start_y__fid_ext_offset_y = 0x01380001,
160
161 .tvdetgp_int_start_stop_x = 0x00140001,
162 .tvdetgp_int_start_stop_y = 0x00010001,
163 .gen_ctrl = 0x00FF0000,
164};
165
166/* from TRM */
167static const struct venc_config venc_config_ntsc_trm = {
168 .f_control = 0,
169 .vidout_ctrl = 1,
170 .sync_ctrl = 0x8040,
171 .llen = 0x359,
172 .flens = 0x20C,
173 .hfltr_ctrl = 0,
174 .cc_carr_wss_carr = 0x043F2631,
175 .c_phase = 0,
176 .gain_u = 0x102,
177 .gain_v = 0x16C,
178 .gain_y = 0x12F,
179 .black_level = 0x43,
180 .blank_level = 0x38,
181 .x_color = 0x7,
182 .m_control = 0x1,
183 .bstamp_wss_data = 0x38,
184 .s_carr = 0x21F07C1F,
185 .line21 = 0,
186 .ln_sel = 0x01310011,
187 .l21__wc_ctl = 0x0000F003,
188 .htrigger_vtrigger = 0,
189
190 .savid__eavid = 0x069300F4,
191 .flen__fal = 0x0016020C,
192 .lal__phase_reset = 0x00060107,
193 .hs_int_start_stop_x = 0x008E0350,
194 .hs_ext_start_stop_x = 0x000F0359,
195 .vs_int_start_x = 0x01A00000,
196 .vs_int_stop_x__vs_int_start_y = 0x020701A0,
197 .vs_int_stop_y__vs_ext_start_x = 0x01AC0024,
198 .vs_ext_stop_x__vs_ext_start_y = 0x020D01AC,
199 .vs_ext_stop_y = 0x00000006,
200 .avid_start_stop_x = 0x03480078,
201 .avid_start_stop_y = 0x02060024,
202 .fid_int_start_x__fid_int_start_y = 0x0001008A,
203 .fid_int_offset_y__fid_ext_start_x = 0x01AC0106,
204 .fid_ext_start_y__fid_ext_offset_y = 0x01060006,
205
206 .tvdetgp_int_start_stop_x = 0x00140001,
207 .tvdetgp_int_start_stop_y = 0x00010001,
208 .gen_ctrl = 0x00F90000,
209};
210
211enum venc_videomode {
212 VENC_MODE_UNKNOWN,
213 VENC_MODE_PAL,
214 VENC_MODE_NTSC,
215};
216
217static const struct drm_display_mode omap_dss_pal_mode = {
218 .hdisplay = 720,
219 .hsync_start = 732,
220 .hsync_end = 796,
221 .htotal = 864,
222 .vdisplay = 574,
223 .vsync_start = 579,
224 .vsync_end = 584,
225 .vtotal = 625,
226 .clock = 13500,
227
228 .flags = DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_NHSYNC |
229 DRM_MODE_FLAG_NVSYNC,
230};
231
232static const struct drm_display_mode omap_dss_ntsc_mode = {
233 .hdisplay = 720,
234 .hsync_start = 736,
235 .hsync_end = 800,
236 .htotal = 858,
237 .vdisplay = 482,
238 .vsync_start = 488,
239 .vsync_end = 494,
240 .vtotal = 525,
241 .clock = 13500,
242
243 .flags = DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_NHSYNC |
244 DRM_MODE_FLAG_NVSYNC,
245};
246
247struct venc_device {
248 struct platform_device *pdev;
249 void __iomem *base;
250 struct regulator *vdda_dac_reg;
251 struct dss_device *dss;
252
253 struct dss_debugfs_entry *debugfs;
254
255 struct clk *tv_dac_clk;
256
257 const struct venc_config *config;
258 enum omap_dss_venc_type type;
259 bool invert_polarity;
260 bool requires_tv_dac_clk;
261
262 struct omap_dss_device output;
263 struct drm_bridge bridge;
264};
265
266#define drm_bridge_to_venc(b) container_of(b, struct venc_device, bridge)
267
268static inline void venc_write_reg(struct venc_device *venc, int idx, u32 val)
269{
270 __raw_writel(val, venc->base + idx);
271}
272
273static inline u32 venc_read_reg(struct venc_device *venc, int idx)
274{
275 u32 l = __raw_readl(venc->base + idx);
276 return l;
277}
278
279static void venc_write_config(struct venc_device *venc,
280 const struct venc_config *config)
281{
282 DSSDBG("write venc conf\n");
283
284 venc_write_reg(venc, VENC_LLEN, config->llen);
285 venc_write_reg(venc, VENC_FLENS, config->flens);
286 venc_write_reg(venc, VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr);
287 venc_write_reg(venc, VENC_C_PHASE, config->c_phase);
288 venc_write_reg(venc, VENC_GAIN_U, config->gain_u);
289 venc_write_reg(venc, VENC_GAIN_V, config->gain_v);
290 venc_write_reg(venc, VENC_GAIN_Y, config->gain_y);
291 venc_write_reg(venc, VENC_BLACK_LEVEL, config->black_level);
292 venc_write_reg(venc, VENC_BLANK_LEVEL, config->blank_level);
293 venc_write_reg(venc, VENC_M_CONTROL, config->m_control);
294 venc_write_reg(venc, VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data);
295 venc_write_reg(venc, VENC_S_CARR, config->s_carr);
296 venc_write_reg(venc, VENC_L21__WC_CTL, config->l21__wc_ctl);
297 venc_write_reg(venc, VENC_SAVID__EAVID, config->savid__eavid);
298 venc_write_reg(venc, VENC_FLEN__FAL, config->flen__fal);
299 venc_write_reg(venc, VENC_LAL__PHASE_RESET, config->lal__phase_reset);
300 venc_write_reg(venc, VENC_HS_INT_START_STOP_X,
301 config->hs_int_start_stop_x);
302 venc_write_reg(venc, VENC_HS_EXT_START_STOP_X,
303 config->hs_ext_start_stop_x);
304 venc_write_reg(venc, VENC_VS_INT_START_X, config->vs_int_start_x);
305 venc_write_reg(venc, VENC_VS_INT_STOP_X__VS_INT_START_Y,
306 config->vs_int_stop_x__vs_int_start_y);
307 venc_write_reg(venc, VENC_VS_INT_STOP_Y__VS_EXT_START_X,
308 config->vs_int_stop_y__vs_ext_start_x);
309 venc_write_reg(venc, VENC_VS_EXT_STOP_X__VS_EXT_START_Y,
310 config->vs_ext_stop_x__vs_ext_start_y);
311 venc_write_reg(venc, VENC_VS_EXT_STOP_Y, config->vs_ext_stop_y);
312 venc_write_reg(venc, VENC_AVID_START_STOP_X, config->avid_start_stop_x);
313 venc_write_reg(venc, VENC_AVID_START_STOP_Y, config->avid_start_stop_y);
314 venc_write_reg(venc, VENC_FID_INT_START_X__FID_INT_START_Y,
315 config->fid_int_start_x__fid_int_start_y);
316 venc_write_reg(venc, VENC_FID_INT_OFFSET_Y__FID_EXT_START_X,
317 config->fid_int_offset_y__fid_ext_start_x);
318 venc_write_reg(venc, VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y,
319 config->fid_ext_start_y__fid_ext_offset_y);
320
321 venc_write_reg(venc, VENC_DAC_B__DAC_C,
322 venc_read_reg(venc, VENC_DAC_B__DAC_C));
323 venc_write_reg(venc, VENC_VIDOUT_CTRL, config->vidout_ctrl);
324 venc_write_reg(venc, VENC_HFLTR_CTRL, config->hfltr_ctrl);
325 venc_write_reg(venc, VENC_X_COLOR, config->x_color);
326 venc_write_reg(venc, VENC_LINE21, config->line21);
327 venc_write_reg(venc, VENC_LN_SEL, config->ln_sel);
328 venc_write_reg(venc, VENC_HTRIGGER_VTRIGGER, config->htrigger_vtrigger);
329 venc_write_reg(venc, VENC_TVDETGP_INT_START_STOP_X,
330 config->tvdetgp_int_start_stop_x);
331 venc_write_reg(venc, VENC_TVDETGP_INT_START_STOP_Y,
332 config->tvdetgp_int_start_stop_y);
333 venc_write_reg(venc, VENC_GEN_CTRL, config->gen_ctrl);
334 venc_write_reg(venc, VENC_F_CONTROL, config->f_control);
335 venc_write_reg(venc, VENC_SYNC_CTRL, config->sync_ctrl);
336}
337
338static void venc_reset(struct venc_device *venc)
339{
340 int t = 1000;
341
342 venc_write_reg(venc, VENC_F_CONTROL, 1<<8);
343 while (venc_read_reg(venc, VENC_F_CONTROL) & (1<<8)) {
344 if (--t == 0) {
345 DSSERR("Failed to reset venc\n");
346 return;
347 }
348 }
349
350#ifdef CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET
351 /* the magical sleep that makes things work */
352 /* XXX more info? What bug this circumvents? */
353 msleep(20);
354#endif
355}
356
357static int venc_runtime_get(struct venc_device *venc)
358{
359 int r;
360
361 DSSDBG("venc_runtime_get\n");
362
363 r = pm_runtime_get_sync(&venc->pdev->dev);
364 WARN_ON(r < 0);
365 return r < 0 ? r : 0;
366}
367
368static void venc_runtime_put(struct venc_device *venc)
369{
370 int r;
371
372 DSSDBG("venc_runtime_put\n");
373
374 r = pm_runtime_put_sync(&venc->pdev->dev);
375 WARN_ON(r < 0 && r != -ENOSYS);
376}
377
378static int venc_power_on(struct venc_device *venc)
379{
380 u32 l;
381 int r;
382
383 r = venc_runtime_get(venc);
384 if (r)
385 goto err0;
386
387 venc_reset(venc);
388 venc_write_config(venc, venc->config);
389
390 dss_set_venc_output(venc->dss, venc->type);
391 dss_set_dac_pwrdn_bgz(venc->dss, 1);
392
393 l = 0;
394
395 if (venc->type == OMAP_DSS_VENC_TYPE_COMPOSITE)
396 l |= 1 << 1;
397 else /* S-Video */
398 l |= (1 << 0) | (1 << 2);
399
400 if (venc->invert_polarity == false)
401 l |= 1 << 3;
402
403 venc_write_reg(venc, VENC_OUTPUT_CONTROL, l);
404
405 r = regulator_enable(venc->vdda_dac_reg);
406 if (r)
407 goto err1;
408
409 r = dss_mgr_enable(&venc->output);
410 if (r)
411 goto err2;
412
413 return 0;
414
415err2:
416 regulator_disable(venc->vdda_dac_reg);
417err1:
418 venc_write_reg(venc, VENC_OUTPUT_CONTROL, 0);
419 dss_set_dac_pwrdn_bgz(venc->dss, 0);
420
421 venc_runtime_put(venc);
422err0:
423 return r;
424}
425
426static void venc_power_off(struct venc_device *venc)
427{
428 venc_write_reg(venc, VENC_OUTPUT_CONTROL, 0);
429 dss_set_dac_pwrdn_bgz(venc->dss, 0);
430
431 dss_mgr_disable(&venc->output);
432
433 regulator_disable(venc->vdda_dac_reg);
434
435 venc_runtime_put(venc);
436}
437
438static enum venc_videomode venc_get_videomode(const struct drm_display_mode *mode)
439{
440 if (!(mode->flags & DRM_MODE_FLAG_INTERLACE))
441 return VENC_MODE_UNKNOWN;
442
443 if (mode->clock == omap_dss_pal_mode.clock &&
444 mode->hdisplay == omap_dss_pal_mode.hdisplay &&
445 mode->vdisplay == omap_dss_pal_mode.vdisplay)
446 return VENC_MODE_PAL;
447
448 if (mode->clock == omap_dss_ntsc_mode.clock &&
449 mode->hdisplay == omap_dss_ntsc_mode.hdisplay &&
450 mode->vdisplay == omap_dss_ntsc_mode.vdisplay)
451 return VENC_MODE_NTSC;
452
453 return VENC_MODE_UNKNOWN;
454}
455
456static int venc_dump_regs(struct seq_file *s, void *p)
457{
458 struct venc_device *venc = s->private;
459
460#define DUMPREG(venc, r) \
461 seq_printf(s, "%-35s %08x\n", #r, venc_read_reg(venc, r))
462
463 if (venc_runtime_get(venc))
464 return 0;
465
466 DUMPREG(venc, VENC_F_CONTROL);
467 DUMPREG(venc, VENC_VIDOUT_CTRL);
468 DUMPREG(venc, VENC_SYNC_CTRL);
469 DUMPREG(venc, VENC_LLEN);
470 DUMPREG(venc, VENC_FLENS);
471 DUMPREG(venc, VENC_HFLTR_CTRL);
472 DUMPREG(venc, VENC_CC_CARR_WSS_CARR);
473 DUMPREG(venc, VENC_C_PHASE);
474 DUMPREG(venc, VENC_GAIN_U);
475 DUMPREG(venc, VENC_GAIN_V);
476 DUMPREG(venc, VENC_GAIN_Y);
477 DUMPREG(venc, VENC_BLACK_LEVEL);
478 DUMPREG(venc, VENC_BLANK_LEVEL);
479 DUMPREG(venc, VENC_X_COLOR);
480 DUMPREG(venc, VENC_M_CONTROL);
481 DUMPREG(venc, VENC_BSTAMP_WSS_DATA);
482 DUMPREG(venc, VENC_S_CARR);
483 DUMPREG(venc, VENC_LINE21);
484 DUMPREG(venc, VENC_LN_SEL);
485 DUMPREG(venc, VENC_L21__WC_CTL);
486 DUMPREG(venc, VENC_HTRIGGER_VTRIGGER);
487 DUMPREG(venc, VENC_SAVID__EAVID);
488 DUMPREG(venc, VENC_FLEN__FAL);
489 DUMPREG(venc, VENC_LAL__PHASE_RESET);
490 DUMPREG(venc, VENC_HS_INT_START_STOP_X);
491 DUMPREG(venc, VENC_HS_EXT_START_STOP_X);
492 DUMPREG(venc, VENC_VS_INT_START_X);
493 DUMPREG(venc, VENC_VS_INT_STOP_X__VS_INT_START_Y);
494 DUMPREG(venc, VENC_VS_INT_STOP_Y__VS_EXT_START_X);
495 DUMPREG(venc, VENC_VS_EXT_STOP_X__VS_EXT_START_Y);
496 DUMPREG(venc, VENC_VS_EXT_STOP_Y);
497 DUMPREG(venc, VENC_AVID_START_STOP_X);
498 DUMPREG(venc, VENC_AVID_START_STOP_Y);
499 DUMPREG(venc, VENC_FID_INT_START_X__FID_INT_START_Y);
500 DUMPREG(venc, VENC_FID_INT_OFFSET_Y__FID_EXT_START_X);
501 DUMPREG(venc, VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y);
502 DUMPREG(venc, VENC_TVDETGP_INT_START_STOP_X);
503 DUMPREG(venc, VENC_TVDETGP_INT_START_STOP_Y);
504 DUMPREG(venc, VENC_GEN_CTRL);
505 DUMPREG(venc, VENC_OUTPUT_CONTROL);
506 DUMPREG(venc, VENC_OUTPUT_TEST);
507
508 venc_runtime_put(venc);
509
510#undef DUMPREG
511 return 0;
512}
513
514static int venc_get_clocks(struct venc_device *venc)
515{
516 struct clk *clk;
517
518 if (venc->requires_tv_dac_clk) {
519 clk = devm_clk_get(&venc->pdev->dev, "tv_dac_clk");
520 if (IS_ERR(clk)) {
521 DSSERR("can't get tv_dac_clk\n");
522 return PTR_ERR(clk);
523 }
524 } else {
525 clk = NULL;
526 }
527
528 venc->tv_dac_clk = clk;
529
530 return 0;
531}
532
533/* -----------------------------------------------------------------------------
534 * DRM Bridge Operations
535 */
536
537static int venc_bridge_attach(struct drm_bridge *bridge,
538 enum drm_bridge_attach_flags flags)
539{
540 struct venc_device *venc = drm_bridge_to_venc(bridge);
541
542 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR))
543 return -EINVAL;
544
545 return drm_bridge_attach(bridge->encoder, venc->output.next_bridge,
546 bridge, flags);
547}
548
549static enum drm_mode_status
550venc_bridge_mode_valid(struct drm_bridge *bridge,
551 const struct drm_display_info *info,
552 const struct drm_display_mode *mode)
553{
554 switch (venc_get_videomode(mode)) {
555 case VENC_MODE_PAL:
556 case VENC_MODE_NTSC:
557 return MODE_OK;
558
559 default:
560 return MODE_BAD;
561 }
562}
563
564static bool venc_bridge_mode_fixup(struct drm_bridge *bridge,
565 const struct drm_display_mode *mode,
566 struct drm_display_mode *adjusted_mode)
567{
568 const struct drm_display_mode *venc_mode;
569
570 switch (venc_get_videomode(adjusted_mode)) {
571 case VENC_MODE_PAL:
572 venc_mode = &omap_dss_pal_mode;
573 break;
574
575 case VENC_MODE_NTSC:
576 venc_mode = &omap_dss_ntsc_mode;
577 break;
578
579 default:
580 return false;
581 }
582
583 drm_mode_copy(adjusted_mode, venc_mode);
584 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
585 drm_mode_set_name(adjusted_mode);
586
587 return true;
588}
589
590static void venc_bridge_mode_set(struct drm_bridge *bridge,
591 const struct drm_display_mode *mode,
592 const struct drm_display_mode *adjusted_mode)
593{
594 struct venc_device *venc = drm_bridge_to_venc(bridge);
595 enum venc_videomode venc_mode = venc_get_videomode(adjusted_mode);
596
597 switch (venc_mode) {
598 default:
599 WARN_ON_ONCE(1);
600 fallthrough;
601 case VENC_MODE_PAL:
602 venc->config = &venc_config_pal_trm;
603 break;
604
605 case VENC_MODE_NTSC:
606 venc->config = &venc_config_ntsc_trm;
607 break;
608 }
609
610 dispc_set_tv_pclk(venc->dss->dispc, 13500000);
611}
612
613static void venc_bridge_enable(struct drm_bridge *bridge)
614{
615 struct venc_device *venc = drm_bridge_to_venc(bridge);
616
617 venc_power_on(venc);
618}
619
620static void venc_bridge_disable(struct drm_bridge *bridge)
621{
622 struct venc_device *venc = drm_bridge_to_venc(bridge);
623
624 venc_power_off(venc);
625}
626
627static int venc_bridge_get_modes(struct drm_bridge *bridge,
628 struct drm_connector *connector)
629{
630 static const struct drm_display_mode *modes[] = {
631 &omap_dss_pal_mode,
632 &omap_dss_ntsc_mode,
633 };
634 unsigned int i;
635
636 for (i = 0; i < ARRAY_SIZE(modes); ++i) {
637 struct drm_display_mode *mode;
638
639 mode = drm_mode_duplicate(connector->dev, modes[i]);
640 if (!mode)
641 return i;
642
643 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
644 drm_mode_set_name(mode);
645 drm_mode_probed_add(connector, mode);
646 }
647
648 return ARRAY_SIZE(modes);
649}
650
651static const struct drm_bridge_funcs venc_bridge_funcs = {
652 .attach = venc_bridge_attach,
653 .mode_valid = venc_bridge_mode_valid,
654 .mode_fixup = venc_bridge_mode_fixup,
655 .mode_set = venc_bridge_mode_set,
656 .enable = venc_bridge_enable,
657 .disable = venc_bridge_disable,
658 .get_modes = venc_bridge_get_modes,
659};
660
661static void venc_bridge_init(struct venc_device *venc)
662{
663 venc->bridge.funcs = &venc_bridge_funcs;
664 venc->bridge.of_node = venc->pdev->dev.of_node;
665 venc->bridge.ops = DRM_BRIDGE_OP_MODES;
666 venc->bridge.type = DRM_MODE_CONNECTOR_SVIDEO;
667 venc->bridge.interlace_allowed = true;
668
669 drm_bridge_add(&venc->bridge);
670}
671
672static void venc_bridge_cleanup(struct venc_device *venc)
673{
674 drm_bridge_remove(&venc->bridge);
675}
676
677/* -----------------------------------------------------------------------------
678 * Component Bind & Unbind
679 */
680
681static int venc_bind(struct device *dev, struct device *master, void *data)
682{
683 struct dss_device *dss = dss_get_device(master);
684 struct venc_device *venc = dev_get_drvdata(dev);
685 u8 rev_id;
686 int r;
687
688 venc->dss = dss;
689
690 r = venc_runtime_get(venc);
691 if (r)
692 return r;
693
694 rev_id = (u8)(venc_read_reg(venc, VENC_REV_ID) & 0xff);
695 dev_dbg(dev, "OMAP VENC rev %d\n", rev_id);
696
697 venc_runtime_put(venc);
698
699 venc->debugfs = dss_debugfs_create_file(dss, "venc", venc_dump_regs,
700 venc);
701
702 return 0;
703}
704
705static void venc_unbind(struct device *dev, struct device *master, void *data)
706{
707 struct venc_device *venc = dev_get_drvdata(dev);
708
709 dss_debugfs_remove_file(venc->debugfs);
710}
711
712static const struct component_ops venc_component_ops = {
713 .bind = venc_bind,
714 .unbind = venc_unbind,
715};
716
717/* -----------------------------------------------------------------------------
718 * Probe & Remove, Suspend & Resume
719 */
720
721static int venc_init_output(struct venc_device *venc)
722{
723 struct omap_dss_device *out = &venc->output;
724 int r;
725
726 venc_bridge_init(venc);
727
728 out->dev = &venc->pdev->dev;
729 out->id = OMAP_DSS_OUTPUT_VENC;
730 out->type = OMAP_DISPLAY_TYPE_VENC;
731 out->name = "venc.0";
732 out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT;
733 out->owner = THIS_MODULE;
734 out->of_port = 0;
735 out->ops_flags = OMAP_DSS_DEVICE_OP_MODES;
736
737 r = omapdss_device_init_output(out, &venc->bridge);
738 if (r < 0) {
739 venc_bridge_cleanup(venc);
740 return r;
741 }
742
743 omapdss_device_register(out);
744
745 return 0;
746}
747
748static void venc_uninit_output(struct venc_device *venc)
749{
750 omapdss_device_unregister(&venc->output);
751 omapdss_device_cleanup_output(&venc->output);
752
753 venc_bridge_cleanup(venc);
754}
755
756static int venc_probe_of(struct venc_device *venc)
757{
758 struct device_node *node = venc->pdev->dev.of_node;
759 struct device_node *ep;
760 u32 channels;
761 int r;
762
763 ep = of_graph_get_endpoint_by_regs(node, 0, 0);
764 if (!ep)
765 return 0;
766
767 venc->invert_polarity = of_property_read_bool(ep, "ti,invert-polarity");
768
769 r = of_property_read_u32(ep, "ti,channels", &channels);
770 if (r) {
771 dev_err(&venc->pdev->dev,
772 "failed to read property 'ti,channels': %d\n", r);
773 goto err;
774 }
775
776 switch (channels) {
777 case 1:
778 venc->type = OMAP_DSS_VENC_TYPE_COMPOSITE;
779 break;
780 case 2:
781 venc->type = OMAP_DSS_VENC_TYPE_SVIDEO;
782 break;
783 default:
784 dev_err(&venc->pdev->dev, "bad channel propert '%d'\n",
785 channels);
786 r = -EINVAL;
787 goto err;
788 }
789
790 of_node_put(ep);
791
792 return 0;
793
794err:
795 of_node_put(ep);
796 return r;
797}
798
799static const struct soc_device_attribute venc_soc_devices[] = {
800 { .machine = "OMAP3[45]*" },
801 { .machine = "AM35*" },
802 { /* sentinel */ }
803};
804
805static int venc_probe(struct platform_device *pdev)
806{
807 struct venc_device *venc;
808 struct resource *venc_mem;
809 int r;
810
811 venc = kzalloc(sizeof(*venc), GFP_KERNEL);
812 if (!venc)
813 return -ENOMEM;
814
815 venc->pdev = pdev;
816
817 platform_set_drvdata(pdev, venc);
818
819 /* The OMAP34xx, OMAP35xx and AM35xx VENC require the TV DAC clock. */
820 if (soc_device_match(venc_soc_devices))
821 venc->requires_tv_dac_clk = true;
822
823 venc->config = &venc_config_pal_trm;
824
825 venc_mem = platform_get_resource(venc->pdev, IORESOURCE_MEM, 0);
826 venc->base = devm_ioremap_resource(&pdev->dev, venc_mem);
827 if (IS_ERR(venc->base)) {
828 r = PTR_ERR(venc->base);
829 goto err_free;
830 }
831
832 venc->vdda_dac_reg = devm_regulator_get(&pdev->dev, "vdda");
833 if (IS_ERR(venc->vdda_dac_reg)) {
834 r = PTR_ERR(venc->vdda_dac_reg);
835 if (r != -EPROBE_DEFER)
836 DSSERR("can't get VDDA_DAC regulator\n");
837 goto err_free;
838 }
839
840 r = venc_get_clocks(venc);
841 if (r)
842 goto err_free;
843
844 r = venc_probe_of(venc);
845 if (r)
846 goto err_free;
847
848 pm_runtime_enable(&pdev->dev);
849
850 r = venc_init_output(venc);
851 if (r)
852 goto err_pm_disable;
853
854 r = component_add(&pdev->dev, &venc_component_ops);
855 if (r)
856 goto err_uninit_output;
857
858 return 0;
859
860err_uninit_output:
861 venc_uninit_output(venc);
862err_pm_disable:
863 pm_runtime_disable(&pdev->dev);
864err_free:
865 kfree(venc);
866 return r;
867}
868
869static int venc_remove(struct platform_device *pdev)
870{
871 struct venc_device *venc = platform_get_drvdata(pdev);
872
873 component_del(&pdev->dev, &venc_component_ops);
874
875 venc_uninit_output(venc);
876
877 pm_runtime_disable(&pdev->dev);
878
879 kfree(venc);
880 return 0;
881}
882
883static int venc_runtime_suspend(struct device *dev)
884{
885 struct venc_device *venc = dev_get_drvdata(dev);
886
887 if (venc->tv_dac_clk)
888 clk_disable_unprepare(venc->tv_dac_clk);
889
890 return 0;
891}
892
893static int venc_runtime_resume(struct device *dev)
894{
895 struct venc_device *venc = dev_get_drvdata(dev);
896
897 if (venc->tv_dac_clk)
898 clk_prepare_enable(venc->tv_dac_clk);
899
900 return 0;
901}
902
903static const struct dev_pm_ops venc_pm_ops = {
904 .runtime_suspend = venc_runtime_suspend,
905 .runtime_resume = venc_runtime_resume,
906 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
907};
908
909static const struct of_device_id venc_of_match[] = {
910 { .compatible = "ti,omap2-venc", },
911 { .compatible = "ti,omap3-venc", },
912 { .compatible = "ti,omap4-venc", },
913 {},
914};
915
916struct platform_driver omap_venchw_driver = {
917 .probe = venc_probe,
918 .remove = venc_remove,
919 .driver = {
920 .name = "omapdss_venc",
921 .pm = &venc_pm_ops,
922 .of_match_table = venc_of_match,
923 .suppress_bind_attrs = true,
924 },
925};