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1/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
3/*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
33#include <uapi/drm/i915_drm.h>
34#include <uapi/drm/drm_fourcc.h>
35
36#include <drm/drmP.h>
37#include "i915_params.h"
38#include "i915_reg.h"
39#include "intel_bios.h"
40#include "intel_ringbuffer.h"
41#include "intel_lrc.h"
42#include "i915_gem_gtt.h"
43#include "i915_gem_render_state.h"
44#include <linux/io-mapping.h>
45#include <linux/i2c.h>
46#include <linux/i2c-algo-bit.h>
47#include <drm/intel-gtt.h>
48#include <drm/drm_legacy.h> /* for struct drm_dma_handle */
49#include <drm/drm_gem.h>
50#include <linux/backlight.h>
51#include <linux/hashtable.h>
52#include <linux/intel-iommu.h>
53#include <linux/kref.h>
54#include <linux/pm_qos.h>
55#include "intel_guc.h"
56
57/* General customization:
58 */
59
60#define DRIVER_NAME "i915"
61#define DRIVER_DESC "Intel Graphics"
62#define DRIVER_DATE "20160229"
63
64#undef WARN_ON
65/* Many gcc seem to no see through this and fall over :( */
66#if 0
67#define WARN_ON(x) ({ \
68 bool __i915_warn_cond = (x); \
69 if (__builtin_constant_p(__i915_warn_cond)) \
70 BUILD_BUG_ON(__i915_warn_cond); \
71 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
72#else
73#define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
74#endif
75
76#undef WARN_ON_ONCE
77#define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
78
79#define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
80 (long) (x), __func__);
81
82/* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
83 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
84 * which may not necessarily be a user visible problem. This will either
85 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
86 * enable distros and users to tailor their preferred amount of i915 abrt
87 * spam.
88 */
89#define I915_STATE_WARN(condition, format...) ({ \
90 int __ret_warn_on = !!(condition); \
91 if (unlikely(__ret_warn_on)) \
92 if (!WARN(i915.verbose_state_checks, format)) \
93 DRM_ERROR(format); \
94 unlikely(__ret_warn_on); \
95})
96
97#define I915_STATE_WARN_ON(x) \
98 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
99
100static inline const char *yesno(bool v)
101{
102 return v ? "yes" : "no";
103}
104
105static inline const char *onoff(bool v)
106{
107 return v ? "on" : "off";
108}
109
110enum pipe {
111 INVALID_PIPE = -1,
112 PIPE_A = 0,
113 PIPE_B,
114 PIPE_C,
115 _PIPE_EDP,
116 I915_MAX_PIPES = _PIPE_EDP
117};
118#define pipe_name(p) ((p) + 'A')
119
120enum transcoder {
121 TRANSCODER_A = 0,
122 TRANSCODER_B,
123 TRANSCODER_C,
124 TRANSCODER_EDP,
125 I915_MAX_TRANSCODERS
126};
127#define transcoder_name(t) ((t) + 'A')
128
129/*
130 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
131 * number of planes per CRTC. Not all platforms really have this many planes,
132 * which means some arrays of size I915_MAX_PLANES may have unused entries
133 * between the topmost sprite plane and the cursor plane.
134 */
135enum plane {
136 PLANE_A = 0,
137 PLANE_B,
138 PLANE_C,
139 PLANE_CURSOR,
140 I915_MAX_PLANES,
141};
142#define plane_name(p) ((p) + 'A')
143
144#define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
145
146enum port {
147 PORT_A = 0,
148 PORT_B,
149 PORT_C,
150 PORT_D,
151 PORT_E,
152 I915_MAX_PORTS
153};
154#define port_name(p) ((p) + 'A')
155
156#define I915_NUM_PHYS_VLV 2
157
158enum dpio_channel {
159 DPIO_CH0,
160 DPIO_CH1
161};
162
163enum dpio_phy {
164 DPIO_PHY0,
165 DPIO_PHY1
166};
167
168enum intel_display_power_domain {
169 POWER_DOMAIN_PIPE_A,
170 POWER_DOMAIN_PIPE_B,
171 POWER_DOMAIN_PIPE_C,
172 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
173 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
174 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
175 POWER_DOMAIN_TRANSCODER_A,
176 POWER_DOMAIN_TRANSCODER_B,
177 POWER_DOMAIN_TRANSCODER_C,
178 POWER_DOMAIN_TRANSCODER_EDP,
179 POWER_DOMAIN_PORT_DDI_A_LANES,
180 POWER_DOMAIN_PORT_DDI_B_LANES,
181 POWER_DOMAIN_PORT_DDI_C_LANES,
182 POWER_DOMAIN_PORT_DDI_D_LANES,
183 POWER_DOMAIN_PORT_DDI_E_LANES,
184 POWER_DOMAIN_PORT_DSI,
185 POWER_DOMAIN_PORT_CRT,
186 POWER_DOMAIN_PORT_OTHER,
187 POWER_DOMAIN_VGA,
188 POWER_DOMAIN_AUDIO,
189 POWER_DOMAIN_PLLS,
190 POWER_DOMAIN_AUX_A,
191 POWER_DOMAIN_AUX_B,
192 POWER_DOMAIN_AUX_C,
193 POWER_DOMAIN_AUX_D,
194 POWER_DOMAIN_GMBUS,
195 POWER_DOMAIN_MODESET,
196 POWER_DOMAIN_INIT,
197
198 POWER_DOMAIN_NUM,
199};
200
201#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
202#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
203 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
204#define POWER_DOMAIN_TRANSCODER(tran) \
205 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
206 (tran) + POWER_DOMAIN_TRANSCODER_A)
207
208enum hpd_pin {
209 HPD_NONE = 0,
210 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
211 HPD_CRT,
212 HPD_SDVO_B,
213 HPD_SDVO_C,
214 HPD_PORT_A,
215 HPD_PORT_B,
216 HPD_PORT_C,
217 HPD_PORT_D,
218 HPD_PORT_E,
219 HPD_NUM_PINS
220};
221
222#define for_each_hpd_pin(__pin) \
223 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
224
225struct i915_hotplug {
226 struct work_struct hotplug_work;
227
228 struct {
229 unsigned long last_jiffies;
230 int count;
231 enum {
232 HPD_ENABLED = 0,
233 HPD_DISABLED = 1,
234 HPD_MARK_DISABLED = 2
235 } state;
236 } stats[HPD_NUM_PINS];
237 u32 event_bits;
238 struct delayed_work reenable_work;
239
240 struct intel_digital_port *irq_port[I915_MAX_PORTS];
241 u32 long_port_mask;
242 u32 short_port_mask;
243 struct work_struct dig_port_work;
244
245 /*
246 * if we get a HPD irq from DP and a HPD irq from non-DP
247 * the non-DP HPD could block the workqueue on a mode config
248 * mutex getting, that userspace may have taken. However
249 * userspace is waiting on the DP workqueue to run which is
250 * blocked behind the non-DP one.
251 */
252 struct workqueue_struct *dp_wq;
253};
254
255#define I915_GEM_GPU_DOMAINS \
256 (I915_GEM_DOMAIN_RENDER | \
257 I915_GEM_DOMAIN_SAMPLER | \
258 I915_GEM_DOMAIN_COMMAND | \
259 I915_GEM_DOMAIN_INSTRUCTION | \
260 I915_GEM_DOMAIN_VERTEX)
261
262#define for_each_pipe(__dev_priv, __p) \
263 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
264#define for_each_pipe_masked(__dev_priv, __p, __mask) \
265 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
266 for_each_if ((__mask) & (1 << (__p)))
267#define for_each_plane(__dev_priv, __pipe, __p) \
268 for ((__p) = 0; \
269 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
270 (__p)++)
271#define for_each_sprite(__dev_priv, __p, __s) \
272 for ((__s) = 0; \
273 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
274 (__s)++)
275
276#define for_each_crtc(dev, crtc) \
277 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
278
279#define for_each_intel_plane(dev, intel_plane) \
280 list_for_each_entry(intel_plane, \
281 &dev->mode_config.plane_list, \
282 base.head)
283
284#define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
285 list_for_each_entry(intel_plane, \
286 &(dev)->mode_config.plane_list, \
287 base.head) \
288 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
289
290#define for_each_intel_crtc(dev, intel_crtc) \
291 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
292
293#define for_each_intel_encoder(dev, intel_encoder) \
294 list_for_each_entry(intel_encoder, \
295 &(dev)->mode_config.encoder_list, \
296 base.head)
297
298#define for_each_intel_connector(dev, intel_connector) \
299 list_for_each_entry(intel_connector, \
300 &dev->mode_config.connector_list, \
301 base.head)
302
303#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
304 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
305 for_each_if ((intel_encoder)->base.crtc == (__crtc))
306
307#define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
308 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
309 for_each_if ((intel_connector)->base.encoder == (__encoder))
310
311#define for_each_power_domain(domain, mask) \
312 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
313 for_each_if ((1 << (domain)) & (mask))
314
315struct drm_i915_private;
316struct i915_mm_struct;
317struct i915_mmu_object;
318
319struct drm_i915_file_private {
320 struct drm_i915_private *dev_priv;
321 struct drm_file *file;
322
323 struct {
324 spinlock_t lock;
325 struct list_head request_list;
326/* 20ms is a fairly arbitrary limit (greater than the average frame time)
327 * chosen to prevent the CPU getting more than a frame ahead of the GPU
328 * (when using lax throttling for the frontbuffer). We also use it to
329 * offer free GPU waitboosts for severely congested workloads.
330 */
331#define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
332 } mm;
333 struct idr context_idr;
334
335 struct intel_rps_client {
336 struct list_head link;
337 unsigned boosts;
338 } rps;
339
340 unsigned int bsd_ring;
341};
342
343enum intel_dpll_id {
344 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
345 /* real shared dpll ids must be >= 0 */
346 DPLL_ID_PCH_PLL_A = 0,
347 DPLL_ID_PCH_PLL_B = 1,
348 /* hsw/bdw */
349 DPLL_ID_WRPLL1 = 0,
350 DPLL_ID_WRPLL2 = 1,
351 DPLL_ID_SPLL = 2,
352
353 /* skl */
354 DPLL_ID_SKL_DPLL1 = 0,
355 DPLL_ID_SKL_DPLL2 = 1,
356 DPLL_ID_SKL_DPLL3 = 2,
357};
358#define I915_NUM_PLLS 3
359
360struct intel_dpll_hw_state {
361 /* i9xx, pch plls */
362 uint32_t dpll;
363 uint32_t dpll_md;
364 uint32_t fp0;
365 uint32_t fp1;
366
367 /* hsw, bdw */
368 uint32_t wrpll;
369 uint32_t spll;
370
371 /* skl */
372 /*
373 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
374 * lower part of ctrl1 and they get shifted into position when writing
375 * the register. This allows us to easily compare the state to share
376 * the DPLL.
377 */
378 uint32_t ctrl1;
379 /* HDMI only, 0 when used for DP */
380 uint32_t cfgcr1, cfgcr2;
381
382 /* bxt */
383 uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10,
384 pcsdw12;
385};
386
387struct intel_shared_dpll_config {
388 unsigned crtc_mask; /* mask of CRTCs sharing this PLL */
389 struct intel_dpll_hw_state hw_state;
390};
391
392struct intel_shared_dpll {
393 struct intel_shared_dpll_config config;
394
395 int active; /* count of number of active CRTCs (i.e. DPMS on) */
396 bool on; /* is the PLL actually active? Disabled during modeset */
397 const char *name;
398 /* should match the index in the dev_priv->shared_dplls array */
399 enum intel_dpll_id id;
400 /* The mode_set hook is optional and should be used together with the
401 * intel_prepare_shared_dpll function. */
402 void (*mode_set)(struct drm_i915_private *dev_priv,
403 struct intel_shared_dpll *pll);
404 void (*enable)(struct drm_i915_private *dev_priv,
405 struct intel_shared_dpll *pll);
406 void (*disable)(struct drm_i915_private *dev_priv,
407 struct intel_shared_dpll *pll);
408 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
409 struct intel_shared_dpll *pll,
410 struct intel_dpll_hw_state *hw_state);
411};
412
413#define SKL_DPLL0 0
414#define SKL_DPLL1 1
415#define SKL_DPLL2 2
416#define SKL_DPLL3 3
417
418/* Used by dp and fdi links */
419struct intel_link_m_n {
420 uint32_t tu;
421 uint32_t gmch_m;
422 uint32_t gmch_n;
423 uint32_t link_m;
424 uint32_t link_n;
425};
426
427void intel_link_compute_m_n(int bpp, int nlanes,
428 int pixel_clock, int link_clock,
429 struct intel_link_m_n *m_n);
430
431/* Interface history:
432 *
433 * 1.1: Original.
434 * 1.2: Add Power Management
435 * 1.3: Add vblank support
436 * 1.4: Fix cmdbuffer path, add heap destroy
437 * 1.5: Add vblank pipe configuration
438 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
439 * - Support vertical blank on secondary display pipe
440 */
441#define DRIVER_MAJOR 1
442#define DRIVER_MINOR 6
443#define DRIVER_PATCHLEVEL 0
444
445#define WATCH_LISTS 0
446
447struct opregion_header;
448struct opregion_acpi;
449struct opregion_swsci;
450struct opregion_asle;
451
452struct intel_opregion {
453 struct opregion_header *header;
454 struct opregion_acpi *acpi;
455 struct opregion_swsci *swsci;
456 u32 swsci_gbda_sub_functions;
457 u32 swsci_sbcb_sub_functions;
458 struct opregion_asle *asle;
459 void *rvda;
460 const void *vbt;
461 u32 vbt_size;
462 u32 *lid_state;
463 struct work_struct asle_work;
464};
465#define OPREGION_SIZE (8*1024)
466
467struct intel_overlay;
468struct intel_overlay_error_state;
469
470#define I915_FENCE_REG_NONE -1
471#define I915_MAX_NUM_FENCES 32
472/* 32 fences + sign bit for FENCE_REG_NONE */
473#define I915_MAX_NUM_FENCE_BITS 6
474
475struct drm_i915_fence_reg {
476 struct list_head lru_list;
477 struct drm_i915_gem_object *obj;
478 int pin_count;
479};
480
481struct sdvo_device_mapping {
482 u8 initialized;
483 u8 dvo_port;
484 u8 slave_addr;
485 u8 dvo_wiring;
486 u8 i2c_pin;
487 u8 ddc_pin;
488};
489
490struct intel_display_error_state;
491
492struct drm_i915_error_state {
493 struct kref ref;
494 struct timeval time;
495
496 char error_msg[128];
497 int iommu;
498 u32 reset_count;
499 u32 suspend_count;
500
501 /* Generic register state */
502 u32 eir;
503 u32 pgtbl_er;
504 u32 ier;
505 u32 gtier[4];
506 u32 ccid;
507 u32 derrmr;
508 u32 forcewake;
509 u32 error; /* gen6+ */
510 u32 err_int; /* gen7 */
511 u32 fault_data0; /* gen8, gen9 */
512 u32 fault_data1; /* gen8, gen9 */
513 u32 done_reg;
514 u32 gac_eco;
515 u32 gam_ecochk;
516 u32 gab_ctl;
517 u32 gfx_mode;
518 u32 extra_instdone[I915_NUM_INSTDONE_REG];
519 u64 fence[I915_MAX_NUM_FENCES];
520 struct intel_overlay_error_state *overlay;
521 struct intel_display_error_state *display;
522 struct drm_i915_error_object *semaphore_obj;
523
524 struct drm_i915_error_ring {
525 bool valid;
526 /* Software tracked state */
527 bool waiting;
528 int hangcheck_score;
529 enum intel_ring_hangcheck_action hangcheck_action;
530 int num_requests;
531
532 /* our own tracking of ring head and tail */
533 u32 cpu_ring_head;
534 u32 cpu_ring_tail;
535
536 u32 semaphore_seqno[I915_NUM_RINGS - 1];
537
538 /* Register state */
539 u32 start;
540 u32 tail;
541 u32 head;
542 u32 ctl;
543 u32 hws;
544 u32 ipeir;
545 u32 ipehr;
546 u32 instdone;
547 u32 bbstate;
548 u32 instpm;
549 u32 instps;
550 u32 seqno;
551 u64 bbaddr;
552 u64 acthd;
553 u32 fault_reg;
554 u64 faddr;
555 u32 rc_psmi; /* sleep state */
556 u32 semaphore_mboxes[I915_NUM_RINGS - 1];
557
558 struct drm_i915_error_object {
559 int page_count;
560 u64 gtt_offset;
561 u32 *pages[0];
562 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
563
564 struct drm_i915_error_request {
565 long jiffies;
566 u32 seqno;
567 u32 tail;
568 } *requests;
569
570 struct {
571 u32 gfx_mode;
572 union {
573 u64 pdp[4];
574 u32 pp_dir_base;
575 };
576 } vm_info;
577
578 pid_t pid;
579 char comm[TASK_COMM_LEN];
580 } ring[I915_NUM_RINGS];
581
582 struct drm_i915_error_buffer {
583 u32 size;
584 u32 name;
585 u32 rseqno[I915_NUM_RINGS], wseqno;
586 u64 gtt_offset;
587 u32 read_domains;
588 u32 write_domain;
589 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
590 s32 pinned:2;
591 u32 tiling:2;
592 u32 dirty:1;
593 u32 purgeable:1;
594 u32 userptr:1;
595 s32 ring:4;
596 u32 cache_level:3;
597 } **active_bo, **pinned_bo;
598
599 u32 *active_bo_count, *pinned_bo_count;
600 u32 vm_count;
601};
602
603struct intel_connector;
604struct intel_encoder;
605struct intel_crtc_state;
606struct intel_initial_plane_config;
607struct intel_crtc;
608struct intel_limit;
609struct dpll;
610
611struct drm_i915_display_funcs {
612 int (*get_display_clock_speed)(struct drm_device *dev);
613 int (*get_fifo_size)(struct drm_device *dev, int plane);
614 /**
615 * find_dpll() - Find the best values for the PLL
616 * @limit: limits for the PLL
617 * @crtc: current CRTC
618 * @target: target frequency in kHz
619 * @refclk: reference clock frequency in kHz
620 * @match_clock: if provided, @best_clock P divider must
621 * match the P divider from @match_clock
622 * used for LVDS downclocking
623 * @best_clock: best PLL values found
624 *
625 * Returns true on success, false on failure.
626 */
627 bool (*find_dpll)(const struct intel_limit *limit,
628 struct intel_crtc_state *crtc_state,
629 int target, int refclk,
630 struct dpll *match_clock,
631 struct dpll *best_clock);
632 int (*compute_pipe_wm)(struct intel_crtc *crtc,
633 struct drm_atomic_state *state);
634 void (*program_watermarks)(struct intel_crtc_state *cstate);
635 void (*update_wm)(struct drm_crtc *crtc);
636 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
637 void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
638 /* Returns the active state of the crtc, and if the crtc is active,
639 * fills out the pipe-config with the hw state. */
640 bool (*get_pipe_config)(struct intel_crtc *,
641 struct intel_crtc_state *);
642 void (*get_initial_plane_config)(struct intel_crtc *,
643 struct intel_initial_plane_config *);
644 int (*crtc_compute_clock)(struct intel_crtc *crtc,
645 struct intel_crtc_state *crtc_state);
646 void (*crtc_enable)(struct drm_crtc *crtc);
647 void (*crtc_disable)(struct drm_crtc *crtc);
648 void (*audio_codec_enable)(struct drm_connector *connector,
649 struct intel_encoder *encoder,
650 const struct drm_display_mode *adjusted_mode);
651 void (*audio_codec_disable)(struct intel_encoder *encoder);
652 void (*fdi_link_train)(struct drm_crtc *crtc);
653 void (*init_clock_gating)(struct drm_device *dev);
654 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
655 struct drm_framebuffer *fb,
656 struct drm_i915_gem_object *obj,
657 struct drm_i915_gem_request *req,
658 uint32_t flags);
659 void (*hpd_irq_setup)(struct drm_device *dev);
660 /* clock updates for mode set */
661 /* cursor updates */
662 /* render clock increase/decrease */
663 /* display clock increase/decrease */
664 /* pll clock increase/decrease */
665};
666
667enum forcewake_domain_id {
668 FW_DOMAIN_ID_RENDER = 0,
669 FW_DOMAIN_ID_BLITTER,
670 FW_DOMAIN_ID_MEDIA,
671
672 FW_DOMAIN_ID_COUNT
673};
674
675enum forcewake_domains {
676 FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
677 FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
678 FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
679 FORCEWAKE_ALL = (FORCEWAKE_RENDER |
680 FORCEWAKE_BLITTER |
681 FORCEWAKE_MEDIA)
682};
683
684struct intel_uncore_funcs {
685 void (*force_wake_get)(struct drm_i915_private *dev_priv,
686 enum forcewake_domains domains);
687 void (*force_wake_put)(struct drm_i915_private *dev_priv,
688 enum forcewake_domains domains);
689
690 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
691 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
692 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
693 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
694
695 void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r,
696 uint8_t val, bool trace);
697 void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r,
698 uint16_t val, bool trace);
699 void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r,
700 uint32_t val, bool trace);
701 void (*mmio_writeq)(struct drm_i915_private *dev_priv, i915_reg_t r,
702 uint64_t val, bool trace);
703};
704
705struct intel_uncore {
706 spinlock_t lock; /** lock is also taken in irq contexts. */
707
708 struct intel_uncore_funcs funcs;
709
710 unsigned fifo_count;
711 enum forcewake_domains fw_domains;
712
713 struct intel_uncore_forcewake_domain {
714 struct drm_i915_private *i915;
715 enum forcewake_domain_id id;
716 unsigned wake_count;
717 struct timer_list timer;
718 i915_reg_t reg_set;
719 u32 val_set;
720 u32 val_clear;
721 i915_reg_t reg_ack;
722 i915_reg_t reg_post;
723 u32 val_reset;
724 } fw_domain[FW_DOMAIN_ID_COUNT];
725
726 int unclaimed_mmio_check;
727};
728
729/* Iterate over initialised fw domains */
730#define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \
731 for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
732 (i__) < FW_DOMAIN_ID_COUNT; \
733 (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \
734 for_each_if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__)))
735
736#define for_each_fw_domain(domain__, dev_priv__, i__) \
737 for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
738
739#define CSR_VERSION(major, minor) ((major) << 16 | (minor))
740#define CSR_VERSION_MAJOR(version) ((version) >> 16)
741#define CSR_VERSION_MINOR(version) ((version) & 0xffff)
742
743struct intel_csr {
744 struct work_struct work;
745 const char *fw_path;
746 uint32_t *dmc_payload;
747 uint32_t dmc_fw_size;
748 uint32_t version;
749 uint32_t mmio_count;
750 i915_reg_t mmioaddr[8];
751 uint32_t mmiodata[8];
752 uint32_t dc_state;
753};
754
755#define DEV_INFO_FOR_EACH_FLAG(func, sep) \
756 func(is_mobile) sep \
757 func(is_i85x) sep \
758 func(is_i915g) sep \
759 func(is_i945gm) sep \
760 func(is_g33) sep \
761 func(need_gfx_hws) sep \
762 func(is_g4x) sep \
763 func(is_pineview) sep \
764 func(is_broadwater) sep \
765 func(is_crestline) sep \
766 func(is_ivybridge) sep \
767 func(is_valleyview) sep \
768 func(is_cherryview) sep \
769 func(is_haswell) sep \
770 func(is_skylake) sep \
771 func(is_broxton) sep \
772 func(is_kabylake) sep \
773 func(is_preliminary) sep \
774 func(has_fbc) sep \
775 func(has_pipe_cxsr) sep \
776 func(has_hotplug) sep \
777 func(cursor_needs_physical) sep \
778 func(has_overlay) sep \
779 func(overlay_needs_physical) sep \
780 func(supports_tv) sep \
781 func(has_llc) sep \
782 func(has_ddi) sep \
783 func(has_fpga_dbg)
784
785#define DEFINE_FLAG(name) u8 name:1
786#define SEP_SEMICOLON ;
787
788struct intel_device_info {
789 u32 display_mmio_offset;
790 u16 device_id;
791 u8 num_pipes:3;
792 u8 num_sprites[I915_MAX_PIPES];
793 u8 gen;
794 u8 ring_mask; /* Rings supported by the HW */
795 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
796 /* Register offsets for the various display pipes and transcoders */
797 int pipe_offsets[I915_MAX_TRANSCODERS];
798 int trans_offsets[I915_MAX_TRANSCODERS];
799 int palette_offsets[I915_MAX_PIPES];
800 int cursor_offsets[I915_MAX_PIPES];
801
802 /* Slice/subslice/EU info */
803 u8 slice_total;
804 u8 subslice_total;
805 u8 subslice_per_slice;
806 u8 eu_total;
807 u8 eu_per_subslice;
808 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
809 u8 subslice_7eu[3];
810 u8 has_slice_pg:1;
811 u8 has_subslice_pg:1;
812 u8 has_eu_pg:1;
813};
814
815#undef DEFINE_FLAG
816#undef SEP_SEMICOLON
817
818enum i915_cache_level {
819 I915_CACHE_NONE = 0,
820 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
821 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
822 caches, eg sampler/render caches, and the
823 large Last-Level-Cache. LLC is coherent with
824 the CPU, but L3 is only visible to the GPU. */
825 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
826};
827
828struct i915_ctx_hang_stats {
829 /* This context had batch pending when hang was declared */
830 unsigned batch_pending;
831
832 /* This context had batch active when hang was declared */
833 unsigned batch_active;
834
835 /* Time when this context was last blamed for a GPU reset */
836 unsigned long guilty_ts;
837
838 /* If the contexts causes a second GPU hang within this time,
839 * it is permanently banned from submitting any more work.
840 */
841 unsigned long ban_period_seconds;
842
843 /* This context is banned to submit more work */
844 bool banned;
845};
846
847/* This must match up with the value previously used for execbuf2.rsvd1. */
848#define DEFAULT_CONTEXT_HANDLE 0
849
850#define CONTEXT_NO_ZEROMAP (1<<0)
851/**
852 * struct intel_context - as the name implies, represents a context.
853 * @ref: reference count.
854 * @user_handle: userspace tracking identity for this context.
855 * @remap_slice: l3 row remapping information.
856 * @flags: context specific flags:
857 * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
858 * @file_priv: filp associated with this context (NULL for global default
859 * context).
860 * @hang_stats: information about the role of this context in possible GPU
861 * hangs.
862 * @ppgtt: virtual memory space used by this context.
863 * @legacy_hw_ctx: render context backing object and whether it is correctly
864 * initialized (legacy ring submission mechanism only).
865 * @link: link in the global list of contexts.
866 *
867 * Contexts are memory images used by the hardware to store copies of their
868 * internal state.
869 */
870struct intel_context {
871 struct kref ref;
872 int user_handle;
873 uint8_t remap_slice;
874 struct drm_i915_private *i915;
875 int flags;
876 struct drm_i915_file_private *file_priv;
877 struct i915_ctx_hang_stats hang_stats;
878 struct i915_hw_ppgtt *ppgtt;
879
880 /* Legacy ring buffer submission */
881 struct {
882 struct drm_i915_gem_object *rcs_state;
883 bool initialized;
884 } legacy_hw_ctx;
885
886 /* Execlists */
887 struct {
888 struct drm_i915_gem_object *state;
889 struct intel_ringbuffer *ringbuf;
890 int pin_count;
891 struct i915_vma *lrc_vma;
892 u64 lrc_desc;
893 uint32_t *lrc_reg_state;
894 } engine[I915_NUM_RINGS];
895
896 struct list_head link;
897};
898
899enum fb_op_origin {
900 ORIGIN_GTT,
901 ORIGIN_CPU,
902 ORIGIN_CS,
903 ORIGIN_FLIP,
904 ORIGIN_DIRTYFB,
905};
906
907struct intel_fbc {
908 /* This is always the inner lock when overlapping with struct_mutex and
909 * it's the outer lock when overlapping with stolen_lock. */
910 struct mutex lock;
911 unsigned threshold;
912 unsigned int possible_framebuffer_bits;
913 unsigned int busy_bits;
914 unsigned int visible_pipes_mask;
915 struct intel_crtc *crtc;
916
917 struct drm_mm_node compressed_fb;
918 struct drm_mm_node *compressed_llb;
919
920 bool false_color;
921
922 bool enabled;
923 bool active;
924
925 struct intel_fbc_state_cache {
926 struct {
927 unsigned int mode_flags;
928 uint32_t hsw_bdw_pixel_rate;
929 } crtc;
930
931 struct {
932 unsigned int rotation;
933 int src_w;
934 int src_h;
935 bool visible;
936 } plane;
937
938 struct {
939 u64 ilk_ggtt_offset;
940 uint32_t pixel_format;
941 unsigned int stride;
942 int fence_reg;
943 unsigned int tiling_mode;
944 } fb;
945 } state_cache;
946
947 struct intel_fbc_reg_params {
948 struct {
949 enum pipe pipe;
950 enum plane plane;
951 unsigned int fence_y_offset;
952 } crtc;
953
954 struct {
955 u64 ggtt_offset;
956 uint32_t pixel_format;
957 unsigned int stride;
958 int fence_reg;
959 } fb;
960
961 int cfb_size;
962 } params;
963
964 struct intel_fbc_work {
965 bool scheduled;
966 u32 scheduled_vblank;
967 struct work_struct work;
968 } work;
969
970 const char *no_fbc_reason;
971};
972
973/**
974 * HIGH_RR is the highest eDP panel refresh rate read from EDID
975 * LOW_RR is the lowest eDP panel refresh rate found from EDID
976 * parsing for same resolution.
977 */
978enum drrs_refresh_rate_type {
979 DRRS_HIGH_RR,
980 DRRS_LOW_RR,
981 DRRS_MAX_RR, /* RR count */
982};
983
984enum drrs_support_type {
985 DRRS_NOT_SUPPORTED = 0,
986 STATIC_DRRS_SUPPORT = 1,
987 SEAMLESS_DRRS_SUPPORT = 2
988};
989
990struct intel_dp;
991struct i915_drrs {
992 struct mutex mutex;
993 struct delayed_work work;
994 struct intel_dp *dp;
995 unsigned busy_frontbuffer_bits;
996 enum drrs_refresh_rate_type refresh_rate_type;
997 enum drrs_support_type type;
998};
999
1000struct i915_psr {
1001 struct mutex lock;
1002 bool sink_support;
1003 bool source_ok;
1004 struct intel_dp *enabled;
1005 bool active;
1006 struct delayed_work work;
1007 unsigned busy_frontbuffer_bits;
1008 bool psr2_support;
1009 bool aux_frame_sync;
1010 bool link_standby;
1011};
1012
1013enum intel_pch {
1014 PCH_NONE = 0, /* No PCH present */
1015 PCH_IBX, /* Ibexpeak PCH */
1016 PCH_CPT, /* Cougarpoint PCH */
1017 PCH_LPT, /* Lynxpoint PCH */
1018 PCH_SPT, /* Sunrisepoint PCH */
1019 PCH_NOP,
1020};
1021
1022enum intel_sbi_destination {
1023 SBI_ICLK,
1024 SBI_MPHY,
1025};
1026
1027#define QUIRK_PIPEA_FORCE (1<<0)
1028#define QUIRK_LVDS_SSC_DISABLE (1<<1)
1029#define QUIRK_INVERT_BRIGHTNESS (1<<2)
1030#define QUIRK_BACKLIGHT_PRESENT (1<<3)
1031#define QUIRK_PIPEB_FORCE (1<<4)
1032#define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1033
1034struct intel_fbdev;
1035struct intel_fbc_work;
1036
1037struct intel_gmbus {
1038 struct i2c_adapter adapter;
1039 u32 force_bit;
1040 u32 reg0;
1041 i915_reg_t gpio_reg;
1042 struct i2c_algo_bit_data bit_algo;
1043 struct drm_i915_private *dev_priv;
1044};
1045
1046struct i915_suspend_saved_registers {
1047 u32 saveDSPARB;
1048 u32 saveLVDS;
1049 u32 savePP_ON_DELAYS;
1050 u32 savePP_OFF_DELAYS;
1051 u32 savePP_ON;
1052 u32 savePP_OFF;
1053 u32 savePP_CONTROL;
1054 u32 savePP_DIVISOR;
1055 u32 saveFBC_CONTROL;
1056 u32 saveCACHE_MODE_0;
1057 u32 saveMI_ARB_STATE;
1058 u32 saveSWF0[16];
1059 u32 saveSWF1[16];
1060 u32 saveSWF3[3];
1061 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1062 u32 savePCH_PORT_HOTPLUG;
1063 u16 saveGCDGMBUS;
1064};
1065
1066struct vlv_s0ix_state {
1067 /* GAM */
1068 u32 wr_watermark;
1069 u32 gfx_prio_ctrl;
1070 u32 arb_mode;
1071 u32 gfx_pend_tlb0;
1072 u32 gfx_pend_tlb1;
1073 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
1074 u32 media_max_req_count;
1075 u32 gfx_max_req_count;
1076 u32 render_hwsp;
1077 u32 ecochk;
1078 u32 bsd_hwsp;
1079 u32 blt_hwsp;
1080 u32 tlb_rd_addr;
1081
1082 /* MBC */
1083 u32 g3dctl;
1084 u32 gsckgctl;
1085 u32 mbctl;
1086
1087 /* GCP */
1088 u32 ucgctl1;
1089 u32 ucgctl3;
1090 u32 rcgctl1;
1091 u32 rcgctl2;
1092 u32 rstctl;
1093 u32 misccpctl;
1094
1095 /* GPM */
1096 u32 gfxpause;
1097 u32 rpdeuhwtc;
1098 u32 rpdeuc;
1099 u32 ecobus;
1100 u32 pwrdwnupctl;
1101 u32 rp_down_timeout;
1102 u32 rp_deucsw;
1103 u32 rcubmabdtmr;
1104 u32 rcedata;
1105 u32 spare2gh;
1106
1107 /* Display 1 CZ domain */
1108 u32 gt_imr;
1109 u32 gt_ier;
1110 u32 pm_imr;
1111 u32 pm_ier;
1112 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1113
1114 /* GT SA CZ domain */
1115 u32 tilectl;
1116 u32 gt_fifoctl;
1117 u32 gtlc_wake_ctrl;
1118 u32 gtlc_survive;
1119 u32 pmwgicz;
1120
1121 /* Display 2 CZ domain */
1122 u32 gu_ctl0;
1123 u32 gu_ctl1;
1124 u32 pcbr;
1125 u32 clock_gate_dis2;
1126};
1127
1128struct intel_rps_ei {
1129 u32 cz_clock;
1130 u32 render_c0;
1131 u32 media_c0;
1132};
1133
1134struct intel_gen6_power_mgmt {
1135 /*
1136 * work, interrupts_enabled and pm_iir are protected by
1137 * dev_priv->irq_lock
1138 */
1139 struct work_struct work;
1140 bool interrupts_enabled;
1141 u32 pm_iir;
1142
1143 /* Frequencies are stored in potentially platform dependent multiples.
1144 * In other words, *_freq needs to be multiplied by X to be interesting.
1145 * Soft limits are those which are used for the dynamic reclocking done
1146 * by the driver (raise frequencies under heavy loads, and lower for
1147 * lighter loads). Hard limits are those imposed by the hardware.
1148 *
1149 * A distinction is made for overclocking, which is never enabled by
1150 * default, and is considered to be above the hard limit if it's
1151 * possible at all.
1152 */
1153 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1154 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1155 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1156 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1157 u8 min_freq; /* AKA RPn. Minimum frequency */
1158 u8 idle_freq; /* Frequency to request when we are idle */
1159 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1160 u8 rp1_freq; /* "less than" RP0 power/freqency */
1161 u8 rp0_freq; /* Non-overclocked max frequency. */
1162
1163 u8 up_threshold; /* Current %busy required to uplock */
1164 u8 down_threshold; /* Current %busy required to downclock */
1165
1166 int last_adj;
1167 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1168
1169 spinlock_t client_lock;
1170 struct list_head clients;
1171 bool client_boost;
1172
1173 bool enabled;
1174 struct delayed_work delayed_resume_work;
1175 unsigned boosts;
1176
1177 struct intel_rps_client semaphores, mmioflips;
1178
1179 /* manual wa residency calculations */
1180 struct intel_rps_ei up_ei, down_ei;
1181
1182 /*
1183 * Protects RPS/RC6 register access and PCU communication.
1184 * Must be taken after struct_mutex if nested. Note that
1185 * this lock may be held for long periods of time when
1186 * talking to hw - so only take it when talking to hw!
1187 */
1188 struct mutex hw_lock;
1189};
1190
1191/* defined intel_pm.c */
1192extern spinlock_t mchdev_lock;
1193
1194struct intel_ilk_power_mgmt {
1195 u8 cur_delay;
1196 u8 min_delay;
1197 u8 max_delay;
1198 u8 fmax;
1199 u8 fstart;
1200
1201 u64 last_count1;
1202 unsigned long last_time1;
1203 unsigned long chipset_power;
1204 u64 last_count2;
1205 u64 last_time2;
1206 unsigned long gfx_power;
1207 u8 corr;
1208
1209 int c_m;
1210 int r_t;
1211};
1212
1213struct drm_i915_private;
1214struct i915_power_well;
1215
1216struct i915_power_well_ops {
1217 /*
1218 * Synchronize the well's hw state to match the current sw state, for
1219 * example enable/disable it based on the current refcount. Called
1220 * during driver init and resume time, possibly after first calling
1221 * the enable/disable handlers.
1222 */
1223 void (*sync_hw)(struct drm_i915_private *dev_priv,
1224 struct i915_power_well *power_well);
1225 /*
1226 * Enable the well and resources that depend on it (for example
1227 * interrupts located on the well). Called after the 0->1 refcount
1228 * transition.
1229 */
1230 void (*enable)(struct drm_i915_private *dev_priv,
1231 struct i915_power_well *power_well);
1232 /*
1233 * Disable the well and resources that depend on it. Called after
1234 * the 1->0 refcount transition.
1235 */
1236 void (*disable)(struct drm_i915_private *dev_priv,
1237 struct i915_power_well *power_well);
1238 /* Returns the hw enabled state. */
1239 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1240 struct i915_power_well *power_well);
1241};
1242
1243/* Power well structure for haswell */
1244struct i915_power_well {
1245 const char *name;
1246 bool always_on;
1247 /* power well enable/disable usage count */
1248 int count;
1249 /* cached hw enabled state */
1250 bool hw_enabled;
1251 unsigned long domains;
1252 unsigned long data;
1253 const struct i915_power_well_ops *ops;
1254};
1255
1256struct i915_power_domains {
1257 /*
1258 * Power wells needed for initialization at driver init and suspend
1259 * time are on. They are kept on until after the first modeset.
1260 */
1261 bool init_power_on;
1262 bool initializing;
1263 int power_well_count;
1264
1265 struct mutex lock;
1266 int domain_use_count[POWER_DOMAIN_NUM];
1267 struct i915_power_well *power_wells;
1268};
1269
1270#define MAX_L3_SLICES 2
1271struct intel_l3_parity {
1272 u32 *remap_info[MAX_L3_SLICES];
1273 struct work_struct error_work;
1274 int which_slice;
1275};
1276
1277struct i915_gem_mm {
1278 /** Memory allocator for GTT stolen memory */
1279 struct drm_mm stolen;
1280 /** Protects the usage of the GTT stolen memory allocator. This is
1281 * always the inner lock when overlapping with struct_mutex. */
1282 struct mutex stolen_lock;
1283
1284 /** List of all objects in gtt_space. Used to restore gtt
1285 * mappings on resume */
1286 struct list_head bound_list;
1287 /**
1288 * List of objects which are not bound to the GTT (thus
1289 * are idle and not used by the GPU) but still have
1290 * (presumably uncached) pages still attached.
1291 */
1292 struct list_head unbound_list;
1293
1294 /** Usable portion of the GTT for GEM */
1295 unsigned long stolen_base; /* limited to low memory (32-bit) */
1296
1297 /** PPGTT used for aliasing the PPGTT with the GTT */
1298 struct i915_hw_ppgtt *aliasing_ppgtt;
1299
1300 struct notifier_block oom_notifier;
1301 struct shrinker shrinker;
1302 bool shrinker_no_lock_stealing;
1303
1304 /** LRU list of objects with fence regs on them. */
1305 struct list_head fence_list;
1306
1307 /**
1308 * We leave the user IRQ off as much as possible,
1309 * but this means that requests will finish and never
1310 * be retired once the system goes idle. Set a timer to
1311 * fire periodically while the ring is running. When it
1312 * fires, go retire requests.
1313 */
1314 struct delayed_work retire_work;
1315
1316 /**
1317 * When we detect an idle GPU, we want to turn on
1318 * powersaving features. So once we see that there
1319 * are no more requests outstanding and no more
1320 * arrive within a small period of time, we fire
1321 * off the idle_work.
1322 */
1323 struct delayed_work idle_work;
1324
1325 /**
1326 * Are we in a non-interruptible section of code like
1327 * modesetting?
1328 */
1329 bool interruptible;
1330
1331 /**
1332 * Is the GPU currently considered idle, or busy executing userspace
1333 * requests? Whilst idle, we attempt to power down the hardware and
1334 * display clocks. In order to reduce the effect on performance, there
1335 * is a slight delay before we do so.
1336 */
1337 bool busy;
1338
1339 /* the indicator for dispatch video commands on two BSD rings */
1340 unsigned int bsd_ring_dispatch_index;
1341
1342 /** Bit 6 swizzling required for X tiling */
1343 uint32_t bit_6_swizzle_x;
1344 /** Bit 6 swizzling required for Y tiling */
1345 uint32_t bit_6_swizzle_y;
1346
1347 /* accounting, useful for userland debugging */
1348 spinlock_t object_stat_lock;
1349 size_t object_memory;
1350 u32 object_count;
1351};
1352
1353struct drm_i915_error_state_buf {
1354 struct drm_i915_private *i915;
1355 unsigned bytes;
1356 unsigned size;
1357 int err;
1358 u8 *buf;
1359 loff_t start;
1360 loff_t pos;
1361};
1362
1363struct i915_error_state_file_priv {
1364 struct drm_device *dev;
1365 struct drm_i915_error_state *error;
1366};
1367
1368struct i915_gpu_error {
1369 /* For hangcheck timer */
1370#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1371#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1372 /* Hang gpu twice in this window and your context gets banned */
1373#define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1374
1375 struct workqueue_struct *hangcheck_wq;
1376 struct delayed_work hangcheck_work;
1377
1378 /* For reset and error_state handling. */
1379 spinlock_t lock;
1380 /* Protected by the above dev->gpu_error.lock. */
1381 struct drm_i915_error_state *first_error;
1382
1383 unsigned long missed_irq_rings;
1384
1385 /**
1386 * State variable controlling the reset flow and count
1387 *
1388 * This is a counter which gets incremented when reset is triggered,
1389 * and again when reset has been handled. So odd values (lowest bit set)
1390 * means that reset is in progress and even values that
1391 * (reset_counter >> 1):th reset was successfully completed.
1392 *
1393 * If reset is not completed succesfully, the I915_WEDGE bit is
1394 * set meaning that hardware is terminally sour and there is no
1395 * recovery. All waiters on the reset_queue will be woken when
1396 * that happens.
1397 *
1398 * This counter is used by the wait_seqno code to notice that reset
1399 * event happened and it needs to restart the entire ioctl (since most
1400 * likely the seqno it waited for won't ever signal anytime soon).
1401 *
1402 * This is important for lock-free wait paths, where no contended lock
1403 * naturally enforces the correct ordering between the bail-out of the
1404 * waiter and the gpu reset work code.
1405 */
1406 atomic_t reset_counter;
1407
1408#define I915_RESET_IN_PROGRESS_FLAG 1
1409#define I915_WEDGED (1 << 31)
1410
1411 /**
1412 * Waitqueue to signal when the reset has completed. Used by clients
1413 * that wait for dev_priv->mm.wedged to settle.
1414 */
1415 wait_queue_head_t reset_queue;
1416
1417 /* Userspace knobs for gpu hang simulation;
1418 * combines both a ring mask, and extra flags
1419 */
1420 u32 stop_rings;
1421#define I915_STOP_RING_ALLOW_BAN (1 << 31)
1422#define I915_STOP_RING_ALLOW_WARN (1 << 30)
1423
1424 /* For missed irq/seqno simulation. */
1425 unsigned int test_irq_rings;
1426
1427 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1428 bool reload_in_reset;
1429};
1430
1431enum modeset_restore {
1432 MODESET_ON_LID_OPEN,
1433 MODESET_DONE,
1434 MODESET_SUSPENDED,
1435};
1436
1437#define DP_AUX_A 0x40
1438#define DP_AUX_B 0x10
1439#define DP_AUX_C 0x20
1440#define DP_AUX_D 0x30
1441
1442#define DDC_PIN_B 0x05
1443#define DDC_PIN_C 0x04
1444#define DDC_PIN_D 0x06
1445
1446struct ddi_vbt_port_info {
1447 /*
1448 * This is an index in the HDMI/DVI DDI buffer translation table.
1449 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1450 * populate this field.
1451 */
1452#define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1453 uint8_t hdmi_level_shift;
1454
1455 uint8_t supports_dvi:1;
1456 uint8_t supports_hdmi:1;
1457 uint8_t supports_dp:1;
1458
1459 uint8_t alternate_aux_channel;
1460 uint8_t alternate_ddc_pin;
1461
1462 uint8_t dp_boost_level;
1463 uint8_t hdmi_boost_level;
1464};
1465
1466enum psr_lines_to_wait {
1467 PSR_0_LINES_TO_WAIT = 0,
1468 PSR_1_LINE_TO_WAIT,
1469 PSR_4_LINES_TO_WAIT,
1470 PSR_8_LINES_TO_WAIT
1471};
1472
1473struct intel_vbt_data {
1474 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1475 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1476
1477 /* Feature bits */
1478 unsigned int int_tv_support:1;
1479 unsigned int lvds_dither:1;
1480 unsigned int lvds_vbt:1;
1481 unsigned int int_crt_support:1;
1482 unsigned int lvds_use_ssc:1;
1483 unsigned int display_clock_mode:1;
1484 unsigned int fdi_rx_polarity_inverted:1;
1485 unsigned int has_mipi:1;
1486 int lvds_ssc_freq;
1487 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1488
1489 enum drrs_support_type drrs_type;
1490
1491 /* eDP */
1492 int edp_rate;
1493 int edp_lanes;
1494 int edp_preemphasis;
1495 int edp_vswing;
1496 bool edp_initialized;
1497 bool edp_support;
1498 int edp_bpp;
1499 struct edp_power_seq edp_pps;
1500
1501 struct {
1502 bool full_link;
1503 bool require_aux_wakeup;
1504 int idle_frames;
1505 enum psr_lines_to_wait lines_to_wait;
1506 int tp1_wakeup_time;
1507 int tp2_tp3_wakeup_time;
1508 } psr;
1509
1510 struct {
1511 u16 pwm_freq_hz;
1512 bool present;
1513 bool active_low_pwm;
1514 u8 min_brightness; /* min_brightness/255 of max */
1515 } backlight;
1516
1517 /* MIPI DSI */
1518 struct {
1519 u16 port;
1520 u16 panel_id;
1521 struct mipi_config *config;
1522 struct mipi_pps_data *pps;
1523 u8 seq_version;
1524 u32 size;
1525 u8 *data;
1526 const u8 *sequence[MIPI_SEQ_MAX];
1527 } dsi;
1528
1529 int crt_ddc_pin;
1530
1531 int child_dev_num;
1532 union child_device_config *child_dev;
1533
1534 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1535};
1536
1537enum intel_ddb_partitioning {
1538 INTEL_DDB_PART_1_2,
1539 INTEL_DDB_PART_5_6, /* IVB+ */
1540};
1541
1542struct intel_wm_level {
1543 bool enable;
1544 uint32_t pri_val;
1545 uint32_t spr_val;
1546 uint32_t cur_val;
1547 uint32_t fbc_val;
1548};
1549
1550struct ilk_wm_values {
1551 uint32_t wm_pipe[3];
1552 uint32_t wm_lp[3];
1553 uint32_t wm_lp_spr[3];
1554 uint32_t wm_linetime[3];
1555 bool enable_fbc_wm;
1556 enum intel_ddb_partitioning partitioning;
1557};
1558
1559struct vlv_pipe_wm {
1560 uint16_t primary;
1561 uint16_t sprite[2];
1562 uint8_t cursor;
1563};
1564
1565struct vlv_sr_wm {
1566 uint16_t plane;
1567 uint8_t cursor;
1568};
1569
1570struct vlv_wm_values {
1571 struct vlv_pipe_wm pipe[3];
1572 struct vlv_sr_wm sr;
1573 struct {
1574 uint8_t cursor;
1575 uint8_t sprite[2];
1576 uint8_t primary;
1577 } ddl[3];
1578 uint8_t level;
1579 bool cxsr;
1580};
1581
1582struct skl_ddb_entry {
1583 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1584};
1585
1586static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1587{
1588 return entry->end - entry->start;
1589}
1590
1591static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1592 const struct skl_ddb_entry *e2)
1593{
1594 if (e1->start == e2->start && e1->end == e2->end)
1595 return true;
1596
1597 return false;
1598}
1599
1600struct skl_ddb_allocation {
1601 struct skl_ddb_entry pipe[I915_MAX_PIPES];
1602 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1603 struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1604};
1605
1606struct skl_wm_values {
1607 bool dirty[I915_MAX_PIPES];
1608 struct skl_ddb_allocation ddb;
1609 uint32_t wm_linetime[I915_MAX_PIPES];
1610 uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
1611 uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
1612};
1613
1614struct skl_wm_level {
1615 bool plane_en[I915_MAX_PLANES];
1616 uint16_t plane_res_b[I915_MAX_PLANES];
1617 uint8_t plane_res_l[I915_MAX_PLANES];
1618};
1619
1620/*
1621 * This struct helps tracking the state needed for runtime PM, which puts the
1622 * device in PCI D3 state. Notice that when this happens, nothing on the
1623 * graphics device works, even register access, so we don't get interrupts nor
1624 * anything else.
1625 *
1626 * Every piece of our code that needs to actually touch the hardware needs to
1627 * either call intel_runtime_pm_get or call intel_display_power_get with the
1628 * appropriate power domain.
1629 *
1630 * Our driver uses the autosuspend delay feature, which means we'll only really
1631 * suspend if we stay with zero refcount for a certain amount of time. The
1632 * default value is currently very conservative (see intel_runtime_pm_enable), but
1633 * it can be changed with the standard runtime PM files from sysfs.
1634 *
1635 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1636 * goes back to false exactly before we reenable the IRQs. We use this variable
1637 * to check if someone is trying to enable/disable IRQs while they're supposed
1638 * to be disabled. This shouldn't happen and we'll print some error messages in
1639 * case it happens.
1640 *
1641 * For more, read the Documentation/power/runtime_pm.txt.
1642 */
1643struct i915_runtime_pm {
1644 atomic_t wakeref_count;
1645 atomic_t atomic_seq;
1646 bool suspended;
1647 bool irqs_enabled;
1648};
1649
1650enum intel_pipe_crc_source {
1651 INTEL_PIPE_CRC_SOURCE_NONE,
1652 INTEL_PIPE_CRC_SOURCE_PLANE1,
1653 INTEL_PIPE_CRC_SOURCE_PLANE2,
1654 INTEL_PIPE_CRC_SOURCE_PF,
1655 INTEL_PIPE_CRC_SOURCE_PIPE,
1656 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1657 INTEL_PIPE_CRC_SOURCE_TV,
1658 INTEL_PIPE_CRC_SOURCE_DP_B,
1659 INTEL_PIPE_CRC_SOURCE_DP_C,
1660 INTEL_PIPE_CRC_SOURCE_DP_D,
1661 INTEL_PIPE_CRC_SOURCE_AUTO,
1662 INTEL_PIPE_CRC_SOURCE_MAX,
1663};
1664
1665struct intel_pipe_crc_entry {
1666 uint32_t frame;
1667 uint32_t crc[5];
1668};
1669
1670#define INTEL_PIPE_CRC_ENTRIES_NR 128
1671struct intel_pipe_crc {
1672 spinlock_t lock;
1673 bool opened; /* exclusive access to the result file */
1674 struct intel_pipe_crc_entry *entries;
1675 enum intel_pipe_crc_source source;
1676 int head, tail;
1677 wait_queue_head_t wq;
1678};
1679
1680struct i915_frontbuffer_tracking {
1681 struct mutex lock;
1682
1683 /*
1684 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1685 * scheduled flips.
1686 */
1687 unsigned busy_bits;
1688 unsigned flip_bits;
1689};
1690
1691struct i915_wa_reg {
1692 i915_reg_t addr;
1693 u32 value;
1694 /* bitmask representing WA bits */
1695 u32 mask;
1696};
1697
1698/*
1699 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1700 * allowing it for RCS as we don't foresee any requirement of having
1701 * a whitelist for other engines. When it is really required for
1702 * other engines then the limit need to be increased.
1703 */
1704#define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1705
1706struct i915_workarounds {
1707 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1708 u32 count;
1709 u32 hw_whitelist_count[I915_NUM_RINGS];
1710};
1711
1712struct i915_virtual_gpu {
1713 bool active;
1714};
1715
1716struct i915_execbuffer_params {
1717 struct drm_device *dev;
1718 struct drm_file *file;
1719 uint32_t dispatch_flags;
1720 uint32_t args_batch_start_offset;
1721 uint64_t batch_obj_vm_offset;
1722 struct intel_engine_cs *ring;
1723 struct drm_i915_gem_object *batch_obj;
1724 struct intel_context *ctx;
1725 struct drm_i915_gem_request *request;
1726};
1727
1728/* used in computing the new watermarks state */
1729struct intel_wm_config {
1730 unsigned int num_pipes_active;
1731 bool sprites_enabled;
1732 bool sprites_scaled;
1733};
1734
1735struct drm_i915_private {
1736 struct drm_device *dev;
1737 struct kmem_cache *objects;
1738 struct kmem_cache *vmas;
1739 struct kmem_cache *requests;
1740
1741 const struct intel_device_info info;
1742
1743 int relative_constants_mode;
1744
1745 void __iomem *regs;
1746
1747 struct intel_uncore uncore;
1748
1749 struct i915_virtual_gpu vgpu;
1750
1751 struct intel_guc guc;
1752
1753 struct intel_csr csr;
1754
1755 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1756
1757 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1758 * controller on different i2c buses. */
1759 struct mutex gmbus_mutex;
1760
1761 /**
1762 * Base address of the gmbus and gpio block.
1763 */
1764 uint32_t gpio_mmio_base;
1765
1766 /* MMIO base address for MIPI regs */
1767 uint32_t mipi_mmio_base;
1768
1769 uint32_t psr_mmio_base;
1770
1771 wait_queue_head_t gmbus_wait_queue;
1772
1773 struct pci_dev *bridge_dev;
1774 struct intel_engine_cs ring[I915_NUM_RINGS];
1775 struct drm_i915_gem_object *semaphore_obj;
1776 uint32_t last_seqno, next_seqno;
1777
1778 struct drm_dma_handle *status_page_dmah;
1779 struct resource mch_res;
1780
1781 /* protects the irq masks */
1782 spinlock_t irq_lock;
1783
1784 /* protects the mmio flip data */
1785 spinlock_t mmio_flip_lock;
1786
1787 bool display_irqs_enabled;
1788
1789 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1790 struct pm_qos_request pm_qos;
1791
1792 /* Sideband mailbox protection */
1793 struct mutex sb_lock;
1794
1795 /** Cached value of IMR to avoid reads in updating the bitfield */
1796 union {
1797 u32 irq_mask;
1798 u32 de_irq_mask[I915_MAX_PIPES];
1799 };
1800 u32 gt_irq_mask;
1801 u32 pm_irq_mask;
1802 u32 pm_rps_events;
1803 u32 pipestat_irq_mask[I915_MAX_PIPES];
1804
1805 struct i915_hotplug hotplug;
1806 struct intel_fbc fbc;
1807 struct i915_drrs drrs;
1808 struct intel_opregion opregion;
1809 struct intel_vbt_data vbt;
1810
1811 bool preserve_bios_swizzle;
1812
1813 /* overlay */
1814 struct intel_overlay *overlay;
1815
1816 /* backlight registers and fields in struct intel_panel */
1817 struct mutex backlight_lock;
1818
1819 /* LVDS info */
1820 bool no_aux_handshake;
1821
1822 /* protects panel power sequencer state */
1823 struct mutex pps_mutex;
1824
1825 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1826 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1827
1828 unsigned int fsb_freq, mem_freq, is_ddr3;
1829 unsigned int skl_boot_cdclk;
1830 unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
1831 unsigned int max_dotclk_freq;
1832 unsigned int hpll_freq;
1833 unsigned int czclk_freq;
1834
1835 /**
1836 * wq - Driver workqueue for GEM.
1837 *
1838 * NOTE: Work items scheduled here are not allowed to grab any modeset
1839 * locks, for otherwise the flushing done in the pageflip code will
1840 * result in deadlocks.
1841 */
1842 struct workqueue_struct *wq;
1843
1844 /* Display functions */
1845 struct drm_i915_display_funcs display;
1846
1847 /* PCH chipset type */
1848 enum intel_pch pch_type;
1849 unsigned short pch_id;
1850
1851 unsigned long quirks;
1852
1853 enum modeset_restore modeset_restore;
1854 struct mutex modeset_restore_lock;
1855 struct drm_atomic_state *modeset_restore_state;
1856
1857 struct list_head vm_list; /* Global list of all address spaces */
1858 struct i915_gtt gtt; /* VM representing the global address space */
1859
1860 struct i915_gem_mm mm;
1861 DECLARE_HASHTABLE(mm_structs, 7);
1862 struct mutex mm_lock;
1863
1864 /* Kernel Modesetting */
1865
1866 struct sdvo_device_mapping sdvo_mappings[2];
1867
1868 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1869 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1870 wait_queue_head_t pending_flip_queue;
1871
1872#ifdef CONFIG_DEBUG_FS
1873 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1874#endif
1875
1876 /* dpll and cdclk state is protected by connection_mutex */
1877 int num_shared_dpll;
1878 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1879
1880 unsigned int active_crtcs;
1881 unsigned int min_pixclk[I915_MAX_PIPES];
1882
1883 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1884
1885 struct i915_workarounds workarounds;
1886
1887 /* Reclocking support */
1888 bool render_reclock_avail;
1889
1890 struct i915_frontbuffer_tracking fb_tracking;
1891
1892 u16 orig_clock;
1893
1894 bool mchbar_need_disable;
1895
1896 struct intel_l3_parity l3_parity;
1897
1898 /* Cannot be determined by PCIID. You must always read a register. */
1899 size_t ellc_size;
1900
1901 /* gen6+ rps state */
1902 struct intel_gen6_power_mgmt rps;
1903
1904 /* ilk-only ips/rps state. Everything in here is protected by the global
1905 * mchdev_lock in intel_pm.c */
1906 struct intel_ilk_power_mgmt ips;
1907
1908 struct i915_power_domains power_domains;
1909
1910 struct i915_psr psr;
1911
1912 struct i915_gpu_error gpu_error;
1913
1914 struct drm_i915_gem_object *vlv_pctx;
1915
1916#ifdef CONFIG_DRM_FBDEV_EMULATION
1917 /* list of fbdev register on this device */
1918 struct intel_fbdev *fbdev;
1919 struct work_struct fbdev_suspend_work;
1920#endif
1921
1922 struct drm_property *broadcast_rgb_property;
1923 struct drm_property *force_audio_property;
1924
1925 /* hda/i915 audio component */
1926 struct i915_audio_component *audio_component;
1927 bool audio_component_registered;
1928 /**
1929 * av_mutex - mutex for audio/video sync
1930 *
1931 */
1932 struct mutex av_mutex;
1933
1934 uint32_t hw_context_size;
1935 struct list_head context_list;
1936
1937 u32 fdi_rx_config;
1938
1939 u32 chv_phy_control;
1940
1941 u32 suspend_count;
1942 bool suspended_to_idle;
1943 struct i915_suspend_saved_registers regfile;
1944 struct vlv_s0ix_state vlv_s0ix_state;
1945
1946 struct {
1947 /*
1948 * Raw watermark latency values:
1949 * in 0.1us units for WM0,
1950 * in 0.5us units for WM1+.
1951 */
1952 /* primary */
1953 uint16_t pri_latency[5];
1954 /* sprite */
1955 uint16_t spr_latency[5];
1956 /* cursor */
1957 uint16_t cur_latency[5];
1958 /*
1959 * Raw watermark memory latency values
1960 * for SKL for all 8 levels
1961 * in 1us units.
1962 */
1963 uint16_t skl_latency[8];
1964
1965 /* Committed wm config */
1966 struct intel_wm_config config;
1967
1968 /*
1969 * The skl_wm_values structure is a bit too big for stack
1970 * allocation, so we keep the staging struct where we store
1971 * intermediate results here instead.
1972 */
1973 struct skl_wm_values skl_results;
1974
1975 /* current hardware state */
1976 union {
1977 struct ilk_wm_values hw;
1978 struct skl_wm_values skl_hw;
1979 struct vlv_wm_values vlv;
1980 };
1981
1982 uint8_t max_level;
1983 } wm;
1984
1985 struct i915_runtime_pm pm;
1986
1987 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1988 struct {
1989 int (*execbuf_submit)(struct i915_execbuffer_params *params,
1990 struct drm_i915_gem_execbuffer2 *args,
1991 struct list_head *vmas);
1992 int (*init_rings)(struct drm_device *dev);
1993 void (*cleanup_ring)(struct intel_engine_cs *ring);
1994 void (*stop_ring)(struct intel_engine_cs *ring);
1995 } gt;
1996
1997 struct intel_context *kernel_context;
1998
1999 bool edp_low_vswing;
2000
2001 /* perform PHY state sanity checks? */
2002 bool chv_phy_assert[2];
2003
2004 struct intel_encoder *dig_port_map[I915_MAX_PORTS];
2005
2006 /*
2007 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2008 * will be rejected. Instead look for a better place.
2009 */
2010};
2011
2012static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
2013{
2014 return dev->dev_private;
2015}
2016
2017static inline struct drm_i915_private *dev_to_i915(struct device *dev)
2018{
2019 return to_i915(dev_get_drvdata(dev));
2020}
2021
2022static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
2023{
2024 return container_of(guc, struct drm_i915_private, guc);
2025}
2026
2027/* Iterate over initialised rings */
2028#define for_each_ring(ring__, dev_priv__, i__) \
2029 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
2030 for_each_if ((((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))))
2031
2032enum hdmi_force_audio {
2033 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
2034 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
2035 HDMI_AUDIO_AUTO, /* trust EDID */
2036 HDMI_AUDIO_ON, /* force turn on HDMI audio */
2037};
2038
2039#define I915_GTT_OFFSET_NONE ((u32)-1)
2040
2041struct drm_i915_gem_object_ops {
2042 unsigned int flags;
2043#define I915_GEM_OBJECT_HAS_STRUCT_PAGE 0x1
2044
2045 /* Interface between the GEM object and its backing storage.
2046 * get_pages() is called once prior to the use of the associated set
2047 * of pages before to binding them into the GTT, and put_pages() is
2048 * called after we no longer need them. As we expect there to be
2049 * associated cost with migrating pages between the backing storage
2050 * and making them available for the GPU (e.g. clflush), we may hold
2051 * onto the pages after they are no longer referenced by the GPU
2052 * in case they may be used again shortly (for example migrating the
2053 * pages to a different memory domain within the GTT). put_pages()
2054 * will therefore most likely be called when the object itself is
2055 * being released or under memory pressure (where we attempt to
2056 * reap pages for the shrinker).
2057 */
2058 int (*get_pages)(struct drm_i915_gem_object *);
2059 void (*put_pages)(struct drm_i915_gem_object *);
2060
2061 int (*dmabuf_export)(struct drm_i915_gem_object *);
2062 void (*release)(struct drm_i915_gem_object *);
2063};
2064
2065/*
2066 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2067 * considered to be the frontbuffer for the given plane interface-wise. This
2068 * doesn't mean that the hw necessarily already scans it out, but that any
2069 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2070 *
2071 * We have one bit per pipe and per scanout plane type.
2072 */
2073#define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2074#define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2075#define INTEL_FRONTBUFFER_BITS \
2076 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
2077#define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2078 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2079#define INTEL_FRONTBUFFER_CURSOR(pipe) \
2080 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2081#define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2082 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2083#define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2084 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2085#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2086 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2087
2088struct drm_i915_gem_object {
2089 struct drm_gem_object base;
2090
2091 const struct drm_i915_gem_object_ops *ops;
2092
2093 /** List of VMAs backed by this object */
2094 struct list_head vma_list;
2095
2096 /** Stolen memory for this object, instead of being backed by shmem. */
2097 struct drm_mm_node *stolen;
2098 struct list_head global_list;
2099
2100 struct list_head ring_list[I915_NUM_RINGS];
2101 /** Used in execbuf to temporarily hold a ref */
2102 struct list_head obj_exec_link;
2103
2104 struct list_head batch_pool_link;
2105
2106 /**
2107 * This is set if the object is on the active lists (has pending
2108 * rendering and so a non-zero seqno), and is not set if it i s on
2109 * inactive (ready to be unbound) list.
2110 */
2111 unsigned int active:I915_NUM_RINGS;
2112
2113 /**
2114 * This is set if the object has been written to since last bound
2115 * to the GTT
2116 */
2117 unsigned int dirty:1;
2118
2119 /**
2120 * Fence register bits (if any) for this object. Will be set
2121 * as needed when mapped into the GTT.
2122 * Protected by dev->struct_mutex.
2123 */
2124 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
2125
2126 /**
2127 * Advice: are the backing pages purgeable?
2128 */
2129 unsigned int madv:2;
2130
2131 /**
2132 * Current tiling mode for the object.
2133 */
2134 unsigned int tiling_mode:2;
2135 /**
2136 * Whether the tiling parameters for the currently associated fence
2137 * register have changed. Note that for the purposes of tracking
2138 * tiling changes we also treat the unfenced register, the register
2139 * slot that the object occupies whilst it executes a fenced
2140 * command (such as BLT on gen2/3), as a "fence".
2141 */
2142 unsigned int fence_dirty:1;
2143
2144 /**
2145 * Is the object at the current location in the gtt mappable and
2146 * fenceable? Used to avoid costly recalculations.
2147 */
2148 unsigned int map_and_fenceable:1;
2149
2150 /**
2151 * Whether the current gtt mapping needs to be mappable (and isn't just
2152 * mappable by accident). Track pin and fault separate for a more
2153 * accurate mappable working set.
2154 */
2155 unsigned int fault_mappable:1;
2156
2157 /*
2158 * Is the object to be mapped as read-only to the GPU
2159 * Only honoured if hardware has relevant pte bit
2160 */
2161 unsigned long gt_ro:1;
2162 unsigned int cache_level:3;
2163 unsigned int cache_dirty:1;
2164
2165 unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
2166
2167 unsigned int pin_display;
2168
2169 struct sg_table *pages;
2170 int pages_pin_count;
2171 struct get_page {
2172 struct scatterlist *sg;
2173 int last;
2174 } get_page;
2175
2176 /* prime dma-buf support */
2177 void *dma_buf_vmapping;
2178 int vmapping_count;
2179
2180 /** Breadcrumb of last rendering to the buffer.
2181 * There can only be one writer, but we allow for multiple readers.
2182 * If there is a writer that necessarily implies that all other
2183 * read requests are complete - but we may only be lazily clearing
2184 * the read requests. A read request is naturally the most recent
2185 * request on a ring, so we may have two different write and read
2186 * requests on one ring where the write request is older than the
2187 * read request. This allows for the CPU to read from an active
2188 * buffer by only waiting for the write to complete.
2189 * */
2190 struct drm_i915_gem_request *last_read_req[I915_NUM_RINGS];
2191 struct drm_i915_gem_request *last_write_req;
2192 /** Breadcrumb of last fenced GPU access to the buffer. */
2193 struct drm_i915_gem_request *last_fenced_req;
2194
2195 /** Current tiling stride for the object, if it's tiled. */
2196 uint32_t stride;
2197
2198 /** References from framebuffers, locks out tiling changes. */
2199 unsigned long framebuffer_references;
2200
2201 /** Record of address bit 17 of each page at last unbind. */
2202 unsigned long *bit_17;
2203
2204 union {
2205 /** for phy allocated objects */
2206 struct drm_dma_handle *phys_handle;
2207
2208 struct i915_gem_userptr {
2209 uintptr_t ptr;
2210 unsigned read_only :1;
2211 unsigned workers :4;
2212#define I915_GEM_USERPTR_MAX_WORKERS 15
2213
2214 struct i915_mm_struct *mm;
2215 struct i915_mmu_object *mmu_object;
2216 struct work_struct *work;
2217 } userptr;
2218 };
2219};
2220#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2221
2222void i915_gem_track_fb(struct drm_i915_gem_object *old,
2223 struct drm_i915_gem_object *new,
2224 unsigned frontbuffer_bits);
2225
2226/**
2227 * Request queue structure.
2228 *
2229 * The request queue allows us to note sequence numbers that have been emitted
2230 * and may be associated with active buffers to be retired.
2231 *
2232 * By keeping this list, we can avoid having to do questionable sequence
2233 * number comparisons on buffer last_read|write_seqno. It also allows an
2234 * emission time to be associated with the request for tracking how far ahead
2235 * of the GPU the submission is.
2236 *
2237 * The requests are reference counted, so upon creation they should have an
2238 * initial reference taken using kref_init
2239 */
2240struct drm_i915_gem_request {
2241 struct kref ref;
2242
2243 /** On Which ring this request was generated */
2244 struct drm_i915_private *i915;
2245 struct intel_engine_cs *ring;
2246
2247 /** GEM sequence number associated with the previous request,
2248 * when the HWS breadcrumb is equal to this the GPU is processing
2249 * this request.
2250 */
2251 u32 previous_seqno;
2252
2253 /** GEM sequence number associated with this request,
2254 * when the HWS breadcrumb is equal or greater than this the GPU
2255 * has finished processing this request.
2256 */
2257 u32 seqno;
2258
2259 /** Position in the ringbuffer of the start of the request */
2260 u32 head;
2261
2262 /**
2263 * Position in the ringbuffer of the start of the postfix.
2264 * This is required to calculate the maximum available ringbuffer
2265 * space without overwriting the postfix.
2266 */
2267 u32 postfix;
2268
2269 /** Position in the ringbuffer of the end of the whole request */
2270 u32 tail;
2271
2272 /**
2273 * Context and ring buffer related to this request
2274 * Contexts are refcounted, so when this request is associated with a
2275 * context, we must increment the context's refcount, to guarantee that
2276 * it persists while any request is linked to it. Requests themselves
2277 * are also refcounted, so the request will only be freed when the last
2278 * reference to it is dismissed, and the code in
2279 * i915_gem_request_free() will then decrement the refcount on the
2280 * context.
2281 */
2282 struct intel_context *ctx;
2283 struct intel_ringbuffer *ringbuf;
2284
2285 /** Batch buffer related to this request if any (used for
2286 error state dump only) */
2287 struct drm_i915_gem_object *batch_obj;
2288
2289 /** Time at which this request was emitted, in jiffies. */
2290 unsigned long emitted_jiffies;
2291
2292 /** global list entry for this request */
2293 struct list_head list;
2294
2295 struct drm_i915_file_private *file_priv;
2296 /** file_priv list entry for this request */
2297 struct list_head client_list;
2298
2299 /** process identifier submitting this request */
2300 struct pid *pid;
2301
2302 /**
2303 * The ELSP only accepts two elements at a time, so we queue
2304 * context/tail pairs on a given queue (ring->execlist_queue) until the
2305 * hardware is available. The queue serves a double purpose: we also use
2306 * it to keep track of the up to 2 contexts currently in the hardware
2307 * (usually one in execution and the other queued up by the GPU): We
2308 * only remove elements from the head of the queue when the hardware
2309 * informs us that an element has been completed.
2310 *
2311 * All accesses to the queue are mediated by a spinlock
2312 * (ring->execlist_lock).
2313 */
2314
2315 /** Execlist link in the submission queue.*/
2316 struct list_head execlist_link;
2317
2318 /** Execlists no. of times this request has been sent to the ELSP */
2319 int elsp_submitted;
2320
2321};
2322
2323struct drm_i915_gem_request * __must_check
2324i915_gem_request_alloc(struct intel_engine_cs *engine,
2325 struct intel_context *ctx);
2326void i915_gem_request_cancel(struct drm_i915_gem_request *req);
2327void i915_gem_request_free(struct kref *req_ref);
2328int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
2329 struct drm_file *file);
2330
2331static inline uint32_t
2332i915_gem_request_get_seqno(struct drm_i915_gem_request *req)
2333{
2334 return req ? req->seqno : 0;
2335}
2336
2337static inline struct intel_engine_cs *
2338i915_gem_request_get_ring(struct drm_i915_gem_request *req)
2339{
2340 return req ? req->ring : NULL;
2341}
2342
2343static inline struct drm_i915_gem_request *
2344i915_gem_request_reference(struct drm_i915_gem_request *req)
2345{
2346 if (req)
2347 kref_get(&req->ref);
2348 return req;
2349}
2350
2351static inline void
2352i915_gem_request_unreference(struct drm_i915_gem_request *req)
2353{
2354 WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex));
2355 kref_put(&req->ref, i915_gem_request_free);
2356}
2357
2358static inline void
2359i915_gem_request_unreference__unlocked(struct drm_i915_gem_request *req)
2360{
2361 struct drm_device *dev;
2362
2363 if (!req)
2364 return;
2365
2366 dev = req->ring->dev;
2367 if (kref_put_mutex(&req->ref, i915_gem_request_free, &dev->struct_mutex))
2368 mutex_unlock(&dev->struct_mutex);
2369}
2370
2371static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst,
2372 struct drm_i915_gem_request *src)
2373{
2374 if (src)
2375 i915_gem_request_reference(src);
2376
2377 if (*pdst)
2378 i915_gem_request_unreference(*pdst);
2379
2380 *pdst = src;
2381}
2382
2383/*
2384 * XXX: i915_gem_request_completed should be here but currently needs the
2385 * definition of i915_seqno_passed() which is below. It will be moved in
2386 * a later patch when the call to i915_seqno_passed() is obsoleted...
2387 */
2388
2389/*
2390 * A command that requires special handling by the command parser.
2391 */
2392struct drm_i915_cmd_descriptor {
2393 /*
2394 * Flags describing how the command parser processes the command.
2395 *
2396 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2397 * a length mask if not set
2398 * CMD_DESC_SKIP: The command is allowed but does not follow the
2399 * standard length encoding for the opcode range in
2400 * which it falls
2401 * CMD_DESC_REJECT: The command is never allowed
2402 * CMD_DESC_REGISTER: The command should be checked against the
2403 * register whitelist for the appropriate ring
2404 * CMD_DESC_MASTER: The command is allowed if the submitting process
2405 * is the DRM master
2406 */
2407 u32 flags;
2408#define CMD_DESC_FIXED (1<<0)
2409#define CMD_DESC_SKIP (1<<1)
2410#define CMD_DESC_REJECT (1<<2)
2411#define CMD_DESC_REGISTER (1<<3)
2412#define CMD_DESC_BITMASK (1<<4)
2413#define CMD_DESC_MASTER (1<<5)
2414
2415 /*
2416 * The command's unique identification bits and the bitmask to get them.
2417 * This isn't strictly the opcode field as defined in the spec and may
2418 * also include type, subtype, and/or subop fields.
2419 */
2420 struct {
2421 u32 value;
2422 u32 mask;
2423 } cmd;
2424
2425 /*
2426 * The command's length. The command is either fixed length (i.e. does
2427 * not include a length field) or has a length field mask. The flag
2428 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2429 * a length mask. All command entries in a command table must include
2430 * length information.
2431 */
2432 union {
2433 u32 fixed;
2434 u32 mask;
2435 } length;
2436
2437 /*
2438 * Describes where to find a register address in the command to check
2439 * against the ring's register whitelist. Only valid if flags has the
2440 * CMD_DESC_REGISTER bit set.
2441 *
2442 * A non-zero step value implies that the command may access multiple
2443 * registers in sequence (e.g. LRI), in that case step gives the
2444 * distance in dwords between individual offset fields.
2445 */
2446 struct {
2447 u32 offset;
2448 u32 mask;
2449 u32 step;
2450 } reg;
2451
2452#define MAX_CMD_DESC_BITMASKS 3
2453 /*
2454 * Describes command checks where a particular dword is masked and
2455 * compared against an expected value. If the command does not match
2456 * the expected value, the parser rejects it. Only valid if flags has
2457 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2458 * are valid.
2459 *
2460 * If the check specifies a non-zero condition_mask then the parser
2461 * only performs the check when the bits specified by condition_mask
2462 * are non-zero.
2463 */
2464 struct {
2465 u32 offset;
2466 u32 mask;
2467 u32 expected;
2468 u32 condition_offset;
2469 u32 condition_mask;
2470 } bits[MAX_CMD_DESC_BITMASKS];
2471};
2472
2473/*
2474 * A table of commands requiring special handling by the command parser.
2475 *
2476 * Each ring has an array of tables. Each table consists of an array of command
2477 * descriptors, which must be sorted with command opcodes in ascending order.
2478 */
2479struct drm_i915_cmd_table {
2480 const struct drm_i915_cmd_descriptor *table;
2481 int count;
2482};
2483
2484/* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2485#define __I915__(p) ({ \
2486 struct drm_i915_private *__p; \
2487 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2488 __p = (struct drm_i915_private *)p; \
2489 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2490 __p = to_i915((struct drm_device *)p); \
2491 else \
2492 BUILD_BUG(); \
2493 __p; \
2494})
2495#define INTEL_INFO(p) (&__I915__(p)->info)
2496#define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2497#define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
2498
2499#define REVID_FOREVER 0xff
2500/*
2501 * Return true if revision is in range [since,until] inclusive.
2502 *
2503 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2504 */
2505#define IS_REVID(p, since, until) \
2506 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2507
2508#define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2509#define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2510#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2511#define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2512#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2513#define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2514#define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2515#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2516#define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2517#define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2518#define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2519#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2520#define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2521#define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2522#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2523#define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2524#define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2525#define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2526#define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2527 INTEL_DEVID(dev) == 0x0152 || \
2528 INTEL_DEVID(dev) == 0x015a)
2529#define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2530#define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview)
2531#define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2532#define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_cherryview && IS_GEN8(dev))
2533#define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2534#define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
2535#define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake)
2536#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2537#define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2538 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2539#define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2540 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
2541 (INTEL_DEVID(dev) & 0xf) == 0xb || \
2542 (INTEL_DEVID(dev) & 0xf) == 0xe))
2543/* ULX machines are also considered ULT. */
2544#define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \
2545 (INTEL_DEVID(dev) & 0xf) == 0xe)
2546#define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2547 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2548#define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2549 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2550#define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2551 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2552/* ULX machines are also considered ULT. */
2553#define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2554 INTEL_DEVID(dev) == 0x0A1E)
2555#define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \
2556 INTEL_DEVID(dev) == 0x1913 || \
2557 INTEL_DEVID(dev) == 0x1916 || \
2558 INTEL_DEVID(dev) == 0x1921 || \
2559 INTEL_DEVID(dev) == 0x1926)
2560#define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \
2561 INTEL_DEVID(dev) == 0x1915 || \
2562 INTEL_DEVID(dev) == 0x191E)
2563#define IS_KBL_ULT(dev) (INTEL_DEVID(dev) == 0x5906 || \
2564 INTEL_DEVID(dev) == 0x5913 || \
2565 INTEL_DEVID(dev) == 0x5916 || \
2566 INTEL_DEVID(dev) == 0x5921 || \
2567 INTEL_DEVID(dev) == 0x5926)
2568#define IS_KBL_ULX(dev) (INTEL_DEVID(dev) == 0x590E || \
2569 INTEL_DEVID(dev) == 0x5915 || \
2570 INTEL_DEVID(dev) == 0x591E)
2571#define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \
2572 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2573#define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \
2574 (INTEL_DEVID(dev) & 0x00F0) == 0x0030)
2575
2576#define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2577
2578#define SKL_REVID_A0 0x0
2579#define SKL_REVID_B0 0x1
2580#define SKL_REVID_C0 0x2
2581#define SKL_REVID_D0 0x3
2582#define SKL_REVID_E0 0x4
2583#define SKL_REVID_F0 0x5
2584
2585#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2586
2587#define BXT_REVID_A0 0x0
2588#define BXT_REVID_A1 0x1
2589#define BXT_REVID_B0 0x3
2590#define BXT_REVID_C0 0x9
2591
2592#define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
2593
2594/*
2595 * The genX designation typically refers to the render engine, so render
2596 * capability related checks should use IS_GEN, while display and other checks
2597 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2598 * chips, etc.).
2599 */
2600#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2601#define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2602#define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2603#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2604#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2605#define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
2606#define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
2607#define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
2608
2609#define RENDER_RING (1<<RCS)
2610#define BSD_RING (1<<VCS)
2611#define BLT_RING (1<<BCS)
2612#define VEBOX_RING (1<<VECS)
2613#define BSD2_RING (1<<VCS2)
2614#define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2615#define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2616#define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2617#define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2618#define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2619#define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2620 __I915__(dev)->ellc_size)
2621#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2622
2623#define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2624#define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2625#define USES_PPGTT(dev) (i915.enable_ppgtt)
2626#define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2)
2627#define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3)
2628
2629#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2630#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2631
2632/* Early gen2 have a totally busted CS tlb and require pinned batches. */
2633#define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2634
2635/* WaRsDisableCoarsePowerGating:skl,bxt */
2636#define NEEDS_WaRsDisableCoarsePowerGating(dev) (IS_BXT_REVID(dev, 0, BXT_REVID_A1) || \
2637 IS_SKL_GT3(dev) || \
2638 IS_SKL_GT4(dev))
2639
2640/*
2641 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2642 * even when in MSI mode. This results in spurious interrupt warnings if the
2643 * legacy irq no. is shared with another device. The kernel then disables that
2644 * interrupt source and so prevents the other device from working properly.
2645 */
2646#define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2647#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2648
2649/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2650 * rows, which changed the alignment requirements and fence programming.
2651 */
2652#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2653 IS_I915GM(dev)))
2654#define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2655#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2656
2657#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2658#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2659#define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2660
2661#define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2662
2663#define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2664 INTEL_INFO(dev)->gen >= 9)
2665
2666#define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2667#define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2668#define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2669 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2670 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
2671#define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2672 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
2673 IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
2674 IS_KABYLAKE(dev))
2675#define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2676#define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
2677
2678#define HAS_CSR(dev) (IS_GEN9(dev))
2679
2680#define HAS_GUC_UCODE(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev))
2681#define HAS_GUC_SCHED(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev))
2682
2683#define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
2684 INTEL_INFO(dev)->gen >= 8)
2685
2686#define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \
2687 !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
2688 !IS_BROXTON(dev))
2689
2690#define INTEL_PCH_DEVICE_ID_MASK 0xff00
2691#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2692#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2693#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2694#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2695#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2696#define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2697#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2698#define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2699#define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2700
2701#define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2702#define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2703#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2704#define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2705#define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2706#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2707#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2708#define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2709#define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2710
2711#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \
2712 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2713
2714/* DPF == dynamic parity feature */
2715#define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2716#define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2717
2718#define GT_FREQUENCY_MULTIPLIER 50
2719#define GEN9_FREQ_SCALER 3
2720
2721#include "i915_trace.h"
2722
2723extern const struct drm_ioctl_desc i915_ioctls[];
2724extern int i915_max_ioctl;
2725
2726extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
2727extern int i915_resume_switcheroo(struct drm_device *dev);
2728
2729/* i915_dma.c */
2730extern int i915_driver_load(struct drm_device *, unsigned long flags);
2731extern int i915_driver_unload(struct drm_device *);
2732extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
2733extern void i915_driver_lastclose(struct drm_device * dev);
2734extern void i915_driver_preclose(struct drm_device *dev,
2735 struct drm_file *file);
2736extern void i915_driver_postclose(struct drm_device *dev,
2737 struct drm_file *file);
2738#ifdef CONFIG_COMPAT
2739extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2740 unsigned long arg);
2741#endif
2742extern int intel_gpu_reset(struct drm_device *dev);
2743extern bool intel_has_gpu_reset(struct drm_device *dev);
2744extern int i915_reset(struct drm_device *dev);
2745extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2746extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2747extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2748extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2749int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2750
2751/* intel_hotplug.c */
2752void intel_hpd_irq_handler(struct drm_device *dev, u32 pin_mask, u32 long_mask);
2753void intel_hpd_init(struct drm_i915_private *dev_priv);
2754void intel_hpd_init_work(struct drm_i915_private *dev_priv);
2755void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2756bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
2757
2758/* i915_irq.c */
2759void i915_queue_hangcheck(struct drm_device *dev);
2760__printf(3, 4)
2761void i915_handle_error(struct drm_device *dev, bool wedged,
2762 const char *fmt, ...);
2763
2764extern void intel_irq_init(struct drm_i915_private *dev_priv);
2765int intel_irq_install(struct drm_i915_private *dev_priv);
2766void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2767
2768extern void intel_uncore_sanitize(struct drm_device *dev);
2769extern void intel_uncore_early_sanitize(struct drm_device *dev,
2770 bool restore_forcewake);
2771extern void intel_uncore_init(struct drm_device *dev);
2772extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
2773extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
2774extern void intel_uncore_fini(struct drm_device *dev);
2775extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
2776const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
2777void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
2778 enum forcewake_domains domains);
2779void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
2780 enum forcewake_domains domains);
2781/* Like above but the caller must manage the uncore.lock itself.
2782 * Must be used with I915_READ_FW and friends.
2783 */
2784void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
2785 enum forcewake_domains domains);
2786void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
2787 enum forcewake_domains domains);
2788void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
2789static inline bool intel_vgpu_active(struct drm_device *dev)
2790{
2791 return to_i915(dev)->vgpu.active;
2792}
2793
2794void
2795i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2796 u32 status_mask);
2797
2798void
2799i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2800 u32 status_mask);
2801
2802void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2803void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2804void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
2805 uint32_t mask,
2806 uint32_t bits);
2807void ilk_update_display_irq(struct drm_i915_private *dev_priv,
2808 uint32_t interrupt_mask,
2809 uint32_t enabled_irq_mask);
2810static inline void
2811ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2812{
2813 ilk_update_display_irq(dev_priv, bits, bits);
2814}
2815static inline void
2816ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2817{
2818 ilk_update_display_irq(dev_priv, bits, 0);
2819}
2820void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
2821 enum pipe pipe,
2822 uint32_t interrupt_mask,
2823 uint32_t enabled_irq_mask);
2824static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
2825 enum pipe pipe, uint32_t bits)
2826{
2827 bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
2828}
2829static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
2830 enum pipe pipe, uint32_t bits)
2831{
2832 bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
2833}
2834void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2835 uint32_t interrupt_mask,
2836 uint32_t enabled_irq_mask);
2837static inline void
2838ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
2839{
2840 ibx_display_interrupt_update(dev_priv, bits, bits);
2841}
2842static inline void
2843ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
2844{
2845 ibx_display_interrupt_update(dev_priv, bits, 0);
2846}
2847
2848
2849/* i915_gem.c */
2850int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2851 struct drm_file *file_priv);
2852int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2853 struct drm_file *file_priv);
2854int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2855 struct drm_file *file_priv);
2856int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2857 struct drm_file *file_priv);
2858int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2859 struct drm_file *file_priv);
2860int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2861 struct drm_file *file_priv);
2862int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2863 struct drm_file *file_priv);
2864void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
2865 struct drm_i915_gem_request *req);
2866void i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params);
2867int i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
2868 struct drm_i915_gem_execbuffer2 *args,
2869 struct list_head *vmas);
2870int i915_gem_execbuffer(struct drm_device *dev, void *data,
2871 struct drm_file *file_priv);
2872int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2873 struct drm_file *file_priv);
2874int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2875 struct drm_file *file_priv);
2876int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2877 struct drm_file *file);
2878int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2879 struct drm_file *file);
2880int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2881 struct drm_file *file_priv);
2882int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2883 struct drm_file *file_priv);
2884int i915_gem_set_tiling(struct drm_device *dev, void *data,
2885 struct drm_file *file_priv);
2886int i915_gem_get_tiling(struct drm_device *dev, void *data,
2887 struct drm_file *file_priv);
2888int i915_gem_init_userptr(struct drm_device *dev);
2889int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2890 struct drm_file *file);
2891int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2892 struct drm_file *file_priv);
2893int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2894 struct drm_file *file_priv);
2895void i915_gem_load_init(struct drm_device *dev);
2896void i915_gem_load_cleanup(struct drm_device *dev);
2897void *i915_gem_object_alloc(struct drm_device *dev);
2898void i915_gem_object_free(struct drm_i915_gem_object *obj);
2899void i915_gem_object_init(struct drm_i915_gem_object *obj,
2900 const struct drm_i915_gem_object_ops *ops);
2901struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2902 size_t size);
2903struct drm_i915_gem_object *i915_gem_object_create_from_data(
2904 struct drm_device *dev, const void *data, size_t size);
2905void i915_gem_free_object(struct drm_gem_object *obj);
2906void i915_gem_vma_destroy(struct i915_vma *vma);
2907
2908/* Flags used by pin/bind&friends. */
2909#define PIN_MAPPABLE (1<<0)
2910#define PIN_NONBLOCK (1<<1)
2911#define PIN_GLOBAL (1<<2)
2912#define PIN_OFFSET_BIAS (1<<3)
2913#define PIN_USER (1<<4)
2914#define PIN_UPDATE (1<<5)
2915#define PIN_ZONE_4G (1<<6)
2916#define PIN_HIGH (1<<7)
2917#define PIN_OFFSET_FIXED (1<<8)
2918#define PIN_OFFSET_MASK (~4095)
2919int __must_check
2920i915_gem_object_pin(struct drm_i915_gem_object *obj,
2921 struct i915_address_space *vm,
2922 uint32_t alignment,
2923 uint64_t flags);
2924int __must_check
2925i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
2926 const struct i915_ggtt_view *view,
2927 uint32_t alignment,
2928 uint64_t flags);
2929
2930int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2931 u32 flags);
2932void __i915_vma_set_map_and_fenceable(struct i915_vma *vma);
2933int __must_check i915_vma_unbind(struct i915_vma *vma);
2934/*
2935 * BEWARE: Do not use the function below unless you can _absolutely_
2936 * _guarantee_ VMA in question is _not in use_ anywhere.
2937 */
2938int __must_check __i915_vma_unbind_no_wait(struct i915_vma *vma);
2939int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2940void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2941void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2942
2943int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2944 int *needs_clflush);
2945
2946int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2947
2948static inline int __sg_page_count(struct scatterlist *sg)
2949{
2950 return sg->length >> PAGE_SHIFT;
2951}
2952
2953struct page *
2954i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n);
2955
2956static inline struct page *
2957i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2958{
2959 if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT))
2960 return NULL;
2961
2962 if (n < obj->get_page.last) {
2963 obj->get_page.sg = obj->pages->sgl;
2964 obj->get_page.last = 0;
2965 }
2966
2967 while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
2968 obj->get_page.last += __sg_page_count(obj->get_page.sg++);
2969 if (unlikely(sg_is_chain(obj->get_page.sg)))
2970 obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
2971 }
2972
2973 return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last);
2974}
2975
2976static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2977{
2978 BUG_ON(obj->pages == NULL);
2979 obj->pages_pin_count++;
2980}
2981static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2982{
2983 BUG_ON(obj->pages_pin_count == 0);
2984 obj->pages_pin_count--;
2985}
2986
2987int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2988int i915_gem_object_sync(struct drm_i915_gem_object *obj,
2989 struct intel_engine_cs *to,
2990 struct drm_i915_gem_request **to_req);
2991void i915_vma_move_to_active(struct i915_vma *vma,
2992 struct drm_i915_gem_request *req);
2993int i915_gem_dumb_create(struct drm_file *file_priv,
2994 struct drm_device *dev,
2995 struct drm_mode_create_dumb *args);
2996int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2997 uint32_t handle, uint64_t *offset);
2998/**
2999 * Returns true if seq1 is later than seq2.
3000 */
3001static inline bool
3002i915_seqno_passed(uint32_t seq1, uint32_t seq2)
3003{
3004 return (int32_t)(seq1 - seq2) >= 0;
3005}
3006
3007static inline bool i915_gem_request_started(struct drm_i915_gem_request *req,
3008 bool lazy_coherency)
3009{
3010 u32 seqno = req->ring->get_seqno(req->ring, lazy_coherency);
3011 return i915_seqno_passed(seqno, req->previous_seqno);
3012}
3013
3014static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
3015 bool lazy_coherency)
3016{
3017 u32 seqno = req->ring->get_seqno(req->ring, lazy_coherency);
3018 return i915_seqno_passed(seqno, req->seqno);
3019}
3020
3021int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
3022int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
3023
3024struct drm_i915_gem_request *
3025i915_gem_find_active_request(struct intel_engine_cs *ring);
3026
3027bool i915_gem_retire_requests(struct drm_device *dev);
3028void i915_gem_retire_requests_ring(struct intel_engine_cs *ring);
3029int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
3030 bool interruptible);
3031
3032static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
3033{
3034 return unlikely(atomic_read(&error->reset_counter)
3035 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
3036}
3037
3038static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3039{
3040 return atomic_read(&error->reset_counter) & I915_WEDGED;
3041}
3042
3043static inline u32 i915_reset_count(struct i915_gpu_error *error)
3044{
3045 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
3046}
3047
3048static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
3049{
3050 return dev_priv->gpu_error.stop_rings == 0 ||
3051 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
3052}
3053
3054static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
3055{
3056 return dev_priv->gpu_error.stop_rings == 0 ||
3057 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
3058}
3059
3060void i915_gem_reset(struct drm_device *dev);
3061bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
3062int __must_check i915_gem_init(struct drm_device *dev);
3063int i915_gem_init_rings(struct drm_device *dev);
3064int __must_check i915_gem_init_hw(struct drm_device *dev);
3065int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice);
3066void i915_gem_init_swizzling(struct drm_device *dev);
3067void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
3068int __must_check i915_gpu_idle(struct drm_device *dev);
3069int __must_check i915_gem_suspend(struct drm_device *dev);
3070void __i915_add_request(struct drm_i915_gem_request *req,
3071 struct drm_i915_gem_object *batch_obj,
3072 bool flush_caches);
3073#define i915_add_request(req) \
3074 __i915_add_request(req, NULL, true)
3075#define i915_add_request_no_flush(req) \
3076 __i915_add_request(req, NULL, false)
3077int __i915_wait_request(struct drm_i915_gem_request *req,
3078 unsigned reset_counter,
3079 bool interruptible,
3080 s64 *timeout,
3081 struct intel_rps_client *rps);
3082int __must_check i915_wait_request(struct drm_i915_gem_request *req);
3083int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
3084int __must_check
3085i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
3086 bool readonly);
3087int __must_check
3088i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
3089 bool write);
3090int __must_check
3091i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3092int __must_check
3093i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3094 u32 alignment,
3095 const struct i915_ggtt_view *view);
3096void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
3097 const struct i915_ggtt_view *view);
3098int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3099 int align);
3100int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3101void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3102
3103uint32_t
3104i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
3105uint32_t
3106i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
3107 int tiling_mode, bool fenced);
3108
3109int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3110 enum i915_cache_level cache_level);
3111
3112struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3113 struct dma_buf *dma_buf);
3114
3115struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3116 struct drm_gem_object *gem_obj, int flags);
3117
3118u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
3119 const struct i915_ggtt_view *view);
3120u64 i915_gem_obj_offset(struct drm_i915_gem_object *o,
3121 struct i915_address_space *vm);
3122static inline u64
3123i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o)
3124{
3125 return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal);
3126}
3127
3128bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
3129bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
3130 const struct i915_ggtt_view *view);
3131bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
3132 struct i915_address_space *vm);
3133
3134unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
3135 struct i915_address_space *vm);
3136struct i915_vma *
3137i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
3138 struct i915_address_space *vm);
3139struct i915_vma *
3140i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
3141 const struct i915_ggtt_view *view);
3142
3143struct i915_vma *
3144i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
3145 struct i915_address_space *vm);
3146struct i915_vma *
3147i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
3148 const struct i915_ggtt_view *view);
3149
3150static inline struct i915_vma *
3151i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
3152{
3153 return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal);
3154}
3155bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj);
3156
3157/* Some GGTT VM helpers */
3158#define i915_obj_to_ggtt(obj) \
3159 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
3160
3161static inline struct i915_hw_ppgtt *
3162i915_vm_to_ppgtt(struct i915_address_space *vm)
3163{
3164 WARN_ON(i915_is_ggtt(vm));
3165 return container_of(vm, struct i915_hw_ppgtt, base);
3166}
3167
3168
3169static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
3170{
3171 return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal);
3172}
3173
3174static inline unsigned long
3175i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
3176{
3177 return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
3178}
3179
3180static inline int __must_check
3181i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
3182 uint32_t alignment,
3183 unsigned flags)
3184{
3185 return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj),
3186 alignment, flags | PIN_GLOBAL);
3187}
3188
3189static inline int
3190i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
3191{
3192 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
3193}
3194
3195void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
3196 const struct i915_ggtt_view *view);
3197static inline void
3198i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
3199{
3200 i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal);
3201}
3202
3203/* i915_gem_fence.c */
3204int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
3205int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
3206
3207bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
3208void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
3209
3210void i915_gem_restore_fences(struct drm_device *dev);
3211
3212void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
3213void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
3214void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
3215
3216/* i915_gem_context.c */
3217int __must_check i915_gem_context_init(struct drm_device *dev);
3218void i915_gem_context_fini(struct drm_device *dev);
3219void i915_gem_context_reset(struct drm_device *dev);
3220int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
3221int i915_gem_context_enable(struct drm_i915_gem_request *req);
3222void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
3223int i915_switch_context(struct drm_i915_gem_request *req);
3224struct intel_context *
3225i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
3226void i915_gem_context_free(struct kref *ctx_ref);
3227struct drm_i915_gem_object *
3228i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
3229static inline void i915_gem_context_reference(struct intel_context *ctx)
3230{
3231 kref_get(&ctx->ref);
3232}
3233
3234static inline void i915_gem_context_unreference(struct intel_context *ctx)
3235{
3236 kref_put(&ctx->ref, i915_gem_context_free);
3237}
3238
3239static inline bool i915_gem_context_is_default(const struct intel_context *c)
3240{
3241 return c->user_handle == DEFAULT_CONTEXT_HANDLE;
3242}
3243
3244int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
3245 struct drm_file *file);
3246int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
3247 struct drm_file *file);
3248int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
3249 struct drm_file *file_priv);
3250int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
3251 struct drm_file *file_priv);
3252
3253/* i915_gem_evict.c */
3254int __must_check i915_gem_evict_something(struct drm_device *dev,
3255 struct i915_address_space *vm,
3256 int min_size,
3257 unsigned alignment,
3258 unsigned cache_level,
3259 unsigned long start,
3260 unsigned long end,
3261 unsigned flags);
3262int __must_check i915_gem_evict_for_vma(struct i915_vma *target);
3263int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3264
3265/* belongs in i915_gem_gtt.h */
3266static inline void i915_gem_chipset_flush(struct drm_device *dev)
3267{
3268 if (INTEL_INFO(dev)->gen < 6)
3269 intel_gtt_chipset_flush();
3270}
3271
3272/* i915_gem_stolen.c */
3273int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3274 struct drm_mm_node *node, u64 size,
3275 unsigned alignment);
3276int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3277 struct drm_mm_node *node, u64 size,
3278 unsigned alignment, u64 start,
3279 u64 end);
3280void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3281 struct drm_mm_node *node);
3282int i915_gem_init_stolen(struct drm_device *dev);
3283void i915_gem_cleanup_stolen(struct drm_device *dev);
3284struct drm_i915_gem_object *
3285i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
3286struct drm_i915_gem_object *
3287i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
3288 u32 stolen_offset,
3289 u32 gtt_offset,
3290 u32 size);
3291
3292/* i915_gem_shrinker.c */
3293unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3294 unsigned long target,
3295 unsigned flags);
3296#define I915_SHRINK_PURGEABLE 0x1
3297#define I915_SHRINK_UNBOUND 0x2
3298#define I915_SHRINK_BOUND 0x4
3299#define I915_SHRINK_ACTIVE 0x8
3300unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3301void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3302void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
3303
3304
3305/* i915_gem_tiling.c */
3306static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3307{
3308 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3309
3310 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3311 obj->tiling_mode != I915_TILING_NONE;
3312}
3313
3314/* i915_gem_debug.c */
3315#if WATCH_LISTS
3316int i915_verify_lists(struct drm_device *dev);
3317#else
3318#define i915_verify_lists(dev) 0
3319#endif
3320
3321/* i915_debugfs.c */
3322int i915_debugfs_init(struct drm_minor *minor);
3323void i915_debugfs_cleanup(struct drm_minor *minor);
3324#ifdef CONFIG_DEBUG_FS
3325int i915_debugfs_connector_add(struct drm_connector *connector);
3326void intel_display_crc_init(struct drm_device *dev);
3327#else
3328static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3329{ return 0; }
3330static inline void intel_display_crc_init(struct drm_device *dev) {}
3331#endif
3332
3333/* i915_gpu_error.c */
3334__printf(2, 3)
3335void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3336int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3337 const struct i915_error_state_file_priv *error);
3338int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3339 struct drm_i915_private *i915,
3340 size_t count, loff_t pos);
3341static inline void i915_error_state_buf_release(
3342 struct drm_i915_error_state_buf *eb)
3343{
3344 kfree(eb->buf);
3345}
3346void i915_capture_error_state(struct drm_device *dev, bool wedge,
3347 const char *error_msg);
3348void i915_error_state_get(struct drm_device *dev,
3349 struct i915_error_state_file_priv *error_priv);
3350void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
3351void i915_destroy_error_state(struct drm_device *dev);
3352
3353void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
3354const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3355
3356/* i915_cmd_parser.c */
3357int i915_cmd_parser_get_version(void);
3358int i915_cmd_parser_init_ring(struct intel_engine_cs *ring);
3359void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring);
3360bool i915_needs_cmd_parser(struct intel_engine_cs *ring);
3361int i915_parse_cmds(struct intel_engine_cs *ring,
3362 struct drm_i915_gem_object *batch_obj,
3363 struct drm_i915_gem_object *shadow_batch_obj,
3364 u32 batch_start_offset,
3365 u32 batch_len,
3366 bool is_master);
3367
3368/* i915_suspend.c */
3369extern int i915_save_state(struct drm_device *dev);
3370extern int i915_restore_state(struct drm_device *dev);
3371
3372/* i915_sysfs.c */
3373void i915_setup_sysfs(struct drm_device *dev_priv);
3374void i915_teardown_sysfs(struct drm_device *dev_priv);
3375
3376/* intel_i2c.c */
3377extern int intel_setup_gmbus(struct drm_device *dev);
3378extern void intel_teardown_gmbus(struct drm_device *dev);
3379extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3380 unsigned int pin);
3381
3382extern struct i2c_adapter *
3383intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3384extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3385extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3386static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3387{
3388 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3389}
3390extern void intel_i2c_reset(struct drm_device *dev);
3391
3392/* intel_bios.c */
3393int intel_bios_init(struct drm_i915_private *dev_priv);
3394bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3395
3396/* intel_opregion.c */
3397#ifdef CONFIG_ACPI
3398extern int intel_opregion_setup(struct drm_device *dev);
3399extern void intel_opregion_init(struct drm_device *dev);
3400extern void intel_opregion_fini(struct drm_device *dev);
3401extern void intel_opregion_asle_intr(struct drm_device *dev);
3402extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3403 bool enable);
3404extern int intel_opregion_notify_adapter(struct drm_device *dev,
3405 pci_power_t state);
3406#else
3407static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
3408static inline void intel_opregion_init(struct drm_device *dev) { return; }
3409static inline void intel_opregion_fini(struct drm_device *dev) { return; }
3410static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
3411static inline int
3412intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3413{
3414 return 0;
3415}
3416static inline int
3417intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
3418{
3419 return 0;
3420}
3421#endif
3422
3423/* intel_acpi.c */
3424#ifdef CONFIG_ACPI
3425extern void intel_register_dsm_handler(void);
3426extern void intel_unregister_dsm_handler(void);
3427#else
3428static inline void intel_register_dsm_handler(void) { return; }
3429static inline void intel_unregister_dsm_handler(void) { return; }
3430#endif /* CONFIG_ACPI */
3431
3432/* modesetting */
3433extern void intel_modeset_init_hw(struct drm_device *dev);
3434extern void intel_modeset_init(struct drm_device *dev);
3435extern void intel_modeset_gem_init(struct drm_device *dev);
3436extern void intel_modeset_cleanup(struct drm_device *dev);
3437extern void intel_connector_unregister(struct intel_connector *);
3438extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
3439extern void intel_display_resume(struct drm_device *dev);
3440extern void i915_redisable_vga(struct drm_device *dev);
3441extern void i915_redisable_vga_power_on(struct drm_device *dev);
3442extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
3443extern void intel_init_pch_refclk(struct drm_device *dev);
3444extern void intel_set_rps(struct drm_device *dev, u8 val);
3445extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3446 bool enable);
3447extern void intel_detect_pch(struct drm_device *dev);
3448extern int intel_enable_rc6(const struct drm_device *dev);
3449
3450extern bool i915_semaphore_is_enabled(struct drm_device *dev);
3451int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3452 struct drm_file *file);
3453int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
3454 struct drm_file *file);
3455
3456/* overlay */
3457extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
3458extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3459 struct intel_overlay_error_state *error);
3460
3461extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
3462extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3463 struct drm_device *dev,
3464 struct intel_display_error_state *error);
3465
3466int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3467int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3468
3469/* intel_sideband.c */
3470u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3471void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3472u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3473u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
3474void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3475u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3476void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3477u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3478void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3479u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3480void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3481u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3482void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3483u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3484 enum intel_sbi_destination destination);
3485void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3486 enum intel_sbi_destination destination);
3487u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3488void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3489
3490int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3491int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3492
3493#define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3494#define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3495
3496#define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3497#define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3498#define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3499#define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3500
3501#define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3502#define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3503#define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3504#define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3505
3506/* Be very careful with read/write 64-bit values. On 32-bit machines, they
3507 * will be implemented using 2 32-bit writes in an arbitrary order with
3508 * an arbitrary delay between them. This can cause the hardware to
3509 * act upon the intermediate value, possibly leading to corruption and
3510 * machine death. You have been warned.
3511 */
3512#define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3513#define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3514
3515#define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3516 u32 upper, lower, old_upper, loop = 0; \
3517 upper = I915_READ(upper_reg); \
3518 do { \
3519 old_upper = upper; \
3520 lower = I915_READ(lower_reg); \
3521 upper = I915_READ(upper_reg); \
3522 } while (upper != old_upper && loop++ < 2); \
3523 (u64)upper << 32 | lower; })
3524
3525#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3526#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3527
3528#define __raw_read(x, s) \
3529static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3530 i915_reg_t reg) \
3531{ \
3532 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3533}
3534
3535#define __raw_write(x, s) \
3536static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3537 i915_reg_t reg, uint##x##_t val) \
3538{ \
3539 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3540}
3541__raw_read(8, b)
3542__raw_read(16, w)
3543__raw_read(32, l)
3544__raw_read(64, q)
3545
3546__raw_write(8, b)
3547__raw_write(16, w)
3548__raw_write(32, l)
3549__raw_write(64, q)
3550
3551#undef __raw_read
3552#undef __raw_write
3553
3554/* These are untraced mmio-accessors that are only valid to be used inside
3555 * criticial sections inside IRQ handlers where forcewake is explicitly
3556 * controlled.
3557 * Think twice, and think again, before using these.
3558 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3559 * intel_uncore_forcewake_irqunlock().
3560 */
3561#define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3562#define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3563#define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3564
3565/* "Broadcast RGB" property */
3566#define INTEL_BROADCAST_RGB_AUTO 0
3567#define INTEL_BROADCAST_RGB_FULL 1
3568#define INTEL_BROADCAST_RGB_LIMITED 2
3569
3570static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev)
3571{
3572 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
3573 return VLV_VGACNTRL;
3574 else if (INTEL_INFO(dev)->gen >= 5)
3575 return CPU_VGACNTRL;
3576 else
3577 return VGACNTRL;
3578}
3579
3580static inline void __user *to_user_ptr(u64 address)
3581{
3582 return (void __user *)(uintptr_t)address;
3583}
3584
3585static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3586{
3587 unsigned long j = msecs_to_jiffies(m);
3588
3589 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3590}
3591
3592static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3593{
3594 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3595}
3596
3597static inline unsigned long
3598timespec_to_jiffies_timeout(const struct timespec *value)
3599{
3600 unsigned long j = timespec_to_jiffies(value);
3601
3602 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3603}
3604
3605/*
3606 * If you need to wait X milliseconds between events A and B, but event B
3607 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3608 * when event A happened, then just before event B you call this function and
3609 * pass the timestamp as the first argument, and X as the second argument.
3610 */
3611static inline void
3612wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3613{
3614 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3615
3616 /*
3617 * Don't re-read the value of "jiffies" every time since it may change
3618 * behind our back and break the math.
3619 */
3620 tmp_jiffies = jiffies;
3621 target_jiffies = timestamp_jiffies +
3622 msecs_to_jiffies_timeout(to_wait_ms);
3623
3624 if (time_after(target_jiffies, tmp_jiffies)) {
3625 remaining_jiffies = target_jiffies - tmp_jiffies;
3626 while (remaining_jiffies)
3627 remaining_jiffies =
3628 schedule_timeout_uninterruptible(remaining_jiffies);
3629 }
3630}
3631
3632static inline void i915_trace_irq_get(struct intel_engine_cs *ring,
3633 struct drm_i915_gem_request *req)
3634{
3635 if (ring->trace_irq_req == NULL && ring->irq_get(ring))
3636 i915_gem_request_assign(&ring->trace_irq_req, req);
3637}
3638
3639#endif
1/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
3/*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
33#include <uapi/drm/i915_drm.h>
34#include <uapi/drm/drm_fourcc.h>
35
36#include <linux/io-mapping.h>
37#include <linux/i2c.h>
38#include <linux/i2c-algo-bit.h>
39#include <linux/backlight.h>
40#include <linux/hash.h>
41#include <linux/intel-iommu.h>
42#include <linux/kref.h>
43#include <linux/mm_types.h>
44#include <linux/perf_event.h>
45#include <linux/pm_qos.h>
46#include <linux/dma-resv.h>
47#include <linux/shmem_fs.h>
48#include <linux/stackdepot.h>
49
50#include <drm/intel-gtt.h>
51#include <drm/drm_legacy.h> /* for struct drm_dma_handle */
52#include <drm/drm_gem.h>
53#include <drm/drm_auth.h>
54#include <drm/drm_cache.h>
55#include <drm/drm_util.h>
56#include <drm/drm_dsc.h>
57#include <drm/drm_atomic.h>
58#include <drm/drm_connector.h>
59#include <drm/i915_mei_hdcp_interface.h>
60
61#include "i915_fixed.h"
62#include "i915_params.h"
63#include "i915_reg.h"
64#include "i915_utils.h"
65
66#include "display/intel_bios.h"
67#include "display/intel_display.h"
68#include "display/intel_display_power.h"
69#include "display/intel_dpll_mgr.h"
70#include "display/intel_frontbuffer.h"
71#include "display/intel_gmbus.h"
72#include "display/intel_opregion.h"
73
74#include "gem/i915_gem_context_types.h"
75#include "gem/i915_gem_shrinker.h"
76#include "gem/i915_gem_stolen.h"
77
78#include "gt/intel_lrc.h"
79#include "gt/intel_engine.h"
80#include "gt/intel_gt_types.h"
81#include "gt/intel_workarounds.h"
82#include "gt/uc/intel_uc.h"
83
84#include "intel_device_info.h"
85#include "intel_pch.h"
86#include "intel_runtime_pm.h"
87#include "intel_uncore.h"
88#include "intel_wakeref.h"
89#include "intel_wopcm.h"
90
91#include "i915_gem.h"
92#include "i915_gem_fence_reg.h"
93#include "i915_gem_gtt.h"
94#include "i915_gpu_error.h"
95#include "i915_request.h"
96#include "i915_scheduler.h"
97#include "gt/intel_timeline.h"
98#include "i915_vma.h"
99#include "i915_irq.h"
100
101#include "intel_gvt.h"
102
103/* General customization:
104 */
105
106#define DRIVER_NAME "i915"
107#define DRIVER_DESC "Intel Graphics"
108#define DRIVER_DATE "20190822"
109#define DRIVER_TIMESTAMP 1566477988
110
111struct drm_i915_gem_object;
112
113enum hpd_pin {
114 HPD_NONE = 0,
115 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
116 HPD_CRT,
117 HPD_SDVO_B,
118 HPD_SDVO_C,
119 HPD_PORT_A,
120 HPD_PORT_B,
121 HPD_PORT_C,
122 HPD_PORT_D,
123 HPD_PORT_E,
124 HPD_PORT_F,
125 HPD_PORT_G,
126 HPD_PORT_H,
127 HPD_PORT_I,
128
129 HPD_NUM_PINS
130};
131
132#define for_each_hpd_pin(__pin) \
133 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
134
135/* Threshold == 5 for long IRQs, 50 for short */
136#define HPD_STORM_DEFAULT_THRESHOLD 50
137
138struct i915_hotplug {
139 struct delayed_work hotplug_work;
140
141 struct {
142 unsigned long last_jiffies;
143 int count;
144 enum {
145 HPD_ENABLED = 0,
146 HPD_DISABLED = 1,
147 HPD_MARK_DISABLED = 2
148 } state;
149 } stats[HPD_NUM_PINS];
150 u32 event_bits;
151 u32 retry_bits;
152 struct delayed_work reenable_work;
153
154 u32 long_port_mask;
155 u32 short_port_mask;
156 struct work_struct dig_port_work;
157
158 struct work_struct poll_init_work;
159 bool poll_enabled;
160
161 unsigned int hpd_storm_threshold;
162 /* Whether or not to count short HPD IRQs in HPD storms */
163 u8 hpd_short_storm_enabled;
164
165 /*
166 * if we get a HPD irq from DP and a HPD irq from non-DP
167 * the non-DP HPD could block the workqueue on a mode config
168 * mutex getting, that userspace may have taken. However
169 * userspace is waiting on the DP workqueue to run which is
170 * blocked behind the non-DP one.
171 */
172 struct workqueue_struct *dp_wq;
173};
174
175#define I915_GEM_GPU_DOMAINS \
176 (I915_GEM_DOMAIN_RENDER | \
177 I915_GEM_DOMAIN_SAMPLER | \
178 I915_GEM_DOMAIN_COMMAND | \
179 I915_GEM_DOMAIN_INSTRUCTION | \
180 I915_GEM_DOMAIN_VERTEX)
181
182struct drm_i915_private;
183struct i915_mm_struct;
184struct i915_mmu_object;
185
186struct drm_i915_file_private {
187 struct drm_i915_private *dev_priv;
188 struct drm_file *file;
189
190 struct {
191 spinlock_t lock;
192 struct list_head request_list;
193 } mm;
194
195 struct idr context_idr;
196 struct mutex context_idr_lock; /* guards context_idr */
197
198 struct idr vm_idr;
199 struct mutex vm_idr_lock; /* guards vm_idr */
200
201 unsigned int bsd_engine;
202
203/*
204 * Every context ban increments per client ban score. Also
205 * hangs in short succession increments ban score. If ban threshold
206 * is reached, client is considered banned and submitting more work
207 * will fail. This is a stop gap measure to limit the badly behaving
208 * clients access to gpu. Note that unbannable contexts never increment
209 * the client ban score.
210 */
211#define I915_CLIENT_SCORE_HANG_FAST 1
212#define I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ)
213#define I915_CLIENT_SCORE_CONTEXT_BAN 3
214#define I915_CLIENT_SCORE_BANNED 9
215 /** ban_score: Accumulated score of all ctx bans and fast hangs. */
216 atomic_t ban_score;
217 unsigned long hang_timestamp;
218};
219
220/* Interface history:
221 *
222 * 1.1: Original.
223 * 1.2: Add Power Management
224 * 1.3: Add vblank support
225 * 1.4: Fix cmdbuffer path, add heap destroy
226 * 1.5: Add vblank pipe configuration
227 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
228 * - Support vertical blank on secondary display pipe
229 */
230#define DRIVER_MAJOR 1
231#define DRIVER_MINOR 6
232#define DRIVER_PATCHLEVEL 0
233
234struct intel_overlay;
235struct intel_overlay_error_state;
236
237struct sdvo_device_mapping {
238 u8 initialized;
239 u8 dvo_port;
240 u8 slave_addr;
241 u8 dvo_wiring;
242 u8 i2c_pin;
243 u8 ddc_pin;
244};
245
246struct intel_connector;
247struct intel_encoder;
248struct intel_atomic_state;
249struct intel_crtc_state;
250struct intel_initial_plane_config;
251struct intel_crtc;
252struct intel_limit;
253struct dpll;
254struct intel_cdclk_state;
255
256struct drm_i915_display_funcs {
257 void (*get_cdclk)(struct drm_i915_private *dev_priv,
258 struct intel_cdclk_state *cdclk_state);
259 void (*set_cdclk)(struct drm_i915_private *dev_priv,
260 const struct intel_cdclk_state *cdclk_state,
261 enum pipe pipe);
262 int (*get_fifo_size)(struct drm_i915_private *dev_priv,
263 enum i9xx_plane_id i9xx_plane);
264 int (*compute_pipe_wm)(struct intel_crtc_state *crtc_state);
265 int (*compute_intermediate_wm)(struct intel_crtc_state *crtc_state);
266 void (*initial_watermarks)(struct intel_atomic_state *state,
267 struct intel_crtc_state *crtc_state);
268 void (*atomic_update_watermarks)(struct intel_atomic_state *state,
269 struct intel_crtc_state *crtc_state);
270 void (*optimize_watermarks)(struct intel_atomic_state *state,
271 struct intel_crtc_state *crtc_state);
272 int (*compute_global_watermarks)(struct intel_atomic_state *state);
273 void (*update_wm)(struct intel_crtc *crtc);
274 int (*modeset_calc_cdclk)(struct intel_atomic_state *state);
275 /* Returns the active state of the crtc, and if the crtc is active,
276 * fills out the pipe-config with the hw state. */
277 bool (*get_pipe_config)(struct intel_crtc *,
278 struct intel_crtc_state *);
279 void (*get_initial_plane_config)(struct intel_crtc *,
280 struct intel_initial_plane_config *);
281 int (*crtc_compute_clock)(struct intel_crtc *crtc,
282 struct intel_crtc_state *crtc_state);
283 void (*crtc_enable)(struct intel_crtc_state *pipe_config,
284 struct intel_atomic_state *old_state);
285 void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
286 struct intel_atomic_state *old_state);
287 void (*update_crtcs)(struct intel_atomic_state *state);
288 void (*audio_codec_enable)(struct intel_encoder *encoder,
289 const struct intel_crtc_state *crtc_state,
290 const struct drm_connector_state *conn_state);
291 void (*audio_codec_disable)(struct intel_encoder *encoder,
292 const struct intel_crtc_state *old_crtc_state,
293 const struct drm_connector_state *old_conn_state);
294 void (*fdi_link_train)(struct intel_crtc *crtc,
295 const struct intel_crtc_state *crtc_state);
296 void (*init_clock_gating)(struct drm_i915_private *dev_priv);
297 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
298 /* clock updates for mode set */
299 /* cursor updates */
300 /* render clock increase/decrease */
301 /* display clock increase/decrease */
302 /* pll clock increase/decrease */
303
304 int (*color_check)(struct intel_crtc_state *crtc_state);
305 /*
306 * Program double buffered color management registers during
307 * vblank evasion. The registers should then latch during the
308 * next vblank start, alongside any other double buffered registers
309 * involved with the same commit.
310 */
311 void (*color_commit)(const struct intel_crtc_state *crtc_state);
312 /*
313 * Load LUTs (and other single buffered color management
314 * registers). Will (hopefully) be called during the vblank
315 * following the latching of any double buffered registers
316 * involved with the same commit.
317 */
318 void (*load_luts)(const struct intel_crtc_state *crtc_state);
319 void (*read_luts)(struct intel_crtc_state *crtc_state);
320};
321
322struct intel_csr {
323 struct work_struct work;
324 const char *fw_path;
325 u32 required_version;
326 u32 max_fw_size; /* bytes */
327 u32 *dmc_payload;
328 u32 dmc_fw_size; /* dwords */
329 u32 version;
330 u32 mmio_count;
331 i915_reg_t mmioaddr[20];
332 u32 mmiodata[20];
333 u32 dc_state;
334 u32 allowed_dc_mask;
335 intel_wakeref_t wakeref;
336};
337
338enum i915_cache_level {
339 I915_CACHE_NONE = 0,
340 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
341 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
342 caches, eg sampler/render caches, and the
343 large Last-Level-Cache. LLC is coherent with
344 the CPU, but L3 is only visible to the GPU. */
345 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
346};
347
348#define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
349
350struct intel_fbc {
351 /* This is always the inner lock when overlapping with struct_mutex and
352 * it's the outer lock when overlapping with stolen_lock. */
353 struct mutex lock;
354 unsigned threshold;
355 unsigned int possible_framebuffer_bits;
356 unsigned int busy_bits;
357 unsigned int visible_pipes_mask;
358 struct intel_crtc *crtc;
359
360 struct drm_mm_node compressed_fb;
361 struct drm_mm_node *compressed_llb;
362
363 bool false_color;
364
365 bool enabled;
366 bool active;
367 bool flip_pending;
368
369 bool underrun_detected;
370 struct work_struct underrun_work;
371
372 /*
373 * Due to the atomic rules we can't access some structures without the
374 * appropriate locking, so we cache information here in order to avoid
375 * these problems.
376 */
377 struct intel_fbc_state_cache {
378 struct i915_vma *vma;
379 unsigned long flags;
380
381 struct {
382 unsigned int mode_flags;
383 u32 hsw_bdw_pixel_rate;
384 } crtc;
385
386 struct {
387 unsigned int rotation;
388 int src_w;
389 int src_h;
390 bool visible;
391 /*
392 * Display surface base address adjustement for
393 * pageflips. Note that on gen4+ this only adjusts up
394 * to a tile, offsets within a tile are handled in
395 * the hw itself (with the TILEOFF register).
396 */
397 int adjusted_x;
398 int adjusted_y;
399
400 int y;
401
402 u16 pixel_blend_mode;
403 } plane;
404
405 struct {
406 const struct drm_format_info *format;
407 unsigned int stride;
408 } fb;
409 } state_cache;
410
411 /*
412 * This structure contains everything that's relevant to program the
413 * hardware registers. When we want to figure out if we need to disable
414 * and re-enable FBC for a new configuration we just check if there's
415 * something different in the struct. The genx_fbc_activate functions
416 * are supposed to read from it in order to program the registers.
417 */
418 struct intel_fbc_reg_params {
419 struct i915_vma *vma;
420 unsigned long flags;
421
422 struct {
423 enum pipe pipe;
424 enum i9xx_plane_id i9xx_plane;
425 unsigned int fence_y_offset;
426 } crtc;
427
428 struct {
429 const struct drm_format_info *format;
430 unsigned int stride;
431 } fb;
432
433 int cfb_size;
434 unsigned int gen9_wa_cfb_stride;
435 } params;
436
437 const char *no_fbc_reason;
438};
439
440/*
441 * HIGH_RR is the highest eDP panel refresh rate read from EDID
442 * LOW_RR is the lowest eDP panel refresh rate found from EDID
443 * parsing for same resolution.
444 */
445enum drrs_refresh_rate_type {
446 DRRS_HIGH_RR,
447 DRRS_LOW_RR,
448 DRRS_MAX_RR, /* RR count */
449};
450
451enum drrs_support_type {
452 DRRS_NOT_SUPPORTED = 0,
453 STATIC_DRRS_SUPPORT = 1,
454 SEAMLESS_DRRS_SUPPORT = 2
455};
456
457struct intel_dp;
458struct i915_drrs {
459 struct mutex mutex;
460 struct delayed_work work;
461 struct intel_dp *dp;
462 unsigned busy_frontbuffer_bits;
463 enum drrs_refresh_rate_type refresh_rate_type;
464 enum drrs_support_type type;
465};
466
467struct i915_psr {
468 struct mutex lock;
469
470#define I915_PSR_DEBUG_MODE_MASK 0x0f
471#define I915_PSR_DEBUG_DEFAULT 0x00
472#define I915_PSR_DEBUG_DISABLE 0x01
473#define I915_PSR_DEBUG_ENABLE 0x02
474#define I915_PSR_DEBUG_FORCE_PSR1 0x03
475#define I915_PSR_DEBUG_IRQ 0x10
476
477 u32 debug;
478 bool sink_support;
479 bool enabled;
480 struct intel_dp *dp;
481 enum pipe pipe;
482 bool active;
483 struct work_struct work;
484 unsigned busy_frontbuffer_bits;
485 bool sink_psr2_support;
486 bool link_standby;
487 bool colorimetry_support;
488 bool psr2_enabled;
489 u8 sink_sync_latency;
490 ktime_t last_entry_attempt;
491 ktime_t last_exit;
492 bool sink_not_reliable;
493 bool irq_aux_error;
494 u16 su_x_granularity;
495};
496
497#define QUIRK_LVDS_SSC_DISABLE (1<<1)
498#define QUIRK_INVERT_BRIGHTNESS (1<<2)
499#define QUIRK_BACKLIGHT_PRESENT (1<<3)
500#define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
501#define QUIRK_INCREASE_T12_DELAY (1<<6)
502#define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
503
504struct intel_fbdev;
505struct intel_fbc_work;
506
507struct intel_gmbus {
508 struct i2c_adapter adapter;
509#define GMBUS_FORCE_BIT_RETRY (1U << 31)
510 u32 force_bit;
511 u32 reg0;
512 i915_reg_t gpio_reg;
513 struct i2c_algo_bit_data bit_algo;
514 struct drm_i915_private *dev_priv;
515};
516
517struct i915_suspend_saved_registers {
518 u32 saveDSPARB;
519 u32 saveFBC_CONTROL;
520 u32 saveCACHE_MODE_0;
521 u32 saveMI_ARB_STATE;
522 u32 saveSWF0[16];
523 u32 saveSWF1[16];
524 u32 saveSWF3[3];
525 u64 saveFENCE[I915_MAX_NUM_FENCES];
526 u32 savePCH_PORT_HOTPLUG;
527 u16 saveGCDGMBUS;
528};
529
530struct vlv_s0ix_state;
531
532struct intel_rps_ei {
533 ktime_t ktime;
534 u32 render_c0;
535 u32 media_c0;
536};
537
538struct intel_rps {
539 struct mutex lock; /* protects enabling and the worker */
540
541 /*
542 * work, interrupts_enabled and pm_iir are protected by
543 * dev_priv->irq_lock
544 */
545 struct work_struct work;
546 bool interrupts_enabled;
547 u32 pm_iir;
548
549 /* PM interrupt bits that should never be masked */
550 u32 pm_intrmsk_mbz;
551
552 /* Frequencies are stored in potentially platform dependent multiples.
553 * In other words, *_freq needs to be multiplied by X to be interesting.
554 * Soft limits are those which are used for the dynamic reclocking done
555 * by the driver (raise frequencies under heavy loads, and lower for
556 * lighter loads). Hard limits are those imposed by the hardware.
557 *
558 * A distinction is made for overclocking, which is never enabled by
559 * default, and is considered to be above the hard limit if it's
560 * possible at all.
561 */
562 u8 cur_freq; /* Current frequency (cached, may not == HW) */
563 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
564 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
565 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
566 u8 min_freq; /* AKA RPn. Minimum frequency */
567 u8 boost_freq; /* Frequency to request when wait boosting */
568 u8 idle_freq; /* Frequency to request when we are idle */
569 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
570 u8 rp1_freq; /* "less than" RP0 power/freqency */
571 u8 rp0_freq; /* Non-overclocked max frequency. */
572 u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */
573
574 int last_adj;
575
576 struct {
577 struct mutex mutex;
578
579 enum { LOW_POWER, BETWEEN, HIGH_POWER } mode;
580 unsigned int interactive;
581
582 u8 up_threshold; /* Current %busy required to uplock */
583 u8 down_threshold; /* Current %busy required to downclock */
584 } power;
585
586 bool enabled;
587 atomic_t num_waiters;
588 atomic_t boosts;
589
590 /* manual wa residency calculations */
591 struct intel_rps_ei ei;
592};
593
594struct intel_rc6 {
595 bool enabled;
596 bool ctx_corrupted;
597 intel_wakeref_t ctx_corrupted_wakeref;
598 u64 prev_hw_residency[4];
599 u64 cur_residency[4];
600};
601
602struct intel_llc_pstate {
603 bool enabled;
604};
605
606struct intel_gen6_power_mgmt {
607 struct intel_rps rps;
608 struct intel_rc6 rc6;
609 struct intel_llc_pstate llc_pstate;
610};
611
612/* defined intel_pm.c */
613extern spinlock_t mchdev_lock;
614
615struct intel_ilk_power_mgmt {
616 u8 cur_delay;
617 u8 min_delay;
618 u8 max_delay;
619 u8 fmax;
620 u8 fstart;
621
622 u64 last_count1;
623 unsigned long last_time1;
624 unsigned long chipset_power;
625 u64 last_count2;
626 u64 last_time2;
627 unsigned long gfx_power;
628 u8 corr;
629
630 int c_m;
631 int r_t;
632};
633
634#define MAX_L3_SLICES 2
635struct intel_l3_parity {
636 u32 *remap_info[MAX_L3_SLICES];
637 struct work_struct error_work;
638 int which_slice;
639};
640
641struct i915_gem_mm {
642 /** Memory allocator for GTT stolen memory */
643 struct drm_mm stolen;
644 /** Protects the usage of the GTT stolen memory allocator. This is
645 * always the inner lock when overlapping with struct_mutex. */
646 struct mutex stolen_lock;
647
648 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
649 spinlock_t obj_lock;
650
651 /**
652 * List of objects which are purgeable.
653 */
654 struct list_head purge_list;
655
656 /**
657 * List of objects which have allocated pages and are shrinkable.
658 */
659 struct list_head shrink_list;
660
661 /**
662 * List of objects which are pending destruction.
663 */
664 struct llist_head free_list;
665 struct work_struct free_work;
666 /**
667 * Count of objects pending destructions. Used to skip needlessly
668 * waiting on an RCU barrier if no objects are waiting to be freed.
669 */
670 atomic_t free_count;
671
672 /**
673 * Small stash of WC pages
674 */
675 struct pagestash wc_stash;
676
677 /**
678 * tmpfs instance used for shmem backed objects
679 */
680 struct vfsmount *gemfs;
681
682 struct notifier_block oom_notifier;
683 struct notifier_block vmap_notifier;
684 struct shrinker shrinker;
685
686 /**
687 * Workqueue to fault in userptr pages, flushed by the execbuf
688 * when required but otherwise left to userspace to try again
689 * on EAGAIN.
690 */
691 struct workqueue_struct *userptr_wq;
692
693 /** Bit 6 swizzling required for X tiling */
694 u32 bit_6_swizzle_x;
695 /** Bit 6 swizzling required for Y tiling */
696 u32 bit_6_swizzle_y;
697
698 /* shrinker accounting, also useful for userland debugging */
699 u64 shrink_memory;
700 u32 shrink_count;
701};
702
703#define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */
704
705#define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
706#define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
707
708#define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */
709#define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */
710
711#define I915_ENGINE_WEDGED_TIMEOUT (60 * HZ) /* Reset but no recovery? */
712
713struct ddi_vbt_port_info {
714 /* Non-NULL if port present. */
715 const struct child_device_config *child;
716
717 int max_tmds_clock;
718
719 /*
720 * This is an index in the HDMI/DVI DDI buffer translation table.
721 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
722 * populate this field.
723 */
724#define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
725 u8 hdmi_level_shift;
726
727 u8 supports_dvi:1;
728 u8 supports_hdmi:1;
729 u8 supports_dp:1;
730 u8 supports_edp:1;
731 u8 supports_typec_usb:1;
732 u8 supports_tbt:1;
733
734 u8 alternate_aux_channel;
735 u8 alternate_ddc_pin;
736
737 u8 dp_boost_level;
738 u8 hdmi_boost_level;
739 int dp_max_link_rate; /* 0 for not limited by VBT */
740};
741
742enum psr_lines_to_wait {
743 PSR_0_LINES_TO_WAIT = 0,
744 PSR_1_LINE_TO_WAIT,
745 PSR_4_LINES_TO_WAIT,
746 PSR_8_LINES_TO_WAIT
747};
748
749struct intel_vbt_data {
750 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
751 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
752
753 /* Feature bits */
754 unsigned int int_tv_support:1;
755 unsigned int lvds_dither:1;
756 unsigned int int_crt_support:1;
757 unsigned int lvds_use_ssc:1;
758 unsigned int int_lvds_support:1;
759 unsigned int display_clock_mode:1;
760 unsigned int fdi_rx_polarity_inverted:1;
761 unsigned int panel_type:4;
762 int lvds_ssc_freq;
763 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
764 enum drm_panel_orientation orientation;
765
766 enum drrs_support_type drrs_type;
767
768 struct {
769 int rate;
770 int lanes;
771 int preemphasis;
772 int vswing;
773 bool low_vswing;
774 bool initialized;
775 int bpp;
776 struct edp_power_seq pps;
777 } edp;
778
779 struct {
780 bool enable;
781 bool full_link;
782 bool require_aux_wakeup;
783 int idle_frames;
784 enum psr_lines_to_wait lines_to_wait;
785 int tp1_wakeup_time_us;
786 int tp2_tp3_wakeup_time_us;
787 int psr2_tp2_tp3_wakeup_time_us;
788 } psr;
789
790 struct {
791 u16 pwm_freq_hz;
792 bool present;
793 bool active_low_pwm;
794 u8 min_brightness; /* min_brightness/255 of max */
795 u8 controller; /* brightness controller number */
796 enum intel_backlight_type type;
797 } backlight;
798
799 /* MIPI DSI */
800 struct {
801 u16 panel_id;
802 struct mipi_config *config;
803 struct mipi_pps_data *pps;
804 u16 bl_ports;
805 u16 cabc_ports;
806 u8 seq_version;
807 u32 size;
808 u8 *data;
809 const u8 *sequence[MIPI_SEQ_MAX];
810 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
811 enum drm_panel_orientation orientation;
812 } dsi;
813
814 int crt_ddc_pin;
815
816 int child_dev_num;
817 struct child_device_config *child_dev;
818
819 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
820 struct sdvo_device_mapping sdvo_mappings[2];
821};
822
823enum intel_ddb_partitioning {
824 INTEL_DDB_PART_1_2,
825 INTEL_DDB_PART_5_6, /* IVB+ */
826};
827
828struct intel_wm_level {
829 bool enable;
830 u32 pri_val;
831 u32 spr_val;
832 u32 cur_val;
833 u32 fbc_val;
834};
835
836struct ilk_wm_values {
837 u32 wm_pipe[3];
838 u32 wm_lp[3];
839 u32 wm_lp_spr[3];
840 u32 wm_linetime[3];
841 bool enable_fbc_wm;
842 enum intel_ddb_partitioning partitioning;
843};
844
845struct g4x_pipe_wm {
846 u16 plane[I915_MAX_PLANES];
847 u16 fbc;
848};
849
850struct g4x_sr_wm {
851 u16 plane;
852 u16 cursor;
853 u16 fbc;
854};
855
856struct vlv_wm_ddl_values {
857 u8 plane[I915_MAX_PLANES];
858};
859
860struct vlv_wm_values {
861 struct g4x_pipe_wm pipe[3];
862 struct g4x_sr_wm sr;
863 struct vlv_wm_ddl_values ddl[3];
864 u8 level;
865 bool cxsr;
866};
867
868struct g4x_wm_values {
869 struct g4x_pipe_wm pipe[2];
870 struct g4x_sr_wm sr;
871 struct g4x_sr_wm hpll;
872 bool cxsr;
873 bool hpll_en;
874 bool fbc_en;
875};
876
877struct skl_ddb_entry {
878 u16 start, end; /* in number of blocks, 'end' is exclusive */
879};
880
881static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry)
882{
883 return entry->end - entry->start;
884}
885
886static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
887 const struct skl_ddb_entry *e2)
888{
889 if (e1->start == e2->start && e1->end == e2->end)
890 return true;
891
892 return false;
893}
894
895struct skl_ddb_allocation {
896 u8 enabled_slices; /* GEN11 has configurable 2 slices */
897};
898
899struct skl_ddb_values {
900 unsigned dirty_pipes;
901 struct skl_ddb_allocation ddb;
902};
903
904struct skl_wm_level {
905 u16 min_ddb_alloc;
906 u16 plane_res_b;
907 u8 plane_res_l;
908 bool plane_en;
909 bool ignore_lines;
910};
911
912/* Stores plane specific WM parameters */
913struct skl_wm_params {
914 bool x_tiled, y_tiled;
915 bool rc_surface;
916 bool is_planar;
917 u32 width;
918 u8 cpp;
919 u32 plane_pixel_rate;
920 u32 y_min_scanlines;
921 u32 plane_bytes_per_line;
922 uint_fixed_16_16_t plane_blocks_per_line;
923 uint_fixed_16_16_t y_tile_minimum;
924 u32 linetime_us;
925 u32 dbuf_block_size;
926};
927
928enum intel_pipe_crc_source {
929 INTEL_PIPE_CRC_SOURCE_NONE,
930 INTEL_PIPE_CRC_SOURCE_PLANE1,
931 INTEL_PIPE_CRC_SOURCE_PLANE2,
932 INTEL_PIPE_CRC_SOURCE_PLANE3,
933 INTEL_PIPE_CRC_SOURCE_PLANE4,
934 INTEL_PIPE_CRC_SOURCE_PLANE5,
935 INTEL_PIPE_CRC_SOURCE_PLANE6,
936 INTEL_PIPE_CRC_SOURCE_PLANE7,
937 INTEL_PIPE_CRC_SOURCE_PIPE,
938 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
939 INTEL_PIPE_CRC_SOURCE_TV,
940 INTEL_PIPE_CRC_SOURCE_DP_B,
941 INTEL_PIPE_CRC_SOURCE_DP_C,
942 INTEL_PIPE_CRC_SOURCE_DP_D,
943 INTEL_PIPE_CRC_SOURCE_AUTO,
944 INTEL_PIPE_CRC_SOURCE_MAX,
945};
946
947#define INTEL_PIPE_CRC_ENTRIES_NR 128
948struct intel_pipe_crc {
949 spinlock_t lock;
950 int skipped;
951 enum intel_pipe_crc_source source;
952};
953
954struct i915_frontbuffer_tracking {
955 spinlock_t lock;
956
957 /*
958 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
959 * scheduled flips.
960 */
961 unsigned busy_bits;
962 unsigned flip_bits;
963};
964
965struct i915_virtual_gpu {
966 struct mutex lock; /* serialises sending of g2v_notify command pkts */
967 bool active;
968 u32 caps;
969};
970
971/* used in computing the new watermarks state */
972struct intel_wm_config {
973 unsigned int num_pipes_active;
974 bool sprites_enabled;
975 bool sprites_scaled;
976};
977
978struct i915_oa_format {
979 u32 format;
980 int size;
981};
982
983struct i915_oa_reg {
984 i915_reg_t addr;
985 u32 value;
986};
987
988struct i915_oa_config {
989 char uuid[UUID_STRING_LEN + 1];
990 int id;
991
992 const struct i915_oa_reg *mux_regs;
993 u32 mux_regs_len;
994 const struct i915_oa_reg *b_counter_regs;
995 u32 b_counter_regs_len;
996 const struct i915_oa_reg *flex_regs;
997 u32 flex_regs_len;
998
999 struct attribute_group sysfs_metric;
1000 struct attribute *attrs[2];
1001 struct device_attribute sysfs_metric_id;
1002
1003 atomic_t ref_count;
1004};
1005
1006struct i915_perf_stream;
1007
1008/**
1009 * struct i915_perf_stream_ops - the OPs to support a specific stream type
1010 */
1011struct i915_perf_stream_ops {
1012 /**
1013 * @enable: Enables the collection of HW samples, either in response to
1014 * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
1015 * without `I915_PERF_FLAG_DISABLED`.
1016 */
1017 void (*enable)(struct i915_perf_stream *stream);
1018
1019 /**
1020 * @disable: Disables the collection of HW samples, either in response
1021 * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
1022 * the stream.
1023 */
1024 void (*disable)(struct i915_perf_stream *stream);
1025
1026 /**
1027 * @poll_wait: Call poll_wait, passing a wait queue that will be woken
1028 * once there is something ready to read() for the stream
1029 */
1030 void (*poll_wait)(struct i915_perf_stream *stream,
1031 struct file *file,
1032 poll_table *wait);
1033
1034 /**
1035 * @wait_unlocked: For handling a blocking read, wait until there is
1036 * something to ready to read() for the stream. E.g. wait on the same
1037 * wait queue that would be passed to poll_wait().
1038 */
1039 int (*wait_unlocked)(struct i915_perf_stream *stream);
1040
1041 /**
1042 * @read: Copy buffered metrics as records to userspace
1043 * **buf**: the userspace, destination buffer
1044 * **count**: the number of bytes to copy, requested by userspace
1045 * **offset**: zero at the start of the read, updated as the read
1046 * proceeds, it represents how many bytes have been copied so far and
1047 * the buffer offset for copying the next record.
1048 *
1049 * Copy as many buffered i915 perf samples and records for this stream
1050 * to userspace as will fit in the given buffer.
1051 *
1052 * Only write complete records; returning -%ENOSPC if there isn't room
1053 * for a complete record.
1054 *
1055 * Return any error condition that results in a short read such as
1056 * -%ENOSPC or -%EFAULT, even though these may be squashed before
1057 * returning to userspace.
1058 */
1059 int (*read)(struct i915_perf_stream *stream,
1060 char __user *buf,
1061 size_t count,
1062 size_t *offset);
1063
1064 /**
1065 * @destroy: Cleanup any stream specific resources.
1066 *
1067 * The stream will always be disabled before this is called.
1068 */
1069 void (*destroy)(struct i915_perf_stream *stream);
1070};
1071
1072/**
1073 * struct i915_perf_stream - state for a single open stream FD
1074 */
1075struct i915_perf_stream {
1076 /**
1077 * @dev_priv: i915 drm device
1078 */
1079 struct drm_i915_private *dev_priv;
1080
1081 /**
1082 * @link: Links the stream into ``&drm_i915_private->streams``
1083 */
1084 struct list_head link;
1085
1086 /**
1087 * @wakeref: As we keep the device awake while the perf stream is
1088 * active, we track our runtime pm reference for later release.
1089 */
1090 intel_wakeref_t wakeref;
1091
1092 /**
1093 * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
1094 * properties given when opening a stream, representing the contents
1095 * of a single sample as read() by userspace.
1096 */
1097 u32 sample_flags;
1098
1099 /**
1100 * @sample_size: Considering the configured contents of a sample
1101 * combined with the required header size, this is the total size
1102 * of a single sample record.
1103 */
1104 int sample_size;
1105
1106 /**
1107 * @ctx: %NULL if measuring system-wide across all contexts or a
1108 * specific context that is being monitored.
1109 */
1110 struct i915_gem_context *ctx;
1111
1112 /**
1113 * @enabled: Whether the stream is currently enabled, considering
1114 * whether the stream was opened in a disabled state and based
1115 * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
1116 */
1117 bool enabled;
1118
1119 /**
1120 * @ops: The callbacks providing the implementation of this specific
1121 * type of configured stream.
1122 */
1123 const struct i915_perf_stream_ops *ops;
1124
1125 /**
1126 * @oa_config: The OA configuration used by the stream.
1127 */
1128 struct i915_oa_config *oa_config;
1129
1130 /**
1131 * The OA context specific information.
1132 */
1133 struct intel_context *pinned_ctx;
1134 u32 specific_ctx_id;
1135 u32 specific_ctx_id_mask;
1136
1137 struct hrtimer poll_check_timer;
1138 wait_queue_head_t poll_wq;
1139 bool pollin;
1140
1141 bool periodic;
1142 int period_exponent;
1143
1144 /**
1145 * State of the OA buffer.
1146 */
1147 struct {
1148 struct i915_vma *vma;
1149 u8 *vaddr;
1150 u32 last_ctx_id;
1151 int format;
1152 int format_size;
1153 int size_exponent;
1154
1155 /**
1156 * Locks reads and writes to all head/tail state
1157 *
1158 * Consider: the head and tail pointer state needs to be read
1159 * consistently from a hrtimer callback (atomic context) and
1160 * read() fop (user context) with tail pointer updates happening
1161 * in atomic context and head updates in user context and the
1162 * (unlikely) possibility of read() errors needing to reset all
1163 * head/tail state.
1164 *
1165 * Note: Contention/performance aren't currently a significant
1166 * concern here considering the relatively low frequency of
1167 * hrtimer callbacks (5ms period) and that reads typically only
1168 * happen in response to a hrtimer event and likely complete
1169 * before the next callback.
1170 *
1171 * Note: This lock is not held *while* reading and copying data
1172 * to userspace so the value of head observed in htrimer
1173 * callbacks won't represent any partial consumption of data.
1174 */
1175 spinlock_t ptr_lock;
1176
1177 /**
1178 * One 'aging' tail pointer and one 'aged' tail pointer ready to
1179 * used for reading.
1180 *
1181 * Initial values of 0xffffffff are invalid and imply that an
1182 * update is required (and should be ignored by an attempted
1183 * read)
1184 */
1185 struct {
1186 u32 offset;
1187 } tails[2];
1188
1189 /**
1190 * Index for the aged tail ready to read() data up to.
1191 */
1192 unsigned int aged_tail_idx;
1193
1194 /**
1195 * A monotonic timestamp for when the current aging tail pointer
1196 * was read; used to determine when it is old enough to trust.
1197 */
1198 u64 aging_timestamp;
1199
1200 /**
1201 * Although we can always read back the head pointer register,
1202 * we prefer to avoid trusting the HW state, just to avoid any
1203 * risk that some hardware condition could * somehow bump the
1204 * head pointer unpredictably and cause us to forward the wrong
1205 * OA buffer data to userspace.
1206 */
1207 u32 head;
1208 } oa_buffer;
1209};
1210
1211/**
1212 * struct i915_oa_ops - Gen specific implementation of an OA unit stream
1213 */
1214struct i915_oa_ops {
1215 /**
1216 * @is_valid_b_counter_reg: Validates register's address for
1217 * programming boolean counters for a particular platform.
1218 */
1219 bool (*is_valid_b_counter_reg)(struct drm_i915_private *dev_priv,
1220 u32 addr);
1221
1222 /**
1223 * @is_valid_mux_reg: Validates register's address for programming mux
1224 * for a particular platform.
1225 */
1226 bool (*is_valid_mux_reg)(struct drm_i915_private *dev_priv, u32 addr);
1227
1228 /**
1229 * @is_valid_flex_reg: Validates register's address for programming
1230 * flex EU filtering for a particular platform.
1231 */
1232 bool (*is_valid_flex_reg)(struct drm_i915_private *dev_priv, u32 addr);
1233
1234 /**
1235 * @enable_metric_set: Selects and applies any MUX configuration to set
1236 * up the Boolean and Custom (B/C) counters that are part of the
1237 * counter reports being sampled. May apply system constraints such as
1238 * disabling EU clock gating as required.
1239 */
1240 int (*enable_metric_set)(struct i915_perf_stream *stream);
1241
1242 /**
1243 * @disable_metric_set: Remove system constraints associated with using
1244 * the OA unit.
1245 */
1246 void (*disable_metric_set)(struct i915_perf_stream *stream);
1247
1248 /**
1249 * @oa_enable: Enable periodic sampling
1250 */
1251 void (*oa_enable)(struct i915_perf_stream *stream);
1252
1253 /**
1254 * @oa_disable: Disable periodic sampling
1255 */
1256 void (*oa_disable)(struct i915_perf_stream *stream);
1257
1258 /**
1259 * @read: Copy data from the circular OA buffer into a given userspace
1260 * buffer.
1261 */
1262 int (*read)(struct i915_perf_stream *stream,
1263 char __user *buf,
1264 size_t count,
1265 size_t *offset);
1266
1267 /**
1268 * @oa_hw_tail_read: read the OA tail pointer register
1269 *
1270 * In particular this enables us to share all the fiddly code for
1271 * handling the OA unit tail pointer race that affects multiple
1272 * generations.
1273 */
1274 u32 (*oa_hw_tail_read)(struct i915_perf_stream *stream);
1275};
1276
1277struct intel_cdclk_state {
1278 unsigned int cdclk, vco, ref, bypass;
1279 u8 voltage_level;
1280};
1281
1282struct drm_i915_private {
1283 struct drm_device drm;
1284
1285 const struct intel_device_info __info; /* Use INTEL_INFO() to access. */
1286 struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
1287 struct intel_driver_caps caps;
1288
1289 /**
1290 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
1291 * end of stolen which we can optionally use to create GEM objects
1292 * backed by stolen memory. Note that stolen_usable_size tells us
1293 * exactly how much of this we are actually allowed to use, given that
1294 * some portion of it is in fact reserved for use by hardware functions.
1295 */
1296 struct resource dsm;
1297 /**
1298 * Reseved portion of Data Stolen Memory
1299 */
1300 struct resource dsm_reserved;
1301
1302 /*
1303 * Stolen memory is segmented in hardware with different portions
1304 * offlimits to certain functions.
1305 *
1306 * The drm_mm is initialised to the total accessible range, as found
1307 * from the PCI config. On Broadwell+, this is further restricted to
1308 * avoid the first page! The upper end of stolen memory is reserved for
1309 * hardware functions and similarly removed from the accessible range.
1310 */
1311 resource_size_t stolen_usable_size; /* Total size minus reserved ranges */
1312
1313 struct intel_uncore uncore;
1314 struct intel_uncore_mmio_debug mmio_debug;
1315
1316 struct i915_virtual_gpu vgpu;
1317
1318 struct intel_gvt *gvt;
1319
1320 struct intel_wopcm wopcm;
1321
1322 struct intel_csr csr;
1323
1324 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1325
1326 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1327 * controller on different i2c buses. */
1328 struct mutex gmbus_mutex;
1329
1330 /**
1331 * Base address of where the gmbus and gpio blocks are located (either
1332 * on PCH or on SoC for platforms without PCH).
1333 */
1334 u32 gpio_mmio_base;
1335
1336 /* MMIO base address for MIPI regs */
1337 u32 mipi_mmio_base;
1338
1339 u32 psr_mmio_base;
1340
1341 u32 pps_mmio_base;
1342
1343 wait_queue_head_t gmbus_wait_queue;
1344
1345 struct pci_dev *bridge_dev;
1346
1347 /* Context used internally to idle the GPU and setup initial state */
1348 struct i915_gem_context *kernel_context;
1349
1350 struct intel_engine_cs *engine[I915_NUM_ENGINES];
1351 struct rb_root uabi_engines;
1352
1353 struct resource mch_res;
1354
1355 /* protects the irq masks */
1356 spinlock_t irq_lock;
1357
1358 bool display_irqs_enabled;
1359
1360 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1361 struct pm_qos_request pm_qos;
1362
1363 /* Sideband mailbox protection */
1364 struct mutex sb_lock;
1365 struct pm_qos_request sb_qos;
1366
1367 /** Cached value of IMR to avoid reads in updating the bitfield */
1368 union {
1369 u32 irq_mask;
1370 u32 de_irq_mask[I915_MAX_PIPES];
1371 };
1372 u32 pm_rps_events;
1373 u32 pipestat_irq_mask[I915_MAX_PIPES];
1374
1375 struct i915_hotplug hotplug;
1376 struct intel_fbc fbc;
1377 struct i915_drrs drrs;
1378 struct intel_opregion opregion;
1379 struct intel_vbt_data vbt;
1380
1381 bool preserve_bios_swizzle;
1382
1383 /* overlay */
1384 struct intel_overlay *overlay;
1385
1386 /* backlight registers and fields in struct intel_panel */
1387 struct mutex backlight_lock;
1388
1389 /* protects panel power sequencer state */
1390 struct mutex pps_mutex;
1391
1392 unsigned int fsb_freq, mem_freq, is_ddr3;
1393 unsigned int skl_preferred_vco_freq;
1394 unsigned int max_cdclk_freq;
1395
1396 unsigned int max_dotclk_freq;
1397 unsigned int rawclk_freq;
1398 unsigned int hpll_freq;
1399 unsigned int fdi_pll_freq;
1400 unsigned int czclk_freq;
1401
1402 struct {
1403 /*
1404 * The current logical cdclk state.
1405 * See intel_atomic_state.cdclk.logical
1406 *
1407 * For reading holding any crtc lock is sufficient,
1408 * for writing must hold all of them.
1409 */
1410 struct intel_cdclk_state logical;
1411 /*
1412 * The current actual cdclk state.
1413 * See intel_atomic_state.cdclk.actual
1414 */
1415 struct intel_cdclk_state actual;
1416 /* The current hardware cdclk state */
1417 struct intel_cdclk_state hw;
1418
1419 int force_min_cdclk;
1420 } cdclk;
1421
1422 /**
1423 * wq - Driver workqueue for GEM.
1424 *
1425 * NOTE: Work items scheduled here are not allowed to grab any modeset
1426 * locks, for otherwise the flushing done in the pageflip code will
1427 * result in deadlocks.
1428 */
1429 struct workqueue_struct *wq;
1430
1431 /* ordered wq for modesets */
1432 struct workqueue_struct *modeset_wq;
1433
1434 /* Display functions */
1435 struct drm_i915_display_funcs display;
1436
1437 /* PCH chipset type */
1438 enum intel_pch pch_type;
1439 unsigned short pch_id;
1440
1441 unsigned long quirks;
1442
1443 struct drm_atomic_state *modeset_restore_state;
1444 struct drm_modeset_acquire_ctx reset_ctx;
1445
1446 struct i915_ggtt ggtt; /* VM representing the global address space */
1447
1448 struct i915_gem_mm mm;
1449 DECLARE_HASHTABLE(mm_structs, 7);
1450 struct mutex mm_lock;
1451
1452 /* Kernel Modesetting */
1453
1454 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1455 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1456
1457#ifdef CONFIG_DEBUG_FS
1458 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1459#endif
1460
1461 /* dpll and cdclk state is protected by connection_mutex */
1462 int num_shared_dpll;
1463 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1464 const struct intel_dpll_mgr *dpll_mgr;
1465
1466 /*
1467 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
1468 * Must be global rather than per dpll, because on some platforms
1469 * plls share registers.
1470 */
1471 struct mutex dpll_lock;
1472
1473 unsigned int active_crtcs;
1474 /* minimum acceptable cdclk for each pipe */
1475 int min_cdclk[I915_MAX_PIPES];
1476 /* minimum acceptable voltage level for each pipe */
1477 u8 min_voltage_level[I915_MAX_PIPES];
1478
1479 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1480
1481 struct i915_wa_list gt_wa_list;
1482
1483 struct i915_frontbuffer_tracking fb_tracking;
1484
1485 struct intel_atomic_helper {
1486 struct llist_head free_list;
1487 struct work_struct free_work;
1488 } atomic_helper;
1489
1490 u16 orig_clock;
1491
1492 bool mchbar_need_disable;
1493
1494 struct intel_l3_parity l3_parity;
1495
1496 /*
1497 * edram size in MB.
1498 * Cannot be determined by PCIID. You must always read a register.
1499 */
1500 u32 edram_size_mb;
1501
1502 /* gen6+ GT PM state */
1503 struct intel_gen6_power_mgmt gt_pm;
1504
1505 /* ilk-only ips/rps state. Everything in here is protected by the global
1506 * mchdev_lock in intel_pm.c */
1507 struct intel_ilk_power_mgmt ips;
1508
1509 struct i915_power_domains power_domains;
1510
1511 struct i915_psr psr;
1512
1513 struct i915_gpu_error gpu_error;
1514
1515 struct drm_i915_gem_object *vlv_pctx;
1516
1517 /* list of fbdev register on this device */
1518 struct intel_fbdev *fbdev;
1519 struct work_struct fbdev_suspend_work;
1520
1521 struct drm_property *broadcast_rgb_property;
1522 struct drm_property *force_audio_property;
1523
1524 /* hda/i915 audio component */
1525 struct i915_audio_component *audio_component;
1526 bool audio_component_registered;
1527 /**
1528 * av_mutex - mutex for audio/video sync
1529 *
1530 */
1531 struct mutex av_mutex;
1532 int audio_power_refcount;
1533
1534 struct {
1535 struct mutex mutex;
1536 struct list_head list;
1537 struct llist_head free_list;
1538 struct work_struct free_work;
1539
1540 /* The hw wants to have a stable context identifier for the
1541 * lifetime of the context (for OA, PASID, faults, etc).
1542 * This is limited in execlists to 21 bits.
1543 */
1544 struct ida hw_ida;
1545#define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
1546#define MAX_GUC_CONTEXT_HW_ID (1 << 20) /* exclusive */
1547#define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */
1548/* in Gen12 ID 0x7FF is reserved to indicate idle */
1549#define GEN12_MAX_CONTEXT_HW_ID (GEN11_MAX_CONTEXT_HW_ID - 1)
1550 struct list_head hw_id_list;
1551 } contexts;
1552
1553 u32 fdi_rx_config;
1554
1555 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1556 u32 chv_phy_control;
1557 /*
1558 * Shadows for CHV DPLL_MD regs to keep the state
1559 * checker somewhat working in the presence hardware
1560 * crappiness (can't read out DPLL_MD for pipes B & C).
1561 */
1562 u32 chv_dpll_md[I915_MAX_PIPES];
1563 u32 bxt_phy_grc;
1564
1565 u32 suspend_count;
1566 bool power_domains_suspended;
1567 struct i915_suspend_saved_registers regfile;
1568 struct vlv_s0ix_state *vlv_s0ix_state;
1569
1570 enum {
1571 I915_SAGV_UNKNOWN = 0,
1572 I915_SAGV_DISABLED,
1573 I915_SAGV_ENABLED,
1574 I915_SAGV_NOT_CONTROLLED
1575 } sagv_status;
1576
1577 struct {
1578 /*
1579 * Raw watermark latency values:
1580 * in 0.1us units for WM0,
1581 * in 0.5us units for WM1+.
1582 */
1583 /* primary */
1584 u16 pri_latency[5];
1585 /* sprite */
1586 u16 spr_latency[5];
1587 /* cursor */
1588 u16 cur_latency[5];
1589 /*
1590 * Raw watermark memory latency values
1591 * for SKL for all 8 levels
1592 * in 1us units.
1593 */
1594 u16 skl_latency[8];
1595
1596 /* current hardware state */
1597 union {
1598 struct ilk_wm_values hw;
1599 struct skl_ddb_values skl_hw;
1600 struct vlv_wm_values vlv;
1601 struct g4x_wm_values g4x;
1602 };
1603
1604 u8 max_level;
1605
1606 /*
1607 * Should be held around atomic WM register writing; also
1608 * protects * intel_crtc->wm.active and
1609 * crtc_state->wm.need_postvbl_update.
1610 */
1611 struct mutex wm_mutex;
1612
1613 /*
1614 * Set during HW readout of watermarks/DDB. Some platforms
1615 * need to know when we're still using BIOS-provided values
1616 * (which we don't fully trust).
1617 */
1618 bool distrust_bios_wm;
1619 } wm;
1620
1621 struct dram_info {
1622 bool valid;
1623 bool is_16gb_dimm;
1624 u8 num_channels;
1625 u8 ranks;
1626 u32 bandwidth_kbps;
1627 bool symmetric_memory;
1628 enum intel_dram_type {
1629 INTEL_DRAM_UNKNOWN,
1630 INTEL_DRAM_DDR3,
1631 INTEL_DRAM_DDR4,
1632 INTEL_DRAM_LPDDR3,
1633 INTEL_DRAM_LPDDR4
1634 } type;
1635 } dram_info;
1636
1637 struct intel_bw_info {
1638 unsigned int deratedbw[3]; /* for each QGV point */
1639 u8 num_qgv_points;
1640 u8 num_planes;
1641 } max_bw[6];
1642
1643 struct drm_private_obj bw_obj;
1644
1645 struct intel_runtime_pm runtime_pm;
1646
1647 struct {
1648 bool initialized;
1649
1650 struct kobject *metrics_kobj;
1651 struct ctl_table_header *sysctl_header;
1652
1653 /*
1654 * Lock associated with adding/modifying/removing OA configs
1655 * in dev_priv->perf.metrics_idr.
1656 */
1657 struct mutex metrics_lock;
1658
1659 /*
1660 * List of dynamic configurations, you need to hold
1661 * dev_priv->perf.metrics_lock to access it.
1662 */
1663 struct idr metrics_idr;
1664
1665 /*
1666 * Lock associated with anything below within this structure
1667 * except exclusive_stream.
1668 */
1669 struct mutex lock;
1670 struct list_head streams;
1671
1672 /*
1673 * The stream currently using the OA unit. If accessed
1674 * outside a syscall associated to its file
1675 * descriptor, you need to hold
1676 * dev_priv->drm.struct_mutex.
1677 */
1678 struct i915_perf_stream *exclusive_stream;
1679
1680 /**
1681 * For rate limiting any notifications of spurious
1682 * invalid OA reports
1683 */
1684 struct ratelimit_state spurious_report_rs;
1685
1686 struct i915_oa_config test_config;
1687
1688 u32 gen7_latched_oastatus1;
1689 u32 ctx_oactxctrl_offset;
1690 u32 ctx_flexeu0_offset;
1691
1692 /**
1693 * The RPT_ID/reason field for Gen8+ includes a bit
1694 * to determine if the CTX ID in the report is valid
1695 * but the specific bit differs between Gen 8 and 9
1696 */
1697 u32 gen8_valid_ctx_bit;
1698
1699 struct i915_oa_ops ops;
1700 const struct i915_oa_format *oa_formats;
1701 } perf;
1702
1703 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1704 struct intel_gt gt;
1705
1706 struct {
1707 struct notifier_block pm_notifier;
1708
1709 /**
1710 * We leave the user IRQ off as much as possible,
1711 * but this means that requests will finish and never
1712 * be retired once the system goes idle. Set a timer to
1713 * fire periodically while the ring is running. When it
1714 * fires, go retire requests.
1715 */
1716 struct delayed_work retire_work;
1717
1718 /**
1719 * When we detect an idle GPU, we want to turn on
1720 * powersaving features. So once we see that there
1721 * are no more requests outstanding and no more
1722 * arrive within a small period of time, we fire
1723 * off the idle_work.
1724 */
1725 struct work_struct idle_work;
1726 } gem;
1727
1728 u8 pch_ssc_use;
1729
1730 /* For i945gm vblank irq vs. C3 workaround */
1731 struct {
1732 struct work_struct work;
1733 struct pm_qos_request pm_qos;
1734 u8 c3_disable_latency;
1735 u8 enabled;
1736 } i945gm_vblank;
1737
1738 /* perform PHY state sanity checks? */
1739 bool chv_phy_assert[2];
1740
1741 bool ipc_enabled;
1742
1743 /* Used to save the pipe-to-encoder mapping for audio */
1744 struct intel_encoder *av_enc_map[I915_MAX_PIPES];
1745
1746 /* necessary resource sharing with HDMI LPE audio driver. */
1747 struct {
1748 struct platform_device *platdev;
1749 int irq;
1750 } lpe_audio;
1751
1752 struct i915_pmu pmu;
1753
1754 struct i915_hdcp_comp_master *hdcp_master;
1755 bool hdcp_comp_added;
1756
1757 /* Mutex to protect the above hdcp component related values. */
1758 struct mutex hdcp_comp_mutex;
1759
1760 /*
1761 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1762 * will be rejected. Instead look for a better place.
1763 */
1764};
1765
1766struct dram_dimm_info {
1767 u8 size, width, ranks;
1768};
1769
1770struct dram_channel_info {
1771 struct dram_dimm_info dimm_l, dimm_s;
1772 u8 ranks;
1773 bool is_16gb_dimm;
1774};
1775
1776static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1777{
1778 return container_of(dev, struct drm_i915_private, drm);
1779}
1780
1781static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
1782{
1783 return dev_get_drvdata(kdev);
1784}
1785
1786static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
1787{
1788 return pci_get_drvdata(pdev);
1789}
1790
1791/* Simple iterator over all initialised engines */
1792#define for_each_engine(engine__, dev_priv__, id__) \
1793 for ((id__) = 0; \
1794 (id__) < I915_NUM_ENGINES; \
1795 (id__)++) \
1796 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
1797
1798/* Iterator over subset of engines selected by mask */
1799#define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
1800 for ((tmp__) = (mask__) & INTEL_INFO(dev_priv__)->engine_mask; \
1801 (tmp__) ? \
1802 ((engine__) = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : \
1803 0;)
1804
1805#define rb_to_uabi_engine(rb) \
1806 rb_entry_safe(rb, struct intel_engine_cs, uabi_node)
1807
1808#define for_each_uabi_engine(engine__, i915__) \
1809 for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\
1810 (engine__); \
1811 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
1812
1813#define I915_GTT_OFFSET_NONE ((u32)-1)
1814
1815/*
1816 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1817 * considered to be the frontbuffer for the given plane interface-wise. This
1818 * doesn't mean that the hw necessarily already scans it out, but that any
1819 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1820 *
1821 * We have one bit per pipe and per scanout plane type.
1822 */
1823#define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
1824#define INTEL_FRONTBUFFER(pipe, plane_id) ({ \
1825 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \
1826 BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \
1827 BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \
1828})
1829#define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1830 BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
1831#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1832 GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
1833 INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
1834
1835#define INTEL_INFO(dev_priv) (&(dev_priv)->__info)
1836#define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime)
1837#define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps)
1838
1839#define INTEL_GEN(dev_priv) (INTEL_INFO(dev_priv)->gen)
1840#define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id)
1841
1842#define REVID_FOREVER 0xff
1843#define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
1844
1845#define INTEL_GEN_MASK(s, e) ( \
1846 BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
1847 BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
1848 GENMASK((e) - 1, (s) - 1))
1849
1850/* Returns true if Gen is in inclusive range [Start, End] */
1851#define IS_GEN_RANGE(dev_priv, s, e) \
1852 (!!(INTEL_INFO(dev_priv)->gen_mask & INTEL_GEN_MASK((s), (e))))
1853
1854#define IS_GEN(dev_priv, n) \
1855 (BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \
1856 INTEL_INFO(dev_priv)->gen == (n))
1857
1858/*
1859 * Return true if revision is in range [since,until] inclusive.
1860 *
1861 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
1862 */
1863#define IS_REVID(p, since, until) \
1864 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
1865
1866static __always_inline unsigned int
1867__platform_mask_index(const struct intel_runtime_info *info,
1868 enum intel_platform p)
1869{
1870 const unsigned int pbits =
1871 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
1872
1873 /* Expand the platform_mask array if this fails. */
1874 BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
1875 pbits * ARRAY_SIZE(info->platform_mask));
1876
1877 return p / pbits;
1878}
1879
1880static __always_inline unsigned int
1881__platform_mask_bit(const struct intel_runtime_info *info,
1882 enum intel_platform p)
1883{
1884 const unsigned int pbits =
1885 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
1886
1887 return p % pbits + INTEL_SUBPLATFORM_BITS;
1888}
1889
1890static inline u32
1891intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)
1892{
1893 const unsigned int pi = __platform_mask_index(info, p);
1894
1895 return info->platform_mask[pi] & INTEL_SUBPLATFORM_BITS;
1896}
1897
1898static __always_inline bool
1899IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
1900{
1901 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
1902 const unsigned int pi = __platform_mask_index(info, p);
1903 const unsigned int pb = __platform_mask_bit(info, p);
1904
1905 BUILD_BUG_ON(!__builtin_constant_p(p));
1906
1907 return info->platform_mask[pi] & BIT(pb);
1908}
1909
1910static __always_inline bool
1911IS_SUBPLATFORM(const struct drm_i915_private *i915,
1912 enum intel_platform p, unsigned int s)
1913{
1914 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
1915 const unsigned int pi = __platform_mask_index(info, p);
1916 const unsigned int pb = __platform_mask_bit(info, p);
1917 const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
1918 const u32 mask = info->platform_mask[pi];
1919
1920 BUILD_BUG_ON(!__builtin_constant_p(p));
1921 BUILD_BUG_ON(!__builtin_constant_p(s));
1922 BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
1923
1924 /* Shift and test on the MSB position so sign flag can be used. */
1925 return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
1926}
1927
1928#define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile)
1929
1930#define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)
1931#define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
1932#define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X)
1933#define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G)
1934#define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G)
1935#define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM)
1936#define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G)
1937#define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM)
1938#define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G)
1939#define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM)
1940#define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45)
1941#define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45)
1942#define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
1943#define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
1944#define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33)
1945#define IS_IRONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IRONLAKE)
1946#define IS_IRONLAKE_M(dev_priv) \
1947 (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv))
1948#define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
1949#define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
1950 INTEL_INFO(dev_priv)->gt == 1)
1951#define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
1952#define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
1953#define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL)
1954#define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL)
1955#define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
1956#define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON)
1957#define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
1958#define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
1959#define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
1960#define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
1961#define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
1962#define IS_ELKHARTLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
1963#define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
1964#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
1965 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
1966#define IS_BDW_ULT(dev_priv) \
1967 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
1968#define IS_BDW_ULX(dev_priv) \
1969 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
1970#define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
1971 INTEL_INFO(dev_priv)->gt == 3)
1972#define IS_HSW_ULT(dev_priv) \
1973 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
1974#define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
1975 INTEL_INFO(dev_priv)->gt == 3)
1976#define IS_HSW_GT1(dev_priv) (IS_HASWELL(dev_priv) && \
1977 INTEL_INFO(dev_priv)->gt == 1)
1978/* ULX machines are also considered ULT. */
1979#define IS_HSW_ULX(dev_priv) \
1980 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
1981#define IS_SKL_ULT(dev_priv) \
1982 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
1983#define IS_SKL_ULX(dev_priv) \
1984 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
1985#define IS_KBL_ULT(dev_priv) \
1986 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
1987#define IS_KBL_ULX(dev_priv) \
1988 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
1989#define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
1990 INTEL_INFO(dev_priv)->gt == 2)
1991#define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
1992 INTEL_INFO(dev_priv)->gt == 3)
1993#define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
1994 INTEL_INFO(dev_priv)->gt == 4)
1995#define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \
1996 INTEL_INFO(dev_priv)->gt == 2)
1997#define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
1998 INTEL_INFO(dev_priv)->gt == 3)
1999#define IS_CFL_ULT(dev_priv) \
2000 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
2001#define IS_CFL_ULX(dev_priv) \
2002 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
2003#define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2004 INTEL_INFO(dev_priv)->gt == 2)
2005#define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2006 INTEL_INFO(dev_priv)->gt == 3)
2007#define IS_CNL_WITH_PORT_F(dev_priv) \
2008 IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, INTEL_SUBPLATFORM_PORTF)
2009#define IS_ICL_WITH_PORT_F(dev_priv) \
2010 IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
2011
2012#define SKL_REVID_A0 0x0
2013#define SKL_REVID_B0 0x1
2014#define SKL_REVID_C0 0x2
2015#define SKL_REVID_D0 0x3
2016#define SKL_REVID_E0 0x4
2017#define SKL_REVID_F0 0x5
2018#define SKL_REVID_G0 0x6
2019#define SKL_REVID_H0 0x7
2020
2021#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2022
2023#define BXT_REVID_A0 0x0
2024#define BXT_REVID_A1 0x1
2025#define BXT_REVID_B0 0x3
2026#define BXT_REVID_B_LAST 0x8
2027#define BXT_REVID_C0 0x9
2028
2029#define IS_BXT_REVID(dev_priv, since, until) \
2030 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2031
2032#define KBL_REVID_A0 0x0
2033#define KBL_REVID_B0 0x1
2034#define KBL_REVID_C0 0x2
2035#define KBL_REVID_D0 0x3
2036#define KBL_REVID_E0 0x4
2037
2038#define IS_KBL_REVID(dev_priv, since, until) \
2039 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2040
2041#define GLK_REVID_A0 0x0
2042#define GLK_REVID_A1 0x1
2043
2044#define IS_GLK_REVID(dev_priv, since, until) \
2045 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2046
2047#define CNL_REVID_A0 0x0
2048#define CNL_REVID_B0 0x1
2049#define CNL_REVID_C0 0x2
2050
2051#define IS_CNL_REVID(p, since, until) \
2052 (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
2053
2054#define ICL_REVID_A0 0x0
2055#define ICL_REVID_A2 0x1
2056#define ICL_REVID_B0 0x3
2057#define ICL_REVID_B2 0x4
2058#define ICL_REVID_C0 0x5
2059
2060#define IS_ICL_REVID(p, since, until) \
2061 (IS_ICELAKE(p) && IS_REVID(p, since, until))
2062
2063#define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
2064#define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
2065#define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
2066
2067#define HAS_ENGINE(dev_priv, id) (INTEL_INFO(dev_priv)->engine_mask & BIT(id))
2068
2069#define ENGINE_INSTANCES_MASK(dev_priv, first, count) ({ \
2070 unsigned int first__ = (first); \
2071 unsigned int count__ = (count); \
2072 (INTEL_INFO(dev_priv)->engine_mask & \
2073 GENMASK(first__ + count__ - 1, first__)) >> first__; \
2074})
2075#define VDBOX_MASK(dev_priv) \
2076 ENGINE_INSTANCES_MASK(dev_priv, VCS0, I915_MAX_VCS)
2077#define VEBOX_MASK(dev_priv) \
2078 ENGINE_INSTANCES_MASK(dev_priv, VECS0, I915_MAX_VECS)
2079
2080/*
2081 * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
2082 * All later gens can run the final buffer from the ppgtt
2083 */
2084#define CMDPARSER_USES_GGTT(dev_priv) IS_GEN(dev_priv, 7)
2085
2086#define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
2087#define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
2088#define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
2089#define HAS_SECURE_BATCHES(dev_priv) (INTEL_GEN(dev_priv) < 6)
2090#define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
2091 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2092
2093#define HWS_NEEDS_PHYSICAL(dev_priv) (INTEL_INFO(dev_priv)->hws_needs_physical)
2094
2095#define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
2096 (INTEL_INFO(dev_priv)->has_logical_ring_contexts)
2097#define HAS_LOGICAL_RING_ELSQ(dev_priv) \
2098 (INTEL_INFO(dev_priv)->has_logical_ring_elsq)
2099#define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
2100 (INTEL_INFO(dev_priv)->has_logical_ring_preemption)
2101
2102#define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
2103
2104#define INTEL_PPGTT(dev_priv) (INTEL_INFO(dev_priv)->ppgtt_type)
2105#define HAS_PPGTT(dev_priv) \
2106 (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
2107#define HAS_FULL_PPGTT(dev_priv) \
2108 (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
2109
2110#define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
2111 GEM_BUG_ON((sizes) == 0); \
2112 ((sizes) & ~INTEL_INFO(dev_priv)->page_sizes) == 0; \
2113})
2114
2115#define HAS_OVERLAY(dev_priv) (INTEL_INFO(dev_priv)->display.has_overlay)
2116#define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
2117 (INTEL_INFO(dev_priv)->display.overlay_needs_physical)
2118
2119/* Early gen2 have a totally busted CS tlb and require pinned batches. */
2120#define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
2121
2122#define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv) \
2123 (IS_BROADWELL(dev_priv) || IS_GEN(dev_priv, 9))
2124
2125/* WaRsDisableCoarsePowerGating:skl,cnl */
2126#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2127 (IS_CANNONLAKE(dev_priv) || IS_GEN(dev_priv, 9))
2128
2129#define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
2130#define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
2131 IS_GEMINILAKE(dev_priv) || \
2132 IS_KABYLAKE(dev_priv))
2133
2134/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2135 * rows, which changed the alignment requirements and fence programming.
2136 */
2137#define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \
2138 !(IS_I915G(dev_priv) || \
2139 IS_I915GM(dev_priv)))
2140#define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->display.supports_tv)
2141#define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug)
2142
2143#define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
2144#define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.has_fbc)
2145#define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && INTEL_GEN(dev_priv) >= 7)
2146
2147#define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2148
2149#define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst)
2150
2151#define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi)
2152#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->has_fpga_dbg)
2153#define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr)
2154#define HAS_TRANSCODER_EDP(dev_priv) (INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_EDP] != 0)
2155
2156#define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6)
2157#define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p)
2158#define HAS_RC6pp(dev_priv) (false) /* HW was never validated */
2159
2160#define HAS_RPS(dev_priv) (INTEL_INFO(dev_priv)->has_rps)
2161
2162#define HAS_CSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_csr)
2163
2164#define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
2165#define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
2166
2167#define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
2168
2169#define HAS_GT_UC(dev_priv) (INTEL_INFO(dev_priv)->has_gt_uc)
2170
2171/* Having GuC is not the same as using GuC */
2172#define USES_GUC(dev_priv) intel_uc_uses_guc(&(dev_priv)->gt.uc)
2173#define USES_GUC_SUBMISSION(dev_priv) intel_uc_uses_guc_submission(&(dev_priv)->gt.uc)
2174
2175#define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu)
2176
2177#define HAS_GLOBAL_MOCS_REGISTERS(dev_priv) (INTEL_INFO(dev_priv)->has_global_mocs)
2178
2179
2180#define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
2181
2182#define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
2183
2184/* DPF == dynamic parity feature */
2185#define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
2186#define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
2187 2 : HAS_L3_DPF(dev_priv))
2188
2189#define GT_FREQUENCY_MULTIPLIER 50
2190#define GEN9_FREQ_SCALER 3
2191
2192#define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->num_pipes > 0)
2193
2194static inline bool intel_vtd_active(void)
2195{
2196#ifdef CONFIG_INTEL_IOMMU
2197 if (intel_iommu_gfx_mapped)
2198 return true;
2199#endif
2200 return false;
2201}
2202
2203static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
2204{
2205 return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();
2206}
2207
2208static inline bool
2209intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
2210{
2211 return IS_BROXTON(dev_priv) && intel_vtd_active();
2212}
2213
2214/* i915_drv.c */
2215#ifdef CONFIG_COMPAT
2216long i915_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg);
2217#else
2218#define i915_compat_ioctl NULL
2219#endif
2220extern const struct dev_pm_ops i915_pm_ops;
2221
2222int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
2223void i915_driver_remove(struct drm_i915_private *i915);
2224
2225void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
2226int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2227
2228static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
2229{
2230 return dev_priv->gvt;
2231}
2232
2233static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
2234{
2235 return dev_priv->vgpu.active;
2236}
2237
2238int i915_getparam_ioctl(struct drm_device *dev, void *data,
2239 struct drm_file *file_priv);
2240
2241/* i915_gem.c */
2242int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
2243void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
2244void i915_gem_sanitize(struct drm_i915_private *i915);
2245int i915_gem_init_early(struct drm_i915_private *dev_priv);
2246void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
2247int i915_gem_freeze(struct drm_i915_private *dev_priv);
2248int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
2249
2250static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
2251{
2252 /*
2253 * A single pass should suffice to release all the freed objects (along
2254 * most call paths) , but be a little more paranoid in that freeing
2255 * the objects does take a little amount of time, during which the rcu
2256 * callbacks could have added new objects into the freed list, and
2257 * armed the work again.
2258 */
2259 while (atomic_read(&i915->mm.free_count)) {
2260 flush_work(&i915->mm.free_work);
2261 rcu_barrier();
2262 }
2263}
2264
2265static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915)
2266{
2267 /*
2268 * Similar to objects above (see i915_gem_drain_freed-objects), in
2269 * general we have workers that are armed by RCU and then rearm
2270 * themselves in their callbacks. To be paranoid, we need to
2271 * drain the workqueue a second time after waiting for the RCU
2272 * grace period so that we catch work queued via RCU from the first
2273 * pass. As neither drain_workqueue() nor flush_workqueue() report
2274 * a result, we make an assumption that we only don't require more
2275 * than 3 passes to catch all _recursive_ RCU delayed work.
2276 *
2277 */
2278 int pass = 3;
2279 do {
2280 flush_workqueue(i915->wq);
2281 rcu_barrier();
2282 i915_gem_drain_freed_objects(i915);
2283 } while (--pass);
2284 drain_workqueue(i915->wq);
2285}
2286
2287struct i915_vma * __must_check
2288i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
2289 const struct i915_ggtt_view *view,
2290 u64 size,
2291 u64 alignment,
2292 u64 flags);
2293
2294int i915_gem_object_unbind(struct drm_i915_gem_object *obj,
2295 unsigned long flags);
2296#define I915_GEM_OBJECT_UNBIND_ACTIVE BIT(0)
2297
2298struct i915_vma * __must_check
2299i915_gem_object_pin(struct drm_i915_gem_object *obj,
2300 struct i915_address_space *vm,
2301 const struct i915_ggtt_view *view,
2302 u64 size,
2303 u64 alignment,
2304 u64 flags);
2305
2306void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
2307
2308static inline int __must_check
2309i915_mutex_lock_interruptible(struct drm_device *dev)
2310{
2311 return mutex_lock_interruptible(&dev->struct_mutex);
2312}
2313
2314int i915_gem_dumb_create(struct drm_file *file_priv,
2315 struct drm_device *dev,
2316 struct drm_mode_create_dumb *args);
2317int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2318 u32 handle, u64 *offset);
2319int i915_gem_mmap_gtt_version(void);
2320
2321int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
2322
2323static inline u32 i915_reset_count(struct i915_gpu_error *error)
2324{
2325 return atomic_read(&error->reset_count);
2326}
2327
2328static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
2329 struct intel_engine_cs *engine)
2330{
2331 return atomic_read(&error->reset_engine_count[engine->uabi_class]);
2332}
2333
2334void i915_gem_init_mmio(struct drm_i915_private *i915);
2335int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
2336int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
2337void i915_gem_driver_register(struct drm_i915_private *i915);
2338void i915_gem_driver_unregister(struct drm_i915_private *i915);
2339void i915_gem_driver_remove(struct drm_i915_private *dev_priv);
2340void i915_gem_driver_release(struct drm_i915_private *dev_priv);
2341int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
2342 unsigned int flags, long timeout);
2343void i915_gem_suspend(struct drm_i915_private *dev_priv);
2344void i915_gem_suspend_late(struct drm_i915_private *dev_priv);
2345void i915_gem_resume(struct drm_i915_private *dev_priv);
2346vm_fault_t i915_gem_fault(struct vm_fault *vmf);
2347
2348int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
2349void i915_gem_release(struct drm_device *dev, struct drm_file *file);
2350
2351int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2352 enum i915_cache_level cache_level);
2353
2354struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
2355 struct dma_buf *dma_buf);
2356
2357struct dma_buf *i915_gem_prime_export(struct drm_gem_object *gem_obj, int flags);
2358
2359static inline struct i915_gem_context *
2360__i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id)
2361{
2362 return idr_find(&file_priv->context_idr, id);
2363}
2364
2365static inline struct i915_gem_context *
2366i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
2367{
2368 struct i915_gem_context *ctx;
2369
2370 rcu_read_lock();
2371 ctx = __i915_gem_context_lookup_rcu(file_priv, id);
2372 if (ctx && !kref_get_unless_zero(&ctx->ref))
2373 ctx = NULL;
2374 rcu_read_unlock();
2375
2376 return ctx;
2377}
2378
2379/* i915_gem_evict.c */
2380int __must_check i915_gem_evict_something(struct i915_address_space *vm,
2381 u64 min_size, u64 alignment,
2382 unsigned cache_level,
2383 u64 start, u64 end,
2384 unsigned flags);
2385int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
2386 struct drm_mm_node *node,
2387 unsigned int flags);
2388int i915_gem_evict_vm(struct i915_address_space *vm);
2389
2390/* i915_gem_internal.c */
2391struct drm_i915_gem_object *
2392i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
2393 phys_addr_t size);
2394
2395/* i915_gem_tiling.c */
2396static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
2397{
2398 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
2399
2400 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
2401 i915_gem_object_is_tiled(obj);
2402}
2403
2404u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
2405 unsigned int tiling, unsigned int stride);
2406u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
2407 unsigned int tiling, unsigned int stride);
2408
2409const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
2410
2411/* i915_cmd_parser.c */
2412int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
2413void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
2414void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
2415int intel_engine_cmd_parser(struct i915_gem_context *cxt,
2416 struct intel_engine_cs *engine,
2417 struct drm_i915_gem_object *batch_obj,
2418 u64 user_batch_start,
2419 u32 batch_start_offset,
2420 u32 batch_len,
2421 struct drm_i915_gem_object *shadow_batch_obj,
2422 u64 shadow_batch_start);
2423
2424/* intel_device_info.c */
2425static inline struct intel_device_info *
2426mkwrite_device_info(struct drm_i915_private *dev_priv)
2427{
2428 return (struct intel_device_info *)INTEL_INFO(dev_priv);
2429}
2430
2431int i915_reg_read_ioctl(struct drm_device *dev, void *data,
2432 struct drm_file *file);
2433
2434#define __I915_REG_OP(op__, dev_priv__, ...) \
2435 intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
2436
2437#define I915_READ(reg__) __I915_REG_OP(read, dev_priv, (reg__))
2438#define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__))
2439
2440#define POSTING_READ(reg__) __I915_REG_OP(posting_read, dev_priv, (reg__))
2441
2442/* These are untraced mmio-accessors that are only valid to be used inside
2443 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
2444 * controlled.
2445 *
2446 * Think twice, and think again, before using these.
2447 *
2448 * As an example, these accessors can possibly be used between:
2449 *
2450 * spin_lock_irq(&dev_priv->uncore.lock);
2451 * intel_uncore_forcewake_get__locked();
2452 *
2453 * and
2454 *
2455 * intel_uncore_forcewake_put__locked();
2456 * spin_unlock_irq(&dev_priv->uncore.lock);
2457 *
2458 *
2459 * Note: some registers may not need forcewake held, so
2460 * intel_uncore_forcewake_{get,put} can be omitted, see
2461 * intel_uncore_forcewake_for_reg().
2462 *
2463 * Certain architectures will die if the same cacheline is concurrently accessed
2464 * by different clients (e.g. on Ivybridge). Access to registers should
2465 * therefore generally be serialised, by either the dev_priv->uncore.lock or
2466 * a more localised lock guarding all access to that bank of registers.
2467 */
2468#define I915_READ_FW(reg__) __I915_REG_OP(read_fw, dev_priv, (reg__))
2469#define I915_WRITE_FW(reg__, val__) __I915_REG_OP(write_fw, dev_priv, (reg__), (val__))
2470
2471/* register wait wrappers for display regs */
2472#define intel_de_wait_for_register(dev_priv_, reg_, mask_, value_, timeout_) \
2473 intel_wait_for_register(&(dev_priv_)->uncore, \
2474 (reg_), (mask_), (value_), (timeout_))
2475
2476#define intel_de_wait_for_set(dev_priv_, reg_, mask_, timeout_) ({ \
2477 u32 mask__ = (mask_); \
2478 intel_de_wait_for_register((dev_priv_), (reg_), \
2479 mask__, mask__, (timeout_)); \
2480})
2481
2482#define intel_de_wait_for_clear(dev_priv_, reg_, mask_, timeout_) \
2483 intel_de_wait_for_register((dev_priv_), (reg_), (mask_), 0, (timeout_))
2484
2485/* i915_mm.c */
2486int remap_io_mapping(struct vm_area_struct *vma,
2487 unsigned long addr, unsigned long pfn, unsigned long size,
2488 struct io_mapping *iomap);
2489
2490static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
2491{
2492 if (INTEL_GEN(i915) >= 10)
2493 return CNL_HWS_CSB_WRITE_INDEX;
2494 else
2495 return I915_HWS_CSB_WRITE_INDEX;
2496}
2497
2498static inline enum i915_map_type
2499i915_coherent_map_type(struct drm_i915_private *i915)
2500{
2501 return HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC;
2502}
2503
2504#endif