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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
4 * datasheet: http://www.ti.com/lit/ds/symlink/sn65dsi86.pdf
5 */
6
7#include <linux/clk.h>
8#include <linux/debugfs.h>
9#include <linux/gpio/consumer.h>
10#include <linux/i2c.h>
11#include <linux/iopoll.h>
12#include <linux/module.h>
13#include <linux/of_graph.h>
14#include <linux/pm_runtime.h>
15#include <linux/regmap.h>
16#include <linux/regulator/consumer.h>
17
18#include <drm/drm_atomic.h>
19#include <drm/drm_atomic_helper.h>
20#include <drm/drm_dp_helper.h>
21#include <drm/drm_mipi_dsi.h>
22#include <drm/drm_of.h>
23#include <drm/drm_panel.h>
24#include <drm/drm_print.h>
25#include <drm/drm_probe_helper.h>
26
27#define SN_DEVICE_REV_REG 0x08
28#define SN_DPPLL_SRC_REG 0x0A
29#define DPPLL_CLK_SRC_DSICLK BIT(0)
30#define REFCLK_FREQ_MASK GENMASK(3, 1)
31#define REFCLK_FREQ(x) ((x) << 1)
32#define DPPLL_SRC_DP_PLL_LOCK BIT(7)
33#define SN_PLL_ENABLE_REG 0x0D
34#define SN_DSI_LANES_REG 0x10
35#define CHA_DSI_LANES_MASK GENMASK(4, 3)
36#define CHA_DSI_LANES(x) ((x) << 3)
37#define SN_DSIA_CLK_FREQ_REG 0x12
38#define SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG 0x20
39#define SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG 0x24
40#define SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG 0x2C
41#define SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG 0x2D
42#define CHA_HSYNC_POLARITY BIT(7)
43#define SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG 0x30
44#define SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG 0x31
45#define CHA_VSYNC_POLARITY BIT(7)
46#define SN_CHA_HORIZONTAL_BACK_PORCH_REG 0x34
47#define SN_CHA_VERTICAL_BACK_PORCH_REG 0x36
48#define SN_CHA_HORIZONTAL_FRONT_PORCH_REG 0x38
49#define SN_CHA_VERTICAL_FRONT_PORCH_REG 0x3A
50#define SN_ENH_FRAME_REG 0x5A
51#define VSTREAM_ENABLE BIT(3)
52#define SN_DATA_FORMAT_REG 0x5B
53#define SN_HPD_DISABLE_REG 0x5C
54#define HPD_DISABLE BIT(0)
55#define SN_AUX_WDATA_REG(x) (0x64 + (x))
56#define SN_AUX_ADDR_19_16_REG 0x74
57#define SN_AUX_ADDR_15_8_REG 0x75
58#define SN_AUX_ADDR_7_0_REG 0x76
59#define SN_AUX_LENGTH_REG 0x77
60#define SN_AUX_CMD_REG 0x78
61#define AUX_CMD_SEND BIT(0)
62#define AUX_CMD_REQ(x) ((x) << 4)
63#define SN_AUX_RDATA_REG(x) (0x79 + (x))
64#define SN_SSC_CONFIG_REG 0x93
65#define DP_NUM_LANES_MASK GENMASK(5, 4)
66#define DP_NUM_LANES(x) ((x) << 4)
67#define SN_DATARATE_CONFIG_REG 0x94
68#define DP_DATARATE_MASK GENMASK(7, 5)
69#define DP_DATARATE(x) ((x) << 5)
70#define SN_ML_TX_MODE_REG 0x96
71#define ML_TX_MAIN_LINK_OFF 0
72#define ML_TX_NORMAL_MODE BIT(0)
73#define SN_AUX_CMD_STATUS_REG 0xF4
74#define AUX_IRQ_STATUS_AUX_RPLY_TOUT BIT(3)
75#define AUX_IRQ_STATUS_AUX_SHORT BIT(5)
76#define AUX_IRQ_STATUS_NAT_I2C_FAIL BIT(6)
77
78#define MIN_DSI_CLK_FREQ_MHZ 40
79
80/* fudge factor required to account for 8b/10b encoding */
81#define DP_CLK_FUDGE_NUM 10
82#define DP_CLK_FUDGE_DEN 8
83
84/* Matches DP_AUX_MAX_PAYLOAD_BYTES (for now) */
85#define SN_AUX_MAX_PAYLOAD_BYTES 16
86
87#define SN_REGULATOR_SUPPLY_NUM 4
88
89struct ti_sn_bridge {
90 struct device *dev;
91 struct regmap *regmap;
92 struct drm_dp_aux aux;
93 struct drm_bridge bridge;
94 struct drm_connector connector;
95 struct dentry *debugfs;
96 struct device_node *host_node;
97 struct mipi_dsi_device *dsi;
98 struct clk *refclk;
99 struct drm_panel *panel;
100 struct gpio_desc *enable_gpio;
101 struct regulator_bulk_data supplies[SN_REGULATOR_SUPPLY_NUM];
102};
103
104static const struct regmap_range ti_sn_bridge_volatile_ranges[] = {
105 { .range_min = 0, .range_max = 0xFF },
106};
107
108static const struct regmap_access_table ti_sn_bridge_volatile_table = {
109 .yes_ranges = ti_sn_bridge_volatile_ranges,
110 .n_yes_ranges = ARRAY_SIZE(ti_sn_bridge_volatile_ranges),
111};
112
113static const struct regmap_config ti_sn_bridge_regmap_config = {
114 .reg_bits = 8,
115 .val_bits = 8,
116 .volatile_table = &ti_sn_bridge_volatile_table,
117 .cache_type = REGCACHE_NONE,
118};
119
120static void ti_sn_bridge_write_u16(struct ti_sn_bridge *pdata,
121 unsigned int reg, u16 val)
122{
123 regmap_write(pdata->regmap, reg, val & 0xFF);
124 regmap_write(pdata->regmap, reg + 1, val >> 8);
125}
126
127static int __maybe_unused ti_sn_bridge_resume(struct device *dev)
128{
129 struct ti_sn_bridge *pdata = dev_get_drvdata(dev);
130 int ret;
131
132 ret = regulator_bulk_enable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies);
133 if (ret) {
134 DRM_ERROR("failed to enable supplies %d\n", ret);
135 return ret;
136 }
137
138 gpiod_set_value(pdata->enable_gpio, 1);
139
140 return ret;
141}
142
143static int __maybe_unused ti_sn_bridge_suspend(struct device *dev)
144{
145 struct ti_sn_bridge *pdata = dev_get_drvdata(dev);
146 int ret;
147
148 gpiod_set_value(pdata->enable_gpio, 0);
149
150 ret = regulator_bulk_disable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies);
151 if (ret)
152 DRM_ERROR("failed to disable supplies %d\n", ret);
153
154 return ret;
155}
156
157static const struct dev_pm_ops ti_sn_bridge_pm_ops = {
158 SET_RUNTIME_PM_OPS(ti_sn_bridge_suspend, ti_sn_bridge_resume, NULL)
159};
160
161static int status_show(struct seq_file *s, void *data)
162{
163 struct ti_sn_bridge *pdata = s->private;
164 unsigned int reg, val;
165
166 seq_puts(s, "STATUS REGISTERS:\n");
167
168 pm_runtime_get_sync(pdata->dev);
169
170 /* IRQ Status Registers, see Table 31 in datasheet */
171 for (reg = 0xf0; reg <= 0xf8; reg++) {
172 regmap_read(pdata->regmap, reg, &val);
173 seq_printf(s, "[0x%02x] = 0x%08x\n", reg, val);
174 }
175
176 pm_runtime_put(pdata->dev);
177
178 return 0;
179}
180
181DEFINE_SHOW_ATTRIBUTE(status);
182
183static void ti_sn_debugfs_init(struct ti_sn_bridge *pdata)
184{
185 pdata->debugfs = debugfs_create_dir(dev_name(pdata->dev), NULL);
186
187 debugfs_create_file("status", 0600, pdata->debugfs, pdata,
188 &status_fops);
189}
190
191static void ti_sn_debugfs_remove(struct ti_sn_bridge *pdata)
192{
193 debugfs_remove_recursive(pdata->debugfs);
194 pdata->debugfs = NULL;
195}
196
197/* Connector funcs */
198static struct ti_sn_bridge *
199connector_to_ti_sn_bridge(struct drm_connector *connector)
200{
201 return container_of(connector, struct ti_sn_bridge, connector);
202}
203
204static int ti_sn_bridge_connector_get_modes(struct drm_connector *connector)
205{
206 struct ti_sn_bridge *pdata = connector_to_ti_sn_bridge(connector);
207
208 return drm_panel_get_modes(pdata->panel);
209}
210
211static enum drm_mode_status
212ti_sn_bridge_connector_mode_valid(struct drm_connector *connector,
213 struct drm_display_mode *mode)
214{
215 /* maximum supported resolution is 4K at 60 fps */
216 if (mode->clock > 594000)
217 return MODE_CLOCK_HIGH;
218
219 return MODE_OK;
220}
221
222static struct drm_connector_helper_funcs ti_sn_bridge_connector_helper_funcs = {
223 .get_modes = ti_sn_bridge_connector_get_modes,
224 .mode_valid = ti_sn_bridge_connector_mode_valid,
225};
226
227static enum drm_connector_status
228ti_sn_bridge_connector_detect(struct drm_connector *connector, bool force)
229{
230 /**
231 * TODO: Currently if drm_panel is present, then always
232 * return the status as connected. Need to add support to detect
233 * device state for hot pluggable scenarios.
234 */
235 return connector_status_connected;
236}
237
238static const struct drm_connector_funcs ti_sn_bridge_connector_funcs = {
239 .fill_modes = drm_helper_probe_single_connector_modes,
240 .detect = ti_sn_bridge_connector_detect,
241 .destroy = drm_connector_cleanup,
242 .reset = drm_atomic_helper_connector_reset,
243 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
244 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
245};
246
247static struct ti_sn_bridge *bridge_to_ti_sn_bridge(struct drm_bridge *bridge)
248{
249 return container_of(bridge, struct ti_sn_bridge, bridge);
250}
251
252static int ti_sn_bridge_parse_regulators(struct ti_sn_bridge *pdata)
253{
254 unsigned int i;
255 const char * const ti_sn_bridge_supply_names[] = {
256 "vcca", "vcc", "vccio", "vpll",
257 };
258
259 for (i = 0; i < SN_REGULATOR_SUPPLY_NUM; i++)
260 pdata->supplies[i].supply = ti_sn_bridge_supply_names[i];
261
262 return devm_regulator_bulk_get(pdata->dev, SN_REGULATOR_SUPPLY_NUM,
263 pdata->supplies);
264}
265
266static int ti_sn_bridge_attach(struct drm_bridge *bridge)
267{
268 int ret, val;
269 struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
270 struct mipi_dsi_host *host;
271 struct mipi_dsi_device *dsi;
272 const struct mipi_dsi_device_info info = { .type = "ti_sn_bridge",
273 .channel = 0,
274 .node = NULL,
275 };
276
277 ret = drm_connector_init(bridge->dev, &pdata->connector,
278 &ti_sn_bridge_connector_funcs,
279 DRM_MODE_CONNECTOR_eDP);
280 if (ret) {
281 DRM_ERROR("Failed to initialize connector with drm\n");
282 return ret;
283 }
284
285 drm_connector_helper_add(&pdata->connector,
286 &ti_sn_bridge_connector_helper_funcs);
287 drm_connector_attach_encoder(&pdata->connector, bridge->encoder);
288
289 /*
290 * TODO: ideally finding host resource and dsi dev registration needs
291 * to be done in bridge probe. But some existing DSI host drivers will
292 * wait for any of the drm_bridge/drm_panel to get added to the global
293 * bridge/panel list, before completing their probe. So if we do the
294 * dsi dev registration part in bridge probe, before populating in
295 * the global bridge list, then it will cause deadlock as dsi host probe
296 * will never complete, neither our bridge probe. So keeping it here
297 * will satisfy most of the existing host drivers. Once the host driver
298 * is fixed we can move the below code to bridge probe safely.
299 */
300 host = of_find_mipi_dsi_host_by_node(pdata->host_node);
301 if (!host) {
302 DRM_ERROR("failed to find dsi host\n");
303 ret = -ENODEV;
304 goto err_dsi_host;
305 }
306
307 dsi = mipi_dsi_device_register_full(host, &info);
308 if (IS_ERR(dsi)) {
309 DRM_ERROR("failed to create dsi device\n");
310 ret = PTR_ERR(dsi);
311 goto err_dsi_host;
312 }
313
314 /* TODO: setting to 4 lanes always for now */
315 dsi->lanes = 4;
316 dsi->format = MIPI_DSI_FMT_RGB888;
317 dsi->mode_flags = MIPI_DSI_MODE_VIDEO;
318
319 /* check if continuous dsi clock is required or not */
320 pm_runtime_get_sync(pdata->dev);
321 regmap_read(pdata->regmap, SN_DPPLL_SRC_REG, &val);
322 pm_runtime_put(pdata->dev);
323 if (!(val & DPPLL_CLK_SRC_DSICLK))
324 dsi->mode_flags |= MIPI_DSI_CLOCK_NON_CONTINUOUS;
325
326 ret = mipi_dsi_attach(dsi);
327 if (ret < 0) {
328 DRM_ERROR("failed to attach dsi to host\n");
329 goto err_dsi_attach;
330 }
331 pdata->dsi = dsi;
332
333 /* attach panel to bridge */
334 drm_panel_attach(pdata->panel, &pdata->connector);
335
336 return 0;
337
338err_dsi_attach:
339 mipi_dsi_device_unregister(dsi);
340err_dsi_host:
341 drm_connector_cleanup(&pdata->connector);
342 return ret;
343}
344
345static void ti_sn_bridge_disable(struct drm_bridge *bridge)
346{
347 struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
348
349 drm_panel_disable(pdata->panel);
350
351 /* disable video stream */
352 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE, 0);
353 /* semi auto link training mode OFF */
354 regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0);
355 /* disable DP PLL */
356 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0);
357
358 drm_panel_unprepare(pdata->panel);
359}
360
361static u32 ti_sn_bridge_get_dsi_freq(struct ti_sn_bridge *pdata)
362{
363 u32 bit_rate_khz, clk_freq_khz;
364 struct drm_display_mode *mode =
365 &pdata->bridge.encoder->crtc->state->adjusted_mode;
366
367 bit_rate_khz = mode->clock *
368 mipi_dsi_pixel_format_to_bpp(pdata->dsi->format);
369 clk_freq_khz = bit_rate_khz / (pdata->dsi->lanes * 2);
370
371 return clk_freq_khz;
372}
373
374/* clk frequencies supported by bridge in Hz in case derived from REFCLK pin */
375static const u32 ti_sn_bridge_refclk_lut[] = {
376 12000000,
377 19200000,
378 26000000,
379 27000000,
380 38400000,
381};
382
383/* clk frequencies supported by bridge in Hz in case derived from DACP/N pin */
384static const u32 ti_sn_bridge_dsiclk_lut[] = {
385 468000000,
386 384000000,
387 416000000,
388 486000000,
389 460800000,
390};
391
392static void ti_sn_bridge_set_refclk_freq(struct ti_sn_bridge *pdata)
393{
394 int i;
395 u32 refclk_rate;
396 const u32 *refclk_lut;
397 size_t refclk_lut_size;
398
399 if (pdata->refclk) {
400 refclk_rate = clk_get_rate(pdata->refclk);
401 refclk_lut = ti_sn_bridge_refclk_lut;
402 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_refclk_lut);
403 clk_prepare_enable(pdata->refclk);
404 } else {
405 refclk_rate = ti_sn_bridge_get_dsi_freq(pdata) * 1000;
406 refclk_lut = ti_sn_bridge_dsiclk_lut;
407 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_dsiclk_lut);
408 }
409
410 /* for i equals to refclk_lut_size means default frequency */
411 for (i = 0; i < refclk_lut_size; i++)
412 if (refclk_lut[i] == refclk_rate)
413 break;
414
415 regmap_update_bits(pdata->regmap, SN_DPPLL_SRC_REG, REFCLK_FREQ_MASK,
416 REFCLK_FREQ(i));
417}
418
419/**
420 * LUT index corresponds to register value and
421 * LUT values corresponds to dp data rate supported
422 * by the bridge in Mbps unit.
423 */
424static const unsigned int ti_sn_bridge_dp_rate_lut[] = {
425 0, 1620, 2160, 2430, 2700, 3240, 4320, 5400
426};
427
428static void ti_sn_bridge_set_dsi_dp_rate(struct ti_sn_bridge *pdata)
429{
430 unsigned int bit_rate_mhz, clk_freq_mhz, dp_rate_mhz;
431 unsigned int val, i;
432 struct drm_display_mode *mode =
433 &pdata->bridge.encoder->crtc->state->adjusted_mode;
434
435 /* set DSIA clk frequency */
436 bit_rate_mhz = (mode->clock / 1000) *
437 mipi_dsi_pixel_format_to_bpp(pdata->dsi->format);
438 clk_freq_mhz = bit_rate_mhz / (pdata->dsi->lanes * 2);
439
440 /* for each increment in val, frequency increases by 5MHz */
441 val = (MIN_DSI_CLK_FREQ_MHZ / 5) +
442 (((clk_freq_mhz - MIN_DSI_CLK_FREQ_MHZ) / 5) & 0xFF);
443 regmap_write(pdata->regmap, SN_DSIA_CLK_FREQ_REG, val);
444
445 /* set DP data rate */
446 dp_rate_mhz = ((bit_rate_mhz / pdata->dsi->lanes) * DP_CLK_FUDGE_NUM) /
447 DP_CLK_FUDGE_DEN;
448 for (i = 0; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut) - 1; i++)
449 if (ti_sn_bridge_dp_rate_lut[i] > dp_rate_mhz)
450 break;
451
452 regmap_update_bits(pdata->regmap, SN_DATARATE_CONFIG_REG,
453 DP_DATARATE_MASK, DP_DATARATE(i));
454}
455
456static void ti_sn_bridge_set_video_timings(struct ti_sn_bridge *pdata)
457{
458 struct drm_display_mode *mode =
459 &pdata->bridge.encoder->crtc->state->adjusted_mode;
460 u8 hsync_polarity = 0, vsync_polarity = 0;
461
462 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
463 hsync_polarity = CHA_HSYNC_POLARITY;
464 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
465 vsync_polarity = CHA_VSYNC_POLARITY;
466
467 ti_sn_bridge_write_u16(pdata, SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG,
468 mode->hdisplay);
469 ti_sn_bridge_write_u16(pdata, SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG,
470 mode->vdisplay);
471 regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG,
472 (mode->hsync_end - mode->hsync_start) & 0xFF);
473 regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG,
474 (((mode->hsync_end - mode->hsync_start) >> 8) & 0x7F) |
475 hsync_polarity);
476 regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG,
477 (mode->vsync_end - mode->vsync_start) & 0xFF);
478 regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG,
479 (((mode->vsync_end - mode->vsync_start) >> 8) & 0x7F) |
480 vsync_polarity);
481
482 regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_BACK_PORCH_REG,
483 (mode->htotal - mode->hsync_end) & 0xFF);
484 regmap_write(pdata->regmap, SN_CHA_VERTICAL_BACK_PORCH_REG,
485 (mode->vtotal - mode->vsync_end) & 0xFF);
486
487 regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_FRONT_PORCH_REG,
488 (mode->hsync_start - mode->hdisplay) & 0xFF);
489 regmap_write(pdata->regmap, SN_CHA_VERTICAL_FRONT_PORCH_REG,
490 (mode->vsync_start - mode->vdisplay) & 0xFF);
491
492 usleep_range(10000, 10500); /* 10ms delay recommended by spec */
493}
494
495static void ti_sn_bridge_enable(struct drm_bridge *bridge)
496{
497 struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
498 unsigned int val;
499 int ret;
500
501 /* DSI_A lane config */
502 val = CHA_DSI_LANES(4 - pdata->dsi->lanes);
503 regmap_update_bits(pdata->regmap, SN_DSI_LANES_REG,
504 CHA_DSI_LANES_MASK, val);
505
506 /* DP lane config */
507 val = DP_NUM_LANES(pdata->dsi->lanes - 1);
508 regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK,
509 val);
510
511 /* set dsi/dp clk frequency value */
512 ti_sn_bridge_set_dsi_dp_rate(pdata);
513
514 /* enable DP PLL */
515 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 1);
516
517 ret = regmap_read_poll_timeout(pdata->regmap, SN_DPPLL_SRC_REG, val,
518 val & DPPLL_SRC_DP_PLL_LOCK, 1000,
519 50 * 1000);
520 if (ret) {
521 DRM_ERROR("DP_PLL_LOCK polling failed (%d)\n", ret);
522 return;
523 }
524
525 /**
526 * The SN65DSI86 only supports ASSR Display Authentication method and
527 * this method is enabled by default. An eDP panel must support this
528 * authentication method. We need to enable this method in the eDP panel
529 * at DisplayPort address 0x0010A prior to link training.
530 */
531 drm_dp_dpcd_writeb(&pdata->aux, DP_EDP_CONFIGURATION_SET,
532 DP_ALTERNATE_SCRAMBLER_RESET_ENABLE);
533
534 /* Semi auto link training mode */
535 regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0x0A);
536 ret = regmap_read_poll_timeout(pdata->regmap, SN_ML_TX_MODE_REG, val,
537 val == ML_TX_MAIN_LINK_OFF ||
538 val == ML_TX_NORMAL_MODE, 1000,
539 500 * 1000);
540 if (ret) {
541 DRM_ERROR("Training complete polling failed (%d)\n", ret);
542 return;
543 } else if (val == ML_TX_MAIN_LINK_OFF) {
544 DRM_ERROR("Link training failed, link is off\n");
545 return;
546 }
547
548 /* config video parameters */
549 ti_sn_bridge_set_video_timings(pdata);
550
551 /* enable video stream */
552 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE,
553 VSTREAM_ENABLE);
554
555 drm_panel_enable(pdata->panel);
556}
557
558static void ti_sn_bridge_pre_enable(struct drm_bridge *bridge)
559{
560 struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
561
562 pm_runtime_get_sync(pdata->dev);
563
564 /* configure bridge ref_clk */
565 ti_sn_bridge_set_refclk_freq(pdata);
566
567 /*
568 * HPD on this bridge chip is a bit useless. This is an eDP bridge
569 * so the HPD is an internal signal that's only there to signal that
570 * the panel is done powering up. ...but the bridge chip debounces
571 * this signal by between 100 ms and 400 ms (depending on process,
572 * voltage, and temperate--I measured it at about 200 ms). One
573 * particular panel asserted HPD 84 ms after it was powered on meaning
574 * that we saw HPD 284 ms after power on. ...but the same panel said
575 * that instead of looking at HPD you could just hardcode a delay of
576 * 200 ms. We'll assume that the panel driver will have the hardcoded
577 * delay in its prepare and always disable HPD.
578 *
579 * If HPD somehow makes sense on some future panel we'll have to
580 * change this to be conditional on someone specifying that HPD should
581 * be used.
582 */
583 regmap_update_bits(pdata->regmap, SN_HPD_DISABLE_REG, HPD_DISABLE,
584 HPD_DISABLE);
585
586 drm_panel_prepare(pdata->panel);
587}
588
589static void ti_sn_bridge_post_disable(struct drm_bridge *bridge)
590{
591 struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
592
593 if (pdata->refclk)
594 clk_disable_unprepare(pdata->refclk);
595
596 pm_runtime_put_sync(pdata->dev);
597}
598
599static const struct drm_bridge_funcs ti_sn_bridge_funcs = {
600 .attach = ti_sn_bridge_attach,
601 .pre_enable = ti_sn_bridge_pre_enable,
602 .enable = ti_sn_bridge_enable,
603 .disable = ti_sn_bridge_disable,
604 .post_disable = ti_sn_bridge_post_disable,
605};
606
607static struct ti_sn_bridge *aux_to_ti_sn_bridge(struct drm_dp_aux *aux)
608{
609 return container_of(aux, struct ti_sn_bridge, aux);
610}
611
612static ssize_t ti_sn_aux_transfer(struct drm_dp_aux *aux,
613 struct drm_dp_aux_msg *msg)
614{
615 struct ti_sn_bridge *pdata = aux_to_ti_sn_bridge(aux);
616 u32 request = msg->request & ~DP_AUX_I2C_MOT;
617 u32 request_val = AUX_CMD_REQ(msg->request);
618 u8 *buf = (u8 *)msg->buffer;
619 unsigned int val;
620 int ret, i;
621
622 if (msg->size > SN_AUX_MAX_PAYLOAD_BYTES)
623 return -EINVAL;
624
625 switch (request) {
626 case DP_AUX_NATIVE_WRITE:
627 case DP_AUX_I2C_WRITE:
628 case DP_AUX_NATIVE_READ:
629 case DP_AUX_I2C_READ:
630 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val);
631 break;
632 default:
633 return -EINVAL;
634 }
635
636 regmap_write(pdata->regmap, SN_AUX_ADDR_19_16_REG,
637 (msg->address >> 16) & 0xF);
638 regmap_write(pdata->regmap, SN_AUX_ADDR_15_8_REG,
639 (msg->address >> 8) & 0xFF);
640 regmap_write(pdata->regmap, SN_AUX_ADDR_7_0_REG, msg->address & 0xFF);
641
642 regmap_write(pdata->regmap, SN_AUX_LENGTH_REG, msg->size);
643
644 if (request == DP_AUX_NATIVE_WRITE || request == DP_AUX_I2C_WRITE) {
645 for (i = 0; i < msg->size; i++)
646 regmap_write(pdata->regmap, SN_AUX_WDATA_REG(i),
647 buf[i]);
648 }
649
650 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val | AUX_CMD_SEND);
651
652 ret = regmap_read_poll_timeout(pdata->regmap, SN_AUX_CMD_REG, val,
653 !(val & AUX_CMD_SEND), 200,
654 50 * 1000);
655 if (ret)
656 return ret;
657
658 ret = regmap_read(pdata->regmap, SN_AUX_CMD_STATUS_REG, &val);
659 if (ret)
660 return ret;
661 else if ((val & AUX_IRQ_STATUS_NAT_I2C_FAIL)
662 || (val & AUX_IRQ_STATUS_AUX_RPLY_TOUT)
663 || (val & AUX_IRQ_STATUS_AUX_SHORT))
664 return -ENXIO;
665
666 if (request == DP_AUX_NATIVE_WRITE || request == DP_AUX_I2C_WRITE)
667 return msg->size;
668
669 for (i = 0; i < msg->size; i++) {
670 unsigned int val;
671 ret = regmap_read(pdata->regmap, SN_AUX_RDATA_REG(i),
672 &val);
673 if (ret)
674 return ret;
675
676 WARN_ON(val & ~0xFF);
677 buf[i] = (u8)(val & 0xFF);
678 }
679
680 return msg->size;
681}
682
683static int ti_sn_bridge_parse_dsi_host(struct ti_sn_bridge *pdata)
684{
685 struct device_node *np = pdata->dev->of_node;
686
687 pdata->host_node = of_graph_get_remote_node(np, 0, 0);
688
689 if (!pdata->host_node) {
690 DRM_ERROR("remote dsi host node not found\n");
691 return -ENODEV;
692 }
693
694 return 0;
695}
696
697static int ti_sn_bridge_probe(struct i2c_client *client,
698 const struct i2c_device_id *id)
699{
700 struct ti_sn_bridge *pdata;
701 int ret;
702
703 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
704 DRM_ERROR("device doesn't support I2C\n");
705 return -ENODEV;
706 }
707
708 pdata = devm_kzalloc(&client->dev, sizeof(struct ti_sn_bridge),
709 GFP_KERNEL);
710 if (!pdata)
711 return -ENOMEM;
712
713 pdata->regmap = devm_regmap_init_i2c(client,
714 &ti_sn_bridge_regmap_config);
715 if (IS_ERR(pdata->regmap)) {
716 DRM_ERROR("regmap i2c init failed\n");
717 return PTR_ERR(pdata->regmap);
718 }
719
720 pdata->dev = &client->dev;
721
722 ret = drm_of_find_panel_or_bridge(pdata->dev->of_node, 1, 0,
723 &pdata->panel, NULL);
724 if (ret) {
725 DRM_ERROR("could not find any panel node\n");
726 return ret;
727 }
728
729 dev_set_drvdata(&client->dev, pdata);
730
731 pdata->enable_gpio = devm_gpiod_get(pdata->dev, "enable",
732 GPIOD_OUT_LOW);
733 if (IS_ERR(pdata->enable_gpio)) {
734 DRM_ERROR("failed to get enable gpio from DT\n");
735 ret = PTR_ERR(pdata->enable_gpio);
736 return ret;
737 }
738
739 ret = ti_sn_bridge_parse_regulators(pdata);
740 if (ret) {
741 DRM_ERROR("failed to parse regulators\n");
742 return ret;
743 }
744
745 pdata->refclk = devm_clk_get(pdata->dev, "refclk");
746 if (IS_ERR(pdata->refclk)) {
747 ret = PTR_ERR(pdata->refclk);
748 if (ret == -EPROBE_DEFER)
749 return ret;
750 DRM_DEBUG_KMS("refclk not found\n");
751 pdata->refclk = NULL;
752 }
753
754 ret = ti_sn_bridge_parse_dsi_host(pdata);
755 if (ret)
756 return ret;
757
758 pm_runtime_enable(pdata->dev);
759
760 i2c_set_clientdata(client, pdata);
761
762 pdata->aux.name = "ti-sn65dsi86-aux";
763 pdata->aux.dev = pdata->dev;
764 pdata->aux.transfer = ti_sn_aux_transfer;
765 drm_dp_aux_register(&pdata->aux);
766
767 pdata->bridge.funcs = &ti_sn_bridge_funcs;
768 pdata->bridge.of_node = client->dev.of_node;
769
770 drm_bridge_add(&pdata->bridge);
771
772 ti_sn_debugfs_init(pdata);
773
774 return 0;
775}
776
777static int ti_sn_bridge_remove(struct i2c_client *client)
778{
779 struct ti_sn_bridge *pdata = i2c_get_clientdata(client);
780
781 if (!pdata)
782 return -EINVAL;
783
784 ti_sn_debugfs_remove(pdata);
785
786 of_node_put(pdata->host_node);
787
788 pm_runtime_disable(pdata->dev);
789
790 if (pdata->dsi) {
791 mipi_dsi_detach(pdata->dsi);
792 mipi_dsi_device_unregister(pdata->dsi);
793 }
794
795 drm_bridge_remove(&pdata->bridge);
796
797 return 0;
798}
799
800static struct i2c_device_id ti_sn_bridge_id[] = {
801 { "ti,sn65dsi86", 0},
802 {},
803};
804MODULE_DEVICE_TABLE(i2c, ti_sn_bridge_id);
805
806static const struct of_device_id ti_sn_bridge_match_table[] = {
807 {.compatible = "ti,sn65dsi86"},
808 {},
809};
810MODULE_DEVICE_TABLE(of, ti_sn_bridge_match_table);
811
812static struct i2c_driver ti_sn_bridge_driver = {
813 .driver = {
814 .name = "ti_sn65dsi86",
815 .of_match_table = ti_sn_bridge_match_table,
816 .pm = &ti_sn_bridge_pm_ops,
817 },
818 .probe = ti_sn_bridge_probe,
819 .remove = ti_sn_bridge_remove,
820 .id_table = ti_sn_bridge_id,
821};
822module_i2c_driver(ti_sn_bridge_driver);
823
824MODULE_AUTHOR("Sandeep Panda <spanda@codeaurora.org>");
825MODULE_DESCRIPTION("sn65dsi86 DSI to eDP bridge driver");
826MODULE_LICENSE("GPL v2");