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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
4 * datasheet: https://www.ti.com/lit/ds/symlink/sn65dsi86.pdf
5 */
6
7#include <linux/bits.h>
8#include <linux/clk.h>
9#include <linux/debugfs.h>
10#include <linux/gpio/consumer.h>
11#include <linux/gpio/driver.h>
12#include <linux/i2c.h>
13#include <linux/iopoll.h>
14#include <linux/module.h>
15#include <linux/of_graph.h>
16#include <linux/pm_runtime.h>
17#include <linux/regmap.h>
18#include <linux/regulator/consumer.h>
19
20#include <drm/drm_atomic.h>
21#include <drm/drm_atomic_helper.h>
22#include <drm/drm_bridge.h>
23#include <drm/drm_dp_helper.h>
24#include <drm/drm_mipi_dsi.h>
25#include <drm/drm_of.h>
26#include <drm/drm_panel.h>
27#include <drm/drm_print.h>
28#include <drm/drm_probe_helper.h>
29
30#define SN_DEVICE_REV_REG 0x08
31#define SN_DPPLL_SRC_REG 0x0A
32#define DPPLL_CLK_SRC_DSICLK BIT(0)
33#define REFCLK_FREQ_MASK GENMASK(3, 1)
34#define REFCLK_FREQ(x) ((x) << 1)
35#define DPPLL_SRC_DP_PLL_LOCK BIT(7)
36#define SN_PLL_ENABLE_REG 0x0D
37#define SN_DSI_LANES_REG 0x10
38#define CHA_DSI_LANES_MASK GENMASK(4, 3)
39#define CHA_DSI_LANES(x) ((x) << 3)
40#define SN_DSIA_CLK_FREQ_REG 0x12
41#define SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG 0x20
42#define SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG 0x24
43#define SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG 0x2C
44#define SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG 0x2D
45#define CHA_HSYNC_POLARITY BIT(7)
46#define SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG 0x30
47#define SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG 0x31
48#define CHA_VSYNC_POLARITY BIT(7)
49#define SN_CHA_HORIZONTAL_BACK_PORCH_REG 0x34
50#define SN_CHA_VERTICAL_BACK_PORCH_REG 0x36
51#define SN_CHA_HORIZONTAL_FRONT_PORCH_REG 0x38
52#define SN_CHA_VERTICAL_FRONT_PORCH_REG 0x3A
53#define SN_LN_ASSIGN_REG 0x59
54#define LN_ASSIGN_WIDTH 2
55#define SN_ENH_FRAME_REG 0x5A
56#define VSTREAM_ENABLE BIT(3)
57#define LN_POLRS_OFFSET 4
58#define LN_POLRS_MASK 0xf0
59#define SN_DATA_FORMAT_REG 0x5B
60#define BPP_18_RGB BIT(0)
61#define SN_HPD_DISABLE_REG 0x5C
62#define HPD_DISABLE BIT(0)
63#define SN_GPIO_IO_REG 0x5E
64#define SN_GPIO_INPUT_SHIFT 4
65#define SN_GPIO_OUTPUT_SHIFT 0
66#define SN_GPIO_CTRL_REG 0x5F
67#define SN_GPIO_MUX_INPUT 0
68#define SN_GPIO_MUX_OUTPUT 1
69#define SN_GPIO_MUX_SPECIAL 2
70#define SN_GPIO_MUX_MASK 0x3
71#define SN_AUX_WDATA_REG(x) (0x64 + (x))
72#define SN_AUX_ADDR_19_16_REG 0x74
73#define SN_AUX_ADDR_15_8_REG 0x75
74#define SN_AUX_ADDR_7_0_REG 0x76
75#define SN_AUX_LENGTH_REG 0x77
76#define SN_AUX_CMD_REG 0x78
77#define AUX_CMD_SEND BIT(0)
78#define AUX_CMD_REQ(x) ((x) << 4)
79#define SN_AUX_RDATA_REG(x) (0x79 + (x))
80#define SN_SSC_CONFIG_REG 0x93
81#define DP_NUM_LANES_MASK GENMASK(5, 4)
82#define DP_NUM_LANES(x) ((x) << 4)
83#define SN_DATARATE_CONFIG_REG 0x94
84#define DP_DATARATE_MASK GENMASK(7, 5)
85#define DP_DATARATE(x) ((x) << 5)
86#define SN_ML_TX_MODE_REG 0x96
87#define ML_TX_MAIN_LINK_OFF 0
88#define ML_TX_NORMAL_MODE BIT(0)
89#define SN_AUX_CMD_STATUS_REG 0xF4
90#define AUX_IRQ_STATUS_AUX_RPLY_TOUT BIT(3)
91#define AUX_IRQ_STATUS_AUX_SHORT BIT(5)
92#define AUX_IRQ_STATUS_NAT_I2C_FAIL BIT(6)
93
94#define MIN_DSI_CLK_FREQ_MHZ 40
95
96/* fudge factor required to account for 8b/10b encoding */
97#define DP_CLK_FUDGE_NUM 10
98#define DP_CLK_FUDGE_DEN 8
99
100/* Matches DP_AUX_MAX_PAYLOAD_BYTES (for now) */
101#define SN_AUX_MAX_PAYLOAD_BYTES 16
102
103#define SN_REGULATOR_SUPPLY_NUM 4
104
105#define SN_MAX_DP_LANES 4
106#define SN_NUM_GPIOS 4
107#define SN_GPIO_PHYSICAL_OFFSET 1
108
109/**
110 * struct ti_sn_bridge - Platform data for ti-sn65dsi86 driver.
111 * @dev: Pointer to our device.
112 * @regmap: Regmap for accessing i2c.
113 * @aux: Our aux channel.
114 * @bridge: Our bridge.
115 * @connector: Our connector.
116 * @debugfs: Used for managing our debugfs.
117 * @host_node: Remote DSI node.
118 * @dsi: Our MIPI DSI source.
119 * @refclk: Our reference clock.
120 * @panel: Our panel.
121 * @enable_gpio: The GPIO we toggle to enable the bridge.
122 * @supplies: Data for bulk enabling/disabling our regulators.
123 * @dp_lanes: Count of dp_lanes we're using.
124 * @ln_assign: Value to program to the LN_ASSIGN register.
125 * @ln_polrs: Value for the 4-bit LN_POLRS field of SN_ENH_FRAME_REG.
126 *
127 * @gchip: If we expose our GPIOs, this is used.
128 * @gchip_output: A cache of whether we've set GPIOs to output. This
129 * serves double-duty of keeping track of the direction and
130 * also keeping track of whether we've incremented the
131 * pm_runtime reference count for this pin, which we do
132 * whenever a pin is configured as an output. This is a
133 * bitmap so we can do atomic ops on it without an extra
134 * lock so concurrent users of our 4 GPIOs don't stomp on
135 * each other's read-modify-write.
136 */
137struct ti_sn_bridge {
138 struct device *dev;
139 struct regmap *regmap;
140 struct drm_dp_aux aux;
141 struct drm_bridge bridge;
142 struct drm_connector connector;
143 struct dentry *debugfs;
144 struct device_node *host_node;
145 struct mipi_dsi_device *dsi;
146 struct clk *refclk;
147 struct drm_panel *panel;
148 struct gpio_desc *enable_gpio;
149 struct regulator_bulk_data supplies[SN_REGULATOR_SUPPLY_NUM];
150 int dp_lanes;
151 u8 ln_assign;
152 u8 ln_polrs;
153
154#if defined(CONFIG_OF_GPIO)
155 struct gpio_chip gchip;
156 DECLARE_BITMAP(gchip_output, SN_NUM_GPIOS);
157#endif
158};
159
160static const struct regmap_range ti_sn_bridge_volatile_ranges[] = {
161 { .range_min = 0, .range_max = 0xFF },
162};
163
164static const struct regmap_access_table ti_sn_bridge_volatile_table = {
165 .yes_ranges = ti_sn_bridge_volatile_ranges,
166 .n_yes_ranges = ARRAY_SIZE(ti_sn_bridge_volatile_ranges),
167};
168
169static const struct regmap_config ti_sn_bridge_regmap_config = {
170 .reg_bits = 8,
171 .val_bits = 8,
172 .volatile_table = &ti_sn_bridge_volatile_table,
173 .cache_type = REGCACHE_NONE,
174};
175
176static void ti_sn_bridge_write_u16(struct ti_sn_bridge *pdata,
177 unsigned int reg, u16 val)
178{
179 regmap_write(pdata->regmap, reg, val & 0xFF);
180 regmap_write(pdata->regmap, reg + 1, val >> 8);
181}
182
183static int __maybe_unused ti_sn_bridge_resume(struct device *dev)
184{
185 struct ti_sn_bridge *pdata = dev_get_drvdata(dev);
186 int ret;
187
188 ret = regulator_bulk_enable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies);
189 if (ret) {
190 DRM_ERROR("failed to enable supplies %d\n", ret);
191 return ret;
192 }
193
194 gpiod_set_value(pdata->enable_gpio, 1);
195
196 return ret;
197}
198
199static int __maybe_unused ti_sn_bridge_suspend(struct device *dev)
200{
201 struct ti_sn_bridge *pdata = dev_get_drvdata(dev);
202 int ret;
203
204 gpiod_set_value(pdata->enable_gpio, 0);
205
206 ret = regulator_bulk_disable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies);
207 if (ret)
208 DRM_ERROR("failed to disable supplies %d\n", ret);
209
210 return ret;
211}
212
213static const struct dev_pm_ops ti_sn_bridge_pm_ops = {
214 SET_RUNTIME_PM_OPS(ti_sn_bridge_suspend, ti_sn_bridge_resume, NULL)
215 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
216 pm_runtime_force_resume)
217};
218
219static int status_show(struct seq_file *s, void *data)
220{
221 struct ti_sn_bridge *pdata = s->private;
222 unsigned int reg, val;
223
224 seq_puts(s, "STATUS REGISTERS:\n");
225
226 pm_runtime_get_sync(pdata->dev);
227
228 /* IRQ Status Registers, see Table 31 in datasheet */
229 for (reg = 0xf0; reg <= 0xf8; reg++) {
230 regmap_read(pdata->regmap, reg, &val);
231 seq_printf(s, "[0x%02x] = 0x%08x\n", reg, val);
232 }
233
234 pm_runtime_put(pdata->dev);
235
236 return 0;
237}
238
239DEFINE_SHOW_ATTRIBUTE(status);
240
241static void ti_sn_debugfs_init(struct ti_sn_bridge *pdata)
242{
243 pdata->debugfs = debugfs_create_dir(dev_name(pdata->dev), NULL);
244
245 debugfs_create_file("status", 0600, pdata->debugfs, pdata,
246 &status_fops);
247}
248
249static void ti_sn_debugfs_remove(struct ti_sn_bridge *pdata)
250{
251 debugfs_remove_recursive(pdata->debugfs);
252 pdata->debugfs = NULL;
253}
254
255/* Connector funcs */
256static struct ti_sn_bridge *
257connector_to_ti_sn_bridge(struct drm_connector *connector)
258{
259 return container_of(connector, struct ti_sn_bridge, connector);
260}
261
262static int ti_sn_bridge_connector_get_modes(struct drm_connector *connector)
263{
264 struct ti_sn_bridge *pdata = connector_to_ti_sn_bridge(connector);
265
266 return drm_panel_get_modes(pdata->panel, connector);
267}
268
269static enum drm_mode_status
270ti_sn_bridge_connector_mode_valid(struct drm_connector *connector,
271 struct drm_display_mode *mode)
272{
273 /* maximum supported resolution is 4K at 60 fps */
274 if (mode->clock > 594000)
275 return MODE_CLOCK_HIGH;
276
277 return MODE_OK;
278}
279
280static struct drm_connector_helper_funcs ti_sn_bridge_connector_helper_funcs = {
281 .get_modes = ti_sn_bridge_connector_get_modes,
282 .mode_valid = ti_sn_bridge_connector_mode_valid,
283};
284
285static enum drm_connector_status
286ti_sn_bridge_connector_detect(struct drm_connector *connector, bool force)
287{
288 /**
289 * TODO: Currently if drm_panel is present, then always
290 * return the status as connected. Need to add support to detect
291 * device state for hot pluggable scenarios.
292 */
293 return connector_status_connected;
294}
295
296static const struct drm_connector_funcs ti_sn_bridge_connector_funcs = {
297 .fill_modes = drm_helper_probe_single_connector_modes,
298 .detect = ti_sn_bridge_connector_detect,
299 .destroy = drm_connector_cleanup,
300 .reset = drm_atomic_helper_connector_reset,
301 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
302 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
303};
304
305static struct ti_sn_bridge *bridge_to_ti_sn_bridge(struct drm_bridge *bridge)
306{
307 return container_of(bridge, struct ti_sn_bridge, bridge);
308}
309
310static int ti_sn_bridge_parse_regulators(struct ti_sn_bridge *pdata)
311{
312 unsigned int i;
313 const char * const ti_sn_bridge_supply_names[] = {
314 "vcca", "vcc", "vccio", "vpll",
315 };
316
317 for (i = 0; i < SN_REGULATOR_SUPPLY_NUM; i++)
318 pdata->supplies[i].supply = ti_sn_bridge_supply_names[i];
319
320 return devm_regulator_bulk_get(pdata->dev, SN_REGULATOR_SUPPLY_NUM,
321 pdata->supplies);
322}
323
324static int ti_sn_bridge_attach(struct drm_bridge *bridge,
325 enum drm_bridge_attach_flags flags)
326{
327 int ret, val;
328 struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
329 struct mipi_dsi_host *host;
330 struct mipi_dsi_device *dsi;
331 const struct mipi_dsi_device_info info = { .type = "ti_sn_bridge",
332 .channel = 0,
333 .node = NULL,
334 };
335
336 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) {
337 DRM_ERROR("Fix bridge driver to make connector optional!");
338 return -EINVAL;
339 }
340
341 ret = drm_connector_init(bridge->dev, &pdata->connector,
342 &ti_sn_bridge_connector_funcs,
343 DRM_MODE_CONNECTOR_eDP);
344 if (ret) {
345 DRM_ERROR("Failed to initialize connector with drm\n");
346 return ret;
347 }
348
349 drm_connector_helper_add(&pdata->connector,
350 &ti_sn_bridge_connector_helper_funcs);
351 drm_connector_attach_encoder(&pdata->connector, bridge->encoder);
352
353 /*
354 * TODO: ideally finding host resource and dsi dev registration needs
355 * to be done in bridge probe. But some existing DSI host drivers will
356 * wait for any of the drm_bridge/drm_panel to get added to the global
357 * bridge/panel list, before completing their probe. So if we do the
358 * dsi dev registration part in bridge probe, before populating in
359 * the global bridge list, then it will cause deadlock as dsi host probe
360 * will never complete, neither our bridge probe. So keeping it here
361 * will satisfy most of the existing host drivers. Once the host driver
362 * is fixed we can move the below code to bridge probe safely.
363 */
364 host = of_find_mipi_dsi_host_by_node(pdata->host_node);
365 if (!host) {
366 DRM_ERROR("failed to find dsi host\n");
367 ret = -ENODEV;
368 goto err_dsi_host;
369 }
370
371 dsi = mipi_dsi_device_register_full(host, &info);
372 if (IS_ERR(dsi)) {
373 DRM_ERROR("failed to create dsi device\n");
374 ret = PTR_ERR(dsi);
375 goto err_dsi_host;
376 }
377
378 /* TODO: setting to 4 MIPI lanes always for now */
379 dsi->lanes = 4;
380 dsi->format = MIPI_DSI_FMT_RGB888;
381 dsi->mode_flags = MIPI_DSI_MODE_VIDEO;
382
383 /* check if continuous dsi clock is required or not */
384 pm_runtime_get_sync(pdata->dev);
385 regmap_read(pdata->regmap, SN_DPPLL_SRC_REG, &val);
386 pm_runtime_put(pdata->dev);
387 if (!(val & DPPLL_CLK_SRC_DSICLK))
388 dsi->mode_flags |= MIPI_DSI_CLOCK_NON_CONTINUOUS;
389
390 ret = mipi_dsi_attach(dsi);
391 if (ret < 0) {
392 DRM_ERROR("failed to attach dsi to host\n");
393 goto err_dsi_attach;
394 }
395 pdata->dsi = dsi;
396
397 /* attach panel to bridge */
398 drm_panel_attach(pdata->panel, &pdata->connector);
399
400 return 0;
401
402err_dsi_attach:
403 mipi_dsi_device_unregister(dsi);
404err_dsi_host:
405 drm_connector_cleanup(&pdata->connector);
406 return ret;
407}
408
409static void ti_sn_bridge_disable(struct drm_bridge *bridge)
410{
411 struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
412
413 drm_panel_disable(pdata->panel);
414
415 /* disable video stream */
416 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE, 0);
417 /* semi auto link training mode OFF */
418 regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0);
419 /* disable DP PLL */
420 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0);
421
422 drm_panel_unprepare(pdata->panel);
423}
424
425static u32 ti_sn_bridge_get_dsi_freq(struct ti_sn_bridge *pdata)
426{
427 u32 bit_rate_khz, clk_freq_khz;
428 struct drm_display_mode *mode =
429 &pdata->bridge.encoder->crtc->state->adjusted_mode;
430
431 bit_rate_khz = mode->clock *
432 mipi_dsi_pixel_format_to_bpp(pdata->dsi->format);
433 clk_freq_khz = bit_rate_khz / (pdata->dsi->lanes * 2);
434
435 return clk_freq_khz;
436}
437
438/* clk frequencies supported by bridge in Hz in case derived from REFCLK pin */
439static const u32 ti_sn_bridge_refclk_lut[] = {
440 12000000,
441 19200000,
442 26000000,
443 27000000,
444 38400000,
445};
446
447/* clk frequencies supported by bridge in Hz in case derived from DACP/N pin */
448static const u32 ti_sn_bridge_dsiclk_lut[] = {
449 468000000,
450 384000000,
451 416000000,
452 486000000,
453 460800000,
454};
455
456static void ti_sn_bridge_set_refclk_freq(struct ti_sn_bridge *pdata)
457{
458 int i;
459 u32 refclk_rate;
460 const u32 *refclk_lut;
461 size_t refclk_lut_size;
462
463 if (pdata->refclk) {
464 refclk_rate = clk_get_rate(pdata->refclk);
465 refclk_lut = ti_sn_bridge_refclk_lut;
466 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_refclk_lut);
467 clk_prepare_enable(pdata->refclk);
468 } else {
469 refclk_rate = ti_sn_bridge_get_dsi_freq(pdata) * 1000;
470 refclk_lut = ti_sn_bridge_dsiclk_lut;
471 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_dsiclk_lut);
472 }
473
474 /* for i equals to refclk_lut_size means default frequency */
475 for (i = 0; i < refclk_lut_size; i++)
476 if (refclk_lut[i] == refclk_rate)
477 break;
478
479 regmap_update_bits(pdata->regmap, SN_DPPLL_SRC_REG, REFCLK_FREQ_MASK,
480 REFCLK_FREQ(i));
481}
482
483static void ti_sn_bridge_set_dsi_rate(struct ti_sn_bridge *pdata)
484{
485 unsigned int bit_rate_mhz, clk_freq_mhz;
486 unsigned int val;
487 struct drm_display_mode *mode =
488 &pdata->bridge.encoder->crtc->state->adjusted_mode;
489
490 /* set DSIA clk frequency */
491 bit_rate_mhz = (mode->clock / 1000) *
492 mipi_dsi_pixel_format_to_bpp(pdata->dsi->format);
493 clk_freq_mhz = bit_rate_mhz / (pdata->dsi->lanes * 2);
494
495 /* for each increment in val, frequency increases by 5MHz */
496 val = (MIN_DSI_CLK_FREQ_MHZ / 5) +
497 (((clk_freq_mhz - MIN_DSI_CLK_FREQ_MHZ) / 5) & 0xFF);
498 regmap_write(pdata->regmap, SN_DSIA_CLK_FREQ_REG, val);
499}
500
501static unsigned int ti_sn_bridge_get_bpp(struct ti_sn_bridge *pdata)
502{
503 if (pdata->connector.display_info.bpc <= 6)
504 return 18;
505 else
506 return 24;
507}
508
509/*
510 * LUT index corresponds to register value and
511 * LUT values corresponds to dp data rate supported
512 * by the bridge in Mbps unit.
513 */
514static const unsigned int ti_sn_bridge_dp_rate_lut[] = {
515 0, 1620, 2160, 2430, 2700, 3240, 4320, 5400
516};
517
518static int ti_sn_bridge_calc_min_dp_rate_idx(struct ti_sn_bridge *pdata)
519{
520 unsigned int bit_rate_khz, dp_rate_mhz;
521 unsigned int i;
522 struct drm_display_mode *mode =
523 &pdata->bridge.encoder->crtc->state->adjusted_mode;
524
525 /* Calculate minimum bit rate based on our pixel clock. */
526 bit_rate_khz = mode->clock * ti_sn_bridge_get_bpp(pdata);
527
528 /* Calculate minimum DP data rate, taking 80% as per DP spec */
529 dp_rate_mhz = DIV_ROUND_UP(bit_rate_khz * DP_CLK_FUDGE_NUM,
530 1000 * pdata->dp_lanes * DP_CLK_FUDGE_DEN);
531
532 for (i = 1; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut) - 1; i++)
533 if (ti_sn_bridge_dp_rate_lut[i] >= dp_rate_mhz)
534 break;
535
536 return i;
537}
538
539static void ti_sn_bridge_read_valid_rates(struct ti_sn_bridge *pdata,
540 bool rate_valid[])
541{
542 unsigned int rate_per_200khz;
543 unsigned int rate_mhz;
544 u8 dpcd_val;
545 int ret;
546 int i, j;
547
548 ret = drm_dp_dpcd_readb(&pdata->aux, DP_EDP_DPCD_REV, &dpcd_val);
549 if (ret != 1) {
550 DRM_DEV_ERROR(pdata->dev,
551 "Can't read eDP rev (%d), assuming 1.1\n", ret);
552 dpcd_val = DP_EDP_11;
553 }
554
555 if (dpcd_val >= DP_EDP_14) {
556 /* eDP 1.4 devices must provide a custom table */
557 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
558
559 ret = drm_dp_dpcd_read(&pdata->aux, DP_SUPPORTED_LINK_RATES,
560 sink_rates, sizeof(sink_rates));
561
562 if (ret != sizeof(sink_rates)) {
563 DRM_DEV_ERROR(pdata->dev,
564 "Can't read supported rate table (%d)\n", ret);
565
566 /* By zeroing we'll fall back to DP_MAX_LINK_RATE. */
567 memset(sink_rates, 0, sizeof(sink_rates));
568 }
569
570 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
571 rate_per_200khz = le16_to_cpu(sink_rates[i]);
572
573 if (!rate_per_200khz)
574 break;
575
576 rate_mhz = rate_per_200khz * 200 / 1000;
577 for (j = 0;
578 j < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut);
579 j++) {
580 if (ti_sn_bridge_dp_rate_lut[j] == rate_mhz)
581 rate_valid[j] = true;
582 }
583 }
584
585 for (i = 0; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut); i++) {
586 if (rate_valid[i])
587 return;
588 }
589 DRM_DEV_ERROR(pdata->dev,
590 "No matching eDP rates in table; falling back\n");
591 }
592
593 /* On older versions best we can do is use DP_MAX_LINK_RATE */
594 ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LINK_RATE, &dpcd_val);
595 if (ret != 1) {
596 DRM_DEV_ERROR(pdata->dev,
597 "Can't read max rate (%d); assuming 5.4 GHz\n",
598 ret);
599 dpcd_val = DP_LINK_BW_5_4;
600 }
601
602 switch (dpcd_val) {
603 default:
604 DRM_DEV_ERROR(pdata->dev,
605 "Unexpected max rate (%#x); assuming 5.4 GHz\n",
606 (int)dpcd_val);
607 fallthrough;
608 case DP_LINK_BW_5_4:
609 rate_valid[7] = 1;
610 fallthrough;
611 case DP_LINK_BW_2_7:
612 rate_valid[4] = 1;
613 fallthrough;
614 case DP_LINK_BW_1_62:
615 rate_valid[1] = 1;
616 break;
617 }
618}
619
620static void ti_sn_bridge_set_video_timings(struct ti_sn_bridge *pdata)
621{
622 struct drm_display_mode *mode =
623 &pdata->bridge.encoder->crtc->state->adjusted_mode;
624 u8 hsync_polarity = 0, vsync_polarity = 0;
625
626 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
627 hsync_polarity = CHA_HSYNC_POLARITY;
628 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
629 vsync_polarity = CHA_VSYNC_POLARITY;
630
631 ti_sn_bridge_write_u16(pdata, SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG,
632 mode->hdisplay);
633 ti_sn_bridge_write_u16(pdata, SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG,
634 mode->vdisplay);
635 regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG,
636 (mode->hsync_end - mode->hsync_start) & 0xFF);
637 regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG,
638 (((mode->hsync_end - mode->hsync_start) >> 8) & 0x7F) |
639 hsync_polarity);
640 regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG,
641 (mode->vsync_end - mode->vsync_start) & 0xFF);
642 regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG,
643 (((mode->vsync_end - mode->vsync_start) >> 8) & 0x7F) |
644 vsync_polarity);
645
646 regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_BACK_PORCH_REG,
647 (mode->htotal - mode->hsync_end) & 0xFF);
648 regmap_write(pdata->regmap, SN_CHA_VERTICAL_BACK_PORCH_REG,
649 (mode->vtotal - mode->vsync_end) & 0xFF);
650
651 regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_FRONT_PORCH_REG,
652 (mode->hsync_start - mode->hdisplay) & 0xFF);
653 regmap_write(pdata->regmap, SN_CHA_VERTICAL_FRONT_PORCH_REG,
654 (mode->vsync_start - mode->vdisplay) & 0xFF);
655
656 usleep_range(10000, 10500); /* 10ms delay recommended by spec */
657}
658
659static unsigned int ti_sn_get_max_lanes(struct ti_sn_bridge *pdata)
660{
661 u8 data;
662 int ret;
663
664 ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LANE_COUNT, &data);
665 if (ret != 1) {
666 DRM_DEV_ERROR(pdata->dev,
667 "Can't read lane count (%d); assuming 4\n", ret);
668 return 4;
669 }
670
671 return data & DP_LANE_COUNT_MASK;
672}
673
674static int ti_sn_link_training(struct ti_sn_bridge *pdata, int dp_rate_idx,
675 const char **last_err_str)
676{
677 unsigned int val;
678 int ret;
679
680 /* set dp clk frequency value */
681 regmap_update_bits(pdata->regmap, SN_DATARATE_CONFIG_REG,
682 DP_DATARATE_MASK, DP_DATARATE(dp_rate_idx));
683
684 /* enable DP PLL */
685 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 1);
686
687 ret = regmap_read_poll_timeout(pdata->regmap, SN_DPPLL_SRC_REG, val,
688 val & DPPLL_SRC_DP_PLL_LOCK, 1000,
689 50 * 1000);
690 if (ret) {
691 *last_err_str = "DP_PLL_LOCK polling failed";
692 goto exit;
693 }
694
695 /* Semi auto link training mode */
696 regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0x0A);
697 ret = regmap_read_poll_timeout(pdata->regmap, SN_ML_TX_MODE_REG, val,
698 val == ML_TX_MAIN_LINK_OFF ||
699 val == ML_TX_NORMAL_MODE, 1000,
700 500 * 1000);
701 if (ret) {
702 *last_err_str = "Training complete polling failed";
703 } else if (val == ML_TX_MAIN_LINK_OFF) {
704 *last_err_str = "Link training failed, link is off";
705 ret = -EIO;
706 }
707
708exit:
709 /* Disable the PLL if we failed */
710 if (ret)
711 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0);
712
713 return ret;
714}
715
716static void ti_sn_bridge_enable(struct drm_bridge *bridge)
717{
718 struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
719 bool rate_valid[ARRAY_SIZE(ti_sn_bridge_dp_rate_lut)] = { };
720 const char *last_err_str = "No supported DP rate";
721 int dp_rate_idx;
722 unsigned int val;
723 int ret = -EINVAL;
724 int max_dp_lanes;
725
726 max_dp_lanes = ti_sn_get_max_lanes(pdata);
727 pdata->dp_lanes = min(pdata->dp_lanes, max_dp_lanes);
728
729 /* DSI_A lane config */
730 val = CHA_DSI_LANES(SN_MAX_DP_LANES - pdata->dsi->lanes);
731 regmap_update_bits(pdata->regmap, SN_DSI_LANES_REG,
732 CHA_DSI_LANES_MASK, val);
733
734 regmap_write(pdata->regmap, SN_LN_ASSIGN_REG, pdata->ln_assign);
735 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, LN_POLRS_MASK,
736 pdata->ln_polrs << LN_POLRS_OFFSET);
737
738 /* set dsi clk frequency value */
739 ti_sn_bridge_set_dsi_rate(pdata);
740
741 /**
742 * The SN65DSI86 only supports ASSR Display Authentication method and
743 * this method is enabled by default. An eDP panel must support this
744 * authentication method. We need to enable this method in the eDP panel
745 * at DisplayPort address 0x0010A prior to link training.
746 */
747 drm_dp_dpcd_writeb(&pdata->aux, DP_EDP_CONFIGURATION_SET,
748 DP_ALTERNATE_SCRAMBLER_RESET_ENABLE);
749
750 /* Set the DP output format (18 bpp or 24 bpp) */
751 val = (ti_sn_bridge_get_bpp(pdata) == 18) ? BPP_18_RGB : 0;
752 regmap_update_bits(pdata->regmap, SN_DATA_FORMAT_REG, BPP_18_RGB, val);
753
754 /* DP lane config */
755 val = DP_NUM_LANES(min(pdata->dp_lanes, 3));
756 regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK,
757 val);
758
759 ti_sn_bridge_read_valid_rates(pdata, rate_valid);
760
761 /* Train until we run out of rates */
762 for (dp_rate_idx = ti_sn_bridge_calc_min_dp_rate_idx(pdata);
763 dp_rate_idx < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut);
764 dp_rate_idx++) {
765 if (!rate_valid[dp_rate_idx])
766 continue;
767
768 ret = ti_sn_link_training(pdata, dp_rate_idx, &last_err_str);
769 if (!ret)
770 break;
771 }
772 if (ret) {
773 DRM_DEV_ERROR(pdata->dev, "%s (%d)\n", last_err_str, ret);
774 return;
775 }
776
777 /* config video parameters */
778 ti_sn_bridge_set_video_timings(pdata);
779
780 /* enable video stream */
781 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE,
782 VSTREAM_ENABLE);
783
784 drm_panel_enable(pdata->panel);
785}
786
787static void ti_sn_bridge_pre_enable(struct drm_bridge *bridge)
788{
789 struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
790
791 pm_runtime_get_sync(pdata->dev);
792
793 /* configure bridge ref_clk */
794 ti_sn_bridge_set_refclk_freq(pdata);
795
796 /*
797 * HPD on this bridge chip is a bit useless. This is an eDP bridge
798 * so the HPD is an internal signal that's only there to signal that
799 * the panel is done powering up. ...but the bridge chip debounces
800 * this signal by between 100 ms and 400 ms (depending on process,
801 * voltage, and temperate--I measured it at about 200 ms). One
802 * particular panel asserted HPD 84 ms after it was powered on meaning
803 * that we saw HPD 284 ms after power on. ...but the same panel said
804 * that instead of looking at HPD you could just hardcode a delay of
805 * 200 ms. We'll assume that the panel driver will have the hardcoded
806 * delay in its prepare and always disable HPD.
807 *
808 * If HPD somehow makes sense on some future panel we'll have to
809 * change this to be conditional on someone specifying that HPD should
810 * be used.
811 */
812 regmap_update_bits(pdata->regmap, SN_HPD_DISABLE_REG, HPD_DISABLE,
813 HPD_DISABLE);
814
815 drm_panel_prepare(pdata->panel);
816}
817
818static void ti_sn_bridge_post_disable(struct drm_bridge *bridge)
819{
820 struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
821
822 if (pdata->refclk)
823 clk_disable_unprepare(pdata->refclk);
824
825 pm_runtime_put_sync(pdata->dev);
826}
827
828static const struct drm_bridge_funcs ti_sn_bridge_funcs = {
829 .attach = ti_sn_bridge_attach,
830 .pre_enable = ti_sn_bridge_pre_enable,
831 .enable = ti_sn_bridge_enable,
832 .disable = ti_sn_bridge_disable,
833 .post_disable = ti_sn_bridge_post_disable,
834};
835
836static struct ti_sn_bridge *aux_to_ti_sn_bridge(struct drm_dp_aux *aux)
837{
838 return container_of(aux, struct ti_sn_bridge, aux);
839}
840
841static ssize_t ti_sn_aux_transfer(struct drm_dp_aux *aux,
842 struct drm_dp_aux_msg *msg)
843{
844 struct ti_sn_bridge *pdata = aux_to_ti_sn_bridge(aux);
845 u32 request = msg->request & ~DP_AUX_I2C_MOT;
846 u32 request_val = AUX_CMD_REQ(msg->request);
847 u8 *buf = (u8 *)msg->buffer;
848 unsigned int val;
849 int ret, i;
850
851 if (msg->size > SN_AUX_MAX_PAYLOAD_BYTES)
852 return -EINVAL;
853
854 switch (request) {
855 case DP_AUX_NATIVE_WRITE:
856 case DP_AUX_I2C_WRITE:
857 case DP_AUX_NATIVE_READ:
858 case DP_AUX_I2C_READ:
859 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val);
860 break;
861 default:
862 return -EINVAL;
863 }
864
865 regmap_write(pdata->regmap, SN_AUX_ADDR_19_16_REG,
866 (msg->address >> 16) & 0xF);
867 regmap_write(pdata->regmap, SN_AUX_ADDR_15_8_REG,
868 (msg->address >> 8) & 0xFF);
869 regmap_write(pdata->regmap, SN_AUX_ADDR_7_0_REG, msg->address & 0xFF);
870
871 regmap_write(pdata->regmap, SN_AUX_LENGTH_REG, msg->size);
872
873 if (request == DP_AUX_NATIVE_WRITE || request == DP_AUX_I2C_WRITE) {
874 for (i = 0; i < msg->size; i++)
875 regmap_write(pdata->regmap, SN_AUX_WDATA_REG(i),
876 buf[i]);
877 }
878
879 /* Clear old status bits before start so we don't get confused */
880 regmap_write(pdata->regmap, SN_AUX_CMD_STATUS_REG,
881 AUX_IRQ_STATUS_NAT_I2C_FAIL |
882 AUX_IRQ_STATUS_AUX_RPLY_TOUT |
883 AUX_IRQ_STATUS_AUX_SHORT);
884
885 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val | AUX_CMD_SEND);
886
887 ret = regmap_read_poll_timeout(pdata->regmap, SN_AUX_CMD_REG, val,
888 !(val & AUX_CMD_SEND), 200,
889 50 * 1000);
890 if (ret)
891 return ret;
892
893 ret = regmap_read(pdata->regmap, SN_AUX_CMD_STATUS_REG, &val);
894 if (ret)
895 return ret;
896 else if ((val & AUX_IRQ_STATUS_NAT_I2C_FAIL)
897 || (val & AUX_IRQ_STATUS_AUX_RPLY_TOUT)
898 || (val & AUX_IRQ_STATUS_AUX_SHORT))
899 return -ENXIO;
900
901 if (request == DP_AUX_NATIVE_WRITE || request == DP_AUX_I2C_WRITE)
902 return msg->size;
903
904 for (i = 0; i < msg->size; i++) {
905 unsigned int val;
906 ret = regmap_read(pdata->regmap, SN_AUX_RDATA_REG(i),
907 &val);
908 if (ret)
909 return ret;
910
911 WARN_ON(val & ~0xFF);
912 buf[i] = (u8)(val & 0xFF);
913 }
914
915 return msg->size;
916}
917
918static int ti_sn_bridge_parse_dsi_host(struct ti_sn_bridge *pdata)
919{
920 struct device_node *np = pdata->dev->of_node;
921
922 pdata->host_node = of_graph_get_remote_node(np, 0, 0);
923
924 if (!pdata->host_node) {
925 DRM_ERROR("remote dsi host node not found\n");
926 return -ENODEV;
927 }
928
929 return 0;
930}
931
932#if defined(CONFIG_OF_GPIO)
933
934static int tn_sn_bridge_of_xlate(struct gpio_chip *chip,
935 const struct of_phandle_args *gpiospec,
936 u32 *flags)
937{
938 if (WARN_ON(gpiospec->args_count < chip->of_gpio_n_cells))
939 return -EINVAL;
940
941 if (gpiospec->args[0] > chip->ngpio || gpiospec->args[0] < 1)
942 return -EINVAL;
943
944 if (flags)
945 *flags = gpiospec->args[1];
946
947 return gpiospec->args[0] - SN_GPIO_PHYSICAL_OFFSET;
948}
949
950static int ti_sn_bridge_gpio_get_direction(struct gpio_chip *chip,
951 unsigned int offset)
952{
953 struct ti_sn_bridge *pdata = gpiochip_get_data(chip);
954
955 /*
956 * We already have to keep track of the direction because we use
957 * that to figure out whether we've powered the device. We can
958 * just return that rather than (maybe) powering up the device
959 * to ask its direction.
960 */
961 return test_bit(offset, pdata->gchip_output) ?
962 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
963}
964
965static int ti_sn_bridge_gpio_get(struct gpio_chip *chip, unsigned int offset)
966{
967 struct ti_sn_bridge *pdata = gpiochip_get_data(chip);
968 unsigned int val;
969 int ret;
970
971 /*
972 * When the pin is an input we don't forcibly keep the bridge
973 * powered--we just power it on to read the pin. NOTE: part of
974 * the reason this works is that the bridge defaults (when
975 * powered back on) to all 4 GPIOs being configured as GPIO input.
976 * Also note that if something else is keeping the chip powered the
977 * pm_runtime functions are lightweight increments of a refcount.
978 */
979 pm_runtime_get_sync(pdata->dev);
980 ret = regmap_read(pdata->regmap, SN_GPIO_IO_REG, &val);
981 pm_runtime_put(pdata->dev);
982
983 if (ret)
984 return ret;
985
986 return !!(val & BIT(SN_GPIO_INPUT_SHIFT + offset));
987}
988
989static void ti_sn_bridge_gpio_set(struct gpio_chip *chip, unsigned int offset,
990 int val)
991{
992 struct ti_sn_bridge *pdata = gpiochip_get_data(chip);
993 int ret;
994
995 if (!test_bit(offset, pdata->gchip_output)) {
996 dev_err(pdata->dev, "Ignoring GPIO set while input\n");
997 return;
998 }
999
1000 val &= 1;
1001 ret = regmap_update_bits(pdata->regmap, SN_GPIO_IO_REG,
1002 BIT(SN_GPIO_OUTPUT_SHIFT + offset),
1003 val << (SN_GPIO_OUTPUT_SHIFT + offset));
1004 if (ret)
1005 dev_warn(pdata->dev,
1006 "Failed to set bridge GPIO %u: %d\n", offset, ret);
1007}
1008
1009static int ti_sn_bridge_gpio_direction_input(struct gpio_chip *chip,
1010 unsigned int offset)
1011{
1012 struct ti_sn_bridge *pdata = gpiochip_get_data(chip);
1013 int shift = offset * 2;
1014 int ret;
1015
1016 if (!test_and_clear_bit(offset, pdata->gchip_output))
1017 return 0;
1018
1019 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG,
1020 SN_GPIO_MUX_MASK << shift,
1021 SN_GPIO_MUX_INPUT << shift);
1022 if (ret) {
1023 set_bit(offset, pdata->gchip_output);
1024 return ret;
1025 }
1026
1027 /*
1028 * NOTE: if nobody else is powering the device this may fully power
1029 * it off and when it comes back it will have lost all state, but
1030 * that's OK because the default is input and we're now an input.
1031 */
1032 pm_runtime_put(pdata->dev);
1033
1034 return 0;
1035}
1036
1037static int ti_sn_bridge_gpio_direction_output(struct gpio_chip *chip,
1038 unsigned int offset, int val)
1039{
1040 struct ti_sn_bridge *pdata = gpiochip_get_data(chip);
1041 int shift = offset * 2;
1042 int ret;
1043
1044 if (test_and_set_bit(offset, pdata->gchip_output))
1045 return 0;
1046
1047 pm_runtime_get_sync(pdata->dev);
1048
1049 /* Set value first to avoid glitching */
1050 ti_sn_bridge_gpio_set(chip, offset, val);
1051
1052 /* Set direction */
1053 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG,
1054 SN_GPIO_MUX_MASK << shift,
1055 SN_GPIO_MUX_OUTPUT << shift);
1056 if (ret) {
1057 clear_bit(offset, pdata->gchip_output);
1058 pm_runtime_put(pdata->dev);
1059 }
1060
1061 return ret;
1062}
1063
1064static void ti_sn_bridge_gpio_free(struct gpio_chip *chip, unsigned int offset)
1065{
1066 /* We won't keep pm_runtime if we're input, so switch there on free */
1067 ti_sn_bridge_gpio_direction_input(chip, offset);
1068}
1069
1070static const char * const ti_sn_bridge_gpio_names[SN_NUM_GPIOS] = {
1071 "GPIO1", "GPIO2", "GPIO3", "GPIO4"
1072};
1073
1074static int ti_sn_setup_gpio_controller(struct ti_sn_bridge *pdata)
1075{
1076 int ret;
1077
1078 /* Only init if someone is going to use us as a GPIO controller */
1079 if (!of_property_read_bool(pdata->dev->of_node, "gpio-controller"))
1080 return 0;
1081
1082 pdata->gchip.label = dev_name(pdata->dev);
1083 pdata->gchip.parent = pdata->dev;
1084 pdata->gchip.owner = THIS_MODULE;
1085 pdata->gchip.of_xlate = tn_sn_bridge_of_xlate;
1086 pdata->gchip.of_gpio_n_cells = 2;
1087 pdata->gchip.free = ti_sn_bridge_gpio_free;
1088 pdata->gchip.get_direction = ti_sn_bridge_gpio_get_direction;
1089 pdata->gchip.direction_input = ti_sn_bridge_gpio_direction_input;
1090 pdata->gchip.direction_output = ti_sn_bridge_gpio_direction_output;
1091 pdata->gchip.get = ti_sn_bridge_gpio_get;
1092 pdata->gchip.set = ti_sn_bridge_gpio_set;
1093 pdata->gchip.can_sleep = true;
1094 pdata->gchip.names = ti_sn_bridge_gpio_names;
1095 pdata->gchip.ngpio = SN_NUM_GPIOS;
1096 pdata->gchip.base = -1;
1097 ret = devm_gpiochip_add_data(pdata->dev, &pdata->gchip, pdata);
1098 if (ret)
1099 dev_err(pdata->dev, "can't add gpio chip\n");
1100
1101 return ret;
1102}
1103
1104#else
1105
1106static inline int ti_sn_setup_gpio_controller(struct ti_sn_bridge *pdata)
1107{
1108 return 0;
1109}
1110
1111#endif
1112
1113static void ti_sn_bridge_parse_lanes(struct ti_sn_bridge *pdata,
1114 struct device_node *np)
1115{
1116 u32 lane_assignments[SN_MAX_DP_LANES] = { 0, 1, 2, 3 };
1117 u32 lane_polarities[SN_MAX_DP_LANES] = { };
1118 struct device_node *endpoint;
1119 u8 ln_assign = 0;
1120 u8 ln_polrs = 0;
1121 int dp_lanes;
1122 int i;
1123
1124 /*
1125 * Read config from the device tree about lane remapping and lane
1126 * polarities. These are optional and we assume identity map and
1127 * normal polarity if nothing is specified. It's OK to specify just
1128 * data-lanes but not lane-polarities but not vice versa.
1129 *
1130 * Error checking is light (we just make sure we don't crash or
1131 * buffer overrun) and we assume dts is well formed and specifying
1132 * mappings that the hardware supports.
1133 */
1134 endpoint = of_graph_get_endpoint_by_regs(np, 1, -1);
1135 dp_lanes = of_property_count_u32_elems(endpoint, "data-lanes");
1136 if (dp_lanes > 0 && dp_lanes <= SN_MAX_DP_LANES) {
1137 of_property_read_u32_array(endpoint, "data-lanes",
1138 lane_assignments, dp_lanes);
1139 of_property_read_u32_array(endpoint, "lane-polarities",
1140 lane_polarities, dp_lanes);
1141 } else {
1142 dp_lanes = SN_MAX_DP_LANES;
1143 }
1144 of_node_put(endpoint);
1145
1146 /*
1147 * Convert into register format. Loop over all lanes even if
1148 * data-lanes had fewer elements so that we nicely initialize
1149 * the LN_ASSIGN register.
1150 */
1151 for (i = SN_MAX_DP_LANES - 1; i >= 0; i--) {
1152 ln_assign = ln_assign << LN_ASSIGN_WIDTH | lane_assignments[i];
1153 ln_polrs = ln_polrs << 1 | lane_polarities[i];
1154 }
1155
1156 /* Stash in our struct for when we power on */
1157 pdata->dp_lanes = dp_lanes;
1158 pdata->ln_assign = ln_assign;
1159 pdata->ln_polrs = ln_polrs;
1160}
1161
1162static int ti_sn_bridge_probe(struct i2c_client *client,
1163 const struct i2c_device_id *id)
1164{
1165 struct ti_sn_bridge *pdata;
1166 int ret;
1167
1168 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
1169 DRM_ERROR("device doesn't support I2C\n");
1170 return -ENODEV;
1171 }
1172
1173 pdata = devm_kzalloc(&client->dev, sizeof(struct ti_sn_bridge),
1174 GFP_KERNEL);
1175 if (!pdata)
1176 return -ENOMEM;
1177
1178 pdata->regmap = devm_regmap_init_i2c(client,
1179 &ti_sn_bridge_regmap_config);
1180 if (IS_ERR(pdata->regmap)) {
1181 DRM_ERROR("regmap i2c init failed\n");
1182 return PTR_ERR(pdata->regmap);
1183 }
1184
1185 pdata->dev = &client->dev;
1186
1187 ret = drm_of_find_panel_or_bridge(pdata->dev->of_node, 1, 0,
1188 &pdata->panel, NULL);
1189 if (ret) {
1190 DRM_ERROR("could not find any panel node\n");
1191 return ret;
1192 }
1193
1194 dev_set_drvdata(&client->dev, pdata);
1195
1196 pdata->enable_gpio = devm_gpiod_get(pdata->dev, "enable",
1197 GPIOD_OUT_LOW);
1198 if (IS_ERR(pdata->enable_gpio)) {
1199 DRM_ERROR("failed to get enable gpio from DT\n");
1200 ret = PTR_ERR(pdata->enable_gpio);
1201 return ret;
1202 }
1203
1204 ti_sn_bridge_parse_lanes(pdata, client->dev.of_node);
1205
1206 ret = ti_sn_bridge_parse_regulators(pdata);
1207 if (ret) {
1208 DRM_ERROR("failed to parse regulators\n");
1209 return ret;
1210 }
1211
1212 pdata->refclk = devm_clk_get(pdata->dev, "refclk");
1213 if (IS_ERR(pdata->refclk)) {
1214 ret = PTR_ERR(pdata->refclk);
1215 if (ret == -EPROBE_DEFER)
1216 return ret;
1217 DRM_DEBUG_KMS("refclk not found\n");
1218 pdata->refclk = NULL;
1219 }
1220
1221 ret = ti_sn_bridge_parse_dsi_host(pdata);
1222 if (ret)
1223 return ret;
1224
1225 pm_runtime_enable(pdata->dev);
1226
1227 ret = ti_sn_setup_gpio_controller(pdata);
1228 if (ret) {
1229 pm_runtime_disable(pdata->dev);
1230 return ret;
1231 }
1232
1233 i2c_set_clientdata(client, pdata);
1234
1235 pdata->aux.name = "ti-sn65dsi86-aux";
1236 pdata->aux.dev = pdata->dev;
1237 pdata->aux.transfer = ti_sn_aux_transfer;
1238 drm_dp_aux_register(&pdata->aux);
1239
1240 pdata->bridge.funcs = &ti_sn_bridge_funcs;
1241 pdata->bridge.of_node = client->dev.of_node;
1242
1243 drm_bridge_add(&pdata->bridge);
1244
1245 ti_sn_debugfs_init(pdata);
1246
1247 return 0;
1248}
1249
1250static int ti_sn_bridge_remove(struct i2c_client *client)
1251{
1252 struct ti_sn_bridge *pdata = i2c_get_clientdata(client);
1253
1254 if (!pdata)
1255 return -EINVAL;
1256
1257 ti_sn_debugfs_remove(pdata);
1258
1259 of_node_put(pdata->host_node);
1260
1261 pm_runtime_disable(pdata->dev);
1262
1263 if (pdata->dsi) {
1264 mipi_dsi_detach(pdata->dsi);
1265 mipi_dsi_device_unregister(pdata->dsi);
1266 }
1267
1268 drm_bridge_remove(&pdata->bridge);
1269
1270 return 0;
1271}
1272
1273static struct i2c_device_id ti_sn_bridge_id[] = {
1274 { "ti,sn65dsi86", 0},
1275 {},
1276};
1277MODULE_DEVICE_TABLE(i2c, ti_sn_bridge_id);
1278
1279static const struct of_device_id ti_sn_bridge_match_table[] = {
1280 {.compatible = "ti,sn65dsi86"},
1281 {},
1282};
1283MODULE_DEVICE_TABLE(of, ti_sn_bridge_match_table);
1284
1285static struct i2c_driver ti_sn_bridge_driver = {
1286 .driver = {
1287 .name = "ti_sn65dsi86",
1288 .of_match_table = ti_sn_bridge_match_table,
1289 .pm = &ti_sn_bridge_pm_ops,
1290 },
1291 .probe = ti_sn_bridge_probe,
1292 .remove = ti_sn_bridge_remove,
1293 .id_table = ti_sn_bridge_id,
1294};
1295module_i2c_driver(ti_sn_bridge_driver);
1296
1297MODULE_AUTHOR("Sandeep Panda <spanda@codeaurora.org>");
1298MODULE_DESCRIPTION("sn65dsi86 DSI to eDP bridge driver");
1299MODULE_LICENSE("GPL v2");