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1/*
2 * Driver for A2 audio system used in SGI machines
3 * Copyright (c) 2008 Thomas Bogendoerfer <tsbogend@alpha.fanken.de>
4 *
5 * Based on OSS code from Ladislav Michl <ladis@linux-mips.org>, which
6 * was based on code from Ulf Carlsson
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 *
21 */
22#include <linux/kernel.h>
23#include <linux/init.h>
24#include <linux/interrupt.h>
25#include <linux/dma-mapping.h>
26#include <linux/platform_device.h>
27#include <linux/io.h>
28#include <linux/slab.h>
29#include <linux/module.h>
30
31#include <asm/sgi/hpc3.h>
32#include <asm/sgi/ip22.h>
33
34#include <sound/core.h>
35#include <sound/control.h>
36#include <sound/pcm.h>
37#include <sound/pcm-indirect.h>
38#include <sound/initval.h>
39
40#include "hal2.h"
41
42static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */
43static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
44
45module_param(index, int, 0444);
46MODULE_PARM_DESC(index, "Index value for SGI HAL2 soundcard.");
47module_param(id, charp, 0444);
48MODULE_PARM_DESC(id, "ID string for SGI HAL2 soundcard.");
49MODULE_DESCRIPTION("ALSA driver for SGI HAL2 audio");
50MODULE_AUTHOR("Thomas Bogendoerfer");
51MODULE_LICENSE("GPL");
52
53
54#define H2_BLOCK_SIZE 1024
55#define H2_BUF_SIZE 16384
56
57struct hal2_pbus {
58 struct hpc3_pbus_dmacregs *pbus;
59 int pbusnr;
60 unsigned int ctrl; /* Current state of pbus->pbdma_ctrl */
61};
62
63struct hal2_desc {
64 struct hpc_dma_desc desc;
65 u32 pad; /* padding */
66};
67
68struct hal2_codec {
69 struct snd_pcm_indirect pcm_indirect;
70 struct snd_pcm_substream *substream;
71
72 unsigned char *buffer;
73 dma_addr_t buffer_dma;
74 struct hal2_desc *desc;
75 dma_addr_t desc_dma;
76 int desc_count;
77 struct hal2_pbus pbus;
78 int voices; /* mono/stereo */
79 unsigned int sample_rate;
80 unsigned int master; /* Master frequency */
81 unsigned short mod; /* MOD value */
82 unsigned short inc; /* INC value */
83};
84
85#define H2_MIX_OUTPUT_ATT 0
86#define H2_MIX_INPUT_GAIN 1
87
88struct snd_hal2 {
89 struct snd_card *card;
90
91 struct hal2_ctl_regs *ctl_regs; /* HAL2 ctl registers */
92 struct hal2_aes_regs *aes_regs; /* HAL2 aes registers */
93 struct hal2_vol_regs *vol_regs; /* HAL2 vol registers */
94 struct hal2_syn_regs *syn_regs; /* HAL2 syn registers */
95
96 struct hal2_codec dac;
97 struct hal2_codec adc;
98};
99
100#define H2_INDIRECT_WAIT(regs) while (hal2_read(®s->isr) & H2_ISR_TSTATUS);
101
102#define H2_READ_ADDR(addr) (addr | (1<<7))
103#define H2_WRITE_ADDR(addr) (addr)
104
105static inline u32 hal2_read(u32 *reg)
106{
107 return __raw_readl(reg);
108}
109
110static inline void hal2_write(u32 val, u32 *reg)
111{
112 __raw_writel(val, reg);
113}
114
115
116static u32 hal2_i_read32(struct snd_hal2 *hal2, u16 addr)
117{
118 u32 ret;
119 struct hal2_ctl_regs *regs = hal2->ctl_regs;
120
121 hal2_write(H2_READ_ADDR(addr), ®s->iar);
122 H2_INDIRECT_WAIT(regs);
123 ret = hal2_read(®s->idr0) & 0xffff;
124 hal2_write(H2_READ_ADDR(addr) | 0x1, ®s->iar);
125 H2_INDIRECT_WAIT(regs);
126 ret |= (hal2_read(®s->idr0) & 0xffff) << 16;
127 return ret;
128}
129
130static void hal2_i_write16(struct snd_hal2 *hal2, u16 addr, u16 val)
131{
132 struct hal2_ctl_regs *regs = hal2->ctl_regs;
133
134 hal2_write(val, ®s->idr0);
135 hal2_write(0, ®s->idr1);
136 hal2_write(0, ®s->idr2);
137 hal2_write(0, ®s->idr3);
138 hal2_write(H2_WRITE_ADDR(addr), ®s->iar);
139 H2_INDIRECT_WAIT(regs);
140}
141
142static void hal2_i_write32(struct snd_hal2 *hal2, u16 addr, u32 val)
143{
144 struct hal2_ctl_regs *regs = hal2->ctl_regs;
145
146 hal2_write(val & 0xffff, ®s->idr0);
147 hal2_write(val >> 16, ®s->idr1);
148 hal2_write(0, ®s->idr2);
149 hal2_write(0, ®s->idr3);
150 hal2_write(H2_WRITE_ADDR(addr), ®s->iar);
151 H2_INDIRECT_WAIT(regs);
152}
153
154static void hal2_i_setbit16(struct snd_hal2 *hal2, u16 addr, u16 bit)
155{
156 struct hal2_ctl_regs *regs = hal2->ctl_regs;
157
158 hal2_write(H2_READ_ADDR(addr), ®s->iar);
159 H2_INDIRECT_WAIT(regs);
160 hal2_write((hal2_read(®s->idr0) & 0xffff) | bit, ®s->idr0);
161 hal2_write(0, ®s->idr1);
162 hal2_write(0, ®s->idr2);
163 hal2_write(0, ®s->idr3);
164 hal2_write(H2_WRITE_ADDR(addr), ®s->iar);
165 H2_INDIRECT_WAIT(regs);
166}
167
168static void hal2_i_clearbit16(struct snd_hal2 *hal2, u16 addr, u16 bit)
169{
170 struct hal2_ctl_regs *regs = hal2->ctl_regs;
171
172 hal2_write(H2_READ_ADDR(addr), ®s->iar);
173 H2_INDIRECT_WAIT(regs);
174 hal2_write((hal2_read(®s->idr0) & 0xffff) & ~bit, ®s->idr0);
175 hal2_write(0, ®s->idr1);
176 hal2_write(0, ®s->idr2);
177 hal2_write(0, ®s->idr3);
178 hal2_write(H2_WRITE_ADDR(addr), ®s->iar);
179 H2_INDIRECT_WAIT(regs);
180}
181
182static int hal2_gain_info(struct snd_kcontrol *kcontrol,
183 struct snd_ctl_elem_info *uinfo)
184{
185 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
186 uinfo->count = 2;
187 uinfo->value.integer.min = 0;
188 switch ((int)kcontrol->private_value) {
189 case H2_MIX_OUTPUT_ATT:
190 uinfo->value.integer.max = 31;
191 break;
192 case H2_MIX_INPUT_GAIN:
193 uinfo->value.integer.max = 15;
194 break;
195 }
196 return 0;
197}
198
199static int hal2_gain_get(struct snd_kcontrol *kcontrol,
200 struct snd_ctl_elem_value *ucontrol)
201{
202 struct snd_hal2 *hal2 = snd_kcontrol_chip(kcontrol);
203 u32 tmp;
204 int l, r;
205
206 switch ((int)kcontrol->private_value) {
207 case H2_MIX_OUTPUT_ATT:
208 tmp = hal2_i_read32(hal2, H2I_DAC_C2);
209 if (tmp & H2I_C2_MUTE) {
210 l = 0;
211 r = 0;
212 } else {
213 l = 31 - ((tmp >> H2I_C2_L_ATT_SHIFT) & 31);
214 r = 31 - ((tmp >> H2I_C2_R_ATT_SHIFT) & 31);
215 }
216 break;
217 case H2_MIX_INPUT_GAIN:
218 tmp = hal2_i_read32(hal2, H2I_ADC_C2);
219 l = (tmp >> H2I_C2_L_GAIN_SHIFT) & 15;
220 r = (tmp >> H2I_C2_R_GAIN_SHIFT) & 15;
221 break;
222 }
223 ucontrol->value.integer.value[0] = l;
224 ucontrol->value.integer.value[1] = r;
225
226 return 0;
227}
228
229static int hal2_gain_put(struct snd_kcontrol *kcontrol,
230 struct snd_ctl_elem_value *ucontrol)
231{
232 struct snd_hal2 *hal2 = snd_kcontrol_chip(kcontrol);
233 u32 old, new;
234 int l, r;
235
236 l = ucontrol->value.integer.value[0];
237 r = ucontrol->value.integer.value[1];
238
239 switch ((int)kcontrol->private_value) {
240 case H2_MIX_OUTPUT_ATT:
241 old = hal2_i_read32(hal2, H2I_DAC_C2);
242 new = old & ~(H2I_C2_L_ATT_M | H2I_C2_R_ATT_M | H2I_C2_MUTE);
243 if (l | r) {
244 l = 31 - l;
245 r = 31 - r;
246 new |= (l << H2I_C2_L_ATT_SHIFT);
247 new |= (r << H2I_C2_R_ATT_SHIFT);
248 } else
249 new |= H2I_C2_L_ATT_M | H2I_C2_R_ATT_M | H2I_C2_MUTE;
250 hal2_i_write32(hal2, H2I_DAC_C2, new);
251 break;
252 case H2_MIX_INPUT_GAIN:
253 old = hal2_i_read32(hal2, H2I_ADC_C2);
254 new = old & ~(H2I_C2_L_GAIN_M | H2I_C2_R_GAIN_M);
255 new |= (l << H2I_C2_L_GAIN_SHIFT);
256 new |= (r << H2I_C2_R_GAIN_SHIFT);
257 hal2_i_write32(hal2, H2I_ADC_C2, new);
258 break;
259 }
260 return old != new;
261}
262
263static struct snd_kcontrol_new hal2_ctrl_headphone = {
264 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
265 .name = "Headphone Playback Volume",
266 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
267 .private_value = H2_MIX_OUTPUT_ATT,
268 .info = hal2_gain_info,
269 .get = hal2_gain_get,
270 .put = hal2_gain_put,
271};
272
273static struct snd_kcontrol_new hal2_ctrl_mic = {
274 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
275 .name = "Mic Capture Volume",
276 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
277 .private_value = H2_MIX_INPUT_GAIN,
278 .info = hal2_gain_info,
279 .get = hal2_gain_get,
280 .put = hal2_gain_put,
281};
282
283static int hal2_mixer_create(struct snd_hal2 *hal2)
284{
285 int err;
286
287 /* mute DAC */
288 hal2_i_write32(hal2, H2I_DAC_C2,
289 H2I_C2_L_ATT_M | H2I_C2_R_ATT_M | H2I_C2_MUTE);
290 /* mute ADC */
291 hal2_i_write32(hal2, H2I_ADC_C2, 0);
292
293 err = snd_ctl_add(hal2->card,
294 snd_ctl_new1(&hal2_ctrl_headphone, hal2));
295 if (err < 0)
296 return err;
297
298 err = snd_ctl_add(hal2->card,
299 snd_ctl_new1(&hal2_ctrl_mic, hal2));
300 if (err < 0)
301 return err;
302
303 return 0;
304}
305
306static irqreturn_t hal2_interrupt(int irq, void *dev_id)
307{
308 struct snd_hal2 *hal2 = dev_id;
309 irqreturn_t ret = IRQ_NONE;
310
311 /* decide what caused this interrupt */
312 if (hal2->dac.pbus.pbus->pbdma_ctrl & HPC3_PDMACTRL_INT) {
313 snd_pcm_period_elapsed(hal2->dac.substream);
314 ret = IRQ_HANDLED;
315 }
316 if (hal2->adc.pbus.pbus->pbdma_ctrl & HPC3_PDMACTRL_INT) {
317 snd_pcm_period_elapsed(hal2->adc.substream);
318 ret = IRQ_HANDLED;
319 }
320 return ret;
321}
322
323static int hal2_compute_rate(struct hal2_codec *codec, unsigned int rate)
324{
325 unsigned short mod;
326
327 if (44100 % rate < 48000 % rate) {
328 mod = 4 * 44100 / rate;
329 codec->master = 44100;
330 } else {
331 mod = 4 * 48000 / rate;
332 codec->master = 48000;
333 }
334
335 codec->inc = 4;
336 codec->mod = mod;
337 rate = 4 * codec->master / mod;
338
339 return rate;
340}
341
342static void hal2_set_dac_rate(struct snd_hal2 *hal2)
343{
344 unsigned int master = hal2->dac.master;
345 int inc = hal2->dac.inc;
346 int mod = hal2->dac.mod;
347
348 hal2_i_write16(hal2, H2I_BRES1_C1, (master == 44100) ? 1 : 0);
349 hal2_i_write32(hal2, H2I_BRES1_C2,
350 ((0xffff & (inc - mod - 1)) << 16) | inc);
351}
352
353static void hal2_set_adc_rate(struct snd_hal2 *hal2)
354{
355 unsigned int master = hal2->adc.master;
356 int inc = hal2->adc.inc;
357 int mod = hal2->adc.mod;
358
359 hal2_i_write16(hal2, H2I_BRES2_C1, (master == 44100) ? 1 : 0);
360 hal2_i_write32(hal2, H2I_BRES2_C2,
361 ((0xffff & (inc - mod - 1)) << 16) | inc);
362}
363
364static void hal2_setup_dac(struct snd_hal2 *hal2)
365{
366 unsigned int fifobeg, fifoend, highwater, sample_size;
367 struct hal2_pbus *pbus = &hal2->dac.pbus;
368
369 /* Now we set up some PBUS information. The PBUS needs information about
370 * what portion of the fifo it will use. If it's receiving or
371 * transmitting, and finally whether the stream is little endian or big
372 * endian. The information is written later, on the start call.
373 */
374 sample_size = 2 * hal2->dac.voices;
375 /* Fifo should be set to hold exactly four samples. Highwater mark
376 * should be set to two samples. */
377 highwater = (sample_size * 2) >> 1; /* halfwords */
378 fifobeg = 0; /* playback is first */
379 fifoend = (sample_size * 4) >> 3; /* doublewords */
380 pbus->ctrl = HPC3_PDMACTRL_RT | HPC3_PDMACTRL_LD |
381 (highwater << 8) | (fifobeg << 16) | (fifoend << 24);
382 /* We disable everything before we do anything at all */
383 pbus->pbus->pbdma_ctrl = HPC3_PDMACTRL_LD;
384 hal2_i_clearbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECTX);
385 /* Setup the HAL2 for playback */
386 hal2_set_dac_rate(hal2);
387 /* Set endianess */
388 hal2_i_clearbit16(hal2, H2I_DMA_END, H2I_DMA_END_CODECTX);
389 /* Set DMA bus */
390 hal2_i_setbit16(hal2, H2I_DMA_DRV, (1 << pbus->pbusnr));
391 /* We are using 1st Bresenham clock generator for playback */
392 hal2_i_write16(hal2, H2I_DAC_C1, (pbus->pbusnr << H2I_C1_DMA_SHIFT)
393 | (1 << H2I_C1_CLKID_SHIFT)
394 | (hal2->dac.voices << H2I_C1_DATAT_SHIFT));
395}
396
397static void hal2_setup_adc(struct snd_hal2 *hal2)
398{
399 unsigned int fifobeg, fifoend, highwater, sample_size;
400 struct hal2_pbus *pbus = &hal2->adc.pbus;
401
402 sample_size = 2 * hal2->adc.voices;
403 highwater = (sample_size * 2) >> 1; /* halfwords */
404 fifobeg = (4 * 4) >> 3; /* record is second */
405 fifoend = (4 * 4 + sample_size * 4) >> 3; /* doublewords */
406 pbus->ctrl = HPC3_PDMACTRL_RT | HPC3_PDMACTRL_RCV | HPC3_PDMACTRL_LD |
407 (highwater << 8) | (fifobeg << 16) | (fifoend << 24);
408 pbus->pbus->pbdma_ctrl = HPC3_PDMACTRL_LD;
409 hal2_i_clearbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECR);
410 /* Setup the HAL2 for record */
411 hal2_set_adc_rate(hal2);
412 /* Set endianess */
413 hal2_i_clearbit16(hal2, H2I_DMA_END, H2I_DMA_END_CODECR);
414 /* Set DMA bus */
415 hal2_i_setbit16(hal2, H2I_DMA_DRV, (1 << pbus->pbusnr));
416 /* We are using 2nd Bresenham clock generator for record */
417 hal2_i_write16(hal2, H2I_ADC_C1, (pbus->pbusnr << H2I_C1_DMA_SHIFT)
418 | (2 << H2I_C1_CLKID_SHIFT)
419 | (hal2->adc.voices << H2I_C1_DATAT_SHIFT));
420}
421
422static void hal2_start_dac(struct snd_hal2 *hal2)
423{
424 struct hal2_pbus *pbus = &hal2->dac.pbus;
425
426 pbus->pbus->pbdma_dptr = hal2->dac.desc_dma;
427 pbus->pbus->pbdma_ctrl = pbus->ctrl | HPC3_PDMACTRL_ACT;
428 /* enable DAC */
429 hal2_i_setbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECTX);
430}
431
432static void hal2_start_adc(struct snd_hal2 *hal2)
433{
434 struct hal2_pbus *pbus = &hal2->adc.pbus;
435
436 pbus->pbus->pbdma_dptr = hal2->adc.desc_dma;
437 pbus->pbus->pbdma_ctrl = pbus->ctrl | HPC3_PDMACTRL_ACT;
438 /* enable ADC */
439 hal2_i_setbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECR);
440}
441
442static inline void hal2_stop_dac(struct snd_hal2 *hal2)
443{
444 hal2->dac.pbus.pbus->pbdma_ctrl = HPC3_PDMACTRL_LD;
445 /* The HAL2 itself may remain enabled safely */
446}
447
448static inline void hal2_stop_adc(struct snd_hal2 *hal2)
449{
450 hal2->adc.pbus.pbus->pbdma_ctrl = HPC3_PDMACTRL_LD;
451}
452
453static int hal2_alloc_dmabuf(struct hal2_codec *codec)
454{
455 struct hal2_desc *desc;
456 dma_addr_t desc_dma, buffer_dma;
457 int count = H2_BUF_SIZE / H2_BLOCK_SIZE;
458 int i;
459
460 codec->buffer = dma_alloc_noncoherent(NULL, H2_BUF_SIZE,
461 &buffer_dma, GFP_KERNEL);
462 if (!codec->buffer)
463 return -ENOMEM;
464 desc = dma_alloc_noncoherent(NULL, count * sizeof(struct hal2_desc),
465 &desc_dma, GFP_KERNEL);
466 if (!desc) {
467 dma_free_noncoherent(NULL, H2_BUF_SIZE,
468 codec->buffer, buffer_dma);
469 return -ENOMEM;
470 }
471 codec->buffer_dma = buffer_dma;
472 codec->desc_dma = desc_dma;
473 codec->desc = desc;
474 for (i = 0; i < count; i++) {
475 desc->desc.pbuf = buffer_dma + i * H2_BLOCK_SIZE;
476 desc->desc.cntinfo = HPCDMA_XIE | H2_BLOCK_SIZE;
477 desc->desc.pnext = (i == count - 1) ?
478 desc_dma : desc_dma + (i + 1) * sizeof(struct hal2_desc);
479 desc++;
480 }
481 dma_cache_sync(NULL, codec->desc, count * sizeof(struct hal2_desc),
482 DMA_TO_DEVICE);
483 codec->desc_count = count;
484 return 0;
485}
486
487static void hal2_free_dmabuf(struct hal2_codec *codec)
488{
489 dma_free_noncoherent(NULL, codec->desc_count * sizeof(struct hal2_desc),
490 codec->desc, codec->desc_dma);
491 dma_free_noncoherent(NULL, H2_BUF_SIZE, codec->buffer,
492 codec->buffer_dma);
493}
494
495static struct snd_pcm_hardware hal2_pcm_hw = {
496 .info = (SNDRV_PCM_INFO_MMAP |
497 SNDRV_PCM_INFO_MMAP_VALID |
498 SNDRV_PCM_INFO_INTERLEAVED |
499 SNDRV_PCM_INFO_BLOCK_TRANSFER),
500 .formats = SNDRV_PCM_FMTBIT_S16_BE,
501 .rates = SNDRV_PCM_RATE_8000_48000,
502 .rate_min = 8000,
503 .rate_max = 48000,
504 .channels_min = 2,
505 .channels_max = 2,
506 .buffer_bytes_max = 65536,
507 .period_bytes_min = 1024,
508 .period_bytes_max = 65536,
509 .periods_min = 2,
510 .periods_max = 1024,
511};
512
513static int hal2_pcm_hw_params(struct snd_pcm_substream *substream,
514 struct snd_pcm_hw_params *params)
515{
516 int err;
517
518 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params));
519 if (err < 0)
520 return err;
521
522 return 0;
523}
524
525static int hal2_pcm_hw_free(struct snd_pcm_substream *substream)
526{
527 return snd_pcm_lib_free_pages(substream);
528}
529
530static int hal2_playback_open(struct snd_pcm_substream *substream)
531{
532 struct snd_pcm_runtime *runtime = substream->runtime;
533 struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
534 int err;
535
536 runtime->hw = hal2_pcm_hw;
537
538 err = hal2_alloc_dmabuf(&hal2->dac);
539 if (err)
540 return err;
541 return 0;
542}
543
544static int hal2_playback_close(struct snd_pcm_substream *substream)
545{
546 struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
547
548 hal2_free_dmabuf(&hal2->dac);
549 return 0;
550}
551
552static int hal2_playback_prepare(struct snd_pcm_substream *substream)
553{
554 struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
555 struct snd_pcm_runtime *runtime = substream->runtime;
556 struct hal2_codec *dac = &hal2->dac;
557
558 dac->voices = runtime->channels;
559 dac->sample_rate = hal2_compute_rate(dac, runtime->rate);
560 memset(&dac->pcm_indirect, 0, sizeof(dac->pcm_indirect));
561 dac->pcm_indirect.hw_buffer_size = H2_BUF_SIZE;
562 dac->pcm_indirect.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
563 dac->substream = substream;
564 hal2_setup_dac(hal2);
565 return 0;
566}
567
568static int hal2_playback_trigger(struct snd_pcm_substream *substream, int cmd)
569{
570 struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
571
572 switch (cmd) {
573 case SNDRV_PCM_TRIGGER_START:
574 hal2->dac.pcm_indirect.hw_io = hal2->dac.buffer_dma;
575 hal2->dac.pcm_indirect.hw_data = 0;
576 substream->ops->ack(substream);
577 hal2_start_dac(hal2);
578 break;
579 case SNDRV_PCM_TRIGGER_STOP:
580 hal2_stop_dac(hal2);
581 break;
582 default:
583 return -EINVAL;
584 }
585 return 0;
586}
587
588static snd_pcm_uframes_t
589hal2_playback_pointer(struct snd_pcm_substream *substream)
590{
591 struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
592 struct hal2_codec *dac = &hal2->dac;
593
594 return snd_pcm_indirect_playback_pointer(substream, &dac->pcm_indirect,
595 dac->pbus.pbus->pbdma_bptr);
596}
597
598static void hal2_playback_transfer(struct snd_pcm_substream *substream,
599 struct snd_pcm_indirect *rec, size_t bytes)
600{
601 struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
602 unsigned char *buf = hal2->dac.buffer + rec->hw_data;
603
604 memcpy(buf, substream->runtime->dma_area + rec->sw_data, bytes);
605 dma_cache_sync(NULL, buf, bytes, DMA_TO_DEVICE);
606
607}
608
609static int hal2_playback_ack(struct snd_pcm_substream *substream)
610{
611 struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
612 struct hal2_codec *dac = &hal2->dac;
613
614 dac->pcm_indirect.hw_queue_size = H2_BUF_SIZE / 2;
615 snd_pcm_indirect_playback_transfer(substream,
616 &dac->pcm_indirect,
617 hal2_playback_transfer);
618 return 0;
619}
620
621static int hal2_capture_open(struct snd_pcm_substream *substream)
622{
623 struct snd_pcm_runtime *runtime = substream->runtime;
624 struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
625 struct hal2_codec *adc = &hal2->adc;
626 int err;
627
628 runtime->hw = hal2_pcm_hw;
629
630 err = hal2_alloc_dmabuf(adc);
631 if (err)
632 return err;
633 return 0;
634}
635
636static int hal2_capture_close(struct snd_pcm_substream *substream)
637{
638 struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
639
640 hal2_free_dmabuf(&hal2->adc);
641 return 0;
642}
643
644static int hal2_capture_prepare(struct snd_pcm_substream *substream)
645{
646 struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
647 struct snd_pcm_runtime *runtime = substream->runtime;
648 struct hal2_codec *adc = &hal2->adc;
649
650 adc->voices = runtime->channels;
651 adc->sample_rate = hal2_compute_rate(adc, runtime->rate);
652 memset(&adc->pcm_indirect, 0, sizeof(adc->pcm_indirect));
653 adc->pcm_indirect.hw_buffer_size = H2_BUF_SIZE;
654 adc->pcm_indirect.hw_queue_size = H2_BUF_SIZE / 2;
655 adc->pcm_indirect.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
656 adc->substream = substream;
657 hal2_setup_adc(hal2);
658 return 0;
659}
660
661static int hal2_capture_trigger(struct snd_pcm_substream *substream, int cmd)
662{
663 struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
664
665 switch (cmd) {
666 case SNDRV_PCM_TRIGGER_START:
667 hal2->adc.pcm_indirect.hw_io = hal2->adc.buffer_dma;
668 hal2->adc.pcm_indirect.hw_data = 0;
669 printk(KERN_DEBUG "buffer_dma %x\n", hal2->adc.buffer_dma);
670 hal2_start_adc(hal2);
671 break;
672 case SNDRV_PCM_TRIGGER_STOP:
673 hal2_stop_adc(hal2);
674 break;
675 default:
676 return -EINVAL;
677 }
678 return 0;
679}
680
681static snd_pcm_uframes_t
682hal2_capture_pointer(struct snd_pcm_substream *substream)
683{
684 struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
685 struct hal2_codec *adc = &hal2->adc;
686
687 return snd_pcm_indirect_capture_pointer(substream, &adc->pcm_indirect,
688 adc->pbus.pbus->pbdma_bptr);
689}
690
691static void hal2_capture_transfer(struct snd_pcm_substream *substream,
692 struct snd_pcm_indirect *rec, size_t bytes)
693{
694 struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
695 unsigned char *buf = hal2->adc.buffer + rec->hw_data;
696
697 dma_cache_sync(NULL, buf, bytes, DMA_FROM_DEVICE);
698 memcpy(substream->runtime->dma_area + rec->sw_data, buf, bytes);
699}
700
701static int hal2_capture_ack(struct snd_pcm_substream *substream)
702{
703 struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
704 struct hal2_codec *adc = &hal2->adc;
705
706 snd_pcm_indirect_capture_transfer(substream,
707 &adc->pcm_indirect,
708 hal2_capture_transfer);
709 return 0;
710}
711
712static struct snd_pcm_ops hal2_playback_ops = {
713 .open = hal2_playback_open,
714 .close = hal2_playback_close,
715 .ioctl = snd_pcm_lib_ioctl,
716 .hw_params = hal2_pcm_hw_params,
717 .hw_free = hal2_pcm_hw_free,
718 .prepare = hal2_playback_prepare,
719 .trigger = hal2_playback_trigger,
720 .pointer = hal2_playback_pointer,
721 .ack = hal2_playback_ack,
722};
723
724static struct snd_pcm_ops hal2_capture_ops = {
725 .open = hal2_capture_open,
726 .close = hal2_capture_close,
727 .ioctl = snd_pcm_lib_ioctl,
728 .hw_params = hal2_pcm_hw_params,
729 .hw_free = hal2_pcm_hw_free,
730 .prepare = hal2_capture_prepare,
731 .trigger = hal2_capture_trigger,
732 .pointer = hal2_capture_pointer,
733 .ack = hal2_capture_ack,
734};
735
736static int hal2_pcm_create(struct snd_hal2 *hal2)
737{
738 struct snd_pcm *pcm;
739 int err;
740
741 /* create first pcm device with one outputs and one input */
742 err = snd_pcm_new(hal2->card, "SGI HAL2 Audio", 0, 1, 1, &pcm);
743 if (err < 0)
744 return err;
745
746 pcm->private_data = hal2;
747 strcpy(pcm->name, "SGI HAL2");
748
749 /* set operators */
750 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
751 &hal2_playback_ops);
752 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
753 &hal2_capture_ops);
754 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_CONTINUOUS,
755 snd_dma_continuous_data(GFP_KERNEL),
756 0, 1024 * 1024);
757
758 return 0;
759}
760
761static int hal2_dev_free(struct snd_device *device)
762{
763 struct snd_hal2 *hal2 = device->device_data;
764
765 free_irq(SGI_HPCDMA_IRQ, hal2);
766 kfree(hal2);
767 return 0;
768}
769
770static struct snd_device_ops hal2_ops = {
771 .dev_free = hal2_dev_free,
772};
773
774static void hal2_init_codec(struct hal2_codec *codec, struct hpc3_regs *hpc3,
775 int index)
776{
777 codec->pbus.pbusnr = index;
778 codec->pbus.pbus = &hpc3->pbdma[index];
779}
780
781static int hal2_detect(struct snd_hal2 *hal2)
782{
783 unsigned short board, major, minor;
784 unsigned short rev;
785
786 /* reset HAL2 */
787 hal2_write(0, &hal2->ctl_regs->isr);
788
789 /* release reset */
790 hal2_write(H2_ISR_GLOBAL_RESET_N | H2_ISR_CODEC_RESET_N,
791 &hal2->ctl_regs->isr);
792
793
794 hal2_i_write16(hal2, H2I_RELAY_C, H2I_RELAY_C_STATE);
795 rev = hal2_read(&hal2->ctl_regs->rev);
796 if (rev & H2_REV_AUDIO_PRESENT)
797 return -ENODEV;
798
799 board = (rev & H2_REV_BOARD_M) >> 12;
800 major = (rev & H2_REV_MAJOR_CHIP_M) >> 4;
801 minor = (rev & H2_REV_MINOR_CHIP_M);
802
803 printk(KERN_INFO "SGI HAL2 revision %i.%i.%i\n",
804 board, major, minor);
805
806 return 0;
807}
808
809static int hal2_create(struct snd_card *card, struct snd_hal2 **rchip)
810{
811 struct snd_hal2 *hal2;
812 struct hpc3_regs *hpc3 = hpc3c0;
813 int err;
814
815 hal2 = kzalloc(sizeof(struct snd_hal2), GFP_KERNEL);
816 if (!hal2)
817 return -ENOMEM;
818
819 hal2->card = card;
820
821 if (request_irq(SGI_HPCDMA_IRQ, hal2_interrupt, IRQF_SHARED,
822 "SGI HAL2", hal2)) {
823 printk(KERN_ERR "HAL2: Can't get irq %d\n", SGI_HPCDMA_IRQ);
824 kfree(hal2);
825 return -EAGAIN;
826 }
827
828 hal2->ctl_regs = (struct hal2_ctl_regs *)hpc3->pbus_extregs[0];
829 hal2->aes_regs = (struct hal2_aes_regs *)hpc3->pbus_extregs[1];
830 hal2->vol_regs = (struct hal2_vol_regs *)hpc3->pbus_extregs[2];
831 hal2->syn_regs = (struct hal2_syn_regs *)hpc3->pbus_extregs[3];
832
833 if (hal2_detect(hal2) < 0) {
834 kfree(hal2);
835 return -ENODEV;
836 }
837
838 hal2_init_codec(&hal2->dac, hpc3, 0);
839 hal2_init_codec(&hal2->adc, hpc3, 1);
840
841 /*
842 * All DMA channel interfaces in HAL2 are designed to operate with
843 * PBUS programmed for 2 cycles in D3, 2 cycles in D4 and 2 cycles
844 * in D5. HAL2 is a 16-bit device which can accept both big and little
845 * endian format. It assumes that even address bytes are on high
846 * portion of PBUS (15:8) and assumes that HPC3 is programmed to
847 * accept a live (unsynchronized) version of P_DREQ_N from HAL2.
848 */
849#define HAL2_PBUS_DMACFG ((0 << HPC3_DMACFG_D3R_SHIFT) | \
850 (2 << HPC3_DMACFG_D4R_SHIFT) | \
851 (2 << HPC3_DMACFG_D5R_SHIFT) | \
852 (0 << HPC3_DMACFG_D3W_SHIFT) | \
853 (2 << HPC3_DMACFG_D4W_SHIFT) | \
854 (2 << HPC3_DMACFG_D5W_SHIFT) | \
855 HPC3_DMACFG_DS16 | \
856 HPC3_DMACFG_EVENHI | \
857 HPC3_DMACFG_RTIME | \
858 (8 << HPC3_DMACFG_BURST_SHIFT) | \
859 HPC3_DMACFG_DRQLIVE)
860 /*
861 * Ignore what's mentioned in the specification and write value which
862 * works in The Real World (TM)
863 */
864 hpc3->pbus_dmacfg[hal2->dac.pbus.pbusnr][0] = 0x8208844;
865 hpc3->pbus_dmacfg[hal2->adc.pbus.pbusnr][0] = 0x8208844;
866
867 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, hal2, &hal2_ops);
868 if (err < 0) {
869 free_irq(SGI_HPCDMA_IRQ, hal2);
870 kfree(hal2);
871 return err;
872 }
873 *rchip = hal2;
874 return 0;
875}
876
877static int hal2_probe(struct platform_device *pdev)
878{
879 struct snd_card *card;
880 struct snd_hal2 *chip;
881 int err;
882
883 err = snd_card_new(&pdev->dev, index, id, THIS_MODULE, 0, &card);
884 if (err < 0)
885 return err;
886
887 err = hal2_create(card, &chip);
888 if (err < 0) {
889 snd_card_free(card);
890 return err;
891 }
892
893 err = hal2_pcm_create(chip);
894 if (err < 0) {
895 snd_card_free(card);
896 return err;
897 }
898 err = hal2_mixer_create(chip);
899 if (err < 0) {
900 snd_card_free(card);
901 return err;
902 }
903
904 strcpy(card->driver, "SGI HAL2 Audio");
905 strcpy(card->shortname, "SGI HAL2 Audio");
906 sprintf(card->longname, "%s irq %i",
907 card->shortname,
908 SGI_HPCDMA_IRQ);
909
910 err = snd_card_register(card);
911 if (err < 0) {
912 snd_card_free(card);
913 return err;
914 }
915 platform_set_drvdata(pdev, card);
916 return 0;
917}
918
919static int hal2_remove(struct platform_device *pdev)
920{
921 struct snd_card *card = platform_get_drvdata(pdev);
922
923 snd_card_free(card);
924 return 0;
925}
926
927static struct platform_driver hal2_driver = {
928 .probe = hal2_probe,
929 .remove = hal2_remove,
930 .driver = {
931 .name = "sgihal2",
932 }
933};
934
935module_platform_driver(hal2_driver);
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Driver for A2 audio system used in SGI machines
4 * Copyright (c) 2008 Thomas Bogendoerfer <tsbogend@alpha.fanken.de>
5 *
6 * Based on OSS code from Ladislav Michl <ladis@linux-mips.org>, which
7 * was based on code from Ulf Carlsson
8 */
9#include <linux/kernel.h>
10#include <linux/init.h>
11#include <linux/interrupt.h>
12#include <linux/dma-mapping.h>
13#include <linux/platform_device.h>
14#include <linux/io.h>
15#include <linux/slab.h>
16#include <linux/module.h>
17
18#include <asm/sgi/hpc3.h>
19#include <asm/sgi/ip22.h>
20
21#include <sound/core.h>
22#include <sound/control.h>
23#include <sound/pcm.h>
24#include <sound/pcm-indirect.h>
25#include <sound/initval.h>
26
27#include "hal2.h"
28
29static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */
30static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
31
32module_param(index, int, 0444);
33MODULE_PARM_DESC(index, "Index value for SGI HAL2 soundcard.");
34module_param(id, charp, 0444);
35MODULE_PARM_DESC(id, "ID string for SGI HAL2 soundcard.");
36MODULE_DESCRIPTION("ALSA driver for SGI HAL2 audio");
37MODULE_AUTHOR("Thomas Bogendoerfer");
38MODULE_LICENSE("GPL");
39
40
41#define H2_BLOCK_SIZE 1024
42#define H2_BUF_SIZE 16384
43
44struct hal2_pbus {
45 struct hpc3_pbus_dmacregs *pbus;
46 int pbusnr;
47 unsigned int ctrl; /* Current state of pbus->pbdma_ctrl */
48};
49
50struct hal2_desc {
51 struct hpc_dma_desc desc;
52 u32 pad; /* padding */
53};
54
55struct hal2_codec {
56 struct snd_pcm_indirect pcm_indirect;
57 struct snd_pcm_substream *substream;
58
59 unsigned char *buffer;
60 dma_addr_t buffer_dma;
61 struct hal2_desc *desc;
62 dma_addr_t desc_dma;
63 int desc_count;
64 struct hal2_pbus pbus;
65 int voices; /* mono/stereo */
66 unsigned int sample_rate;
67 unsigned int master; /* Master frequency */
68 unsigned short mod; /* MOD value */
69 unsigned short inc; /* INC value */
70};
71
72#define H2_MIX_OUTPUT_ATT 0
73#define H2_MIX_INPUT_GAIN 1
74
75struct snd_hal2 {
76 struct snd_card *card;
77
78 struct hal2_ctl_regs *ctl_regs; /* HAL2 ctl registers */
79 struct hal2_aes_regs *aes_regs; /* HAL2 aes registers */
80 struct hal2_vol_regs *vol_regs; /* HAL2 vol registers */
81 struct hal2_syn_regs *syn_regs; /* HAL2 syn registers */
82
83 struct hal2_codec dac;
84 struct hal2_codec adc;
85};
86
87#define H2_INDIRECT_WAIT(regs) while (hal2_read(®s->isr) & H2_ISR_TSTATUS);
88
89#define H2_READ_ADDR(addr) (addr | (1<<7))
90#define H2_WRITE_ADDR(addr) (addr)
91
92static inline u32 hal2_read(u32 *reg)
93{
94 return __raw_readl(reg);
95}
96
97static inline void hal2_write(u32 val, u32 *reg)
98{
99 __raw_writel(val, reg);
100}
101
102
103static u32 hal2_i_read32(struct snd_hal2 *hal2, u16 addr)
104{
105 u32 ret;
106 struct hal2_ctl_regs *regs = hal2->ctl_regs;
107
108 hal2_write(H2_READ_ADDR(addr), ®s->iar);
109 H2_INDIRECT_WAIT(regs);
110 ret = hal2_read(®s->idr0) & 0xffff;
111 hal2_write(H2_READ_ADDR(addr) | 0x1, ®s->iar);
112 H2_INDIRECT_WAIT(regs);
113 ret |= (hal2_read(®s->idr0) & 0xffff) << 16;
114 return ret;
115}
116
117static void hal2_i_write16(struct snd_hal2 *hal2, u16 addr, u16 val)
118{
119 struct hal2_ctl_regs *regs = hal2->ctl_regs;
120
121 hal2_write(val, ®s->idr0);
122 hal2_write(0, ®s->idr1);
123 hal2_write(0, ®s->idr2);
124 hal2_write(0, ®s->idr3);
125 hal2_write(H2_WRITE_ADDR(addr), ®s->iar);
126 H2_INDIRECT_WAIT(regs);
127}
128
129static void hal2_i_write32(struct snd_hal2 *hal2, u16 addr, u32 val)
130{
131 struct hal2_ctl_regs *regs = hal2->ctl_regs;
132
133 hal2_write(val & 0xffff, ®s->idr0);
134 hal2_write(val >> 16, ®s->idr1);
135 hal2_write(0, ®s->idr2);
136 hal2_write(0, ®s->idr3);
137 hal2_write(H2_WRITE_ADDR(addr), ®s->iar);
138 H2_INDIRECT_WAIT(regs);
139}
140
141static void hal2_i_setbit16(struct snd_hal2 *hal2, u16 addr, u16 bit)
142{
143 struct hal2_ctl_regs *regs = hal2->ctl_regs;
144
145 hal2_write(H2_READ_ADDR(addr), ®s->iar);
146 H2_INDIRECT_WAIT(regs);
147 hal2_write((hal2_read(®s->idr0) & 0xffff) | bit, ®s->idr0);
148 hal2_write(0, ®s->idr1);
149 hal2_write(0, ®s->idr2);
150 hal2_write(0, ®s->idr3);
151 hal2_write(H2_WRITE_ADDR(addr), ®s->iar);
152 H2_INDIRECT_WAIT(regs);
153}
154
155static void hal2_i_clearbit16(struct snd_hal2 *hal2, u16 addr, u16 bit)
156{
157 struct hal2_ctl_regs *regs = hal2->ctl_regs;
158
159 hal2_write(H2_READ_ADDR(addr), ®s->iar);
160 H2_INDIRECT_WAIT(regs);
161 hal2_write((hal2_read(®s->idr0) & 0xffff) & ~bit, ®s->idr0);
162 hal2_write(0, ®s->idr1);
163 hal2_write(0, ®s->idr2);
164 hal2_write(0, ®s->idr3);
165 hal2_write(H2_WRITE_ADDR(addr), ®s->iar);
166 H2_INDIRECT_WAIT(regs);
167}
168
169static int hal2_gain_info(struct snd_kcontrol *kcontrol,
170 struct snd_ctl_elem_info *uinfo)
171{
172 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
173 uinfo->count = 2;
174 uinfo->value.integer.min = 0;
175 switch ((int)kcontrol->private_value) {
176 case H2_MIX_OUTPUT_ATT:
177 uinfo->value.integer.max = 31;
178 break;
179 case H2_MIX_INPUT_GAIN:
180 uinfo->value.integer.max = 15;
181 break;
182 }
183 return 0;
184}
185
186static int hal2_gain_get(struct snd_kcontrol *kcontrol,
187 struct snd_ctl_elem_value *ucontrol)
188{
189 struct snd_hal2 *hal2 = snd_kcontrol_chip(kcontrol);
190 u32 tmp;
191 int l, r;
192
193 switch ((int)kcontrol->private_value) {
194 case H2_MIX_OUTPUT_ATT:
195 tmp = hal2_i_read32(hal2, H2I_DAC_C2);
196 if (tmp & H2I_C2_MUTE) {
197 l = 0;
198 r = 0;
199 } else {
200 l = 31 - ((tmp >> H2I_C2_L_ATT_SHIFT) & 31);
201 r = 31 - ((tmp >> H2I_C2_R_ATT_SHIFT) & 31);
202 }
203 break;
204 case H2_MIX_INPUT_GAIN:
205 tmp = hal2_i_read32(hal2, H2I_ADC_C2);
206 l = (tmp >> H2I_C2_L_GAIN_SHIFT) & 15;
207 r = (tmp >> H2I_C2_R_GAIN_SHIFT) & 15;
208 break;
209 default:
210 return -EINVAL;
211 }
212 ucontrol->value.integer.value[0] = l;
213 ucontrol->value.integer.value[1] = r;
214
215 return 0;
216}
217
218static int hal2_gain_put(struct snd_kcontrol *kcontrol,
219 struct snd_ctl_elem_value *ucontrol)
220{
221 struct snd_hal2 *hal2 = snd_kcontrol_chip(kcontrol);
222 u32 old, new;
223 int l, r;
224
225 l = ucontrol->value.integer.value[0];
226 r = ucontrol->value.integer.value[1];
227
228 switch ((int)kcontrol->private_value) {
229 case H2_MIX_OUTPUT_ATT:
230 old = hal2_i_read32(hal2, H2I_DAC_C2);
231 new = old & ~(H2I_C2_L_ATT_M | H2I_C2_R_ATT_M | H2I_C2_MUTE);
232 if (l | r) {
233 l = 31 - l;
234 r = 31 - r;
235 new |= (l << H2I_C2_L_ATT_SHIFT);
236 new |= (r << H2I_C2_R_ATT_SHIFT);
237 } else
238 new |= H2I_C2_L_ATT_M | H2I_C2_R_ATT_M | H2I_C2_MUTE;
239 hal2_i_write32(hal2, H2I_DAC_C2, new);
240 break;
241 case H2_MIX_INPUT_GAIN:
242 old = hal2_i_read32(hal2, H2I_ADC_C2);
243 new = old & ~(H2I_C2_L_GAIN_M | H2I_C2_R_GAIN_M);
244 new |= (l << H2I_C2_L_GAIN_SHIFT);
245 new |= (r << H2I_C2_R_GAIN_SHIFT);
246 hal2_i_write32(hal2, H2I_ADC_C2, new);
247 break;
248 default:
249 return -EINVAL;
250 }
251 return old != new;
252}
253
254static const struct snd_kcontrol_new hal2_ctrl_headphone = {
255 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
256 .name = "Headphone Playback Volume",
257 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
258 .private_value = H2_MIX_OUTPUT_ATT,
259 .info = hal2_gain_info,
260 .get = hal2_gain_get,
261 .put = hal2_gain_put,
262};
263
264static const struct snd_kcontrol_new hal2_ctrl_mic = {
265 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
266 .name = "Mic Capture Volume",
267 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
268 .private_value = H2_MIX_INPUT_GAIN,
269 .info = hal2_gain_info,
270 .get = hal2_gain_get,
271 .put = hal2_gain_put,
272};
273
274static int hal2_mixer_create(struct snd_hal2 *hal2)
275{
276 int err;
277
278 /* mute DAC */
279 hal2_i_write32(hal2, H2I_DAC_C2,
280 H2I_C2_L_ATT_M | H2I_C2_R_ATT_M | H2I_C2_MUTE);
281 /* mute ADC */
282 hal2_i_write32(hal2, H2I_ADC_C2, 0);
283
284 err = snd_ctl_add(hal2->card,
285 snd_ctl_new1(&hal2_ctrl_headphone, hal2));
286 if (err < 0)
287 return err;
288
289 err = snd_ctl_add(hal2->card,
290 snd_ctl_new1(&hal2_ctrl_mic, hal2));
291 if (err < 0)
292 return err;
293
294 return 0;
295}
296
297static irqreturn_t hal2_interrupt(int irq, void *dev_id)
298{
299 struct snd_hal2 *hal2 = dev_id;
300 irqreturn_t ret = IRQ_NONE;
301
302 /* decide what caused this interrupt */
303 if (hal2->dac.pbus.pbus->pbdma_ctrl & HPC3_PDMACTRL_INT) {
304 snd_pcm_period_elapsed(hal2->dac.substream);
305 ret = IRQ_HANDLED;
306 }
307 if (hal2->adc.pbus.pbus->pbdma_ctrl & HPC3_PDMACTRL_INT) {
308 snd_pcm_period_elapsed(hal2->adc.substream);
309 ret = IRQ_HANDLED;
310 }
311 return ret;
312}
313
314static int hal2_compute_rate(struct hal2_codec *codec, unsigned int rate)
315{
316 unsigned short mod;
317
318 if (44100 % rate < 48000 % rate) {
319 mod = 4 * 44100 / rate;
320 codec->master = 44100;
321 } else {
322 mod = 4 * 48000 / rate;
323 codec->master = 48000;
324 }
325
326 codec->inc = 4;
327 codec->mod = mod;
328 rate = 4 * codec->master / mod;
329
330 return rate;
331}
332
333static void hal2_set_dac_rate(struct snd_hal2 *hal2)
334{
335 unsigned int master = hal2->dac.master;
336 int inc = hal2->dac.inc;
337 int mod = hal2->dac.mod;
338
339 hal2_i_write16(hal2, H2I_BRES1_C1, (master == 44100) ? 1 : 0);
340 hal2_i_write32(hal2, H2I_BRES1_C2,
341 ((0xffff & (inc - mod - 1)) << 16) | inc);
342}
343
344static void hal2_set_adc_rate(struct snd_hal2 *hal2)
345{
346 unsigned int master = hal2->adc.master;
347 int inc = hal2->adc.inc;
348 int mod = hal2->adc.mod;
349
350 hal2_i_write16(hal2, H2I_BRES2_C1, (master == 44100) ? 1 : 0);
351 hal2_i_write32(hal2, H2I_BRES2_C2,
352 ((0xffff & (inc - mod - 1)) << 16) | inc);
353}
354
355static void hal2_setup_dac(struct snd_hal2 *hal2)
356{
357 unsigned int fifobeg, fifoend, highwater, sample_size;
358 struct hal2_pbus *pbus = &hal2->dac.pbus;
359
360 /* Now we set up some PBUS information. The PBUS needs information about
361 * what portion of the fifo it will use. If it's receiving or
362 * transmitting, and finally whether the stream is little endian or big
363 * endian. The information is written later, on the start call.
364 */
365 sample_size = 2 * hal2->dac.voices;
366 /* Fifo should be set to hold exactly four samples. Highwater mark
367 * should be set to two samples. */
368 highwater = (sample_size * 2) >> 1; /* halfwords */
369 fifobeg = 0; /* playback is first */
370 fifoend = (sample_size * 4) >> 3; /* doublewords */
371 pbus->ctrl = HPC3_PDMACTRL_RT | HPC3_PDMACTRL_LD |
372 (highwater << 8) | (fifobeg << 16) | (fifoend << 24);
373 /* We disable everything before we do anything at all */
374 pbus->pbus->pbdma_ctrl = HPC3_PDMACTRL_LD;
375 hal2_i_clearbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECTX);
376 /* Setup the HAL2 for playback */
377 hal2_set_dac_rate(hal2);
378 /* Set endianess */
379 hal2_i_clearbit16(hal2, H2I_DMA_END, H2I_DMA_END_CODECTX);
380 /* Set DMA bus */
381 hal2_i_setbit16(hal2, H2I_DMA_DRV, (1 << pbus->pbusnr));
382 /* We are using 1st Bresenham clock generator for playback */
383 hal2_i_write16(hal2, H2I_DAC_C1, (pbus->pbusnr << H2I_C1_DMA_SHIFT)
384 | (1 << H2I_C1_CLKID_SHIFT)
385 | (hal2->dac.voices << H2I_C1_DATAT_SHIFT));
386}
387
388static void hal2_setup_adc(struct snd_hal2 *hal2)
389{
390 unsigned int fifobeg, fifoend, highwater, sample_size;
391 struct hal2_pbus *pbus = &hal2->adc.pbus;
392
393 sample_size = 2 * hal2->adc.voices;
394 highwater = (sample_size * 2) >> 1; /* halfwords */
395 fifobeg = (4 * 4) >> 3; /* record is second */
396 fifoend = (4 * 4 + sample_size * 4) >> 3; /* doublewords */
397 pbus->ctrl = HPC3_PDMACTRL_RT | HPC3_PDMACTRL_RCV | HPC3_PDMACTRL_LD |
398 (highwater << 8) | (fifobeg << 16) | (fifoend << 24);
399 pbus->pbus->pbdma_ctrl = HPC3_PDMACTRL_LD;
400 hal2_i_clearbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECR);
401 /* Setup the HAL2 for record */
402 hal2_set_adc_rate(hal2);
403 /* Set endianess */
404 hal2_i_clearbit16(hal2, H2I_DMA_END, H2I_DMA_END_CODECR);
405 /* Set DMA bus */
406 hal2_i_setbit16(hal2, H2I_DMA_DRV, (1 << pbus->pbusnr));
407 /* We are using 2nd Bresenham clock generator for record */
408 hal2_i_write16(hal2, H2I_ADC_C1, (pbus->pbusnr << H2I_C1_DMA_SHIFT)
409 | (2 << H2I_C1_CLKID_SHIFT)
410 | (hal2->adc.voices << H2I_C1_DATAT_SHIFT));
411}
412
413static void hal2_start_dac(struct snd_hal2 *hal2)
414{
415 struct hal2_pbus *pbus = &hal2->dac.pbus;
416
417 pbus->pbus->pbdma_dptr = hal2->dac.desc_dma;
418 pbus->pbus->pbdma_ctrl = pbus->ctrl | HPC3_PDMACTRL_ACT;
419 /* enable DAC */
420 hal2_i_setbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECTX);
421}
422
423static void hal2_start_adc(struct snd_hal2 *hal2)
424{
425 struct hal2_pbus *pbus = &hal2->adc.pbus;
426
427 pbus->pbus->pbdma_dptr = hal2->adc.desc_dma;
428 pbus->pbus->pbdma_ctrl = pbus->ctrl | HPC3_PDMACTRL_ACT;
429 /* enable ADC */
430 hal2_i_setbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECR);
431}
432
433static inline void hal2_stop_dac(struct snd_hal2 *hal2)
434{
435 hal2->dac.pbus.pbus->pbdma_ctrl = HPC3_PDMACTRL_LD;
436 /* The HAL2 itself may remain enabled safely */
437}
438
439static inline void hal2_stop_adc(struct snd_hal2 *hal2)
440{
441 hal2->adc.pbus.pbus->pbdma_ctrl = HPC3_PDMACTRL_LD;
442}
443
444static int hal2_alloc_dmabuf(struct snd_hal2 *hal2, struct hal2_codec *codec)
445{
446 struct device *dev = hal2->card->dev;
447 struct hal2_desc *desc;
448 dma_addr_t desc_dma, buffer_dma;
449 int count = H2_BUF_SIZE / H2_BLOCK_SIZE;
450 int i;
451
452 codec->buffer = dma_alloc_attrs(dev, H2_BUF_SIZE, &buffer_dma,
453 GFP_KERNEL, DMA_ATTR_NON_CONSISTENT);
454 if (!codec->buffer)
455 return -ENOMEM;
456 desc = dma_alloc_attrs(dev, count * sizeof(struct hal2_desc),
457 &desc_dma, GFP_KERNEL, DMA_ATTR_NON_CONSISTENT);
458 if (!desc) {
459 dma_free_attrs(dev, H2_BUF_SIZE, codec->buffer, buffer_dma,
460 DMA_ATTR_NON_CONSISTENT);
461 return -ENOMEM;
462 }
463 codec->buffer_dma = buffer_dma;
464 codec->desc_dma = desc_dma;
465 codec->desc = desc;
466 for (i = 0; i < count; i++) {
467 desc->desc.pbuf = buffer_dma + i * H2_BLOCK_SIZE;
468 desc->desc.cntinfo = HPCDMA_XIE | H2_BLOCK_SIZE;
469 desc->desc.pnext = (i == count - 1) ?
470 desc_dma : desc_dma + (i + 1) * sizeof(struct hal2_desc);
471 desc++;
472 }
473 dma_cache_sync(dev, codec->desc, count * sizeof(struct hal2_desc),
474 DMA_TO_DEVICE);
475 codec->desc_count = count;
476 return 0;
477}
478
479static void hal2_free_dmabuf(struct snd_hal2 *hal2, struct hal2_codec *codec)
480{
481 struct device *dev = hal2->card->dev;
482
483 dma_free_attrs(dev, codec->desc_count * sizeof(struct hal2_desc),
484 codec->desc, codec->desc_dma, DMA_ATTR_NON_CONSISTENT);
485 dma_free_attrs(dev, H2_BUF_SIZE, codec->buffer, codec->buffer_dma,
486 DMA_ATTR_NON_CONSISTENT);
487}
488
489static const struct snd_pcm_hardware hal2_pcm_hw = {
490 .info = (SNDRV_PCM_INFO_MMAP |
491 SNDRV_PCM_INFO_MMAP_VALID |
492 SNDRV_PCM_INFO_INTERLEAVED |
493 SNDRV_PCM_INFO_BLOCK_TRANSFER |
494 SNDRV_PCM_INFO_SYNC_APPLPTR),
495 .formats = SNDRV_PCM_FMTBIT_S16_BE,
496 .rates = SNDRV_PCM_RATE_8000_48000,
497 .rate_min = 8000,
498 .rate_max = 48000,
499 .channels_min = 2,
500 .channels_max = 2,
501 .buffer_bytes_max = 65536,
502 .period_bytes_min = 1024,
503 .period_bytes_max = 65536,
504 .periods_min = 2,
505 .periods_max = 1024,
506};
507
508static int hal2_pcm_hw_params(struct snd_pcm_substream *substream,
509 struct snd_pcm_hw_params *params)
510{
511 int err;
512
513 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params));
514 if (err < 0)
515 return err;
516
517 return 0;
518}
519
520static int hal2_pcm_hw_free(struct snd_pcm_substream *substream)
521{
522 return snd_pcm_lib_free_pages(substream);
523}
524
525static int hal2_playback_open(struct snd_pcm_substream *substream)
526{
527 struct snd_pcm_runtime *runtime = substream->runtime;
528 struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
529 int err;
530
531 runtime->hw = hal2_pcm_hw;
532
533 err = hal2_alloc_dmabuf(hal2, &hal2->dac);
534 if (err)
535 return err;
536 return 0;
537}
538
539static int hal2_playback_close(struct snd_pcm_substream *substream)
540{
541 struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
542
543 hal2_free_dmabuf(hal2, &hal2->dac);
544 return 0;
545}
546
547static int hal2_playback_prepare(struct snd_pcm_substream *substream)
548{
549 struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
550 struct snd_pcm_runtime *runtime = substream->runtime;
551 struct hal2_codec *dac = &hal2->dac;
552
553 dac->voices = runtime->channels;
554 dac->sample_rate = hal2_compute_rate(dac, runtime->rate);
555 memset(&dac->pcm_indirect, 0, sizeof(dac->pcm_indirect));
556 dac->pcm_indirect.hw_buffer_size = H2_BUF_SIZE;
557 dac->pcm_indirect.hw_queue_size = H2_BUF_SIZE / 2;
558 dac->pcm_indirect.hw_io = dac->buffer_dma;
559 dac->pcm_indirect.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
560 dac->substream = substream;
561 hal2_setup_dac(hal2);
562 return 0;
563}
564
565static int hal2_playback_trigger(struct snd_pcm_substream *substream, int cmd)
566{
567 struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
568
569 switch (cmd) {
570 case SNDRV_PCM_TRIGGER_START:
571 hal2_start_dac(hal2);
572 break;
573 case SNDRV_PCM_TRIGGER_STOP:
574 hal2_stop_dac(hal2);
575 break;
576 default:
577 return -EINVAL;
578 }
579 return 0;
580}
581
582static snd_pcm_uframes_t
583hal2_playback_pointer(struct snd_pcm_substream *substream)
584{
585 struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
586 struct hal2_codec *dac = &hal2->dac;
587
588 return snd_pcm_indirect_playback_pointer(substream, &dac->pcm_indirect,
589 dac->pbus.pbus->pbdma_bptr);
590}
591
592static void hal2_playback_transfer(struct snd_pcm_substream *substream,
593 struct snd_pcm_indirect *rec, size_t bytes)
594{
595 struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
596 unsigned char *buf = hal2->dac.buffer + rec->hw_data;
597
598 memcpy(buf, substream->runtime->dma_area + rec->sw_data, bytes);
599 dma_cache_sync(hal2->card->dev, buf, bytes, DMA_TO_DEVICE);
600
601}
602
603static int hal2_playback_ack(struct snd_pcm_substream *substream)
604{
605 struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
606 struct hal2_codec *dac = &hal2->dac;
607
608 return snd_pcm_indirect_playback_transfer(substream,
609 &dac->pcm_indirect,
610 hal2_playback_transfer);
611}
612
613static int hal2_capture_open(struct snd_pcm_substream *substream)
614{
615 struct snd_pcm_runtime *runtime = substream->runtime;
616 struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
617 struct hal2_codec *adc = &hal2->adc;
618 int err;
619
620 runtime->hw = hal2_pcm_hw;
621
622 err = hal2_alloc_dmabuf(hal2, adc);
623 if (err)
624 return err;
625 return 0;
626}
627
628static int hal2_capture_close(struct snd_pcm_substream *substream)
629{
630 struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
631
632 hal2_free_dmabuf(hal2, &hal2->adc);
633 return 0;
634}
635
636static int hal2_capture_prepare(struct snd_pcm_substream *substream)
637{
638 struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
639 struct snd_pcm_runtime *runtime = substream->runtime;
640 struct hal2_codec *adc = &hal2->adc;
641
642 adc->voices = runtime->channels;
643 adc->sample_rate = hal2_compute_rate(adc, runtime->rate);
644 memset(&adc->pcm_indirect, 0, sizeof(adc->pcm_indirect));
645 adc->pcm_indirect.hw_buffer_size = H2_BUF_SIZE;
646 adc->pcm_indirect.hw_queue_size = H2_BUF_SIZE / 2;
647 adc->pcm_indirect.hw_io = adc->buffer_dma;
648 adc->pcm_indirect.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
649 adc->substream = substream;
650 hal2_setup_adc(hal2);
651 return 0;
652}
653
654static int hal2_capture_trigger(struct snd_pcm_substream *substream, int cmd)
655{
656 struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
657
658 switch (cmd) {
659 case SNDRV_PCM_TRIGGER_START:
660 hal2_start_adc(hal2);
661 break;
662 case SNDRV_PCM_TRIGGER_STOP:
663 hal2_stop_adc(hal2);
664 break;
665 default:
666 return -EINVAL;
667 }
668 return 0;
669}
670
671static snd_pcm_uframes_t
672hal2_capture_pointer(struct snd_pcm_substream *substream)
673{
674 struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
675 struct hal2_codec *adc = &hal2->adc;
676
677 return snd_pcm_indirect_capture_pointer(substream, &adc->pcm_indirect,
678 adc->pbus.pbus->pbdma_bptr);
679}
680
681static void hal2_capture_transfer(struct snd_pcm_substream *substream,
682 struct snd_pcm_indirect *rec, size_t bytes)
683{
684 struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
685 unsigned char *buf = hal2->adc.buffer + rec->hw_data;
686
687 dma_cache_sync(hal2->card->dev, buf, bytes, DMA_FROM_DEVICE);
688 memcpy(substream->runtime->dma_area + rec->sw_data, buf, bytes);
689}
690
691static int hal2_capture_ack(struct snd_pcm_substream *substream)
692{
693 struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
694 struct hal2_codec *adc = &hal2->adc;
695
696 return snd_pcm_indirect_capture_transfer(substream,
697 &adc->pcm_indirect,
698 hal2_capture_transfer);
699}
700
701static const struct snd_pcm_ops hal2_playback_ops = {
702 .open = hal2_playback_open,
703 .close = hal2_playback_close,
704 .ioctl = snd_pcm_lib_ioctl,
705 .hw_params = hal2_pcm_hw_params,
706 .hw_free = hal2_pcm_hw_free,
707 .prepare = hal2_playback_prepare,
708 .trigger = hal2_playback_trigger,
709 .pointer = hal2_playback_pointer,
710 .ack = hal2_playback_ack,
711};
712
713static const struct snd_pcm_ops hal2_capture_ops = {
714 .open = hal2_capture_open,
715 .close = hal2_capture_close,
716 .ioctl = snd_pcm_lib_ioctl,
717 .hw_params = hal2_pcm_hw_params,
718 .hw_free = hal2_pcm_hw_free,
719 .prepare = hal2_capture_prepare,
720 .trigger = hal2_capture_trigger,
721 .pointer = hal2_capture_pointer,
722 .ack = hal2_capture_ack,
723};
724
725static int hal2_pcm_create(struct snd_hal2 *hal2)
726{
727 struct snd_pcm *pcm;
728 int err;
729
730 /* create first pcm device with one outputs and one input */
731 err = snd_pcm_new(hal2->card, "SGI HAL2 Audio", 0, 1, 1, &pcm);
732 if (err < 0)
733 return err;
734
735 pcm->private_data = hal2;
736 strcpy(pcm->name, "SGI HAL2");
737
738 /* set operators */
739 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
740 &hal2_playback_ops);
741 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
742 &hal2_capture_ops);
743 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_CONTINUOUS,
744 snd_dma_continuous_data(GFP_KERNEL),
745 0, 1024 * 1024);
746
747 return 0;
748}
749
750static int hal2_dev_free(struct snd_device *device)
751{
752 struct snd_hal2 *hal2 = device->device_data;
753
754 free_irq(SGI_HPCDMA_IRQ, hal2);
755 kfree(hal2);
756 return 0;
757}
758
759static struct snd_device_ops hal2_ops = {
760 .dev_free = hal2_dev_free,
761};
762
763static void hal2_init_codec(struct hal2_codec *codec, struct hpc3_regs *hpc3,
764 int index)
765{
766 codec->pbus.pbusnr = index;
767 codec->pbus.pbus = &hpc3->pbdma[index];
768}
769
770static int hal2_detect(struct snd_hal2 *hal2)
771{
772 unsigned short board, major, minor;
773 unsigned short rev;
774
775 /* reset HAL2 */
776 hal2_write(0, &hal2->ctl_regs->isr);
777
778 /* release reset */
779 hal2_write(H2_ISR_GLOBAL_RESET_N | H2_ISR_CODEC_RESET_N,
780 &hal2->ctl_regs->isr);
781
782
783 hal2_i_write16(hal2, H2I_RELAY_C, H2I_RELAY_C_STATE);
784 rev = hal2_read(&hal2->ctl_regs->rev);
785 if (rev & H2_REV_AUDIO_PRESENT)
786 return -ENODEV;
787
788 board = (rev & H2_REV_BOARD_M) >> 12;
789 major = (rev & H2_REV_MAJOR_CHIP_M) >> 4;
790 minor = (rev & H2_REV_MINOR_CHIP_M);
791
792 printk(KERN_INFO "SGI HAL2 revision %i.%i.%i\n",
793 board, major, minor);
794
795 return 0;
796}
797
798static int hal2_create(struct snd_card *card, struct snd_hal2 **rchip)
799{
800 struct snd_hal2 *hal2;
801 struct hpc3_regs *hpc3 = hpc3c0;
802 int err;
803
804 hal2 = kzalloc(sizeof(*hal2), GFP_KERNEL);
805 if (!hal2)
806 return -ENOMEM;
807
808 hal2->card = card;
809
810 if (request_irq(SGI_HPCDMA_IRQ, hal2_interrupt, IRQF_SHARED,
811 "SGI HAL2", hal2)) {
812 printk(KERN_ERR "HAL2: Can't get irq %d\n", SGI_HPCDMA_IRQ);
813 kfree(hal2);
814 return -EAGAIN;
815 }
816
817 hal2->ctl_regs = (struct hal2_ctl_regs *)hpc3->pbus_extregs[0];
818 hal2->aes_regs = (struct hal2_aes_regs *)hpc3->pbus_extregs[1];
819 hal2->vol_regs = (struct hal2_vol_regs *)hpc3->pbus_extregs[2];
820 hal2->syn_regs = (struct hal2_syn_regs *)hpc3->pbus_extregs[3];
821
822 if (hal2_detect(hal2) < 0) {
823 kfree(hal2);
824 return -ENODEV;
825 }
826
827 hal2_init_codec(&hal2->dac, hpc3, 0);
828 hal2_init_codec(&hal2->adc, hpc3, 1);
829
830 /*
831 * All DMA channel interfaces in HAL2 are designed to operate with
832 * PBUS programmed for 2 cycles in D3, 2 cycles in D4 and 2 cycles
833 * in D5. HAL2 is a 16-bit device which can accept both big and little
834 * endian format. It assumes that even address bytes are on high
835 * portion of PBUS (15:8) and assumes that HPC3 is programmed to
836 * accept a live (unsynchronized) version of P_DREQ_N from HAL2.
837 */
838#define HAL2_PBUS_DMACFG ((0 << HPC3_DMACFG_D3R_SHIFT) | \
839 (2 << HPC3_DMACFG_D4R_SHIFT) | \
840 (2 << HPC3_DMACFG_D5R_SHIFT) | \
841 (0 << HPC3_DMACFG_D3W_SHIFT) | \
842 (2 << HPC3_DMACFG_D4W_SHIFT) | \
843 (2 << HPC3_DMACFG_D5W_SHIFT) | \
844 HPC3_DMACFG_DS16 | \
845 HPC3_DMACFG_EVENHI | \
846 HPC3_DMACFG_RTIME | \
847 (8 << HPC3_DMACFG_BURST_SHIFT) | \
848 HPC3_DMACFG_DRQLIVE)
849 /*
850 * Ignore what's mentioned in the specification and write value which
851 * works in The Real World (TM)
852 */
853 hpc3->pbus_dmacfg[hal2->dac.pbus.pbusnr][0] = 0x8208844;
854 hpc3->pbus_dmacfg[hal2->adc.pbus.pbusnr][0] = 0x8208844;
855
856 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, hal2, &hal2_ops);
857 if (err < 0) {
858 free_irq(SGI_HPCDMA_IRQ, hal2);
859 kfree(hal2);
860 return err;
861 }
862 *rchip = hal2;
863 return 0;
864}
865
866static int hal2_probe(struct platform_device *pdev)
867{
868 struct snd_card *card;
869 struct snd_hal2 *chip;
870 int err;
871
872 err = snd_card_new(&pdev->dev, index, id, THIS_MODULE, 0, &card);
873 if (err < 0)
874 return err;
875
876 err = hal2_create(card, &chip);
877 if (err < 0) {
878 snd_card_free(card);
879 return err;
880 }
881
882 err = hal2_pcm_create(chip);
883 if (err < 0) {
884 snd_card_free(card);
885 return err;
886 }
887 err = hal2_mixer_create(chip);
888 if (err < 0) {
889 snd_card_free(card);
890 return err;
891 }
892
893 strcpy(card->driver, "SGI HAL2 Audio");
894 strcpy(card->shortname, "SGI HAL2 Audio");
895 sprintf(card->longname, "%s irq %i",
896 card->shortname,
897 SGI_HPCDMA_IRQ);
898
899 err = snd_card_register(card);
900 if (err < 0) {
901 snd_card_free(card);
902 return err;
903 }
904 platform_set_drvdata(pdev, card);
905 return 0;
906}
907
908static int hal2_remove(struct platform_device *pdev)
909{
910 struct snd_card *card = platform_get_drvdata(pdev);
911
912 snd_card_free(card);
913 return 0;
914}
915
916static struct platform_driver hal2_driver = {
917 .probe = hal2_probe,
918 .remove = hal2_remove,
919 .driver = {
920 .name = "sgihal2",
921 }
922};
923
924module_platform_driver(hal2_driver);