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1/**
2 * dwc3-pci.c - PCI Specific glue layer
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/slab.h>
22#include <linux/pci.h>
23#include <linux/platform_device.h>
24#include <linux/gpio/consumer.h>
25#include <linux/acpi.h>
26
27#include "platform_data.h"
28
29#define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3 0xabcd
30#define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI 0xabce
31#define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31 0xabcf
32#define PCI_DEVICE_ID_INTEL_BYT 0x0f37
33#define PCI_DEVICE_ID_INTEL_MRFLD 0x119e
34#define PCI_DEVICE_ID_INTEL_BSW 0x22b7
35#define PCI_DEVICE_ID_INTEL_SPTLP 0x9d30
36#define PCI_DEVICE_ID_INTEL_SPTH 0xa130
37#define PCI_DEVICE_ID_INTEL_BXT 0x0aaa
38#define PCI_DEVICE_ID_INTEL_BXT_M 0x1aaa
39#define PCI_DEVICE_ID_INTEL_APL 0x5aaa
40
41static const struct acpi_gpio_params reset_gpios = { 0, 0, false };
42static const struct acpi_gpio_params cs_gpios = { 1, 0, false };
43
44static const struct acpi_gpio_mapping acpi_dwc3_byt_gpios[] = {
45 { "reset-gpios", &reset_gpios, 1 },
46 { "cs-gpios", &cs_gpios, 1 },
47 { },
48};
49
50static int dwc3_pci_quirks(struct pci_dev *pdev)
51{
52 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
53 pdev->device == PCI_DEVICE_ID_AMD_NL_USB) {
54 struct dwc3_platform_data pdata;
55
56 memset(&pdata, 0, sizeof(pdata));
57
58 pdata.has_lpm_erratum = true;
59 pdata.lpm_nyet_threshold = 0xf;
60
61 pdata.u2exit_lfps_quirk = true;
62 pdata.u2ss_inp3_quirk = true;
63 pdata.req_p1p2p3_quirk = true;
64 pdata.del_p1p2p3_quirk = true;
65 pdata.del_phy_power_chg_quirk = true;
66 pdata.lfps_filter_quirk = true;
67 pdata.rx_detect_poll_quirk = true;
68
69 pdata.tx_de_emphasis_quirk = true;
70 pdata.tx_de_emphasis = 1;
71
72 /*
73 * FIXME these quirks should be removed when AMD NL
74 * taps out
75 */
76 pdata.disable_scramble_quirk = true;
77 pdata.dis_u3_susphy_quirk = true;
78 pdata.dis_u2_susphy_quirk = true;
79
80 return platform_device_add_data(pci_get_drvdata(pdev), &pdata,
81 sizeof(pdata));
82 }
83
84 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
85 pdev->device == PCI_DEVICE_ID_INTEL_BYT) {
86 struct gpio_desc *gpio;
87
88 acpi_dev_add_driver_gpios(ACPI_COMPANION(&pdev->dev),
89 acpi_dwc3_byt_gpios);
90
91 /*
92 * These GPIOs will turn on the USB2 PHY. Note that we have to
93 * put the gpio descriptors again here because the phy driver
94 * might want to grab them, too.
95 */
96 gpio = gpiod_get_optional(&pdev->dev, "cs", GPIOD_OUT_LOW);
97 if (IS_ERR(gpio))
98 return PTR_ERR(gpio);
99
100 gpiod_set_value_cansleep(gpio, 1);
101 gpiod_put(gpio);
102
103 gpio = gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW);
104 if (IS_ERR(gpio))
105 return PTR_ERR(gpio);
106
107 if (gpio) {
108 gpiod_set_value_cansleep(gpio, 1);
109 gpiod_put(gpio);
110 usleep_range(10000, 11000);
111 }
112 }
113
114 if (pdev->vendor == PCI_VENDOR_ID_SYNOPSYS &&
115 (pdev->device == PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3 ||
116 pdev->device == PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI ||
117 pdev->device == PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31)) {
118
119 struct dwc3_platform_data pdata;
120
121 memset(&pdata, 0, sizeof(pdata));
122 pdata.usb3_lpm_capable = true;
123 pdata.has_lpm_erratum = true;
124 pdata.dis_enblslpm_quirk = true;
125
126 return platform_device_add_data(pci_get_drvdata(pdev), &pdata,
127 sizeof(pdata));
128 }
129
130 return 0;
131}
132
133static int dwc3_pci_probe(struct pci_dev *pci,
134 const struct pci_device_id *id)
135{
136 struct resource res[2];
137 struct platform_device *dwc3;
138 int ret;
139 struct device *dev = &pci->dev;
140
141 ret = pcim_enable_device(pci);
142 if (ret) {
143 dev_err(dev, "failed to enable pci device\n");
144 return -ENODEV;
145 }
146
147 pci_set_master(pci);
148
149 dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO);
150 if (!dwc3) {
151 dev_err(dev, "couldn't allocate dwc3 device\n");
152 return -ENOMEM;
153 }
154
155 memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res));
156
157 res[0].start = pci_resource_start(pci, 0);
158 res[0].end = pci_resource_end(pci, 0);
159 res[0].name = "dwc_usb3";
160 res[0].flags = IORESOURCE_MEM;
161
162 res[1].start = pci->irq;
163 res[1].name = "dwc_usb3";
164 res[1].flags = IORESOURCE_IRQ;
165
166 ret = platform_device_add_resources(dwc3, res, ARRAY_SIZE(res));
167 if (ret) {
168 dev_err(dev, "couldn't add resources to dwc3 device\n");
169 return ret;
170 }
171
172 pci_set_drvdata(pci, dwc3);
173 ret = dwc3_pci_quirks(pci);
174 if (ret)
175 goto err;
176
177 dwc3->dev.parent = dev;
178 ACPI_COMPANION_SET(&dwc3->dev, ACPI_COMPANION(dev));
179
180 ret = platform_device_add(dwc3);
181 if (ret) {
182 dev_err(dev, "failed to register dwc3 device\n");
183 goto err;
184 }
185
186 return 0;
187err:
188 platform_device_put(dwc3);
189 return ret;
190}
191
192static void dwc3_pci_remove(struct pci_dev *pci)
193{
194 acpi_dev_remove_driver_gpios(ACPI_COMPANION(&pci->dev));
195 platform_device_unregister(pci_get_drvdata(pci));
196}
197
198static const struct pci_device_id dwc3_pci_id_table[] = {
199 {
200 PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS,
201 PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3),
202 },
203 {
204 PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS,
205 PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI),
206 },
207 {
208 PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS,
209 PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31),
210 },
211 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW), },
212 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT), },
213 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MRFLD), },
214 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SPTLP), },
215 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SPTH), },
216 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BXT), },
217 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BXT_M), },
218 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_APL), },
219 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB), },
220 { } /* Terminating Entry */
221};
222MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table);
223
224static struct pci_driver dwc3_pci_driver = {
225 .name = "dwc3-pci",
226 .id_table = dwc3_pci_id_table,
227 .probe = dwc3_pci_probe,
228 .remove = dwc3_pci_remove,
229};
230
231MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
232MODULE_LICENSE("GPL v2");
233MODULE_DESCRIPTION("DesignWare USB3 PCI Glue Layer");
234
235module_pci_driver(dwc3_pci_driver);
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dwc3-pci.c - PCI Specific glue layer
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/slab.h>
14#include <linux/pci.h>
15#include <linux/workqueue.h>
16#include <linux/pm_runtime.h>
17#include <linux/platform_device.h>
18#include <linux/gpio/consumer.h>
19#include <linux/gpio/machine.h>
20#include <linux/acpi.h>
21#include <linux/delay.h>
22
23#define PCI_DEVICE_ID_INTEL_BYT 0x0f37
24#define PCI_DEVICE_ID_INTEL_MRFLD 0x119e
25#define PCI_DEVICE_ID_INTEL_BSW 0x22b7
26#define PCI_DEVICE_ID_INTEL_SPTLP 0x9d30
27#define PCI_DEVICE_ID_INTEL_SPTH 0xa130
28#define PCI_DEVICE_ID_INTEL_BXT 0x0aaa
29#define PCI_DEVICE_ID_INTEL_BXT_M 0x1aaa
30#define PCI_DEVICE_ID_INTEL_APL 0x5aaa
31#define PCI_DEVICE_ID_INTEL_KBP 0xa2b0
32#define PCI_DEVICE_ID_INTEL_CMLLP 0x02ee
33#define PCI_DEVICE_ID_INTEL_CMLH 0x06ee
34#define PCI_DEVICE_ID_INTEL_GLK 0x31aa
35#define PCI_DEVICE_ID_INTEL_CNPLP 0x9dee
36#define PCI_DEVICE_ID_INTEL_CNPH 0xa36e
37#define PCI_DEVICE_ID_INTEL_CNPV 0xa3b0
38#define PCI_DEVICE_ID_INTEL_ICLLP 0x34ee
39#define PCI_DEVICE_ID_INTEL_EHL 0x4b7e
40#define PCI_DEVICE_ID_INTEL_TGPLP 0xa0ee
41#define PCI_DEVICE_ID_INTEL_TGPH 0x43ee
42#define PCI_DEVICE_ID_INTEL_JSP 0x4dee
43#define PCI_DEVICE_ID_INTEL_ADLP 0x51ee
44#define PCI_DEVICE_ID_INTEL_ADLM 0x54ee
45#define PCI_DEVICE_ID_INTEL_ADLS 0x7ae1
46#define PCI_DEVICE_ID_INTEL_TGL 0x9a15
47
48#define PCI_INTEL_BXT_DSM_GUID "732b85d5-b7a7-4a1b-9ba0-4bbd00ffd511"
49#define PCI_INTEL_BXT_FUNC_PMU_PWR 4
50#define PCI_INTEL_BXT_STATE_D0 0
51#define PCI_INTEL_BXT_STATE_D3 3
52
53#define GP_RWBAR 1
54#define GP_RWREG1 0xa0
55#define GP_RWREG1_ULPI_REFCLK_DISABLE (1 << 17)
56
57/**
58 * struct dwc3_pci - Driver private structure
59 * @dwc3: child dwc3 platform_device
60 * @pci: our link to PCI bus
61 * @guid: _DSM GUID
62 * @has_dsm_for_pm: true for devices which need to run _DSM on runtime PM
63 * @wakeup_work: work for asynchronous resume
64 */
65struct dwc3_pci {
66 struct platform_device *dwc3;
67 struct pci_dev *pci;
68
69 guid_t guid;
70
71 unsigned int has_dsm_for_pm:1;
72 struct work_struct wakeup_work;
73};
74
75static const struct acpi_gpio_params reset_gpios = { 0, 0, false };
76static const struct acpi_gpio_params cs_gpios = { 1, 0, false };
77
78static const struct acpi_gpio_mapping acpi_dwc3_byt_gpios[] = {
79 { "reset-gpios", &reset_gpios, 1 },
80 { "cs-gpios", &cs_gpios, 1 },
81 { },
82};
83
84static struct gpiod_lookup_table platform_bytcr_gpios = {
85 .dev_id = "0000:00:16.0",
86 .table = {
87 GPIO_LOOKUP("INT33FC:00", 54, "reset", GPIO_ACTIVE_HIGH),
88 GPIO_LOOKUP("INT33FC:02", 14, "cs", GPIO_ACTIVE_HIGH),
89 {}
90 },
91};
92
93static int dwc3_byt_enable_ulpi_refclock(struct pci_dev *pci)
94{
95 void __iomem *reg;
96 u32 value;
97
98 reg = pcim_iomap(pci, GP_RWBAR, 0);
99 if (!reg)
100 return -ENOMEM;
101
102 value = readl(reg + GP_RWREG1);
103 if (!(value & GP_RWREG1_ULPI_REFCLK_DISABLE))
104 goto unmap; /* ULPI refclk already enabled */
105
106 value &= ~GP_RWREG1_ULPI_REFCLK_DISABLE;
107 writel(value, reg + GP_RWREG1);
108 /* This comes from the Intel Android x86 tree w/o any explanation */
109 msleep(100);
110unmap:
111 pcim_iounmap(pci, reg);
112 return 0;
113}
114
115static const struct property_entry dwc3_pci_intel_properties[] = {
116 PROPERTY_ENTRY_STRING("dr_mode", "peripheral"),
117 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
118 {}
119};
120
121static const struct property_entry dwc3_pci_mrfld_properties[] = {
122 PROPERTY_ENTRY_STRING("dr_mode", "otg"),
123 PROPERTY_ENTRY_STRING("linux,extcon-name", "mrfld_bcove_pwrsrc"),
124 PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"),
125 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
126 PROPERTY_ENTRY_BOOL("snps,usb2-gadget-lpm-disable"),
127 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
128 {}
129};
130
131static const struct property_entry dwc3_pci_amd_properties[] = {
132 PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"),
133 PROPERTY_ENTRY_U8("snps,lpm-nyet-threshold", 0xf),
134 PROPERTY_ENTRY_BOOL("snps,u2exit_lfps_quirk"),
135 PROPERTY_ENTRY_BOOL("snps,u2ss_inp3_quirk"),
136 PROPERTY_ENTRY_BOOL("snps,req_p1p2p3_quirk"),
137 PROPERTY_ENTRY_BOOL("snps,del_p1p2p3_quirk"),
138 PROPERTY_ENTRY_BOOL("snps,del_phy_power_chg_quirk"),
139 PROPERTY_ENTRY_BOOL("snps,lfps_filter_quirk"),
140 PROPERTY_ENTRY_BOOL("snps,rx_detect_poll_quirk"),
141 PROPERTY_ENTRY_BOOL("snps,tx_de_emphasis_quirk"),
142 PROPERTY_ENTRY_U8("snps,tx_de_emphasis", 1),
143 /* FIXME these quirks should be removed when AMD NL tapes out */
144 PROPERTY_ENTRY_BOOL("snps,disable_scramble_quirk"),
145 PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"),
146 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
147 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
148 {}
149};
150
151static const struct software_node dwc3_pci_intel_swnode = {
152 .properties = dwc3_pci_intel_properties,
153};
154
155static const struct software_node dwc3_pci_intel_mrfld_swnode = {
156 .properties = dwc3_pci_mrfld_properties,
157};
158
159static const struct software_node dwc3_pci_amd_swnode = {
160 .properties = dwc3_pci_amd_properties,
161};
162
163static int dwc3_pci_quirks(struct dwc3_pci *dwc)
164{
165 struct pci_dev *pdev = dwc->pci;
166
167 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
168 if (pdev->device == PCI_DEVICE_ID_INTEL_BXT ||
169 pdev->device == PCI_DEVICE_ID_INTEL_BXT_M ||
170 pdev->device == PCI_DEVICE_ID_INTEL_EHL) {
171 guid_parse(PCI_INTEL_BXT_DSM_GUID, &dwc->guid);
172 dwc->has_dsm_for_pm = true;
173 }
174
175 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) {
176 struct gpio_desc *gpio;
177 int ret;
178
179 /* On BYT the FW does not always enable the refclock */
180 ret = dwc3_byt_enable_ulpi_refclock(pdev);
181 if (ret)
182 return ret;
183
184 ret = devm_acpi_dev_add_driver_gpios(&pdev->dev,
185 acpi_dwc3_byt_gpios);
186 if (ret)
187 dev_dbg(&pdev->dev, "failed to add mapping table\n");
188
189 /*
190 * A lot of BYT devices lack ACPI resource entries for
191 * the GPIOs, add a fallback mapping to the reference
192 * design GPIOs which all boards seem to use.
193 */
194 gpiod_add_lookup_table(&platform_bytcr_gpios);
195
196 /*
197 * These GPIOs will turn on the USB2 PHY. Note that we have to
198 * put the gpio descriptors again here because the phy driver
199 * might want to grab them, too.
200 */
201 gpio = gpiod_get_optional(&pdev->dev, "cs", GPIOD_OUT_LOW);
202 if (IS_ERR(gpio))
203 return PTR_ERR(gpio);
204
205 gpiod_set_value_cansleep(gpio, 1);
206 gpiod_put(gpio);
207
208 gpio = gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW);
209 if (IS_ERR(gpio))
210 return PTR_ERR(gpio);
211
212 if (gpio) {
213 gpiod_set_value_cansleep(gpio, 1);
214 gpiod_put(gpio);
215 usleep_range(10000, 11000);
216 }
217 }
218 }
219
220 return 0;
221}
222
223#ifdef CONFIG_PM
224static void dwc3_pci_resume_work(struct work_struct *work)
225{
226 struct dwc3_pci *dwc = container_of(work, struct dwc3_pci, wakeup_work);
227 struct platform_device *dwc3 = dwc->dwc3;
228 int ret;
229
230 ret = pm_runtime_get_sync(&dwc3->dev);
231 if (ret) {
232 pm_runtime_put_sync_autosuspend(&dwc3->dev);
233 return;
234 }
235
236 pm_runtime_mark_last_busy(&dwc3->dev);
237 pm_runtime_put_sync_autosuspend(&dwc3->dev);
238}
239#endif
240
241static int dwc3_pci_probe(struct pci_dev *pci, const struct pci_device_id *id)
242{
243 struct dwc3_pci *dwc;
244 struct resource res[2];
245 int ret;
246 struct device *dev = &pci->dev;
247
248 ret = pcim_enable_device(pci);
249 if (ret) {
250 dev_err(dev, "failed to enable pci device\n");
251 return -ENODEV;
252 }
253
254 pci_set_master(pci);
255
256 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
257 if (!dwc)
258 return -ENOMEM;
259
260 dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO);
261 if (!dwc->dwc3)
262 return -ENOMEM;
263
264 memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res));
265
266 res[0].start = pci_resource_start(pci, 0);
267 res[0].end = pci_resource_end(pci, 0);
268 res[0].name = "dwc_usb3";
269 res[0].flags = IORESOURCE_MEM;
270
271 res[1].start = pci->irq;
272 res[1].name = "dwc_usb3";
273 res[1].flags = IORESOURCE_IRQ;
274
275 ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res));
276 if (ret) {
277 dev_err(dev, "couldn't add resources to dwc3 device\n");
278 goto err;
279 }
280
281 dwc->pci = pci;
282 dwc->dwc3->dev.parent = dev;
283 ACPI_COMPANION_SET(&dwc->dwc3->dev, ACPI_COMPANION(dev));
284
285 ret = device_add_software_node(&dwc->dwc3->dev, (void *)id->driver_data);
286 if (ret < 0)
287 goto err;
288
289 ret = dwc3_pci_quirks(dwc);
290 if (ret)
291 goto err;
292
293 ret = platform_device_add(dwc->dwc3);
294 if (ret) {
295 dev_err(dev, "failed to register dwc3 device\n");
296 goto err;
297 }
298
299 device_init_wakeup(dev, true);
300 pci_set_drvdata(pci, dwc);
301 pm_runtime_put(dev);
302#ifdef CONFIG_PM
303 INIT_WORK(&dwc->wakeup_work, dwc3_pci_resume_work);
304#endif
305
306 return 0;
307err:
308 device_remove_software_node(&dwc->dwc3->dev);
309 platform_device_put(dwc->dwc3);
310 return ret;
311}
312
313static void dwc3_pci_remove(struct pci_dev *pci)
314{
315 struct dwc3_pci *dwc = pci_get_drvdata(pci);
316 struct pci_dev *pdev = dwc->pci;
317
318 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT)
319 gpiod_remove_lookup_table(&platform_bytcr_gpios);
320#ifdef CONFIG_PM
321 cancel_work_sync(&dwc->wakeup_work);
322#endif
323 device_init_wakeup(&pci->dev, false);
324 pm_runtime_get(&pci->dev);
325 device_remove_software_node(&dwc->dwc3->dev);
326 platform_device_unregister(dwc->dwc3);
327}
328
329static const struct pci_device_id dwc3_pci_id_table[] = {
330 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BSW),
331 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
332
333 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BYT),
334 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
335
336 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MRFLD),
337 (kernel_ulong_t) &dwc3_pci_intel_mrfld_swnode, },
338
339 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLLP),
340 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
341
342 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLH),
343 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
344
345 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTLP),
346 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
347
348 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTH),
349 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
350
351 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT),
352 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
353
354 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT_M),
355 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
356
357 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_APL),
358 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
359
360 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_KBP),
361 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
362
363 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_GLK),
364 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
365
366 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPLP),
367 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
368
369 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPH),
370 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
371
372 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPV),
373 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
374
375 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICLLP),
376 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
377
378 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_EHL),
379 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
380
381 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGPLP),
382 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
383
384 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGPH),
385 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
386
387 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_JSP),
388 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
389
390 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLP),
391 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
392
393 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLM),
394 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
395
396 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLS),
397 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
398
399 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL),
400 (kernel_ulong_t) &dwc3_pci_intel_swnode, },
401
402 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_NL_USB),
403 (kernel_ulong_t) &dwc3_pci_amd_swnode, },
404 { } /* Terminating Entry */
405};
406MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table);
407
408#if defined(CONFIG_PM) || defined(CONFIG_PM_SLEEP)
409static int dwc3_pci_dsm(struct dwc3_pci *dwc, int param)
410{
411 union acpi_object *obj;
412 union acpi_object tmp;
413 union acpi_object argv4 = ACPI_INIT_DSM_ARGV4(1, &tmp);
414
415 if (!dwc->has_dsm_for_pm)
416 return 0;
417
418 tmp.type = ACPI_TYPE_INTEGER;
419 tmp.integer.value = param;
420
421 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dwc->pci->dev), &dwc->guid,
422 1, PCI_INTEL_BXT_FUNC_PMU_PWR, &argv4);
423 if (!obj) {
424 dev_err(&dwc->pci->dev, "failed to evaluate _DSM\n");
425 return -EIO;
426 }
427
428 ACPI_FREE(obj);
429
430 return 0;
431}
432#endif /* CONFIG_PM || CONFIG_PM_SLEEP */
433
434#ifdef CONFIG_PM
435static int dwc3_pci_runtime_suspend(struct device *dev)
436{
437 struct dwc3_pci *dwc = dev_get_drvdata(dev);
438
439 if (device_can_wakeup(dev))
440 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
441
442 return -EBUSY;
443}
444
445static int dwc3_pci_runtime_resume(struct device *dev)
446{
447 struct dwc3_pci *dwc = dev_get_drvdata(dev);
448 int ret;
449
450 ret = dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
451 if (ret)
452 return ret;
453
454 queue_work(pm_wq, &dwc->wakeup_work);
455
456 return 0;
457}
458#endif /* CONFIG_PM */
459
460#ifdef CONFIG_PM_SLEEP
461static int dwc3_pci_suspend(struct device *dev)
462{
463 struct dwc3_pci *dwc = dev_get_drvdata(dev);
464
465 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
466}
467
468static int dwc3_pci_resume(struct device *dev)
469{
470 struct dwc3_pci *dwc = dev_get_drvdata(dev);
471
472 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
473}
474#endif /* CONFIG_PM_SLEEP */
475
476static const struct dev_pm_ops dwc3_pci_dev_pm_ops = {
477 SET_SYSTEM_SLEEP_PM_OPS(dwc3_pci_suspend, dwc3_pci_resume)
478 SET_RUNTIME_PM_OPS(dwc3_pci_runtime_suspend, dwc3_pci_runtime_resume,
479 NULL)
480};
481
482static struct pci_driver dwc3_pci_driver = {
483 .name = "dwc3-pci",
484 .id_table = dwc3_pci_id_table,
485 .probe = dwc3_pci_probe,
486 .remove = dwc3_pci_remove,
487 .driver = {
488 .pm = &dwc3_pci_dev_pm_ops,
489 }
490};
491
492MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
493MODULE_LICENSE("GPL v2");
494MODULE_DESCRIPTION("DesignWare USB3 PCI Glue Layer");
495
496module_pci_driver(dwc3_pci_driver);