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1/**
2 * dwc3-pci.c - PCI Specific glue layer
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/slab.h>
22#include <linux/pci.h>
23#include <linux/platform_device.h>
24#include <linux/gpio/consumer.h>
25#include <linux/acpi.h>
26
27#include "platform_data.h"
28
29#define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3 0xabcd
30#define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI 0xabce
31#define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31 0xabcf
32#define PCI_DEVICE_ID_INTEL_BYT 0x0f37
33#define PCI_DEVICE_ID_INTEL_MRFLD 0x119e
34#define PCI_DEVICE_ID_INTEL_BSW 0x22b7
35#define PCI_DEVICE_ID_INTEL_SPTLP 0x9d30
36#define PCI_DEVICE_ID_INTEL_SPTH 0xa130
37#define PCI_DEVICE_ID_INTEL_BXT 0x0aaa
38#define PCI_DEVICE_ID_INTEL_BXT_M 0x1aaa
39#define PCI_DEVICE_ID_INTEL_APL 0x5aaa
40
41static const struct acpi_gpio_params reset_gpios = { 0, 0, false };
42static const struct acpi_gpio_params cs_gpios = { 1, 0, false };
43
44static const struct acpi_gpio_mapping acpi_dwc3_byt_gpios[] = {
45 { "reset-gpios", &reset_gpios, 1 },
46 { "cs-gpios", &cs_gpios, 1 },
47 { },
48};
49
50static int dwc3_pci_quirks(struct pci_dev *pdev)
51{
52 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
53 pdev->device == PCI_DEVICE_ID_AMD_NL_USB) {
54 struct dwc3_platform_data pdata;
55
56 memset(&pdata, 0, sizeof(pdata));
57
58 pdata.has_lpm_erratum = true;
59 pdata.lpm_nyet_threshold = 0xf;
60
61 pdata.u2exit_lfps_quirk = true;
62 pdata.u2ss_inp3_quirk = true;
63 pdata.req_p1p2p3_quirk = true;
64 pdata.del_p1p2p3_quirk = true;
65 pdata.del_phy_power_chg_quirk = true;
66 pdata.lfps_filter_quirk = true;
67 pdata.rx_detect_poll_quirk = true;
68
69 pdata.tx_de_emphasis_quirk = true;
70 pdata.tx_de_emphasis = 1;
71
72 /*
73 * FIXME these quirks should be removed when AMD NL
74 * taps out
75 */
76 pdata.disable_scramble_quirk = true;
77 pdata.dis_u3_susphy_quirk = true;
78 pdata.dis_u2_susphy_quirk = true;
79
80 return platform_device_add_data(pci_get_drvdata(pdev), &pdata,
81 sizeof(pdata));
82 }
83
84 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
85 pdev->device == PCI_DEVICE_ID_INTEL_BYT) {
86 struct gpio_desc *gpio;
87
88 acpi_dev_add_driver_gpios(ACPI_COMPANION(&pdev->dev),
89 acpi_dwc3_byt_gpios);
90
91 /*
92 * These GPIOs will turn on the USB2 PHY. Note that we have to
93 * put the gpio descriptors again here because the phy driver
94 * might want to grab them, too.
95 */
96 gpio = gpiod_get_optional(&pdev->dev, "cs", GPIOD_OUT_LOW);
97 if (IS_ERR(gpio))
98 return PTR_ERR(gpio);
99
100 gpiod_set_value_cansleep(gpio, 1);
101 gpiod_put(gpio);
102
103 gpio = gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW);
104 if (IS_ERR(gpio))
105 return PTR_ERR(gpio);
106
107 if (gpio) {
108 gpiod_set_value_cansleep(gpio, 1);
109 gpiod_put(gpio);
110 usleep_range(10000, 11000);
111 }
112 }
113
114 if (pdev->vendor == PCI_VENDOR_ID_SYNOPSYS &&
115 (pdev->device == PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3 ||
116 pdev->device == PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI ||
117 pdev->device == PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31)) {
118
119 struct dwc3_platform_data pdata;
120
121 memset(&pdata, 0, sizeof(pdata));
122 pdata.usb3_lpm_capable = true;
123 pdata.has_lpm_erratum = true;
124 pdata.dis_enblslpm_quirk = true;
125
126 return platform_device_add_data(pci_get_drvdata(pdev), &pdata,
127 sizeof(pdata));
128 }
129
130 return 0;
131}
132
133static int dwc3_pci_probe(struct pci_dev *pci,
134 const struct pci_device_id *id)
135{
136 struct resource res[2];
137 struct platform_device *dwc3;
138 int ret;
139 struct device *dev = &pci->dev;
140
141 ret = pcim_enable_device(pci);
142 if (ret) {
143 dev_err(dev, "failed to enable pci device\n");
144 return -ENODEV;
145 }
146
147 pci_set_master(pci);
148
149 dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO);
150 if (!dwc3) {
151 dev_err(dev, "couldn't allocate dwc3 device\n");
152 return -ENOMEM;
153 }
154
155 memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res));
156
157 res[0].start = pci_resource_start(pci, 0);
158 res[0].end = pci_resource_end(pci, 0);
159 res[0].name = "dwc_usb3";
160 res[0].flags = IORESOURCE_MEM;
161
162 res[1].start = pci->irq;
163 res[1].name = "dwc_usb3";
164 res[1].flags = IORESOURCE_IRQ;
165
166 ret = platform_device_add_resources(dwc3, res, ARRAY_SIZE(res));
167 if (ret) {
168 dev_err(dev, "couldn't add resources to dwc3 device\n");
169 return ret;
170 }
171
172 pci_set_drvdata(pci, dwc3);
173 ret = dwc3_pci_quirks(pci);
174 if (ret)
175 goto err;
176
177 dwc3->dev.parent = dev;
178 ACPI_COMPANION_SET(&dwc3->dev, ACPI_COMPANION(dev));
179
180 ret = platform_device_add(dwc3);
181 if (ret) {
182 dev_err(dev, "failed to register dwc3 device\n");
183 goto err;
184 }
185
186 return 0;
187err:
188 platform_device_put(dwc3);
189 return ret;
190}
191
192static void dwc3_pci_remove(struct pci_dev *pci)
193{
194 acpi_dev_remove_driver_gpios(ACPI_COMPANION(&pci->dev));
195 platform_device_unregister(pci_get_drvdata(pci));
196}
197
198static const struct pci_device_id dwc3_pci_id_table[] = {
199 {
200 PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS,
201 PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3),
202 },
203 {
204 PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS,
205 PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI),
206 },
207 {
208 PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS,
209 PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31),
210 },
211 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW), },
212 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT), },
213 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MRFLD), },
214 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SPTLP), },
215 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SPTH), },
216 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BXT), },
217 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BXT_M), },
218 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_APL), },
219 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB), },
220 { } /* Terminating Entry */
221};
222MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table);
223
224static struct pci_driver dwc3_pci_driver = {
225 .name = "dwc3-pci",
226 .id_table = dwc3_pci_id_table,
227 .probe = dwc3_pci_probe,
228 .remove = dwc3_pci_remove,
229};
230
231MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
232MODULE_LICENSE("GPL v2");
233MODULE_DESCRIPTION("DesignWare USB3 PCI Glue Layer");
234
235module_pci_driver(dwc3_pci_driver);
1// SPDX-License-Identifier: GPL-2.0
2/**
3 * dwc3-pci.c - PCI Specific glue layer
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/slab.h>
14#include <linux/pci.h>
15#include <linux/workqueue.h>
16#include <linux/pm_runtime.h>
17#include <linux/platform_device.h>
18#include <linux/gpio/consumer.h>
19#include <linux/gpio/machine.h>
20#include <linux/acpi.h>
21#include <linux/delay.h>
22
23#define PCI_DEVICE_ID_INTEL_BYT 0x0f37
24#define PCI_DEVICE_ID_INTEL_MRFLD 0x119e
25#define PCI_DEVICE_ID_INTEL_BSW 0x22b7
26#define PCI_DEVICE_ID_INTEL_SPTLP 0x9d30
27#define PCI_DEVICE_ID_INTEL_SPTH 0xa130
28#define PCI_DEVICE_ID_INTEL_BXT 0x0aaa
29#define PCI_DEVICE_ID_INTEL_BXT_M 0x1aaa
30#define PCI_DEVICE_ID_INTEL_APL 0x5aaa
31#define PCI_DEVICE_ID_INTEL_KBP 0xa2b0
32#define PCI_DEVICE_ID_INTEL_CMLH 0x02ee
33#define PCI_DEVICE_ID_INTEL_GLK 0x31aa
34#define PCI_DEVICE_ID_INTEL_CNPLP 0x9dee
35#define PCI_DEVICE_ID_INTEL_CNPH 0xa36e
36#define PCI_DEVICE_ID_INTEL_ICLLP 0x34ee
37#define PCI_DEVICE_ID_INTEL_EHLLP 0x4b7e
38#define PCI_DEVICE_ID_INTEL_TGPLP 0xa0ee
39
40#define PCI_INTEL_BXT_DSM_GUID "732b85d5-b7a7-4a1b-9ba0-4bbd00ffd511"
41#define PCI_INTEL_BXT_FUNC_PMU_PWR 4
42#define PCI_INTEL_BXT_STATE_D0 0
43#define PCI_INTEL_BXT_STATE_D3 3
44
45#define GP_RWBAR 1
46#define GP_RWREG1 0xa0
47#define GP_RWREG1_ULPI_REFCLK_DISABLE (1 << 17)
48
49/**
50 * struct dwc3_pci - Driver private structure
51 * @dwc3: child dwc3 platform_device
52 * @pci: our link to PCI bus
53 * @guid: _DSM GUID
54 * @has_dsm_for_pm: true for devices which need to run _DSM on runtime PM
55 * @wakeup_work: work for asynchronous resume
56 */
57struct dwc3_pci {
58 struct platform_device *dwc3;
59 struct pci_dev *pci;
60
61 guid_t guid;
62
63 unsigned int has_dsm_for_pm:1;
64 struct work_struct wakeup_work;
65};
66
67static const struct acpi_gpio_params reset_gpios = { 0, 0, false };
68static const struct acpi_gpio_params cs_gpios = { 1, 0, false };
69
70static const struct acpi_gpio_mapping acpi_dwc3_byt_gpios[] = {
71 { "reset-gpios", &reset_gpios, 1 },
72 { "cs-gpios", &cs_gpios, 1 },
73 { },
74};
75
76static struct gpiod_lookup_table platform_bytcr_gpios = {
77 .dev_id = "0000:00:16.0",
78 .table = {
79 GPIO_LOOKUP("INT33FC:00", 54, "reset", GPIO_ACTIVE_HIGH),
80 GPIO_LOOKUP("INT33FC:02", 14, "cs", GPIO_ACTIVE_HIGH),
81 {}
82 },
83};
84
85static int dwc3_byt_enable_ulpi_refclock(struct pci_dev *pci)
86{
87 void __iomem *reg;
88 u32 value;
89
90 reg = pcim_iomap(pci, GP_RWBAR, 0);
91 if (!reg)
92 return -ENOMEM;
93
94 value = readl(reg + GP_RWREG1);
95 if (!(value & GP_RWREG1_ULPI_REFCLK_DISABLE))
96 goto unmap; /* ULPI refclk already enabled */
97
98 value &= ~GP_RWREG1_ULPI_REFCLK_DISABLE;
99 writel(value, reg + GP_RWREG1);
100 /* This comes from the Intel Android x86 tree w/o any explanation */
101 msleep(100);
102unmap:
103 pcim_iounmap(pci, reg);
104 return 0;
105}
106
107static const struct property_entry dwc3_pci_intel_properties[] = {
108 PROPERTY_ENTRY_STRING("dr_mode", "peripheral"),
109 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
110 {}
111};
112
113static const struct property_entry dwc3_pci_mrfld_properties[] = {
114 PROPERTY_ENTRY_STRING("dr_mode", "otg"),
115 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
116 {}
117};
118
119static const struct property_entry dwc3_pci_amd_properties[] = {
120 PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"),
121 PROPERTY_ENTRY_U8("snps,lpm-nyet-threshold", 0xf),
122 PROPERTY_ENTRY_BOOL("snps,u2exit_lfps_quirk"),
123 PROPERTY_ENTRY_BOOL("snps,u2ss_inp3_quirk"),
124 PROPERTY_ENTRY_BOOL("snps,req_p1p2p3_quirk"),
125 PROPERTY_ENTRY_BOOL("snps,del_p1p2p3_quirk"),
126 PROPERTY_ENTRY_BOOL("snps,del_phy_power_chg_quirk"),
127 PROPERTY_ENTRY_BOOL("snps,lfps_filter_quirk"),
128 PROPERTY_ENTRY_BOOL("snps,rx_detect_poll_quirk"),
129 PROPERTY_ENTRY_BOOL("snps,tx_de_emphasis_quirk"),
130 PROPERTY_ENTRY_U8("snps,tx_de_emphasis", 1),
131 /* FIXME these quirks should be removed when AMD NL tapes out */
132 PROPERTY_ENTRY_BOOL("snps,disable_scramble_quirk"),
133 PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"),
134 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
135 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
136 {}
137};
138
139static int dwc3_pci_quirks(struct dwc3_pci *dwc)
140{
141 struct pci_dev *pdev = dwc->pci;
142
143 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
144 if (pdev->device == PCI_DEVICE_ID_INTEL_BXT ||
145 pdev->device == PCI_DEVICE_ID_INTEL_BXT_M) {
146 guid_parse(PCI_INTEL_BXT_DSM_GUID, &dwc->guid);
147 dwc->has_dsm_for_pm = true;
148 }
149
150 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) {
151 struct gpio_desc *gpio;
152 int ret;
153
154 /* On BYT the FW does not always enable the refclock */
155 ret = dwc3_byt_enable_ulpi_refclock(pdev);
156 if (ret)
157 return ret;
158
159 ret = devm_acpi_dev_add_driver_gpios(&pdev->dev,
160 acpi_dwc3_byt_gpios);
161 if (ret)
162 dev_dbg(&pdev->dev, "failed to add mapping table\n");
163
164 /*
165 * A lot of BYT devices lack ACPI resource entries for
166 * the GPIOs, add a fallback mapping to the reference
167 * design GPIOs which all boards seem to use.
168 */
169 gpiod_add_lookup_table(&platform_bytcr_gpios);
170
171 /*
172 * These GPIOs will turn on the USB2 PHY. Note that we have to
173 * put the gpio descriptors again here because the phy driver
174 * might want to grab them, too.
175 */
176 gpio = gpiod_get_optional(&pdev->dev, "cs", GPIOD_OUT_LOW);
177 if (IS_ERR(gpio))
178 return PTR_ERR(gpio);
179
180 gpiod_set_value_cansleep(gpio, 1);
181 gpiod_put(gpio);
182
183 gpio = gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW);
184 if (IS_ERR(gpio))
185 return PTR_ERR(gpio);
186
187 if (gpio) {
188 gpiod_set_value_cansleep(gpio, 1);
189 gpiod_put(gpio);
190 usleep_range(10000, 11000);
191 }
192 }
193 }
194
195 return 0;
196}
197
198#ifdef CONFIG_PM
199static void dwc3_pci_resume_work(struct work_struct *work)
200{
201 struct dwc3_pci *dwc = container_of(work, struct dwc3_pci, wakeup_work);
202 struct platform_device *dwc3 = dwc->dwc3;
203 int ret;
204
205 ret = pm_runtime_get_sync(&dwc3->dev);
206 if (ret)
207 return;
208
209 pm_runtime_mark_last_busy(&dwc3->dev);
210 pm_runtime_put_sync_autosuspend(&dwc3->dev);
211}
212#endif
213
214static int dwc3_pci_probe(struct pci_dev *pci, const struct pci_device_id *id)
215{
216 struct property_entry *p = (struct property_entry *)id->driver_data;
217 struct dwc3_pci *dwc;
218 struct resource res[2];
219 int ret;
220 struct device *dev = &pci->dev;
221
222 ret = pcim_enable_device(pci);
223 if (ret) {
224 dev_err(dev, "failed to enable pci device\n");
225 return -ENODEV;
226 }
227
228 pci_set_master(pci);
229
230 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
231 if (!dwc)
232 return -ENOMEM;
233
234 dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO);
235 if (!dwc->dwc3)
236 return -ENOMEM;
237
238 memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res));
239
240 res[0].start = pci_resource_start(pci, 0);
241 res[0].end = pci_resource_end(pci, 0);
242 res[0].name = "dwc_usb3";
243 res[0].flags = IORESOURCE_MEM;
244
245 res[1].start = pci->irq;
246 res[1].name = "dwc_usb3";
247 res[1].flags = IORESOURCE_IRQ;
248
249 ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res));
250 if (ret) {
251 dev_err(dev, "couldn't add resources to dwc3 device\n");
252 goto err;
253 }
254
255 dwc->pci = pci;
256 dwc->dwc3->dev.parent = dev;
257 ACPI_COMPANION_SET(&dwc->dwc3->dev, ACPI_COMPANION(dev));
258
259 ret = platform_device_add_properties(dwc->dwc3, p);
260 if (ret < 0)
261 goto err;
262
263 ret = dwc3_pci_quirks(dwc);
264 if (ret)
265 goto err;
266
267 ret = platform_device_add(dwc->dwc3);
268 if (ret) {
269 dev_err(dev, "failed to register dwc3 device\n");
270 goto err;
271 }
272
273 device_init_wakeup(dev, true);
274 pci_set_drvdata(pci, dwc);
275 pm_runtime_put(dev);
276#ifdef CONFIG_PM
277 INIT_WORK(&dwc->wakeup_work, dwc3_pci_resume_work);
278#endif
279
280 return 0;
281err:
282 platform_device_put(dwc->dwc3);
283 return ret;
284}
285
286static void dwc3_pci_remove(struct pci_dev *pci)
287{
288 struct dwc3_pci *dwc = pci_get_drvdata(pci);
289 struct pci_dev *pdev = dwc->pci;
290
291 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT)
292 gpiod_remove_lookup_table(&platform_bytcr_gpios);
293#ifdef CONFIG_PM
294 cancel_work_sync(&dwc->wakeup_work);
295#endif
296 device_init_wakeup(&pci->dev, false);
297 pm_runtime_get(&pci->dev);
298 platform_device_unregister(dwc->dwc3);
299}
300
301static const struct pci_device_id dwc3_pci_id_table[] = {
302 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BSW),
303 (kernel_ulong_t) &dwc3_pci_intel_properties },
304
305 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BYT),
306 (kernel_ulong_t) &dwc3_pci_intel_properties, },
307
308 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MRFLD),
309 (kernel_ulong_t) &dwc3_pci_mrfld_properties, },
310
311 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLH),
312 (kernel_ulong_t) &dwc3_pci_intel_properties, },
313
314 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTLP),
315 (kernel_ulong_t) &dwc3_pci_intel_properties, },
316
317 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTH),
318 (kernel_ulong_t) &dwc3_pci_intel_properties, },
319
320 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT),
321 (kernel_ulong_t) &dwc3_pci_intel_properties, },
322
323 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT_M),
324 (kernel_ulong_t) &dwc3_pci_intel_properties, },
325
326 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_APL),
327 (kernel_ulong_t) &dwc3_pci_intel_properties, },
328
329 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_KBP),
330 (kernel_ulong_t) &dwc3_pci_intel_properties, },
331
332 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_GLK),
333 (kernel_ulong_t) &dwc3_pci_intel_properties, },
334
335 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPLP),
336 (kernel_ulong_t) &dwc3_pci_intel_properties, },
337
338 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPH),
339 (kernel_ulong_t) &dwc3_pci_intel_properties, },
340
341 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICLLP),
342 (kernel_ulong_t) &dwc3_pci_intel_properties, },
343
344 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_EHLLP),
345 (kernel_ulong_t) &dwc3_pci_intel_properties, },
346
347 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGPLP),
348 (kernel_ulong_t) &dwc3_pci_intel_properties, },
349
350 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_NL_USB),
351 (kernel_ulong_t) &dwc3_pci_amd_properties, },
352 { } /* Terminating Entry */
353};
354MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table);
355
356#if defined(CONFIG_PM) || defined(CONFIG_PM_SLEEP)
357static int dwc3_pci_dsm(struct dwc3_pci *dwc, int param)
358{
359 union acpi_object *obj;
360 union acpi_object tmp;
361 union acpi_object argv4 = ACPI_INIT_DSM_ARGV4(1, &tmp);
362
363 if (!dwc->has_dsm_for_pm)
364 return 0;
365
366 tmp.type = ACPI_TYPE_INTEGER;
367 tmp.integer.value = param;
368
369 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dwc->pci->dev), &dwc->guid,
370 1, PCI_INTEL_BXT_FUNC_PMU_PWR, &argv4);
371 if (!obj) {
372 dev_err(&dwc->pci->dev, "failed to evaluate _DSM\n");
373 return -EIO;
374 }
375
376 ACPI_FREE(obj);
377
378 return 0;
379}
380#endif /* CONFIG_PM || CONFIG_PM_SLEEP */
381
382#ifdef CONFIG_PM
383static int dwc3_pci_runtime_suspend(struct device *dev)
384{
385 struct dwc3_pci *dwc = dev_get_drvdata(dev);
386
387 if (device_can_wakeup(dev))
388 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
389
390 return -EBUSY;
391}
392
393static int dwc3_pci_runtime_resume(struct device *dev)
394{
395 struct dwc3_pci *dwc = dev_get_drvdata(dev);
396 int ret;
397
398 ret = dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
399 if (ret)
400 return ret;
401
402 queue_work(pm_wq, &dwc->wakeup_work);
403
404 return 0;
405}
406#endif /* CONFIG_PM */
407
408#ifdef CONFIG_PM_SLEEP
409static int dwc3_pci_suspend(struct device *dev)
410{
411 struct dwc3_pci *dwc = dev_get_drvdata(dev);
412
413 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
414}
415
416static int dwc3_pci_resume(struct device *dev)
417{
418 struct dwc3_pci *dwc = dev_get_drvdata(dev);
419
420 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
421}
422#endif /* CONFIG_PM_SLEEP */
423
424static const struct dev_pm_ops dwc3_pci_dev_pm_ops = {
425 SET_SYSTEM_SLEEP_PM_OPS(dwc3_pci_suspend, dwc3_pci_resume)
426 SET_RUNTIME_PM_OPS(dwc3_pci_runtime_suspend, dwc3_pci_runtime_resume,
427 NULL)
428};
429
430static struct pci_driver dwc3_pci_driver = {
431 .name = "dwc3-pci",
432 .id_table = dwc3_pci_id_table,
433 .probe = dwc3_pci_probe,
434 .remove = dwc3_pci_remove,
435 .driver = {
436 .pm = &dwc3_pci_dev_pm_ops,
437 }
438};
439
440MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
441MODULE_LICENSE("GPL v2");
442MODULE_DESCRIPTION("DesignWare USB3 PCI Glue Layer");
443
444module_pci_driver(dwc3_pci_driver);