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1/*
2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#include "hdmi.h"
19
20struct hdmi_bridge {
21 struct drm_bridge base;
22 struct hdmi *hdmi;
23};
24#define to_hdmi_bridge(x) container_of(x, struct hdmi_bridge, base)
25
26void msm_hdmi_bridge_destroy(struct drm_bridge *bridge)
27{
28}
29
30static void msm_hdmi_power_on(struct drm_bridge *bridge)
31{
32 struct drm_device *dev = bridge->dev;
33 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
34 struct hdmi *hdmi = hdmi_bridge->hdmi;
35 const struct hdmi_platform_config *config = hdmi->config;
36 int i, ret;
37
38 for (i = 0; i < config->pwr_reg_cnt; i++) {
39 ret = regulator_enable(hdmi->pwr_regs[i]);
40 if (ret) {
41 dev_err(dev->dev, "failed to enable pwr regulator: %s (%d)\n",
42 config->pwr_reg_names[i], ret);
43 }
44 }
45
46 if (config->pwr_clk_cnt > 0) {
47 DBG("pixclock: %lu", hdmi->pixclock);
48 ret = clk_set_rate(hdmi->pwr_clks[0], hdmi->pixclock);
49 if (ret) {
50 dev_err(dev->dev, "failed to set pixel clk: %s (%d)\n",
51 config->pwr_clk_names[0], ret);
52 }
53 }
54
55 for (i = 0; i < config->pwr_clk_cnt; i++) {
56 ret = clk_prepare_enable(hdmi->pwr_clks[i]);
57 if (ret) {
58 dev_err(dev->dev, "failed to enable pwr clk: %s (%d)\n",
59 config->pwr_clk_names[i], ret);
60 }
61 }
62}
63
64static void power_off(struct drm_bridge *bridge)
65{
66 struct drm_device *dev = bridge->dev;
67 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
68 struct hdmi *hdmi = hdmi_bridge->hdmi;
69 const struct hdmi_platform_config *config = hdmi->config;
70 int i, ret;
71
72 /* TODO do we need to wait for final vblank somewhere before
73 * cutting the clocks?
74 */
75 mdelay(16 + 4);
76
77 for (i = 0; i < config->pwr_clk_cnt; i++)
78 clk_disable_unprepare(hdmi->pwr_clks[i]);
79
80 for (i = 0; i < config->pwr_reg_cnt; i++) {
81 ret = regulator_disable(hdmi->pwr_regs[i]);
82 if (ret) {
83 dev_err(dev->dev, "failed to disable pwr regulator: %s (%d)\n",
84 config->pwr_reg_names[i], ret);
85 }
86 }
87}
88
89static void msm_hdmi_bridge_pre_enable(struct drm_bridge *bridge)
90{
91 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
92 struct hdmi *hdmi = hdmi_bridge->hdmi;
93 struct hdmi_phy *phy = hdmi->phy;
94
95 DBG("power up");
96
97 if (!hdmi->power_on) {
98 msm_hdmi_phy_resource_enable(phy);
99 msm_hdmi_power_on(bridge);
100 hdmi->power_on = true;
101 msm_hdmi_audio_update(hdmi);
102 }
103
104 msm_hdmi_phy_powerup(phy, hdmi->pixclock);
105
106 msm_hdmi_set_mode(hdmi, true);
107
108 if (hdmi->hdcp_ctrl)
109 msm_hdmi_hdcp_on(hdmi->hdcp_ctrl);
110}
111
112static void msm_hdmi_bridge_enable(struct drm_bridge *bridge)
113{
114}
115
116static void msm_hdmi_bridge_disable(struct drm_bridge *bridge)
117{
118}
119
120static void msm_hdmi_bridge_post_disable(struct drm_bridge *bridge)
121{
122 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
123 struct hdmi *hdmi = hdmi_bridge->hdmi;
124 struct hdmi_phy *phy = hdmi->phy;
125
126 if (hdmi->hdcp_ctrl)
127 msm_hdmi_hdcp_off(hdmi->hdcp_ctrl);
128
129 DBG("power down");
130 msm_hdmi_set_mode(hdmi, false);
131
132 msm_hdmi_phy_powerdown(phy);
133
134 if (hdmi->power_on) {
135 power_off(bridge);
136 hdmi->power_on = false;
137 msm_hdmi_audio_update(hdmi);
138 msm_hdmi_phy_resource_disable(phy);
139 }
140}
141
142static void msm_hdmi_bridge_mode_set(struct drm_bridge *bridge,
143 struct drm_display_mode *mode,
144 struct drm_display_mode *adjusted_mode)
145{
146 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
147 struct hdmi *hdmi = hdmi_bridge->hdmi;
148 int hstart, hend, vstart, vend;
149 uint32_t frame_ctrl;
150
151 mode = adjusted_mode;
152
153 hdmi->pixclock = mode->clock * 1000;
154
155 hstart = mode->htotal - mode->hsync_start;
156 hend = mode->htotal - mode->hsync_start + mode->hdisplay;
157
158 vstart = mode->vtotal - mode->vsync_start - 1;
159 vend = mode->vtotal - mode->vsync_start + mode->vdisplay - 1;
160
161 DBG("htotal=%d, vtotal=%d, hstart=%d, hend=%d, vstart=%d, vend=%d",
162 mode->htotal, mode->vtotal, hstart, hend, vstart, vend);
163
164 hdmi_write(hdmi, REG_HDMI_TOTAL,
165 HDMI_TOTAL_H_TOTAL(mode->htotal - 1) |
166 HDMI_TOTAL_V_TOTAL(mode->vtotal - 1));
167
168 hdmi_write(hdmi, REG_HDMI_ACTIVE_HSYNC,
169 HDMI_ACTIVE_HSYNC_START(hstart) |
170 HDMI_ACTIVE_HSYNC_END(hend));
171 hdmi_write(hdmi, REG_HDMI_ACTIVE_VSYNC,
172 HDMI_ACTIVE_VSYNC_START(vstart) |
173 HDMI_ACTIVE_VSYNC_END(vend));
174
175 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
176 hdmi_write(hdmi, REG_HDMI_VSYNC_TOTAL_F2,
177 HDMI_VSYNC_TOTAL_F2_V_TOTAL(mode->vtotal));
178 hdmi_write(hdmi, REG_HDMI_VSYNC_ACTIVE_F2,
179 HDMI_VSYNC_ACTIVE_F2_START(vstart + 1) |
180 HDMI_VSYNC_ACTIVE_F2_END(vend + 1));
181 } else {
182 hdmi_write(hdmi, REG_HDMI_VSYNC_TOTAL_F2,
183 HDMI_VSYNC_TOTAL_F2_V_TOTAL(0));
184 hdmi_write(hdmi, REG_HDMI_VSYNC_ACTIVE_F2,
185 HDMI_VSYNC_ACTIVE_F2_START(0) |
186 HDMI_VSYNC_ACTIVE_F2_END(0));
187 }
188
189 frame_ctrl = 0;
190 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
191 frame_ctrl |= HDMI_FRAME_CTRL_HSYNC_LOW;
192 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
193 frame_ctrl |= HDMI_FRAME_CTRL_VSYNC_LOW;
194 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
195 frame_ctrl |= HDMI_FRAME_CTRL_INTERLACED_EN;
196 DBG("frame_ctrl=%08x", frame_ctrl);
197 hdmi_write(hdmi, REG_HDMI_FRAME_CTRL, frame_ctrl);
198
199 msm_hdmi_audio_update(hdmi);
200}
201
202static const struct drm_bridge_funcs msm_hdmi_bridge_funcs = {
203 .pre_enable = msm_hdmi_bridge_pre_enable,
204 .enable = msm_hdmi_bridge_enable,
205 .disable = msm_hdmi_bridge_disable,
206 .post_disable = msm_hdmi_bridge_post_disable,
207 .mode_set = msm_hdmi_bridge_mode_set,
208};
209
210
211/* initialize bridge */
212struct drm_bridge *msm_hdmi_bridge_init(struct hdmi *hdmi)
213{
214 struct drm_bridge *bridge = NULL;
215 struct hdmi_bridge *hdmi_bridge;
216 int ret;
217
218 hdmi_bridge = devm_kzalloc(hdmi->dev->dev,
219 sizeof(*hdmi_bridge), GFP_KERNEL);
220 if (!hdmi_bridge) {
221 ret = -ENOMEM;
222 goto fail;
223 }
224
225 hdmi_bridge->hdmi = hdmi;
226
227 bridge = &hdmi_bridge->base;
228 bridge->funcs = &msm_hdmi_bridge_funcs;
229
230 ret = drm_bridge_attach(hdmi->dev, bridge);
231 if (ret)
232 goto fail;
233
234 return bridge;
235
236fail:
237 if (bridge)
238 msm_hdmi_bridge_destroy(bridge);
239
240 return ERR_PTR(ret);
241}
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
5 */
6
7#include <linux/delay.h>
8
9#include "hdmi.h"
10
11struct hdmi_bridge {
12 struct drm_bridge base;
13 struct hdmi *hdmi;
14};
15#define to_hdmi_bridge(x) container_of(x, struct hdmi_bridge, base)
16
17void msm_hdmi_bridge_destroy(struct drm_bridge *bridge)
18{
19}
20
21static void msm_hdmi_power_on(struct drm_bridge *bridge)
22{
23 struct drm_device *dev = bridge->dev;
24 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
25 struct hdmi *hdmi = hdmi_bridge->hdmi;
26 const struct hdmi_platform_config *config = hdmi->config;
27 int i, ret;
28
29 pm_runtime_get_sync(&hdmi->pdev->dev);
30
31 for (i = 0; i < config->pwr_reg_cnt; i++) {
32 ret = regulator_enable(hdmi->pwr_regs[i]);
33 if (ret) {
34 DRM_DEV_ERROR(dev->dev, "failed to enable pwr regulator: %s (%d)\n",
35 config->pwr_reg_names[i], ret);
36 }
37 }
38
39 if (config->pwr_clk_cnt > 0) {
40 DBG("pixclock: %lu", hdmi->pixclock);
41 ret = clk_set_rate(hdmi->pwr_clks[0], hdmi->pixclock);
42 if (ret) {
43 DRM_DEV_ERROR(dev->dev, "failed to set pixel clk: %s (%d)\n",
44 config->pwr_clk_names[0], ret);
45 }
46 }
47
48 for (i = 0; i < config->pwr_clk_cnt; i++) {
49 ret = clk_prepare_enable(hdmi->pwr_clks[i]);
50 if (ret) {
51 DRM_DEV_ERROR(dev->dev, "failed to enable pwr clk: %s (%d)\n",
52 config->pwr_clk_names[i], ret);
53 }
54 }
55}
56
57static void power_off(struct drm_bridge *bridge)
58{
59 struct drm_device *dev = bridge->dev;
60 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
61 struct hdmi *hdmi = hdmi_bridge->hdmi;
62 const struct hdmi_platform_config *config = hdmi->config;
63 int i, ret;
64
65 /* TODO do we need to wait for final vblank somewhere before
66 * cutting the clocks?
67 */
68 mdelay(16 + 4);
69
70 for (i = 0; i < config->pwr_clk_cnt; i++)
71 clk_disable_unprepare(hdmi->pwr_clks[i]);
72
73 for (i = 0; i < config->pwr_reg_cnt; i++) {
74 ret = regulator_disable(hdmi->pwr_regs[i]);
75 if (ret) {
76 DRM_DEV_ERROR(dev->dev, "failed to disable pwr regulator: %s (%d)\n",
77 config->pwr_reg_names[i], ret);
78 }
79 }
80
81 pm_runtime_put_autosuspend(&hdmi->pdev->dev);
82}
83
84#define AVI_IFRAME_LINE_NUMBER 1
85
86static void msm_hdmi_config_avi_infoframe(struct hdmi *hdmi)
87{
88 struct drm_crtc *crtc = hdmi->encoder->crtc;
89 const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
90 union hdmi_infoframe frame;
91 u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
92 u32 val;
93 int len;
94
95 drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
96 hdmi->connector, mode);
97
98 len = hdmi_infoframe_pack(&frame, buffer, sizeof(buffer));
99 if (len < 0) {
100 DRM_DEV_ERROR(&hdmi->pdev->dev,
101 "failed to configure avi infoframe\n");
102 return;
103 }
104
105 /*
106 * the AVI_INFOx registers don't map exactly to how the AVI infoframes
107 * are packed according to the spec. The checksum from the header is
108 * written to the LSB byte of AVI_INFO0 and the version is written to
109 * the third byte from the LSB of AVI_INFO3
110 */
111 hdmi_write(hdmi, REG_HDMI_AVI_INFO(0),
112 buffer[3] |
113 buffer[4] << 8 |
114 buffer[5] << 16 |
115 buffer[6] << 24);
116
117 hdmi_write(hdmi, REG_HDMI_AVI_INFO(1),
118 buffer[7] |
119 buffer[8] << 8 |
120 buffer[9] << 16 |
121 buffer[10] << 24);
122
123 hdmi_write(hdmi, REG_HDMI_AVI_INFO(2),
124 buffer[11] |
125 buffer[12] << 8 |
126 buffer[13] << 16 |
127 buffer[14] << 24);
128
129 hdmi_write(hdmi, REG_HDMI_AVI_INFO(3),
130 buffer[15] |
131 buffer[16] << 8 |
132 buffer[1] << 24);
133
134 hdmi_write(hdmi, REG_HDMI_INFOFRAME_CTRL0,
135 HDMI_INFOFRAME_CTRL0_AVI_SEND |
136 HDMI_INFOFRAME_CTRL0_AVI_CONT);
137
138 val = hdmi_read(hdmi, REG_HDMI_INFOFRAME_CTRL1);
139 val &= ~HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__MASK;
140 val |= HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE(AVI_IFRAME_LINE_NUMBER);
141 hdmi_write(hdmi, REG_HDMI_INFOFRAME_CTRL1, val);
142}
143
144static void msm_hdmi_bridge_pre_enable(struct drm_bridge *bridge)
145{
146 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
147 struct hdmi *hdmi = hdmi_bridge->hdmi;
148 struct hdmi_phy *phy = hdmi->phy;
149
150 DBG("power up");
151
152 if (!hdmi->power_on) {
153 msm_hdmi_phy_resource_enable(phy);
154 msm_hdmi_power_on(bridge);
155 hdmi->power_on = true;
156 if (hdmi->hdmi_mode) {
157 msm_hdmi_config_avi_infoframe(hdmi);
158 msm_hdmi_audio_update(hdmi);
159 }
160 }
161
162 msm_hdmi_phy_powerup(phy, hdmi->pixclock);
163
164 msm_hdmi_set_mode(hdmi, true);
165
166 if (hdmi->hdcp_ctrl)
167 msm_hdmi_hdcp_on(hdmi->hdcp_ctrl);
168}
169
170static void msm_hdmi_bridge_enable(struct drm_bridge *bridge)
171{
172}
173
174static void msm_hdmi_bridge_disable(struct drm_bridge *bridge)
175{
176}
177
178static void msm_hdmi_bridge_post_disable(struct drm_bridge *bridge)
179{
180 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
181 struct hdmi *hdmi = hdmi_bridge->hdmi;
182 struct hdmi_phy *phy = hdmi->phy;
183
184 if (hdmi->hdcp_ctrl)
185 msm_hdmi_hdcp_off(hdmi->hdcp_ctrl);
186
187 DBG("power down");
188 msm_hdmi_set_mode(hdmi, false);
189
190 msm_hdmi_phy_powerdown(phy);
191
192 if (hdmi->power_on) {
193 power_off(bridge);
194 hdmi->power_on = false;
195 if (hdmi->hdmi_mode)
196 msm_hdmi_audio_update(hdmi);
197 msm_hdmi_phy_resource_disable(phy);
198 }
199}
200
201static void msm_hdmi_bridge_mode_set(struct drm_bridge *bridge,
202 const struct drm_display_mode *mode,
203 const struct drm_display_mode *adjusted_mode)
204{
205 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
206 struct hdmi *hdmi = hdmi_bridge->hdmi;
207 int hstart, hend, vstart, vend;
208 uint32_t frame_ctrl;
209
210 mode = adjusted_mode;
211
212 hdmi->pixclock = mode->clock * 1000;
213
214 hstart = mode->htotal - mode->hsync_start;
215 hend = mode->htotal - mode->hsync_start + mode->hdisplay;
216
217 vstart = mode->vtotal - mode->vsync_start - 1;
218 vend = mode->vtotal - mode->vsync_start + mode->vdisplay - 1;
219
220 DBG("htotal=%d, vtotal=%d, hstart=%d, hend=%d, vstart=%d, vend=%d",
221 mode->htotal, mode->vtotal, hstart, hend, vstart, vend);
222
223 hdmi_write(hdmi, REG_HDMI_TOTAL,
224 HDMI_TOTAL_H_TOTAL(mode->htotal - 1) |
225 HDMI_TOTAL_V_TOTAL(mode->vtotal - 1));
226
227 hdmi_write(hdmi, REG_HDMI_ACTIVE_HSYNC,
228 HDMI_ACTIVE_HSYNC_START(hstart) |
229 HDMI_ACTIVE_HSYNC_END(hend));
230 hdmi_write(hdmi, REG_HDMI_ACTIVE_VSYNC,
231 HDMI_ACTIVE_VSYNC_START(vstart) |
232 HDMI_ACTIVE_VSYNC_END(vend));
233
234 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
235 hdmi_write(hdmi, REG_HDMI_VSYNC_TOTAL_F2,
236 HDMI_VSYNC_TOTAL_F2_V_TOTAL(mode->vtotal));
237 hdmi_write(hdmi, REG_HDMI_VSYNC_ACTIVE_F2,
238 HDMI_VSYNC_ACTIVE_F2_START(vstart + 1) |
239 HDMI_VSYNC_ACTIVE_F2_END(vend + 1));
240 } else {
241 hdmi_write(hdmi, REG_HDMI_VSYNC_TOTAL_F2,
242 HDMI_VSYNC_TOTAL_F2_V_TOTAL(0));
243 hdmi_write(hdmi, REG_HDMI_VSYNC_ACTIVE_F2,
244 HDMI_VSYNC_ACTIVE_F2_START(0) |
245 HDMI_VSYNC_ACTIVE_F2_END(0));
246 }
247
248 frame_ctrl = 0;
249 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
250 frame_ctrl |= HDMI_FRAME_CTRL_HSYNC_LOW;
251 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
252 frame_ctrl |= HDMI_FRAME_CTRL_VSYNC_LOW;
253 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
254 frame_ctrl |= HDMI_FRAME_CTRL_INTERLACED_EN;
255 DBG("frame_ctrl=%08x", frame_ctrl);
256 hdmi_write(hdmi, REG_HDMI_FRAME_CTRL, frame_ctrl);
257
258 if (hdmi->hdmi_mode)
259 msm_hdmi_audio_update(hdmi);
260}
261
262static const struct drm_bridge_funcs msm_hdmi_bridge_funcs = {
263 .pre_enable = msm_hdmi_bridge_pre_enable,
264 .enable = msm_hdmi_bridge_enable,
265 .disable = msm_hdmi_bridge_disable,
266 .post_disable = msm_hdmi_bridge_post_disable,
267 .mode_set = msm_hdmi_bridge_mode_set,
268};
269
270
271/* initialize bridge */
272struct drm_bridge *msm_hdmi_bridge_init(struct hdmi *hdmi)
273{
274 struct drm_bridge *bridge = NULL;
275 struct hdmi_bridge *hdmi_bridge;
276 int ret;
277
278 hdmi_bridge = devm_kzalloc(hdmi->dev->dev,
279 sizeof(*hdmi_bridge), GFP_KERNEL);
280 if (!hdmi_bridge) {
281 ret = -ENOMEM;
282 goto fail;
283 }
284
285 hdmi_bridge->hdmi = hdmi;
286
287 bridge = &hdmi_bridge->base;
288 bridge->funcs = &msm_hdmi_bridge_funcs;
289
290 ret = drm_bridge_attach(hdmi->encoder, bridge, NULL, 0);
291 if (ret)
292 goto fail;
293
294 return bridge;
295
296fail:
297 if (bridge)
298 msm_hdmi_bridge_destroy(bridge);
299
300 return ERR_PTR(ret);
301}