Loading...
1/*
2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#include "hdmi.h"
19
20struct hdmi_bridge {
21 struct drm_bridge base;
22 struct hdmi *hdmi;
23};
24#define to_hdmi_bridge(x) container_of(x, struct hdmi_bridge, base)
25
26void msm_hdmi_bridge_destroy(struct drm_bridge *bridge)
27{
28}
29
30static void msm_hdmi_power_on(struct drm_bridge *bridge)
31{
32 struct drm_device *dev = bridge->dev;
33 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
34 struct hdmi *hdmi = hdmi_bridge->hdmi;
35 const struct hdmi_platform_config *config = hdmi->config;
36 int i, ret;
37
38 for (i = 0; i < config->pwr_reg_cnt; i++) {
39 ret = regulator_enable(hdmi->pwr_regs[i]);
40 if (ret) {
41 dev_err(dev->dev, "failed to enable pwr regulator: %s (%d)\n",
42 config->pwr_reg_names[i], ret);
43 }
44 }
45
46 if (config->pwr_clk_cnt > 0) {
47 DBG("pixclock: %lu", hdmi->pixclock);
48 ret = clk_set_rate(hdmi->pwr_clks[0], hdmi->pixclock);
49 if (ret) {
50 dev_err(dev->dev, "failed to set pixel clk: %s (%d)\n",
51 config->pwr_clk_names[0], ret);
52 }
53 }
54
55 for (i = 0; i < config->pwr_clk_cnt; i++) {
56 ret = clk_prepare_enable(hdmi->pwr_clks[i]);
57 if (ret) {
58 dev_err(dev->dev, "failed to enable pwr clk: %s (%d)\n",
59 config->pwr_clk_names[i], ret);
60 }
61 }
62}
63
64static void power_off(struct drm_bridge *bridge)
65{
66 struct drm_device *dev = bridge->dev;
67 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
68 struct hdmi *hdmi = hdmi_bridge->hdmi;
69 const struct hdmi_platform_config *config = hdmi->config;
70 int i, ret;
71
72 /* TODO do we need to wait for final vblank somewhere before
73 * cutting the clocks?
74 */
75 mdelay(16 + 4);
76
77 for (i = 0; i < config->pwr_clk_cnt; i++)
78 clk_disable_unprepare(hdmi->pwr_clks[i]);
79
80 for (i = 0; i < config->pwr_reg_cnt; i++) {
81 ret = regulator_disable(hdmi->pwr_regs[i]);
82 if (ret) {
83 dev_err(dev->dev, "failed to disable pwr regulator: %s (%d)\n",
84 config->pwr_reg_names[i], ret);
85 }
86 }
87}
88
89static void msm_hdmi_bridge_pre_enable(struct drm_bridge *bridge)
90{
91 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
92 struct hdmi *hdmi = hdmi_bridge->hdmi;
93 struct hdmi_phy *phy = hdmi->phy;
94
95 DBG("power up");
96
97 if (!hdmi->power_on) {
98 msm_hdmi_phy_resource_enable(phy);
99 msm_hdmi_power_on(bridge);
100 hdmi->power_on = true;
101 msm_hdmi_audio_update(hdmi);
102 }
103
104 msm_hdmi_phy_powerup(phy, hdmi->pixclock);
105
106 msm_hdmi_set_mode(hdmi, true);
107
108 if (hdmi->hdcp_ctrl)
109 msm_hdmi_hdcp_on(hdmi->hdcp_ctrl);
110}
111
112static void msm_hdmi_bridge_enable(struct drm_bridge *bridge)
113{
114}
115
116static void msm_hdmi_bridge_disable(struct drm_bridge *bridge)
117{
118}
119
120static void msm_hdmi_bridge_post_disable(struct drm_bridge *bridge)
121{
122 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
123 struct hdmi *hdmi = hdmi_bridge->hdmi;
124 struct hdmi_phy *phy = hdmi->phy;
125
126 if (hdmi->hdcp_ctrl)
127 msm_hdmi_hdcp_off(hdmi->hdcp_ctrl);
128
129 DBG("power down");
130 msm_hdmi_set_mode(hdmi, false);
131
132 msm_hdmi_phy_powerdown(phy);
133
134 if (hdmi->power_on) {
135 power_off(bridge);
136 hdmi->power_on = false;
137 msm_hdmi_audio_update(hdmi);
138 msm_hdmi_phy_resource_disable(phy);
139 }
140}
141
142static void msm_hdmi_bridge_mode_set(struct drm_bridge *bridge,
143 struct drm_display_mode *mode,
144 struct drm_display_mode *adjusted_mode)
145{
146 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
147 struct hdmi *hdmi = hdmi_bridge->hdmi;
148 int hstart, hend, vstart, vend;
149 uint32_t frame_ctrl;
150
151 mode = adjusted_mode;
152
153 hdmi->pixclock = mode->clock * 1000;
154
155 hstart = mode->htotal - mode->hsync_start;
156 hend = mode->htotal - mode->hsync_start + mode->hdisplay;
157
158 vstart = mode->vtotal - mode->vsync_start - 1;
159 vend = mode->vtotal - mode->vsync_start + mode->vdisplay - 1;
160
161 DBG("htotal=%d, vtotal=%d, hstart=%d, hend=%d, vstart=%d, vend=%d",
162 mode->htotal, mode->vtotal, hstart, hend, vstart, vend);
163
164 hdmi_write(hdmi, REG_HDMI_TOTAL,
165 HDMI_TOTAL_H_TOTAL(mode->htotal - 1) |
166 HDMI_TOTAL_V_TOTAL(mode->vtotal - 1));
167
168 hdmi_write(hdmi, REG_HDMI_ACTIVE_HSYNC,
169 HDMI_ACTIVE_HSYNC_START(hstart) |
170 HDMI_ACTIVE_HSYNC_END(hend));
171 hdmi_write(hdmi, REG_HDMI_ACTIVE_VSYNC,
172 HDMI_ACTIVE_VSYNC_START(vstart) |
173 HDMI_ACTIVE_VSYNC_END(vend));
174
175 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
176 hdmi_write(hdmi, REG_HDMI_VSYNC_TOTAL_F2,
177 HDMI_VSYNC_TOTAL_F2_V_TOTAL(mode->vtotal));
178 hdmi_write(hdmi, REG_HDMI_VSYNC_ACTIVE_F2,
179 HDMI_VSYNC_ACTIVE_F2_START(vstart + 1) |
180 HDMI_VSYNC_ACTIVE_F2_END(vend + 1));
181 } else {
182 hdmi_write(hdmi, REG_HDMI_VSYNC_TOTAL_F2,
183 HDMI_VSYNC_TOTAL_F2_V_TOTAL(0));
184 hdmi_write(hdmi, REG_HDMI_VSYNC_ACTIVE_F2,
185 HDMI_VSYNC_ACTIVE_F2_START(0) |
186 HDMI_VSYNC_ACTIVE_F2_END(0));
187 }
188
189 frame_ctrl = 0;
190 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
191 frame_ctrl |= HDMI_FRAME_CTRL_HSYNC_LOW;
192 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
193 frame_ctrl |= HDMI_FRAME_CTRL_VSYNC_LOW;
194 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
195 frame_ctrl |= HDMI_FRAME_CTRL_INTERLACED_EN;
196 DBG("frame_ctrl=%08x", frame_ctrl);
197 hdmi_write(hdmi, REG_HDMI_FRAME_CTRL, frame_ctrl);
198
199 msm_hdmi_audio_update(hdmi);
200}
201
202static const struct drm_bridge_funcs msm_hdmi_bridge_funcs = {
203 .pre_enable = msm_hdmi_bridge_pre_enable,
204 .enable = msm_hdmi_bridge_enable,
205 .disable = msm_hdmi_bridge_disable,
206 .post_disable = msm_hdmi_bridge_post_disable,
207 .mode_set = msm_hdmi_bridge_mode_set,
208};
209
210
211/* initialize bridge */
212struct drm_bridge *msm_hdmi_bridge_init(struct hdmi *hdmi)
213{
214 struct drm_bridge *bridge = NULL;
215 struct hdmi_bridge *hdmi_bridge;
216 int ret;
217
218 hdmi_bridge = devm_kzalloc(hdmi->dev->dev,
219 sizeof(*hdmi_bridge), GFP_KERNEL);
220 if (!hdmi_bridge) {
221 ret = -ENOMEM;
222 goto fail;
223 }
224
225 hdmi_bridge->hdmi = hdmi;
226
227 bridge = &hdmi_bridge->base;
228 bridge->funcs = &msm_hdmi_bridge_funcs;
229
230 ret = drm_bridge_attach(hdmi->dev, bridge);
231 if (ret)
232 goto fail;
233
234 return bridge;
235
236fail:
237 if (bridge)
238 msm_hdmi_bridge_destroy(bridge);
239
240 return ERR_PTR(ret);
241}
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
5 */
6
7#include <linux/delay.h>
8#include <drm/drm_bridge_connector.h>
9#include <drm/drm_edid.h>
10
11#include "msm_kms.h"
12#include "hdmi.h"
13
14static void msm_hdmi_power_on(struct drm_bridge *bridge)
15{
16 struct drm_device *dev = bridge->dev;
17 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
18 struct hdmi *hdmi = hdmi_bridge->hdmi;
19 const struct hdmi_platform_config *config = hdmi->config;
20 int i, ret;
21
22 pm_runtime_get_sync(&hdmi->pdev->dev);
23
24 ret = regulator_bulk_enable(config->pwr_reg_cnt, hdmi->pwr_regs);
25 if (ret)
26 DRM_DEV_ERROR(dev->dev, "failed to enable pwr regulator: %d\n", ret);
27
28 if (config->pwr_clk_cnt > 0) {
29 DBG("pixclock: %lu", hdmi->pixclock);
30 ret = clk_set_rate(hdmi->pwr_clks[0], hdmi->pixclock);
31 if (ret) {
32 DRM_DEV_ERROR(dev->dev, "failed to set pixel clk: %s (%d)\n",
33 config->pwr_clk_names[0], ret);
34 }
35 }
36
37 for (i = 0; i < config->pwr_clk_cnt; i++) {
38 ret = clk_prepare_enable(hdmi->pwr_clks[i]);
39 if (ret) {
40 DRM_DEV_ERROR(dev->dev, "failed to enable pwr clk: %s (%d)\n",
41 config->pwr_clk_names[i], ret);
42 }
43 }
44}
45
46static void power_off(struct drm_bridge *bridge)
47{
48 struct drm_device *dev = bridge->dev;
49 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
50 struct hdmi *hdmi = hdmi_bridge->hdmi;
51 const struct hdmi_platform_config *config = hdmi->config;
52 int i, ret;
53
54 /* TODO do we need to wait for final vblank somewhere before
55 * cutting the clocks?
56 */
57 mdelay(16 + 4);
58
59 for (i = 0; i < config->pwr_clk_cnt; i++)
60 clk_disable_unprepare(hdmi->pwr_clks[i]);
61
62 ret = regulator_bulk_disable(config->pwr_reg_cnt, hdmi->pwr_regs);
63 if (ret)
64 DRM_DEV_ERROR(dev->dev, "failed to disable pwr regulator: %d\n", ret);
65
66 pm_runtime_put(&hdmi->pdev->dev);
67}
68
69#define AVI_IFRAME_LINE_NUMBER 1
70
71static void msm_hdmi_config_avi_infoframe(struct hdmi *hdmi)
72{
73 struct drm_crtc *crtc = hdmi->encoder->crtc;
74 const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
75 union hdmi_infoframe frame;
76 u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
77 u32 val;
78 int len;
79
80 drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
81 hdmi->connector, mode);
82
83 len = hdmi_infoframe_pack(&frame, buffer, sizeof(buffer));
84 if (len < 0) {
85 DRM_DEV_ERROR(&hdmi->pdev->dev,
86 "failed to configure avi infoframe\n");
87 return;
88 }
89
90 /*
91 * the AVI_INFOx registers don't map exactly to how the AVI infoframes
92 * are packed according to the spec. The checksum from the header is
93 * written to the LSB byte of AVI_INFO0 and the version is written to
94 * the third byte from the LSB of AVI_INFO3
95 */
96 hdmi_write(hdmi, REG_HDMI_AVI_INFO(0),
97 buffer[3] |
98 buffer[4] << 8 |
99 buffer[5] << 16 |
100 buffer[6] << 24);
101
102 hdmi_write(hdmi, REG_HDMI_AVI_INFO(1),
103 buffer[7] |
104 buffer[8] << 8 |
105 buffer[9] << 16 |
106 buffer[10] << 24);
107
108 hdmi_write(hdmi, REG_HDMI_AVI_INFO(2),
109 buffer[11] |
110 buffer[12] << 8 |
111 buffer[13] << 16 |
112 buffer[14] << 24);
113
114 hdmi_write(hdmi, REG_HDMI_AVI_INFO(3),
115 buffer[15] |
116 buffer[16] << 8 |
117 buffer[1] << 24);
118
119 hdmi_write(hdmi, REG_HDMI_INFOFRAME_CTRL0,
120 HDMI_INFOFRAME_CTRL0_AVI_SEND |
121 HDMI_INFOFRAME_CTRL0_AVI_CONT);
122
123 val = hdmi_read(hdmi, REG_HDMI_INFOFRAME_CTRL1);
124 val &= ~HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__MASK;
125 val |= HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE(AVI_IFRAME_LINE_NUMBER);
126 hdmi_write(hdmi, REG_HDMI_INFOFRAME_CTRL1, val);
127}
128
129static void msm_hdmi_bridge_pre_enable(struct drm_bridge *bridge)
130{
131 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
132 struct hdmi *hdmi = hdmi_bridge->hdmi;
133 struct hdmi_phy *phy = hdmi->phy;
134
135 DBG("power up");
136
137 if (!hdmi->power_on) {
138 msm_hdmi_phy_resource_enable(phy);
139 msm_hdmi_power_on(bridge);
140 hdmi->power_on = true;
141 if (hdmi->hdmi_mode) {
142 msm_hdmi_config_avi_infoframe(hdmi);
143 msm_hdmi_audio_update(hdmi);
144 }
145 }
146
147 msm_hdmi_phy_powerup(phy, hdmi->pixclock);
148
149 msm_hdmi_set_mode(hdmi, true);
150
151 if (hdmi->hdcp_ctrl)
152 msm_hdmi_hdcp_on(hdmi->hdcp_ctrl);
153}
154
155static void msm_hdmi_bridge_post_disable(struct drm_bridge *bridge)
156{
157 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
158 struct hdmi *hdmi = hdmi_bridge->hdmi;
159 struct hdmi_phy *phy = hdmi->phy;
160
161 if (hdmi->hdcp_ctrl)
162 msm_hdmi_hdcp_off(hdmi->hdcp_ctrl);
163
164 DBG("power down");
165 msm_hdmi_set_mode(hdmi, false);
166
167 msm_hdmi_phy_powerdown(phy);
168
169 if (hdmi->power_on) {
170 power_off(bridge);
171 hdmi->power_on = false;
172 if (hdmi->hdmi_mode)
173 msm_hdmi_audio_update(hdmi);
174 msm_hdmi_phy_resource_disable(phy);
175 }
176}
177
178static void msm_hdmi_bridge_mode_set(struct drm_bridge *bridge,
179 const struct drm_display_mode *mode,
180 const struct drm_display_mode *adjusted_mode)
181{
182 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
183 struct hdmi *hdmi = hdmi_bridge->hdmi;
184 int hstart, hend, vstart, vend;
185 uint32_t frame_ctrl;
186
187 mode = adjusted_mode;
188
189 hdmi->pixclock = mode->clock * 1000;
190
191 hstart = mode->htotal - mode->hsync_start;
192 hend = mode->htotal - mode->hsync_start + mode->hdisplay;
193
194 vstart = mode->vtotal - mode->vsync_start - 1;
195 vend = mode->vtotal - mode->vsync_start + mode->vdisplay - 1;
196
197 DBG("htotal=%d, vtotal=%d, hstart=%d, hend=%d, vstart=%d, vend=%d",
198 mode->htotal, mode->vtotal, hstart, hend, vstart, vend);
199
200 hdmi_write(hdmi, REG_HDMI_TOTAL,
201 HDMI_TOTAL_H_TOTAL(mode->htotal - 1) |
202 HDMI_TOTAL_V_TOTAL(mode->vtotal - 1));
203
204 hdmi_write(hdmi, REG_HDMI_ACTIVE_HSYNC,
205 HDMI_ACTIVE_HSYNC_START(hstart) |
206 HDMI_ACTIVE_HSYNC_END(hend));
207 hdmi_write(hdmi, REG_HDMI_ACTIVE_VSYNC,
208 HDMI_ACTIVE_VSYNC_START(vstart) |
209 HDMI_ACTIVE_VSYNC_END(vend));
210
211 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
212 hdmi_write(hdmi, REG_HDMI_VSYNC_TOTAL_F2,
213 HDMI_VSYNC_TOTAL_F2_V_TOTAL(mode->vtotal));
214 hdmi_write(hdmi, REG_HDMI_VSYNC_ACTIVE_F2,
215 HDMI_VSYNC_ACTIVE_F2_START(vstart + 1) |
216 HDMI_VSYNC_ACTIVE_F2_END(vend + 1));
217 } else {
218 hdmi_write(hdmi, REG_HDMI_VSYNC_TOTAL_F2,
219 HDMI_VSYNC_TOTAL_F2_V_TOTAL(0));
220 hdmi_write(hdmi, REG_HDMI_VSYNC_ACTIVE_F2,
221 HDMI_VSYNC_ACTIVE_F2_START(0) |
222 HDMI_VSYNC_ACTIVE_F2_END(0));
223 }
224
225 frame_ctrl = 0;
226 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
227 frame_ctrl |= HDMI_FRAME_CTRL_HSYNC_LOW;
228 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
229 frame_ctrl |= HDMI_FRAME_CTRL_VSYNC_LOW;
230 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
231 frame_ctrl |= HDMI_FRAME_CTRL_INTERLACED_EN;
232 DBG("frame_ctrl=%08x", frame_ctrl);
233 hdmi_write(hdmi, REG_HDMI_FRAME_CTRL, frame_ctrl);
234
235 if (hdmi->hdmi_mode)
236 msm_hdmi_audio_update(hdmi);
237}
238
239static struct edid *msm_hdmi_bridge_get_edid(struct drm_bridge *bridge,
240 struct drm_connector *connector)
241{
242 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
243 struct hdmi *hdmi = hdmi_bridge->hdmi;
244 struct edid *edid;
245 uint32_t hdmi_ctrl;
246
247 hdmi_ctrl = hdmi_read(hdmi, REG_HDMI_CTRL);
248 hdmi_write(hdmi, REG_HDMI_CTRL, hdmi_ctrl | HDMI_CTRL_ENABLE);
249
250 edid = drm_get_edid(connector, hdmi->i2c);
251
252 hdmi_write(hdmi, REG_HDMI_CTRL, hdmi_ctrl);
253
254 hdmi->hdmi_mode = drm_detect_hdmi_monitor(edid);
255
256 return edid;
257}
258
259static enum drm_mode_status msm_hdmi_bridge_mode_valid(struct drm_bridge *bridge,
260 const struct drm_display_info *info,
261 const struct drm_display_mode *mode)
262{
263 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
264 struct hdmi *hdmi = hdmi_bridge->hdmi;
265 const struct hdmi_platform_config *config = hdmi->config;
266 struct msm_drm_private *priv = bridge->dev->dev_private;
267 struct msm_kms *kms = priv->kms;
268 long actual, requested;
269
270 requested = 1000 * mode->clock;
271
272 /* for mdp5/apq8074, we manage our own pixel clk (as opposed to
273 * mdp4/dtv stuff where pixel clk is assigned to mdp/encoder
274 * instead):
275 */
276 if (kms->funcs->round_pixclk)
277 actual = kms->funcs->round_pixclk(kms,
278 requested, hdmi_bridge->hdmi->encoder);
279 else if (config->pwr_clk_cnt > 0)
280 actual = clk_round_rate(hdmi->pwr_clks[0], requested);
281 else
282 actual = requested;
283
284 DBG("requested=%ld, actual=%ld", requested, actual);
285
286 if (actual != requested)
287 return MODE_CLOCK_RANGE;
288
289 return 0;
290}
291
292static const struct drm_bridge_funcs msm_hdmi_bridge_funcs = {
293 .pre_enable = msm_hdmi_bridge_pre_enable,
294 .post_disable = msm_hdmi_bridge_post_disable,
295 .mode_set = msm_hdmi_bridge_mode_set,
296 .mode_valid = msm_hdmi_bridge_mode_valid,
297 .get_edid = msm_hdmi_bridge_get_edid,
298 .detect = msm_hdmi_bridge_detect,
299};
300
301static void
302msm_hdmi_hotplug_work(struct work_struct *work)
303{
304 struct hdmi_bridge *hdmi_bridge =
305 container_of(work, struct hdmi_bridge, hpd_work);
306 struct drm_bridge *bridge = &hdmi_bridge->base;
307
308 drm_bridge_hpd_notify(bridge, drm_bridge_detect(bridge));
309}
310
311/* initialize bridge */
312int msm_hdmi_bridge_init(struct hdmi *hdmi)
313{
314 struct drm_bridge *bridge = NULL;
315 struct hdmi_bridge *hdmi_bridge;
316 int ret;
317
318 hdmi_bridge = devm_kzalloc(hdmi->dev->dev,
319 sizeof(*hdmi_bridge), GFP_KERNEL);
320 if (!hdmi_bridge)
321 return -ENOMEM;
322
323 hdmi_bridge->hdmi = hdmi;
324 INIT_WORK(&hdmi_bridge->hpd_work, msm_hdmi_hotplug_work);
325
326 bridge = &hdmi_bridge->base;
327 bridge->funcs = &msm_hdmi_bridge_funcs;
328 bridge->ddc = hdmi->i2c;
329 bridge->type = DRM_MODE_CONNECTOR_HDMIA;
330 bridge->ops = DRM_BRIDGE_OP_HPD |
331 DRM_BRIDGE_OP_DETECT |
332 DRM_BRIDGE_OP_EDID;
333
334 ret = devm_drm_bridge_add(hdmi->dev->dev, bridge);
335 if (ret)
336 return ret;
337
338 ret = drm_bridge_attach(hdmi->encoder, bridge, NULL, DRM_BRIDGE_ATTACH_NO_CONNECTOR);
339 if (ret)
340 return ret;
341
342 hdmi->bridge = bridge;
343
344 return 0;
345}