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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries.
4 * All rights reserved.
5 */
6
7#ifndef WILC_WLAN_H
8#define WILC_WLAN_H
9
10#include <linux/types.h>
11#include <linux/bitfield.h>
12
13/********************************************
14 *
15 * Mac eth header length
16 *
17 ********************************************/
18#define MAX_MAC_HDR_LEN 26 /* QOS_MAC_HDR_LEN */
19#define SUB_MSDU_HEADER_LENGTH 14
20#define SNAP_HDR_LEN 8
21#define ETHERNET_HDR_LEN 14
22#define WORD_ALIGNMENT_PAD 0
23
24#define ETH_ETHERNET_HDR_OFFSET (MAX_MAC_HDR_LEN + \
25 SUB_MSDU_HEADER_LENGTH + \
26 SNAP_HDR_LEN - \
27 ETHERNET_HDR_LEN + \
28 WORD_ALIGNMENT_PAD)
29
30#define HOST_HDR_OFFSET 4
31#define ETHERNET_HDR_LEN 14
32#define IP_HDR_LEN 20
33#define IP_HDR_OFFSET ETHERNET_HDR_LEN
34#define UDP_HDR_OFFSET (IP_HDR_LEN + IP_HDR_OFFSET)
35#define UDP_HDR_LEN 8
36#define UDP_DATA_OFFSET (UDP_HDR_OFFSET + UDP_HDR_LEN)
37#define ETH_CONFIG_PKT_HDR_LEN UDP_DATA_OFFSET
38
39#define ETH_CONFIG_PKT_HDR_OFFSET (ETH_ETHERNET_HDR_OFFSET + \
40 ETH_CONFIG_PKT_HDR_LEN)
41
42/********************************************
43 *
44 * Register Defines
45 *
46 ********************************************/
47#define WILC_PERIPH_REG_BASE 0x1000
48#define WILC_CHANGING_VIR_IF 0x108c
49#define WILC_CHIPID WILC_PERIPH_REG_BASE
50#define WILC_GLB_RESET_0 (WILC_PERIPH_REG_BASE + 0x400)
51#define WILC_PIN_MUX_0 (WILC_PERIPH_REG_BASE + 0x408)
52#define WILC_HOST_TX_CTRL (WILC_PERIPH_REG_BASE + 0x6c)
53#define WILC_HOST_RX_CTRL_0 (WILC_PERIPH_REG_BASE + 0x70)
54#define WILC_HOST_RX_CTRL_1 (WILC_PERIPH_REG_BASE + 0x74)
55#define WILC_HOST_VMM_CTL (WILC_PERIPH_REG_BASE + 0x78)
56#define WILC_HOST_RX_CTRL (WILC_PERIPH_REG_BASE + 0x80)
57#define WILC_HOST_RX_EXTRA_SIZE (WILC_PERIPH_REG_BASE + 0x84)
58#define WILC_HOST_TX_CTRL_1 (WILC_PERIPH_REG_BASE + 0x88)
59#define WILC_MISC (WILC_PERIPH_REG_BASE + 0x428)
60#define WILC_INTR_REG_BASE (WILC_PERIPH_REG_BASE + 0xa00)
61#define WILC_INTR_ENABLE WILC_INTR_REG_BASE
62#define WILC_INTR2_ENABLE (WILC_INTR_REG_BASE + 4)
63
64#define WILC_INTR_POLARITY (WILC_INTR_REG_BASE + 0x10)
65#define WILC_INTR_TYPE (WILC_INTR_REG_BASE + 0x20)
66#define WILC_INTR_CLEAR (WILC_INTR_REG_BASE + 0x30)
67#define WILC_INTR_STATUS (WILC_INTR_REG_BASE + 0x40)
68
69#define WILC_RF_REVISION_ID 0x13f4
70
71#define WILC_VMM_TBL_SIZE 64
72#define WILC_VMM_TX_TBL_BASE 0x150400
73#define WILC_VMM_RX_TBL_BASE 0x150500
74
75#define WILC_VMM_BASE 0x150000
76#define WILC_VMM_CORE_CTL WILC_VMM_BASE
77#define WILC_VMM_TBL_CTL (WILC_VMM_BASE + 0x4)
78#define WILC_VMM_TBL_ENTRY (WILC_VMM_BASE + 0x8)
79#define WILC_VMM_TBL0_SIZE (WILC_VMM_BASE + 0xc)
80#define WILC_VMM_TO_HOST_SIZE (WILC_VMM_BASE + 0x10)
81#define WILC_VMM_CORE_CFG (WILC_VMM_BASE + 0x14)
82#define WILC_VMM_TBL_ACTIVE (WILC_VMM_BASE + 040)
83#define WILC_VMM_TBL_STATUS (WILC_VMM_BASE + 0x44)
84
85#define WILC_SPI_REG_BASE 0xe800
86#define WILC_SPI_CTL WILC_SPI_REG_BASE
87#define WILC_SPI_MASTER_DMA_ADDR (WILC_SPI_REG_BASE + 0x4)
88#define WILC_SPI_MASTER_DMA_COUNT (WILC_SPI_REG_BASE + 0x8)
89#define WILC_SPI_SLAVE_DMA_ADDR (WILC_SPI_REG_BASE + 0xc)
90#define WILC_SPI_SLAVE_DMA_COUNT (WILC_SPI_REG_BASE + 0x10)
91#define WILC_SPI_TX_MODE (WILC_SPI_REG_BASE + 0x20)
92#define WILC_SPI_PROTOCOL_CONFIG (WILC_SPI_REG_BASE + 0x24)
93#define WILC_SPI_INTR_CTL (WILC_SPI_REG_BASE + 0x2c)
94#define WILC_SPI_INT_STATUS (WILC_SPI_REG_BASE + 0x40)
95#define WILC_SPI_INT_CLEAR (WILC_SPI_REG_BASE + 0x44)
96
97#define WILC_SPI_WAKEUP_REG 0x1
98#define WILC_SPI_WAKEUP_BIT BIT(1)
99
100#define WILC_SPI_HOST_TO_FW_REG 0x0b
101#define WILC_SPI_HOST_TO_FW_BIT BIT(0)
102
103#define WILC_SPI_FW_TO_HOST_REG 0x10
104#define WILC_SPI_FW_TO_HOST_BIT BIT(0)
105
106#define WILC_SPI_PROTOCOL_OFFSET (WILC_SPI_PROTOCOL_CONFIG - \
107 WILC_SPI_REG_BASE)
108
109#define WILC_SPI_CLOCKLESS_ADDR_LIMIT 0x30
110
111/* Functions IO enables bits */
112#define WILC_SDIO_CCCR_IO_EN_FUNC1 BIT(1)
113
114/* Function/Interrupt enables bits */
115#define WILC_SDIO_CCCR_IEN_MASTER BIT(0)
116#define WILC_SDIO_CCCR_IEN_FUNC1 BIT(1)
117
118/* Abort CCCR register bits */
119#define WILC_SDIO_CCCR_ABORT_RESET BIT(3)
120
121/* Vendor specific CCCR registers */
122#define WILC_SDIO_WAKEUP_REG 0xf0
123#define WILC_SDIO_WAKEUP_BIT BIT(0)
124
125#define WILC_SDIO_CLK_STATUS_REG 0xf1
126#define WILC_SDIO_CLK_STATUS_BIT BIT(0)
127
128#define WILC_SDIO_INTERRUPT_DATA_SZ_REG 0xf2 /* Read size (2 bytes) */
129
130#define WILC_SDIO_VMM_TBL_CTRL_REG 0xf6
131#define WILC_SDIO_IRQ_FLAG_REG 0xf7
132#define WILC_SDIO_IRQ_CLEAR_FLAG_REG 0xf8
133
134#define WILC_SDIO_HOST_TO_FW_REG 0xfa
135#define WILC_SDIO_HOST_TO_FW_BIT BIT(0)
136
137#define WILC_SDIO_FW_TO_HOST_REG 0xfc
138#define WILC_SDIO_FW_TO_HOST_BIT BIT(0)
139
140/* Function 1 specific FBR register */
141#define WILC_SDIO_FBR_CSA_REG 0x10C /* CSA pointer (3 bytes) */
142#define WILC_SDIO_FBR_DATA_REG 0x10F
143
144#define WILC_SDIO_F1_DATA_REG 0x0
145#define WILC_SDIO_EXT_IRQ_FLAG_REG 0x4
146
147#define WILC_AHB_DATA_MEM_BASE 0x30000
148#define WILC_AHB_SHARE_MEM_BASE 0xd0000
149
150#define WILC_VMM_TBL_RX_SHADOW_BASE WILC_AHB_SHARE_MEM_BASE
151#define WILC_VMM_TBL_RX_SHADOW_SIZE 256
152
153#define WILC_FW_HOST_COMM 0x13c0
154#define WILC_GP_REG_0 0x149c
155#define WILC_GP_REG_1 0x14a0
156
157#define WILC_HAVE_SDIO_IRQ_GPIO BIT(0)
158#define WILC_HAVE_USE_PMU BIT(1)
159#define WILC_HAVE_SLEEP_CLK_SRC_RTC BIT(2)
160#define WILC_HAVE_SLEEP_CLK_SRC_XO BIT(3)
161#define WILC_HAVE_EXT_PA_INV_TX_RX BIT(4)
162#define WILC_HAVE_LEGACY_RF_SETTINGS BIT(5)
163#define WILC_HAVE_XTAL_24 BIT(6)
164#define WILC_HAVE_DISABLE_WILC_UART BIT(7)
165#define WILC_HAVE_USE_IRQ_AS_HOST_WAKE BIT(8)
166
167#define WILC_CORTUS_INTERRUPT_BASE 0x10A8
168#define WILC_CORTUS_INTERRUPT_1 (WILC_CORTUS_INTERRUPT_BASE + 0x4)
169#define WILC_CORTUS_INTERRUPT_2 (WILC_CORTUS_INTERRUPT_BASE + 0x8)
170
171/* tx control register 1 to 4 for RX */
172#define WILC_REG_4_TO_1_RX 0x1e1c
173
174/* tx control register 1 to 4 for TX Bank_0 */
175#define WILC_REG_4_TO_1_TX_BANK0 0x1e9c
176
177#define WILC_CORTUS_RESET_MUX_SEL 0x1118
178#define WILC_CORTUS_BOOT_REGISTER 0xc0000
179
180#define WILC_CORTUS_BOOT_FROM_IRAM 0x71
181
182#define WILC_1000_BASE_ID 0x100000
183
184#define WILC_1000_BASE_ID_2A 0x1002A0
185#define WILC_1000_BASE_ID_2A_REV1 (WILC_1000_BASE_ID_2A + 1)
186
187#define WILC_1000_BASE_ID_2B 0x1002B0
188#define WILC_1000_BASE_ID_2B_REV1 (WILC_1000_BASE_ID_2B + 1)
189#define WILC_1000_BASE_ID_2B_REV2 (WILC_1000_BASE_ID_2B + 2)
190
191#define WILC_CHIP_REV_FIELD GENMASK(11, 0)
192
193/********************************************
194 *
195 * Wlan Defines
196 *
197 ********************************************/
198#define WILC_CFG_PKT 1
199#define WILC_NET_PKT 0
200#define WILC_MGMT_PKT 2
201
202#define WILC_CFG_SET 1
203#define WILC_CFG_QUERY 0
204
205#define WILC_CFG_RSP 1
206#define WILC_CFG_RSP_STATUS 2
207#define WILC_CFG_RSP_SCAN 3
208
209#define WILC_ABORT_REQ_BIT BIT(31)
210
211#define WILC_RX_BUFF_SIZE (96 * 1024)
212#define WILC_TX_BUFF_SIZE (64 * 1024)
213
214#define MODALIAS "WILC_SPI"
215
216#define NQUEUES 4
217#define AC_BUFFER_SIZE 1000
218
219#define VO_AC_COUNT_FIELD GENMASK(31, 25)
220#define VO_AC_ACM_STAT_FIELD BIT(24)
221#define VI_AC_COUNT_FIELD GENMASK(23, 17)
222#define VI_AC_ACM_STAT_FIELD BIT(16)
223#define BE_AC_COUNT_FIELD GENMASK(15, 9)
224#define BE_AC_ACM_STAT_FIELD BIT(8)
225#define BK_AC_COUNT_FIELD GENMASK(7, 3)
226#define BK_AC_ACM_STAT_FIELD BIT(1)
227
228#define WILC_PKT_HDR_CONFIG_FIELD BIT(31)
229#define WILC_PKT_HDR_OFFSET_FIELD GENMASK(30, 22)
230#define WILC_PKT_HDR_TOTAL_LEN_FIELD GENMASK(21, 11)
231#define WILC_PKT_HDR_LEN_FIELD GENMASK(10, 0)
232
233#define WILC_INTERRUPT_DATA_SIZE GENMASK(14, 0)
234
235#define WILC_VMM_BUFFER_SIZE GENMASK(9, 0)
236
237#define WILC_VMM_HDR_TYPE BIT(31)
238#define WILC_VMM_HDR_MGMT_FIELD BIT(30)
239#define WILC_VMM_HDR_PKT_SIZE GENMASK(29, 15)
240#define WILC_VMM_HDR_BUFF_SIZE GENMASK(14, 0)
241
242#define WILC_VMM_ENTRY_COUNT GENMASK(8, 3)
243#define WILC_VMM_ENTRY_AVAILABLE BIT(2)
244/*******************************************/
245/* E0 and later Interrupt flags. */
246/*******************************************/
247/*******************************************/
248/* E0 and later Interrupt flags. */
249/* IRQ Status word */
250/* 15:0 = DMA count in words. */
251/* 16: INT0 flag */
252/* 17: INT1 flag */
253/* 18: INT2 flag */
254/* 19: INT3 flag */
255/* 20: INT4 flag */
256/* 21: INT5 flag */
257/*******************************************/
258#define IRG_FLAGS_OFFSET 16
259#define IRQ_DMA_WD_CNT_MASK GENMASK(IRG_FLAGS_OFFSET - 1, 0)
260#define INT_0 BIT(IRG_FLAGS_OFFSET)
261#define INT_1 BIT(IRG_FLAGS_OFFSET + 1)
262#define INT_2 BIT(IRG_FLAGS_OFFSET + 2)
263#define INT_3 BIT(IRG_FLAGS_OFFSET + 3)
264#define INT_4 BIT(IRG_FLAGS_OFFSET + 4)
265#define INT_5 BIT(IRG_FLAGS_OFFSET + 5)
266#define MAX_NUM_INT 5
267#define IRG_FLAGS_MASK GENMASK(IRG_FLAGS_OFFSET + MAX_NUM_INT, \
268 IRG_FLAGS_OFFSET)
269
270/*******************************************/
271/* E0 and later Interrupt flags. */
272/* IRQ Clear word */
273/* 0: Clear INT0 */
274/* 1: Clear INT1 */
275/* 2: Clear INT2 */
276/* 3: Clear INT3 */
277/* 4: Clear INT4 */
278/* 5: Clear INT5 */
279/* 6: Select VMM table 1 */
280/* 7: Select VMM table 2 */
281/* 8: Enable VMM */
282/*******************************************/
283#define CLR_INT0 BIT(0)
284#define CLR_INT1 BIT(1)
285#define CLR_INT2 BIT(2)
286#define CLR_INT3 BIT(3)
287#define CLR_INT4 BIT(4)
288#define CLR_INT5 BIT(5)
289#define SEL_VMM_TBL0 BIT(6)
290#define SEL_VMM_TBL1 BIT(7)
291#define EN_VMM BIT(8)
292
293#define DATA_INT_EXT INT_0
294#define ALL_INT_EXT DATA_INT_EXT
295#define NUM_INT_EXT 1
296#define UNHANDLED_IRQ_MASK GENMASK(MAX_NUM_INT - 1, NUM_INT_EXT)
297
298#define DATA_INT_CLR CLR_INT0
299
300#define ENABLE_RX_VMM (SEL_VMM_TBL1 | EN_VMM)
301#define ENABLE_TX_VMM (SEL_VMM_TBL0 | EN_VMM)
302/* time for expiring the completion of cfg packets */
303#define WILC_CFG_PKTS_TIMEOUT msecs_to_jiffies(2000)
304
305#define IS_MANAGMEMENT 0x100
306#define IS_MANAGMEMENT_CALLBACK 0x080
307#define IS_MGMT_STATUS_SUCCES 0x040
308
309#define WILC_WID_TYPE GENMASK(15, 12)
310#define WILC_VMM_ENTRY_FULL_RETRY 1
311/********************************************
312 *
313 * Tx/Rx Queue Structure
314 *
315 ********************************************/
316enum ip_pkt_priority {
317 AC_VO_Q = 0,
318 AC_VI_Q = 1,
319 AC_BE_Q = 2,
320 AC_BK_Q = 3
321};
322
323struct txq_entry_t {
324 struct list_head list;
325 int type;
326 u8 q_num;
327 int ack_idx;
328 u8 *buffer;
329 int buffer_size;
330 void *priv;
331 int status;
332 struct wilc_vif *vif;
333 void (*tx_complete_func)(void *priv, int status);
334};
335
336struct txq_fw_recv_queue_stat {
337 u8 acm;
338 u8 count;
339};
340
341struct txq_handle {
342 struct txq_entry_t txq_head;
343 u16 count;
344 struct txq_fw_recv_queue_stat fw;
345};
346
347struct rxq_entry_t {
348 struct list_head list;
349 u8 *buffer;
350 int buffer_size;
351};
352
353/********************************************
354 *
355 * Host IF Structure
356 *
357 ********************************************/
358struct wilc;
359struct wilc_hif_func {
360 int (*hif_init)(struct wilc *wilc, bool resume);
361 int (*hif_deinit)(struct wilc *wilc);
362 int (*hif_read_reg)(struct wilc *wilc, u32 addr, u32 *data);
363 int (*hif_write_reg)(struct wilc *wilc, u32 addr, u32 data);
364 int (*hif_block_rx)(struct wilc *wilc, u32 addr, u8 *buf, u32 size);
365 int (*hif_block_tx)(struct wilc *wilc, u32 addr, u8 *buf, u32 size);
366 int (*hif_read_int)(struct wilc *wilc, u32 *int_status);
367 int (*hif_clear_int_ext)(struct wilc *wilc, u32 val);
368 int (*hif_read_size)(struct wilc *wilc, u32 *size);
369 int (*hif_block_tx_ext)(struct wilc *wilc, u32 addr, u8 *buf, u32 size);
370 int (*hif_block_rx_ext)(struct wilc *wilc, u32 addr, u8 *buf, u32 size);
371 int (*hif_sync_ext)(struct wilc *wilc, int nint);
372 int (*enable_interrupt)(struct wilc *nic);
373 void (*disable_interrupt)(struct wilc *nic);
374};
375
376#define WILC_MAX_CFG_FRAME_SIZE 1468
377
378struct tx_complete_data {
379 int size;
380 void *buff;
381 struct sk_buff *skb;
382};
383
384struct wilc_cfg_cmd_hdr {
385 u8 cmd_type;
386 u8 seq_no;
387 __le16 total_len;
388 __le32 driver_handler;
389};
390
391struct wilc_cfg_frame {
392 struct wilc_cfg_cmd_hdr hdr;
393 u8 frame[WILC_MAX_CFG_FRAME_SIZE];
394};
395
396struct wilc_cfg_rsp {
397 u8 type;
398 u8 seq_no;
399};
400
401struct wilc_vif;
402
403int wilc_wlan_firmware_download(struct wilc *wilc, const u8 *buffer,
404 u32 buffer_size);
405int wilc_wlan_start(struct wilc *wilc);
406int wilc_wlan_stop(struct wilc *wilc, struct wilc_vif *vif);
407int wilc_wlan_txq_add_net_pkt(struct net_device *dev,
408 struct tx_complete_data *tx_data, u8 *buffer,
409 u32 buffer_size,
410 void (*tx_complete_fn)(void *, int));
411int wilc_wlan_handle_txq(struct wilc *wl, u32 *txq_count);
412void wilc_handle_isr(struct wilc *wilc);
413void wilc_wlan_cleanup(struct net_device *dev);
414int wilc_wlan_cfg_set(struct wilc_vif *vif, int start, u16 wid, u8 *buffer,
415 u32 buffer_size, int commit, u32 drv_handler);
416int wilc_wlan_cfg_get(struct wilc_vif *vif, int start, u16 wid, int commit,
417 u32 drv_handler);
418int wilc_wlan_txq_add_mgmt_pkt(struct net_device *dev, void *priv, u8 *buffer,
419 u32 buffer_size, void (*func)(void *, int));
420void wilc_enable_tcp_ack_filter(struct wilc_vif *vif, bool value);
421int wilc_wlan_get_num_conn_ifcs(struct wilc *wilc);
422netdev_tx_t wilc_mac_xmit(struct sk_buff *skb, struct net_device *dev);
423
424void wilc_wfi_p2p_rx(struct wilc_vif *vif, u8 *buff, u32 size);
425void host_wakeup_notify(struct wilc *wilc);
426void host_sleep_notify(struct wilc *wilc);
427void chip_allow_sleep(struct wilc *wilc);
428void chip_wakeup(struct wilc *wilc);
429int wilc_send_config_pkt(struct wilc_vif *vif, u8 mode, struct wid *wids,
430 u32 count);
431int wilc_wlan_init(struct net_device *dev);
432u32 wilc_get_chipid(struct wilc *wilc, bool update);
433#endif