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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries.
4 * All rights reserved.
5 */
6
7#ifndef WILC_WLAN_H
8#define WILC_WLAN_H
9
10#include <linux/types.h>
11#include <linux/bitfield.h>
12
13/********************************************
14 *
15 * Mac eth header length
16 *
17 ********************************************/
18#define MAX_MAC_HDR_LEN 26 /* QOS_MAC_HDR_LEN */
19#define SUB_MSDU_HEADER_LENGTH 14
20#define SNAP_HDR_LEN 8
21#define ETHERNET_HDR_LEN 14
22#define WORD_ALIGNMENT_PAD 0
23
24#define ETH_ETHERNET_HDR_OFFSET (MAX_MAC_HDR_LEN + \
25 SUB_MSDU_HEADER_LENGTH + \
26 SNAP_HDR_LEN - \
27 ETHERNET_HDR_LEN + \
28 WORD_ALIGNMENT_PAD)
29
30#define HOST_HDR_OFFSET 4
31#define ETHERNET_HDR_LEN 14
32#define IP_HDR_LEN 20
33#define IP_HDR_OFFSET ETHERNET_HDR_LEN
34#define UDP_HDR_OFFSET (IP_HDR_LEN + IP_HDR_OFFSET)
35#define UDP_HDR_LEN 8
36#define UDP_DATA_OFFSET (UDP_HDR_OFFSET + UDP_HDR_LEN)
37#define ETH_CONFIG_PKT_HDR_LEN UDP_DATA_OFFSET
38
39#define ETH_CONFIG_PKT_HDR_OFFSET (ETH_ETHERNET_HDR_OFFSET + \
40 ETH_CONFIG_PKT_HDR_LEN)
41
42/********************************************
43 *
44 * Register Defines
45 *
46 ********************************************/
47#define WILC_PERIPH_REG_BASE 0x1000
48#define WILC_CHANGING_VIR_IF 0x108c
49#define WILC_CHIPID WILC_PERIPH_REG_BASE
50#define WILC_GLB_RESET_0 (WILC_PERIPH_REG_BASE + 0x400)
51#define WILC_PIN_MUX_0 (WILC_PERIPH_REG_BASE + 0x408)
52#define WILC_HOST_TX_CTRL (WILC_PERIPH_REG_BASE + 0x6c)
53#define WILC_HOST_RX_CTRL_0 (WILC_PERIPH_REG_BASE + 0x70)
54#define WILC_HOST_RX_CTRL_1 (WILC_PERIPH_REG_BASE + 0x74)
55#define WILC_HOST_VMM_CTL (WILC_PERIPH_REG_BASE + 0x78)
56#define WILC_HOST_RX_CTRL (WILC_PERIPH_REG_BASE + 0x80)
57#define WILC_HOST_RX_EXTRA_SIZE (WILC_PERIPH_REG_BASE + 0x84)
58#define WILC_HOST_TX_CTRL_1 (WILC_PERIPH_REG_BASE + 0x88)
59#define WILC_MISC (WILC_PERIPH_REG_BASE + 0x428)
60#define WILC_INTR_REG_BASE (WILC_PERIPH_REG_BASE + 0xa00)
61#define WILC_INTR_ENABLE WILC_INTR_REG_BASE
62#define WILC_INTR2_ENABLE (WILC_INTR_REG_BASE + 4)
63
64#define WILC_INTR_POLARITY (WILC_INTR_REG_BASE + 0x10)
65#define WILC_INTR_TYPE (WILC_INTR_REG_BASE + 0x20)
66#define WILC_INTR_CLEAR (WILC_INTR_REG_BASE + 0x30)
67#define WILC_INTR_STATUS (WILC_INTR_REG_BASE + 0x40)
68
69#define WILC_RF_REVISION_ID 0x13f4
70
71#define WILC_VMM_TBL_SIZE 64
72#define WILC_VMM_TX_TBL_BASE 0x150400
73#define WILC_VMM_RX_TBL_BASE 0x150500
74
75#define WILC_VMM_BASE 0x150000
76#define WILC_VMM_CORE_CTL WILC_VMM_BASE
77#define WILC_VMM_TBL_CTL (WILC_VMM_BASE + 0x4)
78#define WILC_VMM_TBL_ENTRY (WILC_VMM_BASE + 0x8)
79#define WILC_VMM_TBL0_SIZE (WILC_VMM_BASE + 0xc)
80#define WILC_VMM_TO_HOST_SIZE (WILC_VMM_BASE + 0x10)
81#define WILC_VMM_CORE_CFG (WILC_VMM_BASE + 0x14)
82#define WILC_VMM_TBL_ACTIVE (WILC_VMM_BASE + 040)
83#define WILC_VMM_TBL_STATUS (WILC_VMM_BASE + 0x44)
84
85#define WILC_SPI_REG_BASE 0xe800
86#define WILC_SPI_CTL WILC_SPI_REG_BASE
87#define WILC_SPI_MASTER_DMA_ADDR (WILC_SPI_REG_BASE + 0x4)
88#define WILC_SPI_MASTER_DMA_COUNT (WILC_SPI_REG_BASE + 0x8)
89#define WILC_SPI_SLAVE_DMA_ADDR (WILC_SPI_REG_BASE + 0xc)
90#define WILC_SPI_SLAVE_DMA_COUNT (WILC_SPI_REG_BASE + 0x10)
91#define WILC_SPI_TX_MODE (WILC_SPI_REG_BASE + 0x20)
92#define WILC_SPI_PROTOCOL_CONFIG (WILC_SPI_REG_BASE + 0x24)
93#define WILC_SPI_INTR_CTL (WILC_SPI_REG_BASE + 0x2c)
94#define WILC_SPI_INT_STATUS (WILC_SPI_REG_BASE + 0x40)
95#define WILC_SPI_INT_CLEAR (WILC_SPI_REG_BASE + 0x44)
96
97#define WILC_SPI_WAKEUP_REG 0x1
98#define WILC_SPI_WAKEUP_BIT BIT(1)
99
100#define WILC_SPI_CLK_STATUS_REG 0x0f
101#define WILC_SPI_CLK_STATUS_BIT BIT(2)
102#define WILC_SPI_HOST_TO_FW_REG 0x0b
103#define WILC_SPI_HOST_TO_FW_BIT BIT(0)
104
105#define WILC_SPI_FW_TO_HOST_REG 0x10
106#define WILC_SPI_FW_TO_HOST_BIT BIT(0)
107
108#define WILC_SPI_PROTOCOL_OFFSET (WILC_SPI_PROTOCOL_CONFIG - \
109 WILC_SPI_REG_BASE)
110
111#define WILC_SPI_CLOCKLESS_ADDR_LIMIT 0x30
112
113/* Functions IO enables bits */
114#define WILC_SDIO_CCCR_IO_EN_FUNC1 BIT(1)
115
116/* Function/Interrupt enables bits */
117#define WILC_SDIO_CCCR_IEN_MASTER BIT(0)
118#define WILC_SDIO_CCCR_IEN_FUNC1 BIT(1)
119
120/* Abort CCCR register bits */
121#define WILC_SDIO_CCCR_ABORT_RESET BIT(3)
122
123/* Vendor specific CCCR registers */
124#define WILC_SDIO_WAKEUP_REG 0xf0
125#define WILC_SDIO_WAKEUP_BIT BIT(0)
126
127#define WILC_SDIO_CLK_STATUS_REG 0xf1
128#define WILC_SDIO_CLK_STATUS_BIT BIT(0)
129
130#define WILC_SDIO_INTERRUPT_DATA_SZ_REG 0xf2 /* Read size (2 bytes) */
131
132#define WILC_SDIO_VMM_TBL_CTRL_REG 0xf6
133#define WILC_SDIO_IRQ_FLAG_REG 0xf7
134#define WILC_SDIO_IRQ_CLEAR_FLAG_REG 0xf8
135
136#define WILC_SDIO_HOST_TO_FW_REG 0xfa
137#define WILC_SDIO_HOST_TO_FW_BIT BIT(0)
138
139#define WILC_SDIO_FW_TO_HOST_REG 0xfc
140#define WILC_SDIO_FW_TO_HOST_BIT BIT(0)
141
142/* Function 1 specific FBR register */
143#define WILC_SDIO_FBR_CSA_REG 0x10C /* CSA pointer (3 bytes) */
144#define WILC_SDIO_FBR_DATA_REG 0x10F
145
146#define WILC_SDIO_F1_DATA_REG 0x0
147#define WILC_SDIO_EXT_IRQ_FLAG_REG 0x4
148
149#define WILC_AHB_DATA_MEM_BASE 0x30000
150#define WILC_AHB_SHARE_MEM_BASE 0xd0000
151
152#define WILC_VMM_TBL_RX_SHADOW_BASE WILC_AHB_SHARE_MEM_BASE
153#define WILC_VMM_TBL_RX_SHADOW_SIZE 256
154
155#define WILC_FW_HOST_COMM 0x13c0
156#define WILC_GP_REG_0 0x149c
157#define WILC_GP_REG_1 0x14a0
158
159#define GLOBAL_MODE_CONTROL 0x1614
160#define PWR_SEQ_MISC_CTRL 0x3008
161
162#define WILC_GLOBAL_MODE_ENABLE_WIFI BIT(0)
163#define WILC_PWR_SEQ_ENABLE_WIFI_SLEEP BIT(28)
164
165#define WILC_HAVE_SDIO_IRQ_GPIO BIT(0)
166#define WILC_HAVE_USE_PMU BIT(1)
167#define WILC_HAVE_SLEEP_CLK_SRC_RTC BIT(2)
168#define WILC_HAVE_SLEEP_CLK_SRC_XO BIT(3)
169#define WILC_HAVE_EXT_PA_INV_TX_RX BIT(4)
170#define WILC_HAVE_LEGACY_RF_SETTINGS BIT(5)
171#define WILC_HAVE_XTAL_24 BIT(6)
172#define WILC_HAVE_DISABLE_WILC_UART BIT(7)
173#define WILC_HAVE_USE_IRQ_AS_HOST_WAKE BIT(8)
174
175#define WILC_CORTUS_INTERRUPT_BASE 0x10A8
176#define WILC_CORTUS_INTERRUPT_1 (WILC_CORTUS_INTERRUPT_BASE + 0x4)
177#define WILC_CORTUS_INTERRUPT_2 (WILC_CORTUS_INTERRUPT_BASE + 0x8)
178
179/* tx control register 1 to 4 for RX */
180#define WILC_REG_4_TO_1_RX 0x1e1c
181
182/* tx control register 1 to 4 for TX Bank_0 */
183#define WILC_REG_4_TO_1_TX_BANK0 0x1e9c
184
185#define WILC_CORTUS_RESET_MUX_SEL 0x1118
186#define WILC_CORTUS_BOOT_REGISTER 0xc0000
187
188#define WILC_CORTUS_BOOT_FROM_IRAM 0x71
189
190#define WILC_1000_BASE_ID 0x100000
191
192#define WILC_1000_BASE_ID_2A 0x1002A0
193#define WILC_1000_BASE_ID_2A_REV1 (WILC_1000_BASE_ID_2A + 1)
194
195#define WILC_1000_BASE_ID_2B 0x1002B0
196#define WILC_1000_BASE_ID_2B_REV1 (WILC_1000_BASE_ID_2B + 1)
197#define WILC_1000_BASE_ID_2B_REV2 (WILC_1000_BASE_ID_2B + 2)
198
199#define WILC_CHIP_REV_FIELD GENMASK(11, 0)
200
201/********************************************
202 *
203 * Wlan Defines
204 *
205 ********************************************/
206#define WILC_CFG_PKT 1
207#define WILC_NET_PKT 0
208#define WILC_MGMT_PKT 2
209
210#define WILC_CFG_SET 1
211#define WILC_CFG_QUERY 0
212
213#define WILC_CFG_RSP 1
214#define WILC_CFG_RSP_STATUS 2
215#define WILC_CFG_RSP_SCAN 3
216
217#define WILC_ABORT_REQ_BIT BIT(31)
218
219#define WILC_RX_BUFF_SIZE (96 * 1024)
220#define WILC_TX_BUFF_SIZE (64 * 1024)
221
222#define NQUEUES 4
223#define AC_BUFFER_SIZE 1000
224
225#define VO_AC_COUNT_FIELD GENMASK(31, 25)
226#define VO_AC_ACM_STAT_FIELD BIT(24)
227#define VI_AC_COUNT_FIELD GENMASK(23, 17)
228#define VI_AC_ACM_STAT_FIELD BIT(16)
229#define BE_AC_COUNT_FIELD GENMASK(15, 9)
230#define BE_AC_ACM_STAT_FIELD BIT(8)
231#define BK_AC_COUNT_FIELD GENMASK(7, 3)
232#define BK_AC_ACM_STAT_FIELD BIT(1)
233
234#define WILC_PKT_HDR_CONFIG_FIELD BIT(31)
235#define WILC_PKT_HDR_OFFSET_FIELD GENMASK(30, 22)
236#define WILC_PKT_HDR_TOTAL_LEN_FIELD GENMASK(21, 11)
237#define WILC_PKT_HDR_LEN_FIELD GENMASK(10, 0)
238
239#define WILC_INTERRUPT_DATA_SIZE GENMASK(14, 0)
240
241#define WILC_VMM_BUFFER_SIZE GENMASK(9, 0)
242
243#define WILC_VMM_HDR_TYPE BIT(31)
244#define WILC_VMM_HDR_MGMT_FIELD BIT(30)
245#define WILC_VMM_HDR_PKT_SIZE GENMASK(29, 15)
246#define WILC_VMM_HDR_BUFF_SIZE GENMASK(14, 0)
247
248#define WILC_VMM_ENTRY_COUNT GENMASK(8, 3)
249#define WILC_VMM_ENTRY_AVAILABLE BIT(2)
250/*******************************************/
251/* E0 and later Interrupt flags. */
252/*******************************************/
253/*******************************************/
254/* E0 and later Interrupt flags. */
255/* IRQ Status word */
256/* 15:0 = DMA count in words. */
257/* 16: INT0 flag */
258/* 17: INT1 flag */
259/* 18: INT2 flag */
260/* 19: INT3 flag */
261/* 20: INT4 flag */
262/* 21: INT5 flag */
263/*******************************************/
264#define IRG_FLAGS_OFFSET 16
265#define IRQ_DMA_WD_CNT_MASK GENMASK(IRG_FLAGS_OFFSET - 1, 0)
266#define INT_0 BIT(IRG_FLAGS_OFFSET)
267#define INT_1 BIT(IRG_FLAGS_OFFSET + 1)
268#define INT_2 BIT(IRG_FLAGS_OFFSET + 2)
269#define INT_3 BIT(IRG_FLAGS_OFFSET + 3)
270#define INT_4 BIT(IRG_FLAGS_OFFSET + 4)
271#define INT_5 BIT(IRG_FLAGS_OFFSET + 5)
272#define MAX_NUM_INT 5
273#define IRG_FLAGS_MASK GENMASK(IRG_FLAGS_OFFSET + MAX_NUM_INT, \
274 IRG_FLAGS_OFFSET)
275
276/*******************************************/
277/* E0 and later Interrupt flags. */
278/* IRQ Clear word */
279/* 0: Clear INT0 */
280/* 1: Clear INT1 */
281/* 2: Clear INT2 */
282/* 3: Clear INT3 */
283/* 4: Clear INT4 */
284/* 5: Clear INT5 */
285/* 6: Select VMM table 1 */
286/* 7: Select VMM table 2 */
287/* 8: Enable VMM */
288/*******************************************/
289#define CLR_INT0 BIT(0)
290#define CLR_INT1 BIT(1)
291#define CLR_INT2 BIT(2)
292#define CLR_INT3 BIT(3)
293#define CLR_INT4 BIT(4)
294#define CLR_INT5 BIT(5)
295#define SEL_VMM_TBL0 BIT(6)
296#define SEL_VMM_TBL1 BIT(7)
297#define EN_VMM BIT(8)
298
299#define DATA_INT_EXT INT_0
300#define ALL_INT_EXT DATA_INT_EXT
301#define NUM_INT_EXT 1
302#define UNHANDLED_IRQ_MASK GENMASK(MAX_NUM_INT - 1, NUM_INT_EXT)
303
304#define DATA_INT_CLR CLR_INT0
305
306#define ENABLE_RX_VMM (SEL_VMM_TBL1 | EN_VMM)
307#define ENABLE_TX_VMM (SEL_VMM_TBL0 | EN_VMM)
308/* time for expiring the completion of cfg packets */
309#define WILC_CFG_PKTS_TIMEOUT msecs_to_jiffies(3000)
310
311#define IS_MANAGMEMENT 0x100
312#define IS_MANAGMEMENT_CALLBACK 0x080
313#define IS_MGMT_STATUS_SUCCES 0x040
314#define IS_MGMT_AUTH_PKT 0x010
315
316#define WILC_WID_TYPE GENMASK(15, 12)
317#define WILC_VMM_ENTRY_FULL_RETRY 1
318/********************************************
319 *
320 * Tx/Rx Queue Structure
321 *
322 ********************************************/
323enum ip_pkt_priority {
324 AC_VO_Q = 0,
325 AC_VI_Q = 1,
326 AC_BE_Q = 2,
327 AC_BK_Q = 3
328};
329
330struct txq_entry_t {
331 struct list_head list;
332 int type;
333 u8 q_num;
334 int ack_idx;
335 u8 *buffer;
336 int buffer_size;
337 void *priv;
338 int status;
339 struct wilc_vif *vif;
340 void (*tx_complete_func)(void *priv, int status);
341};
342
343struct txq_fw_recv_queue_stat {
344 u8 acm;
345 u8 count;
346};
347
348struct txq_handle {
349 struct txq_entry_t txq_head;
350 u16 count;
351 struct txq_fw_recv_queue_stat fw;
352};
353
354struct rxq_entry_t {
355 struct list_head list;
356 u8 *buffer;
357 int buffer_size;
358};
359
360/********************************************
361 *
362 * Host IF Structure
363 *
364 ********************************************/
365struct wilc;
366struct wilc_hif_func {
367 int (*hif_init)(struct wilc *wilc, bool resume);
368 int (*hif_deinit)(struct wilc *wilc);
369 int (*hif_read_reg)(struct wilc *wilc, u32 addr, u32 *data);
370 int (*hif_write_reg)(struct wilc *wilc, u32 addr, u32 data);
371 int (*hif_block_rx)(struct wilc *wilc, u32 addr, u8 *buf, u32 size);
372 int (*hif_block_tx)(struct wilc *wilc, u32 addr, u8 *buf, u32 size);
373 int (*hif_read_int)(struct wilc *wilc, u32 *int_status);
374 int (*hif_clear_int_ext)(struct wilc *wilc, u32 val);
375 int (*hif_read_size)(struct wilc *wilc, u32 *size);
376 int (*hif_block_tx_ext)(struct wilc *wilc, u32 addr, u8 *buf, u32 size);
377 int (*hif_block_rx_ext)(struct wilc *wilc, u32 addr, u8 *buf, u32 size);
378 int (*hif_sync_ext)(struct wilc *wilc, int nint);
379 int (*enable_interrupt)(struct wilc *nic);
380 void (*disable_interrupt)(struct wilc *nic);
381 int (*hif_reset)(struct wilc *wilc);
382 bool (*hif_is_init)(struct wilc *wilc);
383};
384
385#define WILC_MAX_CFG_FRAME_SIZE 1468
386
387struct tx_complete_data {
388 int size;
389 void *buff;
390 struct sk_buff *skb;
391};
392
393struct wilc_cfg_cmd_hdr {
394 u8 cmd_type;
395 u8 seq_no;
396 __le16 total_len;
397 __le32 driver_handler;
398};
399
400struct wilc_cfg_frame {
401 struct wilc_cfg_cmd_hdr hdr;
402 u8 frame[WILC_MAX_CFG_FRAME_SIZE];
403};
404
405struct wilc_cfg_rsp {
406 u8 type;
407 u8 seq_no;
408};
409
410struct wilc_vif;
411
412static inline bool is_wilc1000(u32 id)
413{
414 return (id & (~WILC_CHIP_REV_FIELD)) == WILC_1000_BASE_ID;
415}
416
417int wilc_wlan_firmware_download(struct wilc *wilc, const u8 *buffer,
418 u32 buffer_size);
419int wilc_wlan_start(struct wilc *wilc);
420int wilc_wlan_stop(struct wilc *wilc, struct wilc_vif *vif);
421int wilc_wlan_txq_add_net_pkt(struct net_device *dev,
422 struct tx_complete_data *tx_data, u8 *buffer,
423 u32 buffer_size,
424 void (*tx_complete_fn)(void *, int));
425int wilc_wlan_handle_txq(struct wilc *wl, u32 *txq_count);
426void wilc_handle_isr(struct wilc *wilc);
427void wilc_wlan_cleanup(struct net_device *dev);
428int wilc_wlan_cfg_set(struct wilc_vif *vif, int start, u16 wid, u8 *buffer,
429 u32 buffer_size, int commit, u32 drv_handler);
430int wilc_wlan_cfg_get(struct wilc_vif *vif, int start, u16 wid, int commit,
431 u32 drv_handler);
432int wilc_wlan_txq_add_mgmt_pkt(struct net_device *dev, void *priv, u8 *buffer,
433 u32 buffer_size, void (*func)(void *, int));
434void wilc_enable_tcp_ack_filter(struct wilc_vif *vif, bool value);
435int wilc_wlan_get_num_conn_ifcs(struct wilc *wilc);
436netdev_tx_t wilc_mac_xmit(struct sk_buff *skb, struct net_device *dev);
437
438void wilc_wfi_p2p_rx(struct wilc_vif *vif, u8 *buff, u32 size);
439bool wilc_wfi_mgmt_frame_rx(struct wilc_vif *vif, u8 *buff, u32 size);
440void host_wakeup_notify(struct wilc *wilc);
441void host_sleep_notify(struct wilc *wilc);
442void chip_allow_sleep(struct wilc *wilc);
443void chip_wakeup(struct wilc *wilc);
444int wilc_send_config_pkt(struct wilc_vif *vif, u8 mode, struct wid *wids,
445 u32 count);
446int wilc_wlan_init(struct net_device *dev);
447u32 wilc_get_chipid(struct wilc *wilc, bool update);
448#endif