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1/*
2 * i.MX IPUv3 DP Overlay Planes
3 *
4 * Copyright (C) 2013 Philipp Zabel, Pengutronix
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <drm/drmP.h>
17#include <drm/drm_fb_cma_helper.h>
18#include <drm/drm_gem_cma_helper.h>
19
20#include "video/imx-ipu-v3.h"
21#include "ipuv3-plane.h"
22
23#define to_ipu_plane(x) container_of(x, struct ipu_plane, base)
24
25static const uint32_t ipu_plane_formats[] = {
26 DRM_FORMAT_ARGB1555,
27 DRM_FORMAT_XRGB1555,
28 DRM_FORMAT_ABGR1555,
29 DRM_FORMAT_XBGR1555,
30 DRM_FORMAT_RGBA5551,
31 DRM_FORMAT_BGRA5551,
32 DRM_FORMAT_ARGB4444,
33 DRM_FORMAT_ARGB8888,
34 DRM_FORMAT_XRGB8888,
35 DRM_FORMAT_ABGR8888,
36 DRM_FORMAT_XBGR8888,
37 DRM_FORMAT_RGBA8888,
38 DRM_FORMAT_RGBX8888,
39 DRM_FORMAT_BGRA8888,
40 DRM_FORMAT_BGRA8888,
41 DRM_FORMAT_YUYV,
42 DRM_FORMAT_YVYU,
43 DRM_FORMAT_YUV420,
44 DRM_FORMAT_YVU420,
45 DRM_FORMAT_RGB565,
46};
47
48int ipu_plane_irq(struct ipu_plane *ipu_plane)
49{
50 return ipu_idmac_channel_irq(ipu_plane->ipu, ipu_plane->ipu_ch,
51 IPU_IRQ_EOF);
52}
53
54static int calc_vref(struct drm_display_mode *mode)
55{
56 unsigned long htotal, vtotal;
57
58 htotal = mode->htotal;
59 vtotal = mode->vtotal;
60
61 if (!htotal || !vtotal)
62 return 60;
63
64 return DIV_ROUND_UP(mode->clock * 1000, vtotal * htotal);
65}
66
67static inline int calc_bandwidth(int width, int height, unsigned int vref)
68{
69 return width * height * vref;
70}
71
72int ipu_plane_set_base(struct ipu_plane *ipu_plane, struct drm_framebuffer *fb,
73 int x, int y)
74{
75 struct drm_gem_cma_object *cma_obj[3];
76 unsigned long eba, ubo, vbo;
77 int active, i;
78
79 for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
80 cma_obj[i] = drm_fb_cma_get_gem_obj(fb, i);
81 if (!cma_obj[i]) {
82 DRM_DEBUG_KMS("plane %d entry is null.\n", i);
83 return -EFAULT;
84 }
85 }
86
87 eba = cma_obj[0]->paddr + fb->offsets[0] +
88 fb->pitches[0] * y + (fb->bits_per_pixel >> 3) * x;
89
90 if (eba & 0x7) {
91 DRM_DEBUG_KMS("base address must be a multiple of 8.\n");
92 return -EINVAL;
93 }
94
95 if (fb->pitches[0] < 1 || fb->pitches[0] > 16384) {
96 DRM_DEBUG_KMS("pitches out of range.\n");
97 return -EINVAL;
98 }
99
100 if (ipu_plane->enabled && fb->pitches[0] != ipu_plane->stride[0]) {
101 DRM_DEBUG_KMS("pitches must not change while plane is enabled.\n");
102 return -EINVAL;
103 }
104
105 ipu_plane->stride[0] = fb->pitches[0];
106
107 switch (fb->pixel_format) {
108 case DRM_FORMAT_YUV420:
109 case DRM_FORMAT_YVU420:
110 /*
111 * Multiplanar formats have to meet the following restrictions:
112 * - The (up to) three plane addresses are EBA, EBA+UBO, EBA+VBO
113 * - EBA, UBO and VBO are a multiple of 8
114 * - UBO and VBO are unsigned and not larger than 0xfffff8
115 * - Only EBA may be changed while scanout is active
116 * - The strides of U and V planes must be identical.
117 */
118 ubo = cma_obj[1]->paddr + fb->offsets[1] +
119 fb->pitches[1] * y / 2 + x / 2 - eba;
120 vbo = cma_obj[2]->paddr + fb->offsets[2] +
121 fb->pitches[2] * y / 2 + x / 2 - eba;
122
123 if ((ubo & 0x7) || (vbo & 0x7)) {
124 DRM_DEBUG_KMS("U/V buffer offsets must be a multiple of 8.\n");
125 return -EINVAL;
126 }
127
128 if ((ubo > 0xfffff8) || (vbo > 0xfffff8)) {
129 DRM_DEBUG_KMS("U/V buffer offsets must be positive and not larger than 0xfffff8.\n");
130 return -EINVAL;
131 }
132
133 if (ipu_plane->enabled && ((ipu_plane->u_offset != ubo) ||
134 (ipu_plane->v_offset != vbo))) {
135 DRM_DEBUG_KMS("U/V buffer offsets must not change while plane is enabled.\n");
136 return -EINVAL;
137 }
138
139 if (fb->pitches[1] != fb->pitches[2]) {
140 DRM_DEBUG_KMS("U/V pitches must be identical.\n");
141 return -EINVAL;
142 }
143
144 if (fb->pitches[1] < 1 || fb->pitches[1] > 16384) {
145 DRM_DEBUG_KMS("U/V pitches out of range.\n");
146 return -EINVAL;
147 }
148
149 if (ipu_plane->enabled &&
150 (ipu_plane->stride[1] != fb->pitches[1])) {
151 DRM_DEBUG_KMS("U/V pitches must not change while plane is enabled.\n");
152 return -EINVAL;
153 }
154
155 ipu_plane->u_offset = ubo;
156 ipu_plane->v_offset = vbo;
157 ipu_plane->stride[1] = fb->pitches[1];
158
159 dev_dbg(ipu_plane->base.dev->dev,
160 "phys = %pad %pad %pad, x = %d, y = %d",
161 &cma_obj[0]->paddr, &cma_obj[1]->paddr,
162 &cma_obj[2]->paddr, x, y);
163 break;
164 default:
165 dev_dbg(ipu_plane->base.dev->dev, "phys = %pad, x = %d, y = %d",
166 &cma_obj[0]->paddr, x, y);
167 break;
168 }
169
170 if (ipu_plane->enabled) {
171 active = ipu_idmac_get_current_buffer(ipu_plane->ipu_ch);
172 ipu_cpmem_set_buffer(ipu_plane->ipu_ch, !active, eba);
173 ipu_idmac_select_buffer(ipu_plane->ipu_ch, !active);
174 } else {
175 ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 0, eba);
176 ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 1, eba);
177 }
178
179 /* cache offsets for subsequent pageflips */
180 ipu_plane->x = x;
181 ipu_plane->y = y;
182
183 return 0;
184}
185
186int ipu_plane_mode_set(struct ipu_plane *ipu_plane, struct drm_crtc *crtc,
187 struct drm_display_mode *mode,
188 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
189 unsigned int crtc_w, unsigned int crtc_h,
190 uint32_t src_x, uint32_t src_y,
191 uint32_t src_w, uint32_t src_h, bool interlaced)
192{
193 struct device *dev = ipu_plane->base.dev->dev;
194 int ret;
195
196 /* no scaling */
197 if (src_w != crtc_w || src_h != crtc_h)
198 return -EINVAL;
199
200 /* clip to crtc bounds */
201 if (crtc_x < 0) {
202 if (-crtc_x > crtc_w)
203 return -EINVAL;
204 src_x += -crtc_x;
205 src_w -= -crtc_x;
206 crtc_w -= -crtc_x;
207 crtc_x = 0;
208 }
209 if (crtc_y < 0) {
210 if (-crtc_y > crtc_h)
211 return -EINVAL;
212 src_y += -crtc_y;
213 src_h -= -crtc_y;
214 crtc_h -= -crtc_y;
215 crtc_y = 0;
216 }
217 if (crtc_x + crtc_w > mode->hdisplay) {
218 if (crtc_x > mode->hdisplay)
219 return -EINVAL;
220 crtc_w = mode->hdisplay - crtc_x;
221 src_w = crtc_w;
222 }
223 if (crtc_y + crtc_h > mode->vdisplay) {
224 if (crtc_y > mode->vdisplay)
225 return -EINVAL;
226 crtc_h = mode->vdisplay - crtc_y;
227 src_h = crtc_h;
228 }
229 /* full plane minimum width is 13 pixels */
230 if (crtc_w < 13 && (ipu_plane->dp_flow != IPU_DP_FLOW_SYNC_FG))
231 return -EINVAL;
232 if (crtc_h < 2)
233 return -EINVAL;
234
235 /*
236 * since we cannot touch active IDMAC channels, we do not support
237 * resizing the enabled plane or changing its format
238 */
239 if (ipu_plane->enabled) {
240 if (src_w != ipu_plane->w || src_h != ipu_plane->h ||
241 fb->pixel_format != ipu_plane->base.fb->pixel_format)
242 return -EINVAL;
243
244 return ipu_plane_set_base(ipu_plane, fb, src_x, src_y);
245 }
246
247 switch (ipu_plane->dp_flow) {
248 case IPU_DP_FLOW_SYNC_BG:
249 ret = ipu_dp_setup_channel(ipu_plane->dp,
250 IPUV3_COLORSPACE_RGB,
251 IPUV3_COLORSPACE_RGB);
252 if (ret) {
253 dev_err(dev,
254 "initializing display processor failed with %d\n",
255 ret);
256 return ret;
257 }
258 ipu_dp_set_global_alpha(ipu_plane->dp, true, 0, true);
259 break;
260 case IPU_DP_FLOW_SYNC_FG:
261 ipu_dp_setup_channel(ipu_plane->dp,
262 ipu_drm_fourcc_to_colorspace(fb->pixel_format),
263 IPUV3_COLORSPACE_UNKNOWN);
264 ipu_dp_set_window_pos(ipu_plane->dp, crtc_x, crtc_y);
265 /* Enable local alpha on partial plane */
266 switch (fb->pixel_format) {
267 case DRM_FORMAT_ARGB1555:
268 case DRM_FORMAT_ABGR1555:
269 case DRM_FORMAT_RGBA5551:
270 case DRM_FORMAT_BGRA5551:
271 case DRM_FORMAT_ARGB4444:
272 case DRM_FORMAT_ARGB8888:
273 case DRM_FORMAT_ABGR8888:
274 case DRM_FORMAT_RGBA8888:
275 case DRM_FORMAT_BGRA8888:
276 ipu_dp_set_global_alpha(ipu_plane->dp, false, 0, false);
277 break;
278 default:
279 break;
280 }
281 }
282
283 ret = ipu_dmfc_alloc_bandwidth(ipu_plane->dmfc,
284 calc_bandwidth(crtc_w, crtc_h,
285 calc_vref(mode)), 64);
286 if (ret) {
287 dev_err(dev, "allocating dmfc bandwidth failed with %d\n", ret);
288 return ret;
289 }
290
291 ipu_dmfc_config_wait4eot(ipu_plane->dmfc, crtc_w);
292
293 ipu_cpmem_zero(ipu_plane->ipu_ch);
294 ipu_cpmem_set_resolution(ipu_plane->ipu_ch, src_w, src_h);
295 ret = ipu_cpmem_set_fmt(ipu_plane->ipu_ch, fb->pixel_format);
296 if (ret < 0) {
297 dev_err(dev, "unsupported pixel format 0x%08x\n",
298 fb->pixel_format);
299 return ret;
300 }
301 ipu_cpmem_set_high_priority(ipu_plane->ipu_ch);
302 ipu_idmac_set_double_buffer(ipu_plane->ipu_ch, 1);
303 ipu_cpmem_set_stride(ipu_plane->ipu_ch, fb->pitches[0]);
304
305 ret = ipu_plane_set_base(ipu_plane, fb, src_x, src_y);
306 if (ret < 0)
307 return ret;
308 if (interlaced)
309 ipu_cpmem_interlaced_scan(ipu_plane->ipu_ch, fb->pitches[0]);
310
311 if (fb->pixel_format == DRM_FORMAT_YUV420) {
312 ipu_cpmem_set_yuv_planar_full(ipu_plane->ipu_ch,
313 ipu_plane->stride[1],
314 ipu_plane->u_offset,
315 ipu_plane->v_offset);
316 } else if (fb->pixel_format == DRM_FORMAT_YVU420) {
317 ipu_cpmem_set_yuv_planar_full(ipu_plane->ipu_ch,
318 ipu_plane->stride[1],
319 ipu_plane->v_offset,
320 ipu_plane->u_offset);
321 }
322
323 ipu_plane->w = src_w;
324 ipu_plane->h = src_h;
325
326 return 0;
327}
328
329void ipu_plane_put_resources(struct ipu_plane *ipu_plane)
330{
331 if (!IS_ERR_OR_NULL(ipu_plane->dp))
332 ipu_dp_put(ipu_plane->dp);
333 if (!IS_ERR_OR_NULL(ipu_plane->dmfc))
334 ipu_dmfc_put(ipu_plane->dmfc);
335 if (!IS_ERR_OR_NULL(ipu_plane->ipu_ch))
336 ipu_idmac_put(ipu_plane->ipu_ch);
337}
338
339int ipu_plane_get_resources(struct ipu_plane *ipu_plane)
340{
341 int ret;
342
343 ipu_plane->ipu_ch = ipu_idmac_get(ipu_plane->ipu, ipu_plane->dma);
344 if (IS_ERR(ipu_plane->ipu_ch)) {
345 ret = PTR_ERR(ipu_plane->ipu_ch);
346 DRM_ERROR("failed to get idmac channel: %d\n", ret);
347 return ret;
348 }
349
350 ipu_plane->dmfc = ipu_dmfc_get(ipu_plane->ipu, ipu_plane->dma);
351 if (IS_ERR(ipu_plane->dmfc)) {
352 ret = PTR_ERR(ipu_plane->dmfc);
353 DRM_ERROR("failed to get dmfc: ret %d\n", ret);
354 goto err_out;
355 }
356
357 if (ipu_plane->dp_flow >= 0) {
358 ipu_plane->dp = ipu_dp_get(ipu_plane->ipu, ipu_plane->dp_flow);
359 if (IS_ERR(ipu_plane->dp)) {
360 ret = PTR_ERR(ipu_plane->dp);
361 DRM_ERROR("failed to get dp flow: %d\n", ret);
362 goto err_out;
363 }
364 }
365
366 return 0;
367err_out:
368 ipu_plane_put_resources(ipu_plane);
369
370 return ret;
371}
372
373void ipu_plane_enable(struct ipu_plane *ipu_plane)
374{
375 if (ipu_plane->dp)
376 ipu_dp_enable(ipu_plane->ipu);
377 ipu_dmfc_enable_channel(ipu_plane->dmfc);
378 ipu_idmac_enable_channel(ipu_plane->ipu_ch);
379 if (ipu_plane->dp)
380 ipu_dp_enable_channel(ipu_plane->dp);
381
382 ipu_plane->enabled = true;
383}
384
385void ipu_plane_disable(struct ipu_plane *ipu_plane)
386{
387 ipu_plane->enabled = false;
388
389 ipu_idmac_wait_busy(ipu_plane->ipu_ch, 50);
390
391 if (ipu_plane->dp)
392 ipu_dp_disable_channel(ipu_plane->dp);
393 ipu_idmac_disable_channel(ipu_plane->ipu_ch);
394 ipu_dmfc_disable_channel(ipu_plane->dmfc);
395 if (ipu_plane->dp)
396 ipu_dp_disable(ipu_plane->ipu);
397}
398
399/*
400 * drm_plane API
401 */
402
403static int ipu_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
404 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
405 unsigned int crtc_w, unsigned int crtc_h,
406 uint32_t src_x, uint32_t src_y,
407 uint32_t src_w, uint32_t src_h)
408{
409 struct ipu_plane *ipu_plane = to_ipu_plane(plane);
410 int ret = 0;
411
412 DRM_DEBUG_KMS("plane - %p\n", plane);
413
414 if (!ipu_plane->enabled)
415 ret = ipu_plane_get_resources(ipu_plane);
416 if (ret < 0)
417 return ret;
418
419 ret = ipu_plane_mode_set(ipu_plane, crtc, &crtc->hwmode, fb,
420 crtc_x, crtc_y, crtc_w, crtc_h,
421 src_x >> 16, src_y >> 16, src_w >> 16, src_h >> 16,
422 false);
423 if (ret < 0) {
424 ipu_plane_put_resources(ipu_plane);
425 return ret;
426 }
427
428 if (crtc != plane->crtc)
429 dev_dbg(plane->dev->dev, "crtc change: %p -> %p\n",
430 plane->crtc, crtc);
431 plane->crtc = crtc;
432
433 if (!ipu_plane->enabled)
434 ipu_plane_enable(ipu_plane);
435
436 return 0;
437}
438
439static int ipu_disable_plane(struct drm_plane *plane)
440{
441 struct ipu_plane *ipu_plane = to_ipu_plane(plane);
442
443 DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
444
445 if (ipu_plane->enabled)
446 ipu_plane_disable(ipu_plane);
447
448 ipu_plane_put_resources(ipu_plane);
449
450 return 0;
451}
452
453static void ipu_plane_destroy(struct drm_plane *plane)
454{
455 struct ipu_plane *ipu_plane = to_ipu_plane(plane);
456
457 DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
458
459 ipu_disable_plane(plane);
460 drm_plane_cleanup(plane);
461 kfree(ipu_plane);
462}
463
464static struct drm_plane_funcs ipu_plane_funcs = {
465 .update_plane = ipu_update_plane,
466 .disable_plane = ipu_disable_plane,
467 .destroy = ipu_plane_destroy,
468};
469
470struct ipu_plane *ipu_plane_init(struct drm_device *dev, struct ipu_soc *ipu,
471 int dma, int dp, unsigned int possible_crtcs,
472 enum drm_plane_type type)
473{
474 struct ipu_plane *ipu_plane;
475 int ret;
476
477 DRM_DEBUG_KMS("channel %d, dp flow %d, possible_crtcs=0x%x\n",
478 dma, dp, possible_crtcs);
479
480 ipu_plane = kzalloc(sizeof(*ipu_plane), GFP_KERNEL);
481 if (!ipu_plane) {
482 DRM_ERROR("failed to allocate plane\n");
483 return ERR_PTR(-ENOMEM);
484 }
485
486 ipu_plane->ipu = ipu;
487 ipu_plane->dma = dma;
488 ipu_plane->dp_flow = dp;
489
490 ret = drm_universal_plane_init(dev, &ipu_plane->base, possible_crtcs,
491 &ipu_plane_funcs, ipu_plane_formats,
492 ARRAY_SIZE(ipu_plane_formats), type,
493 NULL);
494 if (ret) {
495 DRM_ERROR("failed to initialize plane\n");
496 kfree(ipu_plane);
497 return ERR_PTR(ret);
498 }
499
500 return ipu_plane;
501}
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * i.MX IPUv3 DP Overlay Planes
4 *
5 * Copyright (C) 2013 Philipp Zabel, Pengutronix
6 */
7
8#include <drm/drm_atomic.h>
9#include <drm/drm_atomic_helper.h>
10#include <drm/drm_fb_cma_helper.h>
11#include <drm/drm_fourcc.h>
12#include <drm/drm_gem_atomic_helper.h>
13#include <drm/drm_gem_cma_helper.h>
14#include <drm/drm_managed.h>
15#include <drm/drm_plane_helper.h>
16
17#include <video/imx-ipu-v3.h>
18
19#include "imx-drm.h"
20#include "ipuv3-plane.h"
21
22struct ipu_plane_state {
23 struct drm_plane_state base;
24 bool use_pre;
25};
26
27static inline struct ipu_plane_state *
28to_ipu_plane_state(struct drm_plane_state *p)
29{
30 return container_of(p, struct ipu_plane_state, base);
31}
32
33static unsigned int ipu_src_rect_width(const struct drm_plane_state *state)
34{
35 return ALIGN(drm_rect_width(&state->src) >> 16, 8);
36}
37
38static inline struct ipu_plane *to_ipu_plane(struct drm_plane *p)
39{
40 return container_of(p, struct ipu_plane, base);
41}
42
43static const uint32_t ipu_plane_all_formats[] = {
44 DRM_FORMAT_ARGB1555,
45 DRM_FORMAT_XRGB1555,
46 DRM_FORMAT_ABGR1555,
47 DRM_FORMAT_XBGR1555,
48 DRM_FORMAT_RGBA5551,
49 DRM_FORMAT_BGRA5551,
50 DRM_FORMAT_ARGB4444,
51 DRM_FORMAT_ARGB8888,
52 DRM_FORMAT_XRGB8888,
53 DRM_FORMAT_ABGR8888,
54 DRM_FORMAT_XBGR8888,
55 DRM_FORMAT_RGBA8888,
56 DRM_FORMAT_RGBX8888,
57 DRM_FORMAT_BGRA8888,
58 DRM_FORMAT_BGRX8888,
59 DRM_FORMAT_UYVY,
60 DRM_FORMAT_VYUY,
61 DRM_FORMAT_YUYV,
62 DRM_FORMAT_YVYU,
63 DRM_FORMAT_YUV420,
64 DRM_FORMAT_YVU420,
65 DRM_FORMAT_YUV422,
66 DRM_FORMAT_YVU422,
67 DRM_FORMAT_YUV444,
68 DRM_FORMAT_YVU444,
69 DRM_FORMAT_NV12,
70 DRM_FORMAT_NV16,
71 DRM_FORMAT_RGB565,
72 DRM_FORMAT_RGB565_A8,
73 DRM_FORMAT_BGR565_A8,
74 DRM_FORMAT_RGB888_A8,
75 DRM_FORMAT_BGR888_A8,
76 DRM_FORMAT_RGBX8888_A8,
77 DRM_FORMAT_BGRX8888_A8,
78};
79
80static const uint32_t ipu_plane_rgb_formats[] = {
81 DRM_FORMAT_ARGB1555,
82 DRM_FORMAT_XRGB1555,
83 DRM_FORMAT_ABGR1555,
84 DRM_FORMAT_XBGR1555,
85 DRM_FORMAT_RGBA5551,
86 DRM_FORMAT_BGRA5551,
87 DRM_FORMAT_ARGB4444,
88 DRM_FORMAT_ARGB8888,
89 DRM_FORMAT_XRGB8888,
90 DRM_FORMAT_ABGR8888,
91 DRM_FORMAT_XBGR8888,
92 DRM_FORMAT_RGBA8888,
93 DRM_FORMAT_RGBX8888,
94 DRM_FORMAT_BGRA8888,
95 DRM_FORMAT_BGRX8888,
96 DRM_FORMAT_RGB565,
97 DRM_FORMAT_RGB565_A8,
98 DRM_FORMAT_BGR565_A8,
99 DRM_FORMAT_RGB888_A8,
100 DRM_FORMAT_BGR888_A8,
101 DRM_FORMAT_RGBX8888_A8,
102 DRM_FORMAT_BGRX8888_A8,
103};
104
105static const uint64_t ipu_format_modifiers[] = {
106 DRM_FORMAT_MOD_LINEAR,
107 DRM_FORMAT_MOD_INVALID
108};
109
110static const uint64_t pre_format_modifiers[] = {
111 DRM_FORMAT_MOD_LINEAR,
112 DRM_FORMAT_MOD_VIVANTE_TILED,
113 DRM_FORMAT_MOD_VIVANTE_SUPER_TILED,
114 DRM_FORMAT_MOD_INVALID
115};
116
117int ipu_plane_irq(struct ipu_plane *ipu_plane)
118{
119 return ipu_idmac_channel_irq(ipu_plane->ipu, ipu_plane->ipu_ch,
120 IPU_IRQ_EOF);
121}
122
123static inline unsigned long
124drm_plane_state_to_eba(struct drm_plane_state *state, int plane)
125{
126 struct drm_framebuffer *fb = state->fb;
127 struct drm_gem_cma_object *cma_obj;
128 int x = state->src.x1 >> 16;
129 int y = state->src.y1 >> 16;
130
131 cma_obj = drm_fb_cma_get_gem_obj(fb, plane);
132 BUG_ON(!cma_obj);
133
134 return cma_obj->paddr + fb->offsets[plane] + fb->pitches[plane] * y +
135 fb->format->cpp[plane] * x;
136}
137
138static inline unsigned long
139drm_plane_state_to_ubo(struct drm_plane_state *state)
140{
141 struct drm_framebuffer *fb = state->fb;
142 struct drm_gem_cma_object *cma_obj;
143 unsigned long eba = drm_plane_state_to_eba(state, 0);
144 int x = state->src.x1 >> 16;
145 int y = state->src.y1 >> 16;
146
147 cma_obj = drm_fb_cma_get_gem_obj(fb, 1);
148 BUG_ON(!cma_obj);
149
150 x /= fb->format->hsub;
151 y /= fb->format->vsub;
152
153 return cma_obj->paddr + fb->offsets[1] + fb->pitches[1] * y +
154 fb->format->cpp[1] * x - eba;
155}
156
157static inline unsigned long
158drm_plane_state_to_vbo(struct drm_plane_state *state)
159{
160 struct drm_framebuffer *fb = state->fb;
161 struct drm_gem_cma_object *cma_obj;
162 unsigned long eba = drm_plane_state_to_eba(state, 0);
163 int x = state->src.x1 >> 16;
164 int y = state->src.y1 >> 16;
165
166 cma_obj = drm_fb_cma_get_gem_obj(fb, 2);
167 BUG_ON(!cma_obj);
168
169 x /= fb->format->hsub;
170 y /= fb->format->vsub;
171
172 return cma_obj->paddr + fb->offsets[2] + fb->pitches[2] * y +
173 fb->format->cpp[2] * x - eba;
174}
175
176static void ipu_plane_put_resources(struct drm_device *dev, void *ptr)
177{
178 struct ipu_plane *ipu_plane = ptr;
179
180 if (!IS_ERR_OR_NULL(ipu_plane->dp))
181 ipu_dp_put(ipu_plane->dp);
182 if (!IS_ERR_OR_NULL(ipu_plane->dmfc))
183 ipu_dmfc_put(ipu_plane->dmfc);
184 if (!IS_ERR_OR_NULL(ipu_plane->ipu_ch))
185 ipu_idmac_put(ipu_plane->ipu_ch);
186 if (!IS_ERR_OR_NULL(ipu_plane->alpha_ch))
187 ipu_idmac_put(ipu_plane->alpha_ch);
188}
189
190static int ipu_plane_get_resources(struct drm_device *dev,
191 struct ipu_plane *ipu_plane)
192{
193 int ret;
194 int alpha_ch;
195
196 ipu_plane->ipu_ch = ipu_idmac_get(ipu_plane->ipu, ipu_plane->dma);
197 if (IS_ERR(ipu_plane->ipu_ch)) {
198 ret = PTR_ERR(ipu_plane->ipu_ch);
199 DRM_ERROR("failed to get idmac channel: %d\n", ret);
200 return ret;
201 }
202
203 ret = drmm_add_action_or_reset(dev, ipu_plane_put_resources, ipu_plane);
204 if (ret)
205 return ret;
206
207 alpha_ch = ipu_channel_alpha_channel(ipu_plane->dma);
208 if (alpha_ch >= 0) {
209 ipu_plane->alpha_ch = ipu_idmac_get(ipu_plane->ipu, alpha_ch);
210 if (IS_ERR(ipu_plane->alpha_ch)) {
211 ret = PTR_ERR(ipu_plane->alpha_ch);
212 DRM_ERROR("failed to get alpha idmac channel %d: %d\n",
213 alpha_ch, ret);
214 return ret;
215 }
216 }
217
218 ipu_plane->dmfc = ipu_dmfc_get(ipu_plane->ipu, ipu_plane->dma);
219 if (IS_ERR(ipu_plane->dmfc)) {
220 ret = PTR_ERR(ipu_plane->dmfc);
221 DRM_ERROR("failed to get dmfc: ret %d\n", ret);
222 return ret;
223 }
224
225 if (ipu_plane->dp_flow >= 0) {
226 ipu_plane->dp = ipu_dp_get(ipu_plane->ipu, ipu_plane->dp_flow);
227 if (IS_ERR(ipu_plane->dp)) {
228 ret = PTR_ERR(ipu_plane->dp);
229 DRM_ERROR("failed to get dp flow: %d\n", ret);
230 return ret;
231 }
232 }
233
234 return 0;
235}
236
237static bool ipu_plane_separate_alpha(struct ipu_plane *ipu_plane)
238{
239 switch (ipu_plane->base.state->fb->format->format) {
240 case DRM_FORMAT_RGB565_A8:
241 case DRM_FORMAT_BGR565_A8:
242 case DRM_FORMAT_RGB888_A8:
243 case DRM_FORMAT_BGR888_A8:
244 case DRM_FORMAT_RGBX8888_A8:
245 case DRM_FORMAT_BGRX8888_A8:
246 return true;
247 default:
248 return false;
249 }
250}
251
252static void ipu_plane_enable(struct ipu_plane *ipu_plane)
253{
254 if (ipu_plane->dp)
255 ipu_dp_enable(ipu_plane->ipu);
256 ipu_dmfc_enable_channel(ipu_plane->dmfc);
257 ipu_idmac_enable_channel(ipu_plane->ipu_ch);
258 if (ipu_plane_separate_alpha(ipu_plane))
259 ipu_idmac_enable_channel(ipu_plane->alpha_ch);
260 if (ipu_plane->dp)
261 ipu_dp_enable_channel(ipu_plane->dp);
262}
263
264void ipu_plane_disable(struct ipu_plane *ipu_plane, bool disable_dp_channel)
265{
266 int ret;
267
268 DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
269
270 ret = ipu_idmac_wait_busy(ipu_plane->ipu_ch, 50);
271 if (ret == -ETIMEDOUT) {
272 DRM_ERROR("[PLANE:%d] IDMAC timeout\n",
273 ipu_plane->base.base.id);
274 }
275
276 if (ipu_plane->dp && disable_dp_channel)
277 ipu_dp_disable_channel(ipu_plane->dp, false);
278 ipu_idmac_disable_channel(ipu_plane->ipu_ch);
279 if (ipu_plane->alpha_ch)
280 ipu_idmac_disable_channel(ipu_plane->alpha_ch);
281 ipu_dmfc_disable_channel(ipu_plane->dmfc);
282 if (ipu_plane->dp)
283 ipu_dp_disable(ipu_plane->ipu);
284 if (ipu_prg_present(ipu_plane->ipu))
285 ipu_prg_channel_disable(ipu_plane->ipu_ch);
286}
287
288void ipu_plane_disable_deferred(struct drm_plane *plane)
289{
290 struct ipu_plane *ipu_plane = to_ipu_plane(plane);
291
292 if (ipu_plane->disabling) {
293 ipu_plane->disabling = false;
294 ipu_plane_disable(ipu_plane, false);
295 }
296}
297
298static void ipu_plane_state_reset(struct drm_plane *plane)
299{
300 unsigned int zpos = (plane->type == DRM_PLANE_TYPE_PRIMARY) ? 0 : 1;
301 struct ipu_plane_state *ipu_state;
302
303 if (plane->state) {
304 ipu_state = to_ipu_plane_state(plane->state);
305 __drm_atomic_helper_plane_destroy_state(plane->state);
306 kfree(ipu_state);
307 plane->state = NULL;
308 }
309
310 ipu_state = kzalloc(sizeof(*ipu_state), GFP_KERNEL);
311
312 if (ipu_state) {
313 __drm_atomic_helper_plane_reset(plane, &ipu_state->base);
314 ipu_state->base.zpos = zpos;
315 ipu_state->base.normalized_zpos = zpos;
316 ipu_state->base.color_encoding = DRM_COLOR_YCBCR_BT601;
317 ipu_state->base.color_range = DRM_COLOR_YCBCR_LIMITED_RANGE;
318 }
319}
320
321static struct drm_plane_state *
322ipu_plane_duplicate_state(struct drm_plane *plane)
323{
324 struct ipu_plane_state *state;
325
326 if (WARN_ON(!plane->state))
327 return NULL;
328
329 state = kmalloc(sizeof(*state), GFP_KERNEL);
330 if (state)
331 __drm_atomic_helper_plane_duplicate_state(plane, &state->base);
332
333 return &state->base;
334}
335
336static void ipu_plane_destroy_state(struct drm_plane *plane,
337 struct drm_plane_state *state)
338{
339 struct ipu_plane_state *ipu_state = to_ipu_plane_state(state);
340
341 __drm_atomic_helper_plane_destroy_state(state);
342 kfree(ipu_state);
343}
344
345static bool ipu_plane_format_mod_supported(struct drm_plane *plane,
346 uint32_t format, uint64_t modifier)
347{
348 struct ipu_soc *ipu = to_ipu_plane(plane)->ipu;
349
350 /* linear is supported for all planes and formats */
351 if (modifier == DRM_FORMAT_MOD_LINEAR)
352 return true;
353
354 /*
355 * Without a PRG the possible modifiers list only includes the linear
356 * modifier, so we always take the early return from this function and
357 * only end up here if the PRG is present.
358 */
359 return ipu_prg_format_supported(ipu, format, modifier);
360}
361
362static const struct drm_plane_funcs ipu_plane_funcs = {
363 .update_plane = drm_atomic_helper_update_plane,
364 .disable_plane = drm_atomic_helper_disable_plane,
365 .reset = ipu_plane_state_reset,
366 .atomic_duplicate_state = ipu_plane_duplicate_state,
367 .atomic_destroy_state = ipu_plane_destroy_state,
368 .format_mod_supported = ipu_plane_format_mod_supported,
369};
370
371static int ipu_plane_atomic_check(struct drm_plane *plane,
372 struct drm_atomic_state *state)
373{
374 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
375 plane);
376 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
377 plane);
378 struct drm_crtc_state *crtc_state;
379 struct device *dev = plane->dev->dev;
380 struct drm_framebuffer *fb = new_state->fb;
381 struct drm_framebuffer *old_fb = old_state->fb;
382 unsigned long eba, ubo, vbo, old_ubo, old_vbo, alpha_eba;
383 bool can_position = (plane->type == DRM_PLANE_TYPE_OVERLAY);
384 int ret;
385
386 /* Ok to disable */
387 if (!fb)
388 return 0;
389
390 if (WARN_ON(!new_state->crtc))
391 return -EINVAL;
392
393 crtc_state =
394 drm_atomic_get_existing_crtc_state(state,
395 new_state->crtc);
396 if (WARN_ON(!crtc_state))
397 return -EINVAL;
398
399 ret = drm_atomic_helper_check_plane_state(new_state, crtc_state,
400 DRM_PLANE_HELPER_NO_SCALING,
401 DRM_PLANE_HELPER_NO_SCALING,
402 can_position, true);
403 if (ret)
404 return ret;
405
406 /* nothing to check when disabling or disabled */
407 if (!crtc_state->enable)
408 return 0;
409
410 switch (plane->type) {
411 case DRM_PLANE_TYPE_PRIMARY:
412 /* full plane minimum width is 13 pixels */
413 if (drm_rect_width(&new_state->dst) < 13)
414 return -EINVAL;
415 break;
416 case DRM_PLANE_TYPE_OVERLAY:
417 break;
418 default:
419 dev_warn(dev, "Unsupported plane type %d\n", plane->type);
420 return -EINVAL;
421 }
422
423 if (drm_rect_height(&new_state->dst) < 2)
424 return -EINVAL;
425
426 /*
427 * We support resizing active plane or changing its format by
428 * forcing CRTC mode change in plane's ->atomic_check callback
429 * and disabling all affected active planes in CRTC's ->atomic_disable
430 * callback. The planes will be reenabled in plane's ->atomic_update
431 * callback.
432 */
433 if (old_fb &&
434 (drm_rect_width(&new_state->dst) != drm_rect_width(&old_state->dst) ||
435 drm_rect_height(&new_state->dst) != drm_rect_height(&old_state->dst) ||
436 fb->format != old_fb->format))
437 crtc_state->mode_changed = true;
438
439 eba = drm_plane_state_to_eba(new_state, 0);
440
441 if (eba & 0x7)
442 return -EINVAL;
443
444 if (fb->pitches[0] < 1 || fb->pitches[0] > 16384)
445 return -EINVAL;
446
447 if (old_fb && fb->pitches[0] != old_fb->pitches[0])
448 crtc_state->mode_changed = true;
449
450 if (ALIGN(fb->width, 8) * fb->format->cpp[0] >
451 fb->pitches[0] + fb->offsets[0]) {
452 dev_warn(dev, "pitch is not big enough for 8 pixels alignment");
453 return -EINVAL;
454 }
455
456 switch (fb->format->format) {
457 case DRM_FORMAT_YUV420:
458 case DRM_FORMAT_YVU420:
459 case DRM_FORMAT_YUV422:
460 case DRM_FORMAT_YVU422:
461 case DRM_FORMAT_YUV444:
462 case DRM_FORMAT_YVU444:
463 /*
464 * Multiplanar formats have to meet the following restrictions:
465 * - The (up to) three plane addresses are EBA, EBA+UBO, EBA+VBO
466 * - EBA, UBO and VBO are a multiple of 8
467 * - UBO and VBO are unsigned and not larger than 0xfffff8
468 * - Only EBA may be changed while scanout is active
469 * - The strides of U and V planes must be identical.
470 */
471 vbo = drm_plane_state_to_vbo(new_state);
472
473 if (vbo & 0x7 || vbo > 0xfffff8)
474 return -EINVAL;
475
476 if (old_fb && (fb->format == old_fb->format)) {
477 old_vbo = drm_plane_state_to_vbo(old_state);
478 if (vbo != old_vbo)
479 crtc_state->mode_changed = true;
480 }
481
482 if (fb->pitches[1] != fb->pitches[2])
483 return -EINVAL;
484
485 fallthrough;
486 case DRM_FORMAT_NV12:
487 case DRM_FORMAT_NV16:
488 ubo = drm_plane_state_to_ubo(new_state);
489
490 if (ubo & 0x7 || ubo > 0xfffff8)
491 return -EINVAL;
492
493 if (old_fb && (fb->format == old_fb->format)) {
494 old_ubo = drm_plane_state_to_ubo(old_state);
495 if (ubo != old_ubo)
496 crtc_state->mode_changed = true;
497 }
498
499 if (fb->pitches[1] < 1 || fb->pitches[1] > 16384)
500 return -EINVAL;
501
502 if (old_fb && old_fb->pitches[1] != fb->pitches[1])
503 crtc_state->mode_changed = true;
504
505 /*
506 * The x/y offsets must be even in case of horizontal/vertical
507 * chroma subsampling.
508 */
509 if (((new_state->src.x1 >> 16) & (fb->format->hsub - 1)) ||
510 ((new_state->src.y1 >> 16) & (fb->format->vsub - 1)))
511 return -EINVAL;
512 break;
513 case DRM_FORMAT_RGB565_A8:
514 case DRM_FORMAT_BGR565_A8:
515 case DRM_FORMAT_RGB888_A8:
516 case DRM_FORMAT_BGR888_A8:
517 case DRM_FORMAT_RGBX8888_A8:
518 case DRM_FORMAT_BGRX8888_A8:
519 alpha_eba = drm_plane_state_to_eba(new_state, 1);
520 if (alpha_eba & 0x7)
521 return -EINVAL;
522
523 if (fb->pitches[1] < 1 || fb->pitches[1] > 16384)
524 return -EINVAL;
525
526 if (old_fb && old_fb->pitches[1] != fb->pitches[1])
527 crtc_state->mode_changed = true;
528 break;
529 }
530
531 return 0;
532}
533
534static void ipu_plane_atomic_disable(struct drm_plane *plane,
535 struct drm_atomic_state *state)
536{
537 struct ipu_plane *ipu_plane = to_ipu_plane(plane);
538
539 if (ipu_plane->dp)
540 ipu_dp_disable_channel(ipu_plane->dp, true);
541 ipu_plane->disabling = true;
542}
543
544static int ipu_chan_assign_axi_id(int ipu_chan)
545{
546 switch (ipu_chan) {
547 case IPUV3_CHANNEL_MEM_BG_SYNC:
548 return 1;
549 case IPUV3_CHANNEL_MEM_FG_SYNC:
550 return 2;
551 case IPUV3_CHANNEL_MEM_DC_SYNC:
552 return 3;
553 default:
554 return 0;
555 }
556}
557
558static void ipu_calculate_bursts(u32 width, u32 cpp, u32 stride,
559 u8 *burstsize, u8 *num_bursts)
560{
561 const unsigned int width_bytes = width * cpp;
562 unsigned int npb, bursts;
563
564 /* Maximum number of pixels per burst without overshooting stride */
565 for (npb = 64 / cpp; npb > 0; --npb) {
566 if (round_up(width_bytes, npb * cpp) <= stride)
567 break;
568 }
569 *burstsize = npb;
570
571 /* Maximum number of consecutive bursts without overshooting stride */
572 for (bursts = 8; bursts > 1; bursts /= 2) {
573 if (round_up(width_bytes, npb * cpp * bursts) <= stride)
574 break;
575 }
576 *num_bursts = bursts;
577}
578
579static void ipu_plane_atomic_update(struct drm_plane *plane,
580 struct drm_atomic_state *state)
581{
582 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
583 plane);
584 struct ipu_plane *ipu_plane = to_ipu_plane(plane);
585 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
586 plane);
587 struct ipu_plane_state *ipu_state = to_ipu_plane_state(new_state);
588 struct drm_crtc_state *crtc_state = new_state->crtc->state;
589 struct drm_framebuffer *fb = new_state->fb;
590 struct drm_rect *dst = &new_state->dst;
591 unsigned long eba, ubo, vbo;
592 unsigned long alpha_eba = 0;
593 enum ipu_color_space ics;
594 unsigned int axi_id = 0;
595 const struct drm_format_info *info;
596 u8 burstsize, num_bursts;
597 u32 width, height;
598 int active;
599
600 if (ipu_plane->dp_flow == IPU_DP_FLOW_SYNC_FG)
601 ipu_dp_set_window_pos(ipu_plane->dp, dst->x1, dst->y1);
602
603 switch (ipu_plane->dp_flow) {
604 case IPU_DP_FLOW_SYNC_BG:
605 if (new_state->normalized_zpos == 1) {
606 ipu_dp_set_global_alpha(ipu_plane->dp,
607 !fb->format->has_alpha, 0xff,
608 true);
609 } else {
610 ipu_dp_set_global_alpha(ipu_plane->dp, true, 0, true);
611 }
612 break;
613 case IPU_DP_FLOW_SYNC_FG:
614 if (new_state->normalized_zpos == 1) {
615 ipu_dp_set_global_alpha(ipu_plane->dp,
616 !fb->format->has_alpha, 0xff,
617 false);
618 }
619 break;
620 }
621
622 eba = drm_plane_state_to_eba(new_state, 0);
623
624 /*
625 * Configure PRG channel and attached PRE, this changes the EBA to an
626 * internal SRAM location.
627 */
628 if (ipu_state->use_pre) {
629 axi_id = ipu_chan_assign_axi_id(ipu_plane->dma);
630 ipu_prg_channel_configure(ipu_plane->ipu_ch, axi_id,
631 ipu_src_rect_width(new_state),
632 drm_rect_height(&new_state->src) >> 16,
633 fb->pitches[0], fb->format->format,
634 fb->modifier, &eba);
635 }
636
637 if (!old_state->fb ||
638 old_state->fb->format->format != fb->format->format ||
639 old_state->color_encoding != new_state->color_encoding ||
640 old_state->color_range != new_state->color_range) {
641 ics = ipu_drm_fourcc_to_colorspace(fb->format->format);
642 switch (ipu_plane->dp_flow) {
643 case IPU_DP_FLOW_SYNC_BG:
644 ipu_dp_setup_channel(ipu_plane->dp, new_state->color_encoding,
645 new_state->color_range, ics,
646 IPUV3_COLORSPACE_RGB);
647 break;
648 case IPU_DP_FLOW_SYNC_FG:
649 ipu_dp_setup_channel(ipu_plane->dp, new_state->color_encoding,
650 new_state->color_range, ics,
651 IPUV3_COLORSPACE_UNKNOWN);
652 break;
653 }
654 }
655
656 if (old_state->fb && !drm_atomic_crtc_needs_modeset(crtc_state)) {
657 /* nothing to do if PRE is used */
658 if (ipu_state->use_pre)
659 return;
660 active = ipu_idmac_get_current_buffer(ipu_plane->ipu_ch);
661 ipu_cpmem_set_buffer(ipu_plane->ipu_ch, !active, eba);
662 ipu_idmac_select_buffer(ipu_plane->ipu_ch, !active);
663 if (ipu_plane_separate_alpha(ipu_plane)) {
664 active = ipu_idmac_get_current_buffer(ipu_plane->alpha_ch);
665 ipu_cpmem_set_buffer(ipu_plane->alpha_ch, !active,
666 alpha_eba);
667 ipu_idmac_select_buffer(ipu_plane->alpha_ch, !active);
668 }
669 return;
670 }
671
672 ics = ipu_drm_fourcc_to_colorspace(fb->format->format);
673 switch (ipu_plane->dp_flow) {
674 case IPU_DP_FLOW_SYNC_BG:
675 ipu_dp_setup_channel(ipu_plane->dp, DRM_COLOR_YCBCR_BT601,
676 DRM_COLOR_YCBCR_LIMITED_RANGE, ics,
677 IPUV3_COLORSPACE_RGB);
678 break;
679 case IPU_DP_FLOW_SYNC_FG:
680 ipu_dp_setup_channel(ipu_plane->dp, DRM_COLOR_YCBCR_BT601,
681 DRM_COLOR_YCBCR_LIMITED_RANGE, ics,
682 IPUV3_COLORSPACE_UNKNOWN);
683 break;
684 }
685
686 ipu_dmfc_config_wait4eot(ipu_plane->dmfc, ALIGN(drm_rect_width(dst), 8));
687
688 width = ipu_src_rect_width(new_state);
689 height = drm_rect_height(&new_state->src) >> 16;
690 info = drm_format_info(fb->format->format);
691 ipu_calculate_bursts(width, info->cpp[0], fb->pitches[0],
692 &burstsize, &num_bursts);
693
694 ipu_cpmem_zero(ipu_plane->ipu_ch);
695 ipu_cpmem_set_resolution(ipu_plane->ipu_ch, width, height);
696 ipu_cpmem_set_fmt(ipu_plane->ipu_ch, fb->format->format);
697 ipu_cpmem_set_burstsize(ipu_plane->ipu_ch, burstsize);
698 ipu_cpmem_set_high_priority(ipu_plane->ipu_ch);
699 ipu_idmac_enable_watermark(ipu_plane->ipu_ch, true);
700 ipu_idmac_set_double_buffer(ipu_plane->ipu_ch, 1);
701 ipu_cpmem_set_stride(ipu_plane->ipu_ch, fb->pitches[0]);
702 ipu_cpmem_set_axi_id(ipu_plane->ipu_ch, axi_id);
703
704 switch (fb->format->format) {
705 case DRM_FORMAT_YUV420:
706 case DRM_FORMAT_YVU420:
707 case DRM_FORMAT_YUV422:
708 case DRM_FORMAT_YVU422:
709 case DRM_FORMAT_YUV444:
710 case DRM_FORMAT_YVU444:
711 ubo = drm_plane_state_to_ubo(new_state);
712 vbo = drm_plane_state_to_vbo(new_state);
713 if (fb->format->format == DRM_FORMAT_YVU420 ||
714 fb->format->format == DRM_FORMAT_YVU422 ||
715 fb->format->format == DRM_FORMAT_YVU444)
716 swap(ubo, vbo);
717
718 ipu_cpmem_set_yuv_planar_full(ipu_plane->ipu_ch,
719 fb->pitches[1], ubo, vbo);
720
721 dev_dbg(ipu_plane->base.dev->dev,
722 "phy = %lu %lu %lu, x = %d, y = %d", eba, ubo, vbo,
723 new_state->src.x1 >> 16, new_state->src.y1 >> 16);
724 break;
725 case DRM_FORMAT_NV12:
726 case DRM_FORMAT_NV16:
727 ubo = drm_plane_state_to_ubo(new_state);
728
729 ipu_cpmem_set_yuv_planar_full(ipu_plane->ipu_ch,
730 fb->pitches[1], ubo, ubo);
731
732 dev_dbg(ipu_plane->base.dev->dev,
733 "phy = %lu %lu, x = %d, y = %d", eba, ubo,
734 new_state->src.x1 >> 16, new_state->src.y1 >> 16);
735 break;
736 case DRM_FORMAT_RGB565_A8:
737 case DRM_FORMAT_BGR565_A8:
738 case DRM_FORMAT_RGB888_A8:
739 case DRM_FORMAT_BGR888_A8:
740 case DRM_FORMAT_RGBX8888_A8:
741 case DRM_FORMAT_BGRX8888_A8:
742 alpha_eba = drm_plane_state_to_eba(new_state, 1);
743 num_bursts = 0;
744
745 dev_dbg(ipu_plane->base.dev->dev, "phys = %lu %lu, x = %d, y = %d",
746 eba, alpha_eba, new_state->src.x1 >> 16,
747 new_state->src.y1 >> 16);
748
749 ipu_cpmem_set_burstsize(ipu_plane->ipu_ch, 16);
750
751 ipu_cpmem_zero(ipu_plane->alpha_ch);
752 ipu_cpmem_set_resolution(ipu_plane->alpha_ch,
753 ipu_src_rect_width(new_state),
754 drm_rect_height(&new_state->src) >> 16);
755 ipu_cpmem_set_format_passthrough(ipu_plane->alpha_ch, 8);
756 ipu_cpmem_set_high_priority(ipu_plane->alpha_ch);
757 ipu_idmac_set_double_buffer(ipu_plane->alpha_ch, 1);
758 ipu_cpmem_set_stride(ipu_plane->alpha_ch, fb->pitches[1]);
759 ipu_cpmem_set_burstsize(ipu_plane->alpha_ch, 16);
760 ipu_cpmem_set_buffer(ipu_plane->alpha_ch, 0, alpha_eba);
761 ipu_cpmem_set_buffer(ipu_plane->alpha_ch, 1, alpha_eba);
762 break;
763 default:
764 dev_dbg(ipu_plane->base.dev->dev, "phys = %lu, x = %d, y = %d",
765 eba, new_state->src.x1 >> 16, new_state->src.y1 >> 16);
766 break;
767 }
768 ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 0, eba);
769 ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 1, eba);
770 ipu_idmac_lock_enable(ipu_plane->ipu_ch, num_bursts);
771 ipu_plane_enable(ipu_plane);
772}
773
774static const struct drm_plane_helper_funcs ipu_plane_helper_funcs = {
775 .prepare_fb = drm_gem_plane_helper_prepare_fb,
776 .atomic_check = ipu_plane_atomic_check,
777 .atomic_disable = ipu_plane_atomic_disable,
778 .atomic_update = ipu_plane_atomic_update,
779};
780
781bool ipu_plane_atomic_update_pending(struct drm_plane *plane)
782{
783 struct ipu_plane *ipu_plane = to_ipu_plane(plane);
784 struct drm_plane_state *state = plane->state;
785 struct ipu_plane_state *ipu_state = to_ipu_plane_state(state);
786
787 /* disabled crtcs must not block the update */
788 if (!state->crtc)
789 return false;
790
791 if (ipu_state->use_pre)
792 return ipu_prg_channel_configure_pending(ipu_plane->ipu_ch);
793
794 /*
795 * Pretend no update is pending in the non-PRE/PRG case. For this to
796 * happen, an atomic update would have to be deferred until after the
797 * start of the next frame and simultaneously interrupt latency would
798 * have to be high enough to let the atomic update finish and issue an
799 * event before the previous end of frame interrupt handler can be
800 * executed.
801 */
802 return false;
803}
804int ipu_planes_assign_pre(struct drm_device *dev,
805 struct drm_atomic_state *state)
806{
807 struct drm_crtc_state *old_crtc_state, *crtc_state;
808 struct drm_plane_state *plane_state;
809 struct ipu_plane_state *ipu_state;
810 struct ipu_plane *ipu_plane;
811 struct drm_plane *plane;
812 struct drm_crtc *crtc;
813 int available_pres = ipu_prg_max_active_channels();
814 int ret, i;
815
816 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) {
817 ret = drm_atomic_add_affected_planes(state, crtc);
818 if (ret)
819 return ret;
820 }
821
822 /*
823 * We are going over the planes in 2 passes: first we assign PREs to
824 * planes with a tiling modifier, which need the PREs to resolve into
825 * linear. Any failure to assign a PRE there is fatal. In the second
826 * pass we try to assign PREs to linear FBs, to improve memory access
827 * patterns for them. Failure at this point is non-fatal, as we can
828 * scan out linear FBs without a PRE.
829 */
830 for_each_new_plane_in_state(state, plane, plane_state, i) {
831 ipu_state = to_ipu_plane_state(plane_state);
832 ipu_plane = to_ipu_plane(plane);
833
834 if (!plane_state->fb) {
835 ipu_state->use_pre = false;
836 continue;
837 }
838
839 if (!(plane_state->fb->flags & DRM_MODE_FB_MODIFIERS) ||
840 plane_state->fb->modifier == DRM_FORMAT_MOD_LINEAR)
841 continue;
842
843 if (!ipu_prg_present(ipu_plane->ipu) || !available_pres)
844 return -EINVAL;
845
846 if (!ipu_prg_format_supported(ipu_plane->ipu,
847 plane_state->fb->format->format,
848 plane_state->fb->modifier))
849 return -EINVAL;
850
851 ipu_state->use_pre = true;
852 available_pres--;
853 }
854
855 for_each_new_plane_in_state(state, plane, plane_state, i) {
856 ipu_state = to_ipu_plane_state(plane_state);
857 ipu_plane = to_ipu_plane(plane);
858
859 if (!plane_state->fb) {
860 ipu_state->use_pre = false;
861 continue;
862 }
863
864 if ((plane_state->fb->flags & DRM_MODE_FB_MODIFIERS) &&
865 plane_state->fb->modifier != DRM_FORMAT_MOD_LINEAR)
866 continue;
867
868 /* make sure that modifier is initialized */
869 plane_state->fb->modifier = DRM_FORMAT_MOD_LINEAR;
870
871 if (ipu_prg_present(ipu_plane->ipu) && available_pres &&
872 ipu_prg_format_supported(ipu_plane->ipu,
873 plane_state->fb->format->format,
874 plane_state->fb->modifier)) {
875 ipu_state->use_pre = true;
876 available_pres--;
877 } else {
878 ipu_state->use_pre = false;
879 }
880 }
881
882 return 0;
883}
884
885struct ipu_plane *ipu_plane_init(struct drm_device *dev, struct ipu_soc *ipu,
886 int dma, int dp, unsigned int possible_crtcs,
887 enum drm_plane_type type)
888{
889 struct ipu_plane *ipu_plane;
890 const uint64_t *modifiers = ipu_format_modifiers;
891 unsigned int zpos = (type == DRM_PLANE_TYPE_PRIMARY) ? 0 : 1;
892 unsigned int format_count;
893 const uint32_t *formats;
894 int ret;
895
896 DRM_DEBUG_KMS("channel %d, dp flow %d, possible_crtcs=0x%x\n",
897 dma, dp, possible_crtcs);
898
899 if (dp == IPU_DP_FLOW_SYNC_BG || dp == IPU_DP_FLOW_SYNC_FG) {
900 formats = ipu_plane_all_formats;
901 format_count = ARRAY_SIZE(ipu_plane_all_formats);
902 } else {
903 formats = ipu_plane_rgb_formats;
904 format_count = ARRAY_SIZE(ipu_plane_rgb_formats);
905 }
906
907 if (ipu_prg_present(ipu))
908 modifiers = pre_format_modifiers;
909
910 ipu_plane = drmm_universal_plane_alloc(dev, struct ipu_plane, base,
911 possible_crtcs, &ipu_plane_funcs,
912 formats, format_count, modifiers,
913 type, NULL);
914 if (IS_ERR(ipu_plane)) {
915 DRM_ERROR("failed to allocate and initialize %s plane\n",
916 zpos ? "overlay" : "primary");
917 return ipu_plane;
918 }
919
920 ipu_plane->ipu = ipu;
921 ipu_plane->dma = dma;
922 ipu_plane->dp_flow = dp;
923
924 drm_plane_helper_add(&ipu_plane->base, &ipu_plane_helper_funcs);
925
926 if (dp == IPU_DP_FLOW_SYNC_BG || dp == IPU_DP_FLOW_SYNC_FG)
927 ret = drm_plane_create_zpos_property(&ipu_plane->base, zpos, 0,
928 1);
929 else
930 ret = drm_plane_create_zpos_immutable_property(&ipu_plane->base,
931 0);
932 if (ret)
933 return ERR_PTR(ret);
934
935 ret = drm_plane_create_color_properties(&ipu_plane->base,
936 BIT(DRM_COLOR_YCBCR_BT601) |
937 BIT(DRM_COLOR_YCBCR_BT709),
938 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE),
939 DRM_COLOR_YCBCR_BT601,
940 DRM_COLOR_YCBCR_LIMITED_RANGE);
941 if (ret)
942 return ERR_PTR(ret);
943
944 ret = ipu_plane_get_resources(dev, ipu_plane);
945 if (ret) {
946 DRM_ERROR("failed to get %s plane resources: %pe\n",
947 zpos ? "overlay" : "primary", &ret);
948 return ERR_PTR(ret);
949 }
950
951 return ipu_plane;
952}