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1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2016 Intel Corporation
4 */
5
6#include <drm/drm_print.h>
7
8#include "gem/i915_gem_context.h"
9
10#include "i915_drv.h"
11
12#include "intel_breadcrumbs.h"
13#include "intel_context.h"
14#include "intel_engine.h"
15#include "intel_engine_pm.h"
16#include "intel_engine_user.h"
17#include "intel_execlists_submission.h"
18#include "intel_gt.h"
19#include "intel_gt_requests.h"
20#include "intel_gt_pm.h"
21#include "intel_lrc_reg.h"
22#include "intel_reset.h"
23#include "intel_ring.h"
24#include "uc/intel_guc_submission.h"
25
26/* Haswell does have the CXT_SIZE register however it does not appear to be
27 * valid. Now, docs explain in dwords what is in the context object. The full
28 * size is 70720 bytes, however, the power context and execlist context will
29 * never be saved (power context is stored elsewhere, and execlists don't work
30 * on HSW) - so the final size, including the extra state required for the
31 * Resource Streamer, is 66944 bytes, which rounds to 17 pages.
32 */
33#define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE)
34
35#define DEFAULT_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
36#define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
37#define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
38#define GEN10_LR_CONTEXT_RENDER_SIZE (18 * PAGE_SIZE)
39#define GEN11_LR_CONTEXT_RENDER_SIZE (14 * PAGE_SIZE)
40
41#define GEN8_LR_CONTEXT_OTHER_SIZE ( 2 * PAGE_SIZE)
42
43#define MAX_MMIO_BASES 3
44struct engine_info {
45 unsigned int hw_id;
46 u8 class;
47 u8 instance;
48 /* mmio bases table *must* be sorted in reverse graphics_ver order */
49 struct engine_mmio_base {
50 u32 graphics_ver : 8;
51 u32 base : 24;
52 } mmio_bases[MAX_MMIO_BASES];
53};
54
55static const struct engine_info intel_engines[] = {
56 [RCS0] = {
57 .hw_id = RCS0_HW,
58 .class = RENDER_CLASS,
59 .instance = 0,
60 .mmio_bases = {
61 { .graphics_ver = 1, .base = RENDER_RING_BASE }
62 },
63 },
64 [BCS0] = {
65 .hw_id = BCS0_HW,
66 .class = COPY_ENGINE_CLASS,
67 .instance = 0,
68 .mmio_bases = {
69 { .graphics_ver = 6, .base = BLT_RING_BASE }
70 },
71 },
72 [VCS0] = {
73 .hw_id = VCS0_HW,
74 .class = VIDEO_DECODE_CLASS,
75 .instance = 0,
76 .mmio_bases = {
77 { .graphics_ver = 11, .base = GEN11_BSD_RING_BASE },
78 { .graphics_ver = 6, .base = GEN6_BSD_RING_BASE },
79 { .graphics_ver = 4, .base = BSD_RING_BASE }
80 },
81 },
82 [VCS1] = {
83 .hw_id = VCS1_HW,
84 .class = VIDEO_DECODE_CLASS,
85 .instance = 1,
86 .mmio_bases = {
87 { .graphics_ver = 11, .base = GEN11_BSD2_RING_BASE },
88 { .graphics_ver = 8, .base = GEN8_BSD2_RING_BASE }
89 },
90 },
91 [VCS2] = {
92 .hw_id = VCS2_HW,
93 .class = VIDEO_DECODE_CLASS,
94 .instance = 2,
95 .mmio_bases = {
96 { .graphics_ver = 11, .base = GEN11_BSD3_RING_BASE }
97 },
98 },
99 [VCS3] = {
100 .hw_id = VCS3_HW,
101 .class = VIDEO_DECODE_CLASS,
102 .instance = 3,
103 .mmio_bases = {
104 { .graphics_ver = 11, .base = GEN11_BSD4_RING_BASE }
105 },
106 },
107 [VECS0] = {
108 .hw_id = VECS0_HW,
109 .class = VIDEO_ENHANCEMENT_CLASS,
110 .instance = 0,
111 .mmio_bases = {
112 { .graphics_ver = 11, .base = GEN11_VEBOX_RING_BASE },
113 { .graphics_ver = 7, .base = VEBOX_RING_BASE }
114 },
115 },
116 [VECS1] = {
117 .hw_id = VECS1_HW,
118 .class = VIDEO_ENHANCEMENT_CLASS,
119 .instance = 1,
120 .mmio_bases = {
121 { .graphics_ver = 11, .base = GEN11_VEBOX2_RING_BASE }
122 },
123 },
124};
125
126/**
127 * intel_engine_context_size() - return the size of the context for an engine
128 * @gt: the gt
129 * @class: engine class
130 *
131 * Each engine class may require a different amount of space for a context
132 * image.
133 *
134 * Return: size (in bytes) of an engine class specific context image
135 *
136 * Note: this size includes the HWSP, which is part of the context image
137 * in LRC mode, but does not include the "shared data page" used with
138 * GuC submission. The caller should account for this if using the GuC.
139 */
140u32 intel_engine_context_size(struct intel_gt *gt, u8 class)
141{
142 struct intel_uncore *uncore = gt->uncore;
143 u32 cxt_size;
144
145 BUILD_BUG_ON(I915_GTT_PAGE_SIZE != PAGE_SIZE);
146
147 switch (class) {
148 case RENDER_CLASS:
149 switch (GRAPHICS_VER(gt->i915)) {
150 default:
151 MISSING_CASE(GRAPHICS_VER(gt->i915));
152 return DEFAULT_LR_CONTEXT_RENDER_SIZE;
153 case 12:
154 case 11:
155 return GEN11_LR_CONTEXT_RENDER_SIZE;
156 case 10:
157 return GEN10_LR_CONTEXT_RENDER_SIZE;
158 case 9:
159 return GEN9_LR_CONTEXT_RENDER_SIZE;
160 case 8:
161 return GEN8_LR_CONTEXT_RENDER_SIZE;
162 case 7:
163 if (IS_HASWELL(gt->i915))
164 return HSW_CXT_TOTAL_SIZE;
165
166 cxt_size = intel_uncore_read(uncore, GEN7_CXT_SIZE);
167 return round_up(GEN7_CXT_TOTAL_SIZE(cxt_size) * 64,
168 PAGE_SIZE);
169 case 6:
170 cxt_size = intel_uncore_read(uncore, CXT_SIZE);
171 return round_up(GEN6_CXT_TOTAL_SIZE(cxt_size) * 64,
172 PAGE_SIZE);
173 case 5:
174 case 4:
175 /*
176 * There is a discrepancy here between the size reported
177 * by the register and the size of the context layout
178 * in the docs. Both are described as authorative!
179 *
180 * The discrepancy is on the order of a few cachelines,
181 * but the total is under one page (4k), which is our
182 * minimum allocation anyway so it should all come
183 * out in the wash.
184 */
185 cxt_size = intel_uncore_read(uncore, CXT_SIZE) + 1;
186 drm_dbg(>->i915->drm,
187 "graphics_ver = %d CXT_SIZE = %d bytes [0x%08x]\n",
188 GRAPHICS_VER(gt->i915), cxt_size * 64,
189 cxt_size - 1);
190 return round_up(cxt_size * 64, PAGE_SIZE);
191 case 3:
192 case 2:
193 /* For the special day when i810 gets merged. */
194 case 1:
195 return 0;
196 }
197 break;
198 default:
199 MISSING_CASE(class);
200 fallthrough;
201 case VIDEO_DECODE_CLASS:
202 case VIDEO_ENHANCEMENT_CLASS:
203 case COPY_ENGINE_CLASS:
204 if (GRAPHICS_VER(gt->i915) < 8)
205 return 0;
206 return GEN8_LR_CONTEXT_OTHER_SIZE;
207 }
208}
209
210static u32 __engine_mmio_base(struct drm_i915_private *i915,
211 const struct engine_mmio_base *bases)
212{
213 int i;
214
215 for (i = 0; i < MAX_MMIO_BASES; i++)
216 if (GRAPHICS_VER(i915) >= bases[i].graphics_ver)
217 break;
218
219 GEM_BUG_ON(i == MAX_MMIO_BASES);
220 GEM_BUG_ON(!bases[i].base);
221
222 return bases[i].base;
223}
224
225static void __sprint_engine_name(struct intel_engine_cs *engine)
226{
227 /*
228 * Before we know what the uABI name for this engine will be,
229 * we still would like to keep track of this engine in the debug logs.
230 * We throw in a ' here as a reminder that this isn't its final name.
231 */
232 GEM_WARN_ON(snprintf(engine->name, sizeof(engine->name), "%s'%u",
233 intel_engine_class_repr(engine->class),
234 engine->instance) >= sizeof(engine->name));
235}
236
237void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask)
238{
239 /*
240 * Though they added more rings on g4x/ilk, they did not add
241 * per-engine HWSTAM until gen6.
242 */
243 if (GRAPHICS_VER(engine->i915) < 6 && engine->class != RENDER_CLASS)
244 return;
245
246 if (GRAPHICS_VER(engine->i915) >= 3)
247 ENGINE_WRITE(engine, RING_HWSTAM, mask);
248 else
249 ENGINE_WRITE16(engine, RING_HWSTAM, mask);
250}
251
252static void intel_engine_sanitize_mmio(struct intel_engine_cs *engine)
253{
254 /* Mask off all writes into the unknown HWSP */
255 intel_engine_set_hwsp_writemask(engine, ~0u);
256}
257
258static void nop_irq_handler(struct intel_engine_cs *engine, u16 iir)
259{
260 GEM_DEBUG_WARN_ON(iir);
261}
262
263static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
264{
265 const struct engine_info *info = &intel_engines[id];
266 struct drm_i915_private *i915 = gt->i915;
267 struct intel_engine_cs *engine;
268 u8 guc_class;
269
270 BUILD_BUG_ON(MAX_ENGINE_CLASS >= BIT(GEN11_ENGINE_CLASS_WIDTH));
271 BUILD_BUG_ON(MAX_ENGINE_INSTANCE >= BIT(GEN11_ENGINE_INSTANCE_WIDTH));
272
273 if (GEM_DEBUG_WARN_ON(id >= ARRAY_SIZE(gt->engine)))
274 return -EINVAL;
275
276 if (GEM_DEBUG_WARN_ON(info->class > MAX_ENGINE_CLASS))
277 return -EINVAL;
278
279 if (GEM_DEBUG_WARN_ON(info->instance > MAX_ENGINE_INSTANCE))
280 return -EINVAL;
281
282 if (GEM_DEBUG_WARN_ON(gt->engine_class[info->class][info->instance]))
283 return -EINVAL;
284
285 engine = kzalloc(sizeof(*engine), GFP_KERNEL);
286 if (!engine)
287 return -ENOMEM;
288
289 BUILD_BUG_ON(BITS_PER_TYPE(engine->mask) < I915_NUM_ENGINES);
290
291 engine->id = id;
292 engine->legacy_idx = INVALID_ENGINE;
293 engine->mask = BIT(id);
294 engine->i915 = i915;
295 engine->gt = gt;
296 engine->uncore = gt->uncore;
297 engine->hw_id = info->hw_id;
298 guc_class = engine_class_to_guc_class(info->class);
299 engine->guc_id = MAKE_GUC_ID(guc_class, info->instance);
300 engine->mmio_base = __engine_mmio_base(i915, info->mmio_bases);
301
302 engine->irq_handler = nop_irq_handler;
303
304 engine->class = info->class;
305 engine->instance = info->instance;
306 __sprint_engine_name(engine);
307
308 engine->props.heartbeat_interval_ms =
309 CONFIG_DRM_I915_HEARTBEAT_INTERVAL;
310 engine->props.max_busywait_duration_ns =
311 CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT;
312 engine->props.preempt_timeout_ms =
313 CONFIG_DRM_I915_PREEMPT_TIMEOUT;
314 engine->props.stop_timeout_ms =
315 CONFIG_DRM_I915_STOP_TIMEOUT;
316 engine->props.timeslice_duration_ms =
317 CONFIG_DRM_I915_TIMESLICE_DURATION;
318
319 /* Override to uninterruptible for OpenCL workloads. */
320 if (GRAPHICS_VER(i915) == 12 && engine->class == RENDER_CLASS)
321 engine->props.preempt_timeout_ms = 0;
322
323 engine->defaults = engine->props; /* never to change again */
324
325 engine->context_size = intel_engine_context_size(gt, engine->class);
326 if (WARN_ON(engine->context_size > BIT(20)))
327 engine->context_size = 0;
328 if (engine->context_size)
329 DRIVER_CAPS(i915)->has_logical_contexts = true;
330
331 /* Nothing to do here, execute in order of dependencies */
332 engine->schedule = NULL;
333
334 ewma__engine_latency_init(&engine->latency);
335 seqcount_init(&engine->stats.lock);
336
337 ATOMIC_INIT_NOTIFIER_HEAD(&engine->context_status_notifier);
338
339 /* Scrub mmio state on takeover */
340 intel_engine_sanitize_mmio(engine);
341
342 gt->engine_class[info->class][info->instance] = engine;
343 gt->engine[id] = engine;
344
345 return 0;
346}
347
348static void __setup_engine_capabilities(struct intel_engine_cs *engine)
349{
350 struct drm_i915_private *i915 = engine->i915;
351
352 if (engine->class == VIDEO_DECODE_CLASS) {
353 /*
354 * HEVC support is present on first engine instance
355 * before Gen11 and on all instances afterwards.
356 */
357 if (GRAPHICS_VER(i915) >= 11 ||
358 (GRAPHICS_VER(i915) >= 9 && engine->instance == 0))
359 engine->uabi_capabilities |=
360 I915_VIDEO_CLASS_CAPABILITY_HEVC;
361
362 /*
363 * SFC block is present only on even logical engine
364 * instances.
365 */
366 if ((GRAPHICS_VER(i915) >= 11 &&
367 (engine->gt->info.vdbox_sfc_access &
368 BIT(engine->instance))) ||
369 (GRAPHICS_VER(i915) >= 9 && engine->instance == 0))
370 engine->uabi_capabilities |=
371 I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
372 } else if (engine->class == VIDEO_ENHANCEMENT_CLASS) {
373 if (GRAPHICS_VER(i915) >= 9)
374 engine->uabi_capabilities |=
375 I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
376 }
377}
378
379static void intel_setup_engine_capabilities(struct intel_gt *gt)
380{
381 struct intel_engine_cs *engine;
382 enum intel_engine_id id;
383
384 for_each_engine(engine, gt, id)
385 __setup_engine_capabilities(engine);
386}
387
388/**
389 * intel_engines_release() - free the resources allocated for Command Streamers
390 * @gt: pointer to struct intel_gt
391 */
392void intel_engines_release(struct intel_gt *gt)
393{
394 struct intel_engine_cs *engine;
395 enum intel_engine_id id;
396
397 /*
398 * Before we release the resources held by engine, we must be certain
399 * that the HW is no longer accessing them -- having the GPU scribble
400 * to or read from a page being used for something else causes no end
401 * of fun.
402 *
403 * The GPU should be reset by this point, but assume the worst just
404 * in case we aborted before completely initialising the engines.
405 */
406 GEM_BUG_ON(intel_gt_pm_is_awake(gt));
407 if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
408 __intel_gt_reset(gt, ALL_ENGINES);
409
410 /* Decouple the backend; but keep the layout for late GPU resets */
411 for_each_engine(engine, gt, id) {
412 if (!engine->release)
413 continue;
414
415 intel_wakeref_wait_for_idle(&engine->wakeref);
416 GEM_BUG_ON(intel_engine_pm_is_awake(engine));
417
418 engine->release(engine);
419 engine->release = NULL;
420
421 memset(&engine->reset, 0, sizeof(engine->reset));
422 }
423}
424
425void intel_engine_free_request_pool(struct intel_engine_cs *engine)
426{
427 if (!engine->request_pool)
428 return;
429
430 kmem_cache_free(i915_request_slab_cache(), engine->request_pool);
431}
432
433void intel_engines_free(struct intel_gt *gt)
434{
435 struct intel_engine_cs *engine;
436 enum intel_engine_id id;
437
438 /* Free the requests! dma-resv keeps fences around for an eternity */
439 rcu_barrier();
440
441 for_each_engine(engine, gt, id) {
442 intel_engine_free_request_pool(engine);
443 kfree(engine);
444 gt->engine[id] = NULL;
445 }
446}
447
448/*
449 * Determine which engines are fused off in our particular hardware.
450 * Note that we have a catch-22 situation where we need to be able to access
451 * the blitter forcewake domain to read the engine fuses, but at the same time
452 * we need to know which engines are available on the system to know which
453 * forcewake domains are present. We solve this by intializing the forcewake
454 * domains based on the full engine mask in the platform capabilities before
455 * calling this function and pruning the domains for fused-off engines
456 * afterwards.
457 */
458static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
459{
460 struct drm_i915_private *i915 = gt->i915;
461 struct intel_gt_info *info = >->info;
462 struct intel_uncore *uncore = gt->uncore;
463 unsigned int logical_vdbox = 0;
464 unsigned int i;
465 u32 media_fuse;
466 u16 vdbox_mask;
467 u16 vebox_mask;
468
469 info->engine_mask = INTEL_INFO(i915)->platform_engine_mask;
470
471 if (GRAPHICS_VER(i915) < 11)
472 return info->engine_mask;
473
474 media_fuse = ~intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
475
476 vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
477 vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
478 GEN11_GT_VEBOX_DISABLE_SHIFT;
479
480 for (i = 0; i < I915_MAX_VCS; i++) {
481 if (!HAS_ENGINE(gt, _VCS(i))) {
482 vdbox_mask &= ~BIT(i);
483 continue;
484 }
485
486 if (!(BIT(i) & vdbox_mask)) {
487 info->engine_mask &= ~BIT(_VCS(i));
488 drm_dbg(&i915->drm, "vcs%u fused off\n", i);
489 continue;
490 }
491
492 /*
493 * In Gen11, only even numbered logical VDBOXes are
494 * hooked up to an SFC (Scaler & Format Converter) unit.
495 * In TGL each VDBOX has access to an SFC.
496 */
497 if (GRAPHICS_VER(i915) >= 12 || logical_vdbox++ % 2 == 0)
498 gt->info.vdbox_sfc_access |= BIT(i);
499 }
500 drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n",
501 vdbox_mask, VDBOX_MASK(gt));
502 GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt));
503
504 for (i = 0; i < I915_MAX_VECS; i++) {
505 if (!HAS_ENGINE(gt, _VECS(i))) {
506 vebox_mask &= ~BIT(i);
507 continue;
508 }
509
510 if (!(BIT(i) & vebox_mask)) {
511 info->engine_mask &= ~BIT(_VECS(i));
512 drm_dbg(&i915->drm, "vecs%u fused off\n", i);
513 }
514 }
515 drm_dbg(&i915->drm, "vebox enable: %04x, instances: %04lx\n",
516 vebox_mask, VEBOX_MASK(gt));
517 GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt));
518
519 return info->engine_mask;
520}
521
522/**
523 * intel_engines_init_mmio() - allocate and prepare the Engine Command Streamers
524 * @gt: pointer to struct intel_gt
525 *
526 * Return: non-zero if the initialization failed.
527 */
528int intel_engines_init_mmio(struct intel_gt *gt)
529{
530 struct drm_i915_private *i915 = gt->i915;
531 const unsigned int engine_mask = init_engine_mask(gt);
532 unsigned int mask = 0;
533 unsigned int i;
534 int err;
535
536 drm_WARN_ON(&i915->drm, engine_mask == 0);
537 drm_WARN_ON(&i915->drm, engine_mask &
538 GENMASK(BITS_PER_TYPE(mask) - 1, I915_NUM_ENGINES));
539
540 if (i915_inject_probe_failure(i915))
541 return -ENODEV;
542
543 for (i = 0; i < ARRAY_SIZE(intel_engines); i++) {
544 if (!HAS_ENGINE(gt, i))
545 continue;
546
547 err = intel_engine_setup(gt, i);
548 if (err)
549 goto cleanup;
550
551 mask |= BIT(i);
552 }
553
554 /*
555 * Catch failures to update intel_engines table when the new engines
556 * are added to the driver by a warning and disabling the forgotten
557 * engines.
558 */
559 if (drm_WARN_ON(&i915->drm, mask != engine_mask))
560 gt->info.engine_mask = mask;
561
562 gt->info.num_engines = hweight32(mask);
563
564 intel_gt_check_and_clear_faults(gt);
565
566 intel_setup_engine_capabilities(gt);
567
568 intel_uncore_prune_engine_fw_domains(gt->uncore, gt);
569
570 return 0;
571
572cleanup:
573 intel_engines_free(gt);
574 return err;
575}
576
577void intel_engine_init_execlists(struct intel_engine_cs *engine)
578{
579 struct intel_engine_execlists * const execlists = &engine->execlists;
580
581 execlists->port_mask = 1;
582 GEM_BUG_ON(!is_power_of_2(execlists_num_ports(execlists)));
583 GEM_BUG_ON(execlists_num_ports(execlists) > EXECLIST_MAX_PORTS);
584
585 memset(execlists->pending, 0, sizeof(execlists->pending));
586 execlists->active =
587 memset(execlists->inflight, 0, sizeof(execlists->inflight));
588
589 execlists->queue_priority_hint = INT_MIN;
590 execlists->queue = RB_ROOT_CACHED;
591}
592
593static void cleanup_status_page(struct intel_engine_cs *engine)
594{
595 struct i915_vma *vma;
596
597 /* Prevent writes into HWSP after returning the page to the system */
598 intel_engine_set_hwsp_writemask(engine, ~0u);
599
600 vma = fetch_and_zero(&engine->status_page.vma);
601 if (!vma)
602 return;
603
604 if (!HWS_NEEDS_PHYSICAL(engine->i915))
605 i915_vma_unpin(vma);
606
607 i915_gem_object_unpin_map(vma->obj);
608 i915_gem_object_put(vma->obj);
609}
610
611static int pin_ggtt_status_page(struct intel_engine_cs *engine,
612 struct i915_gem_ww_ctx *ww,
613 struct i915_vma *vma)
614{
615 unsigned int flags;
616
617 if (!HAS_LLC(engine->i915) && i915_ggtt_has_aperture(engine->gt->ggtt))
618 /*
619 * On g33, we cannot place HWS above 256MiB, so
620 * restrict its pinning to the low mappable arena.
621 * Though this restriction is not documented for
622 * gen4, gen5, or byt, they also behave similarly
623 * and hang if the HWS is placed at the top of the
624 * GTT. To generalise, it appears that all !llc
625 * platforms have issues with us placing the HWS
626 * above the mappable region (even though we never
627 * actually map it).
628 */
629 flags = PIN_MAPPABLE;
630 else
631 flags = PIN_HIGH;
632
633 return i915_ggtt_pin(vma, ww, 0, flags);
634}
635
636static int init_status_page(struct intel_engine_cs *engine)
637{
638 struct drm_i915_gem_object *obj;
639 struct i915_gem_ww_ctx ww;
640 struct i915_vma *vma;
641 void *vaddr;
642 int ret;
643
644 INIT_LIST_HEAD(&engine->status_page.timelines);
645
646 /*
647 * Though the HWS register does support 36bit addresses, historically
648 * we have had hangs and corruption reported due to wild writes if
649 * the HWS is placed above 4G. We only allow objects to be allocated
650 * in GFP_DMA32 for i965, and no earlier physical address users had
651 * access to more than 4G.
652 */
653 obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
654 if (IS_ERR(obj)) {
655 drm_err(&engine->i915->drm,
656 "Failed to allocate status page\n");
657 return PTR_ERR(obj);
658 }
659
660 i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC);
661
662 vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);
663 if (IS_ERR(vma)) {
664 ret = PTR_ERR(vma);
665 goto err_put;
666 }
667
668 i915_gem_ww_ctx_init(&ww, true);
669retry:
670 ret = i915_gem_object_lock(obj, &ww);
671 if (!ret && !HWS_NEEDS_PHYSICAL(engine->i915))
672 ret = pin_ggtt_status_page(engine, &ww, vma);
673 if (ret)
674 goto err;
675
676 vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
677 if (IS_ERR(vaddr)) {
678 ret = PTR_ERR(vaddr);
679 goto err_unpin;
680 }
681
682 engine->status_page.addr = memset(vaddr, 0, PAGE_SIZE);
683 engine->status_page.vma = vma;
684
685err_unpin:
686 if (ret)
687 i915_vma_unpin(vma);
688err:
689 if (ret == -EDEADLK) {
690 ret = i915_gem_ww_ctx_backoff(&ww);
691 if (!ret)
692 goto retry;
693 }
694 i915_gem_ww_ctx_fini(&ww);
695err_put:
696 if (ret)
697 i915_gem_object_put(obj);
698 return ret;
699}
700
701static int engine_setup_common(struct intel_engine_cs *engine)
702{
703 int err;
704
705 init_llist_head(&engine->barrier_tasks);
706
707 err = init_status_page(engine);
708 if (err)
709 return err;
710
711 engine->breadcrumbs = intel_breadcrumbs_create(engine);
712 if (!engine->breadcrumbs) {
713 err = -ENOMEM;
714 goto err_status;
715 }
716
717 err = intel_engine_init_cmd_parser(engine);
718 if (err)
719 goto err_cmd_parser;
720
721 intel_engine_init_active(engine, ENGINE_PHYSICAL);
722 intel_engine_init_execlists(engine);
723 intel_engine_init__pm(engine);
724 intel_engine_init_retire(engine);
725
726 /* Use the whole device by default */
727 engine->sseu =
728 intel_sseu_from_device_info(&engine->gt->info.sseu);
729
730 intel_engine_init_workarounds(engine);
731 intel_engine_init_whitelist(engine);
732 intel_engine_init_ctx_wa(engine);
733
734 if (GRAPHICS_VER(engine->i915) >= 12)
735 engine->flags |= I915_ENGINE_HAS_RELATIVE_MMIO;
736
737 return 0;
738
739err_cmd_parser:
740 intel_breadcrumbs_free(engine->breadcrumbs);
741err_status:
742 cleanup_status_page(engine);
743 return err;
744}
745
746struct measure_breadcrumb {
747 struct i915_request rq;
748 struct intel_ring ring;
749 u32 cs[2048];
750};
751
752static int measure_breadcrumb_dw(struct intel_context *ce)
753{
754 struct intel_engine_cs *engine = ce->engine;
755 struct measure_breadcrumb *frame;
756 int dw;
757
758 GEM_BUG_ON(!engine->gt->scratch);
759
760 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
761 if (!frame)
762 return -ENOMEM;
763
764 frame->rq.engine = engine;
765 frame->rq.context = ce;
766 rcu_assign_pointer(frame->rq.timeline, ce->timeline);
767 frame->rq.hwsp_seqno = ce->timeline->hwsp_seqno;
768
769 frame->ring.vaddr = frame->cs;
770 frame->ring.size = sizeof(frame->cs);
771 frame->ring.wrap =
772 BITS_PER_TYPE(frame->ring.size) - ilog2(frame->ring.size);
773 frame->ring.effective_size = frame->ring.size;
774 intel_ring_update_space(&frame->ring);
775 frame->rq.ring = &frame->ring;
776
777 mutex_lock(&ce->timeline->mutex);
778 spin_lock_irq(&engine->active.lock);
779
780 dw = engine->emit_fini_breadcrumb(&frame->rq, frame->cs) - frame->cs;
781
782 spin_unlock_irq(&engine->active.lock);
783 mutex_unlock(&ce->timeline->mutex);
784
785 GEM_BUG_ON(dw & 1); /* RING_TAIL must be qword aligned */
786
787 kfree(frame);
788 return dw;
789}
790
791void
792intel_engine_init_active(struct intel_engine_cs *engine, unsigned int subclass)
793{
794 INIT_LIST_HEAD(&engine->active.requests);
795 INIT_LIST_HEAD(&engine->active.hold);
796
797 spin_lock_init(&engine->active.lock);
798 lockdep_set_subclass(&engine->active.lock, subclass);
799
800 /*
801 * Due to an interesting quirk in lockdep's internal debug tracking,
802 * after setting a subclass we must ensure the lock is used. Otherwise,
803 * nr_unused_locks is incremented once too often.
804 */
805#ifdef CONFIG_DEBUG_LOCK_ALLOC
806 local_irq_disable();
807 lock_map_acquire(&engine->active.lock.dep_map);
808 lock_map_release(&engine->active.lock.dep_map);
809 local_irq_enable();
810#endif
811}
812
813static struct intel_context *
814create_pinned_context(struct intel_engine_cs *engine,
815 unsigned int hwsp,
816 struct lock_class_key *key,
817 const char *name)
818{
819 struct intel_context *ce;
820 int err;
821
822 ce = intel_context_create(engine);
823 if (IS_ERR(ce))
824 return ce;
825
826 __set_bit(CONTEXT_BARRIER_BIT, &ce->flags);
827 ce->timeline = page_pack_bits(NULL, hwsp);
828
829 err = intel_context_pin(ce); /* perma-pin so it is always available */
830 if (err) {
831 intel_context_put(ce);
832 return ERR_PTR(err);
833 }
834
835 /*
836 * Give our perma-pinned kernel timelines a separate lockdep class,
837 * so that we can use them from within the normal user timelines
838 * should we need to inject GPU operations during their request
839 * construction.
840 */
841 lockdep_set_class_and_name(&ce->timeline->mutex, key, name);
842
843 return ce;
844}
845
846static void destroy_pinned_context(struct intel_context *ce)
847{
848 struct intel_engine_cs *engine = ce->engine;
849 struct i915_vma *hwsp = engine->status_page.vma;
850
851 GEM_BUG_ON(ce->timeline->hwsp_ggtt != hwsp);
852
853 mutex_lock(&hwsp->vm->mutex);
854 list_del(&ce->timeline->engine_link);
855 mutex_unlock(&hwsp->vm->mutex);
856
857 intel_context_unpin(ce);
858 intel_context_put(ce);
859}
860
861static struct intel_context *
862create_kernel_context(struct intel_engine_cs *engine)
863{
864 static struct lock_class_key kernel;
865
866 return create_pinned_context(engine, I915_GEM_HWS_SEQNO_ADDR,
867 &kernel, "kernel_context");
868}
869
870/**
871 * intel_engines_init_common - initialize cengine state which might require hw access
872 * @engine: Engine to initialize.
873 *
874 * Initializes @engine@ structure members shared between legacy and execlists
875 * submission modes which do require hardware access.
876 *
877 * Typcally done at later stages of submission mode specific engine setup.
878 *
879 * Returns zero on success or an error code on failure.
880 */
881static int engine_init_common(struct intel_engine_cs *engine)
882{
883 struct intel_context *ce;
884 int ret;
885
886 engine->set_default_submission(engine);
887
888 /*
889 * We may need to do things with the shrinker which
890 * require us to immediately switch back to the default
891 * context. This can cause a problem as pinning the
892 * default context also requires GTT space which may not
893 * be available. To avoid this we always pin the default
894 * context.
895 */
896 ce = create_kernel_context(engine);
897 if (IS_ERR(ce))
898 return PTR_ERR(ce);
899
900 ret = measure_breadcrumb_dw(ce);
901 if (ret < 0)
902 goto err_context;
903
904 engine->emit_fini_breadcrumb_dw = ret;
905 engine->kernel_context = ce;
906
907 return 0;
908
909err_context:
910 destroy_pinned_context(ce);
911 return ret;
912}
913
914int intel_engines_init(struct intel_gt *gt)
915{
916 int (*setup)(struct intel_engine_cs *engine);
917 struct intel_engine_cs *engine;
918 enum intel_engine_id id;
919 int err;
920
921 if (intel_uc_uses_guc_submission(>->uc)) {
922 gt->submission_method = INTEL_SUBMISSION_GUC;
923 setup = intel_guc_submission_setup;
924 } else if (HAS_EXECLISTS(gt->i915)) {
925 gt->submission_method = INTEL_SUBMISSION_ELSP;
926 setup = intel_execlists_submission_setup;
927 } else {
928 gt->submission_method = INTEL_SUBMISSION_RING;
929 setup = intel_ring_submission_setup;
930 }
931
932 for_each_engine(engine, gt, id) {
933 err = engine_setup_common(engine);
934 if (err)
935 return err;
936
937 err = setup(engine);
938 if (err)
939 return err;
940
941 err = engine_init_common(engine);
942 if (err)
943 return err;
944
945 intel_engine_add_user(engine);
946 }
947
948 return 0;
949}
950
951/**
952 * intel_engines_cleanup_common - cleans up the engine state created by
953 * the common initiailizers.
954 * @engine: Engine to cleanup.
955 *
956 * This cleans up everything created by the common helpers.
957 */
958void intel_engine_cleanup_common(struct intel_engine_cs *engine)
959{
960 GEM_BUG_ON(!list_empty(&engine->active.requests));
961 tasklet_kill(&engine->execlists.tasklet); /* flush the callback */
962
963 intel_breadcrumbs_free(engine->breadcrumbs);
964
965 intel_engine_fini_retire(engine);
966 intel_engine_cleanup_cmd_parser(engine);
967
968 if (engine->default_state)
969 fput(engine->default_state);
970
971 if (engine->kernel_context)
972 destroy_pinned_context(engine->kernel_context);
973
974 GEM_BUG_ON(!llist_empty(&engine->barrier_tasks));
975 cleanup_status_page(engine);
976
977 intel_wa_list_free(&engine->ctx_wa_list);
978 intel_wa_list_free(&engine->wa_list);
979 intel_wa_list_free(&engine->whitelist);
980}
981
982/**
983 * intel_engine_resume - re-initializes the HW state of the engine
984 * @engine: Engine to resume.
985 *
986 * Returns zero on success or an error code on failure.
987 */
988int intel_engine_resume(struct intel_engine_cs *engine)
989{
990 intel_engine_apply_workarounds(engine);
991 intel_engine_apply_whitelist(engine);
992
993 return engine->resume(engine);
994}
995
996u64 intel_engine_get_active_head(const struct intel_engine_cs *engine)
997{
998 struct drm_i915_private *i915 = engine->i915;
999
1000 u64 acthd;
1001
1002 if (GRAPHICS_VER(i915) >= 8)
1003 acthd = ENGINE_READ64(engine, RING_ACTHD, RING_ACTHD_UDW);
1004 else if (GRAPHICS_VER(i915) >= 4)
1005 acthd = ENGINE_READ(engine, RING_ACTHD);
1006 else
1007 acthd = ENGINE_READ(engine, ACTHD);
1008
1009 return acthd;
1010}
1011
1012u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine)
1013{
1014 u64 bbaddr;
1015
1016 if (GRAPHICS_VER(engine->i915) >= 8)
1017 bbaddr = ENGINE_READ64(engine, RING_BBADDR, RING_BBADDR_UDW);
1018 else
1019 bbaddr = ENGINE_READ(engine, RING_BBADDR);
1020
1021 return bbaddr;
1022}
1023
1024static unsigned long stop_timeout(const struct intel_engine_cs *engine)
1025{
1026 if (in_atomic() || irqs_disabled()) /* inside atomic preempt-reset? */
1027 return 0;
1028
1029 /*
1030 * If we are doing a normal GPU reset, we can take our time and allow
1031 * the engine to quiesce. We've stopped submission to the engine, and
1032 * if we wait long enough an innocent context should complete and
1033 * leave the engine idle. So they should not be caught unaware by
1034 * the forthcoming GPU reset (which usually follows the stop_cs)!
1035 */
1036 return READ_ONCE(engine->props.stop_timeout_ms);
1037}
1038
1039static int __intel_engine_stop_cs(struct intel_engine_cs *engine,
1040 int fast_timeout_us,
1041 int slow_timeout_ms)
1042{
1043 struct intel_uncore *uncore = engine->uncore;
1044 const i915_reg_t mode = RING_MI_MODE(engine->mmio_base);
1045 int err;
1046
1047 intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING));
1048 err = __intel_wait_for_register_fw(engine->uncore, mode,
1049 MODE_IDLE, MODE_IDLE,
1050 fast_timeout_us,
1051 slow_timeout_ms,
1052 NULL);
1053
1054 /* A final mmio read to let GPU writes be hopefully flushed to memory */
1055 intel_uncore_posting_read_fw(uncore, mode);
1056 return err;
1057}
1058
1059int intel_engine_stop_cs(struct intel_engine_cs *engine)
1060{
1061 int err = 0;
1062
1063 if (GRAPHICS_VER(engine->i915) < 3)
1064 return -ENODEV;
1065
1066 ENGINE_TRACE(engine, "\n");
1067 if (__intel_engine_stop_cs(engine, 1000, stop_timeout(engine))) {
1068 ENGINE_TRACE(engine,
1069 "timed out on STOP_RING -> IDLE; HEAD:%04x, TAIL:%04x\n",
1070 ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR,
1071 ENGINE_READ_FW(engine, RING_TAIL) & TAIL_ADDR);
1072
1073 /*
1074 * Sometimes we observe that the idle flag is not
1075 * set even though the ring is empty. So double
1076 * check before giving up.
1077 */
1078 if ((ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR) !=
1079 (ENGINE_READ_FW(engine, RING_TAIL) & TAIL_ADDR))
1080 err = -ETIMEDOUT;
1081 }
1082
1083 return err;
1084}
1085
1086void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine)
1087{
1088 ENGINE_TRACE(engine, "\n");
1089
1090 ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
1091}
1092
1093const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
1094{
1095 switch (type) {
1096 case I915_CACHE_NONE: return " uncached";
1097 case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped";
1098 case I915_CACHE_L3_LLC: return " L3+LLC";
1099 case I915_CACHE_WT: return " WT";
1100 default: return "";
1101 }
1102}
1103
1104static u32
1105read_subslice_reg(const struct intel_engine_cs *engine,
1106 int slice, int subslice, i915_reg_t reg)
1107{
1108 struct drm_i915_private *i915 = engine->i915;
1109 struct intel_uncore *uncore = engine->uncore;
1110 u32 mcr_mask, mcr_ss, mcr, old_mcr, val;
1111 enum forcewake_domains fw_domains;
1112
1113 if (GRAPHICS_VER(i915) >= 11) {
1114 mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK;
1115 mcr_ss = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice);
1116 } else {
1117 mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK;
1118 mcr_ss = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
1119 }
1120
1121 fw_domains = intel_uncore_forcewake_for_reg(uncore, reg,
1122 FW_REG_READ);
1123 fw_domains |= intel_uncore_forcewake_for_reg(uncore,
1124 GEN8_MCR_SELECTOR,
1125 FW_REG_READ | FW_REG_WRITE);
1126
1127 spin_lock_irq(&uncore->lock);
1128 intel_uncore_forcewake_get__locked(uncore, fw_domains);
1129
1130 old_mcr = mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR);
1131
1132 mcr &= ~mcr_mask;
1133 mcr |= mcr_ss;
1134 intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
1135
1136 val = intel_uncore_read_fw(uncore, reg);
1137
1138 mcr &= ~mcr_mask;
1139 mcr |= old_mcr & mcr_mask;
1140
1141 intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
1142
1143 intel_uncore_forcewake_put__locked(uncore, fw_domains);
1144 spin_unlock_irq(&uncore->lock);
1145
1146 return val;
1147}
1148
1149/* NB: please notice the memset */
1150void intel_engine_get_instdone(const struct intel_engine_cs *engine,
1151 struct intel_instdone *instdone)
1152{
1153 struct drm_i915_private *i915 = engine->i915;
1154 const struct sseu_dev_info *sseu = &engine->gt->info.sseu;
1155 struct intel_uncore *uncore = engine->uncore;
1156 u32 mmio_base = engine->mmio_base;
1157 int slice;
1158 int subslice;
1159
1160 memset(instdone, 0, sizeof(*instdone));
1161
1162 switch (GRAPHICS_VER(i915)) {
1163 default:
1164 instdone->instdone =
1165 intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
1166
1167 if (engine->id != RCS0)
1168 break;
1169
1170 instdone->slice_common =
1171 intel_uncore_read(uncore, GEN7_SC_INSTDONE);
1172 if (GRAPHICS_VER(i915) >= 12) {
1173 instdone->slice_common_extra[0] =
1174 intel_uncore_read(uncore, GEN12_SC_INSTDONE_EXTRA);
1175 instdone->slice_common_extra[1] =
1176 intel_uncore_read(uncore, GEN12_SC_INSTDONE_EXTRA2);
1177 }
1178 for_each_instdone_slice_subslice(i915, sseu, slice, subslice) {
1179 instdone->sampler[slice][subslice] =
1180 read_subslice_reg(engine, slice, subslice,
1181 GEN7_SAMPLER_INSTDONE);
1182 instdone->row[slice][subslice] =
1183 read_subslice_reg(engine, slice, subslice,
1184 GEN7_ROW_INSTDONE);
1185 }
1186 break;
1187 case 7:
1188 instdone->instdone =
1189 intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
1190
1191 if (engine->id != RCS0)
1192 break;
1193
1194 instdone->slice_common =
1195 intel_uncore_read(uncore, GEN7_SC_INSTDONE);
1196 instdone->sampler[0][0] =
1197 intel_uncore_read(uncore, GEN7_SAMPLER_INSTDONE);
1198 instdone->row[0][0] =
1199 intel_uncore_read(uncore, GEN7_ROW_INSTDONE);
1200
1201 break;
1202 case 6:
1203 case 5:
1204 case 4:
1205 instdone->instdone =
1206 intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
1207 if (engine->id == RCS0)
1208 /* HACK: Using the wrong struct member */
1209 instdone->slice_common =
1210 intel_uncore_read(uncore, GEN4_INSTDONE1);
1211 break;
1212 case 3:
1213 case 2:
1214 instdone->instdone = intel_uncore_read(uncore, GEN2_INSTDONE);
1215 break;
1216 }
1217}
1218
1219static bool ring_is_idle(struct intel_engine_cs *engine)
1220{
1221 bool idle = true;
1222
1223 if (I915_SELFTEST_ONLY(!engine->mmio_base))
1224 return true;
1225
1226 if (!intel_engine_pm_get_if_awake(engine))
1227 return true;
1228
1229 /* First check that no commands are left in the ring */
1230 if ((ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR) !=
1231 (ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR))
1232 idle = false;
1233
1234 /* No bit for gen2, so assume the CS parser is idle */
1235 if (GRAPHICS_VER(engine->i915) > 2 &&
1236 !(ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE))
1237 idle = false;
1238
1239 intel_engine_pm_put(engine);
1240
1241 return idle;
1242}
1243
1244void __intel_engine_flush_submission(struct intel_engine_cs *engine, bool sync)
1245{
1246 struct tasklet_struct *t = &engine->execlists.tasklet;
1247
1248 if (!t->callback)
1249 return;
1250
1251 local_bh_disable();
1252 if (tasklet_trylock(t)) {
1253 /* Must wait for any GPU reset in progress. */
1254 if (__tasklet_is_enabled(t))
1255 t->callback(t);
1256 tasklet_unlock(t);
1257 }
1258 local_bh_enable();
1259
1260 /* Synchronise and wait for the tasklet on another CPU */
1261 if (sync)
1262 tasklet_unlock_wait(t);
1263}
1264
1265/**
1266 * intel_engine_is_idle() - Report if the engine has finished process all work
1267 * @engine: the intel_engine_cs
1268 *
1269 * Return true if there are no requests pending, nothing left to be submitted
1270 * to hardware, and that the engine is idle.
1271 */
1272bool intel_engine_is_idle(struct intel_engine_cs *engine)
1273{
1274 /* More white lies, if wedged, hw state is inconsistent */
1275 if (intel_gt_is_wedged(engine->gt))
1276 return true;
1277
1278 if (!intel_engine_pm_is_awake(engine))
1279 return true;
1280
1281 /* Waiting to drain ELSP? */
1282 intel_synchronize_hardirq(engine->i915);
1283 intel_engine_flush_submission(engine);
1284
1285 /* ELSP is empty, but there are ready requests? E.g. after reset */
1286 if (!RB_EMPTY_ROOT(&engine->execlists.queue.rb_root))
1287 return false;
1288
1289 /* Ring stopped? */
1290 return ring_is_idle(engine);
1291}
1292
1293bool intel_engines_are_idle(struct intel_gt *gt)
1294{
1295 struct intel_engine_cs *engine;
1296 enum intel_engine_id id;
1297
1298 /*
1299 * If the driver is wedged, HW state may be very inconsistent and
1300 * report that it is still busy, even though we have stopped using it.
1301 */
1302 if (intel_gt_is_wedged(gt))
1303 return true;
1304
1305 /* Already parked (and passed an idleness test); must still be idle */
1306 if (!READ_ONCE(gt->awake))
1307 return true;
1308
1309 for_each_engine(engine, gt, id) {
1310 if (!intel_engine_is_idle(engine))
1311 return false;
1312 }
1313
1314 return true;
1315}
1316
1317void intel_engines_reset_default_submission(struct intel_gt *gt)
1318{
1319 struct intel_engine_cs *engine;
1320 enum intel_engine_id id;
1321
1322 for_each_engine(engine, gt, id) {
1323 if (engine->sanitize)
1324 engine->sanitize(engine);
1325
1326 engine->set_default_submission(engine);
1327 }
1328}
1329
1330bool intel_engine_can_store_dword(struct intel_engine_cs *engine)
1331{
1332 switch (GRAPHICS_VER(engine->i915)) {
1333 case 2:
1334 return false; /* uses physical not virtual addresses */
1335 case 3:
1336 /* maybe only uses physical not virtual addresses */
1337 return !(IS_I915G(engine->i915) || IS_I915GM(engine->i915));
1338 case 4:
1339 return !IS_I965G(engine->i915); /* who knows! */
1340 case 6:
1341 return engine->class != VIDEO_DECODE_CLASS; /* b0rked */
1342 default:
1343 return true;
1344 }
1345}
1346
1347static struct intel_timeline *get_timeline(struct i915_request *rq)
1348{
1349 struct intel_timeline *tl;
1350
1351 /*
1352 * Even though we are holding the engine->active.lock here, there
1353 * is no control over the submission queue per-se and we are
1354 * inspecting the active state at a random point in time, with an
1355 * unknown queue. Play safe and make sure the timeline remains valid.
1356 * (Only being used for pretty printing, one extra kref shouldn't
1357 * cause a camel stampede!)
1358 */
1359 rcu_read_lock();
1360 tl = rcu_dereference(rq->timeline);
1361 if (!kref_get_unless_zero(&tl->kref))
1362 tl = NULL;
1363 rcu_read_unlock();
1364
1365 return tl;
1366}
1367
1368static int print_ring(char *buf, int sz, struct i915_request *rq)
1369{
1370 int len = 0;
1371
1372 if (!i915_request_signaled(rq)) {
1373 struct intel_timeline *tl = get_timeline(rq);
1374
1375 len = scnprintf(buf, sz,
1376 "ring:{start:%08x, hwsp:%08x, seqno:%08x, runtime:%llums}, ",
1377 i915_ggtt_offset(rq->ring->vma),
1378 tl ? tl->hwsp_offset : 0,
1379 hwsp_seqno(rq),
1380 DIV_ROUND_CLOSEST_ULL(intel_context_get_total_runtime_ns(rq->context),
1381 1000 * 1000));
1382
1383 if (tl)
1384 intel_timeline_put(tl);
1385 }
1386
1387 return len;
1388}
1389
1390static void hexdump(struct drm_printer *m, const void *buf, size_t len)
1391{
1392 const size_t rowsize = 8 * sizeof(u32);
1393 const void *prev = NULL;
1394 bool skip = false;
1395 size_t pos;
1396
1397 for (pos = 0; pos < len; pos += rowsize) {
1398 char line[128];
1399
1400 if (prev && !memcmp(prev, buf + pos, rowsize)) {
1401 if (!skip) {
1402 drm_printf(m, "*\n");
1403 skip = true;
1404 }
1405 continue;
1406 }
1407
1408 WARN_ON_ONCE(hex_dump_to_buffer(buf + pos, len - pos,
1409 rowsize, sizeof(u32),
1410 line, sizeof(line),
1411 false) >= sizeof(line));
1412 drm_printf(m, "[%04zx] %s\n", pos, line);
1413
1414 prev = buf + pos;
1415 skip = false;
1416 }
1417}
1418
1419static const char *repr_timer(const struct timer_list *t)
1420{
1421 if (!READ_ONCE(t->expires))
1422 return "inactive";
1423
1424 if (timer_pending(t))
1425 return "active";
1426
1427 return "expired";
1428}
1429
1430static void intel_engine_print_registers(struct intel_engine_cs *engine,
1431 struct drm_printer *m)
1432{
1433 struct drm_i915_private *dev_priv = engine->i915;
1434 struct intel_engine_execlists * const execlists = &engine->execlists;
1435 u64 addr;
1436
1437 if (engine->id == RENDER_CLASS && IS_GRAPHICS_VER(dev_priv, 4, 7))
1438 drm_printf(m, "\tCCID: 0x%08x\n", ENGINE_READ(engine, CCID));
1439 if (HAS_EXECLISTS(dev_priv)) {
1440 drm_printf(m, "\tEL_STAT_HI: 0x%08x\n",
1441 ENGINE_READ(engine, RING_EXECLIST_STATUS_HI));
1442 drm_printf(m, "\tEL_STAT_LO: 0x%08x\n",
1443 ENGINE_READ(engine, RING_EXECLIST_STATUS_LO));
1444 }
1445 drm_printf(m, "\tRING_START: 0x%08x\n",
1446 ENGINE_READ(engine, RING_START));
1447 drm_printf(m, "\tRING_HEAD: 0x%08x\n",
1448 ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR);
1449 drm_printf(m, "\tRING_TAIL: 0x%08x\n",
1450 ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR);
1451 drm_printf(m, "\tRING_CTL: 0x%08x%s\n",
1452 ENGINE_READ(engine, RING_CTL),
1453 ENGINE_READ(engine, RING_CTL) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? " [waiting]" : "");
1454 if (GRAPHICS_VER(engine->i915) > 2) {
1455 drm_printf(m, "\tRING_MODE: 0x%08x%s\n",
1456 ENGINE_READ(engine, RING_MI_MODE),
1457 ENGINE_READ(engine, RING_MI_MODE) & (MODE_IDLE) ? " [idle]" : "");
1458 }
1459
1460 if (GRAPHICS_VER(dev_priv) >= 6) {
1461 drm_printf(m, "\tRING_IMR: 0x%08x\n",
1462 ENGINE_READ(engine, RING_IMR));
1463 drm_printf(m, "\tRING_ESR: 0x%08x\n",
1464 ENGINE_READ(engine, RING_ESR));
1465 drm_printf(m, "\tRING_EMR: 0x%08x\n",
1466 ENGINE_READ(engine, RING_EMR));
1467 drm_printf(m, "\tRING_EIR: 0x%08x\n",
1468 ENGINE_READ(engine, RING_EIR));
1469 }
1470
1471 addr = intel_engine_get_active_head(engine);
1472 drm_printf(m, "\tACTHD: 0x%08x_%08x\n",
1473 upper_32_bits(addr), lower_32_bits(addr));
1474 addr = intel_engine_get_last_batch_head(engine);
1475 drm_printf(m, "\tBBADDR: 0x%08x_%08x\n",
1476 upper_32_bits(addr), lower_32_bits(addr));
1477 if (GRAPHICS_VER(dev_priv) >= 8)
1478 addr = ENGINE_READ64(engine, RING_DMA_FADD, RING_DMA_FADD_UDW);
1479 else if (GRAPHICS_VER(dev_priv) >= 4)
1480 addr = ENGINE_READ(engine, RING_DMA_FADD);
1481 else
1482 addr = ENGINE_READ(engine, DMA_FADD_I8XX);
1483 drm_printf(m, "\tDMA_FADDR: 0x%08x_%08x\n",
1484 upper_32_bits(addr), lower_32_bits(addr));
1485 if (GRAPHICS_VER(dev_priv) >= 4) {
1486 drm_printf(m, "\tIPEIR: 0x%08x\n",
1487 ENGINE_READ(engine, RING_IPEIR));
1488 drm_printf(m, "\tIPEHR: 0x%08x\n",
1489 ENGINE_READ(engine, RING_IPEHR));
1490 } else {
1491 drm_printf(m, "\tIPEIR: 0x%08x\n", ENGINE_READ(engine, IPEIR));
1492 drm_printf(m, "\tIPEHR: 0x%08x\n", ENGINE_READ(engine, IPEHR));
1493 }
1494
1495 if (intel_engine_uses_guc(engine)) {
1496 /* nothing to print yet */
1497 } else if (HAS_EXECLISTS(dev_priv)) {
1498 struct i915_request * const *port, *rq;
1499 const u32 *hws =
1500 &engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX];
1501 const u8 num_entries = execlists->csb_size;
1502 unsigned int idx;
1503 u8 read, write;
1504
1505 drm_printf(m, "\tExeclist tasklet queued? %s (%s), preempt? %s, timeslice? %s\n",
1506 yesno(test_bit(TASKLET_STATE_SCHED,
1507 &engine->execlists.tasklet.state)),
1508 enableddisabled(!atomic_read(&engine->execlists.tasklet.count)),
1509 repr_timer(&engine->execlists.preempt),
1510 repr_timer(&engine->execlists.timer));
1511
1512 read = execlists->csb_head;
1513 write = READ_ONCE(*execlists->csb_write);
1514
1515 drm_printf(m, "\tExeclist status: 0x%08x %08x; CSB read:%d, write:%d, entries:%d\n",
1516 ENGINE_READ(engine, RING_EXECLIST_STATUS_LO),
1517 ENGINE_READ(engine, RING_EXECLIST_STATUS_HI),
1518 read, write, num_entries);
1519
1520 if (read >= num_entries)
1521 read = 0;
1522 if (write >= num_entries)
1523 write = 0;
1524 if (read > write)
1525 write += num_entries;
1526 while (read < write) {
1527 idx = ++read % num_entries;
1528 drm_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n",
1529 idx, hws[idx * 2], hws[idx * 2 + 1]);
1530 }
1531
1532 execlists_active_lock_bh(execlists);
1533 rcu_read_lock();
1534 for (port = execlists->active; (rq = *port); port++) {
1535 char hdr[160];
1536 int len;
1537
1538 len = scnprintf(hdr, sizeof(hdr),
1539 "\t\tActive[%d]: ccid:%08x%s%s, ",
1540 (int)(port - execlists->active),
1541 rq->context->lrc.ccid,
1542 intel_context_is_closed(rq->context) ? "!" : "",
1543 intel_context_is_banned(rq->context) ? "*" : "");
1544 len += print_ring(hdr + len, sizeof(hdr) - len, rq);
1545 scnprintf(hdr + len, sizeof(hdr) - len, "rq: ");
1546 i915_request_show(m, rq, hdr, 0);
1547 }
1548 for (port = execlists->pending; (rq = *port); port++) {
1549 char hdr[160];
1550 int len;
1551
1552 len = scnprintf(hdr, sizeof(hdr),
1553 "\t\tPending[%d]: ccid:%08x%s%s, ",
1554 (int)(port - execlists->pending),
1555 rq->context->lrc.ccid,
1556 intel_context_is_closed(rq->context) ? "!" : "",
1557 intel_context_is_banned(rq->context) ? "*" : "");
1558 len += print_ring(hdr + len, sizeof(hdr) - len, rq);
1559 scnprintf(hdr + len, sizeof(hdr) - len, "rq: ");
1560 i915_request_show(m, rq, hdr, 0);
1561 }
1562 rcu_read_unlock();
1563 execlists_active_unlock_bh(execlists);
1564 } else if (GRAPHICS_VER(dev_priv) > 6) {
1565 drm_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
1566 ENGINE_READ(engine, RING_PP_DIR_BASE));
1567 drm_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n",
1568 ENGINE_READ(engine, RING_PP_DIR_BASE_READ));
1569 drm_printf(m, "\tPP_DIR_DCLV: 0x%08x\n",
1570 ENGINE_READ(engine, RING_PP_DIR_DCLV));
1571 }
1572}
1573
1574static void print_request_ring(struct drm_printer *m, struct i915_request *rq)
1575{
1576 void *ring;
1577 int size;
1578
1579 drm_printf(m,
1580 "[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]:\n",
1581 rq->head, rq->postfix, rq->tail,
1582 rq->batch ? upper_32_bits(rq->batch->node.start) : ~0u,
1583 rq->batch ? lower_32_bits(rq->batch->node.start) : ~0u);
1584
1585 size = rq->tail - rq->head;
1586 if (rq->tail < rq->head)
1587 size += rq->ring->size;
1588
1589 ring = kmalloc(size, GFP_ATOMIC);
1590 if (ring) {
1591 const void *vaddr = rq->ring->vaddr;
1592 unsigned int head = rq->head;
1593 unsigned int len = 0;
1594
1595 if (rq->tail < head) {
1596 len = rq->ring->size - head;
1597 memcpy(ring, vaddr + head, len);
1598 head = 0;
1599 }
1600 memcpy(ring + len, vaddr + head, size - len);
1601
1602 hexdump(m, ring, size);
1603 kfree(ring);
1604 }
1605}
1606
1607static unsigned long list_count(struct list_head *list)
1608{
1609 struct list_head *pos;
1610 unsigned long count = 0;
1611
1612 list_for_each(pos, list)
1613 count++;
1614
1615 return count;
1616}
1617
1618static unsigned long read_ul(void *p, size_t x)
1619{
1620 return *(unsigned long *)(p + x);
1621}
1622
1623static void print_properties(struct intel_engine_cs *engine,
1624 struct drm_printer *m)
1625{
1626 static const struct pmap {
1627 size_t offset;
1628 const char *name;
1629 } props[] = {
1630#define P(x) { \
1631 .offset = offsetof(typeof(engine->props), x), \
1632 .name = #x \
1633}
1634 P(heartbeat_interval_ms),
1635 P(max_busywait_duration_ns),
1636 P(preempt_timeout_ms),
1637 P(stop_timeout_ms),
1638 P(timeslice_duration_ms),
1639
1640 {},
1641#undef P
1642 };
1643 const struct pmap *p;
1644
1645 drm_printf(m, "\tProperties:\n");
1646 for (p = props; p->name; p++)
1647 drm_printf(m, "\t\t%s: %lu [default %lu]\n",
1648 p->name,
1649 read_ul(&engine->props, p->offset),
1650 read_ul(&engine->defaults, p->offset));
1651}
1652
1653void intel_engine_dump(struct intel_engine_cs *engine,
1654 struct drm_printer *m,
1655 const char *header, ...)
1656{
1657 struct i915_gpu_error * const error = &engine->i915->gpu_error;
1658 struct i915_request *rq;
1659 intel_wakeref_t wakeref;
1660 unsigned long flags;
1661 ktime_t dummy;
1662
1663 if (header) {
1664 va_list ap;
1665
1666 va_start(ap, header);
1667 drm_vprintf(m, header, &ap);
1668 va_end(ap);
1669 }
1670
1671 if (intel_gt_is_wedged(engine->gt))
1672 drm_printf(m, "*** WEDGED ***\n");
1673
1674 drm_printf(m, "\tAwake? %d\n", atomic_read(&engine->wakeref.count));
1675 drm_printf(m, "\tBarriers?: %s\n",
1676 yesno(!llist_empty(&engine->barrier_tasks)));
1677 drm_printf(m, "\tLatency: %luus\n",
1678 ewma__engine_latency_read(&engine->latency));
1679 if (intel_engine_supports_stats(engine))
1680 drm_printf(m, "\tRuntime: %llums\n",
1681 ktime_to_ms(intel_engine_get_busy_time(engine,
1682 &dummy)));
1683 drm_printf(m, "\tForcewake: %x domains, %d active\n",
1684 engine->fw_domain, READ_ONCE(engine->fw_active));
1685
1686 rcu_read_lock();
1687 rq = READ_ONCE(engine->heartbeat.systole);
1688 if (rq)
1689 drm_printf(m, "\tHeartbeat: %d ms ago\n",
1690 jiffies_to_msecs(jiffies - rq->emitted_jiffies));
1691 rcu_read_unlock();
1692 drm_printf(m, "\tReset count: %d (global %d)\n",
1693 i915_reset_engine_count(error, engine),
1694 i915_reset_count(error));
1695 print_properties(engine, m);
1696
1697 drm_printf(m, "\tRequests:\n");
1698
1699 spin_lock_irqsave(&engine->active.lock, flags);
1700 rq = intel_engine_find_active_request(engine);
1701 if (rq) {
1702 struct intel_timeline *tl = get_timeline(rq);
1703
1704 i915_request_show(m, rq, "\t\tactive ", 0);
1705
1706 drm_printf(m, "\t\tring->start: 0x%08x\n",
1707 i915_ggtt_offset(rq->ring->vma));
1708 drm_printf(m, "\t\tring->head: 0x%08x\n",
1709 rq->ring->head);
1710 drm_printf(m, "\t\tring->tail: 0x%08x\n",
1711 rq->ring->tail);
1712 drm_printf(m, "\t\tring->emit: 0x%08x\n",
1713 rq->ring->emit);
1714 drm_printf(m, "\t\tring->space: 0x%08x\n",
1715 rq->ring->space);
1716
1717 if (tl) {
1718 drm_printf(m, "\t\tring->hwsp: 0x%08x\n",
1719 tl->hwsp_offset);
1720 intel_timeline_put(tl);
1721 }
1722
1723 print_request_ring(m, rq);
1724
1725 if (rq->context->lrc_reg_state) {
1726 drm_printf(m, "Logical Ring Context:\n");
1727 hexdump(m, rq->context->lrc_reg_state, PAGE_SIZE);
1728 }
1729 }
1730 drm_printf(m, "\tOn hold?: %lu\n", list_count(&engine->active.hold));
1731 spin_unlock_irqrestore(&engine->active.lock, flags);
1732
1733 drm_printf(m, "\tMMIO base: 0x%08x\n", engine->mmio_base);
1734 wakeref = intel_runtime_pm_get_if_in_use(engine->uncore->rpm);
1735 if (wakeref) {
1736 intel_engine_print_registers(engine, m);
1737 intel_runtime_pm_put(engine->uncore->rpm, wakeref);
1738 } else {
1739 drm_printf(m, "\tDevice is asleep; skipping register dump\n");
1740 }
1741
1742 intel_execlists_show_requests(engine, m, i915_request_show, 8);
1743
1744 drm_printf(m, "HWSP:\n");
1745 hexdump(m, engine->status_page.addr, PAGE_SIZE);
1746
1747 drm_printf(m, "Idle? %s\n", yesno(intel_engine_is_idle(engine)));
1748
1749 intel_engine_print_breadcrumbs(engine, m);
1750}
1751
1752static ktime_t __intel_engine_get_busy_time(struct intel_engine_cs *engine,
1753 ktime_t *now)
1754{
1755 ktime_t total = engine->stats.total;
1756
1757 /*
1758 * If the engine is executing something at the moment
1759 * add it to the total.
1760 */
1761 *now = ktime_get();
1762 if (READ_ONCE(engine->stats.active))
1763 total = ktime_add(total, ktime_sub(*now, engine->stats.start));
1764
1765 return total;
1766}
1767
1768/**
1769 * intel_engine_get_busy_time() - Return current accumulated engine busyness
1770 * @engine: engine to report on
1771 * @now: monotonic timestamp of sampling
1772 *
1773 * Returns accumulated time @engine was busy since engine stats were enabled.
1774 */
1775ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine, ktime_t *now)
1776{
1777 unsigned int seq;
1778 ktime_t total;
1779
1780 do {
1781 seq = read_seqcount_begin(&engine->stats.lock);
1782 total = __intel_engine_get_busy_time(engine, now);
1783 } while (read_seqcount_retry(&engine->stats.lock, seq));
1784
1785 return total;
1786}
1787
1788static bool match_ring(struct i915_request *rq)
1789{
1790 u32 ring = ENGINE_READ(rq->engine, RING_START);
1791
1792 return ring == i915_ggtt_offset(rq->ring->vma);
1793}
1794
1795struct i915_request *
1796intel_engine_find_active_request(struct intel_engine_cs *engine)
1797{
1798 struct i915_request *request, *active = NULL;
1799
1800 /*
1801 * We are called by the error capture, reset and to dump engine
1802 * state at random points in time. In particular, note that neither is
1803 * crucially ordered with an interrupt. After a hang, the GPU is dead
1804 * and we assume that no more writes can happen (we waited long enough
1805 * for all writes that were in transaction to be flushed) - adding an
1806 * extra delay for a recent interrupt is pointless. Hence, we do
1807 * not need an engine->irq_seqno_barrier() before the seqno reads.
1808 * At all other times, we must assume the GPU is still running, but
1809 * we only care about the snapshot of this moment.
1810 */
1811 lockdep_assert_held(&engine->active.lock);
1812
1813 rcu_read_lock();
1814 request = execlists_active(&engine->execlists);
1815 if (request) {
1816 struct intel_timeline *tl = request->context->timeline;
1817
1818 list_for_each_entry_from_reverse(request, &tl->requests, link) {
1819 if (__i915_request_is_complete(request))
1820 break;
1821
1822 active = request;
1823 }
1824 }
1825 rcu_read_unlock();
1826 if (active)
1827 return active;
1828
1829 list_for_each_entry(request, &engine->active.requests, sched.link) {
1830 if (__i915_request_is_complete(request))
1831 continue;
1832
1833 if (!__i915_request_has_started(request))
1834 continue;
1835
1836 /* More than one preemptible request may match! */
1837 if (!match_ring(request))
1838 continue;
1839
1840 active = request;
1841 break;
1842 }
1843
1844 return active;
1845}
1846
1847#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1848#include "mock_engine.c"
1849#include "selftest_engine.c"
1850#include "selftest_engine_cs.c"
1851#endif