1/*
   2 * Copyright (C) 2014 NVIDIA CORPORATION.  All rights reserved.
   3 *
   4 * This program is free software; you can redistribute it and/or modify
   5 * it under the terms of the GNU General Public License version 2 as
   6 * published by the Free Software Foundation.
   7 */
   8
   9#include <linux/of.h>
  10#include <linux/mm.h>
  11
  12#include <dt-bindings/memory/tegra124-mc.h>
  13
  14#include "mc.h"
  15
  16#define MC_EMEM_ARB_CFG				0x90
  17#define MC_EMEM_ARB_OUTSTANDING_REQ		0x94
  18#define MC_EMEM_ARB_TIMING_RCD			0x98
  19#define MC_EMEM_ARB_TIMING_RP			0x9c
  20#define MC_EMEM_ARB_TIMING_RC			0xa0
  21#define MC_EMEM_ARB_TIMING_RAS			0xa4
  22#define MC_EMEM_ARB_TIMING_FAW			0xa8
  23#define MC_EMEM_ARB_TIMING_RRD			0xac
  24#define MC_EMEM_ARB_TIMING_RAP2PRE		0xb0
  25#define MC_EMEM_ARB_TIMING_WAP2PRE		0xb4
  26#define MC_EMEM_ARB_TIMING_R2R			0xb8
  27#define MC_EMEM_ARB_TIMING_W2W			0xbc
  28#define MC_EMEM_ARB_TIMING_R2W			0xc0
  29#define MC_EMEM_ARB_TIMING_W2R			0xc4
  30#define MC_EMEM_ARB_DA_TURNS			0xd0
  31#define MC_EMEM_ARB_DA_COVERS			0xd4
  32#define MC_EMEM_ARB_MISC0			0xd8
  33#define MC_EMEM_ARB_MISC1			0xdc
  34#define MC_EMEM_ARB_RING1_THROTTLE		0xe0
  35
  36static const unsigned long tegra124_mc_emem_regs[] = {
  37	MC_EMEM_ARB_CFG,
  38	MC_EMEM_ARB_OUTSTANDING_REQ,
  39	MC_EMEM_ARB_TIMING_RCD,
  40	MC_EMEM_ARB_TIMING_RP,
  41	MC_EMEM_ARB_TIMING_RC,
  42	MC_EMEM_ARB_TIMING_RAS,
  43	MC_EMEM_ARB_TIMING_FAW,
  44	MC_EMEM_ARB_TIMING_RRD,
  45	MC_EMEM_ARB_TIMING_RAP2PRE,
  46	MC_EMEM_ARB_TIMING_WAP2PRE,
  47	MC_EMEM_ARB_TIMING_R2R,
  48	MC_EMEM_ARB_TIMING_W2W,
  49	MC_EMEM_ARB_TIMING_R2W,
  50	MC_EMEM_ARB_TIMING_W2R,
  51	MC_EMEM_ARB_DA_TURNS,
  52	MC_EMEM_ARB_DA_COVERS,
  53	MC_EMEM_ARB_MISC0,
  54	MC_EMEM_ARB_MISC1,
  55	MC_EMEM_ARB_RING1_THROTTLE
  56};
  57
  58static const struct tegra_mc_client tegra124_mc_clients[] = {
  59	{
  60		.id = 0x00,
  61		.name = "ptcr",
  62		.swgroup = TEGRA_SWGROUP_PTC,
  63	}, {
  64		.id = 0x01,
  65		.name = "display0a",
  66		.swgroup = TEGRA_SWGROUP_DC,
  67		.smmu = {
  68			.reg = 0x228,
  69			.bit = 1,
  70		},
  71		.la = {
  72			.reg = 0x2e8,
  73			.shift = 0,
  74			.mask = 0xff,
  75			.def = 0xc2,
  76		},
  77	}, {
  78		.id = 0x02,
  79		.name = "display0ab",
  80		.swgroup = TEGRA_SWGROUP_DCB,
  81		.smmu = {
  82			.reg = 0x228,
  83			.bit = 2,
  84		},
  85		.la = {
  86			.reg = 0x2f4,
  87			.shift = 0,
  88			.mask = 0xff,
  89			.def = 0xc6,
  90		},
  91	}, {
  92		.id = 0x03,
  93		.name = "display0b",
  94		.swgroup = TEGRA_SWGROUP_DC,
  95		.smmu = {
  96			.reg = 0x228,
  97			.bit = 3,
  98		},
  99		.la = {
 100			.reg = 0x2e8,
 101			.shift = 16,
 102			.mask = 0xff,
 103			.def = 0x50,
 104		},
 105	}, {
 106		.id = 0x04,
 107		.name = "display0bb",
 108		.swgroup = TEGRA_SWGROUP_DCB,
 109		.smmu = {
 110			.reg = 0x228,
 111			.bit = 4,
 112		},
 113		.la = {
 114			.reg = 0x2f4,
 115			.shift = 16,
 116			.mask = 0xff,
 117			.def = 0x50,
 118		},
 119	}, {
 120		.id = 0x05,
 121		.name = "display0c",
 122		.swgroup = TEGRA_SWGROUP_DC,
 123		.smmu = {
 124			.reg = 0x228,
 125			.bit = 5,
 126		},
 127		.la = {
 128			.reg = 0x2ec,
 129			.shift = 0,
 130			.mask = 0xff,
 131			.def = 0x50,
 132		},
 133	}, {
 134		.id = 0x06,
 135		.name = "display0cb",
 136		.swgroup = TEGRA_SWGROUP_DCB,
 137		.smmu = {
 138			.reg = 0x228,
 139			.bit = 6,
 140		},
 141		.la = {
 142			.reg = 0x2f8,
 143			.shift = 0,
 144			.mask = 0xff,
 145			.def = 0x50,
 146		},
 147	}, {
 148		.id = 0x0e,
 149		.name = "afir",
 150		.swgroup = TEGRA_SWGROUP_AFI,
 151		.smmu = {
 152			.reg = 0x228,
 153			.bit = 14,
 154		},
 155		.la = {
 156			.reg = 0x2e0,
 157			.shift = 0,
 158			.mask = 0xff,
 159			.def = 0x13,
 160		},
 161	}, {
 162		.id = 0x0f,
 163		.name = "avpcarm7r",
 164		.swgroup = TEGRA_SWGROUP_AVPC,
 165		.smmu = {
 166			.reg = 0x228,
 167			.bit = 15,
 168		},
 169		.la = {
 170			.reg = 0x2e4,
 171			.shift = 0,
 172			.mask = 0xff,
 173			.def = 0x04,
 174		},
 175	}, {
 176		.id = 0x10,
 177		.name = "displayhc",
 178		.swgroup = TEGRA_SWGROUP_DC,
 179		.smmu = {
 180			.reg = 0x228,
 181			.bit = 16,
 182		},
 183		.la = {
 184			.reg = 0x2f0,
 185			.shift = 0,
 186			.mask = 0xff,
 187			.def = 0x50,
 188		},
 189	}, {
 190		.id = 0x11,
 191		.name = "displayhcb",
 192		.swgroup = TEGRA_SWGROUP_DCB,
 193		.smmu = {
 194			.reg = 0x228,
 195			.bit = 17,
 196		},
 197		.la = {
 198			.reg = 0x2fc,
 199			.shift = 0,
 200			.mask = 0xff,
 201			.def = 0x50,
 202		},
 203	}, {
 204		.id = 0x15,
 205		.name = "hdar",
 206		.swgroup = TEGRA_SWGROUP_HDA,
 207		.smmu = {
 208			.reg = 0x228,
 209			.bit = 21,
 210		},
 211		.la = {
 212			.reg = 0x318,
 213			.shift = 0,
 214			.mask = 0xff,
 215			.def = 0x24,
 216		},
 217	}, {
 218		.id = 0x16,
 219		.name = "host1xdmar",
 220		.swgroup = TEGRA_SWGROUP_HC,
 221		.smmu = {
 222			.reg = 0x228,
 223			.bit = 22,
 224		},
 225		.la = {
 226			.reg = 0x310,
 227			.shift = 0,
 228			.mask = 0xff,
 229			.def = 0x1e,
 230		},
 231	}, {
 232		.id = 0x17,
 233		.name = "host1xr",
 234		.swgroup = TEGRA_SWGROUP_HC,
 235		.smmu = {
 236			.reg = 0x228,
 237			.bit = 23,
 238		},
 239		.la = {
 240			.reg = 0x310,
 241			.shift = 16,
 242			.mask = 0xff,
 243			.def = 0x50,
 244		},
 245	}, {
 246		.id = 0x1c,
 247		.name = "msencsrd",
 248		.swgroup = TEGRA_SWGROUP_MSENC,
 249		.smmu = {
 250			.reg = 0x228,
 251			.bit = 28,
 252		},
 253		.la = {
 254			.reg = 0x328,
 255			.shift = 0,
 256			.mask = 0xff,
 257			.def = 0x23,
 258		},
 259	}, {
 260		.id = 0x1d,
 261		.name = "ppcsahbdmar",
 262		.swgroup = TEGRA_SWGROUP_PPCS,
 263		.smmu = {
 264			.reg = 0x228,
 265			.bit = 29,
 266		},
 267		.la = {
 268			.reg = 0x344,
 269			.shift = 0,
 270			.mask = 0xff,
 271			.def = 0x49,
 272		},
 273	}, {
 274		.id = 0x1e,
 275		.name = "ppcsahbslvr",
 276		.swgroup = TEGRA_SWGROUP_PPCS,
 277		.smmu = {
 278			.reg = 0x228,
 279			.bit = 30,
 280		},
 281		.la = {
 282			.reg = 0x344,
 283			.shift = 16,
 284			.mask = 0xff,
 285			.def = 0x1a,
 286		},
 287	}, {
 288		.id = 0x1f,
 289		.name = "satar",
 290		.swgroup = TEGRA_SWGROUP_SATA,
 291		.smmu = {
 292			.reg = 0x228,
 293			.bit = 31,
 294		},
 295		.la = {
 296			.reg = 0x350,
 297			.shift = 0,
 298			.mask = 0xff,
 299			.def = 0x65,
 300		},
 301	}, {
 302		.id = 0x22,
 303		.name = "vdebsevr",
 304		.swgroup = TEGRA_SWGROUP_VDE,
 305		.smmu = {
 306			.reg = 0x22c,
 307			.bit = 2,
 308		},
 309		.la = {
 310			.reg = 0x354,
 311			.shift = 0,
 312			.mask = 0xff,
 313			.def = 0x4f,
 314		},
 315	}, {
 316		.id = 0x23,
 317		.name = "vdember",
 318		.swgroup = TEGRA_SWGROUP_VDE,
 319		.smmu = {
 320			.reg = 0x22c,
 321			.bit = 3,
 322		},
 323		.la = {
 324			.reg = 0x354,
 325			.shift = 16,
 326			.mask = 0xff,
 327			.def = 0x3d,
 328		},
 329	}, {
 330		.id = 0x24,
 331		.name = "vdemcer",
 332		.swgroup = TEGRA_SWGROUP_VDE,
 333		.smmu = {
 334			.reg = 0x22c,
 335			.bit = 4,
 336		},
 337		.la = {
 338			.reg = 0x358,
 339			.shift = 0,
 340			.mask = 0xff,
 341			.def = 0x66,
 342		},
 343	}, {
 344		.id = 0x25,
 345		.name = "vdetper",
 346		.swgroup = TEGRA_SWGROUP_VDE,
 347		.smmu = {
 348			.reg = 0x22c,
 349			.bit = 5,
 350		},
 351		.la = {
 352			.reg = 0x358,
 353			.shift = 16,
 354			.mask = 0xff,
 355			.def = 0xa5,
 356		},
 357	}, {
 358		.id = 0x26,
 359		.name = "mpcorelpr",
 360		.swgroup = TEGRA_SWGROUP_MPCORELP,
 361		.la = {
 362			.reg = 0x324,
 363			.shift = 0,
 364			.mask = 0xff,
 365			.def = 0x04,
 366		},
 367	}, {
 368		.id = 0x27,
 369		.name = "mpcorer",
 370		.swgroup = TEGRA_SWGROUP_MPCORE,
 371		.la = {
 372			.reg = 0x320,
 373			.shift = 0,
 374			.mask = 0xff,
 375			.def = 0x04,
 376		},
 377	}, {
 378		.id = 0x2b,
 379		.name = "msencswr",
 380		.swgroup = TEGRA_SWGROUP_MSENC,
 381		.smmu = {
 382			.reg = 0x22c,
 383			.bit = 11,
 384		},
 385		.la = {
 386			.reg = 0x328,
 387			.shift = 16,
 388			.mask = 0xff,
 389			.def = 0x80,
 390		},
 391	}, {
 392		.id = 0x31,
 393		.name = "afiw",
 394		.swgroup = TEGRA_SWGROUP_AFI,
 395		.smmu = {
 396			.reg = 0x22c,
 397			.bit = 17,
 398		},
 399		.la = {
 400			.reg = 0x2e0,
 401			.shift = 16,
 402			.mask = 0xff,
 403			.def = 0x80,
 404		},
 405	}, {
 406		.id = 0x32,
 407		.name = "avpcarm7w",
 408		.swgroup = TEGRA_SWGROUP_AVPC,
 409		.smmu = {
 410			.reg = 0x22c,
 411			.bit = 18,
 412		},
 413		.la = {
 414			.reg = 0x2e4,
 415			.shift = 16,
 416			.mask = 0xff,
 417			.def = 0x80,
 418		},
 419	}, {
 420		.id = 0x35,
 421		.name = "hdaw",
 422		.swgroup = TEGRA_SWGROUP_HDA,
 423		.smmu = {
 424			.reg = 0x22c,
 425			.bit = 21,
 426		},
 427		.la = {
 428			.reg = 0x318,
 429			.shift = 16,
 430			.mask = 0xff,
 431			.def = 0x80,
 432		},
 433	}, {
 434		.id = 0x36,
 435		.name = "host1xw",
 436		.swgroup = TEGRA_SWGROUP_HC,
 437		.smmu = {
 438			.reg = 0x22c,
 439			.bit = 22,
 440		},
 441		.la = {
 442			.reg = 0x314,
 443			.shift = 0,
 444			.mask = 0xff,
 445			.def = 0x80,
 446		},
 447	}, {
 448		.id = 0x38,
 449		.name = "mpcorelpw",
 450		.swgroup = TEGRA_SWGROUP_MPCORELP,
 451		.la = {
 452			.reg = 0x324,
 453			.shift = 16,
 454			.mask = 0xff,
 455			.def = 0x80,
 456		},
 457	}, {
 458		.id = 0x39,
 459		.name = "mpcorew",
 460		.swgroup = TEGRA_SWGROUP_MPCORE,
 461		.la = {
 462			.reg = 0x320,
 463			.shift = 16,
 464			.mask = 0xff,
 465			.def = 0x80,
 466		},
 467	}, {
 468		.id = 0x3b,
 469		.name = "ppcsahbdmaw",
 470		.swgroup = TEGRA_SWGROUP_PPCS,
 471		.smmu = {
 472			.reg = 0x22c,
 473			.bit = 27,
 474		},
 475		.la = {
 476			.reg = 0x348,
 477			.shift = 0,
 478			.mask = 0xff,
 479			.def = 0x80,
 480		},
 481	}, {
 482		.id = 0x3c,
 483		.name = "ppcsahbslvw",
 484		.swgroup = TEGRA_SWGROUP_PPCS,
 485		.smmu = {
 486			.reg = 0x22c,
 487			.bit = 28,
 488		},
 489		.la = {
 490			.reg = 0x348,
 491			.shift = 16,
 492			.mask = 0xff,
 493			.def = 0x80,
 494		},
 495	}, {
 496		.id = 0x3d,
 497		.name = "sataw",
 498		.swgroup = TEGRA_SWGROUP_SATA,
 499		.smmu = {
 500			.reg = 0x22c,
 501			.bit = 29,
 502		},
 503		.la = {
 504			.reg = 0x350,
 505			.shift = 16,
 506			.mask = 0xff,
 507			.def = 0x65,
 508		},
 509	}, {
 510		.id = 0x3e,
 511		.name = "vdebsevw",
 512		.swgroup = TEGRA_SWGROUP_VDE,
 513		.smmu = {
 514			.reg = 0x22c,
 515			.bit = 30,
 516		},
 517		.la = {
 518			.reg = 0x35c,
 519			.shift = 0,
 520			.mask = 0xff,
 521			.def = 0x80,
 522		},
 523	}, {
 524		.id = 0x3f,
 525		.name = "vdedbgw",
 526		.swgroup = TEGRA_SWGROUP_VDE,
 527		.smmu = {
 528			.reg = 0x22c,
 529			.bit = 31,
 530		},
 531		.la = {
 532			.reg = 0x35c,
 533			.shift = 16,
 534			.mask = 0xff,
 535			.def = 0x80,
 536		},
 537	}, {
 538		.id = 0x40,
 539		.name = "vdembew",
 540		.swgroup = TEGRA_SWGROUP_VDE,
 541		.smmu = {
 542			.reg = 0x230,
 543			.bit = 0,
 544		},
 545		.la = {
 546			.reg = 0x360,
 547			.shift = 0,
 548			.mask = 0xff,
 549			.def = 0x80,
 550		},
 551	}, {
 552		.id = 0x41,
 553		.name = "vdetpmw",
 554		.swgroup = TEGRA_SWGROUP_VDE,
 555		.smmu = {
 556			.reg = 0x230,
 557			.bit = 1,
 558		},
 559		.la = {
 560			.reg = 0x360,
 561			.shift = 16,
 562			.mask = 0xff,
 563			.def = 0x80,
 564		},
 565	}, {
 566		.id = 0x44,
 567		.name = "ispra",
 568		.swgroup = TEGRA_SWGROUP_ISP2,
 569		.smmu = {
 570			.reg = 0x230,
 571			.bit = 4,
 572		},
 573		.la = {
 574			.reg = 0x370,
 575			.shift = 0,
 576			.mask = 0xff,
 577			.def = 0x18,
 578		},
 579	}, {
 580		.id = 0x46,
 581		.name = "ispwa",
 582		.swgroup = TEGRA_SWGROUP_ISP2,
 583		.smmu = {
 584			.reg = 0x230,
 585			.bit = 6,
 586		},
 587		.la = {
 588			.reg = 0x374,
 589			.shift = 0,
 590			.mask = 0xff,
 591			.def = 0x80,
 592		},
 593	}, {
 594		.id = 0x47,
 595		.name = "ispwb",
 596		.swgroup = TEGRA_SWGROUP_ISP2,
 597		.smmu = {
 598			.reg = 0x230,
 599			.bit = 7,
 600		},
 601		.la = {
 602			.reg = 0x374,
 603			.shift = 16,
 604			.mask = 0xff,
 605			.def = 0x80,
 606		},
 607	}, {
 608		.id = 0x4a,
 609		.name = "xusb_hostr",
 610		.swgroup = TEGRA_SWGROUP_XUSB_HOST,
 611		.smmu = {
 612			.reg = 0x230,
 613			.bit = 10,
 614		},
 615		.la = {
 616			.reg = 0x37c,
 617			.shift = 0,
 618			.mask = 0xff,
 619			.def = 0x39,
 620		},
 621	}, {
 622		.id = 0x4b,
 623		.name = "xusb_hostw",
 624		.swgroup = TEGRA_SWGROUP_XUSB_HOST,
 625		.smmu = {
 626			.reg = 0x230,
 627			.bit = 11,
 628		},
 629		.la = {
 630			.reg = 0x37c,
 631			.shift = 16,
 632			.mask = 0xff,
 633			.def = 0x80,
 634		},
 635	}, {
 636		.id = 0x4c,
 637		.name = "xusb_devr",
 638		.swgroup = TEGRA_SWGROUP_XUSB_DEV,
 639		.smmu = {
 640			.reg = 0x230,
 641			.bit = 12,
 642		},
 643		.la = {
 644			.reg = 0x380,
 645			.shift = 0,
 646			.mask = 0xff,
 647			.def = 0x39,
 648		},
 649	}, {
 650		.id = 0x4d,
 651		.name = "xusb_devw",
 652		.swgroup = TEGRA_SWGROUP_XUSB_DEV,
 653		.smmu = {
 654			.reg = 0x230,
 655			.bit = 13,
 656		},
 657		.la = {
 658			.reg = 0x380,
 659			.shift = 16,
 660			.mask = 0xff,
 661			.def = 0x80,
 662		},
 663	}, {
 664		.id = 0x4e,
 665		.name = "isprab",
 666		.swgroup = TEGRA_SWGROUP_ISP2B,
 667		.smmu = {
 668			.reg = 0x230,
 669			.bit = 14,
 670		},
 671		.la = {
 672			.reg = 0x384,
 673			.shift = 0,
 674			.mask = 0xff,
 675			.def = 0x18,
 676		},
 677	}, {
 678		.id = 0x50,
 679		.name = "ispwab",
 680		.swgroup = TEGRA_SWGROUP_ISP2B,
 681		.smmu = {
 682			.reg = 0x230,
 683			.bit = 16,
 684		},
 685		.la = {
 686			.reg = 0x388,
 687			.shift = 0,
 688			.mask = 0xff,
 689			.def = 0x80,
 690		},
 691	}, {
 692		.id = 0x51,
 693		.name = "ispwbb",
 694		.swgroup = TEGRA_SWGROUP_ISP2B,
 695		.smmu = {
 696			.reg = 0x230,
 697			.bit = 17,
 698		},
 699		.la = {
 700			.reg = 0x388,
 701			.shift = 16,
 702			.mask = 0xff,
 703			.def = 0x80,
 704		},
 705	}, {
 706		.id = 0x54,
 707		.name = "tsecsrd",
 708		.swgroup = TEGRA_SWGROUP_TSEC,
 709		.smmu = {
 710			.reg = 0x230,
 711			.bit = 20,
 712		},
 713		.la = {
 714			.reg = 0x390,
 715			.shift = 0,
 716			.mask = 0xff,
 717			.def = 0x9b,
 718		},
 719	}, {
 720		.id = 0x55,
 721		.name = "tsecswr",
 722		.swgroup = TEGRA_SWGROUP_TSEC,
 723		.smmu = {
 724			.reg = 0x230,
 725			.bit = 21,
 726		},
 727		.la = {
 728			.reg = 0x390,
 729			.shift = 16,
 730			.mask = 0xff,
 731			.def = 0x80,
 732		},
 733	}, {
 734		.id = 0x56,
 735		.name = "a9avpscr",
 736		.swgroup = TEGRA_SWGROUP_A9AVP,
 737		.smmu = {
 738			.reg = 0x230,
 739			.bit = 22,
 740		},
 741		.la = {
 742			.reg = 0x3a4,
 743			.shift = 0,
 744			.mask = 0xff,
 745			.def = 0x04,
 746		},
 747	}, {
 748		.id = 0x57,
 749		.name = "a9avpscw",
 750		.swgroup = TEGRA_SWGROUP_A9AVP,
 751		.smmu = {
 752			.reg = 0x230,
 753			.bit = 23,
 754		},
 755		.la = {
 756			.reg = 0x3a4,
 757			.shift = 16,
 758			.mask = 0xff,
 759			.def = 0x80,
 760		},
 761	}, {
 762		.id = 0x58,
 763		.name = "gpusrd",
 764		.swgroup = TEGRA_SWGROUP_GPU,
 765		.smmu = {
 766			/* read-only */
 767			.reg = 0x230,
 768			.bit = 24,
 769		},
 770		.la = {
 771			.reg = 0x3c8,
 772			.shift = 0,
 773			.mask = 0xff,
 774			.def = 0x1a,
 775		},
 776	}, {
 777		.id = 0x59,
 778		.name = "gpuswr",
 779		.swgroup = TEGRA_SWGROUP_GPU,
 780		.smmu = {
 781			/* read-only */
 782			.reg = 0x230,
 783			.bit = 25,
 784		},
 785		.la = {
 786			.reg = 0x3c8,
 787			.shift = 16,
 788			.mask = 0xff,
 789			.def = 0x80,
 790		},
 791	}, {
 792		.id = 0x5a,
 793		.name = "displayt",
 794		.swgroup = TEGRA_SWGROUP_DC,
 795		.smmu = {
 796			.reg = 0x230,
 797			.bit = 26,
 798		},
 799		.la = {
 800			.reg = 0x2f0,
 801			.shift = 16,
 802			.mask = 0xff,
 803			.def = 0x50,
 804		},
 805	}, {
 806		.id = 0x60,
 807		.name = "sdmmcra",
 808		.swgroup = TEGRA_SWGROUP_SDMMC1A,
 809		.smmu = {
 810			.reg = 0x234,
 811			.bit = 0,
 812		},
 813		.la = {
 814			.reg = 0x3b8,
 815			.shift = 0,
 816			.mask = 0xff,
 817			.def = 0x49,
 818		},
 819	}, {
 820		.id = 0x61,
 821		.name = "sdmmcraa",
 822		.swgroup = TEGRA_SWGROUP_SDMMC2A,
 823		.smmu = {
 824			.reg = 0x234,
 825			.bit = 1,
 826		},
 827		.la = {
 828			.reg = 0x3bc,
 829			.shift = 0,
 830			.mask = 0xff,
 831			.def = 0x49,
 832		},
 833	}, {
 834		.id = 0x62,
 835		.name = "sdmmcr",
 836		.swgroup = TEGRA_SWGROUP_SDMMC3A,
 837		.smmu = {
 838			.reg = 0x234,
 839			.bit = 2,
 840		},
 841		.la = {
 842			.reg = 0x3c0,
 843			.shift = 0,
 844			.mask = 0xff,
 845			.def = 0x49,
 846		},
 847	}, {
 848		.id = 0x63,
 849		.swgroup = TEGRA_SWGROUP_SDMMC4A,
 850		.name = "sdmmcrab",
 851		.smmu = {
 852			.reg = 0x234,
 853			.bit = 3,
 854		},
 855		.la = {
 856			.reg = 0x3c4,
 857			.shift = 0,
 858			.mask = 0xff,
 859			.def = 0x49,
 860		},
 861	}, {
 862		.id = 0x64,
 863		.name = "sdmmcwa",
 864		.swgroup = TEGRA_SWGROUP_SDMMC1A,
 865		.smmu = {
 866			.reg = 0x234,
 867			.bit = 4,
 868		},
 869		.la = {
 870			.reg = 0x3b8,
 871			.shift = 16,
 872			.mask = 0xff,
 873			.def = 0x80,
 874		},
 875	}, {
 876		.id = 0x65,
 877		.name = "sdmmcwaa",
 878		.swgroup = TEGRA_SWGROUP_SDMMC2A,
 879		.smmu = {
 880			.reg = 0x234,
 881			.bit = 5,
 882		},
 883		.la = {
 884			.reg = 0x3bc,
 885			.shift = 16,
 886			.mask = 0xff,
 887			.def = 0x80,
 888		},
 889	}, {
 890		.id = 0x66,
 891		.name = "sdmmcw",
 892		.swgroup = TEGRA_SWGROUP_SDMMC3A,
 893		.smmu = {
 894			.reg = 0x234,
 895			.bit = 6,
 896		},
 897		.la = {
 898			.reg = 0x3c0,
 899			.shift = 16,
 900			.mask = 0xff,
 901			.def = 0x80,
 902		},
 903	}, {
 904		.id = 0x67,
 905		.name = "sdmmcwab",
 906		.swgroup = TEGRA_SWGROUP_SDMMC4A,
 907		.smmu = {
 908			.reg = 0x234,
 909			.bit = 7,
 910		},
 911		.la = {
 912			.reg = 0x3c4,
 913			.shift = 16,
 914			.mask = 0xff,
 915			.def = 0x80,
 916		},
 917	}, {
 918		.id = 0x6c,
 919		.name = "vicsrd",
 920		.swgroup = TEGRA_SWGROUP_VIC,
 921		.smmu = {
 922			.reg = 0x234,
 923			.bit = 12,
 924		},
 925		.la = {
 926			.reg = 0x394,
 927			.shift = 0,
 928			.mask = 0xff,
 929			.def = 0x1a,
 930		},
 931	}, {
 932		.id = 0x6d,
 933		.name = "vicswr",
 934		.swgroup = TEGRA_SWGROUP_VIC,
 935		.smmu = {
 936			.reg = 0x234,
 937			.bit = 13,
 938		},
 939		.la = {
 940			.reg = 0x394,
 941			.shift = 16,
 942			.mask = 0xff,
 943			.def = 0x80,
 944		},
 945	}, {
 946		.id = 0x72,
 947		.name = "viw",
 948		.swgroup = TEGRA_SWGROUP_VI,
 949		.smmu = {
 950			.reg = 0x234,
 951			.bit = 18,
 952		},
 953		.la = {
 954			.reg = 0x398,
 955			.shift = 0,
 956			.mask = 0xff,
 957			.def = 0x80,
 958		},
 959	}, {
 960		.id = 0x73,
 961		.name = "displayd",
 962		.swgroup = TEGRA_SWGROUP_DC,
 963		.smmu = {
 964			.reg = 0x234,
 965			.bit = 19,
 966		},
 967		.la = {
 968			.reg = 0x3c8,
 969			.shift = 0,
 970			.mask = 0xff,
 971			.def = 0x50,
 972		},
 973	},
 974};
 975
 976static const struct tegra_smmu_swgroup tegra124_swgroups[] = {
 977	{ .name = "dc",        .swgroup = TEGRA_SWGROUP_DC,        .reg = 0x240 },
 978	{ .name = "dcb",       .swgroup = TEGRA_SWGROUP_DCB,       .reg = 0x244 },
 979	{ .name = "afi",       .swgroup = TEGRA_SWGROUP_AFI,       .reg = 0x238 },
 980	{ .name = "avpc",      .swgroup = TEGRA_SWGROUP_AVPC,      .reg = 0x23c },
 981	{ .name = "hda",       .swgroup = TEGRA_SWGROUP_HDA,       .reg = 0x254 },
 982	{ .name = "hc",        .swgroup = TEGRA_SWGROUP_HC,        .reg = 0x250 },
 983	{ .name = "msenc",     .swgroup = TEGRA_SWGROUP_MSENC,     .reg = 0x264 },
 984	{ .name = "ppcs",      .swgroup = TEGRA_SWGROUP_PPCS,      .reg = 0x270 },
 985	{ .name = "sata",      .swgroup = TEGRA_SWGROUP_SATA,      .reg = 0x274 },
 986	{ .name = "vde",       .swgroup = TEGRA_SWGROUP_VDE,       .reg = 0x27c },
 987	{ .name = "isp2",      .swgroup = TEGRA_SWGROUP_ISP2,      .reg = 0x258 },
 988	{ .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
 989	{ .name = "xusb_dev",  .swgroup = TEGRA_SWGROUP_XUSB_DEV,  .reg = 0x28c },
 990	{ .name = "isp2b",     .swgroup = TEGRA_SWGROUP_ISP2B,     .reg = 0xaa4 },
 991	{ .name = "tsec",      .swgroup = TEGRA_SWGROUP_TSEC,      .reg = 0x294 },
 992	{ .name = "a9avp",     .swgroup = TEGRA_SWGROUP_A9AVP,     .reg = 0x290 },
 993	{ .name = "gpu",       .swgroup = TEGRA_SWGROUP_GPU,       .reg = 0xaac },
 994	{ .name = "sdmmc1a",   .swgroup = TEGRA_SWGROUP_SDMMC1A,   .reg = 0xa94 },
 995	{ .name = "sdmmc2a",   .swgroup = TEGRA_SWGROUP_SDMMC2A,   .reg = 0xa98 },
 996	{ .name = "sdmmc3a",   .swgroup = TEGRA_SWGROUP_SDMMC3A,   .reg = 0xa9c },
 997	{ .name = "sdmmc4a",   .swgroup = TEGRA_SWGROUP_SDMMC4A,   .reg = 0xaa0 },
 998	{ .name = "vic",       .swgroup = TEGRA_SWGROUP_VIC,       .reg = 0x284 },
 999	{ .name = "vi",        .swgroup = TEGRA_SWGROUP_VI,        .reg = 0x280 },
1000};
1001
 
 
 
 
 
 
 
 
 
 
 
 
 
1002#ifdef CONFIG_ARCH_TEGRA_124_SOC
1003static const struct tegra_smmu_soc tegra124_smmu_soc = {
1004	.clients = tegra124_mc_clients,
1005	.num_clients = ARRAY_SIZE(tegra124_mc_clients),
1006	.swgroups = tegra124_swgroups,
1007	.num_swgroups = ARRAY_SIZE(tegra124_swgroups),
 
 
1008	.supports_round_robin_arbitration = true,
1009	.supports_request_limit = true,
1010	.num_tlb_lines = 32,
1011	.num_asids = 128,
1012};
1013
1014const struct tegra_mc_soc tegra124_mc_soc = {
1015	.clients = tegra124_mc_clients,
1016	.num_clients = ARRAY_SIZE(tegra124_mc_clients),
1017	.num_address_bits = 34,
1018	.atom_size = 32,
1019	.client_id_mask = 0x7f,
1020	.smmu = &tegra124_smmu_soc,
1021	.emem_regs = tegra124_mc_emem_regs,
1022	.num_emem_regs = ARRAY_SIZE(tegra124_mc_emem_regs),
1023};
1024#endif /* CONFIG_ARCH_TEGRA_124_SOC */
1025
1026#ifdef CONFIG_ARCH_TEGRA_132_SOC
1027static const struct tegra_smmu_soc tegra132_smmu_soc = {
1028	.clients = tegra124_mc_clients,
1029	.num_clients = ARRAY_SIZE(tegra124_mc_clients),
1030	.swgroups = tegra124_swgroups,
1031	.num_swgroups = ARRAY_SIZE(tegra124_swgroups),
 
 
1032	.supports_round_robin_arbitration = true,
1033	.supports_request_limit = true,
1034	.num_tlb_lines = 32,
1035	.num_asids = 128,
1036};
1037
1038const struct tegra_mc_soc tegra132_mc_soc = {
1039	.clients = tegra124_mc_clients,
1040	.num_clients = ARRAY_SIZE(tegra124_mc_clients),
1041	.num_address_bits = 34,
1042	.atom_size = 32,
1043	.client_id_mask = 0x7f,
1044	.smmu = &tegra132_smmu_soc,
1045};
1046#endif /* CONFIG_ARCH_TEGRA_132_SOC */