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1/*
2 * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <linux/of.h>
10#include <linux/mm.h>
11
12#include <dt-bindings/memory/tegra124-mc.h>
13
14#include "mc.h"
15
16#define MC_EMEM_ARB_CFG 0x90
17#define MC_EMEM_ARB_OUTSTANDING_REQ 0x94
18#define MC_EMEM_ARB_TIMING_RCD 0x98
19#define MC_EMEM_ARB_TIMING_RP 0x9c
20#define MC_EMEM_ARB_TIMING_RC 0xa0
21#define MC_EMEM_ARB_TIMING_RAS 0xa4
22#define MC_EMEM_ARB_TIMING_FAW 0xa8
23#define MC_EMEM_ARB_TIMING_RRD 0xac
24#define MC_EMEM_ARB_TIMING_RAP2PRE 0xb0
25#define MC_EMEM_ARB_TIMING_WAP2PRE 0xb4
26#define MC_EMEM_ARB_TIMING_R2R 0xb8
27#define MC_EMEM_ARB_TIMING_W2W 0xbc
28#define MC_EMEM_ARB_TIMING_R2W 0xc0
29#define MC_EMEM_ARB_TIMING_W2R 0xc4
30#define MC_EMEM_ARB_DA_TURNS 0xd0
31#define MC_EMEM_ARB_DA_COVERS 0xd4
32#define MC_EMEM_ARB_MISC0 0xd8
33#define MC_EMEM_ARB_MISC1 0xdc
34#define MC_EMEM_ARB_RING1_THROTTLE 0xe0
35
36static const unsigned long tegra124_mc_emem_regs[] = {
37 MC_EMEM_ARB_CFG,
38 MC_EMEM_ARB_OUTSTANDING_REQ,
39 MC_EMEM_ARB_TIMING_RCD,
40 MC_EMEM_ARB_TIMING_RP,
41 MC_EMEM_ARB_TIMING_RC,
42 MC_EMEM_ARB_TIMING_RAS,
43 MC_EMEM_ARB_TIMING_FAW,
44 MC_EMEM_ARB_TIMING_RRD,
45 MC_EMEM_ARB_TIMING_RAP2PRE,
46 MC_EMEM_ARB_TIMING_WAP2PRE,
47 MC_EMEM_ARB_TIMING_R2R,
48 MC_EMEM_ARB_TIMING_W2W,
49 MC_EMEM_ARB_TIMING_R2W,
50 MC_EMEM_ARB_TIMING_W2R,
51 MC_EMEM_ARB_DA_TURNS,
52 MC_EMEM_ARB_DA_COVERS,
53 MC_EMEM_ARB_MISC0,
54 MC_EMEM_ARB_MISC1,
55 MC_EMEM_ARB_RING1_THROTTLE
56};
57
58static const struct tegra_mc_client tegra124_mc_clients[] = {
59 {
60 .id = 0x00,
61 .name = "ptcr",
62 .swgroup = TEGRA_SWGROUP_PTC,
63 }, {
64 .id = 0x01,
65 .name = "display0a",
66 .swgroup = TEGRA_SWGROUP_DC,
67 .smmu = {
68 .reg = 0x228,
69 .bit = 1,
70 },
71 .la = {
72 .reg = 0x2e8,
73 .shift = 0,
74 .mask = 0xff,
75 .def = 0xc2,
76 },
77 }, {
78 .id = 0x02,
79 .name = "display0ab",
80 .swgroup = TEGRA_SWGROUP_DCB,
81 .smmu = {
82 .reg = 0x228,
83 .bit = 2,
84 },
85 .la = {
86 .reg = 0x2f4,
87 .shift = 0,
88 .mask = 0xff,
89 .def = 0xc6,
90 },
91 }, {
92 .id = 0x03,
93 .name = "display0b",
94 .swgroup = TEGRA_SWGROUP_DC,
95 .smmu = {
96 .reg = 0x228,
97 .bit = 3,
98 },
99 .la = {
100 .reg = 0x2e8,
101 .shift = 16,
102 .mask = 0xff,
103 .def = 0x50,
104 },
105 }, {
106 .id = 0x04,
107 .name = "display0bb",
108 .swgroup = TEGRA_SWGROUP_DCB,
109 .smmu = {
110 .reg = 0x228,
111 .bit = 4,
112 },
113 .la = {
114 .reg = 0x2f4,
115 .shift = 16,
116 .mask = 0xff,
117 .def = 0x50,
118 },
119 }, {
120 .id = 0x05,
121 .name = "display0c",
122 .swgroup = TEGRA_SWGROUP_DC,
123 .smmu = {
124 .reg = 0x228,
125 .bit = 5,
126 },
127 .la = {
128 .reg = 0x2ec,
129 .shift = 0,
130 .mask = 0xff,
131 .def = 0x50,
132 },
133 }, {
134 .id = 0x06,
135 .name = "display0cb",
136 .swgroup = TEGRA_SWGROUP_DCB,
137 .smmu = {
138 .reg = 0x228,
139 .bit = 6,
140 },
141 .la = {
142 .reg = 0x2f8,
143 .shift = 0,
144 .mask = 0xff,
145 .def = 0x50,
146 },
147 }, {
148 .id = 0x0e,
149 .name = "afir",
150 .swgroup = TEGRA_SWGROUP_AFI,
151 .smmu = {
152 .reg = 0x228,
153 .bit = 14,
154 },
155 .la = {
156 .reg = 0x2e0,
157 .shift = 0,
158 .mask = 0xff,
159 .def = 0x13,
160 },
161 }, {
162 .id = 0x0f,
163 .name = "avpcarm7r",
164 .swgroup = TEGRA_SWGROUP_AVPC,
165 .smmu = {
166 .reg = 0x228,
167 .bit = 15,
168 },
169 .la = {
170 .reg = 0x2e4,
171 .shift = 0,
172 .mask = 0xff,
173 .def = 0x04,
174 },
175 }, {
176 .id = 0x10,
177 .name = "displayhc",
178 .swgroup = TEGRA_SWGROUP_DC,
179 .smmu = {
180 .reg = 0x228,
181 .bit = 16,
182 },
183 .la = {
184 .reg = 0x2f0,
185 .shift = 0,
186 .mask = 0xff,
187 .def = 0x50,
188 },
189 }, {
190 .id = 0x11,
191 .name = "displayhcb",
192 .swgroup = TEGRA_SWGROUP_DCB,
193 .smmu = {
194 .reg = 0x228,
195 .bit = 17,
196 },
197 .la = {
198 .reg = 0x2fc,
199 .shift = 0,
200 .mask = 0xff,
201 .def = 0x50,
202 },
203 }, {
204 .id = 0x15,
205 .name = "hdar",
206 .swgroup = TEGRA_SWGROUP_HDA,
207 .smmu = {
208 .reg = 0x228,
209 .bit = 21,
210 },
211 .la = {
212 .reg = 0x318,
213 .shift = 0,
214 .mask = 0xff,
215 .def = 0x24,
216 },
217 }, {
218 .id = 0x16,
219 .name = "host1xdmar",
220 .swgroup = TEGRA_SWGROUP_HC,
221 .smmu = {
222 .reg = 0x228,
223 .bit = 22,
224 },
225 .la = {
226 .reg = 0x310,
227 .shift = 0,
228 .mask = 0xff,
229 .def = 0x1e,
230 },
231 }, {
232 .id = 0x17,
233 .name = "host1xr",
234 .swgroup = TEGRA_SWGROUP_HC,
235 .smmu = {
236 .reg = 0x228,
237 .bit = 23,
238 },
239 .la = {
240 .reg = 0x310,
241 .shift = 16,
242 .mask = 0xff,
243 .def = 0x50,
244 },
245 }, {
246 .id = 0x1c,
247 .name = "msencsrd",
248 .swgroup = TEGRA_SWGROUP_MSENC,
249 .smmu = {
250 .reg = 0x228,
251 .bit = 28,
252 },
253 .la = {
254 .reg = 0x328,
255 .shift = 0,
256 .mask = 0xff,
257 .def = 0x23,
258 },
259 }, {
260 .id = 0x1d,
261 .name = "ppcsahbdmar",
262 .swgroup = TEGRA_SWGROUP_PPCS,
263 .smmu = {
264 .reg = 0x228,
265 .bit = 29,
266 },
267 .la = {
268 .reg = 0x344,
269 .shift = 0,
270 .mask = 0xff,
271 .def = 0x49,
272 },
273 }, {
274 .id = 0x1e,
275 .name = "ppcsahbslvr",
276 .swgroup = TEGRA_SWGROUP_PPCS,
277 .smmu = {
278 .reg = 0x228,
279 .bit = 30,
280 },
281 .la = {
282 .reg = 0x344,
283 .shift = 16,
284 .mask = 0xff,
285 .def = 0x1a,
286 },
287 }, {
288 .id = 0x1f,
289 .name = "satar",
290 .swgroup = TEGRA_SWGROUP_SATA,
291 .smmu = {
292 .reg = 0x228,
293 .bit = 31,
294 },
295 .la = {
296 .reg = 0x350,
297 .shift = 0,
298 .mask = 0xff,
299 .def = 0x65,
300 },
301 }, {
302 .id = 0x22,
303 .name = "vdebsevr",
304 .swgroup = TEGRA_SWGROUP_VDE,
305 .smmu = {
306 .reg = 0x22c,
307 .bit = 2,
308 },
309 .la = {
310 .reg = 0x354,
311 .shift = 0,
312 .mask = 0xff,
313 .def = 0x4f,
314 },
315 }, {
316 .id = 0x23,
317 .name = "vdember",
318 .swgroup = TEGRA_SWGROUP_VDE,
319 .smmu = {
320 .reg = 0x22c,
321 .bit = 3,
322 },
323 .la = {
324 .reg = 0x354,
325 .shift = 16,
326 .mask = 0xff,
327 .def = 0x3d,
328 },
329 }, {
330 .id = 0x24,
331 .name = "vdemcer",
332 .swgroup = TEGRA_SWGROUP_VDE,
333 .smmu = {
334 .reg = 0x22c,
335 .bit = 4,
336 },
337 .la = {
338 .reg = 0x358,
339 .shift = 0,
340 .mask = 0xff,
341 .def = 0x66,
342 },
343 }, {
344 .id = 0x25,
345 .name = "vdetper",
346 .swgroup = TEGRA_SWGROUP_VDE,
347 .smmu = {
348 .reg = 0x22c,
349 .bit = 5,
350 },
351 .la = {
352 .reg = 0x358,
353 .shift = 16,
354 .mask = 0xff,
355 .def = 0xa5,
356 },
357 }, {
358 .id = 0x26,
359 .name = "mpcorelpr",
360 .swgroup = TEGRA_SWGROUP_MPCORELP,
361 .la = {
362 .reg = 0x324,
363 .shift = 0,
364 .mask = 0xff,
365 .def = 0x04,
366 },
367 }, {
368 .id = 0x27,
369 .name = "mpcorer",
370 .swgroup = TEGRA_SWGROUP_MPCORE,
371 .la = {
372 .reg = 0x320,
373 .shift = 0,
374 .mask = 0xff,
375 .def = 0x04,
376 },
377 }, {
378 .id = 0x2b,
379 .name = "msencswr",
380 .swgroup = TEGRA_SWGROUP_MSENC,
381 .smmu = {
382 .reg = 0x22c,
383 .bit = 11,
384 },
385 .la = {
386 .reg = 0x328,
387 .shift = 16,
388 .mask = 0xff,
389 .def = 0x80,
390 },
391 }, {
392 .id = 0x31,
393 .name = "afiw",
394 .swgroup = TEGRA_SWGROUP_AFI,
395 .smmu = {
396 .reg = 0x22c,
397 .bit = 17,
398 },
399 .la = {
400 .reg = 0x2e0,
401 .shift = 16,
402 .mask = 0xff,
403 .def = 0x80,
404 },
405 }, {
406 .id = 0x32,
407 .name = "avpcarm7w",
408 .swgroup = TEGRA_SWGROUP_AVPC,
409 .smmu = {
410 .reg = 0x22c,
411 .bit = 18,
412 },
413 .la = {
414 .reg = 0x2e4,
415 .shift = 16,
416 .mask = 0xff,
417 .def = 0x80,
418 },
419 }, {
420 .id = 0x35,
421 .name = "hdaw",
422 .swgroup = TEGRA_SWGROUP_HDA,
423 .smmu = {
424 .reg = 0x22c,
425 .bit = 21,
426 },
427 .la = {
428 .reg = 0x318,
429 .shift = 16,
430 .mask = 0xff,
431 .def = 0x80,
432 },
433 }, {
434 .id = 0x36,
435 .name = "host1xw",
436 .swgroup = TEGRA_SWGROUP_HC,
437 .smmu = {
438 .reg = 0x22c,
439 .bit = 22,
440 },
441 .la = {
442 .reg = 0x314,
443 .shift = 0,
444 .mask = 0xff,
445 .def = 0x80,
446 },
447 }, {
448 .id = 0x38,
449 .name = "mpcorelpw",
450 .swgroup = TEGRA_SWGROUP_MPCORELP,
451 .la = {
452 .reg = 0x324,
453 .shift = 16,
454 .mask = 0xff,
455 .def = 0x80,
456 },
457 }, {
458 .id = 0x39,
459 .name = "mpcorew",
460 .swgroup = TEGRA_SWGROUP_MPCORE,
461 .la = {
462 .reg = 0x320,
463 .shift = 16,
464 .mask = 0xff,
465 .def = 0x80,
466 },
467 }, {
468 .id = 0x3b,
469 .name = "ppcsahbdmaw",
470 .swgroup = TEGRA_SWGROUP_PPCS,
471 .smmu = {
472 .reg = 0x22c,
473 .bit = 27,
474 },
475 .la = {
476 .reg = 0x348,
477 .shift = 0,
478 .mask = 0xff,
479 .def = 0x80,
480 },
481 }, {
482 .id = 0x3c,
483 .name = "ppcsahbslvw",
484 .swgroup = TEGRA_SWGROUP_PPCS,
485 .smmu = {
486 .reg = 0x22c,
487 .bit = 28,
488 },
489 .la = {
490 .reg = 0x348,
491 .shift = 16,
492 .mask = 0xff,
493 .def = 0x80,
494 },
495 }, {
496 .id = 0x3d,
497 .name = "sataw",
498 .swgroup = TEGRA_SWGROUP_SATA,
499 .smmu = {
500 .reg = 0x22c,
501 .bit = 29,
502 },
503 .la = {
504 .reg = 0x350,
505 .shift = 16,
506 .mask = 0xff,
507 .def = 0x65,
508 },
509 }, {
510 .id = 0x3e,
511 .name = "vdebsevw",
512 .swgroup = TEGRA_SWGROUP_VDE,
513 .smmu = {
514 .reg = 0x22c,
515 .bit = 30,
516 },
517 .la = {
518 .reg = 0x35c,
519 .shift = 0,
520 .mask = 0xff,
521 .def = 0x80,
522 },
523 }, {
524 .id = 0x3f,
525 .name = "vdedbgw",
526 .swgroup = TEGRA_SWGROUP_VDE,
527 .smmu = {
528 .reg = 0x22c,
529 .bit = 31,
530 },
531 .la = {
532 .reg = 0x35c,
533 .shift = 16,
534 .mask = 0xff,
535 .def = 0x80,
536 },
537 }, {
538 .id = 0x40,
539 .name = "vdembew",
540 .swgroup = TEGRA_SWGROUP_VDE,
541 .smmu = {
542 .reg = 0x230,
543 .bit = 0,
544 },
545 .la = {
546 .reg = 0x360,
547 .shift = 0,
548 .mask = 0xff,
549 .def = 0x80,
550 },
551 }, {
552 .id = 0x41,
553 .name = "vdetpmw",
554 .swgroup = TEGRA_SWGROUP_VDE,
555 .smmu = {
556 .reg = 0x230,
557 .bit = 1,
558 },
559 .la = {
560 .reg = 0x360,
561 .shift = 16,
562 .mask = 0xff,
563 .def = 0x80,
564 },
565 }, {
566 .id = 0x44,
567 .name = "ispra",
568 .swgroup = TEGRA_SWGROUP_ISP2,
569 .smmu = {
570 .reg = 0x230,
571 .bit = 4,
572 },
573 .la = {
574 .reg = 0x370,
575 .shift = 0,
576 .mask = 0xff,
577 .def = 0x18,
578 },
579 }, {
580 .id = 0x46,
581 .name = "ispwa",
582 .swgroup = TEGRA_SWGROUP_ISP2,
583 .smmu = {
584 .reg = 0x230,
585 .bit = 6,
586 },
587 .la = {
588 .reg = 0x374,
589 .shift = 0,
590 .mask = 0xff,
591 .def = 0x80,
592 },
593 }, {
594 .id = 0x47,
595 .name = "ispwb",
596 .swgroup = TEGRA_SWGROUP_ISP2,
597 .smmu = {
598 .reg = 0x230,
599 .bit = 7,
600 },
601 .la = {
602 .reg = 0x374,
603 .shift = 16,
604 .mask = 0xff,
605 .def = 0x80,
606 },
607 }, {
608 .id = 0x4a,
609 .name = "xusb_hostr",
610 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
611 .smmu = {
612 .reg = 0x230,
613 .bit = 10,
614 },
615 .la = {
616 .reg = 0x37c,
617 .shift = 0,
618 .mask = 0xff,
619 .def = 0x39,
620 },
621 }, {
622 .id = 0x4b,
623 .name = "xusb_hostw",
624 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
625 .smmu = {
626 .reg = 0x230,
627 .bit = 11,
628 },
629 .la = {
630 .reg = 0x37c,
631 .shift = 16,
632 .mask = 0xff,
633 .def = 0x80,
634 },
635 }, {
636 .id = 0x4c,
637 .name = "xusb_devr",
638 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
639 .smmu = {
640 .reg = 0x230,
641 .bit = 12,
642 },
643 .la = {
644 .reg = 0x380,
645 .shift = 0,
646 .mask = 0xff,
647 .def = 0x39,
648 },
649 }, {
650 .id = 0x4d,
651 .name = "xusb_devw",
652 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
653 .smmu = {
654 .reg = 0x230,
655 .bit = 13,
656 },
657 .la = {
658 .reg = 0x380,
659 .shift = 16,
660 .mask = 0xff,
661 .def = 0x80,
662 },
663 }, {
664 .id = 0x4e,
665 .name = "isprab",
666 .swgroup = TEGRA_SWGROUP_ISP2B,
667 .smmu = {
668 .reg = 0x230,
669 .bit = 14,
670 },
671 .la = {
672 .reg = 0x384,
673 .shift = 0,
674 .mask = 0xff,
675 .def = 0x18,
676 },
677 }, {
678 .id = 0x50,
679 .name = "ispwab",
680 .swgroup = TEGRA_SWGROUP_ISP2B,
681 .smmu = {
682 .reg = 0x230,
683 .bit = 16,
684 },
685 .la = {
686 .reg = 0x388,
687 .shift = 0,
688 .mask = 0xff,
689 .def = 0x80,
690 },
691 }, {
692 .id = 0x51,
693 .name = "ispwbb",
694 .swgroup = TEGRA_SWGROUP_ISP2B,
695 .smmu = {
696 .reg = 0x230,
697 .bit = 17,
698 },
699 .la = {
700 .reg = 0x388,
701 .shift = 16,
702 .mask = 0xff,
703 .def = 0x80,
704 },
705 }, {
706 .id = 0x54,
707 .name = "tsecsrd",
708 .swgroup = TEGRA_SWGROUP_TSEC,
709 .smmu = {
710 .reg = 0x230,
711 .bit = 20,
712 },
713 .la = {
714 .reg = 0x390,
715 .shift = 0,
716 .mask = 0xff,
717 .def = 0x9b,
718 },
719 }, {
720 .id = 0x55,
721 .name = "tsecswr",
722 .swgroup = TEGRA_SWGROUP_TSEC,
723 .smmu = {
724 .reg = 0x230,
725 .bit = 21,
726 },
727 .la = {
728 .reg = 0x390,
729 .shift = 16,
730 .mask = 0xff,
731 .def = 0x80,
732 },
733 }, {
734 .id = 0x56,
735 .name = "a9avpscr",
736 .swgroup = TEGRA_SWGROUP_A9AVP,
737 .smmu = {
738 .reg = 0x230,
739 .bit = 22,
740 },
741 .la = {
742 .reg = 0x3a4,
743 .shift = 0,
744 .mask = 0xff,
745 .def = 0x04,
746 },
747 }, {
748 .id = 0x57,
749 .name = "a9avpscw",
750 .swgroup = TEGRA_SWGROUP_A9AVP,
751 .smmu = {
752 .reg = 0x230,
753 .bit = 23,
754 },
755 .la = {
756 .reg = 0x3a4,
757 .shift = 16,
758 .mask = 0xff,
759 .def = 0x80,
760 },
761 }, {
762 .id = 0x58,
763 .name = "gpusrd",
764 .swgroup = TEGRA_SWGROUP_GPU,
765 .smmu = {
766 /* read-only */
767 .reg = 0x230,
768 .bit = 24,
769 },
770 .la = {
771 .reg = 0x3c8,
772 .shift = 0,
773 .mask = 0xff,
774 .def = 0x1a,
775 },
776 }, {
777 .id = 0x59,
778 .name = "gpuswr",
779 .swgroup = TEGRA_SWGROUP_GPU,
780 .smmu = {
781 /* read-only */
782 .reg = 0x230,
783 .bit = 25,
784 },
785 .la = {
786 .reg = 0x3c8,
787 .shift = 16,
788 .mask = 0xff,
789 .def = 0x80,
790 },
791 }, {
792 .id = 0x5a,
793 .name = "displayt",
794 .swgroup = TEGRA_SWGROUP_DC,
795 .smmu = {
796 .reg = 0x230,
797 .bit = 26,
798 },
799 .la = {
800 .reg = 0x2f0,
801 .shift = 16,
802 .mask = 0xff,
803 .def = 0x50,
804 },
805 }, {
806 .id = 0x60,
807 .name = "sdmmcra",
808 .swgroup = TEGRA_SWGROUP_SDMMC1A,
809 .smmu = {
810 .reg = 0x234,
811 .bit = 0,
812 },
813 .la = {
814 .reg = 0x3b8,
815 .shift = 0,
816 .mask = 0xff,
817 .def = 0x49,
818 },
819 }, {
820 .id = 0x61,
821 .name = "sdmmcraa",
822 .swgroup = TEGRA_SWGROUP_SDMMC2A,
823 .smmu = {
824 .reg = 0x234,
825 .bit = 1,
826 },
827 .la = {
828 .reg = 0x3bc,
829 .shift = 0,
830 .mask = 0xff,
831 .def = 0x49,
832 },
833 }, {
834 .id = 0x62,
835 .name = "sdmmcr",
836 .swgroup = TEGRA_SWGROUP_SDMMC3A,
837 .smmu = {
838 .reg = 0x234,
839 .bit = 2,
840 },
841 .la = {
842 .reg = 0x3c0,
843 .shift = 0,
844 .mask = 0xff,
845 .def = 0x49,
846 },
847 }, {
848 .id = 0x63,
849 .swgroup = TEGRA_SWGROUP_SDMMC4A,
850 .name = "sdmmcrab",
851 .smmu = {
852 .reg = 0x234,
853 .bit = 3,
854 },
855 .la = {
856 .reg = 0x3c4,
857 .shift = 0,
858 .mask = 0xff,
859 .def = 0x49,
860 },
861 }, {
862 .id = 0x64,
863 .name = "sdmmcwa",
864 .swgroup = TEGRA_SWGROUP_SDMMC1A,
865 .smmu = {
866 .reg = 0x234,
867 .bit = 4,
868 },
869 .la = {
870 .reg = 0x3b8,
871 .shift = 16,
872 .mask = 0xff,
873 .def = 0x80,
874 },
875 }, {
876 .id = 0x65,
877 .name = "sdmmcwaa",
878 .swgroup = TEGRA_SWGROUP_SDMMC2A,
879 .smmu = {
880 .reg = 0x234,
881 .bit = 5,
882 },
883 .la = {
884 .reg = 0x3bc,
885 .shift = 16,
886 .mask = 0xff,
887 .def = 0x80,
888 },
889 }, {
890 .id = 0x66,
891 .name = "sdmmcw",
892 .swgroup = TEGRA_SWGROUP_SDMMC3A,
893 .smmu = {
894 .reg = 0x234,
895 .bit = 6,
896 },
897 .la = {
898 .reg = 0x3c0,
899 .shift = 16,
900 .mask = 0xff,
901 .def = 0x80,
902 },
903 }, {
904 .id = 0x67,
905 .name = "sdmmcwab",
906 .swgroup = TEGRA_SWGROUP_SDMMC4A,
907 .smmu = {
908 .reg = 0x234,
909 .bit = 7,
910 },
911 .la = {
912 .reg = 0x3c4,
913 .shift = 16,
914 .mask = 0xff,
915 .def = 0x80,
916 },
917 }, {
918 .id = 0x6c,
919 .name = "vicsrd",
920 .swgroup = TEGRA_SWGROUP_VIC,
921 .smmu = {
922 .reg = 0x234,
923 .bit = 12,
924 },
925 .la = {
926 .reg = 0x394,
927 .shift = 0,
928 .mask = 0xff,
929 .def = 0x1a,
930 },
931 }, {
932 .id = 0x6d,
933 .name = "vicswr",
934 .swgroup = TEGRA_SWGROUP_VIC,
935 .smmu = {
936 .reg = 0x234,
937 .bit = 13,
938 },
939 .la = {
940 .reg = 0x394,
941 .shift = 16,
942 .mask = 0xff,
943 .def = 0x80,
944 },
945 }, {
946 .id = 0x72,
947 .name = "viw",
948 .swgroup = TEGRA_SWGROUP_VI,
949 .smmu = {
950 .reg = 0x234,
951 .bit = 18,
952 },
953 .la = {
954 .reg = 0x398,
955 .shift = 0,
956 .mask = 0xff,
957 .def = 0x80,
958 },
959 }, {
960 .id = 0x73,
961 .name = "displayd",
962 .swgroup = TEGRA_SWGROUP_DC,
963 .smmu = {
964 .reg = 0x234,
965 .bit = 19,
966 },
967 .la = {
968 .reg = 0x3c8,
969 .shift = 0,
970 .mask = 0xff,
971 .def = 0x50,
972 },
973 },
974};
975
976static const struct tegra_smmu_swgroup tegra124_swgroups[] = {
977 { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
978 { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
979 { .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
980 { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
981 { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
982 { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
983 { .name = "msenc", .swgroup = TEGRA_SWGROUP_MSENC, .reg = 0x264 },
984 { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
985 { .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 },
986 { .name = "vde", .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c },
987 { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
988 { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
989 { .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
990 { .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 },
991 { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
992 { .name = "a9avp", .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 },
993 { .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac },
994 { .name = "sdmmc1a", .swgroup = TEGRA_SWGROUP_SDMMC1A, .reg = 0xa94 },
995 { .name = "sdmmc2a", .swgroup = TEGRA_SWGROUP_SDMMC2A, .reg = 0xa98 },
996 { .name = "sdmmc3a", .swgroup = TEGRA_SWGROUP_SDMMC3A, .reg = 0xa9c },
997 { .name = "sdmmc4a", .swgroup = TEGRA_SWGROUP_SDMMC4A, .reg = 0xaa0 },
998 { .name = "vic", .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 },
999 { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
1000};
1001
1002#ifdef CONFIG_ARCH_TEGRA_124_SOC
1003static const struct tegra_smmu_soc tegra124_smmu_soc = {
1004 .clients = tegra124_mc_clients,
1005 .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1006 .swgroups = tegra124_swgroups,
1007 .num_swgroups = ARRAY_SIZE(tegra124_swgroups),
1008 .supports_round_robin_arbitration = true,
1009 .supports_request_limit = true,
1010 .num_tlb_lines = 32,
1011 .num_asids = 128,
1012};
1013
1014const struct tegra_mc_soc tegra124_mc_soc = {
1015 .clients = tegra124_mc_clients,
1016 .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1017 .num_address_bits = 34,
1018 .atom_size = 32,
1019 .client_id_mask = 0x7f,
1020 .smmu = &tegra124_smmu_soc,
1021 .emem_regs = tegra124_mc_emem_regs,
1022 .num_emem_regs = ARRAY_SIZE(tegra124_mc_emem_regs),
1023};
1024#endif /* CONFIG_ARCH_TEGRA_124_SOC */
1025
1026#ifdef CONFIG_ARCH_TEGRA_132_SOC
1027static const struct tegra_smmu_soc tegra132_smmu_soc = {
1028 .clients = tegra124_mc_clients,
1029 .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1030 .swgroups = tegra124_swgroups,
1031 .num_swgroups = ARRAY_SIZE(tegra124_swgroups),
1032 .supports_round_robin_arbitration = true,
1033 .supports_request_limit = true,
1034 .num_tlb_lines = 32,
1035 .num_asids = 128,
1036};
1037
1038const struct tegra_mc_soc tegra132_mc_soc = {
1039 .clients = tegra124_mc_clients,
1040 .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1041 .num_address_bits = 34,
1042 .atom_size = 32,
1043 .client_id_mask = 0x7f,
1044 .smmu = &tegra132_smmu_soc,
1045};
1046#endif /* CONFIG_ARCH_TEGRA_132_SOC */
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
4 */
5
6#include <linux/of.h>
7#include <linux/mm.h>
8
9#include <dt-bindings/memory/tegra124-mc.h>
10
11#include "mc.h"
12
13static const struct tegra_mc_client tegra124_mc_clients[] = {
14 {
15 .id = 0x00,
16 .name = "ptcr",
17 .swgroup = TEGRA_SWGROUP_PTC,
18 }, {
19 .id = 0x01,
20 .name = "display0a",
21 .swgroup = TEGRA_SWGROUP_DC,
22 .smmu = {
23 .reg = 0x228,
24 .bit = 1,
25 },
26 .la = {
27 .reg = 0x2e8,
28 .shift = 0,
29 .mask = 0xff,
30 .def = 0xc2,
31 },
32 }, {
33 .id = 0x02,
34 .name = "display0ab",
35 .swgroup = TEGRA_SWGROUP_DCB,
36 .smmu = {
37 .reg = 0x228,
38 .bit = 2,
39 },
40 .la = {
41 .reg = 0x2f4,
42 .shift = 0,
43 .mask = 0xff,
44 .def = 0xc6,
45 },
46 }, {
47 .id = 0x03,
48 .name = "display0b",
49 .swgroup = TEGRA_SWGROUP_DC,
50 .smmu = {
51 .reg = 0x228,
52 .bit = 3,
53 },
54 .la = {
55 .reg = 0x2e8,
56 .shift = 16,
57 .mask = 0xff,
58 .def = 0x50,
59 },
60 }, {
61 .id = 0x04,
62 .name = "display0bb",
63 .swgroup = TEGRA_SWGROUP_DCB,
64 .smmu = {
65 .reg = 0x228,
66 .bit = 4,
67 },
68 .la = {
69 .reg = 0x2f4,
70 .shift = 16,
71 .mask = 0xff,
72 .def = 0x50,
73 },
74 }, {
75 .id = 0x05,
76 .name = "display0c",
77 .swgroup = TEGRA_SWGROUP_DC,
78 .smmu = {
79 .reg = 0x228,
80 .bit = 5,
81 },
82 .la = {
83 .reg = 0x2ec,
84 .shift = 0,
85 .mask = 0xff,
86 .def = 0x50,
87 },
88 }, {
89 .id = 0x06,
90 .name = "display0cb",
91 .swgroup = TEGRA_SWGROUP_DCB,
92 .smmu = {
93 .reg = 0x228,
94 .bit = 6,
95 },
96 .la = {
97 .reg = 0x2f8,
98 .shift = 0,
99 .mask = 0xff,
100 .def = 0x50,
101 },
102 }, {
103 .id = 0x0e,
104 .name = "afir",
105 .swgroup = TEGRA_SWGROUP_AFI,
106 .smmu = {
107 .reg = 0x228,
108 .bit = 14,
109 },
110 .la = {
111 .reg = 0x2e0,
112 .shift = 0,
113 .mask = 0xff,
114 .def = 0x13,
115 },
116 }, {
117 .id = 0x0f,
118 .name = "avpcarm7r",
119 .swgroup = TEGRA_SWGROUP_AVPC,
120 .smmu = {
121 .reg = 0x228,
122 .bit = 15,
123 },
124 .la = {
125 .reg = 0x2e4,
126 .shift = 0,
127 .mask = 0xff,
128 .def = 0x04,
129 },
130 }, {
131 .id = 0x10,
132 .name = "displayhc",
133 .swgroup = TEGRA_SWGROUP_DC,
134 .smmu = {
135 .reg = 0x228,
136 .bit = 16,
137 },
138 .la = {
139 .reg = 0x2f0,
140 .shift = 0,
141 .mask = 0xff,
142 .def = 0x50,
143 },
144 }, {
145 .id = 0x11,
146 .name = "displayhcb",
147 .swgroup = TEGRA_SWGROUP_DCB,
148 .smmu = {
149 .reg = 0x228,
150 .bit = 17,
151 },
152 .la = {
153 .reg = 0x2fc,
154 .shift = 0,
155 .mask = 0xff,
156 .def = 0x50,
157 },
158 }, {
159 .id = 0x15,
160 .name = "hdar",
161 .swgroup = TEGRA_SWGROUP_HDA,
162 .smmu = {
163 .reg = 0x228,
164 .bit = 21,
165 },
166 .la = {
167 .reg = 0x318,
168 .shift = 0,
169 .mask = 0xff,
170 .def = 0x24,
171 },
172 }, {
173 .id = 0x16,
174 .name = "host1xdmar",
175 .swgroup = TEGRA_SWGROUP_HC,
176 .smmu = {
177 .reg = 0x228,
178 .bit = 22,
179 },
180 .la = {
181 .reg = 0x310,
182 .shift = 0,
183 .mask = 0xff,
184 .def = 0x1e,
185 },
186 }, {
187 .id = 0x17,
188 .name = "host1xr",
189 .swgroup = TEGRA_SWGROUP_HC,
190 .smmu = {
191 .reg = 0x228,
192 .bit = 23,
193 },
194 .la = {
195 .reg = 0x310,
196 .shift = 16,
197 .mask = 0xff,
198 .def = 0x50,
199 },
200 }, {
201 .id = 0x1c,
202 .name = "msencsrd",
203 .swgroup = TEGRA_SWGROUP_MSENC,
204 .smmu = {
205 .reg = 0x228,
206 .bit = 28,
207 },
208 .la = {
209 .reg = 0x328,
210 .shift = 0,
211 .mask = 0xff,
212 .def = 0x23,
213 },
214 }, {
215 .id = 0x1d,
216 .name = "ppcsahbdmar",
217 .swgroup = TEGRA_SWGROUP_PPCS,
218 .smmu = {
219 .reg = 0x228,
220 .bit = 29,
221 },
222 .la = {
223 .reg = 0x344,
224 .shift = 0,
225 .mask = 0xff,
226 .def = 0x49,
227 },
228 }, {
229 .id = 0x1e,
230 .name = "ppcsahbslvr",
231 .swgroup = TEGRA_SWGROUP_PPCS,
232 .smmu = {
233 .reg = 0x228,
234 .bit = 30,
235 },
236 .la = {
237 .reg = 0x344,
238 .shift = 16,
239 .mask = 0xff,
240 .def = 0x1a,
241 },
242 }, {
243 .id = 0x1f,
244 .name = "satar",
245 .swgroup = TEGRA_SWGROUP_SATA,
246 .smmu = {
247 .reg = 0x228,
248 .bit = 31,
249 },
250 .la = {
251 .reg = 0x350,
252 .shift = 0,
253 .mask = 0xff,
254 .def = 0x65,
255 },
256 }, {
257 .id = 0x22,
258 .name = "vdebsevr",
259 .swgroup = TEGRA_SWGROUP_VDE,
260 .smmu = {
261 .reg = 0x22c,
262 .bit = 2,
263 },
264 .la = {
265 .reg = 0x354,
266 .shift = 0,
267 .mask = 0xff,
268 .def = 0x4f,
269 },
270 }, {
271 .id = 0x23,
272 .name = "vdember",
273 .swgroup = TEGRA_SWGROUP_VDE,
274 .smmu = {
275 .reg = 0x22c,
276 .bit = 3,
277 },
278 .la = {
279 .reg = 0x354,
280 .shift = 16,
281 .mask = 0xff,
282 .def = 0x3d,
283 },
284 }, {
285 .id = 0x24,
286 .name = "vdemcer",
287 .swgroup = TEGRA_SWGROUP_VDE,
288 .smmu = {
289 .reg = 0x22c,
290 .bit = 4,
291 },
292 .la = {
293 .reg = 0x358,
294 .shift = 0,
295 .mask = 0xff,
296 .def = 0x66,
297 },
298 }, {
299 .id = 0x25,
300 .name = "vdetper",
301 .swgroup = TEGRA_SWGROUP_VDE,
302 .smmu = {
303 .reg = 0x22c,
304 .bit = 5,
305 },
306 .la = {
307 .reg = 0x358,
308 .shift = 16,
309 .mask = 0xff,
310 .def = 0xa5,
311 },
312 }, {
313 .id = 0x26,
314 .name = "mpcorelpr",
315 .swgroup = TEGRA_SWGROUP_MPCORELP,
316 .la = {
317 .reg = 0x324,
318 .shift = 0,
319 .mask = 0xff,
320 .def = 0x04,
321 },
322 }, {
323 .id = 0x27,
324 .name = "mpcorer",
325 .swgroup = TEGRA_SWGROUP_MPCORE,
326 .la = {
327 .reg = 0x320,
328 .shift = 0,
329 .mask = 0xff,
330 .def = 0x04,
331 },
332 }, {
333 .id = 0x2b,
334 .name = "msencswr",
335 .swgroup = TEGRA_SWGROUP_MSENC,
336 .smmu = {
337 .reg = 0x22c,
338 .bit = 11,
339 },
340 .la = {
341 .reg = 0x328,
342 .shift = 16,
343 .mask = 0xff,
344 .def = 0x80,
345 },
346 }, {
347 .id = 0x31,
348 .name = "afiw",
349 .swgroup = TEGRA_SWGROUP_AFI,
350 .smmu = {
351 .reg = 0x22c,
352 .bit = 17,
353 },
354 .la = {
355 .reg = 0x2e0,
356 .shift = 16,
357 .mask = 0xff,
358 .def = 0x80,
359 },
360 }, {
361 .id = 0x32,
362 .name = "avpcarm7w",
363 .swgroup = TEGRA_SWGROUP_AVPC,
364 .smmu = {
365 .reg = 0x22c,
366 .bit = 18,
367 },
368 .la = {
369 .reg = 0x2e4,
370 .shift = 16,
371 .mask = 0xff,
372 .def = 0x80,
373 },
374 }, {
375 .id = 0x35,
376 .name = "hdaw",
377 .swgroup = TEGRA_SWGROUP_HDA,
378 .smmu = {
379 .reg = 0x22c,
380 .bit = 21,
381 },
382 .la = {
383 .reg = 0x318,
384 .shift = 16,
385 .mask = 0xff,
386 .def = 0x80,
387 },
388 }, {
389 .id = 0x36,
390 .name = "host1xw",
391 .swgroup = TEGRA_SWGROUP_HC,
392 .smmu = {
393 .reg = 0x22c,
394 .bit = 22,
395 },
396 .la = {
397 .reg = 0x314,
398 .shift = 0,
399 .mask = 0xff,
400 .def = 0x80,
401 },
402 }, {
403 .id = 0x38,
404 .name = "mpcorelpw",
405 .swgroup = TEGRA_SWGROUP_MPCORELP,
406 .la = {
407 .reg = 0x324,
408 .shift = 16,
409 .mask = 0xff,
410 .def = 0x80,
411 },
412 }, {
413 .id = 0x39,
414 .name = "mpcorew",
415 .swgroup = TEGRA_SWGROUP_MPCORE,
416 .la = {
417 .reg = 0x320,
418 .shift = 16,
419 .mask = 0xff,
420 .def = 0x80,
421 },
422 }, {
423 .id = 0x3b,
424 .name = "ppcsahbdmaw",
425 .swgroup = TEGRA_SWGROUP_PPCS,
426 .smmu = {
427 .reg = 0x22c,
428 .bit = 27,
429 },
430 .la = {
431 .reg = 0x348,
432 .shift = 0,
433 .mask = 0xff,
434 .def = 0x80,
435 },
436 }, {
437 .id = 0x3c,
438 .name = "ppcsahbslvw",
439 .swgroup = TEGRA_SWGROUP_PPCS,
440 .smmu = {
441 .reg = 0x22c,
442 .bit = 28,
443 },
444 .la = {
445 .reg = 0x348,
446 .shift = 16,
447 .mask = 0xff,
448 .def = 0x80,
449 },
450 }, {
451 .id = 0x3d,
452 .name = "sataw",
453 .swgroup = TEGRA_SWGROUP_SATA,
454 .smmu = {
455 .reg = 0x22c,
456 .bit = 29,
457 },
458 .la = {
459 .reg = 0x350,
460 .shift = 16,
461 .mask = 0xff,
462 .def = 0x65,
463 },
464 }, {
465 .id = 0x3e,
466 .name = "vdebsevw",
467 .swgroup = TEGRA_SWGROUP_VDE,
468 .smmu = {
469 .reg = 0x22c,
470 .bit = 30,
471 },
472 .la = {
473 .reg = 0x35c,
474 .shift = 0,
475 .mask = 0xff,
476 .def = 0x80,
477 },
478 }, {
479 .id = 0x3f,
480 .name = "vdedbgw",
481 .swgroup = TEGRA_SWGROUP_VDE,
482 .smmu = {
483 .reg = 0x22c,
484 .bit = 31,
485 },
486 .la = {
487 .reg = 0x35c,
488 .shift = 16,
489 .mask = 0xff,
490 .def = 0x80,
491 },
492 }, {
493 .id = 0x40,
494 .name = "vdembew",
495 .swgroup = TEGRA_SWGROUP_VDE,
496 .smmu = {
497 .reg = 0x230,
498 .bit = 0,
499 },
500 .la = {
501 .reg = 0x360,
502 .shift = 0,
503 .mask = 0xff,
504 .def = 0x80,
505 },
506 }, {
507 .id = 0x41,
508 .name = "vdetpmw",
509 .swgroup = TEGRA_SWGROUP_VDE,
510 .smmu = {
511 .reg = 0x230,
512 .bit = 1,
513 },
514 .la = {
515 .reg = 0x360,
516 .shift = 16,
517 .mask = 0xff,
518 .def = 0x80,
519 },
520 }, {
521 .id = 0x44,
522 .name = "ispra",
523 .swgroup = TEGRA_SWGROUP_ISP2,
524 .smmu = {
525 .reg = 0x230,
526 .bit = 4,
527 },
528 .la = {
529 .reg = 0x370,
530 .shift = 0,
531 .mask = 0xff,
532 .def = 0x18,
533 },
534 }, {
535 .id = 0x46,
536 .name = "ispwa",
537 .swgroup = TEGRA_SWGROUP_ISP2,
538 .smmu = {
539 .reg = 0x230,
540 .bit = 6,
541 },
542 .la = {
543 .reg = 0x374,
544 .shift = 0,
545 .mask = 0xff,
546 .def = 0x80,
547 },
548 }, {
549 .id = 0x47,
550 .name = "ispwb",
551 .swgroup = TEGRA_SWGROUP_ISP2,
552 .smmu = {
553 .reg = 0x230,
554 .bit = 7,
555 },
556 .la = {
557 .reg = 0x374,
558 .shift = 16,
559 .mask = 0xff,
560 .def = 0x80,
561 },
562 }, {
563 .id = 0x4a,
564 .name = "xusb_hostr",
565 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
566 .smmu = {
567 .reg = 0x230,
568 .bit = 10,
569 },
570 .la = {
571 .reg = 0x37c,
572 .shift = 0,
573 .mask = 0xff,
574 .def = 0x39,
575 },
576 }, {
577 .id = 0x4b,
578 .name = "xusb_hostw",
579 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
580 .smmu = {
581 .reg = 0x230,
582 .bit = 11,
583 },
584 .la = {
585 .reg = 0x37c,
586 .shift = 16,
587 .mask = 0xff,
588 .def = 0x80,
589 },
590 }, {
591 .id = 0x4c,
592 .name = "xusb_devr",
593 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
594 .smmu = {
595 .reg = 0x230,
596 .bit = 12,
597 },
598 .la = {
599 .reg = 0x380,
600 .shift = 0,
601 .mask = 0xff,
602 .def = 0x39,
603 },
604 }, {
605 .id = 0x4d,
606 .name = "xusb_devw",
607 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
608 .smmu = {
609 .reg = 0x230,
610 .bit = 13,
611 },
612 .la = {
613 .reg = 0x380,
614 .shift = 16,
615 .mask = 0xff,
616 .def = 0x80,
617 },
618 }, {
619 .id = 0x4e,
620 .name = "isprab",
621 .swgroup = TEGRA_SWGROUP_ISP2B,
622 .smmu = {
623 .reg = 0x230,
624 .bit = 14,
625 },
626 .la = {
627 .reg = 0x384,
628 .shift = 0,
629 .mask = 0xff,
630 .def = 0x18,
631 },
632 }, {
633 .id = 0x50,
634 .name = "ispwab",
635 .swgroup = TEGRA_SWGROUP_ISP2B,
636 .smmu = {
637 .reg = 0x230,
638 .bit = 16,
639 },
640 .la = {
641 .reg = 0x388,
642 .shift = 0,
643 .mask = 0xff,
644 .def = 0x80,
645 },
646 }, {
647 .id = 0x51,
648 .name = "ispwbb",
649 .swgroup = TEGRA_SWGROUP_ISP2B,
650 .smmu = {
651 .reg = 0x230,
652 .bit = 17,
653 },
654 .la = {
655 .reg = 0x388,
656 .shift = 16,
657 .mask = 0xff,
658 .def = 0x80,
659 },
660 }, {
661 .id = 0x54,
662 .name = "tsecsrd",
663 .swgroup = TEGRA_SWGROUP_TSEC,
664 .smmu = {
665 .reg = 0x230,
666 .bit = 20,
667 },
668 .la = {
669 .reg = 0x390,
670 .shift = 0,
671 .mask = 0xff,
672 .def = 0x9b,
673 },
674 }, {
675 .id = 0x55,
676 .name = "tsecswr",
677 .swgroup = TEGRA_SWGROUP_TSEC,
678 .smmu = {
679 .reg = 0x230,
680 .bit = 21,
681 },
682 .la = {
683 .reg = 0x390,
684 .shift = 16,
685 .mask = 0xff,
686 .def = 0x80,
687 },
688 }, {
689 .id = 0x56,
690 .name = "a9avpscr",
691 .swgroup = TEGRA_SWGROUP_A9AVP,
692 .smmu = {
693 .reg = 0x230,
694 .bit = 22,
695 },
696 .la = {
697 .reg = 0x3a4,
698 .shift = 0,
699 .mask = 0xff,
700 .def = 0x04,
701 },
702 }, {
703 .id = 0x57,
704 .name = "a9avpscw",
705 .swgroup = TEGRA_SWGROUP_A9AVP,
706 .smmu = {
707 .reg = 0x230,
708 .bit = 23,
709 },
710 .la = {
711 .reg = 0x3a4,
712 .shift = 16,
713 .mask = 0xff,
714 .def = 0x80,
715 },
716 }, {
717 .id = 0x58,
718 .name = "gpusrd",
719 .swgroup = TEGRA_SWGROUP_GPU,
720 .smmu = {
721 /* read-only */
722 .reg = 0x230,
723 .bit = 24,
724 },
725 .la = {
726 .reg = 0x3c8,
727 .shift = 0,
728 .mask = 0xff,
729 .def = 0x1a,
730 },
731 }, {
732 .id = 0x59,
733 .name = "gpuswr",
734 .swgroup = TEGRA_SWGROUP_GPU,
735 .smmu = {
736 /* read-only */
737 .reg = 0x230,
738 .bit = 25,
739 },
740 .la = {
741 .reg = 0x3c8,
742 .shift = 16,
743 .mask = 0xff,
744 .def = 0x80,
745 },
746 }, {
747 .id = 0x5a,
748 .name = "displayt",
749 .swgroup = TEGRA_SWGROUP_DC,
750 .smmu = {
751 .reg = 0x230,
752 .bit = 26,
753 },
754 .la = {
755 .reg = 0x2f0,
756 .shift = 16,
757 .mask = 0xff,
758 .def = 0x50,
759 },
760 }, {
761 .id = 0x60,
762 .name = "sdmmcra",
763 .swgroup = TEGRA_SWGROUP_SDMMC1A,
764 .smmu = {
765 .reg = 0x234,
766 .bit = 0,
767 },
768 .la = {
769 .reg = 0x3b8,
770 .shift = 0,
771 .mask = 0xff,
772 .def = 0x49,
773 },
774 }, {
775 .id = 0x61,
776 .name = "sdmmcraa",
777 .swgroup = TEGRA_SWGROUP_SDMMC2A,
778 .smmu = {
779 .reg = 0x234,
780 .bit = 1,
781 },
782 .la = {
783 .reg = 0x3bc,
784 .shift = 0,
785 .mask = 0xff,
786 .def = 0x49,
787 },
788 }, {
789 .id = 0x62,
790 .name = "sdmmcr",
791 .swgroup = TEGRA_SWGROUP_SDMMC3A,
792 .smmu = {
793 .reg = 0x234,
794 .bit = 2,
795 },
796 .la = {
797 .reg = 0x3c0,
798 .shift = 0,
799 .mask = 0xff,
800 .def = 0x49,
801 },
802 }, {
803 .id = 0x63,
804 .swgroup = TEGRA_SWGROUP_SDMMC4A,
805 .name = "sdmmcrab",
806 .smmu = {
807 .reg = 0x234,
808 .bit = 3,
809 },
810 .la = {
811 .reg = 0x3c4,
812 .shift = 0,
813 .mask = 0xff,
814 .def = 0x49,
815 },
816 }, {
817 .id = 0x64,
818 .name = "sdmmcwa",
819 .swgroup = TEGRA_SWGROUP_SDMMC1A,
820 .smmu = {
821 .reg = 0x234,
822 .bit = 4,
823 },
824 .la = {
825 .reg = 0x3b8,
826 .shift = 16,
827 .mask = 0xff,
828 .def = 0x80,
829 },
830 }, {
831 .id = 0x65,
832 .name = "sdmmcwaa",
833 .swgroup = TEGRA_SWGROUP_SDMMC2A,
834 .smmu = {
835 .reg = 0x234,
836 .bit = 5,
837 },
838 .la = {
839 .reg = 0x3bc,
840 .shift = 16,
841 .mask = 0xff,
842 .def = 0x80,
843 },
844 }, {
845 .id = 0x66,
846 .name = "sdmmcw",
847 .swgroup = TEGRA_SWGROUP_SDMMC3A,
848 .smmu = {
849 .reg = 0x234,
850 .bit = 6,
851 },
852 .la = {
853 .reg = 0x3c0,
854 .shift = 16,
855 .mask = 0xff,
856 .def = 0x80,
857 },
858 }, {
859 .id = 0x67,
860 .name = "sdmmcwab",
861 .swgroup = TEGRA_SWGROUP_SDMMC4A,
862 .smmu = {
863 .reg = 0x234,
864 .bit = 7,
865 },
866 .la = {
867 .reg = 0x3c4,
868 .shift = 16,
869 .mask = 0xff,
870 .def = 0x80,
871 },
872 }, {
873 .id = 0x6c,
874 .name = "vicsrd",
875 .swgroup = TEGRA_SWGROUP_VIC,
876 .smmu = {
877 .reg = 0x234,
878 .bit = 12,
879 },
880 .la = {
881 .reg = 0x394,
882 .shift = 0,
883 .mask = 0xff,
884 .def = 0x1a,
885 },
886 }, {
887 .id = 0x6d,
888 .name = "vicswr",
889 .swgroup = TEGRA_SWGROUP_VIC,
890 .smmu = {
891 .reg = 0x234,
892 .bit = 13,
893 },
894 .la = {
895 .reg = 0x394,
896 .shift = 16,
897 .mask = 0xff,
898 .def = 0x80,
899 },
900 }, {
901 .id = 0x72,
902 .name = "viw",
903 .swgroup = TEGRA_SWGROUP_VI,
904 .smmu = {
905 .reg = 0x234,
906 .bit = 18,
907 },
908 .la = {
909 .reg = 0x398,
910 .shift = 0,
911 .mask = 0xff,
912 .def = 0x80,
913 },
914 }, {
915 .id = 0x73,
916 .name = "displayd",
917 .swgroup = TEGRA_SWGROUP_DC,
918 .smmu = {
919 .reg = 0x234,
920 .bit = 19,
921 },
922 .la = {
923 .reg = 0x3c8,
924 .shift = 0,
925 .mask = 0xff,
926 .def = 0x50,
927 },
928 },
929};
930
931static const struct tegra_smmu_swgroup tegra124_swgroups[] = {
932 { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
933 { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
934 { .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
935 { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
936 { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
937 { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
938 { .name = "msenc", .swgroup = TEGRA_SWGROUP_MSENC, .reg = 0x264 },
939 { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
940 { .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 },
941 { .name = "vde", .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c },
942 { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
943 { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
944 { .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
945 { .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 },
946 { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
947 { .name = "a9avp", .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 },
948 { .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac },
949 { .name = "sdmmc1a", .swgroup = TEGRA_SWGROUP_SDMMC1A, .reg = 0xa94 },
950 { .name = "sdmmc2a", .swgroup = TEGRA_SWGROUP_SDMMC2A, .reg = 0xa98 },
951 { .name = "sdmmc3a", .swgroup = TEGRA_SWGROUP_SDMMC3A, .reg = 0xa9c },
952 { .name = "sdmmc4a", .swgroup = TEGRA_SWGROUP_SDMMC4A, .reg = 0xaa0 },
953 { .name = "vic", .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 },
954 { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
955};
956
957static const unsigned int tegra124_group_drm[] = {
958 TEGRA_SWGROUP_DC,
959 TEGRA_SWGROUP_DCB,
960 TEGRA_SWGROUP_GPU,
961 TEGRA_SWGROUP_VIC,
962};
963
964static const struct tegra_smmu_group_soc tegra124_groups[] = {
965 {
966 .name = "drm",
967 .swgroups = tegra124_group_drm,
968 .num_swgroups = ARRAY_SIZE(tegra124_group_drm),
969 },
970};
971
972#define TEGRA124_MC_RESET(_name, _control, _status, _bit) \
973 { \
974 .name = #_name, \
975 .id = TEGRA124_MC_RESET_##_name, \
976 .control = _control, \
977 .status = _status, \
978 .bit = _bit, \
979 }
980
981static const struct tegra_mc_reset tegra124_mc_resets[] = {
982 TEGRA124_MC_RESET(AFI, 0x200, 0x204, 0),
983 TEGRA124_MC_RESET(AVPC, 0x200, 0x204, 1),
984 TEGRA124_MC_RESET(DC, 0x200, 0x204, 2),
985 TEGRA124_MC_RESET(DCB, 0x200, 0x204, 3),
986 TEGRA124_MC_RESET(HC, 0x200, 0x204, 6),
987 TEGRA124_MC_RESET(HDA, 0x200, 0x204, 7),
988 TEGRA124_MC_RESET(ISP2, 0x200, 0x204, 8),
989 TEGRA124_MC_RESET(MPCORE, 0x200, 0x204, 9),
990 TEGRA124_MC_RESET(MPCORELP, 0x200, 0x204, 10),
991 TEGRA124_MC_RESET(MSENC, 0x200, 0x204, 11),
992 TEGRA124_MC_RESET(PPCS, 0x200, 0x204, 14),
993 TEGRA124_MC_RESET(SATA, 0x200, 0x204, 15),
994 TEGRA124_MC_RESET(VDE, 0x200, 0x204, 16),
995 TEGRA124_MC_RESET(VI, 0x200, 0x204, 17),
996 TEGRA124_MC_RESET(VIC, 0x200, 0x204, 18),
997 TEGRA124_MC_RESET(XUSB_HOST, 0x200, 0x204, 19),
998 TEGRA124_MC_RESET(XUSB_DEV, 0x200, 0x204, 20),
999 TEGRA124_MC_RESET(TSEC, 0x200, 0x204, 21),
1000 TEGRA124_MC_RESET(SDMMC1, 0x200, 0x204, 22),
1001 TEGRA124_MC_RESET(SDMMC2, 0x200, 0x204, 23),
1002 TEGRA124_MC_RESET(SDMMC3, 0x200, 0x204, 25),
1003 TEGRA124_MC_RESET(SDMMC4, 0x970, 0x974, 0),
1004 TEGRA124_MC_RESET(ISP2B, 0x970, 0x974, 1),
1005 TEGRA124_MC_RESET(GPU, 0x970, 0x974, 2),
1006};
1007
1008#ifdef CONFIG_ARCH_TEGRA_124_SOC
1009static const unsigned long tegra124_mc_emem_regs[] = {
1010 MC_EMEM_ARB_CFG,
1011 MC_EMEM_ARB_OUTSTANDING_REQ,
1012 MC_EMEM_ARB_TIMING_RCD,
1013 MC_EMEM_ARB_TIMING_RP,
1014 MC_EMEM_ARB_TIMING_RC,
1015 MC_EMEM_ARB_TIMING_RAS,
1016 MC_EMEM_ARB_TIMING_FAW,
1017 MC_EMEM_ARB_TIMING_RRD,
1018 MC_EMEM_ARB_TIMING_RAP2PRE,
1019 MC_EMEM_ARB_TIMING_WAP2PRE,
1020 MC_EMEM_ARB_TIMING_R2R,
1021 MC_EMEM_ARB_TIMING_W2W,
1022 MC_EMEM_ARB_TIMING_R2W,
1023 MC_EMEM_ARB_TIMING_W2R,
1024 MC_EMEM_ARB_DA_TURNS,
1025 MC_EMEM_ARB_DA_COVERS,
1026 MC_EMEM_ARB_MISC0,
1027 MC_EMEM_ARB_MISC1,
1028 MC_EMEM_ARB_RING1_THROTTLE
1029};
1030
1031static const struct tegra_smmu_soc tegra124_smmu_soc = {
1032 .clients = tegra124_mc_clients,
1033 .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1034 .swgroups = tegra124_swgroups,
1035 .num_swgroups = ARRAY_SIZE(tegra124_swgroups),
1036 .groups = tegra124_groups,
1037 .num_groups = ARRAY_SIZE(tegra124_groups),
1038 .supports_round_robin_arbitration = true,
1039 .supports_request_limit = true,
1040 .num_tlb_lines = 32,
1041 .num_asids = 128,
1042};
1043
1044const struct tegra_mc_soc tegra124_mc_soc = {
1045 .clients = tegra124_mc_clients,
1046 .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1047 .num_address_bits = 34,
1048 .atom_size = 32,
1049 .client_id_mask = 0x7f,
1050 .smmu = &tegra124_smmu_soc,
1051 .emem_regs = tegra124_mc_emem_regs,
1052 .num_emem_regs = ARRAY_SIZE(tegra124_mc_emem_regs),
1053 .intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1054 MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
1055 MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1056 .reset_ops = &tegra_mc_reset_ops_common,
1057 .resets = tegra124_mc_resets,
1058 .num_resets = ARRAY_SIZE(tegra124_mc_resets),
1059};
1060#endif /* CONFIG_ARCH_TEGRA_124_SOC */
1061
1062#ifdef CONFIG_ARCH_TEGRA_132_SOC
1063static const struct tegra_smmu_soc tegra132_smmu_soc = {
1064 .clients = tegra124_mc_clients,
1065 .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1066 .swgroups = tegra124_swgroups,
1067 .num_swgroups = ARRAY_SIZE(tegra124_swgroups),
1068 .groups = tegra124_groups,
1069 .num_groups = ARRAY_SIZE(tegra124_groups),
1070 .supports_round_robin_arbitration = true,
1071 .supports_request_limit = true,
1072 .num_tlb_lines = 32,
1073 .num_asids = 128,
1074};
1075
1076const struct tegra_mc_soc tegra132_mc_soc = {
1077 .clients = tegra124_mc_clients,
1078 .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1079 .num_address_bits = 34,
1080 .atom_size = 32,
1081 .client_id_mask = 0x7f,
1082 .smmu = &tegra132_smmu_soc,
1083 .intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1084 MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
1085 MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1086 .reset_ops = &tegra_mc_reset_ops_common,
1087 .resets = tegra124_mc_resets,
1088 .num_resets = ARRAY_SIZE(tegra124_mc_resets),
1089};
1090#endif /* CONFIG_ARCH_TEGRA_132_SOC */