Loading...
Note: File does not exist in v4.6.
1/*
2 * Registers of Silicon Image SiI8620 Mobile HD Transmitter
3 *
4 * Copyright (C) 2015, Samsung Electronics Co., Ltd.
5 * Andrzej Hajda <a.hajda@samsung.com>
6 *
7 * Based on MHL driver for Android devices.
8 * Copyright (C) 2013-2014 Silicon Image, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#ifndef __SIL_SII8620_H__
16#define __SIL_SII8620_H__
17
18/* Vendor ID Low byte, default value: 0x01 */
19#define REG_VND_IDL 0x0000
20
21/* Vendor ID High byte, default value: 0x00 */
22#define REG_VND_IDH 0x0001
23
24/* Device ID Low byte, default value: 0x60 */
25#define REG_DEV_IDL 0x0002
26
27/* Device ID High byte, default value: 0x86 */
28#define REG_DEV_IDH 0x0003
29
30/* Device Revision, default value: 0x10 */
31#define REG_DEV_REV 0x0004
32
33/* OTP DBYTE510, default value: 0x00 */
34#define REG_OTP_DBYTE510 0x0006
35
36/* System Control #1, default value: 0x00 */
37#define REG_SYS_CTRL1 0x0008
38#define BIT_SYS_CTRL1_OTPVMUTEOVR_SET BIT(7)
39#define BIT_SYS_CTRL1_VSYNCPIN BIT(6)
40#define BIT_SYS_CTRL1_OTPADROPOVR_SET BIT(5)
41#define BIT_SYS_CTRL1_BLOCK_DDC_BY_HPD BIT(4)
42#define BIT_SYS_CTRL1_OTP2XVOVR_EN BIT(3)
43#define BIT_SYS_CTRL1_OTP2XAOVR_EN BIT(2)
44#define BIT_SYS_CTRL1_TX_CTRL_HDMI BIT(1)
45#define BIT_SYS_CTRL1_OTPAMUTEOVR_SET BIT(0)
46
47/* System Control DPD, default value: 0x90 */
48#define REG_DPD 0x000b
49#define BIT_DPD_PWRON_PLL BIT(7)
50#define BIT_DPD_PDNTX12 BIT(6)
51#define BIT_DPD_PDNRX12 BIT(5)
52#define BIT_DPD_OSC_EN BIT(4)
53#define BIT_DPD_PWRON_HSIC BIT(3)
54#define BIT_DPD_PDIDCK_N BIT(2)
55#define BIT_DPD_PD_MHL_CLK_N BIT(1)
56
57/* Dual link Control, default value: 0x00 */
58#define REG_DCTL 0x000d
59#define BIT_DCTL_TDM_LCLK_PHASE BIT(7)
60#define BIT_DCTL_HSIC_CLK_PHASE BIT(6)
61#define BIT_DCTL_CTS_TCK_PHASE BIT(5)
62#define BIT_DCTL_EXT_DDC_SEL BIT(4)
63#define BIT_DCTL_TRANSCODE BIT(3)
64#define BIT_DCTL_HSIC_RX_STROBE_PHASE BIT(2)
65#define BIT_DCTL_HSIC_TX_BIST_START_SEL BIT(1)
66#define BIT_DCTL_TCLKNX_PHASE BIT(0)
67
68/* PWD Software Reset, default value: 0x20 */
69#define REG_PWD_SRST 0x000e
70#define BIT_PWD_SRST_COC_DOC_RST BIT(7)
71#define BIT_PWD_SRST_CBUS_RST_SW BIT(6)
72#define BIT_PWD_SRST_CBUS_RST_SW_EN BIT(5)
73#define BIT_PWD_SRST_MHLFIFO_RST BIT(4)
74#define BIT_PWD_SRST_CBUS_RST BIT(3)
75#define BIT_PWD_SRST_SW_RST_AUTO BIT(2)
76#define BIT_PWD_SRST_HDCP2X_SW_RST BIT(1)
77#define BIT_PWD_SRST_SW_RST BIT(0)
78
79/* AKSV_1, default value: 0x00 */
80#define REG_AKSV_1 0x001d
81
82/* Video H Resolution #1, default value: 0x00 */
83#define REG_H_RESL 0x003a
84
85/* Video Mode, default value: 0x00 */
86#define REG_VID_MODE 0x004a
87#define BIT_VID_MODE_M1080P BIT(6)
88
89/* Video Input Mode, default value: 0xc0 */
90#define REG_VID_OVRRD 0x0051
91#define BIT_VID_OVRRD_PP_AUTO_DISABLE BIT(7)
92#define BIT_VID_OVRRD_M1080P_OVRRD BIT(6)
93#define BIT_VID_OVRRD_MINIVSYNC_ON BIT(5)
94#define BIT_VID_OVRRD_3DCONV_EN_FRAME_PACK BIT(4)
95#define BIT_VID_OVRRD_ENABLE_AUTO_PATH_EN BIT(3)
96#define BIT_VID_OVRRD_ENRGB2YCBCR_OVRRD BIT(2)
97#define BIT_VID_OVRRD_ENDOWNSAMPLE_OVRRD BIT(0)
98
99/* I2C Address reassignment, default value: 0x00 */
100#define REG_PAGE_MHLSPEC_ADDR 0x0057
101#define REG_PAGE7_ADDR 0x0058
102#define REG_PAGE8_ADDR 0x005c
103
104/* Fast Interrupt Status, default value: 0x00 */
105#define REG_FAST_INTR_STAT 0x005f
106#define LEN_FAST_INTR_STAT 7
107#define BIT_FAST_INTR_STAT_TIMR 8
108#define BIT_FAST_INTR_STAT_INT2 9
109#define BIT_FAST_INTR_STAT_DDC 10
110#define BIT_FAST_INTR_STAT_SCDT 11
111#define BIT_FAST_INTR_STAT_INFR 13
112#define BIT_FAST_INTR_STAT_EDID 14
113#define BIT_FAST_INTR_STAT_HDCP 15
114#define BIT_FAST_INTR_STAT_MSC 16
115#define BIT_FAST_INTR_STAT_MERR 17
116#define BIT_FAST_INTR_STAT_G2WB 18
117#define BIT_FAST_INTR_STAT_G2WB_ERR 19
118#define BIT_FAST_INTR_STAT_DISC 28
119#define BIT_FAST_INTR_STAT_BLOCK 30
120#define BIT_FAST_INTR_STAT_LTRN 31
121#define BIT_FAST_INTR_STAT_HDCP2 32
122#define BIT_FAST_INTR_STAT_TDM 42
123#define BIT_FAST_INTR_STAT_COC 51
124
125/* GPIO Control, default value: 0x15 */
126#define REG_GPIO_CTRL1 0x006e
127#define BIT_CTRL1_GPIO_I_8 BIT(5)
128#define BIT_CTRL1_GPIO_OEN_8 BIT(4)
129#define BIT_CTRL1_GPIO_I_7 BIT(3)
130#define BIT_CTRL1_GPIO_OEN_7 BIT(2)
131#define BIT_CTRL1_GPIO_I_6 BIT(1)
132#define BIT_CTRL1_GPIO_OEN_6 BIT(0)
133
134/* Interrupt Control, default value: 0x06 */
135#define REG_INT_CTRL 0x006f
136#define BIT_INT_CTRL_SOFTWARE_WP BIT(7)
137#define BIT_INT_CTRL_INTR_OD BIT(2)
138#define BIT_INT_CTRL_INTR_POLARITY BIT(1)
139
140/* Interrupt State, default value: 0x00 */
141#define REG_INTR_STATE 0x0070
142#define BIT_INTR_STATE_INTR_STATE BIT(0)
143
144/* Interrupt Source #1, default value: 0x00 */
145#define REG_INTR1 0x0071
146
147/* Interrupt Source #2, default value: 0x00 */
148#define REG_INTR2 0x0072
149
150/* Interrupt Source #3, default value: 0x01 */
151#define REG_INTR3 0x0073
152#define BIT_DDC_CMD_DONE BIT(3)
153
154/* Interrupt Source #5, default value: 0x00 */
155#define REG_INTR5 0x0074
156
157/* Interrupt #1 Mask, default value: 0x00 */
158#define REG_INTR1_MASK 0x0075
159
160/* Interrupt #2 Mask, default value: 0x00 */
161#define REG_INTR2_MASK 0x0076
162
163/* Interrupt #3 Mask, default value: 0x00 */
164#define REG_INTR3_MASK 0x0077
165
166/* Interrupt #5 Mask, default value: 0x00 */
167#define REG_INTR5_MASK 0x0078
168#define BIT_INTR_SCDT_CHANGE BIT(0)
169
170/* Hot Plug Connection Control, default value: 0x45 */
171#define REG_HPD_CTRL 0x0079
172#define BIT_HPD_CTRL_HPD_DS_SIGNAL BIT(7)
173#define BIT_HPD_CTRL_HPD_OUT_OD_EN BIT(6)
174#define BIT_HPD_CTRL_HPD_HIGH BIT(5)
175#define BIT_HPD_CTRL_HPD_OUT_OVR_EN BIT(4)
176#define BIT_HPD_CTRL_GPIO_I_1 BIT(3)
177#define BIT_HPD_CTRL_GPIO_OEN_1 BIT(2)
178#define BIT_HPD_CTRL_GPIO_I_0 BIT(1)
179#define BIT_HPD_CTRL_GPIO_OEN_0 BIT(0)
180
181/* GPIO Control, default value: 0x55 */
182#define REG_GPIO_CTRL 0x007a
183#define BIT_CTRL_GPIO_I_5 BIT(7)
184#define BIT_CTRL_GPIO_OEN_5 BIT(6)
185#define BIT_CTRL_GPIO_I_4 BIT(5)
186#define BIT_CTRL_GPIO_OEN_4 BIT(4)
187#define BIT_CTRL_GPIO_I_3 BIT(3)
188#define BIT_CTRL_GPIO_OEN_3 BIT(2)
189#define BIT_CTRL_GPIO_I_2 BIT(1)
190#define BIT_CTRL_GPIO_OEN_2 BIT(0)
191
192/* Interrupt Source 7, default value: 0x00 */
193#define REG_INTR7 0x007b
194
195/* Interrupt Source 8, default value: 0x00 */
196#define REG_INTR8 0x007c
197
198/* Interrupt #7 Mask, default value: 0x00 */
199#define REG_INTR7_MASK 0x007d
200
201/* Interrupt #8 Mask, default value: 0x00 */
202#define REG_INTR8_MASK 0x007e
203#define BIT_CEA_NEW_VSI BIT(2)
204#define BIT_CEA_NEW_AVI BIT(1)
205
206/* IEEE, default value: 0x10 */
207#define REG_TMDS_CCTRL 0x0080
208#define BIT_TMDS_CCTRL_TMDS_OE BIT(4)
209
210/* TMDS Control #4, default value: 0x02 */
211#define REG_TMDS_CTRL4 0x0085
212#define BIT_TMDS_CTRL4_SCDT_CKDT_SEL BIT(1)
213#define BIT_TMDS_CTRL4_TX_EN_BY_SCDT BIT(0)
214
215/* BIST CNTL, default value: 0x00 */
216#define REG_BIST_CTRL 0x00bb
217#define BIT_RXBIST_VGB_EN BIT(7)
218#define BIT_TXBIST_VGB_EN BIT(6)
219#define BIT_BIST_START_SEL BIT(5)
220#define BIT_BIST_START_BIT BIT(4)
221#define BIT_BIST_ALWAYS_ON BIT(3)
222#define BIT_BIST_TRANS BIT(2)
223#define BIT_BIST_RESET BIT(1)
224#define BIT_BIST_EN BIT(0)
225
226/* BIST DURATION0, default value: 0x00 */
227#define REG_BIST_TEST_SEL 0x00bd
228#define MSK_BIST_TEST_SEL_BIST_PATT_SEL 0x0f
229
230/* BIST VIDEO_MODE, default value: 0x00 */
231#define REG_BIST_VIDEO_MODE 0x00be
232#define MSK_BIST_VIDEO_MODE_BIST_VIDEO_MODE_3_0 0x0f
233
234/* BIST DURATION0, default value: 0x00 */
235#define REG_BIST_DURATION_0 0x00bf
236
237/* BIST DURATION1, default value: 0x00 */
238#define REG_BIST_DURATION_1 0x00c0
239
240/* BIST DURATION2, default value: 0x00 */
241#define REG_BIST_DURATION_2 0x00c1
242
243/* BIST 8BIT_PATTERN, default value: 0x00 */
244#define REG_BIST_8BIT_PATTERN 0x00c2
245
246/* LM DDC, default value: 0x80 */
247#define REG_LM_DDC 0x00c7
248#define BIT_LM_DDC_SW_TPI_EN_DISABLED BIT(7)
249
250#define BIT_LM_DDC_VIDEO_MUTE_EN BIT(5)
251#define BIT_LM_DDC_DDC_TPI_SW BIT(2)
252#define BIT_LM_DDC_DDC_GRANT BIT(1)
253#define BIT_LM_DDC_DDC_GPU_REQUEST BIT(0)
254
255/* DDC I2C Manual, default value: 0x03 */
256#define REG_DDC_MANUAL 0x00ec
257#define BIT_DDC_MANUAL_MAN_DDC BIT(7)
258#define BIT_DDC_MANUAL_VP_SEL BIT(6)
259#define BIT_DDC_MANUAL_DSDA BIT(5)
260#define BIT_DDC_MANUAL_DSCL BIT(4)
261#define BIT_DDC_MANUAL_GCP_HW_CTL_EN BIT(3)
262#define BIT_DDC_MANUAL_DDCM_ABORT_WP BIT(2)
263#define BIT_DDC_MANUAL_IO_DSDA BIT(1)
264#define BIT_DDC_MANUAL_IO_DSCL BIT(0)
265
266/* DDC I2C Target Slave Address, default value: 0x00 */
267#define REG_DDC_ADDR 0x00ed
268#define MSK_DDC_ADDR_DDC_ADDR 0xfe
269
270/* DDC I2C Target Segment Address, default value: 0x00 */
271#define REG_DDC_SEGM 0x00ee
272
273/* DDC I2C Target Offset Address, default value: 0x00 */
274#define REG_DDC_OFFSET 0x00ef
275
276/* DDC I2C Data In count #1, default value: 0x00 */
277#define REG_DDC_DIN_CNT1 0x00f0
278
279/* DDC I2C Data In count #2, default value: 0x00 */
280#define REG_DDC_DIN_CNT2 0x00f1
281#define MSK_DDC_DIN_CNT2_DDC_DIN_CNT_9_8 0x03
282
283/* DDC I2C Status, default value: 0x04 */
284#define REG_DDC_STATUS 0x00f2
285#define BIT_DDC_STATUS_DDC_BUS_LOW BIT(6)
286#define BIT_DDC_STATUS_DDC_NO_ACK BIT(5)
287#define BIT_DDC_STATUS_DDC_I2C_IN_PROG BIT(4)
288#define BIT_DDC_STATUS_DDC_FIFO_FULL BIT(3)
289#define BIT_DDC_STATUS_DDC_FIFO_EMPTY BIT(2)
290#define BIT_DDC_STATUS_DDC_FIFO_READ_IN_SUE BIT(1)
291#define BIT_DDC_STATUS_DDC_FIFO_WRITE_IN_USE BIT(0)
292
293/* DDC I2C Command, default value: 0x70 */
294#define REG_DDC_CMD 0x00f3
295#define BIT_DDC_CMD_HDCP_DDC_EN BIT(6)
296#define BIT_DDC_CMD_SDA_DEL_EN BIT(5)
297#define BIT_DDC_CMD_DDC_FLT_EN BIT(4)
298
299#define MSK_DDC_CMD_DDC_CMD 0x0f
300#define VAL_DDC_CMD_ENH_DDC_READ_NO_ACK 0x04
301#define VAL_DDC_CMD_DDC_CMD_CLEAR_FIFO 0x09
302#define VAL_DDC_CMD_DDC_CMD_ABORT 0x0f
303
304/* DDC I2C FIFO Data In/Out, default value: 0x00 */
305#define REG_DDC_DATA 0x00f4
306
307/* DDC I2C Data Out Counter, default value: 0x00 */
308#define REG_DDC_DOUT_CNT 0x00f5
309#define BIT_DDC_DOUT_CNT_DDC_DELAY_CNT_8 BIT(7)
310#define MSK_DDC_DOUT_CNT_DDC_DATA_OUT_CNT 0x1f
311
312/* DDC I2C Delay Count, default value: 0x14 */
313#define REG_DDC_DELAY_CNT 0x00f6
314
315/* Test Control, default value: 0x80 */
316#define REG_TEST_TXCTRL 0x00f7
317#define BIT_TEST_TXCTRL_RCLK_REF_SEL BIT(7)
318#define BIT_TEST_TXCTRL_PCLK_REF_SEL BIT(6)
319#define MSK_TEST_TXCTRL_BYPASS_PLL_CLK 0x3c
320#define BIT_TEST_TXCTRL_HDMI_MODE BIT(1)
321#define BIT_TEST_TXCTRL_TST_PLLCK BIT(0)
322
323/* CBUS Address, default value: 0x00 */
324#define REG_PAGE_CBUS_ADDR 0x00f8
325
326/* I2C Device Address re-assignment */
327#define REG_PAGE1_ADDR 0x00fc
328#define REG_PAGE2_ADDR 0x00fd
329#define REG_PAGE3_ADDR 0x00fe
330#define REG_HW_TPI_ADDR 0x00ff
331
332/* USBT CTRL0, default value: 0x00 */
333#define REG_UTSRST 0x0100
334#define BIT_UTSRST_FC_SRST BIT(5)
335#define BIT_UTSRST_KEEPER_SRST BIT(4)
336#define BIT_UTSRST_HTX_SRST BIT(3)
337#define BIT_UTSRST_TRX_SRST BIT(2)
338#define BIT_UTSRST_TTX_SRST BIT(1)
339#define BIT_UTSRST_HRX_SRST BIT(0)
340
341/* HSIC RX Control3, default value: 0x07 */
342#define REG_HRXCTRL3 0x0104
343#define MSK_HRXCTRL3_HRX_AFFCTRL 0xf0
344#define BIT_HRXCTRL3_HRX_OUT_EN BIT(2)
345#define BIT_HRXCTRL3_STATUS_EN BIT(1)
346#define BIT_HRXCTRL3_HRX_STAY_RESET BIT(0)
347
348/* HSIC RX INT Registers */
349#define REG_HRXINTL 0x0111
350#define REG_HRXINTH 0x0112
351
352/* TDM TX NUMBITS, default value: 0x0c */
353#define REG_TTXNUMB 0x0116
354#define MSK_TTXNUMB_TTX_AFFCTRL_3_0 0xf0
355#define BIT_TTXNUMB_TTX_COM1_AT_SYNC_WAIT BIT(3)
356#define MSK_TTXNUMB_TTX_NUMBPS 0x07
357
358/* TDM TX NUMSPISYM, default value: 0x04 */
359#define REG_TTXSPINUMS 0x0117
360
361/* TDM TX NUMHSICSYM, default value: 0x14 */
362#define REG_TTXHSICNUMS 0x0118
363
364/* TDM TX NUMTOTSYM, default value: 0x18 */
365#define REG_TTXTOTNUMS 0x0119
366
367/* TDM TX INT Low, default value: 0x00 */
368#define REG_TTXINTL 0x0136
369#define BIT_TTXINTL_TTX_INTR7 BIT(7)
370#define BIT_TTXINTL_TTX_INTR6 BIT(6)
371#define BIT_TTXINTL_TTX_INTR5 BIT(5)
372#define BIT_TTXINTL_TTX_INTR4 BIT(4)
373#define BIT_TTXINTL_TTX_INTR3 BIT(3)
374#define BIT_TTXINTL_TTX_INTR2 BIT(2)
375#define BIT_TTXINTL_TTX_INTR1 BIT(1)
376#define BIT_TTXINTL_TTX_INTR0 BIT(0)
377
378/* TDM TX INT High, default value: 0x00 */
379#define REG_TTXINTH 0x0137
380#define BIT_TTXINTH_TTX_INTR15 BIT(7)
381#define BIT_TTXINTH_TTX_INTR14 BIT(6)
382#define BIT_TTXINTH_TTX_INTR13 BIT(5)
383#define BIT_TTXINTH_TTX_INTR12 BIT(4)
384#define BIT_TTXINTH_TTX_INTR11 BIT(3)
385#define BIT_TTXINTH_TTX_INTR10 BIT(2)
386#define BIT_TTXINTH_TTX_INTR9 BIT(1)
387#define BIT_TTXINTH_TTX_INTR8 BIT(0)
388
389/* TDM RX Control, default value: 0x1c */
390#define REG_TRXCTRL 0x013b
391#define BIT_TRXCTRL_TRX_CLR_WVALLOW BIT(4)
392#define BIT_TRXCTRL_TRX_FROM_SE_COC BIT(3)
393#define MSK_TRXCTRL_TRX_NUMBPS_2_0 0x07
394
395/* TDM RX NUMSPISYM, default value: 0x04 */
396#define REG_TRXSPINUMS 0x013c
397
398/* TDM RX NUMHSICSYM, default value: 0x14 */
399#define REG_TRXHSICNUMS 0x013d
400
401/* TDM RX NUMTOTSYM, default value: 0x18 */
402#define REG_TRXTOTNUMS 0x013e
403
404/* TDM RX Status 2nd, default value: 0x00 */
405#define REG_TRXSTA2 0x015c
406#define MSK_TDM_SYNCHRONIZED 0xc0
407#define VAL_TDM_SYNCHRONIZED 0x80
408
409/* TDM RX INT Low, default value: 0x00 */
410#define REG_TRXINTL 0x0163
411
412/* TDM RX INT High, default value: 0x00 */
413#define REG_TRXINTH 0x0164
414#define BIT_TDM_INTR_SYNC_DATA BIT(0)
415#define BIT_TDM_INTR_SYNC_WAIT BIT(1)
416
417/* TDM RX INTMASK High, default value: 0x00 */
418#define REG_TRXINTMH 0x0166
419
420/* HSIC TX CRTL, default value: 0x00 */
421#define REG_HTXCTRL 0x0169
422#define BIT_HTXCTRL_HTX_ALLSBE_SOP BIT(4)
423#define BIT_HTXCTRL_HTX_RGDINV_USB BIT(3)
424#define BIT_HTXCTRL_HTX_RSPTDM_BUSY BIT(2)
425#define BIT_HTXCTRL_HTX_DRVCONN1 BIT(1)
426#define BIT_HTXCTRL_HTX_DRVRST1 BIT(0)
427
428/* HSIC TX INT Low, default value: 0x00 */
429#define REG_HTXINTL 0x017d
430
431/* HSIC TX INT High, default value: 0x00 */
432#define REG_HTXINTH 0x017e
433
434/* HSIC Keeper, default value: 0x00 */
435#define REG_KEEPER 0x0181
436#define MSK_KEEPER_MODE 0x03
437#define VAL_KEEPER_MODE_HOST 0
438#define VAL_KEEPER_MODE_DEVICE 2
439
440/* HSIC Flow Control General, default value: 0x02 */
441#define REG_FCGC 0x0183
442#define BIT_FCGC_HSIC_HOSTMODE BIT(1)
443#define BIT_FCGC_HSIC_ENABLE BIT(0)
444
445/* HSIC Flow Control CTR13, default value: 0xfc */
446#define REG_FCCTR13 0x0191
447
448/* HSIC Flow Control CTR14, default value: 0xff */
449#define REG_FCCTR14 0x0192
450
451/* HSIC Flow Control CTR15, default value: 0xff */
452#define REG_FCCTR15 0x0193
453
454/* HSIC Flow Control CTR50, default value: 0x03 */
455#define REG_FCCTR50 0x01b6
456
457/* HSIC Flow Control INTR0, default value: 0x00 */
458#define REG_FCINTR0 0x01ec
459#define REG_FCINTR1 0x01ed
460#define REG_FCINTR2 0x01ee
461#define REG_FCINTR3 0x01ef
462#define REG_FCINTR4 0x01f0
463#define REG_FCINTR5 0x01f1
464#define REG_FCINTR6 0x01f2
465#define REG_FCINTR7 0x01f3
466
467/* TDM Low Latency, default value: 0x20 */
468#define REG_TDMLLCTL 0x01fc
469#define MSK_TDMLLCTL_TRX_LL_SEL_MANUAL 0xc0
470#define MSK_TDMLLCTL_TRX_LL_SEL_MODE 0x30
471#define MSK_TDMLLCTL_TTX_LL_SEL_MANUAL 0x0c
472#define BIT_TDMLLCTL_TTX_LL_TIE_LOW BIT(1)
473#define BIT_TDMLLCTL_TTX_LL_SEL_MODE BIT(0)
474
475/* TMDS 0 Clock Control, default value: 0x10 */
476#define REG_TMDS0_CCTRL1 0x0210
477#define MSK_TMDS0_CCTRL1_TEST_SEL 0xc0
478#define MSK_TMDS0_CCTRL1_CLK1X_CTL 0x30
479
480/* TMDS Clock Enable, default value: 0x00 */
481#define REG_TMDS_CLK_EN 0x0211
482#define BIT_TMDS_CLK_EN_CLK_EN BIT(0)
483
484/* TMDS Channel Enable, default value: 0x00 */
485#define REG_TMDS_CH_EN 0x0212
486#define BIT_TMDS_CH_EN_CH0_EN BIT(4)
487#define BIT_TMDS_CH_EN_CH12_EN BIT(0)
488
489/* BGR_BIAS, default value: 0x07 */
490#define REG_BGR_BIAS 0x0215
491#define BIT_BGR_BIAS_BGR_EN BIT(7)
492#define MSK_BGR_BIAS_BIAS_BGR_D 0x0f
493
494/* TMDS 0 Digital I2C BW, default value: 0x0a */
495#define REG_ALICE0_BW_I2C 0x0231
496
497/* TMDS 0 Digital Zone Control, default value: 0xe0 */
498#define REG_ALICE0_ZONE_CTRL 0x024c
499#define BIT_ALICE0_ZONE_CTRL_ICRST_N BIT(7)
500#define BIT_ALICE0_ZONE_CTRL_USE_INT_DIV20 BIT(6)
501#define MSK_ALICE0_ZONE_CTRL_SZONE_I2C 0x30
502#define MSK_ALICE0_ZONE_CTRL_ZONE_CTRL 0x0f
503
504/* TMDS 0 Digital PLL Mode Control, default value: 0x00 */
505#define REG_ALICE0_MODE_CTRL 0x024d
506#define MSK_ALICE0_MODE_CTRL_PLL_MODE_I2C 0x0c
507#define MSK_ALICE0_MODE_CTRL_DIV20_CTRL 0x03
508
509/* MHL Tx Control 6th, default value: 0xa0 */
510#define REG_MHLTX_CTL6 0x0285
511#define MSK_MHLTX_CTL6_EMI_SEL 0xe0
512#define MSK_MHLTX_CTL6_TX_CLK_SHAPE_9_8 0x03
513
514/* Packet Filter0, default value: 0x00 */
515#define REG_PKT_FILTER_0 0x0290
516#define BIT_PKT_FILTER_0_DROP_CEA_GAMUT_PKT BIT(7)
517#define BIT_PKT_FILTER_0_DROP_CEA_CP_PKT BIT(6)
518#define BIT_PKT_FILTER_0_DROP_MPEG_PKT BIT(5)
519#define BIT_PKT_FILTER_0_DROP_SPIF_PKT BIT(4)
520#define BIT_PKT_FILTER_0_DROP_AIF_PKT BIT(3)
521#define BIT_PKT_FILTER_0_DROP_AVI_PKT BIT(2)
522#define BIT_PKT_FILTER_0_DROP_CTS_PKT BIT(1)
523#define BIT_PKT_FILTER_0_DROP_GCP_PKT BIT(0)
524
525/* Packet Filter1, default value: 0x00 */
526#define REG_PKT_FILTER_1 0x0291
527#define BIT_PKT_FILTER_1_VSI_OVERRIDE_DIS BIT(7)
528#define BIT_PKT_FILTER_1_AVI_OVERRIDE_DIS BIT(6)
529#define BIT_PKT_FILTER_1_DROP_AUDIO_PKT BIT(3)
530#define BIT_PKT_FILTER_1_DROP_GEN2_PKT BIT(2)
531#define BIT_PKT_FILTER_1_DROP_GEN_PKT BIT(1)
532#define BIT_PKT_FILTER_1_DROP_VSIF_PKT BIT(0)
533
534/* TMDS Clock Status, default value: 0x10 */
535#define REG_TMDS_CSTAT_P3 0x02a0
536#define BIT_TMDS_CSTAT_P3_RX_HDMI_CP_CLR_MUTE BIT(7)
537#define BIT_TMDS_CSTAT_P3_RX_HDMI_CP_SET_MUTE BIT(6)
538#define BIT_TMDS_CSTAT_P3_RX_HDMI_CP_NEW_CP BIT(5)
539#define BIT_TMDS_CSTAT_P3_CLR_AVI BIT(3)
540#define BIT_TMDS_CSTAT_P3_SCDT_CLR_AVI_DIS BIT(2)
541#define BIT_TMDS_CSTAT_P3_SCDT BIT(1)
542#define BIT_TMDS_CSTAT_P3_CKDT BIT(0)
543
544/* RX_HDMI Control, default value: 0x10 */
545#define REG_RX_HDMI_CTRL0 0x02a1
546#define BIT_RX_HDMI_CTRL0_BYP_DVIFILT_SYNC BIT(5)
547#define BIT_RX_HDMI_CTRL0_HDMI_MODE_EN_ITSELF_CLR BIT(4)
548#define BIT_RX_HDMI_CTRL0_HDMI_MODE_SW_VALUE BIT(3)
549#define BIT_RX_HDMI_CTRL0_HDMI_MODE_OVERWRITE BIT(2)
550#define BIT_RX_HDMI_CTRL0_RX_HDMI_HDMI_MODE_EN BIT(1)
551#define BIT_RX_HDMI_CTRL0_RX_HDMI_HDMI_MODE BIT(0)
552
553/* RX_HDMI Control, default value: 0x38 */
554#define REG_RX_HDMI_CTRL2 0x02a3
555#define MSK_RX_HDMI_CTRL2_IDLE_CNT 0xf0
556#define VAL_RX_HDMI_CTRL2_IDLE_CNT(n) ((n) << 4)
557#define BIT_RX_HDMI_CTRL2_USE_AV_MUTE BIT(3)
558#define BIT_RX_HDMI_CTRL2_VSI_MON_SEL_VSI BIT(0)
559
560/* RX_HDMI Control, default value: 0x0f */
561#define REG_RX_HDMI_CTRL3 0x02a4
562#define MSK_RX_HDMI_CTRL3_PP_MODE_CLK_EN 0x0f
563
564/* rx_hdmi Clear Buffer, default value: 0x00 */
565#define REG_RX_HDMI_CLR_BUFFER 0x02ac
566#define MSK_RX_HDMI_CLR_BUFFER_AIF4VSI_CMP 0xc0
567#define BIT_RX_HDMI_CLR_BUFFER_USE_AIF4VSI BIT(5)
568#define BIT_RX_HDMI_CLR_BUFFER_VSI_CLR_W_AVI BIT(4)
569#define BIT_RX_HDMI_CLR_BUFFER_VSI_IEEE_ID_CHK_EN BIT(3)
570#define BIT_RX_HDMI_CLR_BUFFER_SWAP_VSI_IEEE_ID BIT(2)
571#define BIT_RX_HDMI_CLR_BUFFER_AIF_CLR_EN BIT(1)
572#define BIT_RX_HDMI_CLR_BUFFER_VSI_CLR_EN BIT(0)
573
574/* RX_HDMI VSI Header1, default value: 0x00 */
575#define REG_RX_HDMI_MON_PKT_HEADER1 0x02b8
576
577/* RX_HDMI VSI MHL Monitor, default value: 0x3c */
578#define REG_RX_HDMI_VSIF_MHL_MON 0x02d7
579
580#define MSK_RX_HDMI_VSIF_MHL_MON_RX_HDMI_MHL_3D_FORMAT 0x3c
581#define MSK_RX_HDMI_VSIF_MHL_MON_RX_HDMI_MHL_VID_FORMAT 0x03
582
583/* Interrupt Source 9, default value: 0x00 */
584#define REG_INTR9 0x02e0
585#define BIT_INTR9_EDID_ERROR BIT(6)
586#define BIT_INTR9_EDID_DONE BIT(5)
587#define BIT_INTR9_DEVCAP_DONE BIT(4)
588
589/* Interrupt 9 Mask, default value: 0x00 */
590#define REG_INTR9_MASK 0x02e1
591
592/* TPI CBUS Start, default value: 0x00 */
593#define REG_TPI_CBUS_START 0x02e2
594#define BIT_TPI_CBUS_START_RCP_REQ_START BIT(7)
595#define BIT_TPI_CBUS_START_RCPK_REPLY_START BIT(6)
596#define BIT_TPI_CBUS_START_RCPE_REPLY_START BIT(5)
597#define BIT_TPI_CBUS_START_PUT_LINK_MODE_START BIT(4)
598#define BIT_TPI_CBUS_START_PUT_DCAPCHG_START BIT(3)
599#define BIT_TPI_CBUS_START_PUT_DCAPRDY_START BIT(2)
600#define BIT_TPI_CBUS_START_GET_EDID_START_0 BIT(1)
601#define BIT_TPI_CBUS_START_GET_DEVCAP_START BIT(0)
602
603/* EDID Control, default value: 0x10 */
604#define REG_EDID_CTRL 0x02e3
605#define BIT_EDID_CTRL_EDID_PRIME_VALID BIT(7)
606#define BIT_EDID_CTRL_XDEVCAP_EN BIT(6)
607#define BIT_EDID_CTRL_DEVCAP_SELECT_DEVCAP BIT(5)
608#define BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO BIT(4)
609#define BIT_EDID_CTRL_EDID_FIFO_ACCESS_ALWAYS_EN BIT(3)
610#define BIT_EDID_CTRL_EDID_FIFO_BLOCK_SEL BIT(2)
611#define BIT_EDID_CTRL_INVALID_BKSV BIT(1)
612#define BIT_EDID_CTRL_EDID_MODE_EN BIT(0)
613
614/* EDID FIFO Addr, default value: 0x00 */
615#define REG_EDID_FIFO_ADDR 0x02e9
616
617/* EDID FIFO Write Data, default value: 0x00 */
618#define REG_EDID_FIFO_WR_DATA 0x02ea
619
620/* EDID/DEVCAP FIFO Internal Addr, default value: 0x00 */
621#define REG_EDID_FIFO_ADDR_MON 0x02eb
622
623/* EDID FIFO Read Data, default value: 0x00 */
624#define REG_EDID_FIFO_RD_DATA 0x02ec
625
626/* EDID DDC Segment Pointer, default value: 0x00 */
627#define REG_EDID_START_EXT 0x02ed
628
629/* TX IP BIST CNTL and Status, default value: 0x00 */
630#define REG_TX_IP_BIST_CNTLSTA 0x02f2
631#define BIT_TX_IP_BIST_CNTLSTA_TXBIST_QUARTER_CLK_SEL BIT(6)
632#define BIT_TX_IP_BIST_CNTLSTA_TXBIST_DONE BIT(5)
633#define BIT_TX_IP_BIST_CNTLSTA_TXBIST_ON BIT(4)
634#define BIT_TX_IP_BIST_CNTLSTA_TXBIST_RUN BIT(3)
635#define BIT_TX_IP_BIST_CNTLSTA_TXCLK_HALF_SEL BIT(2)
636#define BIT_TX_IP_BIST_CNTLSTA_TXBIST_EN BIT(1)
637#define BIT_TX_IP_BIST_CNTLSTA_TXBIST_SEL BIT(0)
638
639/* TX IP BIST INST LOW, default value: 0x00 */
640#define REG_TX_IP_BIST_INST_LOW 0x02f3
641#define REG_TX_IP_BIST_INST_HIGH 0x02f4
642
643/* TX IP BIST PATTERN LOW, default value: 0x00 */
644#define REG_TX_IP_BIST_PAT_LOW 0x02f5
645#define REG_TX_IP_BIST_PAT_HIGH 0x02f6
646
647/* TX IP BIST CONFIGURE LOW, default value: 0x00 */
648#define REG_TX_IP_BIST_CONF_LOW 0x02f7
649#define REG_TX_IP_BIST_CONF_HIGH 0x02f8
650
651/* E-MSC General Control, default value: 0x80 */
652#define REG_GENCTL 0x0300
653#define BIT_GENCTL_SPEC_TRANS_DIS BIT(7)
654#define BIT_GENCTL_DIS_XMIT_ERR_STATE BIT(6)
655#define BIT_GENCTL_SPI_MISO_EDGE BIT(5)
656#define BIT_GENCTL_SPI_MOSI_EDGE BIT(4)
657#define BIT_GENCTL_CLR_EMSC_RFIFO BIT(3)
658#define BIT_GENCTL_CLR_EMSC_XFIFO BIT(2)
659#define BIT_GENCTL_START_TRAIN_SEQ BIT(1)
660#define BIT_GENCTL_EMSC_EN BIT(0)
661
662/* E-MSC Comma ErrorCNT, default value: 0x03 */
663#define REG_COMMECNT 0x0305
664#define BIT_COMMECNT_I2C_TO_EMSC_EN BIT(7)
665#define MSK_COMMECNT_COMMA_CHAR_ERR_CNT 0x0f
666
667/* E-MSC RFIFO ByteCnt, default value: 0x00 */
668#define REG_EMSCRFIFOBCNTL 0x031a
669#define REG_EMSCRFIFOBCNTH 0x031b
670
671/* SPI Burst Cnt Status, default value: 0x00 */
672#define REG_SPIBURSTCNT 0x031e
673
674/* SPI Burst Status and SWRST, default value: 0x00 */
675#define REG_SPIBURSTSTAT 0x0322
676#define BIT_SPIBURSTSTAT_SPI_HDCPRST BIT(7)
677#define BIT_SPIBURSTSTAT_SPI_CBUSRST BIT(6)
678#define BIT_SPIBURSTSTAT_SPI_SRST BIT(5)
679#define BIT_SPIBURSTSTAT_EMSC_NORMAL_MODE BIT(0)
680
681/* E-MSC 1st Interrupt, default value: 0x00 */
682#define REG_EMSCINTR 0x0323
683#define BIT_EMSCINTR_EMSC_XFIFO_EMPTY BIT(7)
684#define BIT_EMSCINTR_EMSC_XMIT_ACK_TOUT BIT(6)
685#define BIT_EMSCINTR_EMSC_RFIFO_READ_ERR BIT(5)
686#define BIT_EMSCINTR_EMSC_XFIFO_WRITE_ERR BIT(4)
687#define BIT_EMSCINTR_EMSC_COMMA_CHAR_ERR BIT(3)
688#define BIT_EMSCINTR_EMSC_XMIT_DONE BIT(2)
689#define BIT_EMSCINTR_EMSC_XMIT_GNT_TOUT BIT(1)
690#define BIT_EMSCINTR_SPI_DVLD BIT(0)
691
692/* E-MSC Interrupt Mask, default value: 0x00 */
693#define REG_EMSCINTRMASK 0x0324
694
695/* I2C E-MSC XMIT FIFO Write Port, default value: 0x00 */
696#define REG_EMSC_XMIT_WRITE_PORT 0x032a
697
698/* I2C E-MSC RCV FIFO Write Port, default value: 0x00 */
699#define REG_EMSC_RCV_READ_PORT 0x032b
700
701/* E-MSC 2nd Interrupt, default value: 0x00 */
702#define REG_EMSCINTR1 0x032c
703#define BIT_EMSCINTR1_EMSC_TRAINING_COMMA_ERR BIT(0)
704
705/* E-MSC Interrupt Mask, default value: 0x00 */
706#define REG_EMSCINTRMASK1 0x032d
707#define BIT_EMSCINTRMASK1_EMSC_INTRMASK1_0 BIT(0)
708
709/* MHL Top Ctl, default value: 0x00 */
710#define REG_MHL_TOP_CTL 0x0330
711#define BIT_MHL_TOP_CTL_MHL3_DOC_SEL BIT(7)
712#define BIT_MHL_TOP_CTL_MHL_PP_SEL BIT(6)
713#define MSK_MHL_TOP_CTL_IF_TIMING_CTL 0x03
714
715/* MHL DataPath 1st Ctl, default value: 0xbc */
716#define REG_MHL_DP_CTL0 0x0331
717#define BIT_MHL_DP_CTL0_DP_OE BIT(7)
718#define BIT_MHL_DP_CTL0_TX_OE_OVR BIT(6)
719#define MSK_MHL_DP_CTL0_TX_OE 0x3f
720
721/* MHL DataPath 2nd Ctl, default value: 0xbb */
722#define REG_MHL_DP_CTL1 0x0332
723#define MSK_MHL_DP_CTL1_CK_SWING_CTL 0xf0
724#define MSK_MHL_DP_CTL1_DT_SWING_CTL 0x0f
725
726/* MHL DataPath 3rd Ctl, default value: 0x2f */
727#define REG_MHL_DP_CTL2 0x0333
728#define BIT_MHL_DP_CTL2_CLK_BYPASS_EN BIT(7)
729#define MSK_MHL_DP_CTL2_DAMP_TERM_SEL 0x30
730#define MSK_MHL_DP_CTL2_CK_TERM_SEL 0x0c
731#define MSK_MHL_DP_CTL2_DT_TERM_SEL 0x03
732
733/* MHL DataPath 4th Ctl, default value: 0x48 */
734#define REG_MHL_DP_CTL3 0x0334
735#define MSK_MHL_DP_CTL3_DT_DRV_VNBC_CTL 0xf0
736#define MSK_MHL_DP_CTL3_DT_DRV_VNB_CTL 0x0f
737
738/* MHL DataPath 5th Ctl, default value: 0x48 */
739#define REG_MHL_DP_CTL4 0x0335
740#define MSK_MHL_DP_CTL4_CK_DRV_VNBC_CTL 0xf0
741#define MSK_MHL_DP_CTL4_CK_DRV_VNB_CTL 0x0f
742
743/* MHL DataPath 6th Ctl, default value: 0x3f */
744#define REG_MHL_DP_CTL5 0x0336
745#define BIT_MHL_DP_CTL5_RSEN_EN_OVR BIT(7)
746#define BIT_MHL_DP_CTL5_RSEN_EN BIT(6)
747#define MSK_MHL_DP_CTL5_DAMP_TERM_VGS_CTL 0x30
748#define MSK_MHL_DP_CTL5_CK_TERM_VGS_CTL 0x0c
749#define MSK_MHL_DP_CTL5_DT_TERM_VGS_CTL 0x03
750
751/* MHL PLL 1st Ctl, default value: 0x05 */
752#define REG_MHL_PLL_CTL0 0x0337
753#define BIT_MHL_PLL_CTL0_AUD_CLK_EN BIT(7)
754
755#define MSK_MHL_PLL_CTL0_AUD_CLK_RATIO 0x70
756#define VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_10 0x70
757#define VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_6 0x60
758#define VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_4 0x50
759#define VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_2 0x40
760#define VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_5 0x30
761#define VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_3 0x20
762#define VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_2_PRIME 0x10
763#define VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_1 0x00
764
765#define MSK_MHL_PLL_CTL0_HDMI_CLK_RATIO 0x0c
766#define VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_4X 0x0c
767#define VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_2X 0x08
768#define VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X 0x04
769#define VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_HALF_X 0x00
770
771#define BIT_MHL_PLL_CTL0_CRYSTAL_CLK_SEL BIT(1)
772#define BIT_MHL_PLL_CTL0_ZONE_MASK_OE BIT(0)
773
774/* MHL PLL 3rd Ctl, default value: 0x80 */
775#define REG_MHL_PLL_CTL2 0x0339
776#define BIT_MHL_PLL_CTL2_CLKDETECT_EN BIT(7)
777#define BIT_MHL_PLL_CTL2_MEAS_FVCO BIT(3)
778#define BIT_MHL_PLL_CTL2_PLL_FAST_LOCK BIT(2)
779#define MSK_MHL_PLL_CTL2_PLL_LF_SEL 0x03
780
781/* MHL CBUS 1st Ctl, default value: 0x12 */
782#define REG_MHL_CBUS_CTL0 0x0340
783#define BIT_MHL_CBUS_CTL0_CBUS_RGND_TEST_MODE BIT(7)
784
785#define MSK_MHL_CBUS_CTL0_CBUS_RGND_VTH_CTL 0x30
786#define VAL_MHL_CBUS_CTL0_CBUS_RGND_VBIAS_734 0x00
787#define VAL_MHL_CBUS_CTL0_CBUS_RGND_VBIAS_747 0x10
788#define VAL_MHL_CBUS_CTL0_CBUS_RGND_VBIAS_740 0x20
789#define VAL_MHL_CBUS_CTL0_CBUS_RGND_VBIAS_754 0x30
790
791#define MSK_MHL_CBUS_CTL0_CBUS_RES_TEST_SEL 0x0c
792
793#define MSK_MHL_CBUS_CTL0_CBUS_DRV_SEL 0x03
794#define VAL_MHL_CBUS_CTL0_CBUS_DRV_SEL_WEAKEST 0x00
795#define VAL_MHL_CBUS_CTL0_CBUS_DRV_SEL_WEAK 0x01
796#define VAL_MHL_CBUS_CTL0_CBUS_DRV_SEL_STRONG 0x02
797#define VAL_MHL_CBUS_CTL0_CBUS_DRV_SEL_STRONGEST 0x03
798
799/* MHL CBUS 2nd Ctl, default value: 0x03 */
800#define REG_MHL_CBUS_CTL1 0x0341
801#define MSK_MHL_CBUS_CTL1_CBUS_RGND_RES_CTL 0x07
802#define VAL_MHL_CBUS_CTL1_0888_OHM 0x00
803#define VAL_MHL_CBUS_CTL1_1115_OHM 0x04
804#define VAL_MHL_CBUS_CTL1_1378_OHM 0x07
805
806/* MHL CoC 1st Ctl, default value: 0xc3 */
807#define REG_MHL_COC_CTL0 0x0342
808#define BIT_MHL_COC_CTL0_COC_BIAS_EN BIT(7)
809#define MSK_MHL_COC_CTL0_COC_BIAS_CTL 0x70
810#define MSK_MHL_COC_CTL0_COC_TERM_CTL 0x07
811
812/* MHL CoC 2nd Ctl, default value: 0x87 */
813#define REG_MHL_COC_CTL1 0x0343
814#define BIT_MHL_COC_CTL1_COC_EN BIT(7)
815#define MSK_MHL_COC_CTL1_COC_DRV_CTL 0x3f
816
817/* MHL CoC 4th Ctl, default value: 0x00 */
818#define REG_MHL_COC_CTL3 0x0345
819#define BIT_MHL_COC_CTL3_COC_AECHO_EN BIT(0)
820
821/* MHL CoC 5th Ctl, default value: 0x28 */
822#define REG_MHL_COC_CTL4 0x0346
823#define MSK_MHL_COC_CTL4_COC_IF_CTL 0xf0
824#define MSK_MHL_COC_CTL4_COC_SLEW_CTL 0x0f
825
826/* MHL CoC 6th Ctl, default value: 0x0d */
827#define REG_MHL_COC_CTL5 0x0347
828
829/* MHL DoC 1st Ctl, default value: 0x18 */
830#define REG_MHL_DOC_CTL0 0x0349
831#define BIT_MHL_DOC_CTL0_DOC_RXDATA_EN BIT(7)
832#define MSK_MHL_DOC_CTL0_DOC_DM_TERM 0x38
833#define MSK_MHL_DOC_CTL0_DOC_OPMODE 0x06
834#define BIT_MHL_DOC_CTL0_DOC_RXBIAS_EN BIT(0)
835
836/* MHL DataPath 7th Ctl, default value: 0x2a */
837#define REG_MHL_DP_CTL6 0x0350
838#define BIT_MHL_DP_CTL6_DP_TAP2_SGN BIT(5)
839#define BIT_MHL_DP_CTL6_DP_TAP2_EN BIT(4)
840#define BIT_MHL_DP_CTL6_DP_TAP1_SGN BIT(3)
841#define BIT_MHL_DP_CTL6_DP_TAP1_EN BIT(2)
842#define BIT_MHL_DP_CTL6_DT_PREDRV_FEEDCAP_EN BIT(1)
843#define BIT_MHL_DP_CTL6_DP_PRE_POST_SEL BIT(0)
844
845/* MHL DataPath 8th Ctl, default value: 0x06 */
846#define REG_MHL_DP_CTL7 0x0351
847#define MSK_MHL_DP_CTL7_DT_DRV_VBIAS_CASCTL 0xf0
848#define MSK_MHL_DP_CTL7_DT_DRV_IREF_CTL 0x0f
849
850#define REG_MHL_DP_CTL8 0x0352
851
852/* Tx Zone Ctl1, default value: 0x00 */
853#define REG_TX_ZONE_CTL1 0x0361
854#define VAL_TX_ZONE_CTL1_TX_ZONE_CTRL_MODE 0x08
855
856/* MHL3 Tx Zone Ctl, default value: 0x00 */
857#define REG_MHL3_TX_ZONE_CTL 0x0364
858#define BIT_MHL3_TX_ZONE_CTL_MHL2_INTPLT_ZONE_MANU_EN BIT(7)
859#define MSK_MHL3_TX_ZONE_CTL_MHL3_TX_ZONE 0x03
860
861#define MSK_TX_ZONE_CTL3_TX_ZONE 0x03
862#define VAL_TX_ZONE_CTL3_TX_ZONE_6GBPS 0x00
863#define VAL_TX_ZONE_CTL3_TX_ZONE_3GBPS 0x01
864#define VAL_TX_ZONE_CTL3_TX_ZONE_1_5GBPS 0x02
865
866/* HDCP Polling Control and Status, default value: 0x70 */
867#define REG_HDCP2X_POLL_CS 0x0391
868
869#define BIT_HDCP2X_POLL_CS_HDCP2X_MSG_SZ_CLR_OPTION BIT(6)
870#define BIT_HDCP2X_POLL_CS_HDCP2X_RPT_READY_CLR_OPTION BIT(5)
871#define BIT_HDCP2X_POLL_CS_HDCP2X_REAUTH_REQ_CLR_OPTION BIT(4)
872#define MSK_HDCP2X_POLL_CS_ 0x0c
873#define BIT_HDCP2X_POLL_CS_HDCP2X_DIS_POLL_GNT BIT(1)
874#define BIT_HDCP2X_POLL_CS_HDCP2X_DIS_POLL_EN BIT(0)
875
876/* HDCP Interrupt 0, default value: 0x00 */
877#define REG_HDCP2X_INTR0 0x0398
878
879/* HDCP Interrupt 0 Mask, default value: 0x00 */
880#define REG_HDCP2X_INTR0_MASK 0x0399
881
882/* HDCP General Control 0, default value: 0x02 */
883#define REG_HDCP2X_CTRL_0 0x03a0
884#define BIT_HDCP2X_CTRL_0_HDCP2X_ENCRYPT_EN BIT(7)
885#define BIT_HDCP2X_CTRL_0_HDCP2X_POLINT_SEL BIT(6)
886#define BIT_HDCP2X_CTRL_0_HDCP2X_POLINT_OVR BIT(5)
887#define BIT_HDCP2X_CTRL_0_HDCP2X_PRECOMPUTE BIT(4)
888#define BIT_HDCP2X_CTRL_0_HDCP2X_HDMIMODE BIT(3)
889#define BIT_HDCP2X_CTRL_0_HDCP2X_REPEATER BIT(2)
890#define BIT_HDCP2X_CTRL_0_HDCP2X_HDCPTX BIT(1)
891#define BIT_HDCP2X_CTRL_0_HDCP2X_EN BIT(0)
892
893/* HDCP General Control 1, default value: 0x08 */
894#define REG_HDCP2X_CTRL_1 0x03a1
895#define MSK_HDCP2X_CTRL_1_HDCP2X_REAUTH_MSK_3_0 0xf0
896#define BIT_HDCP2X_CTRL_1_HDCP2X_HPD_SW BIT(3)
897#define BIT_HDCP2X_CTRL_1_HDCP2X_HPD_OVR BIT(2)
898#define BIT_HDCP2X_CTRL_1_HDCP2X_CTL3MSK BIT(1)
899#define BIT_HDCP2X_CTRL_1_HDCP2X_REAUTH_SW BIT(0)
900
901/* HDCP Misc Control, default value: 0x00 */
902#define REG_HDCP2X_MISC_CTRL 0x03a5
903#define BIT_HDCP2X_MISC_CTRL_HDCP2X_RPT_SMNG_XFER_START BIT(4)
904#define BIT_HDCP2X_MISC_CTRL_HDCP2X_RPT_SMNG_WR_START BIT(3)
905#define BIT_HDCP2X_MISC_CTRL_HDCP2X_RPT_SMNG_WR BIT(2)
906#define BIT_HDCP2X_MISC_CTRL_HDCP2X_RPT_RCVID_RD_START BIT(1)
907#define BIT_HDCP2X_MISC_CTRL_HDCP2X_RPT_RCVID_RD BIT(0)
908
909/* HDCP RPT SMNG K, default value: 0x00 */
910#define REG_HDCP2X_RPT_SMNG_K 0x03a6
911
912/* HDCP RPT SMNG In, default value: 0x00 */
913#define REG_HDCP2X_RPT_SMNG_IN 0x03a7
914
915/* HDCP Auth Status, default value: 0x00 */
916#define REG_HDCP2X_AUTH_STAT 0x03aa
917
918/* HDCP RPT RCVID Out, default value: 0x00 */
919#define REG_HDCP2X_RPT_RCVID_OUT 0x03ac
920
921/* HDCP TP1, default value: 0x62 */
922#define REG_HDCP2X_TP1 0x03b4
923
924/* HDCP GP Out 0, default value: 0x00 */
925#define REG_HDCP2X_GP_OUT0 0x03c7
926
927/* HDCP Repeater RCVR ID 0, default value: 0x00 */
928#define REG_HDCP2X_RPT_RCVR_ID0 0x03d1
929
930/* HDCP DDCM Status, default value: 0x00 */
931#define REG_HDCP2X_DDCM_STS 0x03d8
932#define MSK_HDCP2X_DDCM_STS_HDCP2X_DDCM_ERR_STS_3_0 0xf0
933#define MSK_HDCP2X_DDCM_STS_HDCP2X_DDCM_CTL_CS_3_0 0x0f
934
935/* HDMI2MHL3 Control, default value: 0x0a */
936#define REG_M3_CTRL 0x03e0
937#define BIT_M3_CTRL_H2M_SWRST BIT(4)
938#define BIT_M3_CTRL_SW_MHL3_SEL BIT(3)
939#define BIT_M3_CTRL_M3AV_EN BIT(2)
940#define BIT_M3_CTRL_ENC_TMDS BIT(1)
941#define BIT_M3_CTRL_MHL3_MASTER_EN BIT(0)
942
943#define VAL_M3_CTRL_MHL1_2_VALUE (BIT_M3_CTRL_SW_MHL3_SEL \
944 | BIT_M3_CTRL_ENC_TMDS)
945#define VAL_M3_CTRL_MHL3_VALUE (BIT_M3_CTRL_SW_MHL3_SEL \
946 | BIT_M3_CTRL_M3AV_EN \
947 | BIT_M3_CTRL_ENC_TMDS \
948 | BIT_M3_CTRL_MHL3_MASTER_EN)
949
950/* HDMI2MHL3 Port0 Control, default value: 0x04 */
951#define REG_M3_P0CTRL 0x03e1
952#define BIT_M3_P0CTRL_MHL3_P0_HDCP_ENC_EN BIT(4)
953#define BIT_M3_P0CTRL_MHL3_P0_UNLIMIT_EN BIT(3)
954#define BIT_M3_P0CTRL_MHL3_P0_HDCP_EN BIT(2)
955#define BIT_M3_P0CTRL_MHL3_P0_PIXEL_MODE_PACKED BIT(1)
956#define BIT_M3_P0CTRL_MHL3_P0_PORT_EN BIT(0)
957
958#define REG_M3_POSTM 0x03e2
959#define MSK_M3_POSTM_RRP_DECODE 0xf8
960#define MSK_M3_POSTM_MHL3_P0_STM_ID 0x07
961
962/* HDMI2MHL3 Scramble Control, default value: 0x41 */
963#define REG_M3_SCTRL 0x03e6
964#define MSK_M3_SCTRL_MHL3_SR_LENGTH 0xf0
965#define BIT_M3_SCTRL_MHL3_SCRAMBLER_EN BIT(0)
966
967/* HSIC Div Ctl, default value: 0x05 */
968#define REG_DIV_CTL_MAIN 0x03f2
969#define MSK_DIV_CTL_MAIN_PRE_DIV_CTL_MAIN 0x1c
970#define MSK_DIV_CTL_MAIN_FB_DIV_CTL_MAIN 0x03
971
972/* MHL Capability 1st Byte, default value: 0x00 */
973#define REG_MHL_DEVCAP_0 0x0400
974
975/* MHL Interrupt 1st Byte, default value: 0x00 */
976#define REG_MHL_INT_0 0x0420
977
978/* Device Status 1st byte, default value: 0x00 */
979#define REG_MHL_STAT_0 0x0430
980
981/* CBUS Scratch Pad 1st Byte, default value: 0x00 */
982#define REG_MHL_SCRPAD_0 0x0440
983
984/* MHL Extended Capability 1st Byte, default value: 0x00 */
985#define REG_MHL_EXTDEVCAP_0 0x0480
986
987/* Device Extended Status 1st byte, default value: 0x00 */
988#define REG_MHL_EXTSTAT_0 0x0490
989
990/* TPI DTD Byte2, default value: 0x00 */
991#define REG_TPI_DTD_B2 0x0602
992
993#define VAL_TPI_QUAN_RANGE_LIMITED 0x01
994#define VAL_TPI_QUAN_RANGE_FULL 0x02
995#define VAL_TPI_FORMAT_RGB 0x00
996#define VAL_TPI_FORMAT_YCBCR444 0x01
997#define VAL_TPI_FORMAT_YCBCR422 0x02
998#define VAL_TPI_FORMAT_INTERNAL_RGB 0x03
999#define VAL_TPI_FORMAT(_fmt, _qr) \
1000 (VAL_TPI_FORMAT_##_fmt | (VAL_TPI_QUAN_RANGE_##_qr << 2))
1001
1002/* Input Format, default value: 0x00 */
1003#define REG_TPI_INPUT 0x0609
1004#define BIT_TPI_INPUT_EXTENDEDBITMODE BIT(7)
1005#define BIT_TPI_INPUT_ENDITHER BIT(6)
1006#define MSK_TPI_INPUT_INPUT_QUAN_RANGE 0x0c
1007#define MSK_TPI_INPUT_INPUT_FORMAT 0x03
1008
1009/* Output Format, default value: 0x00 */
1010#define REG_TPI_OUTPUT 0x060a
1011#define BIT_TPI_OUTPUT_CSCMODE709 BIT(4)
1012#define MSK_TPI_OUTPUT_OUTPUT_QUAN_RANGE 0x0c
1013#define MSK_TPI_OUTPUT_OUTPUT_FORMAT 0x03
1014
1015/* TPI AVI Check Sum, default value: 0x00 */
1016#define REG_TPI_AVI_CHSUM 0x060c
1017
1018/* TPI System Control, default value: 0x00 */
1019#define REG_TPI_SC 0x061a
1020#define BIT_TPI_SC_TPI_UPDATE_FLG BIT(7)
1021#define BIT_TPI_SC_TPI_REAUTH_CTL BIT(6)
1022#define BIT_TPI_SC_TPI_OUTPUT_MODE_1 BIT(5)
1023#define BIT_TPI_SC_REG_TMDS_OE_POWER_DOWN BIT(4)
1024#define BIT_TPI_SC_TPI_AV_MUTE BIT(3)
1025#define BIT_TPI_SC_DDC_GPU_REQUEST BIT(2)
1026#define BIT_TPI_SC_DDC_TPI_SW BIT(1)
1027#define BIT_TPI_SC_TPI_OUTPUT_MODE_0_HDMI BIT(0)
1028
1029/* TPI COPP Query Data, default value: 0x00 */
1030#define REG_TPI_COPP_DATA1 0x0629
1031#define BIT_TPI_COPP_DATA1_COPP_GPROT BIT(7)
1032#define BIT_TPI_COPP_DATA1_COPP_LPROT BIT(6)
1033#define MSK_TPI_COPP_DATA1_COPP_LINK_STATUS 0x30
1034#define VAL_TPI_COPP_LINK_STATUS_NORMAL 0x00
1035#define VAL_TPI_COPP_LINK_STATUS_LINK_LOST 0x10
1036#define VAL_TPI_COPP_LINK_STATUS_RENEGOTIATION_REQ 0x20
1037#define VAL_TPI_COPP_LINK_STATUS_LINK_SUSPENDED 0x30
1038#define BIT_TPI_COPP_DATA1_COPP_HDCP_REP BIT(3)
1039#define BIT_TPI_COPP_DATA1_COPP_CONNTYPE_0 BIT(2)
1040#define BIT_TPI_COPP_DATA1_COPP_PROTYPE BIT(1)
1041#define BIT_TPI_COPP_DATA1_COPP_CONNTYPE_1 BIT(0)
1042
1043/* TPI COPP Control Data, default value: 0x00 */
1044#define REG_TPI_COPP_DATA2 0x062a
1045#define BIT_TPI_COPP_DATA2_INTR_ENCRYPTION BIT(5)
1046#define BIT_TPI_COPP_DATA2_KSV_FORWARD BIT(4)
1047#define BIT_TPI_COPP_DATA2_INTERM_RI_CHECK_EN BIT(3)
1048#define BIT_TPI_COPP_DATA2_DOUBLE_RI_CHECK BIT(2)
1049#define BIT_TPI_COPP_DATA2_DDC_SHORT_RI_RD BIT(1)
1050#define BIT_TPI_COPP_DATA2_COPP_PROTLEVEL BIT(0)
1051
1052/* TPI Interrupt Enable, default value: 0x00 */
1053#define REG_TPI_INTR_EN 0x063c
1054
1055/* TPI Interrupt Status Low Byte, default value: 0x00 */
1056#define REG_TPI_INTR_ST0 0x063d
1057#define BIT_TPI_INTR_ST0_TPI_AUTH_CHNGE_STAT BIT(7)
1058#define BIT_TPI_INTR_ST0_TPI_V_RDY_STAT BIT(6)
1059#define BIT_TPI_INTR_ST0_TPI_COPP_CHNGE_STAT BIT(5)
1060#define BIT_TPI_INTR_ST0_KSV_FIFO_FIRST_STAT BIT(3)
1061#define BIT_TPI_INTR_ST0_READ_BKSV_BCAPS_DONE_STAT BIT(2)
1062#define BIT_TPI_INTR_ST0_READ_BKSV_BCAPS_ERR_STAT BIT(1)
1063#define BIT_TPI_INTR_ST0_READ_BKSV_ERR_STAT BIT(0)
1064
1065/* TPI DS BCAPS Status, default value: 0x00 */
1066#define REG_TPI_DS_BCAPS 0x0644
1067
1068/* TPI BStatus1, default value: 0x00 */
1069#define REG_TPI_BSTATUS1 0x0645
1070#define BIT_TPI_BSTATUS1_DS_DEV_EXCEED BIT(7)
1071#define MSK_TPI_BSTATUS1_DS_DEV_CNT 0x7f
1072
1073/* TPI BStatus2, default value: 0x10 */
1074#define REG_TPI_BSTATUS2 0x0646
1075#define MSK_TPI_BSTATUS2_DS_BSTATUS 0xe0
1076#define BIT_TPI_BSTATUS2_DS_HDMI_MODE BIT(4)
1077#define BIT_TPI_BSTATUS2_DS_CASC_EXCEED BIT(3)
1078#define MSK_TPI_BSTATUS2_DS_DEPTH 0x07
1079
1080/* TPI HW Optimization Control #3, default value: 0x00 */
1081#define REG_TPI_HW_OPT3 0x06bb
1082#define BIT_TPI_HW_OPT3_DDC_DEBUG BIT(7)
1083#define BIT_TPI_HW_OPT3_RI_CHECK_SKIP BIT(3)
1084#define BIT_TPI_HW_OPT3_TPI_DDC_BURST_MODE BIT(2)
1085#define MSK_TPI_HW_OPT3_TPI_DDC_REQ_LEVEL 0x03
1086
1087/* TPI Info Frame Select, default value: 0x00 */
1088#define REG_TPI_INFO_FSEL 0x06bf
1089#define BIT_TPI_INFO_FSEL_EN BIT(7)
1090#define BIT_TPI_INFO_FSEL_RPT BIT(6)
1091#define BIT_TPI_INFO_FSEL_READ_FLAG BIT(5)
1092#define MSK_TPI_INFO_FSEL_PKT 0x07
1093#define VAL_TPI_INFO_FSEL_AVI 0x00
1094#define VAL_TPI_INFO_FSEL_SPD 0x01
1095#define VAL_TPI_INFO_FSEL_AUD 0x02
1096#define VAL_TPI_INFO_FSEL_MPG 0x03
1097#define VAL_TPI_INFO_FSEL_GEN 0x04
1098#define VAL_TPI_INFO_FSEL_GEN2 0x05
1099#define VAL_TPI_INFO_FSEL_VSI 0x06
1100
1101/* TPI Info Byte #0, default value: 0x00 */
1102#define REG_TPI_INFO_B0 0x06c0
1103
1104/* CoC Status, default value: 0x00 */
1105#define REG_COC_STAT_0 0x0700
1106#define BIT_COC_STAT_0_PLL_LOCKED BIT(7)
1107#define MSK_COC_STAT_0_FSM_STATE 0x0f
1108
1109#define REG_COC_STAT_1 0x0701
1110#define REG_COC_STAT_2 0x0702
1111#define REG_COC_STAT_3 0x0703
1112#define REG_COC_STAT_4 0x0704
1113#define REG_COC_STAT_5 0x0705
1114
1115/* CoC 1st Ctl, default value: 0x40 */
1116#define REG_COC_CTL0 0x0710
1117
1118/* CoC 2nd Ctl, default value: 0x0a */
1119#define REG_COC_CTL1 0x0711
1120#define MSK_COC_CTL1_COC_CTRL1_7_6 0xc0
1121#define MSK_COC_CTL1_COC_CTRL1_5_0 0x3f
1122
1123/* CoC 3rd Ctl, default value: 0x14 */
1124#define REG_COC_CTL2 0x0712
1125#define MSK_COC_CTL2_COC_CTRL2_7_6 0xc0
1126#define MSK_COC_CTL2_COC_CTRL2_5_0 0x3f
1127
1128/* CoC 4th Ctl, default value: 0x40 */
1129#define REG_COC_CTL3 0x0713
1130#define BIT_COC_CTL3_COC_CTRL3_7 BIT(7)
1131#define MSK_COC_CTL3_COC_CTRL3_6_0 0x7f
1132
1133/* CoC 7th Ctl, default value: 0x00 */
1134#define REG_COC_CTL6 0x0716
1135#define BIT_COC_CTL6_COC_CTRL6_7 BIT(7)
1136#define BIT_COC_CTL6_COC_CTRL6_6 BIT(6)
1137#define MSK_COC_CTL6_COC_CTRL6_5_0 0x3f
1138
1139/* CoC 8th Ctl, default value: 0x06 */
1140#define REG_COC_CTL7 0x0717
1141#define BIT_COC_CTL7_COC_CTRL7_7 BIT(7)
1142#define BIT_COC_CTL7_COC_CTRL7_6 BIT(6)
1143#define BIT_COC_CTL7_COC_CTRL7_5 BIT(5)
1144#define MSK_COC_CTL7_COC_CTRL7_4_3 0x18
1145#define MSK_COC_CTL7_COC_CTRL7_2_0 0x07
1146
1147/* CoC 10th Ctl, default value: 0x00 */
1148#define REG_COC_CTL9 0x0719
1149
1150/* CoC 11th Ctl, default value: 0x00 */
1151#define REG_COC_CTLA 0x071a
1152
1153/* CoC 12th Ctl, default value: 0x00 */
1154#define REG_COC_CTLB 0x071b
1155
1156/* CoC 13th Ctl, default value: 0x0f */
1157#define REG_COC_CTLC 0x071c
1158
1159/* CoC 14th Ctl, default value: 0x0a */
1160#define REG_COC_CTLD 0x071d
1161#define BIT_COC_CTLD_COC_CTRLD_7 BIT(7)
1162#define MSK_COC_CTLD_COC_CTRLD_6_0 0x7f
1163
1164/* CoC 15th Ctl, default value: 0x0a */
1165#define REG_COC_CTLE 0x071e
1166#define BIT_COC_CTLE_COC_CTRLE_7 BIT(7)
1167#define MSK_COC_CTLE_COC_CTRLE_6_0 0x7f
1168
1169/* CoC 16th Ctl, default value: 0x00 */
1170#define REG_COC_CTLF 0x071f
1171#define MSK_COC_CTLF_COC_CTRLF_7_3 0xf8
1172#define MSK_COC_CTLF_COC_CTRLF_2_0 0x07
1173
1174/* CoC 18th Ctl, default value: 0x32 */
1175#define REG_COC_CTL11 0x0721
1176#define MSK_COC_CTL11_COC_CTRL11_7_4 0xf0
1177#define MSK_COC_CTL11_COC_CTRL11_3_0 0x0f
1178
1179/* CoC 21st Ctl, default value: 0x00 */
1180#define REG_COC_CTL14 0x0724
1181#define MSK_COC_CTL14_COC_CTRL14_7_4 0xf0
1182#define MSK_COC_CTL14_COC_CTRL14_3_0 0x0f
1183
1184/* CoC 22nd Ctl, default value: 0x00 */
1185#define REG_COC_CTL15 0x0725
1186#define BIT_COC_CTL15_COC_CTRL15_7 BIT(7)
1187#define MSK_COC_CTL15_COC_CTRL15_6_4 0x70
1188#define MSK_COC_CTL15_COC_CTRL15_3_0 0x0f
1189
1190/* CoC Interrupt, default value: 0x00 */
1191#define REG_COC_INTR 0x0726
1192
1193/* CoC Interrupt Mask, default value: 0x00 */
1194#define REG_COC_INTR_MASK 0x0727
1195#define BIT_COC_PLL_LOCK_STATUS_CHANGE BIT(0)
1196#define BIT_COC_CALIBRATION_DONE BIT(1)
1197
1198/* CoC Misc Ctl, default value: 0x00 */
1199#define REG_COC_MISC_CTL0 0x0728
1200#define BIT_COC_MISC_CTL0_FSM_MON BIT(7)
1201
1202/* CoC 24th Ctl, default value: 0x00 */
1203#define REG_COC_CTL17 0x072a
1204#define MSK_COC_CTL17_COC_CTRL17_7_4 0xf0
1205#define MSK_COC_CTL17_COC_CTRL17_3_0 0x0f
1206
1207/* CoC 25th Ctl, default value: 0x00 */
1208#define REG_COC_CTL18 0x072b
1209#define MSK_COC_CTL18_COC_CTRL18_7_4 0xf0
1210#define MSK_COC_CTL18_COC_CTRL18_3_0 0x0f
1211
1212/* CoC 26th Ctl, default value: 0x00 */
1213#define REG_COC_CTL19 0x072c
1214#define MSK_COC_CTL19_COC_CTRL19_7_4 0xf0
1215#define MSK_COC_CTL19_COC_CTRL19_3_0 0x0f
1216
1217/* CoC 27th Ctl, default value: 0x00 */
1218#define REG_COC_CTL1A 0x072d
1219#define MSK_COC_CTL1A_COC_CTRL1A_7_2 0xfc
1220#define MSK_COC_CTL1A_COC_CTRL1A_1_0 0x03
1221
1222/* DoC 9th Status, default value: 0x00 */
1223#define REG_DOC_STAT_8 0x0740
1224
1225/* DoC 10th Status, default value: 0x00 */
1226#define REG_DOC_STAT_9 0x0741
1227
1228/* DoC 5th CFG, default value: 0x00 */
1229#define REG_DOC_CFG4 0x074e
1230#define MSK_DOC_CFG4_DBG_STATE_DOC_FSM 0x0f
1231
1232/* DoC 1st Ctl, default value: 0x40 */
1233#define REG_DOC_CTL0 0x0751
1234
1235/* DoC 7th Ctl, default value: 0x00 */
1236#define REG_DOC_CTL6 0x0757
1237#define BIT_DOC_CTL6_DOC_CTRL6_7 BIT(7)
1238#define BIT_DOC_CTL6_DOC_CTRL6_6 BIT(6)
1239#define MSK_DOC_CTL6_DOC_CTRL6_5_4 0x30
1240#define MSK_DOC_CTL6_DOC_CTRL6_3_0 0x0f
1241
1242/* DoC 8th Ctl, default value: 0x00 */
1243#define REG_DOC_CTL7 0x0758
1244#define BIT_DOC_CTL7_DOC_CTRL7_7 BIT(7)
1245#define BIT_DOC_CTL7_DOC_CTRL7_6 BIT(6)
1246#define BIT_DOC_CTL7_DOC_CTRL7_5 BIT(5)
1247#define MSK_DOC_CTL7_DOC_CTRL7_4_3 0x18
1248#define MSK_DOC_CTL7_DOC_CTRL7_2_0 0x07
1249
1250/* DoC 9th Ctl, default value: 0x00 */
1251#define REG_DOC_CTL8 0x076c
1252#define BIT_DOC_CTL8_DOC_CTRL8_7 BIT(7)
1253#define MSK_DOC_CTL8_DOC_CTRL8_6_4 0x70
1254#define MSK_DOC_CTL8_DOC_CTRL8_3_2 0x0c
1255#define MSK_DOC_CTL8_DOC_CTRL8_1_0 0x03
1256
1257/* DoC 10th Ctl, default value: 0x00 */
1258#define REG_DOC_CTL9 0x076d
1259
1260/* DoC 11th Ctl, default value: 0x00 */
1261#define REG_DOC_CTLA 0x076e
1262
1263/* DoC 15th Ctl, default value: 0x00 */
1264#define REG_DOC_CTLE 0x0772
1265#define BIT_DOC_CTLE_DOC_CTRLE_7 BIT(7)
1266#define BIT_DOC_CTLE_DOC_CTRLE_6 BIT(6)
1267#define MSK_DOC_CTLE_DOC_CTRLE_5_4 0x30
1268#define MSK_DOC_CTLE_DOC_CTRLE_3_0 0x0f
1269
1270/* Interrupt Mask 1st, default value: 0x00 */
1271#define REG_MHL_INT_0_MASK 0x0580
1272
1273/* Interrupt Mask 2nd, default value: 0x00 */
1274#define REG_MHL_INT_1_MASK 0x0581
1275
1276/* Interrupt Mask 3rd, default value: 0x00 */
1277#define REG_MHL_INT_2_MASK 0x0582
1278
1279/* Interrupt Mask 4th, default value: 0x00 */
1280#define REG_MHL_INT_3_MASK 0x0583
1281
1282/* MDT Receive Time Out, default value: 0x00 */
1283#define REG_MDT_RCV_TIMEOUT 0x0584
1284
1285/* MDT Transmit Time Out, default value: 0x00 */
1286#define REG_MDT_XMIT_TIMEOUT 0x0585
1287
1288/* MDT Receive Control, default value: 0x00 */
1289#define REG_MDT_RCV_CTRL 0x0586
1290#define BIT_MDT_RCV_CTRL_MDT_RCV_EN BIT(7)
1291#define BIT_MDT_RCV_CTRL_MDT_DELAY_RCV_EN BIT(6)
1292#define BIT_MDT_RCV_CTRL_MDT_RFIFO_OVER_WR_EN BIT(4)
1293#define BIT_MDT_RCV_CTRL_MDT_XFIFO_OVER_WR_EN BIT(3)
1294#define BIT_MDT_RCV_CTRL_MDT_DISABLE BIT(2)
1295#define BIT_MDT_RCV_CTRL_MDT_RFIFO_CLR_ALL BIT(1)
1296#define BIT_MDT_RCV_CTRL_MDT_RFIFO_CLR_CUR BIT(0)
1297
1298/* MDT Receive Read Port, default value: 0x00 */
1299#define REG_MDT_RCV_READ_PORT 0x0587
1300
1301/* MDT Transmit Control, default value: 0x70 */
1302#define REG_MDT_XMIT_CTRL 0x0588
1303#define BIT_MDT_XMIT_CTRL_EN BIT(7)
1304#define BIT_MDT_XMIT_CTRL_CMD_MERGE_EN BIT(6)
1305#define BIT_MDT_XMIT_CTRL_FIXED_BURST_LEN BIT(5)
1306#define BIT_MDT_XMIT_CTRL_FIXED_AID BIT(4)
1307#define BIT_MDT_XMIT_CTRL_SINGLE_RUN_EN BIT(3)
1308#define BIT_MDT_XMIT_CTRL_CLR_ABORT_WAIT BIT(2)
1309#define BIT_MDT_XMIT_CTRL_XFIFO_CLR_ALL BIT(1)
1310#define BIT_MDT_XMIT_CTRL_XFIFO_CLR_CUR BIT(0)
1311
1312/* MDT Receive WRITE Port, default value: 0x00 */
1313#define REG_MDT_XMIT_WRITE_PORT 0x0589
1314
1315/* MDT RFIFO Status, default value: 0x00 */
1316#define REG_MDT_RFIFO_STAT 0x058a
1317#define MSK_MDT_RFIFO_STAT_MDT_RFIFO_CNT 0xe0
1318#define MSK_MDT_RFIFO_STAT_MDT_RFIFO_CUR_BYTE_CNT 0x1f
1319
1320/* MDT XFIFO Status, default value: 0x80 */
1321#define REG_MDT_XFIFO_STAT 0x058b
1322#define MSK_MDT_XFIFO_STAT_MDT_XFIFO_LEVEL_AVAIL 0xe0
1323#define BIT_MDT_XFIFO_STAT_MDT_XMIT_PRE_HS_EN BIT(4)
1324#define MSK_MDT_XFIFO_STAT_MDT_WRITE_BURST_LEN 0x0f
1325
1326/* MDT Interrupt 0, default value: 0x0c */
1327#define REG_MDT_INT_0 0x058c
1328#define BIT_MDT_RFIFO_DATA_RDY BIT(0)
1329#define BIT_MDT_IDLE_AFTER_HAWB_DISABLE BIT(2)
1330#define BIT_MDT_XFIFO_EMPTY BIT(3)
1331
1332/* MDT Interrupt 0 Mask, default value: 0x00 */
1333#define REG_MDT_INT_0_MASK 0x058d
1334
1335/* MDT Interrupt 1, default value: 0x00 */
1336#define REG_MDT_INT_1 0x058e
1337#define BIT_MDT_RCV_TIMEOUT BIT(0)
1338#define BIT_MDT_RCV_SM_ABORT_PKT_RCVD BIT(1)
1339#define BIT_MDT_RCV_SM_ERROR BIT(2)
1340#define BIT_MDT_XMIT_TIMEOUT BIT(5)
1341#define BIT_MDT_XMIT_SM_ABORT_PKT_RCVD BIT(6)
1342#define BIT_MDT_XMIT_SM_ERROR BIT(7)
1343
1344/* MDT Interrupt 1 Mask, default value: 0x00 */
1345#define REG_MDT_INT_1_MASK 0x058f
1346
1347/* CBUS Vendor ID, default value: 0x01 */
1348#define REG_CBUS_VENDOR_ID 0x0590
1349
1350/* CBUS Connection Status, default value: 0x00 */
1351#define REG_CBUS_STATUS 0x0591
1352#define BIT_CBUS_STATUS_MHL_CABLE_PRESENT BIT(4)
1353#define BIT_CBUS_STATUS_MSC_HB_SUCCESS BIT(3)
1354#define BIT_CBUS_STATUS_CBUS_HPD BIT(2)
1355#define BIT_CBUS_STATUS_MHL_MODE BIT(1)
1356#define BIT_CBUS_STATUS_CBUS_CONNECTED BIT(0)
1357
1358/* CBUS Interrupt 1st, default value: 0x00 */
1359#define REG_CBUS_INT_0 0x0592
1360#define BIT_CBUS_MSC_MT_DONE_NACK BIT(7)
1361#define BIT_CBUS_MSC_MR_SET_INT BIT(6)
1362#define BIT_CBUS_MSC_MR_WRITE_BURST BIT(5)
1363#define BIT_CBUS_MSC_MR_MSC_MSG BIT(4)
1364#define BIT_CBUS_MSC_MR_WRITE_STAT BIT(3)
1365#define BIT_CBUS_HPD_CHG BIT(2)
1366#define BIT_CBUS_MSC_MT_DONE BIT(1)
1367#define BIT_CBUS_CNX_CHG BIT(0)
1368
1369/* CBUS Interrupt Mask 1st, default value: 0x00 */
1370#define REG_CBUS_INT_0_MASK 0x0593
1371
1372/* CBUS Interrupt 2nd, default value: 0x00 */
1373#define REG_CBUS_INT_1 0x0594
1374#define BIT_CBUS_CMD_ABORT BIT(6)
1375#define BIT_CBUS_MSC_ABORT_RCVD BIT(3)
1376#define BIT_CBUS_DDC_ABORT BIT(2)
1377#define BIT_CBUS_CEC_ABORT BIT(1)
1378
1379/* CBUS Interrupt Mask 2nd, default value: 0x00 */
1380#define REG_CBUS_INT_1_MASK 0x0595
1381
1382/* CBUS DDC Abort Interrupt, default value: 0x00 */
1383#define REG_DDC_ABORT_INT 0x0598
1384
1385/* CBUS DDC Abort Interrupt Mask, default value: 0x00 */
1386#define REG_DDC_ABORT_INT_MASK 0x0599
1387
1388/* CBUS MSC Requester Abort Interrupt, default value: 0x00 */
1389#define REG_MSC_MT_ABORT_INT 0x059a
1390
1391/* CBUS MSC Requester Abort Interrupt Mask, default value: 0x00 */
1392#define REG_MSC_MT_ABORT_INT_MASK 0x059b
1393
1394/* CBUS MSC Responder Abort Interrupt, default value: 0x00 */
1395#define REG_MSC_MR_ABORT_INT 0x059c
1396
1397/* CBUS MSC Responder Abort Interrupt Mask, default value: 0x00 */
1398#define REG_MSC_MR_ABORT_INT_MASK 0x059d
1399
1400/* CBUS RX DISCOVERY interrupt, default value: 0x00 */
1401#define REG_CBUS_RX_DISC_INT0 0x059e
1402
1403/* CBUS RX DISCOVERY Interrupt Mask, default value: 0x00 */
1404#define REG_CBUS_RX_DISC_INT0_MASK 0x059f
1405
1406/* CBUS_Link_Layer Control #8, default value: 0x00 */
1407#define REG_CBUS_LINK_CTRL_8 0x05a7
1408
1409/* MDT State Machine Status, default value: 0x00 */
1410#define REG_MDT_SM_STAT 0x05b5
1411#define MSK_MDT_SM_STAT_MDT_RCV_STATE 0xf0
1412#define MSK_MDT_SM_STAT_MDT_XMIT_STATE 0x0f
1413
1414/* CBUS MSC command trigger, default value: 0x00 */
1415#define REG_MSC_COMMAND_START 0x05b8
1416#define BIT_MSC_COMMAND_START_DEBUG BIT(5)
1417#define BIT_MSC_COMMAND_START_WRITE_BURST BIT(4)
1418#define BIT_MSC_COMMAND_START_WRITE_STAT BIT(3)
1419#define BIT_MSC_COMMAND_START_READ_DEVCAP BIT(2)
1420#define BIT_MSC_COMMAND_START_MSC_MSG BIT(1)
1421#define BIT_MSC_COMMAND_START_PEER BIT(0)
1422
1423/* CBUS MSC Command/Offset, default value: 0x00 */
1424#define REG_MSC_CMD_OR_OFFSET 0x05b9
1425
1426/* CBUS MSC Transmit Data */
1427#define REG_MSC_1ST_TRANSMIT_DATA 0x05ba
1428#define REG_MSC_2ND_TRANSMIT_DATA 0x05bb
1429
1430/* CBUS MSC Requester Received Data */
1431#define REG_MSC_MT_RCVD_DATA0 0x05bc
1432#define REG_MSC_MT_RCVD_DATA1 0x05bd
1433
1434/* CBUS MSC Responder MSC_MSG Received Data */
1435#define REG_MSC_MR_MSC_MSG_RCVD_1ST_DATA 0x05bf
1436#define REG_MSC_MR_MSC_MSG_RCVD_2ND_DATA 0x05c0
1437
1438/* CBUS MSC Heartbeat Control, default value: 0x27 */
1439#define REG_MSC_HEARTBEAT_CTRL 0x05c4
1440#define BIT_MSC_HEARTBEAT_CTRL_MSC_HB_EN BIT(7)
1441#define MSK_MSC_HEARTBEAT_CTRL_MSC_HB_FAIL_LIMIT 0x70
1442#define MSK_MSC_HEARTBEAT_CTRL_MSC_HB_PERIOD_MSB 0x0f
1443
1444/* CBUS MSC Compatibility Control, default value: 0x02 */
1445#define REG_CBUS_MSC_COMPAT_CTRL 0x05c7
1446#define BIT_CBUS_MSC_COMPAT_CTRL_XDEVCAP_EN BIT(7)
1447#define BIT_CBUS_MSC_COMPAT_CTRL_DISABLE_MSC_ON_CBUS BIT(6)
1448#define BIT_CBUS_MSC_COMPAT_CTRL_DISABLE_DDC_ON_CBUS BIT(5)
1449#define BIT_CBUS_MSC_COMPAT_CTRL_DISABLE_GET_DDC_ERRORCODE BIT(3)
1450#define BIT_CBUS_MSC_COMPAT_CTRL_DISABLE_GET_VS1_ERRORCODE BIT(2)
1451
1452/* CBUS3 Converter Control, default value: 0x24 */
1453#define REG_CBUS3_CNVT 0x05dc
1454#define MSK_CBUS3_CNVT_CBUS3_RETRYLMT 0xf0
1455#define MSK_CBUS3_CNVT_CBUS3_PEERTOUT_SEL 0x0c
1456#define BIT_CBUS3_CNVT_TEARCBUS_EN BIT(1)
1457#define BIT_CBUS3_CNVT_CBUS3CNVT_EN BIT(0)
1458
1459/* Discovery Control1, default value: 0x24 */
1460#define REG_DISC_CTRL1 0x05e0
1461#define BIT_DISC_CTRL1_CBUS_INTR_EN BIT(7)
1462#define BIT_DISC_CTRL1_HB_ONLY BIT(6)
1463#define MSK_DISC_CTRL1_DISC_ATT 0x30
1464#define MSK_DISC_CTRL1_DISC_CYC 0x0c
1465#define BIT_DISC_CTRL1_DISC_EN BIT(0)
1466
1467#define VAL_PUP_OFF 0
1468#define VAL_PUP_20K 1
1469#define VAL_PUP_5K 2
1470
1471/* Discovery Control4, default value: 0x80 */
1472#define REG_DISC_CTRL4 0x05e3
1473#define MSK_DISC_CTRL4_CBUSDISC_PUP_SEL 0xc0
1474#define MSK_DISC_CTRL4_CBUSIDLE_PUP_SEL 0x30
1475#define VAL_DISC_CTRL4(pup_disc, pup_idle) (((pup_disc) << 6) | (pup_idle << 4))
1476
1477/* Discovery Control5, default value: 0x03 */
1478#define REG_DISC_CTRL5 0x05e4
1479#define BIT_DISC_CTRL5_DSM_OVRIDE BIT(3)
1480#define MSK_DISC_CTRL5_CBUSMHL_PUP_SEL 0x03
1481
1482/* Discovery Control8, default value: 0x81 */
1483#define REG_DISC_CTRL8 0x05e7
1484#define BIT_DISC_CTRL8_NOMHLINT_CLR_BYPASS BIT(7)
1485#define BIT_DISC_CTRL8_DELAY_CBUS_INTR_EN BIT(0)
1486
1487/* Discovery Control9, default value: 0x54 */
1488#define REG_DISC_CTRL9 0x05e8
1489#define BIT_DISC_CTRL9_MHL3_RSEN_BYP BIT(7)
1490#define BIT_DISC_CTRL9_MHL3DISC_EN BIT(6)
1491#define BIT_DISC_CTRL9_WAKE_DRVFLT BIT(4)
1492#define BIT_DISC_CTRL9_NOMHL_EST BIT(3)
1493#define BIT_DISC_CTRL9_DISC_PULSE_PROCEED BIT(2)
1494#define BIT_DISC_CTRL9_WAKE_PULSE_BYPASS BIT(1)
1495#define BIT_DISC_CTRL9_VBUS_OUTPUT_CAPABILITY_SRC BIT(0)
1496
1497/* Discovery Status1, default value: 0x00 */
1498#define REG_DISC_STAT1 0x05eb
1499#define BIT_DISC_STAT1_PSM_OVRIDE BIT(5)
1500#define MSK_DISC_STAT1_DISC_SM 0x0f
1501
1502/* Discovery Status2, default value: 0x00 */
1503#define REG_DISC_STAT2 0x05ec
1504#define BIT_DISC_STAT2_CBUS_OE_POL BIT(6)
1505#define BIT_DISC_STAT2_CBUS_SATUS BIT(5)
1506#define BIT_DISC_STAT2_RSEN BIT(4)
1507
1508#define MSK_DISC_STAT2_MHL_VRSN 0x0c
1509#define VAL_DISC_STAT2_DEFAULT 0x00
1510#define VAL_DISC_STAT2_MHL1_2 0x04
1511#define VAL_DISC_STAT2_MHL3 0x08
1512#define VAL_DISC_STAT2_RESERVED 0x0c
1513
1514#define MSK_DISC_STAT2_RGND 0x03
1515#define VAL_RGND_OPEN 0x00
1516#define VAL_RGND_2K 0x01
1517#define VAL_RGND_1K 0x02
1518#define VAL_RGND_SHORT 0x03
1519
1520/* Interrupt CBUS_reg1 INTR0, default value: 0x00 */
1521#define REG_CBUS_DISC_INTR0 0x05ed
1522#define BIT_RGND_READY_INT BIT(6)
1523#define BIT_CBUS_MHL12_DISCON_INT BIT(5)
1524#define BIT_CBUS_MHL3_DISCON_INT BIT(4)
1525#define BIT_NOT_MHL_EST_INT BIT(3)
1526#define BIT_MHL_EST_INT BIT(2)
1527#define BIT_MHL3_EST_INT BIT(1)
1528#define VAL_CBUS_MHL_DISCON (BIT_CBUS_MHL12_DISCON_INT \
1529 | BIT_CBUS_MHL3_DISCON_INT \
1530 | BIT_NOT_MHL_EST_INT)
1531
1532/* Interrupt CBUS_reg1 INTR0 Mask, default value: 0x00 */
1533#define REG_CBUS_DISC_INTR0_MASK 0x05ee
1534
1535#endif /* __SIL_SII8620_H__ */