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1/*
2 * Registers of Silicon Image SiI8620 Mobile HD Transmitter
3 *
4 * Copyright (C) 2015, Samsung Electronics Co., Ltd.
5 * Andrzej Hajda <a.hajda@samsung.com>
6 *
7 * Based on MHL driver for Android devices.
8 * Copyright (C) 2013-2014 Silicon Image, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#ifndef __SIL_SII8620_H__
16#define __SIL_SII8620_H__
17
18/* Vendor ID Low byte, default value: 0x01 */
19#define REG_VND_IDL 0x0000
20
21/* Vendor ID High byte, default value: 0x00 */
22#define REG_VND_IDH 0x0001
23
24/* Device ID Low byte, default value: 0x60 */
25#define REG_DEV_IDL 0x0002
26
27/* Device ID High byte, default value: 0x86 */
28#define REG_DEV_IDH 0x0003
29
30/* Device Revision, default value: 0x10 */
31#define REG_DEV_REV 0x0004
32
33/* OTP DBYTE510, default value: 0x00 */
34#define REG_OTP_DBYTE510 0x0006
35
36/* System Control #1, default value: 0x00 */
37#define REG_SYS_CTRL1 0x0008
38#define BIT_SYS_CTRL1_OTPVMUTEOVR_SET BIT(7)
39#define BIT_SYS_CTRL1_VSYNCPIN BIT(6)
40#define BIT_SYS_CTRL1_OTPADROPOVR_SET BIT(5)
41#define BIT_SYS_CTRL1_BLOCK_DDC_BY_HPD BIT(4)
42#define BIT_SYS_CTRL1_OTP2XVOVR_EN BIT(3)
43#define BIT_SYS_CTRL1_OTP2XAOVR_EN BIT(2)
44#define BIT_SYS_CTRL1_TX_CTRL_HDMI BIT(1)
45#define BIT_SYS_CTRL1_OTPAMUTEOVR_SET BIT(0)
46
47/* System Control DPD, default value: 0x90 */
48#define REG_DPD 0x000b
49#define BIT_DPD_PWRON_PLL BIT(7)
50#define BIT_DPD_PDNTX12 BIT(6)
51#define BIT_DPD_PDNRX12 BIT(5)
52#define BIT_DPD_OSC_EN BIT(4)
53#define BIT_DPD_PWRON_HSIC BIT(3)
54#define BIT_DPD_PDIDCK_N BIT(2)
55#define BIT_DPD_PD_MHL_CLK_N BIT(1)
56
57/* Dual link Control, default value: 0x00 */
58#define REG_DCTL 0x000d
59#define BIT_DCTL_TDM_LCLK_PHASE BIT(7)
60#define BIT_DCTL_HSIC_CLK_PHASE BIT(6)
61#define BIT_DCTL_CTS_TCK_PHASE BIT(5)
62#define BIT_DCTL_EXT_DDC_SEL BIT(4)
63#define BIT_DCTL_TRANSCODE BIT(3)
64#define BIT_DCTL_HSIC_RX_STROBE_PHASE BIT(2)
65#define BIT_DCTL_HSIC_TX_BIST_START_SEL BIT(1)
66#define BIT_DCTL_TCLKNX_PHASE BIT(0)
67
68/* PWD Software Reset, default value: 0x20 */
69#define REG_PWD_SRST 0x000e
70#define BIT_PWD_SRST_COC_DOC_RST BIT(7)
71#define BIT_PWD_SRST_CBUS_RST_SW BIT(6)
72#define BIT_PWD_SRST_CBUS_RST_SW_EN BIT(5)
73#define BIT_PWD_SRST_MHLFIFO_RST BIT(4)
74#define BIT_PWD_SRST_CBUS_RST BIT(3)
75#define BIT_PWD_SRST_SW_RST_AUTO BIT(2)
76#define BIT_PWD_SRST_HDCP2X_SW_RST BIT(1)
77#define BIT_PWD_SRST_SW_RST BIT(0)
78
79/* AKSV_1, default value: 0x00 */
80#define REG_AKSV_1 0x001d
81
82/* Video H Resolution #1, default value: 0x00 */
83#define REG_H_RESL 0x003a
84
85/* Video Mode, default value: 0x00 */
86#define REG_VID_MODE 0x004a
87#define BIT_VID_MODE_M1080P BIT(6)
88
89/* Video Input Mode, default value: 0xc0 */
90#define REG_VID_OVRRD 0x0051
91#define BIT_VID_OVRRD_PP_AUTO_DISABLE BIT(7)
92#define BIT_VID_OVRRD_M1080P_OVRRD BIT(6)
93#define BIT_VID_OVRRD_MINIVSYNC_ON BIT(5)
94#define BIT_VID_OVRRD_3DCONV_EN_FRAME_PACK BIT(4)
95#define BIT_VID_OVRRD_ENABLE_AUTO_PATH_EN BIT(3)
96#define BIT_VID_OVRRD_ENRGB2YCBCR_OVRRD BIT(2)
97#define BIT_VID_OVRRD_ENDOWNSAMPLE_OVRRD BIT(0)
98
99/* I2C Address reassignment, default value: 0x00 */
100#define REG_PAGE_MHLSPEC_ADDR 0x0057
101#define REG_PAGE7_ADDR 0x0058
102#define REG_PAGE8_ADDR 0x005c
103
104/* Fast Interrupt Status, default value: 0x00 */
105#define REG_FAST_INTR_STAT 0x005f
106#define LEN_FAST_INTR_STAT 7
107#define BIT_FAST_INTR_STAT_TIMR 8
108#define BIT_FAST_INTR_STAT_INT2 9
109#define BIT_FAST_INTR_STAT_DDC 10
110#define BIT_FAST_INTR_STAT_SCDT 11
111#define BIT_FAST_INTR_STAT_INFR 13
112#define BIT_FAST_INTR_STAT_EDID 14
113#define BIT_FAST_INTR_STAT_HDCP 15
114#define BIT_FAST_INTR_STAT_MSC 16
115#define BIT_FAST_INTR_STAT_MERR 17
116#define BIT_FAST_INTR_STAT_G2WB 18
117#define BIT_FAST_INTR_STAT_G2WB_ERR 19
118#define BIT_FAST_INTR_STAT_DISC 28
119#define BIT_FAST_INTR_STAT_BLOCK 30
120#define BIT_FAST_INTR_STAT_LTRN 31
121#define BIT_FAST_INTR_STAT_HDCP2 32
122#define BIT_FAST_INTR_STAT_TDM 42
123#define BIT_FAST_INTR_STAT_COC 51
124
125/* GPIO Control, default value: 0x15 */
126#define REG_GPIO_CTRL1 0x006e
127#define BIT_CTRL1_GPIO_I_8 BIT(5)
128#define BIT_CTRL1_GPIO_OEN_8 BIT(4)
129#define BIT_CTRL1_GPIO_I_7 BIT(3)
130#define BIT_CTRL1_GPIO_OEN_7 BIT(2)
131#define BIT_CTRL1_GPIO_I_6 BIT(1)
132#define BIT_CTRL1_GPIO_OEN_6 BIT(0)
133
134/* Interrupt Control, default value: 0x06 */
135#define REG_INT_CTRL 0x006f
136#define BIT_INT_CTRL_SOFTWARE_WP BIT(7)
137#define BIT_INT_CTRL_INTR_OD BIT(2)
138#define BIT_INT_CTRL_INTR_POLARITY BIT(1)
139
140/* Interrupt State, default value: 0x00 */
141#define REG_INTR_STATE 0x0070
142#define BIT_INTR_STATE_INTR_STATE BIT(0)
143
144/* Interrupt Source #1, default value: 0x00 */
145#define REG_INTR1 0x0071
146
147/* Interrupt Source #2, default value: 0x00 */
148#define REG_INTR2 0x0072
149
150/* Interrupt Source #3, default value: 0x01 */
151#define REG_INTR3 0x0073
152#define BIT_DDC_CMD_DONE BIT(3)
153
154/* Interrupt Source #5, default value: 0x00 */
155#define REG_INTR5 0x0074
156
157/* Interrupt #1 Mask, default value: 0x00 */
158#define REG_INTR1_MASK 0x0075
159
160/* Interrupt #2 Mask, default value: 0x00 */
161#define REG_INTR2_MASK 0x0076
162
163/* Interrupt #3 Mask, default value: 0x00 */
164#define REG_INTR3_MASK 0x0077
165
166/* Interrupt #5 Mask, default value: 0x00 */
167#define REG_INTR5_MASK 0x0078
168#define BIT_INTR_SCDT_CHANGE BIT(0)
169
170/* Hot Plug Connection Control, default value: 0x45 */
171#define REG_HPD_CTRL 0x0079
172#define BIT_HPD_CTRL_HPD_DS_SIGNAL BIT(7)
173#define BIT_HPD_CTRL_HPD_OUT_OD_EN BIT(6)
174#define BIT_HPD_CTRL_HPD_HIGH BIT(5)
175#define BIT_HPD_CTRL_HPD_OUT_OVR_EN BIT(4)
176#define BIT_HPD_CTRL_GPIO_I_1 BIT(3)
177#define BIT_HPD_CTRL_GPIO_OEN_1 BIT(2)
178#define BIT_HPD_CTRL_GPIO_I_0 BIT(1)
179#define BIT_HPD_CTRL_GPIO_OEN_0 BIT(0)
180
181/* GPIO Control, default value: 0x55 */
182#define REG_GPIO_CTRL 0x007a
183#define BIT_CTRL_GPIO_I_5 BIT(7)
184#define BIT_CTRL_GPIO_OEN_5 BIT(6)
185#define BIT_CTRL_GPIO_I_4 BIT(5)
186#define BIT_CTRL_GPIO_OEN_4 BIT(4)
187#define BIT_CTRL_GPIO_I_3 BIT(3)
188#define BIT_CTRL_GPIO_OEN_3 BIT(2)
189#define BIT_CTRL_GPIO_I_2 BIT(1)
190#define BIT_CTRL_GPIO_OEN_2 BIT(0)
191
192/* Interrupt Source 7, default value: 0x00 */
193#define REG_INTR7 0x007b
194
195/* Interrupt Source 8, default value: 0x00 */
196#define REG_INTR8 0x007c
197
198/* Interrupt #7 Mask, default value: 0x00 */
199#define REG_INTR7_MASK 0x007d
200
201/* Interrupt #8 Mask, default value: 0x00 */
202#define REG_INTR8_MASK 0x007e
203#define BIT_CEA_NEW_VSI BIT(2)
204#define BIT_CEA_NEW_AVI BIT(1)
205
206/* IEEE, default value: 0x10 */
207#define REG_TMDS_CCTRL 0x0080
208#define BIT_TMDS_CCTRL_TMDS_OE BIT(4)
209
210/* TMDS Control #4, default value: 0x02 */
211#define REG_TMDS_CTRL4 0x0085
212#define BIT_TMDS_CTRL4_SCDT_CKDT_SEL BIT(1)
213#define BIT_TMDS_CTRL4_TX_EN_BY_SCDT BIT(0)
214
215/* BIST CNTL, default value: 0x00 */
216#define REG_BIST_CTRL 0x00bb
217#define BIT_RXBIST_VGB_EN BIT(7)
218#define BIT_TXBIST_VGB_EN BIT(6)
219#define BIT_BIST_START_SEL BIT(5)
220#define BIT_BIST_START_BIT BIT(4)
221#define BIT_BIST_ALWAYS_ON BIT(3)
222#define BIT_BIST_TRANS BIT(2)
223#define BIT_BIST_RESET BIT(1)
224#define BIT_BIST_EN BIT(0)
225
226/* BIST DURATION0, default value: 0x00 */
227#define REG_BIST_TEST_SEL 0x00bd
228#define MSK_BIST_TEST_SEL_BIST_PATT_SEL 0x0f
229
230/* BIST VIDEO_MODE, default value: 0x00 */
231#define REG_BIST_VIDEO_MODE 0x00be
232#define MSK_BIST_VIDEO_MODE_BIST_VIDEO_MODE_3_0 0x0f
233
234/* BIST DURATION0, default value: 0x00 */
235#define REG_BIST_DURATION_0 0x00bf
236
237/* BIST DURATION1, default value: 0x00 */
238#define REG_BIST_DURATION_1 0x00c0
239
240/* BIST DURATION2, default value: 0x00 */
241#define REG_BIST_DURATION_2 0x00c1
242
243/* BIST 8BIT_PATTERN, default value: 0x00 */
244#define REG_BIST_8BIT_PATTERN 0x00c2
245
246/* LM DDC, default value: 0x80 */
247#define REG_LM_DDC 0x00c7
248#define BIT_LM_DDC_SW_TPI_EN_DISABLED BIT(7)
249
250#define BIT_LM_DDC_VIDEO_MUTE_EN BIT(5)
251#define BIT_LM_DDC_DDC_TPI_SW BIT(2)
252#define BIT_LM_DDC_DDC_GRANT BIT(1)
253#define BIT_LM_DDC_DDC_GPU_REQUEST BIT(0)
254
255/* DDC I2C Manual, default value: 0x03 */
256#define REG_DDC_MANUAL 0x00ec
257#define BIT_DDC_MANUAL_MAN_DDC BIT(7)
258#define BIT_DDC_MANUAL_VP_SEL BIT(6)
259#define BIT_DDC_MANUAL_DSDA BIT(5)
260#define BIT_DDC_MANUAL_DSCL BIT(4)
261#define BIT_DDC_MANUAL_GCP_HW_CTL_EN BIT(3)
262#define BIT_DDC_MANUAL_DDCM_ABORT_WP BIT(2)
263#define BIT_DDC_MANUAL_IO_DSDA BIT(1)
264#define BIT_DDC_MANUAL_IO_DSCL BIT(0)
265
266/* DDC I2C Target Slave Address, default value: 0x00 */
267#define REG_DDC_ADDR 0x00ed
268#define MSK_DDC_ADDR_DDC_ADDR 0xfe
269
270/* DDC I2C Target Segment Address, default value: 0x00 */
271#define REG_DDC_SEGM 0x00ee
272
273/* DDC I2C Target Offset Address, default value: 0x00 */
274#define REG_DDC_OFFSET 0x00ef
275
276/* DDC I2C Data In count #1, default value: 0x00 */
277#define REG_DDC_DIN_CNT1 0x00f0
278
279/* DDC I2C Data In count #2, default value: 0x00 */
280#define REG_DDC_DIN_CNT2 0x00f1
281#define MSK_DDC_DIN_CNT2_DDC_DIN_CNT_9_8 0x03
282
283/* DDC I2C Status, default value: 0x04 */
284#define REG_DDC_STATUS 0x00f2
285#define BIT_DDC_STATUS_DDC_BUS_LOW BIT(6)
286#define BIT_DDC_STATUS_DDC_NO_ACK BIT(5)
287#define BIT_DDC_STATUS_DDC_I2C_IN_PROG BIT(4)
288#define BIT_DDC_STATUS_DDC_FIFO_FULL BIT(3)
289#define BIT_DDC_STATUS_DDC_FIFO_EMPTY BIT(2)
290#define BIT_DDC_STATUS_DDC_FIFO_READ_IN_SUE BIT(1)
291#define BIT_DDC_STATUS_DDC_FIFO_WRITE_IN_USE BIT(0)
292
293/* DDC I2C Command, default value: 0x70 */
294#define REG_DDC_CMD 0x00f3
295#define BIT_DDC_CMD_HDCP_DDC_EN BIT(6)
296#define BIT_DDC_CMD_SDA_DEL_EN BIT(5)
297#define BIT_DDC_CMD_DDC_FLT_EN BIT(4)
298
299#define MSK_DDC_CMD_DDC_CMD 0x0f
300#define VAL_DDC_CMD_ENH_DDC_READ_NO_ACK 0x04
301#define VAL_DDC_CMD_DDC_CMD_CLEAR_FIFO 0x09
302#define VAL_DDC_CMD_DDC_CMD_ABORT 0x0f
303
304/* DDC I2C FIFO Data In/Out, default value: 0x00 */
305#define REG_DDC_DATA 0x00f4
306
307/* DDC I2C Data Out Counter, default value: 0x00 */
308#define REG_DDC_DOUT_CNT 0x00f5
309#define BIT_DDC_DOUT_CNT_DDC_DELAY_CNT_8 BIT(7)
310#define MSK_DDC_DOUT_CNT_DDC_DATA_OUT_CNT 0x1f
311
312/* DDC I2C Delay Count, default value: 0x14 */
313#define REG_DDC_DELAY_CNT 0x00f6
314
315/* Test Control, default value: 0x80 */
316#define REG_TEST_TXCTRL 0x00f7
317#define BIT_TEST_TXCTRL_RCLK_REF_SEL BIT(7)
318#define BIT_TEST_TXCTRL_PCLK_REF_SEL BIT(6)
319#define MSK_TEST_TXCTRL_BYPASS_PLL_CLK 0x3c
320#define BIT_TEST_TXCTRL_HDMI_MODE BIT(1)
321#define BIT_TEST_TXCTRL_TST_PLLCK BIT(0)
322
323/* CBUS Address, default value: 0x00 */
324#define REG_PAGE_CBUS_ADDR 0x00f8
325
326/* I2C Device Address re-assignment */
327#define REG_PAGE1_ADDR 0x00fc
328#define REG_PAGE2_ADDR 0x00fd
329#define REG_PAGE3_ADDR 0x00fe
330#define REG_HW_TPI_ADDR 0x00ff
331
332/* USBT CTRL0, default value: 0x00 */
333#define REG_UTSRST 0x0100
334#define BIT_UTSRST_FC_SRST BIT(5)
335#define BIT_UTSRST_KEEPER_SRST BIT(4)
336#define BIT_UTSRST_HTX_SRST BIT(3)
337#define BIT_UTSRST_TRX_SRST BIT(2)
338#define BIT_UTSRST_TTX_SRST BIT(1)
339#define BIT_UTSRST_HRX_SRST BIT(0)
340
341/* HSIC RX Control3, default value: 0x07 */
342#define REG_HRXCTRL3 0x0104
343#define MSK_HRXCTRL3_HRX_AFFCTRL 0xf0
344#define BIT_HRXCTRL3_HRX_OUT_EN BIT(2)
345#define BIT_HRXCTRL3_STATUS_EN BIT(1)
346#define BIT_HRXCTRL3_HRX_STAY_RESET BIT(0)
347
348/* HSIC RX INT Registers */
349#define REG_HRXINTL 0x0111
350#define REG_HRXINTH 0x0112
351
352/* TDM TX NUMBITS, default value: 0x0c */
353#define REG_TTXNUMB 0x0116
354#define MSK_TTXNUMB_TTX_AFFCTRL_3_0 0xf0
355#define BIT_TTXNUMB_TTX_COM1_AT_SYNC_WAIT BIT(3)
356#define MSK_TTXNUMB_TTX_NUMBPS_2_0 0x07
357
358/* TDM TX NUMSPISYM, default value: 0x04 */
359#define REG_TTXSPINUMS 0x0117
360
361/* TDM TX NUMHSICSYM, default value: 0x14 */
362#define REG_TTXHSICNUMS 0x0118
363
364/* TDM TX NUMTOTSYM, default value: 0x18 */
365#define REG_TTXTOTNUMS 0x0119
366
367/* TDM TX INT Low, default value: 0x00 */
368#define REG_TTXINTL 0x0136
369#define BIT_TTXINTL_TTX_INTR7 BIT(7)
370#define BIT_TTXINTL_TTX_INTR6 BIT(6)
371#define BIT_TTXINTL_TTX_INTR5 BIT(5)
372#define BIT_TTXINTL_TTX_INTR4 BIT(4)
373#define BIT_TTXINTL_TTX_INTR3 BIT(3)
374#define BIT_TTXINTL_TTX_INTR2 BIT(2)
375#define BIT_TTXINTL_TTX_INTR1 BIT(1)
376#define BIT_TTXINTL_TTX_INTR0 BIT(0)
377
378/* TDM TX INT High, default value: 0x00 */
379#define REG_TTXINTH 0x0137
380#define BIT_TTXINTH_TTX_INTR15 BIT(7)
381#define BIT_TTXINTH_TTX_INTR14 BIT(6)
382#define BIT_TTXINTH_TTX_INTR13 BIT(5)
383#define BIT_TTXINTH_TTX_INTR12 BIT(4)
384#define BIT_TTXINTH_TTX_INTR11 BIT(3)
385#define BIT_TTXINTH_TTX_INTR10 BIT(2)
386#define BIT_TTXINTH_TTX_INTR9 BIT(1)
387#define BIT_TTXINTH_TTX_INTR8 BIT(0)
388
389/* TDM RX Control, default value: 0x1c */
390#define REG_TRXCTRL 0x013b
391#define BIT_TRXCTRL_TRX_CLR_WVALLOW BIT(4)
392#define BIT_TRXCTRL_TRX_FROM_SE_COC BIT(3)
393#define MSK_TRXCTRL_TRX_NUMBPS_2_0 0x07
394
395/* TDM RX NUMSPISYM, default value: 0x04 */
396#define REG_TRXSPINUMS 0x013c
397
398/* TDM RX NUMHSICSYM, default value: 0x14 */
399#define REG_TRXHSICNUMS 0x013d
400
401/* TDM RX NUMTOTSYM, default value: 0x18 */
402#define REG_TRXTOTNUMS 0x013e
403
404/* TDM RX Status 2nd, default value: 0x00 */
405#define REG_TRXSTA2 0x015c
406
407/* TDM RX INT Low, default value: 0x00 */
408#define REG_TRXINTL 0x0163
409
410/* TDM RX INT High, default value: 0x00 */
411#define REG_TRXINTH 0x0164
412
413/* TDM RX INTMASK High, default value: 0x00 */
414#define REG_TRXINTMH 0x0166
415
416/* HSIC TX CRTL, default value: 0x00 */
417#define REG_HTXCTRL 0x0169
418#define BIT_HTXCTRL_HTX_ALLSBE_SOP BIT(4)
419#define BIT_HTXCTRL_HTX_RGDINV_USB BIT(3)
420#define BIT_HTXCTRL_HTX_RSPTDM_BUSY BIT(2)
421#define BIT_HTXCTRL_HTX_DRVCONN1 BIT(1)
422#define BIT_HTXCTRL_HTX_DRVRST1 BIT(0)
423
424/* HSIC TX INT Low, default value: 0x00 */
425#define REG_HTXINTL 0x017d
426
427/* HSIC TX INT High, default value: 0x00 */
428#define REG_HTXINTH 0x017e
429
430/* HSIC Keeper, default value: 0x00 */
431#define REG_KEEPER 0x0181
432#define MSK_KEEPER_KEEPER_MODE_1_0 0x03
433
434/* HSIC Flow Control General, default value: 0x02 */
435#define REG_FCGC 0x0183
436#define BIT_FCGC_HSIC_FC_HOSTMODE BIT(1)
437#define BIT_FCGC_HSIC_FC_ENABLE BIT(0)
438
439/* HSIC Flow Control CTR13, default value: 0xfc */
440#define REG_FCCTR13 0x0191
441
442/* HSIC Flow Control CTR14, default value: 0xff */
443#define REG_FCCTR14 0x0192
444
445/* HSIC Flow Control CTR15, default value: 0xff */
446#define REG_FCCTR15 0x0193
447
448/* HSIC Flow Control CTR50, default value: 0x03 */
449#define REG_FCCTR50 0x01b6
450
451/* HSIC Flow Control INTR0, default value: 0x00 */
452#define REG_FCINTR0 0x01ec
453#define REG_FCINTR1 0x01ed
454#define REG_FCINTR2 0x01ee
455#define REG_FCINTR3 0x01ef
456#define REG_FCINTR4 0x01f0
457#define REG_FCINTR5 0x01f1
458#define REG_FCINTR6 0x01f2
459#define REG_FCINTR7 0x01f3
460
461/* TDM Low Latency, default value: 0x20 */
462#define REG_TDMLLCTL 0x01fc
463#define MSK_TDMLLCTL_TRX_LL_SEL_MANUAL 0xc0
464#define MSK_TDMLLCTL_TRX_LL_SEL_MODE 0x30
465#define MSK_TDMLLCTL_TTX_LL_SEL_MANUAL 0x0c
466#define BIT_TDMLLCTL_TTX_LL_TIE_LOW BIT(1)
467#define BIT_TDMLLCTL_TTX_LL_SEL_MODE BIT(0)
468
469/* TMDS 0 Clock Control, default value: 0x10 */
470#define REG_TMDS0_CCTRL1 0x0210
471#define MSK_TMDS0_CCTRL1_TEST_SEL 0xc0
472#define MSK_TMDS0_CCTRL1_CLK1X_CTL 0x30
473
474/* TMDS Clock Enable, default value: 0x00 */
475#define REG_TMDS_CLK_EN 0x0211
476#define BIT_TMDS_CLK_EN_CLK_EN BIT(0)
477
478/* TMDS Channel Enable, default value: 0x00 */
479#define REG_TMDS_CH_EN 0x0212
480#define BIT_TMDS_CH_EN_CH0_EN BIT(4)
481#define BIT_TMDS_CH_EN_CH12_EN BIT(0)
482
483/* BGR_BIAS, default value: 0x07 */
484#define REG_BGR_BIAS 0x0215
485#define BIT_BGR_BIAS_BGR_EN BIT(7)
486#define MSK_BGR_BIAS_BIAS_BGR_D 0x0f
487
488/* TMDS 0 Digital I2C BW, default value: 0x0a */
489#define REG_ALICE0_BW_I2C 0x0231
490
491/* TMDS 0 Digital Zone Control, default value: 0xe0 */
492#define REG_ALICE0_ZONE_CTRL 0x024c
493#define BIT_ALICE0_ZONE_CTRL_ICRST_N BIT(7)
494#define BIT_ALICE0_ZONE_CTRL_USE_INT_DIV20 BIT(6)
495#define MSK_ALICE0_ZONE_CTRL_SZONE_I2C 0x30
496#define MSK_ALICE0_ZONE_CTRL_ZONE_CTRL 0x0f
497
498/* TMDS 0 Digital PLL Mode Control, default value: 0x00 */
499#define REG_ALICE0_MODE_CTRL 0x024d
500#define MSK_ALICE0_MODE_CTRL_PLL_MODE_I2C 0x0c
501#define MSK_ALICE0_MODE_CTRL_DIV20_CTRL 0x03
502
503/* MHL Tx Control 6th, default value: 0xa0 */
504#define REG_MHLTX_CTL6 0x0285
505#define MSK_MHLTX_CTL6_EMI_SEL 0xe0
506#define MSK_MHLTX_CTL6_TX_CLK_SHAPE_9_8 0x03
507
508/* Packet Filter0, default value: 0x00 */
509#define REG_PKT_FILTER_0 0x0290
510#define BIT_PKT_FILTER_0_DROP_CEA_GAMUT_PKT BIT(7)
511#define BIT_PKT_FILTER_0_DROP_CEA_CP_PKT BIT(6)
512#define BIT_PKT_FILTER_0_DROP_MPEG_PKT BIT(5)
513#define BIT_PKT_FILTER_0_DROP_SPIF_PKT BIT(4)
514#define BIT_PKT_FILTER_0_DROP_AIF_PKT BIT(3)
515#define BIT_PKT_FILTER_0_DROP_AVI_PKT BIT(2)
516#define BIT_PKT_FILTER_0_DROP_CTS_PKT BIT(1)
517#define BIT_PKT_FILTER_0_DROP_GCP_PKT BIT(0)
518
519/* Packet Filter1, default value: 0x00 */
520#define REG_PKT_FILTER_1 0x0291
521#define BIT_PKT_FILTER_1_VSI_OVERRIDE_DIS BIT(7)
522#define BIT_PKT_FILTER_1_AVI_OVERRIDE_DIS BIT(6)
523#define BIT_PKT_FILTER_1_DROP_AUDIO_PKT BIT(3)
524#define BIT_PKT_FILTER_1_DROP_GEN2_PKT BIT(2)
525#define BIT_PKT_FILTER_1_DROP_GEN_PKT BIT(1)
526#define BIT_PKT_FILTER_1_DROP_VSIF_PKT BIT(0)
527
528/* TMDS Clock Status, default value: 0x10 */
529#define REG_TMDS_CSTAT_P3 0x02a0
530#define BIT_TMDS_CSTAT_P3_RX_HDMI_CP_CLR_MUTE BIT(7)
531#define BIT_TMDS_CSTAT_P3_RX_HDMI_CP_SET_MUTE BIT(6)
532#define BIT_TMDS_CSTAT_P3_RX_HDMI_CP_NEW_CP BIT(5)
533#define BIT_TMDS_CSTAT_P3_CLR_AVI BIT(3)
534#define BIT_TMDS_CSTAT_P3_SCDT_CLR_AVI_DIS BIT(2)
535#define BIT_TMDS_CSTAT_P3_SCDT BIT(1)
536#define BIT_TMDS_CSTAT_P3_CKDT BIT(0)
537
538/* RX_HDMI Control, default value: 0x10 */
539#define REG_RX_HDMI_CTRL0 0x02a1
540#define BIT_RX_HDMI_CTRL0_BYP_DVIFILT_SYNC BIT(5)
541#define BIT_RX_HDMI_CTRL0_HDMI_MODE_EN_ITSELF_CLR BIT(4)
542#define BIT_RX_HDMI_CTRL0_HDMI_MODE_SW_VALUE BIT(3)
543#define BIT_RX_HDMI_CTRL0_HDMI_MODE_OVERWRITE BIT(2)
544#define BIT_RX_HDMI_CTRL0_RX_HDMI_HDMI_MODE_EN BIT(1)
545#define BIT_RX_HDMI_CTRL0_RX_HDMI_HDMI_MODE BIT(0)
546
547/* RX_HDMI Control, default value: 0x38 */
548#define REG_RX_HDMI_CTRL2 0x02a3
549#define MSK_RX_HDMI_CTRL2_IDLE_CNT 0xf0
550#define VAL_RX_HDMI_CTRL2_IDLE_CNT(n) ((n) << 4)
551#define BIT_RX_HDMI_CTRL2_USE_AV_MUTE BIT(3)
552#define BIT_RX_HDMI_CTRL2_VSI_MON_SEL_VSI BIT(0)
553
554/* RX_HDMI Control, default value: 0x0f */
555#define REG_RX_HDMI_CTRL3 0x02a4
556#define MSK_RX_HDMI_CTRL3_PP_MODE_CLK_EN 0x0f
557
558/* rx_hdmi Clear Buffer, default value: 0x00 */
559#define REG_RX_HDMI_CLR_BUFFER 0x02ac
560#define MSK_RX_HDMI_CLR_BUFFER_AIF4VSI_CMP 0xc0
561#define BIT_RX_HDMI_CLR_BUFFER_USE_AIF4VSI BIT(5)
562#define BIT_RX_HDMI_CLR_BUFFER_VSI_CLR_W_AVI BIT(4)
563#define BIT_RX_HDMI_CLR_BUFFER_VSI_IEEE_ID_CHK_EN BIT(3)
564#define BIT_RX_HDMI_CLR_BUFFER_SWAP_VSI_IEEE_ID BIT(2)
565#define BIT_RX_HDMI_CLR_BUFFER_AIF_CLR_EN BIT(1)
566#define BIT_RX_HDMI_CLR_BUFFER_VSI_CLR_EN BIT(0)
567
568/* RX_HDMI VSI Header1, default value: 0x00 */
569#define REG_RX_HDMI_MON_PKT_HEADER1 0x02b8
570
571/* RX_HDMI VSI MHL Monitor, default value: 0x3c */
572#define REG_RX_HDMI_VSIF_MHL_MON 0x02d7
573
574#define MSK_RX_HDMI_VSIF_MHL_MON_RX_HDMI_MHL_3D_FORMAT 0x3c
575#define MSK_RX_HDMI_VSIF_MHL_MON_RX_HDMI_MHL_VID_FORMAT 0x03
576
577/* Interrupt Source 9, default value: 0x00 */
578#define REG_INTR9 0x02e0
579#define BIT_INTR9_EDID_ERROR BIT(6)
580#define BIT_INTR9_EDID_DONE BIT(5)
581#define BIT_INTR9_DEVCAP_DONE BIT(4)
582
583/* Interrupt 9 Mask, default value: 0x00 */
584#define REG_INTR9_MASK 0x02e1
585
586/* TPI CBUS Start, default value: 0x00 */
587#define REG_TPI_CBUS_START 0x02e2
588#define BIT_TPI_CBUS_START_RCP_REQ_START BIT(7)
589#define BIT_TPI_CBUS_START_RCPK_REPLY_START BIT(6)
590#define BIT_TPI_CBUS_START_RCPE_REPLY_START BIT(5)
591#define BIT_TPI_CBUS_START_PUT_LINK_MODE_START BIT(4)
592#define BIT_TPI_CBUS_START_PUT_DCAPCHG_START BIT(3)
593#define BIT_TPI_CBUS_START_PUT_DCAPRDY_START BIT(2)
594#define BIT_TPI_CBUS_START_GET_EDID_START_0 BIT(1)
595#define BIT_TPI_CBUS_START_GET_DEVCAP_START BIT(0)
596
597/* EDID Control, default value: 0x10 */
598#define REG_EDID_CTRL 0x02e3
599#define BIT_EDID_CTRL_EDID_PRIME_VALID BIT(7)
600#define BIT_EDID_CTRL_XDEVCAP_EN BIT(6)
601#define BIT_EDID_CTRL_DEVCAP_SELECT_DEVCAP BIT(5)
602#define BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO BIT(4)
603#define BIT_EDID_CTRL_EDID_FIFO_ACCESS_ALWAYS_EN BIT(3)
604#define BIT_EDID_CTRL_EDID_FIFO_BLOCK_SEL BIT(2)
605#define BIT_EDID_CTRL_INVALID_BKSV BIT(1)
606#define BIT_EDID_CTRL_EDID_MODE_EN BIT(0)
607
608/* EDID FIFO Addr, default value: 0x00 */
609#define REG_EDID_FIFO_ADDR 0x02e9
610
611/* EDID FIFO Write Data, default value: 0x00 */
612#define REG_EDID_FIFO_WR_DATA 0x02ea
613
614/* EDID/DEVCAP FIFO Internal Addr, default value: 0x00 */
615#define REG_EDID_FIFO_ADDR_MON 0x02eb
616
617/* EDID FIFO Read Data, default value: 0x00 */
618#define REG_EDID_FIFO_RD_DATA 0x02ec
619
620/* EDID DDC Segment Pointer, default value: 0x00 */
621#define REG_EDID_START_EXT 0x02ed
622
623/* TX IP BIST CNTL and Status, default value: 0x00 */
624#define REG_TX_IP_BIST_CNTLSTA 0x02f2
625#define BIT_TX_IP_BIST_CNTLSTA_TXBIST_QUARTER_CLK_SEL BIT(6)
626#define BIT_TX_IP_BIST_CNTLSTA_TXBIST_DONE BIT(5)
627#define BIT_TX_IP_BIST_CNTLSTA_TXBIST_ON BIT(4)
628#define BIT_TX_IP_BIST_CNTLSTA_TXBIST_RUN BIT(3)
629#define BIT_TX_IP_BIST_CNTLSTA_TXCLK_HALF_SEL BIT(2)
630#define BIT_TX_IP_BIST_CNTLSTA_TXBIST_EN BIT(1)
631#define BIT_TX_IP_BIST_CNTLSTA_TXBIST_SEL BIT(0)
632
633/* TX IP BIST INST LOW, default value: 0x00 */
634#define REG_TX_IP_BIST_INST_LOW 0x02f3
635#define REG_TX_IP_BIST_INST_HIGH 0x02f4
636
637/* TX IP BIST PATTERN LOW, default value: 0x00 */
638#define REG_TX_IP_BIST_PAT_LOW 0x02f5
639#define REG_TX_IP_BIST_PAT_HIGH 0x02f6
640
641/* TX IP BIST CONFIGURE LOW, default value: 0x00 */
642#define REG_TX_IP_BIST_CONF_LOW 0x02f7
643#define REG_TX_IP_BIST_CONF_HIGH 0x02f8
644
645/* E-MSC General Control, default value: 0x80 */
646#define REG_GENCTL 0x0300
647#define BIT_GENCTL_SPEC_TRANS_DIS BIT(7)
648#define BIT_GENCTL_DIS_XMIT_ERR_STATE BIT(6)
649#define BIT_GENCTL_SPI_MISO_EDGE BIT(5)
650#define BIT_GENCTL_SPI_MOSI_EDGE BIT(4)
651#define BIT_GENCTL_CLR_EMSC_RFIFO BIT(3)
652#define BIT_GENCTL_CLR_EMSC_XFIFO BIT(2)
653#define BIT_GENCTL_START_TRAIN_SEQ BIT(1)
654#define BIT_GENCTL_EMSC_EN BIT(0)
655
656/* E-MSC Comma ErrorCNT, default value: 0x03 */
657#define REG_COMMECNT 0x0305
658#define BIT_COMMECNT_I2C_TO_EMSC_EN BIT(7)
659#define MSK_COMMECNT_COMMA_CHAR_ERR_CNT 0x0f
660
661/* E-MSC RFIFO ByteCnt, default value: 0x00 */
662#define REG_EMSCRFIFOBCNTL 0x031a
663#define REG_EMSCRFIFOBCNTH 0x031b
664
665/* SPI Burst Cnt Status, default value: 0x00 */
666#define REG_SPIBURSTCNT 0x031e
667
668/* SPI Burst Status and SWRST, default value: 0x00 */
669#define REG_SPIBURSTSTAT 0x0322
670#define BIT_SPIBURSTSTAT_SPI_HDCPRST BIT(7)
671#define BIT_SPIBURSTSTAT_SPI_CBUSRST BIT(6)
672#define BIT_SPIBURSTSTAT_SPI_SRST BIT(5)
673#define BIT_SPIBURSTSTAT_EMSC_NORMAL_MODE BIT(0)
674
675/* E-MSC 1st Interrupt, default value: 0x00 */
676#define REG_EMSCINTR 0x0323
677#define BIT_EMSCINTR_EMSC_XFIFO_EMPTY BIT(7)
678#define BIT_EMSCINTR_EMSC_XMIT_ACK_TOUT BIT(6)
679#define BIT_EMSCINTR_EMSC_RFIFO_READ_ERR BIT(5)
680#define BIT_EMSCINTR_EMSC_XFIFO_WRITE_ERR BIT(4)
681#define BIT_EMSCINTR_EMSC_COMMA_CHAR_ERR BIT(3)
682#define BIT_EMSCINTR_EMSC_XMIT_DONE BIT(2)
683#define BIT_EMSCINTR_EMSC_XMIT_GNT_TOUT BIT(1)
684#define BIT_EMSCINTR_SPI_DVLD BIT(0)
685
686/* E-MSC Interrupt Mask, default value: 0x00 */
687#define REG_EMSCINTRMASK 0x0324
688
689/* I2C E-MSC XMIT FIFO Write Port, default value: 0x00 */
690#define REG_EMSC_XMIT_WRITE_PORT 0x032a
691
692/* I2C E-MSC RCV FIFO Write Port, default value: 0x00 */
693#define REG_EMSC_RCV_READ_PORT 0x032b
694
695/* E-MSC 2nd Interrupt, default value: 0x00 */
696#define REG_EMSCINTR1 0x032c
697#define BIT_EMSCINTR1_EMSC_TRAINING_COMMA_ERR BIT(0)
698
699/* E-MSC Interrupt Mask, default value: 0x00 */
700#define REG_EMSCINTRMASK1 0x032d
701#define BIT_EMSCINTRMASK1_EMSC_INTRMASK1_0 BIT(0)
702
703/* MHL Top Ctl, default value: 0x00 */
704#define REG_MHL_TOP_CTL 0x0330
705#define BIT_MHL_TOP_CTL_MHL3_DOC_SEL BIT(7)
706#define BIT_MHL_TOP_CTL_MHL_PP_SEL BIT(6)
707#define MSK_MHL_TOP_CTL_IF_TIMING_CTL 0x03
708
709/* MHL DataPath 1st Ctl, default value: 0xbc */
710#define REG_MHL_DP_CTL0 0x0331
711#define BIT_MHL_DP_CTL0_DP_OE BIT(7)
712#define BIT_MHL_DP_CTL0_TX_OE_OVR BIT(6)
713#define MSK_MHL_DP_CTL0_TX_OE 0x3f
714
715/* MHL DataPath 2nd Ctl, default value: 0xbb */
716#define REG_MHL_DP_CTL1 0x0332
717#define MSK_MHL_DP_CTL1_CK_SWING_CTL 0xf0
718#define MSK_MHL_DP_CTL1_DT_SWING_CTL 0x0f
719
720/* MHL DataPath 3rd Ctl, default value: 0x2f */
721#define REG_MHL_DP_CTL2 0x0333
722#define BIT_MHL_DP_CTL2_CLK_BYPASS_EN BIT(7)
723#define MSK_MHL_DP_CTL2_DAMP_TERM_SEL 0x30
724#define MSK_MHL_DP_CTL2_CK_TERM_SEL 0x0c
725#define MSK_MHL_DP_CTL2_DT_TERM_SEL 0x03
726
727/* MHL DataPath 4th Ctl, default value: 0x48 */
728#define REG_MHL_DP_CTL3 0x0334
729#define MSK_MHL_DP_CTL3_DT_DRV_VNBC_CTL 0xf0
730#define MSK_MHL_DP_CTL3_DT_DRV_VNB_CTL 0x0f
731
732/* MHL DataPath 5th Ctl, default value: 0x48 */
733#define REG_MHL_DP_CTL4 0x0335
734#define MSK_MHL_DP_CTL4_CK_DRV_VNBC_CTL 0xf0
735#define MSK_MHL_DP_CTL4_CK_DRV_VNB_CTL 0x0f
736
737/* MHL DataPath 6th Ctl, default value: 0x3f */
738#define REG_MHL_DP_CTL5 0x0336
739#define BIT_MHL_DP_CTL5_RSEN_EN_OVR BIT(7)
740#define BIT_MHL_DP_CTL5_RSEN_EN BIT(6)
741#define MSK_MHL_DP_CTL5_DAMP_TERM_VGS_CTL 0x30
742#define MSK_MHL_DP_CTL5_CK_TERM_VGS_CTL 0x0c
743#define MSK_MHL_DP_CTL5_DT_TERM_VGS_CTL 0x03
744
745/* MHL PLL 1st Ctl, default value: 0x05 */
746#define REG_MHL_PLL_CTL0 0x0337
747#define BIT_MHL_PLL_CTL0_AUD_CLK_EN BIT(7)
748
749#define MSK_MHL_PLL_CTL0_AUD_CLK_RATIO 0x70
750#define VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_10 0x70
751#define VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_6 0x60
752#define VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_4 0x50
753#define VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_2 0x40
754#define VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_5 0x30
755#define VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_3 0x20
756#define VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_2_PRIME 0x10
757#define VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_1 0x00
758
759#define MSK_MHL_PLL_CTL0_HDMI_CLK_RATIO 0x0c
760#define VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_4X 0x0c
761#define VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_2X 0x08
762#define VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X 0x04
763#define VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_HALF_X 0x00
764
765#define BIT_MHL_PLL_CTL0_CRYSTAL_CLK_SEL BIT(1)
766#define BIT_MHL_PLL_CTL0_ZONE_MASK_OE BIT(0)
767
768/* MHL PLL 3rd Ctl, default value: 0x80 */
769#define REG_MHL_PLL_CTL2 0x0339
770#define BIT_MHL_PLL_CTL2_CLKDETECT_EN BIT(7)
771#define BIT_MHL_PLL_CTL2_MEAS_FVCO BIT(3)
772#define BIT_MHL_PLL_CTL2_PLL_FAST_LOCK BIT(2)
773#define MSK_MHL_PLL_CTL2_PLL_LF_SEL 0x03
774
775/* MHL CBUS 1st Ctl, default value: 0x12 */
776#define REG_MHL_CBUS_CTL0 0x0340
777#define BIT_MHL_CBUS_CTL0_CBUS_RGND_TEST_MODE BIT(7)
778
779#define MSK_MHL_CBUS_CTL0_CBUS_RGND_VTH_CTL 0x30
780#define VAL_MHL_CBUS_CTL0_CBUS_RGND_VBIAS_734 0x00
781#define VAL_MHL_CBUS_CTL0_CBUS_RGND_VBIAS_747 0x10
782#define VAL_MHL_CBUS_CTL0_CBUS_RGND_VBIAS_740 0x20
783#define VAL_MHL_CBUS_CTL0_CBUS_RGND_VBIAS_754 0x30
784
785#define MSK_MHL_CBUS_CTL0_CBUS_RES_TEST_SEL 0x0c
786
787#define MSK_MHL_CBUS_CTL0_CBUS_DRV_SEL 0x03
788#define VAL_MHL_CBUS_CTL0_CBUS_DRV_SEL_WEAKEST 0x00
789#define VAL_MHL_CBUS_CTL0_CBUS_DRV_SEL_WEAK 0x01
790#define VAL_MHL_CBUS_CTL0_CBUS_DRV_SEL_STRONG 0x02
791#define VAL_MHL_CBUS_CTL0_CBUS_DRV_SEL_STRONGEST 0x03
792
793/* MHL CBUS 2nd Ctl, default value: 0x03 */
794#define REG_MHL_CBUS_CTL1 0x0341
795#define MSK_MHL_CBUS_CTL1_CBUS_RGND_RES_CTL 0x07
796#define VAL_MHL_CBUS_CTL1_0888_OHM 0x00
797#define VAL_MHL_CBUS_CTL1_1115_OHM 0x04
798#define VAL_MHL_CBUS_CTL1_1378_OHM 0x07
799
800/* MHL CoC 1st Ctl, default value: 0xc3 */
801#define REG_MHL_COC_CTL0 0x0342
802#define BIT_MHL_COC_CTL0_COC_BIAS_EN BIT(7)
803#define MSK_MHL_COC_CTL0_COC_BIAS_CTL 0x70
804#define MSK_MHL_COC_CTL0_COC_TERM_CTL 0x07
805
806/* MHL CoC 2nd Ctl, default value: 0x87 */
807#define REG_MHL_COC_CTL1 0x0343
808#define BIT_MHL_COC_CTL1_COC_EN BIT(7)
809#define MSK_MHL_COC_CTL1_COC_DRV_CTL 0x3f
810
811/* MHL CoC 4th Ctl, default value: 0x00 */
812#define REG_MHL_COC_CTL3 0x0345
813#define BIT_MHL_COC_CTL3_COC_AECHO_EN BIT(0)
814
815/* MHL CoC 5th Ctl, default value: 0x28 */
816#define REG_MHL_COC_CTL4 0x0346
817#define MSK_MHL_COC_CTL4_COC_IF_CTL 0xf0
818#define MSK_MHL_COC_CTL4_COC_SLEW_CTL 0x0f
819
820/* MHL CoC 6th Ctl, default value: 0x0d */
821#define REG_MHL_COC_CTL5 0x0347
822
823/* MHL DoC 1st Ctl, default value: 0x18 */
824#define REG_MHL_DOC_CTL0 0x0349
825#define BIT_MHL_DOC_CTL0_DOC_RXDATA_EN BIT(7)
826#define MSK_MHL_DOC_CTL0_DOC_DM_TERM 0x38
827#define MSK_MHL_DOC_CTL0_DOC_OPMODE 0x06
828#define BIT_MHL_DOC_CTL0_DOC_RXBIAS_EN BIT(0)
829
830/* MHL DataPath 7th Ctl, default value: 0x2a */
831#define REG_MHL_DP_CTL6 0x0350
832#define BIT_MHL_DP_CTL6_DP_TAP2_SGN BIT(5)
833#define BIT_MHL_DP_CTL6_DP_TAP2_EN BIT(4)
834#define BIT_MHL_DP_CTL6_DP_TAP1_SGN BIT(3)
835#define BIT_MHL_DP_CTL6_DP_TAP1_EN BIT(2)
836#define BIT_MHL_DP_CTL6_DT_PREDRV_FEEDCAP_EN BIT(1)
837#define BIT_MHL_DP_CTL6_DP_PRE_POST_SEL BIT(0)
838
839/* MHL DataPath 8th Ctl, default value: 0x06 */
840#define REG_MHL_DP_CTL7 0x0351
841#define MSK_MHL_DP_CTL7_DT_DRV_VBIAS_CASCTL 0xf0
842#define MSK_MHL_DP_CTL7_DT_DRV_IREF_CTL 0x0f
843
844/* Tx Zone Ctl1, default value: 0x00 */
845#define REG_TX_ZONE_CTL1 0x0361
846#define VAL_TX_ZONE_CTL1_TX_ZONE_CTRL_MODE 0x08
847
848/* MHL3 Tx Zone Ctl, default value: 0x00 */
849#define REG_MHL3_TX_ZONE_CTL 0x0364
850#define BIT_MHL3_TX_ZONE_CTL_MHL2_INTPLT_ZONE_MANU_EN BIT(7)
851#define MSK_MHL3_TX_ZONE_CTL_MHL3_TX_ZONE 0x03
852
853#define MSK_TX_ZONE_CTL3_TX_ZONE 0x03
854#define VAL_TX_ZONE_CTL3_TX_ZONE_6GBPS 0x00
855#define VAL_TX_ZONE_CTL3_TX_ZONE_3GBPS 0x01
856#define VAL_TX_ZONE_CTL3_TX_ZONE_1_5GBPS 0x02
857
858/* HDCP Polling Control and Status, default value: 0x70 */
859#define REG_HDCP2X_POLL_CS 0x0391
860
861#define BIT_HDCP2X_POLL_CS_HDCP2X_MSG_SZ_CLR_OPTION BIT(6)
862#define BIT_HDCP2X_POLL_CS_HDCP2X_RPT_READY_CLR_OPTION BIT(5)
863#define BIT_HDCP2X_POLL_CS_HDCP2X_REAUTH_REQ_CLR_OPTION BIT(4)
864#define MSK_HDCP2X_POLL_CS_ 0x0c
865#define BIT_HDCP2X_POLL_CS_HDCP2X_DIS_POLL_GNT BIT(1)
866#define BIT_HDCP2X_POLL_CS_HDCP2X_DIS_POLL_EN BIT(0)
867
868/* HDCP Interrupt 0, default value: 0x00 */
869#define REG_HDCP2X_INTR0 0x0398
870
871/* HDCP Interrupt 0 Mask, default value: 0x00 */
872#define REG_HDCP2X_INTR0_MASK 0x0399
873
874/* HDCP General Control 0, default value: 0x02 */
875#define REG_HDCP2X_CTRL_0 0x03a0
876#define BIT_HDCP2X_CTRL_0_HDCP2X_ENCRYPT_EN BIT(7)
877#define BIT_HDCP2X_CTRL_0_HDCP2X_POLINT_SEL BIT(6)
878#define BIT_HDCP2X_CTRL_0_HDCP2X_POLINT_OVR BIT(5)
879#define BIT_HDCP2X_CTRL_0_HDCP2X_PRECOMPUTE BIT(4)
880#define BIT_HDCP2X_CTRL_0_HDCP2X_HDMIMODE BIT(3)
881#define BIT_HDCP2X_CTRL_0_HDCP2X_REPEATER BIT(2)
882#define BIT_HDCP2X_CTRL_0_HDCP2X_HDCPTX BIT(1)
883#define BIT_HDCP2X_CTRL_0_HDCP2X_EN BIT(0)
884
885/* HDCP General Control 1, default value: 0x08 */
886#define REG_HDCP2X_CTRL_1 0x03a1
887#define MSK_HDCP2X_CTRL_1_HDCP2X_REAUTH_MSK_3_0 0xf0
888#define BIT_HDCP2X_CTRL_1_HDCP2X_HPD_SW BIT(3)
889#define BIT_HDCP2X_CTRL_1_HDCP2X_HPD_OVR BIT(2)
890#define BIT_HDCP2X_CTRL_1_HDCP2X_CTL3MSK BIT(1)
891#define BIT_HDCP2X_CTRL_1_HDCP2X_REAUTH_SW BIT(0)
892
893/* HDCP Misc Control, default value: 0x00 */
894#define REG_HDCP2X_MISC_CTRL 0x03a5
895#define BIT_HDCP2X_MISC_CTRL_HDCP2X_RPT_SMNG_XFER_START BIT(4)
896#define BIT_HDCP2X_MISC_CTRL_HDCP2X_RPT_SMNG_WR_START BIT(3)
897#define BIT_HDCP2X_MISC_CTRL_HDCP2X_RPT_SMNG_WR BIT(2)
898#define BIT_HDCP2X_MISC_CTRL_HDCP2X_RPT_RCVID_RD_START BIT(1)
899#define BIT_HDCP2X_MISC_CTRL_HDCP2X_RPT_RCVID_RD BIT(0)
900
901/* HDCP RPT SMNG K, default value: 0x00 */
902#define REG_HDCP2X_RPT_SMNG_K 0x03a6
903
904/* HDCP RPT SMNG In, default value: 0x00 */
905#define REG_HDCP2X_RPT_SMNG_IN 0x03a7
906
907/* HDCP Auth Status, default value: 0x00 */
908#define REG_HDCP2X_AUTH_STAT 0x03aa
909
910/* HDCP RPT RCVID Out, default value: 0x00 */
911#define REG_HDCP2X_RPT_RCVID_OUT 0x03ac
912
913/* HDCP TP1, default value: 0x62 */
914#define REG_HDCP2X_TP1 0x03b4
915
916/* HDCP GP Out 0, default value: 0x00 */
917#define REG_HDCP2X_GP_OUT0 0x03c7
918
919/* HDCP Repeater RCVR ID 0, default value: 0x00 */
920#define REG_HDCP2X_RPT_RCVR_ID0 0x03d1
921
922/* HDCP DDCM Status, default value: 0x00 */
923#define REG_HDCP2X_DDCM_STS 0x03d8
924#define MSK_HDCP2X_DDCM_STS_HDCP2X_DDCM_ERR_STS_3_0 0xf0
925#define MSK_HDCP2X_DDCM_STS_HDCP2X_DDCM_CTL_CS_3_0 0x0f
926
927/* HDMI2MHL3 Control, default value: 0x0a */
928#define REG_M3_CTRL 0x03e0
929#define BIT_M3_CTRL_H2M_SWRST BIT(4)
930#define BIT_M3_CTRL_SW_MHL3_SEL BIT(3)
931#define BIT_M3_CTRL_M3AV_EN BIT(2)
932#define BIT_M3_CTRL_ENC_TMDS BIT(1)
933#define BIT_M3_CTRL_MHL3_MASTER_EN BIT(0)
934
935#define VAL_M3_CTRL_MHL1_2_VALUE (BIT_M3_CTRL_SW_MHL3_SEL \
936 | BIT_M3_CTRL_ENC_TMDS)
937#define VAL_M3_CTRL_MHL3_VALUE (BIT_M3_CTRL_SW_MHL3_SEL \
938 | BIT_M3_CTRL_M3AV_EN \
939 | BIT_M3_CTRL_ENC_TMDS \
940 | BIT_M3_CTRL_MHL3_MASTER_EN)
941
942/* HDMI2MHL3 Port0 Control, default value: 0x04 */
943#define REG_M3_P0CTRL 0x03e1
944#define BIT_M3_P0CTRL_MHL3_P0_HDCP_ENC_EN BIT(4)
945#define BIT_M3_P0CTRL_MHL3_P0_UNLIMIT_EN BIT(3)
946#define BIT_M3_P0CTRL_MHL3_P0_HDCP_EN BIT(2)
947#define BIT_M3_P0CTRL_MHL3_P0_PIXEL_MODE_PACKED BIT(1)
948#define BIT_M3_P0CTRL_MHL3_P0_PORT_EN BIT(0)
949
950#define REG_M3_POSTM 0x03e2
951#define MSK_M3_POSTM_RRP_DECODE 0xf8
952#define MSK_M3_POSTM_MHL3_P0_STM_ID 0x07
953
954/* HDMI2MHL3 Scramble Control, default value: 0x41 */
955#define REG_M3_SCTRL 0x03e6
956#define MSK_M3_SCTRL_MHL3_SR_LENGTH 0xf0
957#define BIT_M3_SCTRL_MHL3_SCRAMBLER_EN BIT(0)
958
959/* HSIC Div Ctl, default value: 0x05 */
960#define REG_DIV_CTL_MAIN 0x03f2
961#define MSK_DIV_CTL_MAIN_PRE_DIV_CTL_MAIN 0x1c
962#define MSK_DIV_CTL_MAIN_FB_DIV_CTL_MAIN 0x03
963
964/* MHL Capability 1st Byte, default value: 0x00 */
965#define REG_MHL_DEVCAP_0 0x0400
966
967/* MHL Interrupt 1st Byte, default value: 0x00 */
968#define REG_MHL_INT_0 0x0420
969
970/* Device Status 1st byte, default value: 0x00 */
971#define REG_MHL_STAT_0 0x0430
972
973/* CBUS Scratch Pad 1st Byte, default value: 0x00 */
974#define REG_MHL_SCRPAD_0 0x0440
975
976/* MHL Extended Capability 1st Byte, default value: 0x00 */
977#define REG_MHL_EXTDEVCAP_0 0x0480
978
979/* Device Extended Status 1st byte, default value: 0x00 */
980#define REG_MHL_EXTSTAT_0 0x0490
981
982/* TPI DTD Byte2, default value: 0x00 */
983#define REG_TPI_DTD_B2 0x0602
984
985#define VAL_TPI_QUAN_RANGE_LIMITED 0x01
986#define VAL_TPI_QUAN_RANGE_FULL 0x02
987#define VAL_TPI_FORMAT_RGB 0x00
988#define VAL_TPI_FORMAT_YCBCR444 0x01
989#define VAL_TPI_FORMAT_YCBCR422 0x02
990#define VAL_TPI_FORMAT_INTERNAL_RGB 0x03
991#define VAL_TPI_FORMAT(_fmt, _qr) \
992 (VAL_TPI_FORMAT_##_fmt | (VAL_TPI_QUAN_RANGE_##_qr << 2))
993
994/* Input Format, default value: 0x00 */
995#define REG_TPI_INPUT 0x0609
996#define BIT_TPI_INPUT_EXTENDEDBITMODE BIT(7)
997#define BIT_TPI_INPUT_ENDITHER BIT(6)
998#define MSK_TPI_INPUT_INPUT_QUAN_RANGE 0x0c
999#define MSK_TPI_INPUT_INPUT_FORMAT 0x03
1000
1001/* Output Format, default value: 0x00 */
1002#define REG_TPI_OUTPUT 0x060a
1003#define BIT_TPI_OUTPUT_CSCMODE709 BIT(4)
1004#define MSK_TPI_OUTPUT_OUTPUT_QUAN_RANGE 0x0c
1005#define MSK_TPI_OUTPUT_OUTPUT_FORMAT 0x03
1006
1007/* TPI AVI Check Sum, default value: 0x00 */
1008#define REG_TPI_AVI_CHSUM 0x060c
1009
1010/* TPI System Control, default value: 0x00 */
1011#define REG_TPI_SC 0x061a
1012#define BIT_TPI_SC_TPI_UPDATE_FLG BIT(7)
1013#define BIT_TPI_SC_TPI_REAUTH_CTL BIT(6)
1014#define BIT_TPI_SC_TPI_OUTPUT_MODE_1 BIT(5)
1015#define BIT_TPI_SC_REG_TMDS_OE_POWER_DOWN BIT(4)
1016#define BIT_TPI_SC_TPI_AV_MUTE BIT(3)
1017#define BIT_TPI_SC_DDC_GPU_REQUEST BIT(2)
1018#define BIT_TPI_SC_DDC_TPI_SW BIT(1)
1019#define BIT_TPI_SC_TPI_OUTPUT_MODE_0_HDMI BIT(0)
1020
1021/* TPI COPP Query Data, default value: 0x00 */
1022#define REG_TPI_COPP_DATA1 0x0629
1023#define BIT_TPI_COPP_DATA1_COPP_GPROT BIT(7)
1024#define BIT_TPI_COPP_DATA1_COPP_LPROT BIT(6)
1025#define MSK_TPI_COPP_DATA1_COPP_LINK_STATUS 0x30
1026#define VAL_TPI_COPP_LINK_STATUS_NORMAL 0x00
1027#define VAL_TPI_COPP_LINK_STATUS_LINK_LOST 0x10
1028#define VAL_TPI_COPP_LINK_STATUS_RENEGOTIATION_REQ 0x20
1029#define VAL_TPI_COPP_LINK_STATUS_LINK_SUSPENDED 0x30
1030#define BIT_TPI_COPP_DATA1_COPP_HDCP_REP BIT(3)
1031#define BIT_TPI_COPP_DATA1_COPP_CONNTYPE_0 BIT(2)
1032#define BIT_TPI_COPP_DATA1_COPP_PROTYPE BIT(1)
1033#define BIT_TPI_COPP_DATA1_COPP_CONNTYPE_1 BIT(0)
1034
1035/* TPI COPP Control Data, default value: 0x00 */
1036#define REG_TPI_COPP_DATA2 0x062a
1037#define BIT_TPI_COPP_DATA2_INTR_ENCRYPTION BIT(5)
1038#define BIT_TPI_COPP_DATA2_KSV_FORWARD BIT(4)
1039#define BIT_TPI_COPP_DATA2_INTERM_RI_CHECK_EN BIT(3)
1040#define BIT_TPI_COPP_DATA2_DOUBLE_RI_CHECK BIT(2)
1041#define BIT_TPI_COPP_DATA2_DDC_SHORT_RI_RD BIT(1)
1042#define BIT_TPI_COPP_DATA2_COPP_PROTLEVEL BIT(0)
1043
1044/* TPI Interrupt Enable, default value: 0x00 */
1045#define REG_TPI_INTR_EN 0x063c
1046
1047/* TPI Interrupt Status Low Byte, default value: 0x00 */
1048#define REG_TPI_INTR_ST0 0x063d
1049#define BIT_TPI_INTR_ST0_TPI_AUTH_CHNGE_STAT BIT(7)
1050#define BIT_TPI_INTR_ST0_TPI_V_RDY_STAT BIT(6)
1051#define BIT_TPI_INTR_ST0_TPI_COPP_CHNGE_STAT BIT(5)
1052#define BIT_TPI_INTR_ST0_KSV_FIFO_FIRST_STAT BIT(3)
1053#define BIT_TPI_INTR_ST0_READ_BKSV_BCAPS_DONE_STAT BIT(2)
1054#define BIT_TPI_INTR_ST0_READ_BKSV_BCAPS_ERR_STAT BIT(1)
1055#define BIT_TPI_INTR_ST0_READ_BKSV_ERR_STAT BIT(0)
1056
1057/* TPI DS BCAPS Status, default value: 0x00 */
1058#define REG_TPI_DS_BCAPS 0x0644
1059
1060/* TPI BStatus1, default value: 0x00 */
1061#define REG_TPI_BSTATUS1 0x0645
1062#define BIT_TPI_BSTATUS1_DS_DEV_EXCEED BIT(7)
1063#define MSK_TPI_BSTATUS1_DS_DEV_CNT 0x7f
1064
1065/* TPI BStatus2, default value: 0x10 */
1066#define REG_TPI_BSTATUS2 0x0646
1067#define MSK_TPI_BSTATUS2_DS_BSTATUS 0xe0
1068#define BIT_TPI_BSTATUS2_DS_HDMI_MODE BIT(4)
1069#define BIT_TPI_BSTATUS2_DS_CASC_EXCEED BIT(3)
1070#define MSK_TPI_BSTATUS2_DS_DEPTH 0x07
1071
1072/* TPI HW Optimization Control #3, default value: 0x00 */
1073#define REG_TPI_HW_OPT3 0x06bb
1074#define BIT_TPI_HW_OPT3_DDC_DEBUG BIT(7)
1075#define BIT_TPI_HW_OPT3_RI_CHECK_SKIP BIT(3)
1076#define BIT_TPI_HW_OPT3_TPI_DDC_BURST_MODE BIT(2)
1077#define MSK_TPI_HW_OPT3_TPI_DDC_REQ_LEVEL 0x03
1078
1079/* TPI Info Frame Select, default value: 0x00 */
1080#define REG_TPI_INFO_FSEL 0x06bf
1081#define BIT_TPI_INFO_FSEL_TPI_INFO_EN BIT(7)
1082#define BIT_TPI_INFO_FSEL_TPI_INFO_RPT BIT(6)
1083#define BIT_TPI_INFO_FSEL_TPI_INFO_READ_FLAG BIT(5)
1084#define MSK_TPI_INFO_FSEL_TPI_INFO_SEL 0x07
1085
1086/* TPI Info Byte #0, default value: 0x00 */
1087#define REG_TPI_INFO_B0 0x06c0
1088
1089/* CoC Status, default value: 0x00 */
1090#define REG_COC_STAT_0 0x0700
1091#define REG_COC_STAT_1 0x0701
1092#define REG_COC_STAT_2 0x0702
1093#define REG_COC_STAT_3 0x0703
1094#define REG_COC_STAT_4 0x0704
1095#define REG_COC_STAT_5 0x0705
1096
1097/* CoC 1st Ctl, default value: 0x40 */
1098#define REG_COC_CTL0 0x0710
1099
1100/* CoC 2nd Ctl, default value: 0x0a */
1101#define REG_COC_CTL1 0x0711
1102#define MSK_COC_CTL1_COC_CTRL1_7_6 0xc0
1103#define MSK_COC_CTL1_COC_CTRL1_5_0 0x3f
1104
1105/* CoC 3rd Ctl, default value: 0x14 */
1106#define REG_COC_CTL2 0x0712
1107#define MSK_COC_CTL2_COC_CTRL2_7_6 0xc0
1108#define MSK_COC_CTL2_COC_CTRL2_5_0 0x3f
1109
1110/* CoC 4th Ctl, default value: 0x40 */
1111#define REG_COC_CTL3 0x0713
1112#define BIT_COC_CTL3_COC_CTRL3_7 BIT(7)
1113#define MSK_COC_CTL3_COC_CTRL3_6_0 0x7f
1114
1115/* CoC 7th Ctl, default value: 0x00 */
1116#define REG_COC_CTL6 0x0716
1117#define BIT_COC_CTL6_COC_CTRL6_7 BIT(7)
1118#define BIT_COC_CTL6_COC_CTRL6_6 BIT(6)
1119#define MSK_COC_CTL6_COC_CTRL6_5_0 0x3f
1120
1121/* CoC 8th Ctl, default value: 0x06 */
1122#define REG_COC_CTL7 0x0717
1123#define BIT_COC_CTL7_COC_CTRL7_7 BIT(7)
1124#define BIT_COC_CTL7_COC_CTRL7_6 BIT(6)
1125#define BIT_COC_CTL7_COC_CTRL7_5 BIT(5)
1126#define MSK_COC_CTL7_COC_CTRL7_4_3 0x18
1127#define MSK_COC_CTL7_COC_CTRL7_2_0 0x07
1128
1129/* CoC 10th Ctl, default value: 0x00 */
1130#define REG_COC_CTL9 0x0719
1131
1132/* CoC 11th Ctl, default value: 0x00 */
1133#define REG_COC_CTLA 0x071a
1134
1135/* CoC 12th Ctl, default value: 0x00 */
1136#define REG_COC_CTLB 0x071b
1137
1138/* CoC 13th Ctl, default value: 0x0f */
1139#define REG_COC_CTLC 0x071c
1140
1141/* CoC 14th Ctl, default value: 0x0a */
1142#define REG_COC_CTLD 0x071d
1143#define BIT_COC_CTLD_COC_CTRLD_7 BIT(7)
1144#define MSK_COC_CTLD_COC_CTRLD_6_0 0x7f
1145
1146/* CoC 15th Ctl, default value: 0x0a */
1147#define REG_COC_CTLE 0x071e
1148#define BIT_COC_CTLE_COC_CTRLE_7 BIT(7)
1149#define MSK_COC_CTLE_COC_CTRLE_6_0 0x7f
1150
1151/* CoC 16th Ctl, default value: 0x00 */
1152#define REG_COC_CTLF 0x071f
1153#define MSK_COC_CTLF_COC_CTRLF_7_3 0xf8
1154#define MSK_COC_CTLF_COC_CTRLF_2_0 0x07
1155
1156/* CoC 18th Ctl, default value: 0x32 */
1157#define REG_COC_CTL11 0x0721
1158#define MSK_COC_CTL11_COC_CTRL11_7_4 0xf0
1159#define MSK_COC_CTL11_COC_CTRL11_3_0 0x0f
1160
1161/* CoC 21st Ctl, default value: 0x00 */
1162#define REG_COC_CTL14 0x0724
1163#define MSK_COC_CTL14_COC_CTRL14_7_4 0xf0
1164#define MSK_COC_CTL14_COC_CTRL14_3_0 0x0f
1165
1166/* CoC 22nd Ctl, default value: 0x00 */
1167#define REG_COC_CTL15 0x0725
1168#define BIT_COC_CTL15_COC_CTRL15_7 BIT(7)
1169#define MSK_COC_CTL15_COC_CTRL15_6_4 0x70
1170#define MSK_COC_CTL15_COC_CTRL15_3_0 0x0f
1171
1172/* CoC Interrupt, default value: 0x00 */
1173#define REG_COC_INTR 0x0726
1174
1175/* CoC Interrupt Mask, default value: 0x00 */
1176#define REG_COC_INTR_MASK 0x0727
1177#define BIT_COC_PLL_LOCK_STATUS_CHANGE BIT(0)
1178#define BIT_COC_CALIBRATION_DONE BIT(1)
1179
1180/* CoC Misc Ctl, default value: 0x00 */
1181#define REG_COC_MISC_CTL0 0x0728
1182#define BIT_COC_MISC_CTL0_FSM_MON BIT(7)
1183
1184/* CoC 24th Ctl, default value: 0x00 */
1185#define REG_COC_CTL17 0x072a
1186#define MSK_COC_CTL17_COC_CTRL17_7_4 0xf0
1187#define MSK_COC_CTL17_COC_CTRL17_3_0 0x0f
1188
1189/* CoC 25th Ctl, default value: 0x00 */
1190#define REG_COC_CTL18 0x072b
1191#define MSK_COC_CTL18_COC_CTRL18_7_4 0xf0
1192#define MSK_COC_CTL18_COC_CTRL18_3_0 0x0f
1193
1194/* CoC 26th Ctl, default value: 0x00 */
1195#define REG_COC_CTL19 0x072c
1196#define MSK_COC_CTL19_COC_CTRL19_7_4 0xf0
1197#define MSK_COC_CTL19_COC_CTRL19_3_0 0x0f
1198
1199/* CoC 27th Ctl, default value: 0x00 */
1200#define REG_COC_CTL1A 0x072d
1201#define MSK_COC_CTL1A_COC_CTRL1A_7_2 0xfc
1202#define MSK_COC_CTL1A_COC_CTRL1A_1_0 0x03
1203
1204/* DoC 9th Status, default value: 0x00 */
1205#define REG_DOC_STAT_8 0x0740
1206
1207/* DoC 10th Status, default value: 0x00 */
1208#define REG_DOC_STAT_9 0x0741
1209
1210/* DoC 5th CFG, default value: 0x00 */
1211#define REG_DOC_CFG4 0x074e
1212#define MSK_DOC_CFG4_DBG_STATE_DOC_FSM 0x0f
1213
1214/* DoC 1st Ctl, default value: 0x40 */
1215#define REG_DOC_CTL0 0x0751
1216
1217/* DoC 7th Ctl, default value: 0x00 */
1218#define REG_DOC_CTL6 0x0757
1219#define BIT_DOC_CTL6_DOC_CTRL6_7 BIT(7)
1220#define BIT_DOC_CTL6_DOC_CTRL6_6 BIT(6)
1221#define MSK_DOC_CTL6_DOC_CTRL6_5_4 0x30
1222#define MSK_DOC_CTL6_DOC_CTRL6_3_0 0x0f
1223
1224/* DoC 8th Ctl, default value: 0x00 */
1225#define REG_DOC_CTL7 0x0758
1226#define BIT_DOC_CTL7_DOC_CTRL7_7 BIT(7)
1227#define BIT_DOC_CTL7_DOC_CTRL7_6 BIT(6)
1228#define BIT_DOC_CTL7_DOC_CTRL7_5 BIT(5)
1229#define MSK_DOC_CTL7_DOC_CTRL7_4_3 0x18
1230#define MSK_DOC_CTL7_DOC_CTRL7_2_0 0x07
1231
1232/* DoC 9th Ctl, default value: 0x00 */
1233#define REG_DOC_CTL8 0x076c
1234#define BIT_DOC_CTL8_DOC_CTRL8_7 BIT(7)
1235#define MSK_DOC_CTL8_DOC_CTRL8_6_4 0x70
1236#define MSK_DOC_CTL8_DOC_CTRL8_3_2 0x0c
1237#define MSK_DOC_CTL8_DOC_CTRL8_1_0 0x03
1238
1239/* DoC 10th Ctl, default value: 0x00 */
1240#define REG_DOC_CTL9 0x076d
1241
1242/* DoC 11th Ctl, default value: 0x00 */
1243#define REG_DOC_CTLA 0x076e
1244
1245/* DoC 15th Ctl, default value: 0x00 */
1246#define REG_DOC_CTLE 0x0772
1247#define BIT_DOC_CTLE_DOC_CTRLE_7 BIT(7)
1248#define BIT_DOC_CTLE_DOC_CTRLE_6 BIT(6)
1249#define MSK_DOC_CTLE_DOC_CTRLE_5_4 0x30
1250#define MSK_DOC_CTLE_DOC_CTRLE_3_0 0x0f
1251
1252/* Interrupt Mask 1st, default value: 0x00 */
1253#define REG_MHL_INT_0_MASK 0x0580
1254
1255/* Interrupt Mask 2nd, default value: 0x00 */
1256#define REG_MHL_INT_1_MASK 0x0581
1257
1258/* Interrupt Mask 3rd, default value: 0x00 */
1259#define REG_MHL_INT_2_MASK 0x0582
1260
1261/* Interrupt Mask 4th, default value: 0x00 */
1262#define REG_MHL_INT_3_MASK 0x0583
1263
1264/* MDT Receive Time Out, default value: 0x00 */
1265#define REG_MDT_RCV_TIMEOUT 0x0584
1266
1267/* MDT Transmit Time Out, default value: 0x00 */
1268#define REG_MDT_XMIT_TIMEOUT 0x0585
1269
1270/* MDT Receive Control, default value: 0x00 */
1271#define REG_MDT_RCV_CTRL 0x0586
1272#define BIT_MDT_RCV_CTRL_MDT_RCV_EN BIT(7)
1273#define BIT_MDT_RCV_CTRL_MDT_DELAY_RCV_EN BIT(6)
1274#define BIT_MDT_RCV_CTRL_MDT_RFIFO_OVER_WR_EN BIT(4)
1275#define BIT_MDT_RCV_CTRL_MDT_XFIFO_OVER_WR_EN BIT(3)
1276#define BIT_MDT_RCV_CTRL_MDT_DISABLE BIT(2)
1277#define BIT_MDT_RCV_CTRL_MDT_RFIFO_CLR_ALL BIT(1)
1278#define BIT_MDT_RCV_CTRL_MDT_RFIFO_CLR_CUR BIT(0)
1279
1280/* MDT Receive Read Port, default value: 0x00 */
1281#define REG_MDT_RCV_READ_PORT 0x0587
1282
1283/* MDT Transmit Control, default value: 0x70 */
1284#define REG_MDT_XMIT_CTRL 0x0588
1285#define BIT_MDT_XMIT_CTRL_MDT_XMIT_EN BIT(7)
1286#define BIT_MDT_XMIT_CTRL_MDT_XMIT_CMD_MERGE_EN BIT(6)
1287#define BIT_MDT_XMIT_CTRL_MDT_XMIT_FIXED_BURST_LEN BIT(5)
1288#define BIT_MDT_XMIT_CTRL_MDT_XMIT_FIXED_AID BIT(4)
1289#define BIT_MDT_XMIT_CTRL_MDT_XMIT_SINGLE_RUN_EN BIT(3)
1290#define BIT_MDT_XMIT_CTRL_MDT_CLR_ABORT_WAIT BIT(2)
1291#define BIT_MDT_XMIT_CTRL_MDT_XFIFO_CLR_ALL BIT(1)
1292#define BIT_MDT_XMIT_CTRL_MDT_XFIFO_CLR_CUR BIT(0)
1293
1294/* MDT Receive WRITE Port, default value: 0x00 */
1295#define REG_MDT_XMIT_WRITE_PORT 0x0589
1296
1297/* MDT RFIFO Status, default value: 0x00 */
1298#define REG_MDT_RFIFO_STAT 0x058a
1299#define MSK_MDT_RFIFO_STAT_MDT_RFIFO_CNT 0xe0
1300#define MSK_MDT_RFIFO_STAT_MDT_RFIFO_CUR_BYTE_CNT 0x1f
1301
1302/* MDT XFIFO Status, default value: 0x80 */
1303#define REG_MDT_XFIFO_STAT 0x058b
1304#define MSK_MDT_XFIFO_STAT_MDT_XFIFO_LEVEL_AVAIL 0xe0
1305#define BIT_MDT_XFIFO_STAT_MDT_XMIT_PRE_HS_EN BIT(4)
1306#define MSK_MDT_XFIFO_STAT_MDT_WRITE_BURST_LEN 0x0f
1307
1308/* MDT Interrupt 0, default value: 0x0c */
1309#define REG_MDT_INT_0 0x058c
1310#define BIT_MDT_RFIFO_DATA_RDY BIT(0)
1311#define BIT_MDT_IDLE_AFTER_HAWB_DISABLE BIT(2)
1312#define BIT_MDT_XFIFO_EMPTY BIT(3)
1313
1314/* MDT Interrupt 0 Mask, default value: 0x00 */
1315#define REG_MDT_INT_0_MASK 0x058d
1316
1317/* MDT Interrupt 1, default value: 0x00 */
1318#define REG_MDT_INT_1 0x058e
1319#define BIT_MDT_RCV_TIMEOUT BIT(0)
1320#define BIT_MDT_RCV_SM_ABORT_PKT_RCVD BIT(1)
1321#define BIT_MDT_RCV_SM_ERROR BIT(2)
1322#define BIT_MDT_XMIT_TIMEOUT BIT(5)
1323#define BIT_MDT_XMIT_SM_ABORT_PKT_RCVD BIT(6)
1324#define BIT_MDT_XMIT_SM_ERROR BIT(7)
1325
1326/* MDT Interrupt 1 Mask, default value: 0x00 */
1327#define REG_MDT_INT_1_MASK 0x058f
1328
1329/* CBUS Vendor ID, default value: 0x01 */
1330#define REG_CBUS_VENDOR_ID 0x0590
1331
1332/* CBUS Connection Status, default value: 0x00 */
1333#define REG_CBUS_STATUS 0x0591
1334#define BIT_CBUS_STATUS_MHL_CABLE_PRESENT BIT(4)
1335#define BIT_CBUS_STATUS_MSC_HB_SUCCESS BIT(3)
1336#define BIT_CBUS_STATUS_CBUS_HPD BIT(2)
1337#define BIT_CBUS_STATUS_MHL_MODE BIT(1)
1338#define BIT_CBUS_STATUS_CBUS_CONNECTED BIT(0)
1339
1340/* CBUS Interrupt 1st, default value: 0x00 */
1341#define REG_CBUS_INT_0 0x0592
1342#define BIT_CBUS_MSC_MT_DONE_NACK BIT(7)
1343#define BIT_CBUS_MSC_MR_SET_INT BIT(6)
1344#define BIT_CBUS_MSC_MR_WRITE_BURST BIT(5)
1345#define BIT_CBUS_MSC_MR_MSC_MSG BIT(4)
1346#define BIT_CBUS_MSC_MR_WRITE_STAT BIT(3)
1347#define BIT_CBUS_HPD_CHG BIT(2)
1348#define BIT_CBUS_MSC_MT_DONE BIT(1)
1349#define BIT_CBUS_CNX_CHG BIT(0)
1350
1351/* CBUS Interrupt Mask 1st, default value: 0x00 */
1352#define REG_CBUS_INT_0_MASK 0x0593
1353
1354/* CBUS Interrupt 2nd, default value: 0x00 */
1355#define REG_CBUS_INT_1 0x0594
1356#define BIT_CBUS_CMD_ABORT BIT(6)
1357#define BIT_CBUS_MSC_ABORT_RCVD BIT(3)
1358#define BIT_CBUS_DDC_ABORT BIT(2)
1359#define BIT_CBUS_CEC_ABORT BIT(1)
1360
1361/* CBUS Interrupt Mask 2nd, default value: 0x00 */
1362#define REG_CBUS_INT_1_MASK 0x0595
1363
1364/* CBUS DDC Abort Interrupt, default value: 0x00 */
1365#define REG_DDC_ABORT_INT 0x0598
1366
1367/* CBUS DDC Abort Interrupt Mask, default value: 0x00 */
1368#define REG_DDC_ABORT_INT_MASK 0x0599
1369
1370/* CBUS MSC Requester Abort Interrupt, default value: 0x00 */
1371#define REG_MSC_MT_ABORT_INT 0x059a
1372
1373/* CBUS MSC Requester Abort Interrupt Mask, default value: 0x00 */
1374#define REG_MSC_MT_ABORT_INT_MASK 0x059b
1375
1376/* CBUS MSC Responder Abort Interrupt, default value: 0x00 */
1377#define REG_MSC_MR_ABORT_INT 0x059c
1378
1379/* CBUS MSC Responder Abort Interrupt Mask, default value: 0x00 */
1380#define REG_MSC_MR_ABORT_INT_MASK 0x059d
1381
1382/* CBUS RX DISCOVERY interrupt, default value: 0x00 */
1383#define REG_CBUS_RX_DISC_INT0 0x059e
1384
1385/* CBUS RX DISCOVERY Interrupt Mask, default value: 0x00 */
1386#define REG_CBUS_RX_DISC_INT0_MASK 0x059f
1387
1388/* CBUS_Link_Layer Control #8, default value: 0x00 */
1389#define REG_CBUS_LINK_CTRL_8 0x05a7
1390
1391/* MDT State Machine Status, default value: 0x00 */
1392#define REG_MDT_SM_STAT 0x05b5
1393#define MSK_MDT_SM_STAT_MDT_RCV_STATE 0xf0
1394#define MSK_MDT_SM_STAT_MDT_XMIT_STATE 0x0f
1395
1396/* CBUS MSC command trigger, default value: 0x00 */
1397#define REG_MSC_COMMAND_START 0x05b8
1398#define BIT_MSC_COMMAND_START_DEBUG BIT(5)
1399#define BIT_MSC_COMMAND_START_WRITE_BURST BIT(4)
1400#define BIT_MSC_COMMAND_START_WRITE_STAT BIT(3)
1401#define BIT_MSC_COMMAND_START_READ_DEVCAP BIT(2)
1402#define BIT_MSC_COMMAND_START_MSC_MSG BIT(1)
1403#define BIT_MSC_COMMAND_START_PEER BIT(0)
1404
1405/* CBUS MSC Command/Offset, default value: 0x00 */
1406#define REG_MSC_CMD_OR_OFFSET 0x05b9
1407
1408/* CBUS MSC Transmit Data */
1409#define REG_MSC_1ST_TRANSMIT_DATA 0x05ba
1410#define REG_MSC_2ND_TRANSMIT_DATA 0x05bb
1411
1412/* CBUS MSC Requester Received Data */
1413#define REG_MSC_MT_RCVD_DATA0 0x05bc
1414#define REG_MSC_MT_RCVD_DATA1 0x05bd
1415
1416/* CBUS MSC Responder MSC_MSG Received Data */
1417#define REG_MSC_MR_MSC_MSG_RCVD_1ST_DATA 0x05bf
1418#define REG_MSC_MR_MSC_MSG_RCVD_2ND_DATA 0x05c0
1419
1420/* CBUS MSC Heartbeat Control, default value: 0x27 */
1421#define REG_MSC_HEARTBEAT_CTRL 0x05c4
1422#define BIT_MSC_HEARTBEAT_CTRL_MSC_HB_EN BIT(7)
1423#define MSK_MSC_HEARTBEAT_CTRL_MSC_HB_FAIL_LIMIT 0x70
1424#define MSK_MSC_HEARTBEAT_CTRL_MSC_HB_PERIOD_MSB 0x0f
1425
1426/* CBUS MSC Compatibility Control, default value: 0x02 */
1427#define REG_CBUS_MSC_COMPAT_CTRL 0x05c7
1428#define BIT_CBUS_MSC_COMPAT_CTRL_XDEVCAP_EN BIT(7)
1429#define BIT_CBUS_MSC_COMPAT_CTRL_DISABLE_MSC_ON_CBUS BIT(6)
1430#define BIT_CBUS_MSC_COMPAT_CTRL_DISABLE_DDC_ON_CBUS BIT(5)
1431#define BIT_CBUS_MSC_COMPAT_CTRL_DISABLE_GET_DDC_ERRORCODE BIT(3)
1432#define BIT_CBUS_MSC_COMPAT_CTRL_DISABLE_GET_VS1_ERRORCODE BIT(2)
1433
1434/* CBUS3 Converter Control, default value: 0x24 */
1435#define REG_CBUS3_CNVT 0x05dc
1436#define MSK_CBUS3_CNVT_CBUS3_RETRYLMT 0xf0
1437#define MSK_CBUS3_CNVT_CBUS3_PEERTOUT_SEL 0x0c
1438#define BIT_CBUS3_CNVT_TEARCBUS_EN BIT(1)
1439#define BIT_CBUS3_CNVT_CBUS3CNVT_EN BIT(0)
1440
1441/* Discovery Control1, default value: 0x24 */
1442#define REG_DISC_CTRL1 0x05e0
1443#define BIT_DISC_CTRL1_CBUS_INTR_EN BIT(7)
1444#define BIT_DISC_CTRL1_HB_ONLY BIT(6)
1445#define MSK_DISC_CTRL1_DISC_ATT 0x30
1446#define MSK_DISC_CTRL1_DISC_CYC 0x0c
1447#define BIT_DISC_CTRL1_DISC_EN BIT(0)
1448
1449#define VAL_PUP_OFF 0
1450#define VAL_PUP_20K 1
1451#define VAL_PUP_5K 2
1452
1453/* Discovery Control4, default value: 0x80 */
1454#define REG_DISC_CTRL4 0x05e3
1455#define MSK_DISC_CTRL4_CBUSDISC_PUP_SEL 0xc0
1456#define MSK_DISC_CTRL4_CBUSIDLE_PUP_SEL 0x30
1457#define VAL_DISC_CTRL4(pup_disc, pup_idle) (((pup_disc) << 6) | (pup_idle << 4))
1458
1459/* Discovery Control5, default value: 0x03 */
1460#define REG_DISC_CTRL5 0x05e4
1461#define BIT_DISC_CTRL5_DSM_OVRIDE BIT(3)
1462#define MSK_DISC_CTRL5_CBUSMHL_PUP_SEL 0x03
1463
1464/* Discovery Control8, default value: 0x81 */
1465#define REG_DISC_CTRL8 0x05e7
1466#define BIT_DISC_CTRL8_NOMHLINT_CLR_BYPASS BIT(7)
1467#define BIT_DISC_CTRL8_DELAY_CBUS_INTR_EN BIT(0)
1468
1469/* Discovery Control9, default value: 0x54 */
1470#define REG_DISC_CTRL9 0x05e8
1471#define BIT_DISC_CTRL9_MHL3_RSEN_BYP BIT(7)
1472#define BIT_DISC_CTRL9_MHL3DISC_EN BIT(6)
1473#define BIT_DISC_CTRL9_WAKE_DRVFLT BIT(4)
1474#define BIT_DISC_CTRL9_NOMHL_EST BIT(3)
1475#define BIT_DISC_CTRL9_DISC_PULSE_PROCEED BIT(2)
1476#define BIT_DISC_CTRL9_WAKE_PULSE_BYPASS BIT(1)
1477#define BIT_DISC_CTRL9_VBUS_OUTPUT_CAPABILITY_SRC BIT(0)
1478
1479/* Discovery Status1, default value: 0x00 */
1480#define REG_DISC_STAT1 0x05eb
1481#define BIT_DISC_STAT1_PSM_OVRIDE BIT(5)
1482#define MSK_DISC_STAT1_DISC_SM 0x0f
1483
1484/* Discovery Status2, default value: 0x00 */
1485#define REG_DISC_STAT2 0x05ec
1486#define BIT_DISC_STAT2_CBUS_OE_POL BIT(6)
1487#define BIT_DISC_STAT2_CBUS_SATUS BIT(5)
1488#define BIT_DISC_STAT2_RSEN BIT(4)
1489
1490#define MSK_DISC_STAT2_MHL_VRSN 0x0c
1491#define VAL_DISC_STAT2_DEFAULT 0x00
1492#define VAL_DISC_STAT2_MHL1_2 0x04
1493#define VAL_DISC_STAT2_MHL3 0x08
1494#define VAL_DISC_STAT2_RESERVED 0x0c
1495
1496#define MSK_DISC_STAT2_RGND 0x03
1497#define VAL_RGND_OPEN 0x00
1498#define VAL_RGND_2K 0x01
1499#define VAL_RGND_1K 0x02
1500#define VAL_RGND_SHORT 0x03
1501
1502/* Interrupt CBUS_reg1 INTR0, default value: 0x00 */
1503#define REG_CBUS_DISC_INTR0 0x05ed
1504#define BIT_RGND_READY_INT BIT(6)
1505#define BIT_CBUS_MHL12_DISCON_INT BIT(5)
1506#define BIT_CBUS_MHL3_DISCON_INT BIT(4)
1507#define BIT_NOT_MHL_EST_INT BIT(3)
1508#define BIT_MHL_EST_INT BIT(2)
1509#define BIT_MHL3_EST_INT BIT(1)
1510#define VAL_CBUS_MHL_DISCON (BIT_CBUS_MHL12_DISCON_INT \
1511 | BIT_CBUS_MHL3_DISCON_INT \
1512 | BIT_NOT_MHL_EST_INT)
1513
1514/* Interrupt CBUS_reg1 INTR0 Mask, default value: 0x00 */
1515#define REG_CBUS_DISC_INTR0_MASK 0x05ee
1516
1517#endif /* __SIL_SII8620_H__ */