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1/*
2 * Copyright (C) 2014 Traphandler
3 * Copyright (C) 2014 Free Electrons
4 * Copyright (C) 2014 Atmel
5 *
6 * Author: Jean-Jacques Hiblot <jjhiblot@traphandler.com>
7 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#include <linux/clk.h>
23#include <linux/irq.h>
24#include <linux/irqchip.h>
25#include <linux/module.h>
26#include <linux/pm_runtime.h>
27
28#include "atmel_hlcdc_dc.h"
29
30#define ATMEL_HLCDC_LAYER_IRQS_OFFSET 8
31
32static const struct atmel_hlcdc_layer_desc atmel_hlcdc_at91sam9n12_layers[] = {
33 {
34 .name = "base",
35 .formats = &atmel_hlcdc_plane_rgb_formats,
36 .regs_offset = 0x40,
37 .id = 0,
38 .type = ATMEL_HLCDC_BASE_LAYER,
39 .nconfigs = 5,
40 .layout = {
41 .xstride = { 2 },
42 .default_color = 3,
43 .general_config = 4,
44 },
45 },
46};
47
48static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_at91sam9n12 = {
49 .min_width = 0,
50 .min_height = 0,
51 .max_width = 1280,
52 .max_height = 860,
53 .nlayers = ARRAY_SIZE(atmel_hlcdc_at91sam9n12_layers),
54 .layers = atmel_hlcdc_at91sam9n12_layers,
55};
56
57static const struct atmel_hlcdc_layer_desc atmel_hlcdc_at91sam9x5_layers[] = {
58 {
59 .name = "base",
60 .formats = &atmel_hlcdc_plane_rgb_formats,
61 .regs_offset = 0x40,
62 .id = 0,
63 .type = ATMEL_HLCDC_BASE_LAYER,
64 .nconfigs = 5,
65 .layout = {
66 .xstride = { 2 },
67 .default_color = 3,
68 .general_config = 4,
69 .disc_pos = 5,
70 .disc_size = 6,
71 },
72 },
73 {
74 .name = "overlay1",
75 .formats = &atmel_hlcdc_plane_rgb_formats,
76 .regs_offset = 0x100,
77 .id = 1,
78 .type = ATMEL_HLCDC_OVERLAY_LAYER,
79 .nconfigs = 10,
80 .layout = {
81 .pos = 2,
82 .size = 3,
83 .xstride = { 4 },
84 .pstride = { 5 },
85 .default_color = 6,
86 .chroma_key = 7,
87 .chroma_key_mask = 8,
88 .general_config = 9,
89 },
90 },
91 {
92 .name = "high-end-overlay",
93 .formats = &atmel_hlcdc_plane_rgb_and_yuv_formats,
94 .regs_offset = 0x280,
95 .id = 2,
96 .type = ATMEL_HLCDC_OVERLAY_LAYER,
97 .nconfigs = 17,
98 .layout = {
99 .pos = 2,
100 .size = 3,
101 .memsize = 4,
102 .xstride = { 5, 7 },
103 .pstride = { 6, 8 },
104 .default_color = 9,
105 .chroma_key = 10,
106 .chroma_key_mask = 11,
107 .general_config = 12,
108 .csc = 14,
109 },
110 },
111 {
112 .name = "cursor",
113 .formats = &atmel_hlcdc_plane_rgb_formats,
114 .regs_offset = 0x340,
115 .id = 3,
116 .type = ATMEL_HLCDC_CURSOR_LAYER,
117 .nconfigs = 10,
118 .max_width = 128,
119 .max_height = 128,
120 .layout = {
121 .pos = 2,
122 .size = 3,
123 .xstride = { 4 },
124 .default_color = 6,
125 .chroma_key = 7,
126 .chroma_key_mask = 8,
127 .general_config = 9,
128 },
129 },
130};
131
132static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_at91sam9x5 = {
133 .min_width = 0,
134 .min_height = 0,
135 .max_width = 800,
136 .max_height = 600,
137 .nlayers = ARRAY_SIZE(atmel_hlcdc_at91sam9x5_layers),
138 .layers = atmel_hlcdc_at91sam9x5_layers,
139};
140
141static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sama5d3_layers[] = {
142 {
143 .name = "base",
144 .formats = &atmel_hlcdc_plane_rgb_formats,
145 .regs_offset = 0x40,
146 .id = 0,
147 .type = ATMEL_HLCDC_BASE_LAYER,
148 .nconfigs = 7,
149 .layout = {
150 .xstride = { 2 },
151 .default_color = 3,
152 .general_config = 4,
153 .disc_pos = 5,
154 .disc_size = 6,
155 },
156 },
157 {
158 .name = "overlay1",
159 .formats = &atmel_hlcdc_plane_rgb_formats,
160 .regs_offset = 0x140,
161 .id = 1,
162 .type = ATMEL_HLCDC_OVERLAY_LAYER,
163 .nconfigs = 10,
164 .layout = {
165 .pos = 2,
166 .size = 3,
167 .xstride = { 4 },
168 .pstride = { 5 },
169 .default_color = 6,
170 .chroma_key = 7,
171 .chroma_key_mask = 8,
172 .general_config = 9,
173 },
174 },
175 {
176 .name = "overlay2",
177 .formats = &atmel_hlcdc_plane_rgb_formats,
178 .regs_offset = 0x240,
179 .id = 2,
180 .type = ATMEL_HLCDC_OVERLAY_LAYER,
181 .nconfigs = 10,
182 .layout = {
183 .pos = 2,
184 .size = 3,
185 .xstride = { 4 },
186 .pstride = { 5 },
187 .default_color = 6,
188 .chroma_key = 7,
189 .chroma_key_mask = 8,
190 .general_config = 9,
191 },
192 },
193 {
194 .name = "high-end-overlay",
195 .formats = &atmel_hlcdc_plane_rgb_and_yuv_formats,
196 .regs_offset = 0x340,
197 .id = 3,
198 .type = ATMEL_HLCDC_OVERLAY_LAYER,
199 .nconfigs = 42,
200 .layout = {
201 .pos = 2,
202 .size = 3,
203 .memsize = 4,
204 .xstride = { 5, 7 },
205 .pstride = { 6, 8 },
206 .default_color = 9,
207 .chroma_key = 10,
208 .chroma_key_mask = 11,
209 .general_config = 12,
210 .csc = 14,
211 },
212 },
213 {
214 .name = "cursor",
215 .formats = &atmel_hlcdc_plane_rgb_formats,
216 .regs_offset = 0x440,
217 .id = 4,
218 .type = ATMEL_HLCDC_CURSOR_LAYER,
219 .nconfigs = 10,
220 .max_width = 128,
221 .max_height = 128,
222 .layout = {
223 .pos = 2,
224 .size = 3,
225 .xstride = { 4 },
226 .pstride = { 5 },
227 .default_color = 6,
228 .chroma_key = 7,
229 .chroma_key_mask = 8,
230 .general_config = 9,
231 },
232 },
233};
234
235static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_sama5d3 = {
236 .min_width = 0,
237 .min_height = 0,
238 .max_width = 2048,
239 .max_height = 2048,
240 .nlayers = ARRAY_SIZE(atmel_hlcdc_sama5d3_layers),
241 .layers = atmel_hlcdc_sama5d3_layers,
242};
243
244static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sama5d4_layers[] = {
245 {
246 .name = "base",
247 .formats = &atmel_hlcdc_plane_rgb_formats,
248 .regs_offset = 0x40,
249 .id = 0,
250 .type = ATMEL_HLCDC_BASE_LAYER,
251 .nconfigs = 7,
252 .layout = {
253 .xstride = { 2 },
254 .default_color = 3,
255 .general_config = 4,
256 .disc_pos = 5,
257 .disc_size = 6,
258 },
259 },
260 {
261 .name = "overlay1",
262 .formats = &atmel_hlcdc_plane_rgb_formats,
263 .regs_offset = 0x140,
264 .id = 1,
265 .type = ATMEL_HLCDC_OVERLAY_LAYER,
266 .nconfigs = 10,
267 .layout = {
268 .pos = 2,
269 .size = 3,
270 .xstride = { 4 },
271 .pstride = { 5 },
272 .default_color = 6,
273 .chroma_key = 7,
274 .chroma_key_mask = 8,
275 .general_config = 9,
276 },
277 },
278 {
279 .name = "overlay2",
280 .formats = &atmel_hlcdc_plane_rgb_formats,
281 .regs_offset = 0x240,
282 .id = 2,
283 .type = ATMEL_HLCDC_OVERLAY_LAYER,
284 .nconfigs = 10,
285 .layout = {
286 .pos = 2,
287 .size = 3,
288 .xstride = { 4 },
289 .pstride = { 5 },
290 .default_color = 6,
291 .chroma_key = 7,
292 .chroma_key_mask = 8,
293 .general_config = 9,
294 },
295 },
296 {
297 .name = "high-end-overlay",
298 .formats = &atmel_hlcdc_plane_rgb_and_yuv_formats,
299 .regs_offset = 0x340,
300 .id = 3,
301 .type = ATMEL_HLCDC_OVERLAY_LAYER,
302 .nconfigs = 42,
303 .layout = {
304 .pos = 2,
305 .size = 3,
306 .memsize = 4,
307 .xstride = { 5, 7 },
308 .pstride = { 6, 8 },
309 .default_color = 9,
310 .chroma_key = 10,
311 .chroma_key_mask = 11,
312 .general_config = 12,
313 .csc = 14,
314 },
315 },
316};
317
318static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_sama5d4 = {
319 .min_width = 0,
320 .min_height = 0,
321 .max_width = 2048,
322 .max_height = 2048,
323 .nlayers = ARRAY_SIZE(atmel_hlcdc_sama5d4_layers),
324 .layers = atmel_hlcdc_sama5d4_layers,
325};
326static const struct of_device_id atmel_hlcdc_of_match[] = {
327 {
328 .compatible = "atmel,at91sam9n12-hlcdc",
329 .data = &atmel_hlcdc_dc_at91sam9n12,
330 },
331 {
332 .compatible = "atmel,at91sam9x5-hlcdc",
333 .data = &atmel_hlcdc_dc_at91sam9x5,
334 },
335 {
336 .compatible = "atmel,sama5d2-hlcdc",
337 .data = &atmel_hlcdc_dc_sama5d4,
338 },
339 {
340 .compatible = "atmel,sama5d3-hlcdc",
341 .data = &atmel_hlcdc_dc_sama5d3,
342 },
343 {
344 .compatible = "atmel,sama5d4-hlcdc",
345 .data = &atmel_hlcdc_dc_sama5d4,
346 },
347 { /* sentinel */ },
348};
349MODULE_DEVICE_TABLE(of, atmel_hlcdc_of_match);
350
351int atmel_hlcdc_dc_mode_valid(struct atmel_hlcdc_dc *dc,
352 struct drm_display_mode *mode)
353{
354 int vfront_porch = mode->vsync_start - mode->vdisplay;
355 int vback_porch = mode->vtotal - mode->vsync_end;
356 int vsync_len = mode->vsync_end - mode->vsync_start;
357 int hfront_porch = mode->hsync_start - mode->hdisplay;
358 int hback_porch = mode->htotal - mode->hsync_end;
359 int hsync_len = mode->hsync_end - mode->hsync_start;
360
361 if (hsync_len > 0x40 || hsync_len < 1)
362 return MODE_HSYNC;
363
364 if (vsync_len > 0x40 || vsync_len < 1)
365 return MODE_VSYNC;
366
367 if (hfront_porch > 0x200 || hfront_porch < 1 ||
368 hback_porch > 0x200 || hback_porch < 1 ||
369 mode->hdisplay < 1)
370 return MODE_H_ILLEGAL;
371
372 if (vfront_porch > 0x40 || vfront_porch < 1 ||
373 vback_porch > 0x40 || vback_porch < 0 ||
374 mode->vdisplay < 1)
375 return MODE_V_ILLEGAL;
376
377 return MODE_OK;
378}
379
380static irqreturn_t atmel_hlcdc_dc_irq_handler(int irq, void *data)
381{
382 struct drm_device *dev = data;
383 struct atmel_hlcdc_dc *dc = dev->dev_private;
384 unsigned long status;
385 unsigned int imr, isr;
386 int i;
387
388 regmap_read(dc->hlcdc->regmap, ATMEL_HLCDC_IMR, &imr);
389 regmap_read(dc->hlcdc->regmap, ATMEL_HLCDC_ISR, &isr);
390 status = imr & isr;
391 if (!status)
392 return IRQ_NONE;
393
394 if (status & ATMEL_HLCDC_SOF)
395 atmel_hlcdc_crtc_irq(dc->crtc);
396
397 for (i = 0; i < ATMEL_HLCDC_MAX_LAYERS; i++) {
398 struct atmel_hlcdc_layer *layer = dc->layers[i];
399
400 if (!(ATMEL_HLCDC_LAYER_STATUS(i) & status) || !layer)
401 continue;
402
403 atmel_hlcdc_layer_irq(layer);
404 }
405
406 return IRQ_HANDLED;
407}
408
409static struct drm_framebuffer *atmel_hlcdc_fb_create(struct drm_device *dev,
410 struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd)
411{
412 return drm_fb_cma_create(dev, file_priv, mode_cmd);
413}
414
415static void atmel_hlcdc_fb_output_poll_changed(struct drm_device *dev)
416{
417 struct atmel_hlcdc_dc *dc = dev->dev_private;
418
419 if (dc->fbdev) {
420 drm_fbdev_cma_hotplug_event(dc->fbdev);
421 } else {
422 dc->fbdev = drm_fbdev_cma_init(dev, 24,
423 dev->mode_config.num_crtc,
424 dev->mode_config.num_connector);
425 if (IS_ERR(dc->fbdev))
426 dc->fbdev = NULL;
427 }
428}
429
430static const struct drm_mode_config_funcs mode_config_funcs = {
431 .fb_create = atmel_hlcdc_fb_create,
432 .output_poll_changed = atmel_hlcdc_fb_output_poll_changed,
433 .atomic_check = drm_atomic_helper_check,
434 .atomic_commit = drm_atomic_helper_commit,
435};
436
437static int atmel_hlcdc_dc_modeset_init(struct drm_device *dev)
438{
439 struct atmel_hlcdc_dc *dc = dev->dev_private;
440 struct atmel_hlcdc_planes *planes;
441 int ret;
442 int i;
443
444 drm_mode_config_init(dev);
445
446 ret = atmel_hlcdc_create_outputs(dev);
447 if (ret) {
448 dev_err(dev->dev, "failed to create panel: %d\n", ret);
449 return ret;
450 }
451
452 planes = atmel_hlcdc_create_planes(dev);
453 if (IS_ERR(planes)) {
454 dev_err(dev->dev, "failed to create planes\n");
455 return PTR_ERR(planes);
456 }
457
458 dc->planes = planes;
459
460 dc->layers[planes->primary->layer.desc->id] =
461 &planes->primary->layer;
462
463 if (planes->cursor)
464 dc->layers[planes->cursor->layer.desc->id] =
465 &planes->cursor->layer;
466
467 for (i = 0; i < planes->noverlays; i++)
468 dc->layers[planes->overlays[i]->layer.desc->id] =
469 &planes->overlays[i]->layer;
470
471 ret = atmel_hlcdc_crtc_create(dev);
472 if (ret) {
473 dev_err(dev->dev, "failed to create crtc\n");
474 return ret;
475 }
476
477 dev->mode_config.min_width = dc->desc->min_width;
478 dev->mode_config.min_height = dc->desc->min_height;
479 dev->mode_config.max_width = dc->desc->max_width;
480 dev->mode_config.max_height = dc->desc->max_height;
481 dev->mode_config.funcs = &mode_config_funcs;
482
483 return 0;
484}
485
486static int atmel_hlcdc_dc_load(struct drm_device *dev)
487{
488 struct platform_device *pdev = to_platform_device(dev->dev);
489 const struct of_device_id *match;
490 struct atmel_hlcdc_dc *dc;
491 int ret;
492
493 match = of_match_node(atmel_hlcdc_of_match, dev->dev->parent->of_node);
494 if (!match) {
495 dev_err(&pdev->dev, "invalid compatible string\n");
496 return -ENODEV;
497 }
498
499 if (!match->data) {
500 dev_err(&pdev->dev, "invalid hlcdc description\n");
501 return -EINVAL;
502 }
503
504 dc = devm_kzalloc(dev->dev, sizeof(*dc), GFP_KERNEL);
505 if (!dc)
506 return -ENOMEM;
507
508 dc->wq = alloc_ordered_workqueue("atmel-hlcdc-dc", 0);
509 if (!dc->wq)
510 return -ENOMEM;
511
512 dc->desc = match->data;
513 dc->hlcdc = dev_get_drvdata(dev->dev->parent);
514 dev->dev_private = dc;
515
516 ret = clk_prepare_enable(dc->hlcdc->periph_clk);
517 if (ret) {
518 dev_err(dev->dev, "failed to enable periph_clk\n");
519 goto err_destroy_wq;
520 }
521
522 pm_runtime_enable(dev->dev);
523
524 ret = drm_vblank_init(dev, 1);
525 if (ret < 0) {
526 dev_err(dev->dev, "failed to initialize vblank\n");
527 goto err_periph_clk_disable;
528 }
529
530 ret = atmel_hlcdc_dc_modeset_init(dev);
531 if (ret < 0) {
532 dev_err(dev->dev, "failed to initialize mode setting\n");
533 goto err_periph_clk_disable;
534 }
535
536 drm_mode_config_reset(dev);
537
538 pm_runtime_get_sync(dev->dev);
539 ret = drm_irq_install(dev, dc->hlcdc->irq);
540 pm_runtime_put_sync(dev->dev);
541 if (ret < 0) {
542 dev_err(dev->dev, "failed to install IRQ handler\n");
543 goto err_periph_clk_disable;
544 }
545
546 platform_set_drvdata(pdev, dev);
547
548 drm_kms_helper_poll_init(dev);
549
550 /* force connectors detection */
551 drm_helper_hpd_irq_event(dev);
552
553 return 0;
554
555err_periph_clk_disable:
556 pm_runtime_disable(dev->dev);
557 clk_disable_unprepare(dc->hlcdc->periph_clk);
558
559err_destroy_wq:
560 destroy_workqueue(dc->wq);
561
562 return ret;
563}
564
565static void atmel_hlcdc_dc_unload(struct drm_device *dev)
566{
567 struct atmel_hlcdc_dc *dc = dev->dev_private;
568
569 if (dc->fbdev)
570 drm_fbdev_cma_fini(dc->fbdev);
571 flush_workqueue(dc->wq);
572 drm_kms_helper_poll_fini(dev);
573 drm_mode_config_cleanup(dev);
574 drm_vblank_cleanup(dev);
575
576 pm_runtime_get_sync(dev->dev);
577 drm_irq_uninstall(dev);
578 pm_runtime_put_sync(dev->dev);
579
580 dev->dev_private = NULL;
581
582 pm_runtime_disable(dev->dev);
583 clk_disable_unprepare(dc->hlcdc->periph_clk);
584 destroy_workqueue(dc->wq);
585}
586
587static int atmel_hlcdc_dc_connector_plug_all(struct drm_device *dev)
588{
589 struct drm_connector *connector, *failed;
590 int ret;
591
592 mutex_lock(&dev->mode_config.mutex);
593 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
594 ret = drm_connector_register(connector);
595 if (ret) {
596 failed = connector;
597 goto err;
598 }
599 }
600 mutex_unlock(&dev->mode_config.mutex);
601 return 0;
602
603err:
604 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
605 if (failed == connector)
606 break;
607
608 drm_connector_unregister(connector);
609 }
610 mutex_unlock(&dev->mode_config.mutex);
611
612 return ret;
613}
614
615static void atmel_hlcdc_dc_connector_unplug_all(struct drm_device *dev)
616{
617 mutex_lock(&dev->mode_config.mutex);
618 drm_connector_unplug_all(dev);
619 mutex_unlock(&dev->mode_config.mutex);
620}
621
622static void atmel_hlcdc_dc_lastclose(struct drm_device *dev)
623{
624 struct atmel_hlcdc_dc *dc = dev->dev_private;
625
626 drm_fbdev_cma_restore_mode(dc->fbdev);
627}
628
629static int atmel_hlcdc_dc_irq_postinstall(struct drm_device *dev)
630{
631 struct atmel_hlcdc_dc *dc = dev->dev_private;
632 unsigned int cfg = 0;
633 int i;
634
635 /* Enable interrupts on activated layers */
636 for (i = 0; i < ATMEL_HLCDC_MAX_LAYERS; i++) {
637 if (dc->layers[i])
638 cfg |= ATMEL_HLCDC_LAYER_STATUS(i);
639 }
640
641 regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IER, cfg);
642
643 return 0;
644}
645
646static void atmel_hlcdc_dc_irq_uninstall(struct drm_device *dev)
647{
648 struct atmel_hlcdc_dc *dc = dev->dev_private;
649 unsigned int isr;
650
651 regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IDR, 0xffffffff);
652 regmap_read(dc->hlcdc->regmap, ATMEL_HLCDC_ISR, &isr);
653}
654
655static int atmel_hlcdc_dc_enable_vblank(struct drm_device *dev,
656 unsigned int pipe)
657{
658 struct atmel_hlcdc_dc *dc = dev->dev_private;
659
660 /* Enable SOF (Start Of Frame) interrupt for vblank counting */
661 regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IER, ATMEL_HLCDC_SOF);
662
663 return 0;
664}
665
666static void atmel_hlcdc_dc_disable_vblank(struct drm_device *dev,
667 unsigned int pipe)
668{
669 struct atmel_hlcdc_dc *dc = dev->dev_private;
670
671 regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IDR, ATMEL_HLCDC_SOF);
672}
673
674static const struct file_operations fops = {
675 .owner = THIS_MODULE,
676 .open = drm_open,
677 .release = drm_release,
678 .unlocked_ioctl = drm_ioctl,
679#ifdef CONFIG_COMPAT
680 .compat_ioctl = drm_compat_ioctl,
681#endif
682 .poll = drm_poll,
683 .read = drm_read,
684 .llseek = no_llseek,
685 .mmap = drm_gem_cma_mmap,
686};
687
688static struct drm_driver atmel_hlcdc_dc_driver = {
689 .driver_features = DRIVER_HAVE_IRQ | DRIVER_GEM |
690 DRIVER_MODESET | DRIVER_PRIME |
691 DRIVER_ATOMIC,
692 .lastclose = atmel_hlcdc_dc_lastclose,
693 .irq_handler = atmel_hlcdc_dc_irq_handler,
694 .irq_preinstall = atmel_hlcdc_dc_irq_uninstall,
695 .irq_postinstall = atmel_hlcdc_dc_irq_postinstall,
696 .irq_uninstall = atmel_hlcdc_dc_irq_uninstall,
697 .get_vblank_counter = drm_vblank_no_hw_counter,
698 .enable_vblank = atmel_hlcdc_dc_enable_vblank,
699 .disable_vblank = atmel_hlcdc_dc_disable_vblank,
700 .gem_free_object = drm_gem_cma_free_object,
701 .gem_vm_ops = &drm_gem_cma_vm_ops,
702 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
703 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
704 .gem_prime_import = drm_gem_prime_import,
705 .gem_prime_export = drm_gem_prime_export,
706 .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
707 .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
708 .gem_prime_vmap = drm_gem_cma_prime_vmap,
709 .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
710 .gem_prime_mmap = drm_gem_cma_prime_mmap,
711 .dumb_create = drm_gem_cma_dumb_create,
712 .dumb_map_offset = drm_gem_cma_dumb_map_offset,
713 .dumb_destroy = drm_gem_dumb_destroy,
714 .fops = &fops,
715 .name = "atmel-hlcdc",
716 .desc = "Atmel HLCD Controller DRM",
717 .date = "20141504",
718 .major = 1,
719 .minor = 0,
720};
721
722static int atmel_hlcdc_dc_drm_probe(struct platform_device *pdev)
723{
724 struct drm_device *ddev;
725 int ret;
726
727 ddev = drm_dev_alloc(&atmel_hlcdc_dc_driver, &pdev->dev);
728 if (!ddev)
729 return -ENOMEM;
730
731 ret = atmel_hlcdc_dc_load(ddev);
732 if (ret)
733 goto err_unref;
734
735 ret = drm_dev_register(ddev, 0);
736 if (ret)
737 goto err_unload;
738
739 ret = atmel_hlcdc_dc_connector_plug_all(ddev);
740 if (ret)
741 goto err_unregister;
742
743 return 0;
744
745err_unregister:
746 drm_dev_unregister(ddev);
747
748err_unload:
749 atmel_hlcdc_dc_unload(ddev);
750
751err_unref:
752 drm_dev_unref(ddev);
753
754 return ret;
755}
756
757static int atmel_hlcdc_dc_drm_remove(struct platform_device *pdev)
758{
759 struct drm_device *ddev = platform_get_drvdata(pdev);
760
761 atmel_hlcdc_dc_connector_unplug_all(ddev);
762 drm_dev_unregister(ddev);
763 atmel_hlcdc_dc_unload(ddev);
764 drm_dev_unref(ddev);
765
766 return 0;
767}
768
769#ifdef CONFIG_PM_SLEEP
770static int atmel_hlcdc_dc_drm_suspend(struct device *dev)
771{
772 struct drm_device *drm_dev = dev_get_drvdata(dev);
773 struct drm_crtc *crtc;
774
775 if (pm_runtime_suspended(dev))
776 return 0;
777
778 drm_modeset_lock_all(drm_dev);
779 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head)
780 atmel_hlcdc_crtc_suspend(crtc);
781 drm_modeset_unlock_all(drm_dev);
782 return 0;
783}
784
785static int atmel_hlcdc_dc_drm_resume(struct device *dev)
786{
787 struct drm_device *drm_dev = dev_get_drvdata(dev);
788 struct drm_crtc *crtc;
789
790 if (pm_runtime_suspended(dev))
791 return 0;
792
793 drm_modeset_lock_all(drm_dev);
794 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head)
795 atmel_hlcdc_crtc_resume(crtc);
796 drm_modeset_unlock_all(drm_dev);
797 return 0;
798}
799#endif
800
801static SIMPLE_DEV_PM_OPS(atmel_hlcdc_dc_drm_pm_ops,
802 atmel_hlcdc_dc_drm_suspend, atmel_hlcdc_dc_drm_resume);
803
804static const struct of_device_id atmel_hlcdc_dc_of_match[] = {
805 { .compatible = "atmel,hlcdc-display-controller" },
806 { },
807};
808
809static struct platform_driver atmel_hlcdc_dc_platform_driver = {
810 .probe = atmel_hlcdc_dc_drm_probe,
811 .remove = atmel_hlcdc_dc_drm_remove,
812 .driver = {
813 .name = "atmel-hlcdc-display-controller",
814 .pm = &atmel_hlcdc_dc_drm_pm_ops,
815 .of_match_table = atmel_hlcdc_dc_of_match,
816 },
817};
818module_platform_driver(atmel_hlcdc_dc_platform_driver);
819
820MODULE_AUTHOR("Jean-Jacques Hiblot <jjhiblot@traphandler.com>");
821MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>");
822MODULE_DESCRIPTION("Atmel HLCDC Display Controller DRM Driver");
823MODULE_LICENSE("GPL");
824MODULE_ALIAS("platform:atmel-hlcdc-dc");
1/*
2 * Copyright (C) 2014 Traphandler
3 * Copyright (C) 2014 Free Electrons
4 * Copyright (C) 2014 Atmel
5 *
6 * Author: Jean-Jacques Hiblot <jjhiblot@traphandler.com>
7 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#include <linux/clk.h>
23#include <linux/irq.h>
24#include <linux/irqchip.h>
25#include <linux/module.h>
26#include <linux/pm_runtime.h>
27
28#include "atmel_hlcdc_dc.h"
29
30#define ATMEL_HLCDC_LAYER_IRQS_OFFSET 8
31
32static const struct atmel_hlcdc_layer_desc atmel_hlcdc_at91sam9n12_layers[] = {
33 {
34 .name = "base",
35 .formats = &atmel_hlcdc_plane_rgb_formats,
36 .regs_offset = 0x40,
37 .id = 0,
38 .type = ATMEL_HLCDC_BASE_LAYER,
39 .cfgs_offset = 0x2c,
40 .layout = {
41 .xstride = { 2 },
42 .default_color = 3,
43 .general_config = 4,
44 },
45 .clut_offset = 0x400,
46 },
47};
48
49static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_at91sam9n12 = {
50 .min_width = 0,
51 .min_height = 0,
52 .max_width = 1280,
53 .max_height = 860,
54 .max_spw = 0x3f,
55 .max_vpw = 0x3f,
56 .max_hpw = 0xff,
57 .conflicting_output_formats = true,
58 .nlayers = ARRAY_SIZE(atmel_hlcdc_at91sam9n12_layers),
59 .layers = atmel_hlcdc_at91sam9n12_layers,
60};
61
62static const struct atmel_hlcdc_layer_desc atmel_hlcdc_at91sam9x5_layers[] = {
63 {
64 .name = "base",
65 .formats = &atmel_hlcdc_plane_rgb_formats,
66 .regs_offset = 0x40,
67 .id = 0,
68 .type = ATMEL_HLCDC_BASE_LAYER,
69 .cfgs_offset = 0x2c,
70 .layout = {
71 .xstride = { 2 },
72 .default_color = 3,
73 .general_config = 4,
74 .disc_pos = 5,
75 .disc_size = 6,
76 },
77 .clut_offset = 0x400,
78 },
79 {
80 .name = "overlay1",
81 .formats = &atmel_hlcdc_plane_rgb_formats,
82 .regs_offset = 0x100,
83 .id = 1,
84 .type = ATMEL_HLCDC_OVERLAY_LAYER,
85 .cfgs_offset = 0x2c,
86 .layout = {
87 .pos = 2,
88 .size = 3,
89 .xstride = { 4 },
90 .pstride = { 5 },
91 .default_color = 6,
92 .chroma_key = 7,
93 .chroma_key_mask = 8,
94 .general_config = 9,
95 },
96 .clut_offset = 0x800,
97 },
98 {
99 .name = "high-end-overlay",
100 .formats = &atmel_hlcdc_plane_rgb_and_yuv_formats,
101 .regs_offset = 0x280,
102 .id = 2,
103 .type = ATMEL_HLCDC_OVERLAY_LAYER,
104 .cfgs_offset = 0x4c,
105 .layout = {
106 .pos = 2,
107 .size = 3,
108 .memsize = 4,
109 .xstride = { 5, 7 },
110 .pstride = { 6, 8 },
111 .default_color = 9,
112 .chroma_key = 10,
113 .chroma_key_mask = 11,
114 .general_config = 12,
115 .scaler_config = 13,
116 .csc = 14,
117 },
118 .clut_offset = 0x1000,
119 },
120 {
121 .name = "cursor",
122 .formats = &atmel_hlcdc_plane_rgb_formats,
123 .regs_offset = 0x340,
124 .id = 3,
125 .type = ATMEL_HLCDC_CURSOR_LAYER,
126 .max_width = 128,
127 .max_height = 128,
128 .cfgs_offset = 0x2c,
129 .layout = {
130 .pos = 2,
131 .size = 3,
132 .xstride = { 4 },
133 .default_color = 6,
134 .chroma_key = 7,
135 .chroma_key_mask = 8,
136 .general_config = 9,
137 },
138 .clut_offset = 0x1400,
139 },
140};
141
142static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_at91sam9x5 = {
143 .min_width = 0,
144 .min_height = 0,
145 .max_width = 800,
146 .max_height = 600,
147 .max_spw = 0x3f,
148 .max_vpw = 0x3f,
149 .max_hpw = 0xff,
150 .conflicting_output_formats = true,
151 .nlayers = ARRAY_SIZE(atmel_hlcdc_at91sam9x5_layers),
152 .layers = atmel_hlcdc_at91sam9x5_layers,
153};
154
155static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sama5d3_layers[] = {
156 {
157 .name = "base",
158 .formats = &atmel_hlcdc_plane_rgb_formats,
159 .regs_offset = 0x40,
160 .id = 0,
161 .type = ATMEL_HLCDC_BASE_LAYER,
162 .cfgs_offset = 0x2c,
163 .layout = {
164 .xstride = { 2 },
165 .default_color = 3,
166 .general_config = 4,
167 .disc_pos = 5,
168 .disc_size = 6,
169 },
170 .clut_offset = 0x600,
171 },
172 {
173 .name = "overlay1",
174 .formats = &atmel_hlcdc_plane_rgb_formats,
175 .regs_offset = 0x140,
176 .id = 1,
177 .type = ATMEL_HLCDC_OVERLAY_LAYER,
178 .cfgs_offset = 0x2c,
179 .layout = {
180 .pos = 2,
181 .size = 3,
182 .xstride = { 4 },
183 .pstride = { 5 },
184 .default_color = 6,
185 .chroma_key = 7,
186 .chroma_key_mask = 8,
187 .general_config = 9,
188 },
189 .clut_offset = 0xa00,
190 },
191 {
192 .name = "overlay2",
193 .formats = &atmel_hlcdc_plane_rgb_formats,
194 .regs_offset = 0x240,
195 .id = 2,
196 .type = ATMEL_HLCDC_OVERLAY_LAYER,
197 .cfgs_offset = 0x2c,
198 .layout = {
199 .pos = 2,
200 .size = 3,
201 .xstride = { 4 },
202 .pstride = { 5 },
203 .default_color = 6,
204 .chroma_key = 7,
205 .chroma_key_mask = 8,
206 .general_config = 9,
207 },
208 .clut_offset = 0xe00,
209 },
210 {
211 .name = "high-end-overlay",
212 .formats = &atmel_hlcdc_plane_rgb_and_yuv_formats,
213 .regs_offset = 0x340,
214 .id = 3,
215 .type = ATMEL_HLCDC_OVERLAY_LAYER,
216 .cfgs_offset = 0x4c,
217 .layout = {
218 .pos = 2,
219 .size = 3,
220 .memsize = 4,
221 .xstride = { 5, 7 },
222 .pstride = { 6, 8 },
223 .default_color = 9,
224 .chroma_key = 10,
225 .chroma_key_mask = 11,
226 .general_config = 12,
227 .scaler_config = 13,
228 .phicoeffs = {
229 .x = 17,
230 .y = 33,
231 },
232 .csc = 14,
233 },
234 .clut_offset = 0x1200,
235 },
236 {
237 .name = "cursor",
238 .formats = &atmel_hlcdc_plane_rgb_formats,
239 .regs_offset = 0x440,
240 .id = 4,
241 .type = ATMEL_HLCDC_CURSOR_LAYER,
242 .max_width = 128,
243 .max_height = 128,
244 .cfgs_offset = 0x2c,
245 .layout = {
246 .pos = 2,
247 .size = 3,
248 .xstride = { 4 },
249 .pstride = { 5 },
250 .default_color = 6,
251 .chroma_key = 7,
252 .chroma_key_mask = 8,
253 .general_config = 9,
254 .scaler_config = 13,
255 },
256 .clut_offset = 0x1600,
257 },
258};
259
260static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_sama5d3 = {
261 .min_width = 0,
262 .min_height = 0,
263 .max_width = 2048,
264 .max_height = 2048,
265 .max_spw = 0x3f,
266 .max_vpw = 0x3f,
267 .max_hpw = 0x1ff,
268 .conflicting_output_formats = true,
269 .nlayers = ARRAY_SIZE(atmel_hlcdc_sama5d3_layers),
270 .layers = atmel_hlcdc_sama5d3_layers,
271};
272
273static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sama5d4_layers[] = {
274 {
275 .name = "base",
276 .formats = &atmel_hlcdc_plane_rgb_formats,
277 .regs_offset = 0x40,
278 .id = 0,
279 .type = ATMEL_HLCDC_BASE_LAYER,
280 .cfgs_offset = 0x2c,
281 .layout = {
282 .xstride = { 2 },
283 .default_color = 3,
284 .general_config = 4,
285 .disc_pos = 5,
286 .disc_size = 6,
287 },
288 .clut_offset = 0x600,
289 },
290 {
291 .name = "overlay1",
292 .formats = &atmel_hlcdc_plane_rgb_formats,
293 .regs_offset = 0x140,
294 .id = 1,
295 .type = ATMEL_HLCDC_OVERLAY_LAYER,
296 .cfgs_offset = 0x2c,
297 .layout = {
298 .pos = 2,
299 .size = 3,
300 .xstride = { 4 },
301 .pstride = { 5 },
302 .default_color = 6,
303 .chroma_key = 7,
304 .chroma_key_mask = 8,
305 .general_config = 9,
306 },
307 .clut_offset = 0xa00,
308 },
309 {
310 .name = "overlay2",
311 .formats = &atmel_hlcdc_plane_rgb_formats,
312 .regs_offset = 0x240,
313 .id = 2,
314 .type = ATMEL_HLCDC_OVERLAY_LAYER,
315 .cfgs_offset = 0x2c,
316 .layout = {
317 .pos = 2,
318 .size = 3,
319 .xstride = { 4 },
320 .pstride = { 5 },
321 .default_color = 6,
322 .chroma_key = 7,
323 .chroma_key_mask = 8,
324 .general_config = 9,
325 },
326 .clut_offset = 0xe00,
327 },
328 {
329 .name = "high-end-overlay",
330 .formats = &atmel_hlcdc_plane_rgb_and_yuv_formats,
331 .regs_offset = 0x340,
332 .id = 3,
333 .type = ATMEL_HLCDC_OVERLAY_LAYER,
334 .cfgs_offset = 0x4c,
335 .layout = {
336 .pos = 2,
337 .size = 3,
338 .memsize = 4,
339 .xstride = { 5, 7 },
340 .pstride = { 6, 8 },
341 .default_color = 9,
342 .chroma_key = 10,
343 .chroma_key_mask = 11,
344 .general_config = 12,
345 .scaler_config = 13,
346 .phicoeffs = {
347 .x = 17,
348 .y = 33,
349 },
350 .csc = 14,
351 },
352 .clut_offset = 0x1200,
353 },
354};
355
356static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_sama5d4 = {
357 .min_width = 0,
358 .min_height = 0,
359 .max_width = 2048,
360 .max_height = 2048,
361 .max_spw = 0xff,
362 .max_vpw = 0xff,
363 .max_hpw = 0x3ff,
364 .nlayers = ARRAY_SIZE(atmel_hlcdc_sama5d4_layers),
365 .layers = atmel_hlcdc_sama5d4_layers,
366};
367static const struct of_device_id atmel_hlcdc_of_match[] = {
368 {
369 .compatible = "atmel,at91sam9n12-hlcdc",
370 .data = &atmel_hlcdc_dc_at91sam9n12,
371 },
372 {
373 .compatible = "atmel,at91sam9x5-hlcdc",
374 .data = &atmel_hlcdc_dc_at91sam9x5,
375 },
376 {
377 .compatible = "atmel,sama5d2-hlcdc",
378 .data = &atmel_hlcdc_dc_sama5d4,
379 },
380 {
381 .compatible = "atmel,sama5d3-hlcdc",
382 .data = &atmel_hlcdc_dc_sama5d3,
383 },
384 {
385 .compatible = "atmel,sama5d4-hlcdc",
386 .data = &atmel_hlcdc_dc_sama5d4,
387 },
388 { /* sentinel */ },
389};
390MODULE_DEVICE_TABLE(of, atmel_hlcdc_of_match);
391
392enum drm_mode_status
393atmel_hlcdc_dc_mode_valid(struct atmel_hlcdc_dc *dc,
394 const struct drm_display_mode *mode)
395{
396 int vfront_porch = mode->vsync_start - mode->vdisplay;
397 int vback_porch = mode->vtotal - mode->vsync_end;
398 int vsync_len = mode->vsync_end - mode->vsync_start;
399 int hfront_porch = mode->hsync_start - mode->hdisplay;
400 int hback_porch = mode->htotal - mode->hsync_end;
401 int hsync_len = mode->hsync_end - mode->hsync_start;
402
403 if (hsync_len > dc->desc->max_spw + 1 || hsync_len < 1)
404 return MODE_HSYNC;
405
406 if (vsync_len > dc->desc->max_spw + 1 || vsync_len < 1)
407 return MODE_VSYNC;
408
409 if (hfront_porch > dc->desc->max_hpw + 1 || hfront_porch < 1 ||
410 hback_porch > dc->desc->max_hpw + 1 || hback_porch < 1 ||
411 mode->hdisplay < 1)
412 return MODE_H_ILLEGAL;
413
414 if (vfront_porch > dc->desc->max_vpw + 1 || vfront_porch < 1 ||
415 vback_porch > dc->desc->max_vpw || vback_porch < 0 ||
416 mode->vdisplay < 1)
417 return MODE_V_ILLEGAL;
418
419 return MODE_OK;
420}
421
422static void atmel_hlcdc_layer_irq(struct atmel_hlcdc_layer *layer)
423{
424 if (!layer)
425 return;
426
427 if (layer->desc->type == ATMEL_HLCDC_BASE_LAYER ||
428 layer->desc->type == ATMEL_HLCDC_OVERLAY_LAYER ||
429 layer->desc->type == ATMEL_HLCDC_CURSOR_LAYER)
430 atmel_hlcdc_plane_irq(atmel_hlcdc_layer_to_plane(layer));
431}
432
433static irqreturn_t atmel_hlcdc_dc_irq_handler(int irq, void *data)
434{
435 struct drm_device *dev = data;
436 struct atmel_hlcdc_dc *dc = dev->dev_private;
437 unsigned long status;
438 unsigned int imr, isr;
439 int i;
440
441 regmap_read(dc->hlcdc->regmap, ATMEL_HLCDC_IMR, &imr);
442 regmap_read(dc->hlcdc->regmap, ATMEL_HLCDC_ISR, &isr);
443 status = imr & isr;
444 if (!status)
445 return IRQ_NONE;
446
447 if (status & ATMEL_HLCDC_SOF)
448 atmel_hlcdc_crtc_irq(dc->crtc);
449
450 for (i = 0; i < ATMEL_HLCDC_MAX_LAYERS; i++) {
451 if (ATMEL_HLCDC_LAYER_STATUS(i) & status)
452 atmel_hlcdc_layer_irq(dc->layers[i]);
453 }
454
455 return IRQ_HANDLED;
456}
457
458static struct drm_framebuffer *atmel_hlcdc_fb_create(struct drm_device *dev,
459 struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd)
460{
461 return drm_gem_fb_create(dev, file_priv, mode_cmd);
462}
463
464struct atmel_hlcdc_dc_commit {
465 struct work_struct work;
466 struct drm_device *dev;
467 struct drm_atomic_state *state;
468};
469
470static void
471atmel_hlcdc_dc_atomic_complete(struct atmel_hlcdc_dc_commit *commit)
472{
473 struct drm_device *dev = commit->dev;
474 struct atmel_hlcdc_dc *dc = dev->dev_private;
475 struct drm_atomic_state *old_state = commit->state;
476
477 /* Apply the atomic update. */
478 drm_atomic_helper_commit_modeset_disables(dev, old_state);
479 drm_atomic_helper_commit_planes(dev, old_state, 0);
480 drm_atomic_helper_commit_modeset_enables(dev, old_state);
481
482 drm_atomic_helper_wait_for_vblanks(dev, old_state);
483
484 drm_atomic_helper_cleanup_planes(dev, old_state);
485
486 drm_atomic_state_put(old_state);
487
488 /* Complete the commit, wake up any waiter. */
489 spin_lock(&dc->commit.wait.lock);
490 dc->commit.pending = false;
491 wake_up_all_locked(&dc->commit.wait);
492 spin_unlock(&dc->commit.wait.lock);
493
494 kfree(commit);
495}
496
497static void atmel_hlcdc_dc_atomic_work(struct work_struct *work)
498{
499 struct atmel_hlcdc_dc_commit *commit =
500 container_of(work, struct atmel_hlcdc_dc_commit, work);
501
502 atmel_hlcdc_dc_atomic_complete(commit);
503}
504
505static int atmel_hlcdc_dc_atomic_commit(struct drm_device *dev,
506 struct drm_atomic_state *state,
507 bool async)
508{
509 struct atmel_hlcdc_dc *dc = dev->dev_private;
510 struct atmel_hlcdc_dc_commit *commit;
511 int ret;
512
513 ret = drm_atomic_helper_prepare_planes(dev, state);
514 if (ret)
515 return ret;
516
517 /* Allocate the commit object. */
518 commit = kzalloc(sizeof(*commit), GFP_KERNEL);
519 if (!commit) {
520 ret = -ENOMEM;
521 goto error;
522 }
523
524 INIT_WORK(&commit->work, atmel_hlcdc_dc_atomic_work);
525 commit->dev = dev;
526 commit->state = state;
527
528 spin_lock(&dc->commit.wait.lock);
529 ret = wait_event_interruptible_locked(dc->commit.wait,
530 !dc->commit.pending);
531 if (ret == 0)
532 dc->commit.pending = true;
533 spin_unlock(&dc->commit.wait.lock);
534
535 if (ret)
536 goto err_free;
537
538 /* We have our own synchronization through the commit lock. */
539 BUG_ON(drm_atomic_helper_swap_state(state, false) < 0);
540
541 /* Swap state succeeded, this is the point of no return. */
542 drm_atomic_state_get(state);
543 if (async)
544 queue_work(dc->wq, &commit->work);
545 else
546 atmel_hlcdc_dc_atomic_complete(commit);
547
548 return 0;
549
550err_free:
551 kfree(commit);
552error:
553 drm_atomic_helper_cleanup_planes(dev, state);
554 return ret;
555}
556
557static const struct drm_mode_config_funcs mode_config_funcs = {
558 .fb_create = atmel_hlcdc_fb_create,
559 .output_poll_changed = drm_fb_helper_output_poll_changed,
560 .atomic_check = drm_atomic_helper_check,
561 .atomic_commit = atmel_hlcdc_dc_atomic_commit,
562};
563
564static int atmel_hlcdc_dc_modeset_init(struct drm_device *dev)
565{
566 struct atmel_hlcdc_dc *dc = dev->dev_private;
567 int ret;
568
569 drm_mode_config_init(dev);
570
571 ret = atmel_hlcdc_create_outputs(dev);
572 if (ret) {
573 dev_err(dev->dev, "failed to create HLCDC outputs: %d\n", ret);
574 return ret;
575 }
576
577 ret = atmel_hlcdc_create_planes(dev);
578 if (ret) {
579 dev_err(dev->dev, "failed to create planes: %d\n", ret);
580 return ret;
581 }
582
583 ret = atmel_hlcdc_crtc_create(dev);
584 if (ret) {
585 dev_err(dev->dev, "failed to create crtc\n");
586 return ret;
587 }
588
589 dev->mode_config.min_width = dc->desc->min_width;
590 dev->mode_config.min_height = dc->desc->min_height;
591 dev->mode_config.max_width = dc->desc->max_width;
592 dev->mode_config.max_height = dc->desc->max_height;
593 dev->mode_config.funcs = &mode_config_funcs;
594
595 return 0;
596}
597
598static int atmel_hlcdc_dc_load(struct drm_device *dev)
599{
600 struct platform_device *pdev = to_platform_device(dev->dev);
601 const struct of_device_id *match;
602 struct atmel_hlcdc_dc *dc;
603 int ret;
604
605 match = of_match_node(atmel_hlcdc_of_match, dev->dev->parent->of_node);
606 if (!match) {
607 dev_err(&pdev->dev, "invalid compatible string\n");
608 return -ENODEV;
609 }
610
611 if (!match->data) {
612 dev_err(&pdev->dev, "invalid hlcdc description\n");
613 return -EINVAL;
614 }
615
616 dc = devm_kzalloc(dev->dev, sizeof(*dc), GFP_KERNEL);
617 if (!dc)
618 return -ENOMEM;
619
620 dc->wq = alloc_ordered_workqueue("atmel-hlcdc-dc", 0);
621 if (!dc->wq)
622 return -ENOMEM;
623
624 init_waitqueue_head(&dc->commit.wait);
625 dc->desc = match->data;
626 dc->hlcdc = dev_get_drvdata(dev->dev->parent);
627 dev->dev_private = dc;
628
629 ret = clk_prepare_enable(dc->hlcdc->periph_clk);
630 if (ret) {
631 dev_err(dev->dev, "failed to enable periph_clk\n");
632 goto err_destroy_wq;
633 }
634
635 pm_runtime_enable(dev->dev);
636
637 ret = drm_vblank_init(dev, 1);
638 if (ret < 0) {
639 dev_err(dev->dev, "failed to initialize vblank\n");
640 goto err_periph_clk_disable;
641 }
642
643 ret = atmel_hlcdc_dc_modeset_init(dev);
644 if (ret < 0) {
645 dev_err(dev->dev, "failed to initialize mode setting\n");
646 goto err_periph_clk_disable;
647 }
648
649 drm_mode_config_reset(dev);
650
651 pm_runtime_get_sync(dev->dev);
652 ret = drm_irq_install(dev, dc->hlcdc->irq);
653 pm_runtime_put_sync(dev->dev);
654 if (ret < 0) {
655 dev_err(dev->dev, "failed to install IRQ handler\n");
656 goto err_periph_clk_disable;
657 }
658
659 platform_set_drvdata(pdev, dev);
660
661 drm_fb_cma_fbdev_init(dev, 24, 0);
662
663 drm_kms_helper_poll_init(dev);
664
665 return 0;
666
667err_periph_clk_disable:
668 pm_runtime_disable(dev->dev);
669 clk_disable_unprepare(dc->hlcdc->periph_clk);
670
671err_destroy_wq:
672 destroy_workqueue(dc->wq);
673
674 return ret;
675}
676
677static void atmel_hlcdc_dc_unload(struct drm_device *dev)
678{
679 struct atmel_hlcdc_dc *dc = dev->dev_private;
680
681 drm_fb_cma_fbdev_fini(dev);
682 flush_workqueue(dc->wq);
683 drm_kms_helper_poll_fini(dev);
684 drm_mode_config_cleanup(dev);
685
686 pm_runtime_get_sync(dev->dev);
687 drm_irq_uninstall(dev);
688 pm_runtime_put_sync(dev->dev);
689
690 dev->dev_private = NULL;
691
692 pm_runtime_disable(dev->dev);
693 clk_disable_unprepare(dc->hlcdc->periph_clk);
694 destroy_workqueue(dc->wq);
695}
696
697static int atmel_hlcdc_dc_irq_postinstall(struct drm_device *dev)
698{
699 struct atmel_hlcdc_dc *dc = dev->dev_private;
700 unsigned int cfg = 0;
701 int i;
702
703 /* Enable interrupts on activated layers */
704 for (i = 0; i < ATMEL_HLCDC_MAX_LAYERS; i++) {
705 if (dc->layers[i])
706 cfg |= ATMEL_HLCDC_LAYER_STATUS(i);
707 }
708
709 regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IER, cfg);
710
711 return 0;
712}
713
714static void atmel_hlcdc_dc_irq_uninstall(struct drm_device *dev)
715{
716 struct atmel_hlcdc_dc *dc = dev->dev_private;
717 unsigned int isr;
718
719 regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IDR, 0xffffffff);
720 regmap_read(dc->hlcdc->regmap, ATMEL_HLCDC_ISR, &isr);
721}
722
723DEFINE_DRM_GEM_CMA_FOPS(fops);
724
725static struct drm_driver atmel_hlcdc_dc_driver = {
726 .driver_features = DRIVER_HAVE_IRQ | DRIVER_GEM |
727 DRIVER_MODESET | DRIVER_PRIME |
728 DRIVER_ATOMIC,
729 .lastclose = drm_fb_helper_lastclose,
730 .irq_handler = atmel_hlcdc_dc_irq_handler,
731 .irq_preinstall = atmel_hlcdc_dc_irq_uninstall,
732 .irq_postinstall = atmel_hlcdc_dc_irq_postinstall,
733 .irq_uninstall = atmel_hlcdc_dc_irq_uninstall,
734 .gem_free_object_unlocked = drm_gem_cma_free_object,
735 .gem_vm_ops = &drm_gem_cma_vm_ops,
736 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
737 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
738 .gem_prime_import = drm_gem_prime_import,
739 .gem_prime_export = drm_gem_prime_export,
740 .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
741 .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
742 .gem_prime_vmap = drm_gem_cma_prime_vmap,
743 .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
744 .gem_prime_mmap = drm_gem_cma_prime_mmap,
745 .dumb_create = drm_gem_cma_dumb_create,
746 .fops = &fops,
747 .name = "atmel-hlcdc",
748 .desc = "Atmel HLCD Controller DRM",
749 .date = "20141504",
750 .major = 1,
751 .minor = 0,
752};
753
754static int atmel_hlcdc_dc_drm_probe(struct platform_device *pdev)
755{
756 struct drm_device *ddev;
757 int ret;
758
759 ddev = drm_dev_alloc(&atmel_hlcdc_dc_driver, &pdev->dev);
760 if (IS_ERR(ddev))
761 return PTR_ERR(ddev);
762
763 ret = atmel_hlcdc_dc_load(ddev);
764 if (ret)
765 goto err_unref;
766
767 ret = drm_dev_register(ddev, 0);
768 if (ret)
769 goto err_unload;
770
771 return 0;
772
773err_unload:
774 atmel_hlcdc_dc_unload(ddev);
775
776err_unref:
777 drm_dev_unref(ddev);
778
779 return ret;
780}
781
782static int atmel_hlcdc_dc_drm_remove(struct platform_device *pdev)
783{
784 struct drm_device *ddev = platform_get_drvdata(pdev);
785
786 drm_dev_unregister(ddev);
787 atmel_hlcdc_dc_unload(ddev);
788 drm_dev_unref(ddev);
789
790 return 0;
791}
792
793#ifdef CONFIG_PM_SLEEP
794static int atmel_hlcdc_dc_drm_suspend(struct device *dev)
795{
796 struct drm_device *drm_dev = dev_get_drvdata(dev);
797 struct atmel_hlcdc_dc *dc = drm_dev->dev_private;
798 struct regmap *regmap = dc->hlcdc->regmap;
799 struct drm_atomic_state *state;
800
801 state = drm_atomic_helper_suspend(drm_dev);
802 if (IS_ERR(state))
803 return PTR_ERR(state);
804
805 dc->suspend.state = state;
806
807 regmap_read(regmap, ATMEL_HLCDC_IMR, &dc->suspend.imr);
808 regmap_write(regmap, ATMEL_HLCDC_IDR, dc->suspend.imr);
809 clk_disable_unprepare(dc->hlcdc->periph_clk);
810
811 return 0;
812}
813
814static int atmel_hlcdc_dc_drm_resume(struct device *dev)
815{
816 struct drm_device *drm_dev = dev_get_drvdata(dev);
817 struct atmel_hlcdc_dc *dc = drm_dev->dev_private;
818
819 clk_prepare_enable(dc->hlcdc->periph_clk);
820 regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IER, dc->suspend.imr);
821
822 return drm_atomic_helper_resume(drm_dev, dc->suspend.state);
823}
824#endif
825
826static SIMPLE_DEV_PM_OPS(atmel_hlcdc_dc_drm_pm_ops,
827 atmel_hlcdc_dc_drm_suspend, atmel_hlcdc_dc_drm_resume);
828
829static const struct of_device_id atmel_hlcdc_dc_of_match[] = {
830 { .compatible = "atmel,hlcdc-display-controller" },
831 { },
832};
833
834static struct platform_driver atmel_hlcdc_dc_platform_driver = {
835 .probe = atmel_hlcdc_dc_drm_probe,
836 .remove = atmel_hlcdc_dc_drm_remove,
837 .driver = {
838 .name = "atmel-hlcdc-display-controller",
839 .pm = &atmel_hlcdc_dc_drm_pm_ops,
840 .of_match_table = atmel_hlcdc_dc_of_match,
841 },
842};
843module_platform_driver(atmel_hlcdc_dc_platform_driver);
844
845MODULE_AUTHOR("Jean-Jacques Hiblot <jjhiblot@traphandler.com>");
846MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>");
847MODULE_DESCRIPTION("Atmel HLCDC Display Controller DRM Driver");
848MODULE_LICENSE("GPL");
849MODULE_ALIAS("platform:atmel-hlcdc-dc");