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1/*
2 * Copyright (C) 2014 Traphandler
3 * Copyright (C) 2014 Free Electrons
4 * Copyright (C) 2014 Atmel
5 *
6 * Author: Jean-Jacques Hiblot <jjhiblot@traphandler.com>
7 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#include <linux/clk.h>
23#include <linux/irq.h>
24#include <linux/irqchip.h>
25#include <linux/module.h>
26#include <linux/pm_runtime.h>
27
28#include "atmel_hlcdc_dc.h"
29
30#define ATMEL_HLCDC_LAYER_IRQS_OFFSET 8
31
32static const struct atmel_hlcdc_layer_desc atmel_hlcdc_at91sam9n12_layers[] = {
33 {
34 .name = "base",
35 .formats = &atmel_hlcdc_plane_rgb_formats,
36 .regs_offset = 0x40,
37 .id = 0,
38 .type = ATMEL_HLCDC_BASE_LAYER,
39 .nconfigs = 5,
40 .layout = {
41 .xstride = { 2 },
42 .default_color = 3,
43 .general_config = 4,
44 },
45 },
46};
47
48static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_at91sam9n12 = {
49 .min_width = 0,
50 .min_height = 0,
51 .max_width = 1280,
52 .max_height = 860,
53 .nlayers = ARRAY_SIZE(atmel_hlcdc_at91sam9n12_layers),
54 .layers = atmel_hlcdc_at91sam9n12_layers,
55};
56
57static const struct atmel_hlcdc_layer_desc atmel_hlcdc_at91sam9x5_layers[] = {
58 {
59 .name = "base",
60 .formats = &atmel_hlcdc_plane_rgb_formats,
61 .regs_offset = 0x40,
62 .id = 0,
63 .type = ATMEL_HLCDC_BASE_LAYER,
64 .nconfigs = 5,
65 .layout = {
66 .xstride = { 2 },
67 .default_color = 3,
68 .general_config = 4,
69 .disc_pos = 5,
70 .disc_size = 6,
71 },
72 },
73 {
74 .name = "overlay1",
75 .formats = &atmel_hlcdc_plane_rgb_formats,
76 .regs_offset = 0x100,
77 .id = 1,
78 .type = ATMEL_HLCDC_OVERLAY_LAYER,
79 .nconfigs = 10,
80 .layout = {
81 .pos = 2,
82 .size = 3,
83 .xstride = { 4 },
84 .pstride = { 5 },
85 .default_color = 6,
86 .chroma_key = 7,
87 .chroma_key_mask = 8,
88 .general_config = 9,
89 },
90 },
91 {
92 .name = "high-end-overlay",
93 .formats = &atmel_hlcdc_plane_rgb_and_yuv_formats,
94 .regs_offset = 0x280,
95 .id = 2,
96 .type = ATMEL_HLCDC_OVERLAY_LAYER,
97 .nconfigs = 17,
98 .layout = {
99 .pos = 2,
100 .size = 3,
101 .memsize = 4,
102 .xstride = { 5, 7 },
103 .pstride = { 6, 8 },
104 .default_color = 9,
105 .chroma_key = 10,
106 .chroma_key_mask = 11,
107 .general_config = 12,
108 .csc = 14,
109 },
110 },
111 {
112 .name = "cursor",
113 .formats = &atmel_hlcdc_plane_rgb_formats,
114 .regs_offset = 0x340,
115 .id = 3,
116 .type = ATMEL_HLCDC_CURSOR_LAYER,
117 .nconfigs = 10,
118 .max_width = 128,
119 .max_height = 128,
120 .layout = {
121 .pos = 2,
122 .size = 3,
123 .xstride = { 4 },
124 .default_color = 6,
125 .chroma_key = 7,
126 .chroma_key_mask = 8,
127 .general_config = 9,
128 },
129 },
130};
131
132static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_at91sam9x5 = {
133 .min_width = 0,
134 .min_height = 0,
135 .max_width = 800,
136 .max_height = 600,
137 .nlayers = ARRAY_SIZE(atmel_hlcdc_at91sam9x5_layers),
138 .layers = atmel_hlcdc_at91sam9x5_layers,
139};
140
141static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sama5d3_layers[] = {
142 {
143 .name = "base",
144 .formats = &atmel_hlcdc_plane_rgb_formats,
145 .regs_offset = 0x40,
146 .id = 0,
147 .type = ATMEL_HLCDC_BASE_LAYER,
148 .nconfigs = 7,
149 .layout = {
150 .xstride = { 2 },
151 .default_color = 3,
152 .general_config = 4,
153 .disc_pos = 5,
154 .disc_size = 6,
155 },
156 },
157 {
158 .name = "overlay1",
159 .formats = &atmel_hlcdc_plane_rgb_formats,
160 .regs_offset = 0x140,
161 .id = 1,
162 .type = ATMEL_HLCDC_OVERLAY_LAYER,
163 .nconfigs = 10,
164 .layout = {
165 .pos = 2,
166 .size = 3,
167 .xstride = { 4 },
168 .pstride = { 5 },
169 .default_color = 6,
170 .chroma_key = 7,
171 .chroma_key_mask = 8,
172 .general_config = 9,
173 },
174 },
175 {
176 .name = "overlay2",
177 .formats = &atmel_hlcdc_plane_rgb_formats,
178 .regs_offset = 0x240,
179 .id = 2,
180 .type = ATMEL_HLCDC_OVERLAY_LAYER,
181 .nconfigs = 10,
182 .layout = {
183 .pos = 2,
184 .size = 3,
185 .xstride = { 4 },
186 .pstride = { 5 },
187 .default_color = 6,
188 .chroma_key = 7,
189 .chroma_key_mask = 8,
190 .general_config = 9,
191 },
192 },
193 {
194 .name = "high-end-overlay",
195 .formats = &atmel_hlcdc_plane_rgb_and_yuv_formats,
196 .regs_offset = 0x340,
197 .id = 3,
198 .type = ATMEL_HLCDC_OVERLAY_LAYER,
199 .nconfigs = 42,
200 .layout = {
201 .pos = 2,
202 .size = 3,
203 .memsize = 4,
204 .xstride = { 5, 7 },
205 .pstride = { 6, 8 },
206 .default_color = 9,
207 .chroma_key = 10,
208 .chroma_key_mask = 11,
209 .general_config = 12,
210 .csc = 14,
211 },
212 },
213 {
214 .name = "cursor",
215 .formats = &atmel_hlcdc_plane_rgb_formats,
216 .regs_offset = 0x440,
217 .id = 4,
218 .type = ATMEL_HLCDC_CURSOR_LAYER,
219 .nconfigs = 10,
220 .max_width = 128,
221 .max_height = 128,
222 .layout = {
223 .pos = 2,
224 .size = 3,
225 .xstride = { 4 },
226 .pstride = { 5 },
227 .default_color = 6,
228 .chroma_key = 7,
229 .chroma_key_mask = 8,
230 .general_config = 9,
231 },
232 },
233};
234
235static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_sama5d3 = {
236 .min_width = 0,
237 .min_height = 0,
238 .max_width = 2048,
239 .max_height = 2048,
240 .nlayers = ARRAY_SIZE(atmel_hlcdc_sama5d3_layers),
241 .layers = atmel_hlcdc_sama5d3_layers,
242};
243
244static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sama5d4_layers[] = {
245 {
246 .name = "base",
247 .formats = &atmel_hlcdc_plane_rgb_formats,
248 .regs_offset = 0x40,
249 .id = 0,
250 .type = ATMEL_HLCDC_BASE_LAYER,
251 .nconfigs = 7,
252 .layout = {
253 .xstride = { 2 },
254 .default_color = 3,
255 .general_config = 4,
256 .disc_pos = 5,
257 .disc_size = 6,
258 },
259 },
260 {
261 .name = "overlay1",
262 .formats = &atmel_hlcdc_plane_rgb_formats,
263 .regs_offset = 0x140,
264 .id = 1,
265 .type = ATMEL_HLCDC_OVERLAY_LAYER,
266 .nconfigs = 10,
267 .layout = {
268 .pos = 2,
269 .size = 3,
270 .xstride = { 4 },
271 .pstride = { 5 },
272 .default_color = 6,
273 .chroma_key = 7,
274 .chroma_key_mask = 8,
275 .general_config = 9,
276 },
277 },
278 {
279 .name = "overlay2",
280 .formats = &atmel_hlcdc_plane_rgb_formats,
281 .regs_offset = 0x240,
282 .id = 2,
283 .type = ATMEL_HLCDC_OVERLAY_LAYER,
284 .nconfigs = 10,
285 .layout = {
286 .pos = 2,
287 .size = 3,
288 .xstride = { 4 },
289 .pstride = { 5 },
290 .default_color = 6,
291 .chroma_key = 7,
292 .chroma_key_mask = 8,
293 .general_config = 9,
294 },
295 },
296 {
297 .name = "high-end-overlay",
298 .formats = &atmel_hlcdc_plane_rgb_and_yuv_formats,
299 .regs_offset = 0x340,
300 .id = 3,
301 .type = ATMEL_HLCDC_OVERLAY_LAYER,
302 .nconfigs = 42,
303 .layout = {
304 .pos = 2,
305 .size = 3,
306 .memsize = 4,
307 .xstride = { 5, 7 },
308 .pstride = { 6, 8 },
309 .default_color = 9,
310 .chroma_key = 10,
311 .chroma_key_mask = 11,
312 .general_config = 12,
313 .csc = 14,
314 },
315 },
316};
317
318static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_sama5d4 = {
319 .min_width = 0,
320 .min_height = 0,
321 .max_width = 2048,
322 .max_height = 2048,
323 .nlayers = ARRAY_SIZE(atmel_hlcdc_sama5d4_layers),
324 .layers = atmel_hlcdc_sama5d4_layers,
325};
326static const struct of_device_id atmel_hlcdc_of_match[] = {
327 {
328 .compatible = "atmel,at91sam9n12-hlcdc",
329 .data = &atmel_hlcdc_dc_at91sam9n12,
330 },
331 {
332 .compatible = "atmel,at91sam9x5-hlcdc",
333 .data = &atmel_hlcdc_dc_at91sam9x5,
334 },
335 {
336 .compatible = "atmel,sama5d2-hlcdc",
337 .data = &atmel_hlcdc_dc_sama5d4,
338 },
339 {
340 .compatible = "atmel,sama5d3-hlcdc",
341 .data = &atmel_hlcdc_dc_sama5d3,
342 },
343 {
344 .compatible = "atmel,sama5d4-hlcdc",
345 .data = &atmel_hlcdc_dc_sama5d4,
346 },
347 { /* sentinel */ },
348};
349MODULE_DEVICE_TABLE(of, atmel_hlcdc_of_match);
350
351int atmel_hlcdc_dc_mode_valid(struct atmel_hlcdc_dc *dc,
352 struct drm_display_mode *mode)
353{
354 int vfront_porch = mode->vsync_start - mode->vdisplay;
355 int vback_porch = mode->vtotal - mode->vsync_end;
356 int vsync_len = mode->vsync_end - mode->vsync_start;
357 int hfront_porch = mode->hsync_start - mode->hdisplay;
358 int hback_porch = mode->htotal - mode->hsync_end;
359 int hsync_len = mode->hsync_end - mode->hsync_start;
360
361 if (hsync_len > 0x40 || hsync_len < 1)
362 return MODE_HSYNC;
363
364 if (vsync_len > 0x40 || vsync_len < 1)
365 return MODE_VSYNC;
366
367 if (hfront_porch > 0x200 || hfront_porch < 1 ||
368 hback_porch > 0x200 || hback_porch < 1 ||
369 mode->hdisplay < 1)
370 return MODE_H_ILLEGAL;
371
372 if (vfront_porch > 0x40 || vfront_porch < 1 ||
373 vback_porch > 0x40 || vback_porch < 0 ||
374 mode->vdisplay < 1)
375 return MODE_V_ILLEGAL;
376
377 return MODE_OK;
378}
379
380static irqreturn_t atmel_hlcdc_dc_irq_handler(int irq, void *data)
381{
382 struct drm_device *dev = data;
383 struct atmel_hlcdc_dc *dc = dev->dev_private;
384 unsigned long status;
385 unsigned int imr, isr;
386 int i;
387
388 regmap_read(dc->hlcdc->regmap, ATMEL_HLCDC_IMR, &imr);
389 regmap_read(dc->hlcdc->regmap, ATMEL_HLCDC_ISR, &isr);
390 status = imr & isr;
391 if (!status)
392 return IRQ_NONE;
393
394 if (status & ATMEL_HLCDC_SOF)
395 atmel_hlcdc_crtc_irq(dc->crtc);
396
397 for (i = 0; i < ATMEL_HLCDC_MAX_LAYERS; i++) {
398 struct atmel_hlcdc_layer *layer = dc->layers[i];
399
400 if (!(ATMEL_HLCDC_LAYER_STATUS(i) & status) || !layer)
401 continue;
402
403 atmel_hlcdc_layer_irq(layer);
404 }
405
406 return IRQ_HANDLED;
407}
408
409static struct drm_framebuffer *atmel_hlcdc_fb_create(struct drm_device *dev,
410 struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd)
411{
412 return drm_fb_cma_create(dev, file_priv, mode_cmd);
413}
414
415static void atmel_hlcdc_fb_output_poll_changed(struct drm_device *dev)
416{
417 struct atmel_hlcdc_dc *dc = dev->dev_private;
418
419 if (dc->fbdev) {
420 drm_fbdev_cma_hotplug_event(dc->fbdev);
421 } else {
422 dc->fbdev = drm_fbdev_cma_init(dev, 24,
423 dev->mode_config.num_crtc,
424 dev->mode_config.num_connector);
425 if (IS_ERR(dc->fbdev))
426 dc->fbdev = NULL;
427 }
428}
429
430static const struct drm_mode_config_funcs mode_config_funcs = {
431 .fb_create = atmel_hlcdc_fb_create,
432 .output_poll_changed = atmel_hlcdc_fb_output_poll_changed,
433 .atomic_check = drm_atomic_helper_check,
434 .atomic_commit = drm_atomic_helper_commit,
435};
436
437static int atmel_hlcdc_dc_modeset_init(struct drm_device *dev)
438{
439 struct atmel_hlcdc_dc *dc = dev->dev_private;
440 struct atmel_hlcdc_planes *planes;
441 int ret;
442 int i;
443
444 drm_mode_config_init(dev);
445
446 ret = atmel_hlcdc_create_outputs(dev);
447 if (ret) {
448 dev_err(dev->dev, "failed to create panel: %d\n", ret);
449 return ret;
450 }
451
452 planes = atmel_hlcdc_create_planes(dev);
453 if (IS_ERR(planes)) {
454 dev_err(dev->dev, "failed to create planes\n");
455 return PTR_ERR(planes);
456 }
457
458 dc->planes = planes;
459
460 dc->layers[planes->primary->layer.desc->id] =
461 &planes->primary->layer;
462
463 if (planes->cursor)
464 dc->layers[planes->cursor->layer.desc->id] =
465 &planes->cursor->layer;
466
467 for (i = 0; i < planes->noverlays; i++)
468 dc->layers[planes->overlays[i]->layer.desc->id] =
469 &planes->overlays[i]->layer;
470
471 ret = atmel_hlcdc_crtc_create(dev);
472 if (ret) {
473 dev_err(dev->dev, "failed to create crtc\n");
474 return ret;
475 }
476
477 dev->mode_config.min_width = dc->desc->min_width;
478 dev->mode_config.min_height = dc->desc->min_height;
479 dev->mode_config.max_width = dc->desc->max_width;
480 dev->mode_config.max_height = dc->desc->max_height;
481 dev->mode_config.funcs = &mode_config_funcs;
482
483 return 0;
484}
485
486static int atmel_hlcdc_dc_load(struct drm_device *dev)
487{
488 struct platform_device *pdev = to_platform_device(dev->dev);
489 const struct of_device_id *match;
490 struct atmel_hlcdc_dc *dc;
491 int ret;
492
493 match = of_match_node(atmel_hlcdc_of_match, dev->dev->parent->of_node);
494 if (!match) {
495 dev_err(&pdev->dev, "invalid compatible string\n");
496 return -ENODEV;
497 }
498
499 if (!match->data) {
500 dev_err(&pdev->dev, "invalid hlcdc description\n");
501 return -EINVAL;
502 }
503
504 dc = devm_kzalloc(dev->dev, sizeof(*dc), GFP_KERNEL);
505 if (!dc)
506 return -ENOMEM;
507
508 dc->wq = alloc_ordered_workqueue("atmel-hlcdc-dc", 0);
509 if (!dc->wq)
510 return -ENOMEM;
511
512 dc->desc = match->data;
513 dc->hlcdc = dev_get_drvdata(dev->dev->parent);
514 dev->dev_private = dc;
515
516 ret = clk_prepare_enable(dc->hlcdc->periph_clk);
517 if (ret) {
518 dev_err(dev->dev, "failed to enable periph_clk\n");
519 goto err_destroy_wq;
520 }
521
522 pm_runtime_enable(dev->dev);
523
524 ret = drm_vblank_init(dev, 1);
525 if (ret < 0) {
526 dev_err(dev->dev, "failed to initialize vblank\n");
527 goto err_periph_clk_disable;
528 }
529
530 ret = atmel_hlcdc_dc_modeset_init(dev);
531 if (ret < 0) {
532 dev_err(dev->dev, "failed to initialize mode setting\n");
533 goto err_periph_clk_disable;
534 }
535
536 drm_mode_config_reset(dev);
537
538 pm_runtime_get_sync(dev->dev);
539 ret = drm_irq_install(dev, dc->hlcdc->irq);
540 pm_runtime_put_sync(dev->dev);
541 if (ret < 0) {
542 dev_err(dev->dev, "failed to install IRQ handler\n");
543 goto err_periph_clk_disable;
544 }
545
546 platform_set_drvdata(pdev, dev);
547
548 drm_kms_helper_poll_init(dev);
549
550 /* force connectors detection */
551 drm_helper_hpd_irq_event(dev);
552
553 return 0;
554
555err_periph_clk_disable:
556 pm_runtime_disable(dev->dev);
557 clk_disable_unprepare(dc->hlcdc->periph_clk);
558
559err_destroy_wq:
560 destroy_workqueue(dc->wq);
561
562 return ret;
563}
564
565static void atmel_hlcdc_dc_unload(struct drm_device *dev)
566{
567 struct atmel_hlcdc_dc *dc = dev->dev_private;
568
569 if (dc->fbdev)
570 drm_fbdev_cma_fini(dc->fbdev);
571 flush_workqueue(dc->wq);
572 drm_kms_helper_poll_fini(dev);
573 drm_mode_config_cleanup(dev);
574 drm_vblank_cleanup(dev);
575
576 pm_runtime_get_sync(dev->dev);
577 drm_irq_uninstall(dev);
578 pm_runtime_put_sync(dev->dev);
579
580 dev->dev_private = NULL;
581
582 pm_runtime_disable(dev->dev);
583 clk_disable_unprepare(dc->hlcdc->periph_clk);
584 destroy_workqueue(dc->wq);
585}
586
587static int atmel_hlcdc_dc_connector_plug_all(struct drm_device *dev)
588{
589 struct drm_connector *connector, *failed;
590 int ret;
591
592 mutex_lock(&dev->mode_config.mutex);
593 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
594 ret = drm_connector_register(connector);
595 if (ret) {
596 failed = connector;
597 goto err;
598 }
599 }
600 mutex_unlock(&dev->mode_config.mutex);
601 return 0;
602
603err:
604 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
605 if (failed == connector)
606 break;
607
608 drm_connector_unregister(connector);
609 }
610 mutex_unlock(&dev->mode_config.mutex);
611
612 return ret;
613}
614
615static void atmel_hlcdc_dc_connector_unplug_all(struct drm_device *dev)
616{
617 mutex_lock(&dev->mode_config.mutex);
618 drm_connector_unplug_all(dev);
619 mutex_unlock(&dev->mode_config.mutex);
620}
621
622static void atmel_hlcdc_dc_lastclose(struct drm_device *dev)
623{
624 struct atmel_hlcdc_dc *dc = dev->dev_private;
625
626 drm_fbdev_cma_restore_mode(dc->fbdev);
627}
628
629static int atmel_hlcdc_dc_irq_postinstall(struct drm_device *dev)
630{
631 struct atmel_hlcdc_dc *dc = dev->dev_private;
632 unsigned int cfg = 0;
633 int i;
634
635 /* Enable interrupts on activated layers */
636 for (i = 0; i < ATMEL_HLCDC_MAX_LAYERS; i++) {
637 if (dc->layers[i])
638 cfg |= ATMEL_HLCDC_LAYER_STATUS(i);
639 }
640
641 regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IER, cfg);
642
643 return 0;
644}
645
646static void atmel_hlcdc_dc_irq_uninstall(struct drm_device *dev)
647{
648 struct atmel_hlcdc_dc *dc = dev->dev_private;
649 unsigned int isr;
650
651 regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IDR, 0xffffffff);
652 regmap_read(dc->hlcdc->regmap, ATMEL_HLCDC_ISR, &isr);
653}
654
655static int atmel_hlcdc_dc_enable_vblank(struct drm_device *dev,
656 unsigned int pipe)
657{
658 struct atmel_hlcdc_dc *dc = dev->dev_private;
659
660 /* Enable SOF (Start Of Frame) interrupt for vblank counting */
661 regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IER, ATMEL_HLCDC_SOF);
662
663 return 0;
664}
665
666static void atmel_hlcdc_dc_disable_vblank(struct drm_device *dev,
667 unsigned int pipe)
668{
669 struct atmel_hlcdc_dc *dc = dev->dev_private;
670
671 regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IDR, ATMEL_HLCDC_SOF);
672}
673
674static const struct file_operations fops = {
675 .owner = THIS_MODULE,
676 .open = drm_open,
677 .release = drm_release,
678 .unlocked_ioctl = drm_ioctl,
679#ifdef CONFIG_COMPAT
680 .compat_ioctl = drm_compat_ioctl,
681#endif
682 .poll = drm_poll,
683 .read = drm_read,
684 .llseek = no_llseek,
685 .mmap = drm_gem_cma_mmap,
686};
687
688static struct drm_driver atmel_hlcdc_dc_driver = {
689 .driver_features = DRIVER_HAVE_IRQ | DRIVER_GEM |
690 DRIVER_MODESET | DRIVER_PRIME |
691 DRIVER_ATOMIC,
692 .lastclose = atmel_hlcdc_dc_lastclose,
693 .irq_handler = atmel_hlcdc_dc_irq_handler,
694 .irq_preinstall = atmel_hlcdc_dc_irq_uninstall,
695 .irq_postinstall = atmel_hlcdc_dc_irq_postinstall,
696 .irq_uninstall = atmel_hlcdc_dc_irq_uninstall,
697 .get_vblank_counter = drm_vblank_no_hw_counter,
698 .enable_vblank = atmel_hlcdc_dc_enable_vblank,
699 .disable_vblank = atmel_hlcdc_dc_disable_vblank,
700 .gem_free_object = drm_gem_cma_free_object,
701 .gem_vm_ops = &drm_gem_cma_vm_ops,
702 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
703 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
704 .gem_prime_import = drm_gem_prime_import,
705 .gem_prime_export = drm_gem_prime_export,
706 .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
707 .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
708 .gem_prime_vmap = drm_gem_cma_prime_vmap,
709 .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
710 .gem_prime_mmap = drm_gem_cma_prime_mmap,
711 .dumb_create = drm_gem_cma_dumb_create,
712 .dumb_map_offset = drm_gem_cma_dumb_map_offset,
713 .dumb_destroy = drm_gem_dumb_destroy,
714 .fops = &fops,
715 .name = "atmel-hlcdc",
716 .desc = "Atmel HLCD Controller DRM",
717 .date = "20141504",
718 .major = 1,
719 .minor = 0,
720};
721
722static int atmel_hlcdc_dc_drm_probe(struct platform_device *pdev)
723{
724 struct drm_device *ddev;
725 int ret;
726
727 ddev = drm_dev_alloc(&atmel_hlcdc_dc_driver, &pdev->dev);
728 if (!ddev)
729 return -ENOMEM;
730
731 ret = atmel_hlcdc_dc_load(ddev);
732 if (ret)
733 goto err_unref;
734
735 ret = drm_dev_register(ddev, 0);
736 if (ret)
737 goto err_unload;
738
739 ret = atmel_hlcdc_dc_connector_plug_all(ddev);
740 if (ret)
741 goto err_unregister;
742
743 return 0;
744
745err_unregister:
746 drm_dev_unregister(ddev);
747
748err_unload:
749 atmel_hlcdc_dc_unload(ddev);
750
751err_unref:
752 drm_dev_unref(ddev);
753
754 return ret;
755}
756
757static int atmel_hlcdc_dc_drm_remove(struct platform_device *pdev)
758{
759 struct drm_device *ddev = platform_get_drvdata(pdev);
760
761 atmel_hlcdc_dc_connector_unplug_all(ddev);
762 drm_dev_unregister(ddev);
763 atmel_hlcdc_dc_unload(ddev);
764 drm_dev_unref(ddev);
765
766 return 0;
767}
768
769#ifdef CONFIG_PM_SLEEP
770static int atmel_hlcdc_dc_drm_suspend(struct device *dev)
771{
772 struct drm_device *drm_dev = dev_get_drvdata(dev);
773 struct drm_crtc *crtc;
774
775 if (pm_runtime_suspended(dev))
776 return 0;
777
778 drm_modeset_lock_all(drm_dev);
779 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head)
780 atmel_hlcdc_crtc_suspend(crtc);
781 drm_modeset_unlock_all(drm_dev);
782 return 0;
783}
784
785static int atmel_hlcdc_dc_drm_resume(struct device *dev)
786{
787 struct drm_device *drm_dev = dev_get_drvdata(dev);
788 struct drm_crtc *crtc;
789
790 if (pm_runtime_suspended(dev))
791 return 0;
792
793 drm_modeset_lock_all(drm_dev);
794 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head)
795 atmel_hlcdc_crtc_resume(crtc);
796 drm_modeset_unlock_all(drm_dev);
797 return 0;
798}
799#endif
800
801static SIMPLE_DEV_PM_OPS(atmel_hlcdc_dc_drm_pm_ops,
802 atmel_hlcdc_dc_drm_suspend, atmel_hlcdc_dc_drm_resume);
803
804static const struct of_device_id atmel_hlcdc_dc_of_match[] = {
805 { .compatible = "atmel,hlcdc-display-controller" },
806 { },
807};
808
809static struct platform_driver atmel_hlcdc_dc_platform_driver = {
810 .probe = atmel_hlcdc_dc_drm_probe,
811 .remove = atmel_hlcdc_dc_drm_remove,
812 .driver = {
813 .name = "atmel-hlcdc-display-controller",
814 .pm = &atmel_hlcdc_dc_drm_pm_ops,
815 .of_match_table = atmel_hlcdc_dc_of_match,
816 },
817};
818module_platform_driver(atmel_hlcdc_dc_platform_driver);
819
820MODULE_AUTHOR("Jean-Jacques Hiblot <jjhiblot@traphandler.com>");
821MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>");
822MODULE_DESCRIPTION("Atmel HLCDC Display Controller DRM Driver");
823MODULE_LICENSE("GPL");
824MODULE_ALIAS("platform:atmel-hlcdc-dc");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2014 Traphandler
4 * Copyright (C) 2014 Free Electrons
5 * Copyright (C) 2014 Atmel
6 *
7 * Author: Jean-Jacques Hiblot <jjhiblot@traphandler.com>
8 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
9 */
10
11#include <linux/clk.h>
12#include <linux/irq.h>
13#include <linux/irqchip.h>
14#include <linux/mfd/atmel-hlcdc.h>
15#include <linux/module.h>
16#include <linux/pm_runtime.h>
17#include <linux/platform_device.h>
18
19#include <drm/drm_atomic.h>
20#include <drm/drm_atomic_helper.h>
21#include <drm/drm_client_setup.h>
22#include <drm/drm_drv.h>
23#include <drm/drm_fbdev_dma.h>
24#include <drm/drm_fourcc.h>
25#include <drm/drm_gem_dma_helper.h>
26#include <drm/drm_gem_framebuffer_helper.h>
27#include <drm/drm_module.h>
28#include <drm/drm_probe_helper.h>
29#include <drm/drm_vblank.h>
30
31#include "atmel_hlcdc_dc.h"
32
33#define ATMEL_HLCDC_LAYER_IRQS_OFFSET 8
34
35static const struct atmel_hlcdc_layer_desc atmel_hlcdc_at91sam9n12_layers[] = {
36 {
37 .name = "base",
38 .formats = &atmel_hlcdc_plane_rgb_formats,
39 .regs_offset = 0x40,
40 .id = 0,
41 .type = ATMEL_HLCDC_BASE_LAYER,
42 .cfgs_offset = 0x2c,
43 .layout = {
44 .xstride = { 2 },
45 .default_color = 3,
46 .general_config = 4,
47 },
48 .clut_offset = 0x400,
49 },
50};
51
52static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_at91sam9n12 = {
53 .min_width = 0,
54 .min_height = 0,
55 .max_width = 1280,
56 .max_height = 860,
57 .max_spw = 0x3f,
58 .max_vpw = 0x3f,
59 .max_hpw = 0xff,
60 .conflicting_output_formats = true,
61 .nlayers = ARRAY_SIZE(atmel_hlcdc_at91sam9n12_layers),
62 .layers = atmel_hlcdc_at91sam9n12_layers,
63 .ops = &atmel_hlcdc_ops,
64};
65
66static const struct atmel_hlcdc_layer_desc atmel_hlcdc_at91sam9x5_layers[] = {
67 {
68 .name = "base",
69 .formats = &atmel_hlcdc_plane_rgb_formats,
70 .regs_offset = 0x40,
71 .id = 0,
72 .type = ATMEL_HLCDC_BASE_LAYER,
73 .cfgs_offset = 0x2c,
74 .layout = {
75 .xstride = { 2 },
76 .default_color = 3,
77 .general_config = 4,
78 .disc_pos = 5,
79 .disc_size = 6,
80 },
81 .clut_offset = 0x400,
82 },
83 {
84 .name = "overlay1",
85 .formats = &atmel_hlcdc_plane_rgb_formats,
86 .regs_offset = 0x100,
87 .id = 1,
88 .type = ATMEL_HLCDC_OVERLAY_LAYER,
89 .cfgs_offset = 0x2c,
90 .layout = {
91 .pos = 2,
92 .size = 3,
93 .xstride = { 4 },
94 .pstride = { 5 },
95 .default_color = 6,
96 .chroma_key = 7,
97 .chroma_key_mask = 8,
98 .general_config = 9,
99 },
100 .clut_offset = 0x800,
101 },
102 {
103 .name = "high-end-overlay",
104 .formats = &atmel_hlcdc_plane_rgb_and_yuv_formats,
105 .regs_offset = 0x280,
106 .id = 2,
107 .type = ATMEL_HLCDC_OVERLAY_LAYER,
108 .cfgs_offset = 0x4c,
109 .layout = {
110 .pos = 2,
111 .size = 3,
112 .memsize = 4,
113 .xstride = { 5, 7 },
114 .pstride = { 6, 8 },
115 .default_color = 9,
116 .chroma_key = 10,
117 .chroma_key_mask = 11,
118 .general_config = 12,
119 .scaler_config = 13,
120 .csc = 14,
121 },
122 .clut_offset = 0x1000,
123 },
124 {
125 .name = "cursor",
126 .formats = &atmel_hlcdc_plane_rgb_formats,
127 .regs_offset = 0x340,
128 .id = 3,
129 .type = ATMEL_HLCDC_CURSOR_LAYER,
130 .max_width = 128,
131 .max_height = 128,
132 .cfgs_offset = 0x2c,
133 .layout = {
134 .pos = 2,
135 .size = 3,
136 .xstride = { 4 },
137 .default_color = 6,
138 .chroma_key = 7,
139 .chroma_key_mask = 8,
140 .general_config = 9,
141 },
142 .clut_offset = 0x1400,
143 },
144};
145
146static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_at91sam9x5 = {
147 .min_width = 0,
148 .min_height = 0,
149 .max_width = 800,
150 .max_height = 600,
151 .max_spw = 0x3f,
152 .max_vpw = 0x3f,
153 .max_hpw = 0xff,
154 .conflicting_output_formats = true,
155 .nlayers = ARRAY_SIZE(atmel_hlcdc_at91sam9x5_layers),
156 .layers = atmel_hlcdc_at91sam9x5_layers,
157 .ops = &atmel_hlcdc_ops,
158};
159
160static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sama5d3_layers[] = {
161 {
162 .name = "base",
163 .formats = &atmel_hlcdc_plane_rgb_formats,
164 .regs_offset = 0x40,
165 .id = 0,
166 .type = ATMEL_HLCDC_BASE_LAYER,
167 .cfgs_offset = 0x2c,
168 .layout = {
169 .xstride = { 2 },
170 .default_color = 3,
171 .general_config = 4,
172 .disc_pos = 5,
173 .disc_size = 6,
174 },
175 .clut_offset = 0x600,
176 },
177 {
178 .name = "overlay1",
179 .formats = &atmel_hlcdc_plane_rgb_formats,
180 .regs_offset = 0x140,
181 .id = 1,
182 .type = ATMEL_HLCDC_OVERLAY_LAYER,
183 .cfgs_offset = 0x2c,
184 .layout = {
185 .pos = 2,
186 .size = 3,
187 .xstride = { 4 },
188 .pstride = { 5 },
189 .default_color = 6,
190 .chroma_key = 7,
191 .chroma_key_mask = 8,
192 .general_config = 9,
193 },
194 .clut_offset = 0xa00,
195 },
196 {
197 .name = "overlay2",
198 .formats = &atmel_hlcdc_plane_rgb_formats,
199 .regs_offset = 0x240,
200 .id = 2,
201 .type = ATMEL_HLCDC_OVERLAY_LAYER,
202 .cfgs_offset = 0x2c,
203 .layout = {
204 .pos = 2,
205 .size = 3,
206 .xstride = { 4 },
207 .pstride = { 5 },
208 .default_color = 6,
209 .chroma_key = 7,
210 .chroma_key_mask = 8,
211 .general_config = 9,
212 },
213 .clut_offset = 0xe00,
214 },
215 {
216 .name = "high-end-overlay",
217 .formats = &atmel_hlcdc_plane_rgb_and_yuv_formats,
218 .regs_offset = 0x340,
219 .id = 3,
220 .type = ATMEL_HLCDC_OVERLAY_LAYER,
221 .cfgs_offset = 0x4c,
222 .layout = {
223 .pos = 2,
224 .size = 3,
225 .memsize = 4,
226 .xstride = { 5, 7 },
227 .pstride = { 6, 8 },
228 .default_color = 9,
229 .chroma_key = 10,
230 .chroma_key_mask = 11,
231 .general_config = 12,
232 .scaler_config = 13,
233 .phicoeffs = {
234 .x = 17,
235 .y = 33,
236 },
237 .csc = 14,
238 },
239 .clut_offset = 0x1200,
240 },
241 {
242 .name = "cursor",
243 .formats = &atmel_hlcdc_plane_rgb_formats,
244 .regs_offset = 0x440,
245 .id = 4,
246 .type = ATMEL_HLCDC_CURSOR_LAYER,
247 .max_width = 128,
248 .max_height = 128,
249 .cfgs_offset = 0x2c,
250 .layout = {
251 .pos = 2,
252 .size = 3,
253 .xstride = { 4 },
254 .pstride = { 5 },
255 .default_color = 6,
256 .chroma_key = 7,
257 .chroma_key_mask = 8,
258 .general_config = 9,
259 .scaler_config = 13,
260 },
261 .clut_offset = 0x1600,
262 },
263};
264
265static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_sama5d3 = {
266 .min_width = 0,
267 .min_height = 0,
268 .max_width = 2048,
269 .max_height = 2048,
270 .max_spw = 0x3f,
271 .max_vpw = 0x3f,
272 .max_hpw = 0x1ff,
273 .conflicting_output_formats = true,
274 .nlayers = ARRAY_SIZE(atmel_hlcdc_sama5d3_layers),
275 .layers = atmel_hlcdc_sama5d3_layers,
276 .ops = &atmel_hlcdc_ops,
277};
278
279static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sama5d4_layers[] = {
280 {
281 .name = "base",
282 .formats = &atmel_hlcdc_plane_rgb_formats,
283 .regs_offset = 0x40,
284 .id = 0,
285 .type = ATMEL_HLCDC_BASE_LAYER,
286 .cfgs_offset = 0x2c,
287 .layout = {
288 .xstride = { 2 },
289 .default_color = 3,
290 .general_config = 4,
291 .disc_pos = 5,
292 .disc_size = 6,
293 },
294 .clut_offset = 0x600,
295 },
296 {
297 .name = "overlay1",
298 .formats = &atmel_hlcdc_plane_rgb_formats,
299 .regs_offset = 0x140,
300 .id = 1,
301 .type = ATMEL_HLCDC_OVERLAY_LAYER,
302 .cfgs_offset = 0x2c,
303 .layout = {
304 .pos = 2,
305 .size = 3,
306 .xstride = { 4 },
307 .pstride = { 5 },
308 .default_color = 6,
309 .chroma_key = 7,
310 .chroma_key_mask = 8,
311 .general_config = 9,
312 },
313 .clut_offset = 0xa00,
314 },
315 {
316 .name = "overlay2",
317 .formats = &atmel_hlcdc_plane_rgb_formats,
318 .regs_offset = 0x240,
319 .id = 2,
320 .type = ATMEL_HLCDC_OVERLAY_LAYER,
321 .cfgs_offset = 0x2c,
322 .layout = {
323 .pos = 2,
324 .size = 3,
325 .xstride = { 4 },
326 .pstride = { 5 },
327 .default_color = 6,
328 .chroma_key = 7,
329 .chroma_key_mask = 8,
330 .general_config = 9,
331 },
332 .clut_offset = 0xe00,
333 },
334 {
335 .name = "high-end-overlay",
336 .formats = &atmel_hlcdc_plane_rgb_and_yuv_formats,
337 .regs_offset = 0x340,
338 .id = 3,
339 .type = ATMEL_HLCDC_OVERLAY_LAYER,
340 .cfgs_offset = 0x4c,
341 .layout = {
342 .pos = 2,
343 .size = 3,
344 .memsize = 4,
345 .xstride = { 5, 7 },
346 .pstride = { 6, 8 },
347 .default_color = 9,
348 .chroma_key = 10,
349 .chroma_key_mask = 11,
350 .general_config = 12,
351 .scaler_config = 13,
352 .phicoeffs = {
353 .x = 17,
354 .y = 33,
355 },
356 .csc = 14,
357 },
358 .clut_offset = 0x1200,
359 },
360};
361
362static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_sama5d4 = {
363 .min_width = 0,
364 .min_height = 0,
365 .max_width = 2048,
366 .max_height = 2048,
367 .max_spw = 0xff,
368 .max_vpw = 0xff,
369 .max_hpw = 0x3ff,
370 .nlayers = ARRAY_SIZE(atmel_hlcdc_sama5d4_layers),
371 .layers = atmel_hlcdc_sama5d4_layers,
372 .ops = &atmel_hlcdc_ops,
373};
374
375static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sam9x60_layers[] = {
376 {
377 .name = "base",
378 .formats = &atmel_hlcdc_plane_rgb_formats,
379 .regs_offset = 0x60,
380 .id = 0,
381 .type = ATMEL_HLCDC_BASE_LAYER,
382 .cfgs_offset = 0x2c,
383 .layout = {
384 .xstride = { 2 },
385 .default_color = 3,
386 .general_config = 4,
387 .disc_pos = 5,
388 .disc_size = 6,
389 },
390 .clut_offset = 0x600,
391 },
392 {
393 .name = "overlay1",
394 .formats = &atmel_hlcdc_plane_rgb_formats,
395 .regs_offset = 0x160,
396 .id = 1,
397 .type = ATMEL_HLCDC_OVERLAY_LAYER,
398 .cfgs_offset = 0x2c,
399 .layout = {
400 .pos = 2,
401 .size = 3,
402 .xstride = { 4 },
403 .pstride = { 5 },
404 .default_color = 6,
405 .chroma_key = 7,
406 .chroma_key_mask = 8,
407 .general_config = 9,
408 },
409 .clut_offset = 0xa00,
410 },
411 {
412 .name = "overlay2",
413 .formats = &atmel_hlcdc_plane_rgb_formats,
414 .regs_offset = 0x260,
415 .id = 2,
416 .type = ATMEL_HLCDC_OVERLAY_LAYER,
417 .cfgs_offset = 0x2c,
418 .layout = {
419 .pos = 2,
420 .size = 3,
421 .xstride = { 4 },
422 .pstride = { 5 },
423 .default_color = 6,
424 .chroma_key = 7,
425 .chroma_key_mask = 8,
426 .general_config = 9,
427 },
428 .clut_offset = 0xe00,
429 },
430 {
431 .name = "high-end-overlay",
432 .formats = &atmel_hlcdc_plane_rgb_and_yuv_formats,
433 .regs_offset = 0x360,
434 .id = 3,
435 .type = ATMEL_HLCDC_OVERLAY_LAYER,
436 .cfgs_offset = 0x4c,
437 .layout = {
438 .pos = 2,
439 .size = 3,
440 .memsize = 4,
441 .xstride = { 5, 7 },
442 .pstride = { 6, 8 },
443 .default_color = 9,
444 .chroma_key = 10,
445 .chroma_key_mask = 11,
446 .general_config = 12,
447 .scaler_config = 13,
448 .phicoeffs = {
449 .x = 17,
450 .y = 33,
451 },
452 .csc = 14,
453 },
454 .clut_offset = 0x1200,
455 },
456};
457
458static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_sam9x60 = {
459 .min_width = 0,
460 .min_height = 0,
461 .max_width = 2048,
462 .max_height = 2048,
463 .max_spw = 0xff,
464 .max_vpw = 0xff,
465 .max_hpw = 0x3ff,
466 .fixed_clksrc = true,
467 .nlayers = ARRAY_SIZE(atmel_hlcdc_sam9x60_layers),
468 .layers = atmel_hlcdc_sam9x60_layers,
469 .ops = &atmel_hlcdc_ops,
470};
471
472static const struct atmel_hlcdc_layer_desc atmel_xlcdc_sam9x75_layers[] = {
473 {
474 .name = "base",
475 .formats = &atmel_hlcdc_plane_rgb_formats,
476 .regs_offset = 0x60,
477 .id = 0,
478 .type = ATMEL_HLCDC_BASE_LAYER,
479 .cfgs_offset = 0x1c,
480 .layout = {
481 .xstride = { 2 },
482 .default_color = 3,
483 .general_config = 4,
484 .disc_pos = 5,
485 .disc_size = 6,
486 },
487 .clut_offset = 0x700,
488 },
489 {
490 .name = "overlay1",
491 .formats = &atmel_hlcdc_plane_rgb_formats,
492 .regs_offset = 0x160,
493 .id = 1,
494 .type = ATMEL_HLCDC_OVERLAY_LAYER,
495 .cfgs_offset = 0x1c,
496 .layout = {
497 .pos = 2,
498 .size = 3,
499 .xstride = { 4 },
500 .pstride = { 5 },
501 .default_color = 6,
502 .chroma_key = 7,
503 .chroma_key_mask = 8,
504 .general_config = 9,
505 },
506 .clut_offset = 0xb00,
507 },
508 {
509 .name = "overlay2",
510 .formats = &atmel_hlcdc_plane_rgb_formats,
511 .regs_offset = 0x260,
512 .id = 2,
513 .type = ATMEL_HLCDC_OVERLAY_LAYER,
514 .cfgs_offset = 0x1c,
515 .layout = {
516 .pos = 2,
517 .size = 3,
518 .xstride = { 4 },
519 .pstride = { 5 },
520 .default_color = 6,
521 .chroma_key = 7,
522 .chroma_key_mask = 8,
523 .general_config = 9,
524 },
525 .clut_offset = 0xf00,
526 },
527 {
528 .name = "high-end-overlay",
529 .formats = &atmel_hlcdc_plane_rgb_and_yuv_formats,
530 .regs_offset = 0x360,
531 .id = 3,
532 .type = ATMEL_HLCDC_OVERLAY_LAYER,
533 .cfgs_offset = 0x30,
534 .layout = {
535 .pos = 2,
536 .size = 3,
537 .memsize = 4,
538 .xstride = { 5, 7 },
539 .pstride = { 6, 8 },
540 .default_color = 9,
541 .chroma_key = 10,
542 .chroma_key_mask = 11,
543 .general_config = 12,
544 .csc = 16,
545 .scaler_config = 23,
546 .vxs_config = 30,
547 .hxs_config = 31,
548 },
549 .clut_offset = 0x1300,
550 },
551};
552
553static const struct atmel_hlcdc_dc_desc atmel_xlcdc_dc_sam9x75 = {
554 .min_width = 0,
555 .min_height = 0,
556 .max_width = 2048,
557 .max_height = 2048,
558 .max_spw = 0x3ff,
559 .max_vpw = 0x3ff,
560 .max_hpw = 0x3ff,
561 .fixed_clksrc = true,
562 .is_xlcdc = true,
563 .nlayers = ARRAY_SIZE(atmel_xlcdc_sam9x75_layers),
564 .layers = atmel_xlcdc_sam9x75_layers,
565 .ops = &atmel_xlcdc_ops,
566};
567
568static const struct of_device_id atmel_hlcdc_of_match[] = {
569 {
570 .compatible = "atmel,at91sam9n12-hlcdc",
571 .data = &atmel_hlcdc_dc_at91sam9n12,
572 },
573 {
574 .compatible = "atmel,at91sam9x5-hlcdc",
575 .data = &atmel_hlcdc_dc_at91sam9x5,
576 },
577 {
578 .compatible = "atmel,sama5d2-hlcdc",
579 .data = &atmel_hlcdc_dc_sama5d4,
580 },
581 {
582 .compatible = "atmel,sama5d3-hlcdc",
583 .data = &atmel_hlcdc_dc_sama5d3,
584 },
585 {
586 .compatible = "atmel,sama5d4-hlcdc",
587 .data = &atmel_hlcdc_dc_sama5d4,
588 },
589 {
590 .compatible = "microchip,sam9x60-hlcdc",
591 .data = &atmel_hlcdc_dc_sam9x60,
592 },
593 {
594 .compatible = "microchip,sam9x75-xlcdc",
595 .data = &atmel_xlcdc_dc_sam9x75,
596 },
597 { /* sentinel */ },
598};
599MODULE_DEVICE_TABLE(of, atmel_hlcdc_of_match);
600
601enum drm_mode_status
602atmel_hlcdc_dc_mode_valid(struct atmel_hlcdc_dc *dc,
603 const struct drm_display_mode *mode)
604{
605 int vfront_porch = mode->vsync_start - mode->vdisplay;
606 int vback_porch = mode->vtotal - mode->vsync_end;
607 int vsync_len = mode->vsync_end - mode->vsync_start;
608 int hfront_porch = mode->hsync_start - mode->hdisplay;
609 int hback_porch = mode->htotal - mode->hsync_end;
610 int hsync_len = mode->hsync_end - mode->hsync_start;
611
612 if (hsync_len > dc->desc->max_spw + 1 || hsync_len < 1)
613 return MODE_HSYNC;
614
615 if (vsync_len > dc->desc->max_spw + 1 || vsync_len < 1)
616 return MODE_VSYNC;
617
618 if (hfront_porch > dc->desc->max_hpw + 1 || hfront_porch < 1 ||
619 hback_porch > dc->desc->max_hpw + 1 || hback_porch < 1 ||
620 mode->hdisplay < 1)
621 return MODE_H_ILLEGAL;
622
623 if (vfront_porch > dc->desc->max_vpw + 1 || vfront_porch < 1 ||
624 vback_porch > dc->desc->max_vpw || vback_porch < 0 ||
625 mode->vdisplay < 1)
626 return MODE_V_ILLEGAL;
627
628 return MODE_OK;
629}
630
631static void atmel_hlcdc_layer_irq(struct atmel_hlcdc_layer *layer)
632{
633 if (!layer)
634 return;
635
636 if (layer->desc->type == ATMEL_HLCDC_BASE_LAYER ||
637 layer->desc->type == ATMEL_HLCDC_OVERLAY_LAYER ||
638 layer->desc->type == ATMEL_HLCDC_CURSOR_LAYER)
639 atmel_hlcdc_plane_irq(atmel_hlcdc_layer_to_plane(layer));
640}
641
642static irqreturn_t atmel_hlcdc_dc_irq_handler(int irq, void *data)
643{
644 struct drm_device *dev = data;
645 struct atmel_hlcdc_dc *dc = dev->dev_private;
646 unsigned long status;
647 unsigned int imr, isr;
648 int i;
649
650 regmap_read(dc->hlcdc->regmap, ATMEL_HLCDC_IMR, &imr);
651 regmap_read(dc->hlcdc->regmap, ATMEL_HLCDC_ISR, &isr);
652 status = imr & isr;
653 if (!status)
654 return IRQ_NONE;
655
656 if (status & ATMEL_HLCDC_SOF)
657 atmel_hlcdc_crtc_irq(dc->crtc);
658
659 for (i = 0; i < ATMEL_HLCDC_MAX_LAYERS; i++) {
660 if (ATMEL_HLCDC_LAYER_STATUS(i) & status)
661 atmel_hlcdc_layer_irq(dc->layers[i]);
662 }
663
664 return IRQ_HANDLED;
665}
666
667static void atmel_hlcdc_dc_irq_postinstall(struct drm_device *dev)
668{
669 struct atmel_hlcdc_dc *dc = dev->dev_private;
670 unsigned int cfg = 0;
671 int i;
672
673 /* Enable interrupts on activated layers */
674 for (i = 0; i < ATMEL_HLCDC_MAX_LAYERS; i++) {
675 if (dc->layers[i])
676 cfg |= ATMEL_HLCDC_LAYER_STATUS(i);
677 }
678
679 regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IER, cfg);
680}
681
682static void atmel_hlcdc_dc_irq_disable(struct drm_device *dev)
683{
684 struct atmel_hlcdc_dc *dc = dev->dev_private;
685 unsigned int isr;
686
687 regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IDR, 0xffffffff);
688 regmap_read(dc->hlcdc->regmap, ATMEL_HLCDC_ISR, &isr);
689}
690
691static int atmel_hlcdc_dc_irq_install(struct drm_device *dev, unsigned int irq)
692{
693 int ret;
694
695 atmel_hlcdc_dc_irq_disable(dev);
696
697 ret = devm_request_irq(dev->dev, irq, atmel_hlcdc_dc_irq_handler, 0,
698 dev->driver->name, dev);
699 if (ret)
700 return ret;
701
702 atmel_hlcdc_dc_irq_postinstall(dev);
703
704 return 0;
705}
706
707static void atmel_hlcdc_dc_irq_uninstall(struct drm_device *dev)
708{
709 atmel_hlcdc_dc_irq_disable(dev);
710}
711
712static const struct drm_mode_config_funcs mode_config_funcs = {
713 .fb_create = drm_gem_fb_create,
714 .atomic_check = drm_atomic_helper_check,
715 .atomic_commit = drm_atomic_helper_commit,
716};
717
718static int atmel_hlcdc_dc_modeset_init(struct drm_device *dev)
719{
720 struct atmel_hlcdc_dc *dc = dev->dev_private;
721 int ret;
722
723 drm_mode_config_init(dev);
724
725 ret = atmel_hlcdc_create_outputs(dev);
726 if (ret) {
727 dev_err(dev->dev, "failed to create HLCDC outputs: %d\n", ret);
728 return ret;
729 }
730
731 ret = atmel_hlcdc_create_planes(dev);
732 if (ret) {
733 dev_err(dev->dev, "failed to create planes: %d\n", ret);
734 return ret;
735 }
736
737 ret = atmel_hlcdc_crtc_create(dev);
738 if (ret) {
739 dev_err(dev->dev, "failed to create crtc\n");
740 return ret;
741 }
742
743 dev->mode_config.min_width = dc->desc->min_width;
744 dev->mode_config.min_height = dc->desc->min_height;
745 dev->mode_config.max_width = dc->desc->max_width;
746 dev->mode_config.max_height = dc->desc->max_height;
747 dev->mode_config.funcs = &mode_config_funcs;
748 dev->mode_config.async_page_flip = true;
749
750 return 0;
751}
752
753static int atmel_hlcdc_dc_load(struct drm_device *dev)
754{
755 struct platform_device *pdev = to_platform_device(dev->dev);
756 const struct of_device_id *match;
757 struct atmel_hlcdc_dc *dc;
758 int ret;
759
760 match = of_match_node(atmel_hlcdc_of_match, dev->dev->parent->of_node);
761 if (!match) {
762 dev_err(&pdev->dev, "invalid compatible string\n");
763 return -ENODEV;
764 }
765
766 if (!match->data) {
767 dev_err(&pdev->dev, "invalid hlcdc description\n");
768 return -EINVAL;
769 }
770
771 dc = devm_kzalloc(dev->dev, sizeof(*dc), GFP_KERNEL);
772 if (!dc)
773 return -ENOMEM;
774
775 dc->desc = match->data;
776 dc->hlcdc = dev_get_drvdata(dev->dev->parent);
777 dev->dev_private = dc;
778
779 ret = clk_prepare_enable(dc->hlcdc->periph_clk);
780 if (ret) {
781 dev_err(dev->dev, "failed to enable periph_clk\n");
782 return ret;
783 }
784
785 pm_runtime_enable(dev->dev);
786
787 ret = drm_vblank_init(dev, 1);
788 if (ret < 0) {
789 dev_err(dev->dev, "failed to initialize vblank\n");
790 goto err_periph_clk_disable;
791 }
792
793 ret = atmel_hlcdc_dc_modeset_init(dev);
794 if (ret < 0) {
795 dev_err(dev->dev, "failed to initialize mode setting\n");
796 goto err_periph_clk_disable;
797 }
798
799 drm_mode_config_reset(dev);
800
801 pm_runtime_get_sync(dev->dev);
802 ret = atmel_hlcdc_dc_irq_install(dev, dc->hlcdc->irq);
803 pm_runtime_put_sync(dev->dev);
804 if (ret < 0) {
805 dev_err(dev->dev, "failed to install IRQ handler\n");
806 goto err_periph_clk_disable;
807 }
808
809 platform_set_drvdata(pdev, dev);
810
811 drm_kms_helper_poll_init(dev);
812
813 return 0;
814
815err_periph_clk_disable:
816 pm_runtime_disable(dev->dev);
817 clk_disable_unprepare(dc->hlcdc->periph_clk);
818
819 return ret;
820}
821
822static void atmel_hlcdc_dc_unload(struct drm_device *dev)
823{
824 struct atmel_hlcdc_dc *dc = dev->dev_private;
825
826 drm_kms_helper_poll_fini(dev);
827 drm_atomic_helper_shutdown(dev);
828 drm_mode_config_cleanup(dev);
829
830 pm_runtime_get_sync(dev->dev);
831 atmel_hlcdc_dc_irq_uninstall(dev);
832 pm_runtime_put_sync(dev->dev);
833
834 dev->dev_private = NULL;
835
836 pm_runtime_disable(dev->dev);
837 clk_disable_unprepare(dc->hlcdc->periph_clk);
838}
839
840DEFINE_DRM_GEM_DMA_FOPS(fops);
841
842static const struct drm_driver atmel_hlcdc_dc_driver = {
843 .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
844 DRM_GEM_DMA_DRIVER_OPS,
845 DRM_FBDEV_DMA_DRIVER_OPS,
846 .fops = &fops,
847 .name = "atmel-hlcdc",
848 .desc = "Atmel HLCD Controller DRM",
849 .date = "20141504",
850 .major = 1,
851 .minor = 0,
852};
853
854static int atmel_hlcdc_dc_drm_probe(struct platform_device *pdev)
855{
856 struct drm_device *ddev;
857 int ret;
858
859 ddev = drm_dev_alloc(&atmel_hlcdc_dc_driver, &pdev->dev);
860 if (IS_ERR(ddev))
861 return PTR_ERR(ddev);
862
863 ret = atmel_hlcdc_dc_load(ddev);
864 if (ret)
865 goto err_put;
866
867 ret = drm_dev_register(ddev, 0);
868 if (ret)
869 goto err_unload;
870
871 drm_client_setup_with_fourcc(ddev, DRM_FORMAT_RGB888);
872
873 return 0;
874
875err_unload:
876 atmel_hlcdc_dc_unload(ddev);
877
878err_put:
879 drm_dev_put(ddev);
880
881 return ret;
882}
883
884static void atmel_hlcdc_dc_drm_remove(struct platform_device *pdev)
885{
886 struct drm_device *ddev = platform_get_drvdata(pdev);
887
888 drm_dev_unregister(ddev);
889 atmel_hlcdc_dc_unload(ddev);
890 drm_dev_put(ddev);
891}
892
893static void atmel_hlcdc_dc_drm_shutdown(struct platform_device *pdev)
894{
895 drm_atomic_helper_shutdown(platform_get_drvdata(pdev));
896}
897
898static int atmel_hlcdc_dc_drm_suspend(struct device *dev)
899{
900 struct drm_device *drm_dev = dev_get_drvdata(dev);
901 struct atmel_hlcdc_dc *dc = drm_dev->dev_private;
902 struct regmap *regmap = dc->hlcdc->regmap;
903 struct drm_atomic_state *state;
904
905 state = drm_atomic_helper_suspend(drm_dev);
906 if (IS_ERR(state))
907 return PTR_ERR(state);
908
909 dc->suspend.state = state;
910
911 regmap_read(regmap, ATMEL_HLCDC_IMR, &dc->suspend.imr);
912 regmap_write(regmap, ATMEL_HLCDC_IDR, dc->suspend.imr);
913 clk_disable_unprepare(dc->hlcdc->periph_clk);
914
915 return 0;
916}
917
918static int atmel_hlcdc_dc_drm_resume(struct device *dev)
919{
920 struct drm_device *drm_dev = dev_get_drvdata(dev);
921 struct atmel_hlcdc_dc *dc = drm_dev->dev_private;
922
923 clk_prepare_enable(dc->hlcdc->periph_clk);
924 regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IER, dc->suspend.imr);
925
926 return drm_atomic_helper_resume(drm_dev, dc->suspend.state);
927}
928
929static DEFINE_SIMPLE_DEV_PM_OPS(atmel_hlcdc_dc_drm_pm_ops,
930 atmel_hlcdc_dc_drm_suspend,
931 atmel_hlcdc_dc_drm_resume);
932
933static const struct of_device_id atmel_hlcdc_dc_of_match[] = {
934 { .compatible = "atmel,hlcdc-display-controller" },
935 { },
936};
937
938static struct platform_driver atmel_hlcdc_dc_platform_driver = {
939 .probe = atmel_hlcdc_dc_drm_probe,
940 .remove = atmel_hlcdc_dc_drm_remove,
941 .shutdown = atmel_hlcdc_dc_drm_shutdown,
942 .driver = {
943 .name = "atmel-hlcdc-display-controller",
944 .pm = pm_sleep_ptr(&atmel_hlcdc_dc_drm_pm_ops),
945 .of_match_table = atmel_hlcdc_dc_of_match,
946 },
947};
948drm_module_platform_driver(atmel_hlcdc_dc_platform_driver);
949
950MODULE_AUTHOR("Jean-Jacques Hiblot <jjhiblot@traphandler.com>");
951MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>");
952MODULE_DESCRIPTION("Atmel HLCDC Display Controller DRM Driver");
953MODULE_LICENSE("GPL");
954MODULE_ALIAS("platform:atmel-hlcdc-dc");