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1/*
2 * Copyright (C) 2002 MontaVista Software Inc.
3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10#ifndef _ASM_FPU_H
11#define _ASM_FPU_H
12
13#include <linux/sched.h>
14#include <linux/thread_info.h>
15#include <linux/bitops.h>
16
17#include <asm/mipsregs.h>
18#include <asm/cpu.h>
19#include <asm/cpu-features.h>
20#include <asm/fpu_emulator.h>
21#include <asm/hazards.h>
22#include <asm/processor.h>
23#include <asm/current.h>
24#include <asm/msa.h>
25
26#ifdef CONFIG_MIPS_MT_FPAFF
27#include <asm/mips_mt.h>
28#endif
29
30struct sigcontext;
31struct sigcontext32;
32
33extern void _init_fpu(unsigned int);
34extern void _save_fp(struct task_struct *);
35extern void _restore_fp(struct task_struct *);
36
37/*
38 * This enum specifies a mode in which we want the FPU to operate, for cores
39 * which implement the Status.FR bit. Note that the bottom bit of the value
40 * purposefully matches the desired value of the Status.FR bit.
41 */
42enum fpu_mode {
43 FPU_32BIT = 0, /* FR = 0 */
44 FPU_64BIT, /* FR = 1, FRE = 0 */
45 FPU_AS_IS,
46 FPU_HYBRID, /* FR = 1, FRE = 1 */
47
48#define FPU_FR_MASK 0x1
49};
50
51#define __disable_fpu() \
52do { \
53 clear_c0_status(ST0_CU1); \
54 disable_fpu_hazard(); \
55} while (0)
56
57static inline int __enable_fpu(enum fpu_mode mode)
58{
59 int fr;
60
61 switch (mode) {
62 case FPU_AS_IS:
63 /* just enable the FPU in its current mode */
64 set_c0_status(ST0_CU1);
65 enable_fpu_hazard();
66 return 0;
67
68 case FPU_HYBRID:
69 if (!cpu_has_fre)
70 return SIGFPE;
71
72 /* set FRE */
73 set_c0_config5(MIPS_CONF5_FRE);
74 goto fr_common;
75
76 case FPU_64BIT:
77#if !(defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) \
78 || defined(CONFIG_64BIT))
79 /* we only have a 32-bit FPU */
80 return SIGFPE;
81#endif
82 /* fall through */
83 case FPU_32BIT:
84 if (cpu_has_fre) {
85 /* clear FRE */
86 clear_c0_config5(MIPS_CONF5_FRE);
87 }
88fr_common:
89 /* set CU1 & change FR appropriately */
90 fr = (int)mode & FPU_FR_MASK;
91 change_c0_status(ST0_CU1 | ST0_FR, ST0_CU1 | (fr ? ST0_FR : 0));
92 enable_fpu_hazard();
93
94 /* check FR has the desired value */
95 if (!!(read_c0_status() & ST0_FR) == !!fr)
96 return 0;
97
98 /* unsupported FR value */
99 __disable_fpu();
100 return SIGFPE;
101
102 default:
103 BUG();
104 }
105
106 return SIGFPE;
107}
108
109#define clear_fpu_owner() clear_thread_flag(TIF_USEDFPU)
110
111static inline int __is_fpu_owner(void)
112{
113 return test_thread_flag(TIF_USEDFPU);
114}
115
116static inline int is_fpu_owner(void)
117{
118 return cpu_has_fpu && __is_fpu_owner();
119}
120
121static inline int __own_fpu(void)
122{
123 enum fpu_mode mode;
124 int ret;
125
126 if (test_thread_flag(TIF_HYBRID_FPREGS))
127 mode = FPU_HYBRID;
128 else
129 mode = !test_thread_flag(TIF_32BIT_FPREGS);
130
131 ret = __enable_fpu(mode);
132 if (ret)
133 return ret;
134
135 KSTK_STATUS(current) |= ST0_CU1;
136 if (mode == FPU_64BIT || mode == FPU_HYBRID)
137 KSTK_STATUS(current) |= ST0_FR;
138 else /* mode == FPU_32BIT */
139 KSTK_STATUS(current) &= ~ST0_FR;
140
141 set_thread_flag(TIF_USEDFPU);
142 return 0;
143}
144
145static inline int own_fpu_inatomic(int restore)
146{
147 int ret = 0;
148
149 if (cpu_has_fpu && !__is_fpu_owner()) {
150 ret = __own_fpu();
151 if (restore && !ret)
152 _restore_fp(current);
153 }
154 return ret;
155}
156
157static inline int own_fpu(int restore)
158{
159 int ret;
160
161 preempt_disable();
162 ret = own_fpu_inatomic(restore);
163 preempt_enable();
164 return ret;
165}
166
167static inline void lose_fpu_inatomic(int save, struct task_struct *tsk)
168{
169 if (is_msa_enabled()) {
170 if (save) {
171 save_msa(tsk);
172 tsk->thread.fpu.fcr31 =
173 read_32bit_cp1_register(CP1_STATUS);
174 }
175 disable_msa();
176 clear_tsk_thread_flag(tsk, TIF_USEDMSA);
177 __disable_fpu();
178 } else if (is_fpu_owner()) {
179 if (save)
180 _save_fp(tsk);
181 __disable_fpu();
182 } else {
183 /* FPU should not have been left enabled with no owner */
184 WARN(read_c0_status() & ST0_CU1,
185 "Orphaned FPU left enabled");
186 }
187 KSTK_STATUS(tsk) &= ~ST0_CU1;
188 clear_tsk_thread_flag(tsk, TIF_USEDFPU);
189}
190
191static inline void lose_fpu(int save)
192{
193 preempt_disable();
194 lose_fpu_inatomic(save, current);
195 preempt_enable();
196}
197
198static inline int init_fpu(void)
199{
200 unsigned int fcr31 = current->thread.fpu.fcr31;
201 int ret = 0;
202
203 if (cpu_has_fpu) {
204 unsigned int config5;
205
206 ret = __own_fpu();
207 if (ret)
208 return ret;
209
210 if (!cpu_has_fre) {
211 _init_fpu(fcr31);
212
213 return 0;
214 }
215
216 /*
217 * Ensure FRE is clear whilst running _init_fpu, since
218 * single precision FP instructions are used. If FRE
219 * was set then we'll just end up initialising all 32
220 * 64b registers.
221 */
222 config5 = clear_c0_config5(MIPS_CONF5_FRE);
223 enable_fpu_hazard();
224
225 _init_fpu(fcr31);
226
227 /* Restore FRE */
228 write_c0_config5(config5);
229 enable_fpu_hazard();
230 } else
231 fpu_emulator_init_fpu();
232
233 return ret;
234}
235
236static inline void save_fp(struct task_struct *tsk)
237{
238 if (cpu_has_fpu)
239 _save_fp(tsk);
240}
241
242static inline void restore_fp(struct task_struct *tsk)
243{
244 if (cpu_has_fpu)
245 _restore_fp(tsk);
246}
247
248static inline union fpureg *get_fpu_regs(struct task_struct *tsk)
249{
250 if (tsk == current) {
251 preempt_disable();
252 if (is_fpu_owner())
253 _save_fp(current);
254 preempt_enable();
255 }
256
257 return tsk->thread.fpu.fpr;
258}
259
260#endif /* _ASM_FPU_H */
1/*
2 * Copyright (C) 2002 MontaVista Software Inc.
3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10#ifndef _ASM_FPU_H
11#define _ASM_FPU_H
12
13#include <linux/sched.h>
14#include <linux/sched/task_stack.h>
15#include <linux/ptrace.h>
16#include <linux/thread_info.h>
17#include <linux/bitops.h>
18
19#include <asm/mipsregs.h>
20#include <asm/cpu.h>
21#include <asm/cpu-features.h>
22#include <asm/fpu_emulator.h>
23#include <asm/hazards.h>
24#include <asm/ptrace.h>
25#include <asm/processor.h>
26#include <asm/current.h>
27#include <asm/msa.h>
28
29#ifdef CONFIG_MIPS_MT_FPAFF
30#include <asm/mips_mt.h>
31#endif
32
33struct sigcontext;
34struct sigcontext32;
35
36extern void _init_fpu(unsigned int);
37extern void _save_fp(struct task_struct *);
38extern void _restore_fp(struct task_struct *);
39
40/*
41 * This enum specifies a mode in which we want the FPU to operate, for cores
42 * which implement the Status.FR bit. Note that the bottom bit of the value
43 * purposefully matches the desired value of the Status.FR bit.
44 */
45enum fpu_mode {
46 FPU_32BIT = 0, /* FR = 0 */
47 FPU_64BIT, /* FR = 1, FRE = 0 */
48 FPU_AS_IS,
49 FPU_HYBRID, /* FR = 1, FRE = 1 */
50
51#define FPU_FR_MASK 0x1
52};
53
54#define __disable_fpu() \
55do { \
56 clear_c0_status(ST0_CU1); \
57 disable_fpu_hazard(); \
58} while (0)
59
60static inline int __enable_fpu(enum fpu_mode mode)
61{
62 int fr;
63
64 switch (mode) {
65 case FPU_AS_IS:
66 /* just enable the FPU in its current mode */
67 set_c0_status(ST0_CU1);
68 enable_fpu_hazard();
69 return 0;
70
71 case FPU_HYBRID:
72 if (!cpu_has_fre)
73 return SIGFPE;
74
75 /* set FRE */
76 set_c0_config5(MIPS_CONF5_FRE);
77 goto fr_common;
78
79 case FPU_64BIT:
80#if !(defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) \
81 || defined(CONFIG_64BIT))
82 /* we only have a 32-bit FPU */
83 return SIGFPE;
84#endif
85 /* fall through */
86 case FPU_32BIT:
87 if (cpu_has_fre) {
88 /* clear FRE */
89 clear_c0_config5(MIPS_CONF5_FRE);
90 }
91fr_common:
92 /* set CU1 & change FR appropriately */
93 fr = (int)mode & FPU_FR_MASK;
94 change_c0_status(ST0_CU1 | ST0_FR, ST0_CU1 | (fr ? ST0_FR : 0));
95 enable_fpu_hazard();
96
97 /* check FR has the desired value */
98 if (!!(read_c0_status() & ST0_FR) == !!fr)
99 return 0;
100
101 /* unsupported FR value */
102 __disable_fpu();
103 return SIGFPE;
104
105 default:
106 BUG();
107 }
108
109 return SIGFPE;
110}
111
112#define clear_fpu_owner() clear_thread_flag(TIF_USEDFPU)
113
114static inline int __is_fpu_owner(void)
115{
116 return test_thread_flag(TIF_USEDFPU);
117}
118
119static inline int is_fpu_owner(void)
120{
121 return cpu_has_fpu && __is_fpu_owner();
122}
123
124static inline int __own_fpu(void)
125{
126 enum fpu_mode mode;
127 int ret;
128
129 if (test_thread_flag(TIF_HYBRID_FPREGS))
130 mode = FPU_HYBRID;
131 else
132 mode = !test_thread_flag(TIF_32BIT_FPREGS);
133
134 ret = __enable_fpu(mode);
135 if (ret)
136 return ret;
137
138 KSTK_STATUS(current) |= ST0_CU1;
139 if (mode == FPU_64BIT || mode == FPU_HYBRID)
140 KSTK_STATUS(current) |= ST0_FR;
141 else /* mode == FPU_32BIT */
142 KSTK_STATUS(current) &= ~ST0_FR;
143
144 set_thread_flag(TIF_USEDFPU);
145 return 0;
146}
147
148static inline int own_fpu_inatomic(int restore)
149{
150 int ret = 0;
151
152 if (cpu_has_fpu && !__is_fpu_owner()) {
153 ret = __own_fpu();
154 if (restore && !ret)
155 _restore_fp(current);
156 }
157 return ret;
158}
159
160static inline int own_fpu(int restore)
161{
162 int ret;
163
164 preempt_disable();
165 ret = own_fpu_inatomic(restore);
166 preempt_enable();
167 return ret;
168}
169
170static inline void lose_fpu_inatomic(int save, struct task_struct *tsk)
171{
172 if (is_msa_enabled()) {
173 if (save) {
174 save_msa(tsk);
175 tsk->thread.fpu.fcr31 =
176 read_32bit_cp1_register(CP1_STATUS);
177 }
178 disable_msa();
179 clear_tsk_thread_flag(tsk, TIF_USEDMSA);
180 __disable_fpu();
181 } else if (is_fpu_owner()) {
182 if (save)
183 _save_fp(tsk);
184 __disable_fpu();
185 } else {
186 /* FPU should not have been left enabled with no owner */
187 WARN(read_c0_status() & ST0_CU1,
188 "Orphaned FPU left enabled");
189 }
190 KSTK_STATUS(tsk) &= ~ST0_CU1;
191 clear_tsk_thread_flag(tsk, TIF_USEDFPU);
192}
193
194static inline void lose_fpu(int save)
195{
196 preempt_disable();
197 lose_fpu_inatomic(save, current);
198 preempt_enable();
199}
200
201static inline int init_fpu(void)
202{
203 unsigned int fcr31 = current->thread.fpu.fcr31;
204 int ret = 0;
205
206 if (cpu_has_fpu) {
207 unsigned int config5;
208
209 ret = __own_fpu();
210 if (ret)
211 return ret;
212
213 if (!cpu_has_fre) {
214 _init_fpu(fcr31);
215
216 return 0;
217 }
218
219 /*
220 * Ensure FRE is clear whilst running _init_fpu, since
221 * single precision FP instructions are used. If FRE
222 * was set then we'll just end up initialising all 32
223 * 64b registers.
224 */
225 config5 = clear_c0_config5(MIPS_CONF5_FRE);
226 enable_fpu_hazard();
227
228 _init_fpu(fcr31);
229
230 /* Restore FRE */
231 write_c0_config5(config5);
232 enable_fpu_hazard();
233 } else
234 fpu_emulator_init_fpu();
235
236 return ret;
237}
238
239static inline void save_fp(struct task_struct *tsk)
240{
241 if (cpu_has_fpu)
242 _save_fp(tsk);
243}
244
245static inline void restore_fp(struct task_struct *tsk)
246{
247 if (cpu_has_fpu)
248 _restore_fp(tsk);
249}
250
251static inline union fpureg *get_fpu_regs(struct task_struct *tsk)
252{
253 if (tsk == current) {
254 preempt_disable();
255 if (is_fpu_owner())
256 _save_fp(current);
257 preempt_enable();
258 }
259
260 return tsk->thread.fpu.fpr;
261}
262
263#endif /* _ASM_FPU_H */