Loading...
1/*
2 * Copyright (C) 2002 MontaVista Software Inc.
3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10#ifndef _ASM_FPU_H
11#define _ASM_FPU_H
12
13#include <linux/sched.h>
14#include <linux/thread_info.h>
15#include <linux/bitops.h>
16
17#include <asm/mipsregs.h>
18#include <asm/cpu.h>
19#include <asm/cpu-features.h>
20#include <asm/fpu_emulator.h>
21#include <asm/hazards.h>
22#include <asm/processor.h>
23#include <asm/current.h>
24#include <asm/msa.h>
25
26#ifdef CONFIG_MIPS_MT_FPAFF
27#include <asm/mips_mt.h>
28#endif
29
30struct sigcontext;
31struct sigcontext32;
32
33extern void _init_fpu(unsigned int);
34extern void _save_fp(struct task_struct *);
35extern void _restore_fp(struct task_struct *);
36
37/*
38 * This enum specifies a mode in which we want the FPU to operate, for cores
39 * which implement the Status.FR bit. Note that the bottom bit of the value
40 * purposefully matches the desired value of the Status.FR bit.
41 */
42enum fpu_mode {
43 FPU_32BIT = 0, /* FR = 0 */
44 FPU_64BIT, /* FR = 1, FRE = 0 */
45 FPU_AS_IS,
46 FPU_HYBRID, /* FR = 1, FRE = 1 */
47
48#define FPU_FR_MASK 0x1
49};
50
51#define __disable_fpu() \
52do { \
53 clear_c0_status(ST0_CU1); \
54 disable_fpu_hazard(); \
55} while (0)
56
57static inline int __enable_fpu(enum fpu_mode mode)
58{
59 int fr;
60
61 switch (mode) {
62 case FPU_AS_IS:
63 /* just enable the FPU in its current mode */
64 set_c0_status(ST0_CU1);
65 enable_fpu_hazard();
66 return 0;
67
68 case FPU_HYBRID:
69 if (!cpu_has_fre)
70 return SIGFPE;
71
72 /* set FRE */
73 set_c0_config5(MIPS_CONF5_FRE);
74 goto fr_common;
75
76 case FPU_64BIT:
77#if !(defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) \
78 || defined(CONFIG_64BIT))
79 /* we only have a 32-bit FPU */
80 return SIGFPE;
81#endif
82 /* fall through */
83 case FPU_32BIT:
84 if (cpu_has_fre) {
85 /* clear FRE */
86 clear_c0_config5(MIPS_CONF5_FRE);
87 }
88fr_common:
89 /* set CU1 & change FR appropriately */
90 fr = (int)mode & FPU_FR_MASK;
91 change_c0_status(ST0_CU1 | ST0_FR, ST0_CU1 | (fr ? ST0_FR : 0));
92 enable_fpu_hazard();
93
94 /* check FR has the desired value */
95 if (!!(read_c0_status() & ST0_FR) == !!fr)
96 return 0;
97
98 /* unsupported FR value */
99 __disable_fpu();
100 return SIGFPE;
101
102 default:
103 BUG();
104 }
105
106 return SIGFPE;
107}
108
109#define clear_fpu_owner() clear_thread_flag(TIF_USEDFPU)
110
111static inline int __is_fpu_owner(void)
112{
113 return test_thread_flag(TIF_USEDFPU);
114}
115
116static inline int is_fpu_owner(void)
117{
118 return cpu_has_fpu && __is_fpu_owner();
119}
120
121static inline int __own_fpu(void)
122{
123 enum fpu_mode mode;
124 int ret;
125
126 if (test_thread_flag(TIF_HYBRID_FPREGS))
127 mode = FPU_HYBRID;
128 else
129 mode = !test_thread_flag(TIF_32BIT_FPREGS);
130
131 ret = __enable_fpu(mode);
132 if (ret)
133 return ret;
134
135 KSTK_STATUS(current) |= ST0_CU1;
136 if (mode == FPU_64BIT || mode == FPU_HYBRID)
137 KSTK_STATUS(current) |= ST0_FR;
138 else /* mode == FPU_32BIT */
139 KSTK_STATUS(current) &= ~ST0_FR;
140
141 set_thread_flag(TIF_USEDFPU);
142 return 0;
143}
144
145static inline int own_fpu_inatomic(int restore)
146{
147 int ret = 0;
148
149 if (cpu_has_fpu && !__is_fpu_owner()) {
150 ret = __own_fpu();
151 if (restore && !ret)
152 _restore_fp(current);
153 }
154 return ret;
155}
156
157static inline int own_fpu(int restore)
158{
159 int ret;
160
161 preempt_disable();
162 ret = own_fpu_inatomic(restore);
163 preempt_enable();
164 return ret;
165}
166
167static inline void lose_fpu_inatomic(int save, struct task_struct *tsk)
168{
169 if (is_msa_enabled()) {
170 if (save) {
171 save_msa(tsk);
172 tsk->thread.fpu.fcr31 =
173 read_32bit_cp1_register(CP1_STATUS);
174 }
175 disable_msa();
176 clear_tsk_thread_flag(tsk, TIF_USEDMSA);
177 __disable_fpu();
178 } else if (is_fpu_owner()) {
179 if (save)
180 _save_fp(tsk);
181 __disable_fpu();
182 } else {
183 /* FPU should not have been left enabled with no owner */
184 WARN(read_c0_status() & ST0_CU1,
185 "Orphaned FPU left enabled");
186 }
187 KSTK_STATUS(tsk) &= ~ST0_CU1;
188 clear_tsk_thread_flag(tsk, TIF_USEDFPU);
189}
190
191static inline void lose_fpu(int save)
192{
193 preempt_disable();
194 lose_fpu_inatomic(save, current);
195 preempt_enable();
196}
197
198static inline int init_fpu(void)
199{
200 unsigned int fcr31 = current->thread.fpu.fcr31;
201 int ret = 0;
202
203 if (cpu_has_fpu) {
204 unsigned int config5;
205
206 ret = __own_fpu();
207 if (ret)
208 return ret;
209
210 if (!cpu_has_fre) {
211 _init_fpu(fcr31);
212
213 return 0;
214 }
215
216 /*
217 * Ensure FRE is clear whilst running _init_fpu, since
218 * single precision FP instructions are used. If FRE
219 * was set then we'll just end up initialising all 32
220 * 64b registers.
221 */
222 config5 = clear_c0_config5(MIPS_CONF5_FRE);
223 enable_fpu_hazard();
224
225 _init_fpu(fcr31);
226
227 /* Restore FRE */
228 write_c0_config5(config5);
229 enable_fpu_hazard();
230 } else
231 fpu_emulator_init_fpu();
232
233 return ret;
234}
235
236static inline void save_fp(struct task_struct *tsk)
237{
238 if (cpu_has_fpu)
239 _save_fp(tsk);
240}
241
242static inline void restore_fp(struct task_struct *tsk)
243{
244 if (cpu_has_fpu)
245 _restore_fp(tsk);
246}
247
248static inline union fpureg *get_fpu_regs(struct task_struct *tsk)
249{
250 if (tsk == current) {
251 preempt_disable();
252 if (is_fpu_owner())
253 _save_fp(current);
254 preempt_enable();
255 }
256
257 return tsk->thread.fpu.fpr;
258}
259
260#endif /* _ASM_FPU_H */
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Copyright (C) 2002 MontaVista Software Inc.
4 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
5 */
6#ifndef _ASM_FPU_H
7#define _ASM_FPU_H
8
9#include <linux/sched.h>
10#include <linux/sched/task_stack.h>
11#include <linux/ptrace.h>
12#include <linux/thread_info.h>
13#include <linux/bitops.h>
14
15#include <asm/mipsregs.h>
16#include <asm/cpu.h>
17#include <asm/cpu-features.h>
18#include <asm/fpu_emulator.h>
19#include <asm/hazards.h>
20#include <asm/ptrace.h>
21#include <asm/processor.h>
22#include <asm/current.h>
23#include <asm/msa.h>
24
25#ifdef CONFIG_MIPS_MT_FPAFF
26#include <asm/mips_mt.h>
27#endif
28
29/*
30 * This enum specifies a mode in which we want the FPU to operate, for cores
31 * which implement the Status.FR bit. Note that the bottom bit of the value
32 * purposefully matches the desired value of the Status.FR bit.
33 */
34enum fpu_mode {
35 FPU_32BIT = 0, /* FR = 0 */
36 FPU_64BIT, /* FR = 1, FRE = 0 */
37 FPU_AS_IS,
38 FPU_HYBRID, /* FR = 1, FRE = 1 */
39
40#define FPU_FR_MASK 0x1
41};
42
43#ifdef CONFIG_MIPS_FP_SUPPORT
44
45extern void _save_fp(struct task_struct *);
46extern void _restore_fp(struct task_struct *);
47
48#define __disable_fpu() \
49do { \
50 clear_c0_status(ST0_CU1); \
51 disable_fpu_hazard(); \
52} while (0)
53
54static inline int __enable_fpu(enum fpu_mode mode)
55{
56 int fr;
57
58 switch (mode) {
59 case FPU_AS_IS:
60 /* just enable the FPU in its current mode */
61 set_c0_status(ST0_CU1);
62 enable_fpu_hazard();
63 return 0;
64
65 case FPU_HYBRID:
66 if (!cpu_has_fre)
67 return SIGFPE;
68
69 /* set FRE */
70 set_c0_config5(MIPS_CONF5_FRE);
71 goto fr_common;
72
73 case FPU_64BIT:
74#if !(defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5) || \
75 defined(CONFIG_CPU_MIPSR6) || defined(CONFIG_64BIT))
76 /* we only have a 32-bit FPU */
77 return SIGFPE;
78#endif
79 /* fallthrough */
80 case FPU_32BIT:
81 if (cpu_has_fre) {
82 /* clear FRE */
83 clear_c0_config5(MIPS_CONF5_FRE);
84 }
85fr_common:
86 /* set CU1 & change FR appropriately */
87 fr = (int)mode & FPU_FR_MASK;
88 change_c0_status(ST0_CU1 | ST0_FR, ST0_CU1 | (fr ? ST0_FR : 0));
89 enable_fpu_hazard();
90
91 /* check FR has the desired value */
92 if (!!(read_c0_status() & ST0_FR) == !!fr)
93 return 0;
94
95 /* unsupported FR value */
96 __disable_fpu();
97 return SIGFPE;
98
99 default:
100 BUG();
101 }
102
103 return SIGFPE;
104}
105
106#define clear_fpu_owner() clear_thread_flag(TIF_USEDFPU)
107
108static inline int __is_fpu_owner(void)
109{
110 return test_thread_flag(TIF_USEDFPU);
111}
112
113static inline int is_fpu_owner(void)
114{
115 return cpu_has_fpu && __is_fpu_owner();
116}
117
118static inline int __own_fpu(void)
119{
120 enum fpu_mode mode;
121 int ret;
122
123 if (test_thread_flag(TIF_HYBRID_FPREGS))
124 mode = FPU_HYBRID;
125 else
126 mode = !test_thread_flag(TIF_32BIT_FPREGS);
127
128 ret = __enable_fpu(mode);
129 if (ret)
130 return ret;
131
132 if (current->thread.fpu.fcr31 & FPU_CSR_NAN2008) {
133 if (!cpu_has_nan_2008) {
134 ret = SIGFPE;
135 goto failed;
136 }
137 } else {
138 if (!cpu_has_nan_legacy) {
139 ret = SIGFPE;
140 goto failed;
141 }
142 }
143
144 KSTK_STATUS(current) |= ST0_CU1;
145 if (mode == FPU_64BIT || mode == FPU_HYBRID)
146 KSTK_STATUS(current) |= ST0_FR;
147 else /* mode == FPU_32BIT */
148 KSTK_STATUS(current) &= ~ST0_FR;
149
150 set_thread_flag(TIF_USEDFPU);
151 return 0;
152failed:
153 __disable_fpu();
154 return ret;
155}
156
157static inline int own_fpu_inatomic(int restore)
158{
159 int ret = 0;
160
161 if (cpu_has_fpu && !__is_fpu_owner()) {
162 ret = __own_fpu();
163 if (restore && !ret)
164 _restore_fp(current);
165 }
166 return ret;
167}
168
169static inline int own_fpu(int restore)
170{
171 int ret;
172
173 preempt_disable();
174 ret = own_fpu_inatomic(restore);
175 preempt_enable();
176 return ret;
177}
178
179static inline void lose_fpu_inatomic(int save, struct task_struct *tsk)
180{
181 if (is_msa_enabled()) {
182 if (save) {
183 save_msa(tsk);
184 tsk->thread.fpu.fcr31 =
185 read_32bit_cp1_register(CP1_STATUS);
186 }
187 disable_msa();
188 clear_tsk_thread_flag(tsk, TIF_USEDMSA);
189 __disable_fpu();
190 } else if (is_fpu_owner()) {
191 if (save)
192 _save_fp(tsk);
193 __disable_fpu();
194 } else {
195 /* FPU should not have been left enabled with no owner */
196 WARN(read_c0_status() & ST0_CU1,
197 "Orphaned FPU left enabled");
198 }
199 KSTK_STATUS(tsk) &= ~ST0_CU1;
200 clear_tsk_thread_flag(tsk, TIF_USEDFPU);
201}
202
203static inline void lose_fpu(int save)
204{
205 preempt_disable();
206 lose_fpu_inatomic(save, current);
207 preempt_enable();
208}
209
210/**
211 * init_fp_ctx() - Initialize task FP context
212 * @target: The task whose FP context should be initialized.
213 *
214 * Initializes the FP context of the target task to sane default values if that
215 * target task does not already have valid FP context. Once the context has
216 * been initialized, the task will be marked as having used FP & thus having
217 * valid FP context.
218 *
219 * Returns: true if context is initialized, else false.
220 */
221static inline bool init_fp_ctx(struct task_struct *target)
222{
223 /* If FP has been used then the target already has context */
224 if (tsk_used_math(target))
225 return false;
226
227 /* Begin with data registers set to all 1s... */
228 memset(&target->thread.fpu.fpr, ~0, sizeof(target->thread.fpu.fpr));
229
230 /* FCSR has been preset by `mips_set_personality_nan'. */
231
232 /*
233 * Record that the target has "used" math, such that the context
234 * just initialised, and any modifications made by the caller,
235 * aren't discarded.
236 */
237 set_stopped_child_used_math(target);
238
239 return true;
240}
241
242static inline void save_fp(struct task_struct *tsk)
243{
244 if (cpu_has_fpu)
245 _save_fp(tsk);
246}
247
248static inline void restore_fp(struct task_struct *tsk)
249{
250 if (cpu_has_fpu)
251 _restore_fp(tsk);
252}
253
254static inline union fpureg *get_fpu_regs(struct task_struct *tsk)
255{
256 if (tsk == current) {
257 preempt_disable();
258 if (is_fpu_owner())
259 _save_fp(current);
260 preempt_enable();
261 }
262
263 return tsk->thread.fpu.fpr;
264}
265
266#else /* !CONFIG_MIPS_FP_SUPPORT */
267
268/*
269 * When FP support is disabled we provide only a minimal set of stub functions
270 * to avoid callers needing to care too much about CONFIG_MIPS_FP_SUPPORT.
271 */
272
273static inline int __enable_fpu(enum fpu_mode mode)
274{
275 return SIGILL;
276}
277
278static inline void __disable_fpu(void)
279{
280 /* no-op */
281}
282
283
284static inline int is_fpu_owner(void)
285{
286 return 0;
287}
288
289static inline void clear_fpu_owner(void)
290{
291 /* no-op */
292}
293
294static inline int own_fpu_inatomic(int restore)
295{
296 return SIGILL;
297}
298
299static inline int own_fpu(int restore)
300{
301 return SIGILL;
302}
303
304static inline void lose_fpu_inatomic(int save, struct task_struct *tsk)
305{
306 /* no-op */
307}
308
309static inline void lose_fpu(int save)
310{
311 /* no-op */
312}
313
314static inline bool init_fp_ctx(struct task_struct *target)
315{
316 return false;
317}
318
319/*
320 * The following functions should only be called in paths where we know that FP
321 * support is enabled, typically a path where own_fpu() or __enable_fpu() have
322 * returned successfully. When CONFIG_MIPS_FP_SUPPORT=n it is known at compile
323 * time that this should never happen, so calls to these functions should be
324 * optimized away & never actually be emitted.
325 */
326
327extern void save_fp(struct task_struct *tsk)
328 __compiletime_error("save_fp() should not be called when CONFIG_MIPS_FP_SUPPORT=n");
329
330extern void _save_fp(struct task_struct *)
331 __compiletime_error("_save_fp() should not be called when CONFIG_MIPS_FP_SUPPORT=n");
332
333extern void restore_fp(struct task_struct *tsk)
334 __compiletime_error("restore_fp() should not be called when CONFIG_MIPS_FP_SUPPORT=n");
335
336extern void _restore_fp(struct task_struct *)
337 __compiletime_error("_restore_fp() should not be called when CONFIG_MIPS_FP_SUPPORT=n");
338
339extern union fpureg *get_fpu_regs(struct task_struct *tsk)
340 __compiletime_error("get_fpu_regs() should not be called when CONFIG_MIPS_FP_SUPPORT=n");
341
342#endif /* !CONFIG_MIPS_FP_SUPPORT */
343#endif /* _ASM_FPU_H */