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1/*
2 * linux/arch/arm/kernel/entry-armv.S
3 *
4 * Copyright (C) 1996,1997,1998 Russell King.
5 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk)
6 * nommu support by Hyok S. Choi (hyok.choi@samsung.com)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Low-level vector interface routines
13 *
14 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction
15 * that causes it to save wrong values... Be aware!
16 */
17
18#include <linux/init.h>
19
20#include <asm/assembler.h>
21#include <asm/memory.h>
22#include <asm/glue-df.h>
23#include <asm/glue-pf.h>
24#include <asm/vfpmacros.h>
25#ifndef CONFIG_MULTI_IRQ_HANDLER
26#include <mach/entry-macro.S>
27#endif
28#include <asm/thread_notify.h>
29#include <asm/unwind.h>
30#include <asm/unistd.h>
31#include <asm/tls.h>
32#include <asm/system_info.h>
33
34#include "entry-header.S"
35#include <asm/entry-macro-multi.S>
36#include <asm/probes.h>
37
38/*
39 * Interrupt handling.
40 */
41 .macro irq_handler
42#ifdef CONFIG_MULTI_IRQ_HANDLER
43 ldr r1, =handle_arch_irq
44 mov r0, sp
45 badr lr, 9997f
46 ldr pc, [r1]
47#else
48 arch_irq_handler_default
49#endif
509997:
51 .endm
52
53 .macro pabt_helper
54 @ PABORT handler takes pt_regs in r2, fault address in r4 and psr in r5
55#ifdef MULTI_PABORT
56 ldr ip, .LCprocfns
57 mov lr, pc
58 ldr pc, [ip, #PROCESSOR_PABT_FUNC]
59#else
60 bl CPU_PABORT_HANDLER
61#endif
62 .endm
63
64 .macro dabt_helper
65
66 @
67 @ Call the processor-specific abort handler:
68 @
69 @ r2 - pt_regs
70 @ r4 - aborted context pc
71 @ r5 - aborted context psr
72 @
73 @ The abort handler must return the aborted address in r0, and
74 @ the fault status register in r1. r9 must be preserved.
75 @
76#ifdef MULTI_DABORT
77 ldr ip, .LCprocfns
78 mov lr, pc
79 ldr pc, [ip, #PROCESSOR_DABT_FUNC]
80#else
81 bl CPU_DABORT_HANDLER
82#endif
83 .endm
84
85#ifdef CONFIG_KPROBES
86 .section .kprobes.text,"ax",%progbits
87#else
88 .text
89#endif
90
91/*
92 * Invalid mode handlers
93 */
94 .macro inv_entry, reason
95 sub sp, sp, #S_FRAME_SIZE
96 ARM( stmib sp, {r1 - lr} )
97 THUMB( stmia sp, {r0 - r12} )
98 THUMB( str sp, [sp, #S_SP] )
99 THUMB( str lr, [sp, #S_LR] )
100 mov r1, #\reason
101 .endm
102
103__pabt_invalid:
104 inv_entry BAD_PREFETCH
105 b common_invalid
106ENDPROC(__pabt_invalid)
107
108__dabt_invalid:
109 inv_entry BAD_DATA
110 b common_invalid
111ENDPROC(__dabt_invalid)
112
113__irq_invalid:
114 inv_entry BAD_IRQ
115 b common_invalid
116ENDPROC(__irq_invalid)
117
118__und_invalid:
119 inv_entry BAD_UNDEFINSTR
120
121 @
122 @ XXX fall through to common_invalid
123 @
124
125@
126@ common_invalid - generic code for failed exception (re-entrant version of handlers)
127@
128common_invalid:
129 zero_fp
130
131 ldmia r0, {r4 - r6}
132 add r0, sp, #S_PC @ here for interlock avoidance
133 mov r7, #-1 @ "" "" "" ""
134 str r4, [sp] @ save preserved r0
135 stmia r0, {r5 - r7} @ lr_<exception>,
136 @ cpsr_<exception>, "old_r0"
137
138 mov r0, sp
139 b bad_mode
140ENDPROC(__und_invalid)
141
142/*
143 * SVC mode handlers
144 */
145
146#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
147#define SPFIX(code...) code
148#else
149#define SPFIX(code...)
150#endif
151
152 .macro svc_entry, stack_hole=0, trace=1, uaccess=1
153 UNWIND(.fnstart )
154 UNWIND(.save {r0 - pc} )
155 sub sp, sp, #(S_FRAME_SIZE + 8 + \stack_hole - 4)
156#ifdef CONFIG_THUMB2_KERNEL
157 SPFIX( str r0, [sp] ) @ temporarily saved
158 SPFIX( mov r0, sp )
159 SPFIX( tst r0, #4 ) @ test original stack alignment
160 SPFIX( ldr r0, [sp] ) @ restored
161#else
162 SPFIX( tst sp, #4 )
163#endif
164 SPFIX( subeq sp, sp, #4 )
165 stmia sp, {r1 - r12}
166
167 ldmia r0, {r3 - r5}
168 add r7, sp, #S_SP - 4 @ here for interlock avoidance
169 mov r6, #-1 @ "" "" "" ""
170 add r2, sp, #(S_FRAME_SIZE + 8 + \stack_hole - 4)
171 SPFIX( addeq r2, r2, #4 )
172 str r3, [sp, #-4]! @ save the "real" r0 copied
173 @ from the exception stack
174
175 mov r3, lr
176
177 @
178 @ We are now ready to fill in the remaining blanks on the stack:
179 @
180 @ r2 - sp_svc
181 @ r3 - lr_svc
182 @ r4 - lr_<exception>, already fixed up for correct return/restart
183 @ r5 - spsr_<exception>
184 @ r6 - orig_r0 (see pt_regs definition in ptrace.h)
185 @
186 stmia r7, {r2 - r6}
187
188 uaccess_save r0
189 .if \uaccess
190 uaccess_disable r0
191 .endif
192
193 .if \trace
194#ifdef CONFIG_TRACE_IRQFLAGS
195 bl trace_hardirqs_off
196#endif
197 .endif
198 .endm
199
200 .align 5
201__dabt_svc:
202 svc_entry uaccess=0
203 mov r2, sp
204 dabt_helper
205 THUMB( ldr r5, [sp, #S_PSR] ) @ potentially updated CPSR
206 svc_exit r5 @ return from exception
207 UNWIND(.fnend )
208ENDPROC(__dabt_svc)
209
210 .align 5
211__irq_svc:
212 svc_entry
213 irq_handler
214
215#ifdef CONFIG_PREEMPT
216 get_thread_info tsk
217 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
218 ldr r0, [tsk, #TI_FLAGS] @ get flags
219 teq r8, #0 @ if preempt count != 0
220 movne r0, #0 @ force flags to 0
221 tst r0, #_TIF_NEED_RESCHED
222 blne svc_preempt
223#endif
224
225 svc_exit r5, irq = 1 @ return from exception
226 UNWIND(.fnend )
227ENDPROC(__irq_svc)
228
229 .ltorg
230
231#ifdef CONFIG_PREEMPT
232svc_preempt:
233 mov r8, lr
2341: bl preempt_schedule_irq @ irq en/disable is done inside
235 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS
236 tst r0, #_TIF_NEED_RESCHED
237 reteq r8 @ go again
238 b 1b
239#endif
240
241__und_fault:
242 @ Correct the PC such that it is pointing at the instruction
243 @ which caused the fault. If the faulting instruction was ARM
244 @ the PC will be pointing at the next instruction, and have to
245 @ subtract 4. Otherwise, it is Thumb, and the PC will be
246 @ pointing at the second half of the Thumb instruction. We
247 @ have to subtract 2.
248 ldr r2, [r0, #S_PC]
249 sub r2, r2, r1
250 str r2, [r0, #S_PC]
251 b do_undefinstr
252ENDPROC(__und_fault)
253
254 .align 5
255__und_svc:
256#ifdef CONFIG_KPROBES
257 @ If a kprobe is about to simulate a "stmdb sp..." instruction,
258 @ it obviously needs free stack space which then will belong to
259 @ the saved context.
260 svc_entry MAX_STACK_SIZE
261#else
262 svc_entry
263#endif
264 @
265 @ call emulation code, which returns using r9 if it has emulated
266 @ the instruction, or the more conventional lr if we are to treat
267 @ this as a real undefined instruction
268 @
269 @ r0 - instruction
270 @
271#ifndef CONFIG_THUMB2_KERNEL
272 ldr r0, [r4, #-4]
273#else
274 mov r1, #2
275 ldrh r0, [r4, #-2] @ Thumb instruction at LR - 2
276 cmp r0, #0xe800 @ 32-bit instruction if xx >= 0
277 blo __und_svc_fault
278 ldrh r9, [r4] @ bottom 16 bits
279 add r4, r4, #2
280 str r4, [sp, #S_PC]
281 orr r0, r9, r0, lsl #16
282#endif
283 badr r9, __und_svc_finish
284 mov r2, r4
285 bl call_fpe
286
287 mov r1, #4 @ PC correction to apply
288__und_svc_fault:
289 mov r0, sp @ struct pt_regs *regs
290 bl __und_fault
291
292__und_svc_finish:
293 ldr r5, [sp, #S_PSR] @ Get SVC cpsr
294 svc_exit r5 @ return from exception
295 UNWIND(.fnend )
296ENDPROC(__und_svc)
297
298 .align 5
299__pabt_svc:
300 svc_entry
301 mov r2, sp @ regs
302 pabt_helper
303 svc_exit r5 @ return from exception
304 UNWIND(.fnend )
305ENDPROC(__pabt_svc)
306
307 .align 5
308__fiq_svc:
309 svc_entry trace=0
310 mov r0, sp @ struct pt_regs *regs
311 bl handle_fiq_as_nmi
312 svc_exit_via_fiq
313 UNWIND(.fnend )
314ENDPROC(__fiq_svc)
315
316 .align 5
317.LCcralign:
318 .word cr_alignment
319#ifdef MULTI_DABORT
320.LCprocfns:
321 .word processor
322#endif
323.LCfp:
324 .word fp_enter
325
326/*
327 * Abort mode handlers
328 */
329
330@
331@ Taking a FIQ in abort mode is similar to taking a FIQ in SVC mode
332@ and reuses the same macros. However in abort mode we must also
333@ save/restore lr_abt and spsr_abt to make nested aborts safe.
334@
335 .align 5
336__fiq_abt:
337 svc_entry trace=0
338
339 ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
340 THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
341 THUMB( msr cpsr_c, r0 )
342 mov r1, lr @ Save lr_abt
343 mrs r2, spsr @ Save spsr_abt, abort is now safe
344 ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
345 THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
346 THUMB( msr cpsr_c, r0 )
347 stmfd sp!, {r1 - r2}
348
349 add r0, sp, #8 @ struct pt_regs *regs
350 bl handle_fiq_as_nmi
351
352 ldmfd sp!, {r1 - r2}
353 ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
354 THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
355 THUMB( msr cpsr_c, r0 )
356 mov lr, r1 @ Restore lr_abt, abort is unsafe
357 msr spsr_cxsf, r2 @ Restore spsr_abt
358 ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
359 THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
360 THUMB( msr cpsr_c, r0 )
361
362 svc_exit_via_fiq
363 UNWIND(.fnend )
364ENDPROC(__fiq_abt)
365
366/*
367 * User mode handlers
368 *
369 * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE
370 */
371
372#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7)
373#error "sizeof(struct pt_regs) must be a multiple of 8"
374#endif
375
376 .macro usr_entry, trace=1, uaccess=1
377 UNWIND(.fnstart )
378 UNWIND(.cantunwind ) @ don't unwind the user space
379 sub sp, sp, #S_FRAME_SIZE
380 ARM( stmib sp, {r1 - r12} )
381 THUMB( stmia sp, {r0 - r12} )
382
383 ATRAP( mrc p15, 0, r7, c1, c0, 0)
384 ATRAP( ldr r8, .LCcralign)
385
386 ldmia r0, {r3 - r5}
387 add r0, sp, #S_PC @ here for interlock avoidance
388 mov r6, #-1 @ "" "" "" ""
389
390 str r3, [sp] @ save the "real" r0 copied
391 @ from the exception stack
392
393 ATRAP( ldr r8, [r8, #0])
394
395 @
396 @ We are now ready to fill in the remaining blanks on the stack:
397 @
398 @ r4 - lr_<exception>, already fixed up for correct return/restart
399 @ r5 - spsr_<exception>
400 @ r6 - orig_r0 (see pt_regs definition in ptrace.h)
401 @
402 @ Also, separately save sp_usr and lr_usr
403 @
404 stmia r0, {r4 - r6}
405 ARM( stmdb r0, {sp, lr}^ )
406 THUMB( store_user_sp_lr r0, r1, S_SP - S_PC )
407
408 .if \uaccess
409 uaccess_disable ip
410 .endif
411
412 @ Enable the alignment trap while in kernel mode
413 ATRAP( teq r8, r7)
414 ATRAP( mcrne p15, 0, r8, c1, c0, 0)
415
416 @
417 @ Clear FP to mark the first stack frame
418 @
419 zero_fp
420
421 .if \trace
422#ifdef CONFIG_TRACE_IRQFLAGS
423 bl trace_hardirqs_off
424#endif
425 ct_user_exit save = 0
426 .endif
427 .endm
428
429 .macro kuser_cmpxchg_check
430#if !defined(CONFIG_CPU_32v6K) && defined(CONFIG_KUSER_HELPERS)
431#ifndef CONFIG_MMU
432#warning "NPTL on non MMU needs fixing"
433#else
434 @ Make sure our user space atomic helper is restarted
435 @ if it was interrupted in a critical region. Here we
436 @ perform a quick test inline since it should be false
437 @ 99.9999% of the time. The rest is done out of line.
438 cmp r4, #TASK_SIZE
439 blhs kuser_cmpxchg64_fixup
440#endif
441#endif
442 .endm
443
444 .align 5
445__dabt_usr:
446 usr_entry uaccess=0
447 kuser_cmpxchg_check
448 mov r2, sp
449 dabt_helper
450 b ret_from_exception
451 UNWIND(.fnend )
452ENDPROC(__dabt_usr)
453
454 .align 5
455__irq_usr:
456 usr_entry
457 kuser_cmpxchg_check
458 irq_handler
459 get_thread_info tsk
460 mov why, #0
461 b ret_to_user_from_irq
462 UNWIND(.fnend )
463ENDPROC(__irq_usr)
464
465 .ltorg
466
467 .align 5
468__und_usr:
469 usr_entry uaccess=0
470
471 mov r2, r4
472 mov r3, r5
473
474 @ r2 = regs->ARM_pc, which is either 2 or 4 bytes ahead of the
475 @ faulting instruction depending on Thumb mode.
476 @ r3 = regs->ARM_cpsr
477 @
478 @ The emulation code returns using r9 if it has emulated the
479 @ instruction, or the more conventional lr if we are to treat
480 @ this as a real undefined instruction
481 @
482 badr r9, ret_from_exception
483
484 @ IRQs must be enabled before attempting to read the instruction from
485 @ user space since that could cause a page/translation fault if the
486 @ page table was modified by another CPU.
487 enable_irq
488
489 tst r3, #PSR_T_BIT @ Thumb mode?
490 bne __und_usr_thumb
491 sub r4, r2, #4 @ ARM instr at LR - 4
4921: ldrt r0, [r4]
493 ARM_BE8(rev r0, r0) @ little endian instruction
494
495 uaccess_disable ip
496
497 @ r0 = 32-bit ARM instruction which caused the exception
498 @ r2 = PC value for the following instruction (:= regs->ARM_pc)
499 @ r4 = PC value for the faulting instruction
500 @ lr = 32-bit undefined instruction function
501 badr lr, __und_usr_fault_32
502 b call_fpe
503
504__und_usr_thumb:
505 @ Thumb instruction
506 sub r4, r2, #2 @ First half of thumb instr at LR - 2
507#if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7
508/*
509 * Thumb-2 instruction handling. Note that because pre-v6 and >= v6 platforms
510 * can never be supported in a single kernel, this code is not applicable at
511 * all when __LINUX_ARM_ARCH__ < 6. This allows simplifying assumptions to be
512 * made about .arch directives.
513 */
514#if __LINUX_ARM_ARCH__ < 7
515/* If the target CPU may not be Thumb-2-capable, a run-time check is needed: */
516#define NEED_CPU_ARCHITECTURE
517 ldr r5, .LCcpu_architecture
518 ldr r5, [r5]
519 cmp r5, #CPU_ARCH_ARMv7
520 blo __und_usr_fault_16 @ 16bit undefined instruction
521/*
522 * The following code won't get run unless the running CPU really is v7, so
523 * coding round the lack of ldrht on older arches is pointless. Temporarily
524 * override the assembler target arch with the minimum required instead:
525 */
526 .arch armv6t2
527#endif
5282: ldrht r5, [r4]
529ARM_BE8(rev16 r5, r5) @ little endian instruction
530 cmp r5, #0xe800 @ 32bit instruction if xx != 0
531 blo __und_usr_fault_16_pan @ 16bit undefined instruction
5323: ldrht r0, [r2]
533ARM_BE8(rev16 r0, r0) @ little endian instruction
534 uaccess_disable ip
535 add r2, r2, #2 @ r2 is PC + 2, make it PC + 4
536 str r2, [sp, #S_PC] @ it's a 2x16bit instr, update
537 orr r0, r0, r5, lsl #16
538 badr lr, __und_usr_fault_32
539 @ r0 = the two 16-bit Thumb instructions which caused the exception
540 @ r2 = PC value for the following Thumb instruction (:= regs->ARM_pc)
541 @ r4 = PC value for the first 16-bit Thumb instruction
542 @ lr = 32bit undefined instruction function
543
544#if __LINUX_ARM_ARCH__ < 7
545/* If the target arch was overridden, change it back: */
546#ifdef CONFIG_CPU_32v6K
547 .arch armv6k
548#else
549 .arch armv6
550#endif
551#endif /* __LINUX_ARM_ARCH__ < 7 */
552#else /* !(CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7) */
553 b __und_usr_fault_16
554#endif
555 UNWIND(.fnend)
556ENDPROC(__und_usr)
557
558/*
559 * The out of line fixup for the ldrt instructions above.
560 */
561 .pushsection .text.fixup, "ax"
562 .align 2
5634: str r4, [sp, #S_PC] @ retry current instruction
564 ret r9
565 .popsection
566 .pushsection __ex_table,"a"
567 .long 1b, 4b
568#if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7
569 .long 2b, 4b
570 .long 3b, 4b
571#endif
572 .popsection
573
574/*
575 * Check whether the instruction is a co-processor instruction.
576 * If yes, we need to call the relevant co-processor handler.
577 *
578 * Note that we don't do a full check here for the co-processor
579 * instructions; all instructions with bit 27 set are well
580 * defined. The only instructions that should fault are the
581 * co-processor instructions. However, we have to watch out
582 * for the ARM6/ARM7 SWI bug.
583 *
584 * NEON is a special case that has to be handled here. Not all
585 * NEON instructions are co-processor instructions, so we have
586 * to make a special case of checking for them. Plus, there's
587 * five groups of them, so we have a table of mask/opcode pairs
588 * to check against, and if any match then we branch off into the
589 * NEON handler code.
590 *
591 * Emulators may wish to make use of the following registers:
592 * r0 = instruction opcode (32-bit ARM or two 16-bit Thumb)
593 * r2 = PC value to resume execution after successful emulation
594 * r9 = normal "successful" return address
595 * r10 = this threads thread_info structure
596 * lr = unrecognised instruction return address
597 * IRQs enabled, FIQs enabled.
598 */
599 @
600 @ Fall-through from Thumb-2 __und_usr
601 @
602#ifdef CONFIG_NEON
603 get_thread_info r10 @ get current thread
604 adr r6, .LCneon_thumb_opcodes
605 b 2f
606#endif
607call_fpe:
608 get_thread_info r10 @ get current thread
609#ifdef CONFIG_NEON
610 adr r6, .LCneon_arm_opcodes
6112: ldr r5, [r6], #4 @ mask value
612 ldr r7, [r6], #4 @ opcode bits matching in mask
613 cmp r5, #0 @ end mask?
614 beq 1f
615 and r8, r0, r5
616 cmp r8, r7 @ NEON instruction?
617 bne 2b
618 mov r7, #1
619 strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used
620 strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used
621 b do_vfp @ let VFP handler handle this
6221:
623#endif
624 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
625 tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2
626 reteq lr
627 and r8, r0, #0x00000f00 @ mask out CP number
628 THUMB( lsr r8, r8, #8 )
629 mov r7, #1
630 add r6, r10, #TI_USED_CP
631 ARM( strb r7, [r6, r8, lsr #8] ) @ set appropriate used_cp[]
632 THUMB( strb r7, [r6, r8] ) @ set appropriate used_cp[]
633#ifdef CONFIG_IWMMXT
634 @ Test if we need to give access to iWMMXt coprocessors
635 ldr r5, [r10, #TI_FLAGS]
636 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only
637 movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1)
638 bcs iwmmxt_task_enable
639#endif
640 ARM( add pc, pc, r8, lsr #6 )
641 THUMB( lsl r8, r8, #2 )
642 THUMB( add pc, r8 )
643 nop
644
645 ret.w lr @ CP#0
646 W(b) do_fpe @ CP#1 (FPE)
647 W(b) do_fpe @ CP#2 (FPE)
648 ret.w lr @ CP#3
649#ifdef CONFIG_CRUNCH
650 b crunch_task_enable @ CP#4 (MaverickCrunch)
651 b crunch_task_enable @ CP#5 (MaverickCrunch)
652 b crunch_task_enable @ CP#6 (MaverickCrunch)
653#else
654 ret.w lr @ CP#4
655 ret.w lr @ CP#5
656 ret.w lr @ CP#6
657#endif
658 ret.w lr @ CP#7
659 ret.w lr @ CP#8
660 ret.w lr @ CP#9
661#ifdef CONFIG_VFP
662 W(b) do_vfp @ CP#10 (VFP)
663 W(b) do_vfp @ CP#11 (VFP)
664#else
665 ret.w lr @ CP#10 (VFP)
666 ret.w lr @ CP#11 (VFP)
667#endif
668 ret.w lr @ CP#12
669 ret.w lr @ CP#13
670 ret.w lr @ CP#14 (Debug)
671 ret.w lr @ CP#15 (Control)
672
673#ifdef NEED_CPU_ARCHITECTURE
674 .align 2
675.LCcpu_architecture:
676 .word __cpu_architecture
677#endif
678
679#ifdef CONFIG_NEON
680 .align 6
681
682.LCneon_arm_opcodes:
683 .word 0xfe000000 @ mask
684 .word 0xf2000000 @ opcode
685
686 .word 0xff100000 @ mask
687 .word 0xf4000000 @ opcode
688
689 .word 0x00000000 @ mask
690 .word 0x00000000 @ opcode
691
692.LCneon_thumb_opcodes:
693 .word 0xef000000 @ mask
694 .word 0xef000000 @ opcode
695
696 .word 0xff100000 @ mask
697 .word 0xf9000000 @ opcode
698
699 .word 0x00000000 @ mask
700 .word 0x00000000 @ opcode
701#endif
702
703do_fpe:
704 ldr r4, .LCfp
705 add r10, r10, #TI_FPSTATE @ r10 = workspace
706 ldr pc, [r4] @ Call FP module USR entry point
707
708/*
709 * The FP module is called with these registers set:
710 * r0 = instruction
711 * r2 = PC+4
712 * r9 = normal "successful" return address
713 * r10 = FP workspace
714 * lr = unrecognised FP instruction return address
715 */
716
717 .pushsection .data
718ENTRY(fp_enter)
719 .word no_fp
720 .popsection
721
722ENTRY(no_fp)
723 ret lr
724ENDPROC(no_fp)
725
726__und_usr_fault_32:
727 mov r1, #4
728 b 1f
729__und_usr_fault_16_pan:
730 uaccess_disable ip
731__und_usr_fault_16:
732 mov r1, #2
7331: mov r0, sp
734 badr lr, ret_from_exception
735 b __und_fault
736ENDPROC(__und_usr_fault_32)
737ENDPROC(__und_usr_fault_16)
738
739 .align 5
740__pabt_usr:
741 usr_entry
742 mov r2, sp @ regs
743 pabt_helper
744 UNWIND(.fnend )
745 /* fall through */
746/*
747 * This is the return code to user mode for abort handlers
748 */
749ENTRY(ret_from_exception)
750 UNWIND(.fnstart )
751 UNWIND(.cantunwind )
752 get_thread_info tsk
753 mov why, #0
754 b ret_to_user
755 UNWIND(.fnend )
756ENDPROC(__pabt_usr)
757ENDPROC(ret_from_exception)
758
759 .align 5
760__fiq_usr:
761 usr_entry trace=0
762 kuser_cmpxchg_check
763 mov r0, sp @ struct pt_regs *regs
764 bl handle_fiq_as_nmi
765 get_thread_info tsk
766 restore_user_regs fast = 0, offset = 0
767 UNWIND(.fnend )
768ENDPROC(__fiq_usr)
769
770/*
771 * Register switch for ARMv3 and ARMv4 processors
772 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
773 * previous and next are guaranteed not to be the same.
774 */
775ENTRY(__switch_to)
776 UNWIND(.fnstart )
777 UNWIND(.cantunwind )
778 add ip, r1, #TI_CPU_SAVE
779 ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack
780 THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack
781 THUMB( str sp, [ip], #4 )
782 THUMB( str lr, [ip], #4 )
783 ldr r4, [r2, #TI_TP_VALUE]
784 ldr r5, [r2, #TI_TP_VALUE + 4]
785#ifdef CONFIG_CPU_USE_DOMAINS
786 mrc p15, 0, r6, c3, c0, 0 @ Get domain register
787 str r6, [r1, #TI_CPU_DOMAIN] @ Save old domain register
788 ldr r6, [r2, #TI_CPU_DOMAIN]
789#endif
790 switch_tls r1, r4, r5, r3, r7
791#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
792 ldr r7, [r2, #TI_TASK]
793 ldr r8, =__stack_chk_guard
794 ldr r7, [r7, #TSK_STACK_CANARY]
795#endif
796#ifdef CONFIG_CPU_USE_DOMAINS
797 mcr p15, 0, r6, c3, c0, 0 @ Set domain register
798#endif
799 mov r5, r0
800 add r4, r2, #TI_CPU_SAVE
801 ldr r0, =thread_notify_head
802 mov r1, #THREAD_NOTIFY_SWITCH
803 bl atomic_notifier_call_chain
804#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
805 str r7, [r8]
806#endif
807 THUMB( mov ip, r4 )
808 mov r0, r5
809 ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously
810 THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously
811 THUMB( ldr sp, [ip], #4 )
812 THUMB( ldr pc, [ip] )
813 UNWIND(.fnend )
814ENDPROC(__switch_to)
815
816 __INIT
817
818/*
819 * User helpers.
820 *
821 * Each segment is 32-byte aligned and will be moved to the top of the high
822 * vector page. New segments (if ever needed) must be added in front of
823 * existing ones. This mechanism should be used only for things that are
824 * really small and justified, and not be abused freely.
825 *
826 * See Documentation/arm/kernel_user_helpers.txt for formal definitions.
827 */
828 THUMB( .arm )
829
830 .macro usr_ret, reg
831#ifdef CONFIG_ARM_THUMB
832 bx \reg
833#else
834 ret \reg
835#endif
836 .endm
837
838 .macro kuser_pad, sym, size
839 .if (. - \sym) & 3
840 .rept 4 - (. - \sym) & 3
841 .byte 0
842 .endr
843 .endif
844 .rept (\size - (. - \sym)) / 4
845 .word 0xe7fddef1
846 .endr
847 .endm
848
849#ifdef CONFIG_KUSER_HELPERS
850 .align 5
851 .globl __kuser_helper_start
852__kuser_helper_start:
853
854/*
855 * Due to the length of some sequences, __kuser_cmpxchg64 spans 2 regular
856 * kuser "slots", therefore 0xffff0f80 is not used as a valid entry point.
857 */
858
859__kuser_cmpxchg64: @ 0xffff0f60
860
861#if defined(CONFIG_CPU_32v6K)
862
863 stmfd sp!, {r4, r5, r6, r7}
864 ldrd r4, r5, [r0] @ load old val
865 ldrd r6, r7, [r1] @ load new val
866 smp_dmb arm
8671: ldrexd r0, r1, [r2] @ load current val
868 eors r3, r0, r4 @ compare with oldval (1)
869 eoreqs r3, r1, r5 @ compare with oldval (2)
870 strexdeq r3, r6, r7, [r2] @ store newval if eq
871 teqeq r3, #1 @ success?
872 beq 1b @ if no then retry
873 smp_dmb arm
874 rsbs r0, r3, #0 @ set returned val and C flag
875 ldmfd sp!, {r4, r5, r6, r7}
876 usr_ret lr
877
878#elif !defined(CONFIG_SMP)
879
880#ifdef CONFIG_MMU
881
882 /*
883 * The only thing that can break atomicity in this cmpxchg64
884 * implementation is either an IRQ or a data abort exception
885 * causing another process/thread to be scheduled in the middle of
886 * the critical sequence. The same strategy as for cmpxchg is used.
887 */
888 stmfd sp!, {r4, r5, r6, lr}
889 ldmia r0, {r4, r5} @ load old val
890 ldmia r1, {r6, lr} @ load new val
8911: ldmia r2, {r0, r1} @ load current val
892 eors r3, r0, r4 @ compare with oldval (1)
893 eoreqs r3, r1, r5 @ compare with oldval (2)
8942: stmeqia r2, {r6, lr} @ store newval if eq
895 rsbs r0, r3, #0 @ set return val and C flag
896 ldmfd sp!, {r4, r5, r6, pc}
897
898 .text
899kuser_cmpxchg64_fixup:
900 @ Called from kuser_cmpxchg_fixup.
901 @ r4 = address of interrupted insn (must be preserved).
902 @ sp = saved regs. r7 and r8 are clobbered.
903 @ 1b = first critical insn, 2b = last critical insn.
904 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b.
905 mov r7, #0xffff0fff
906 sub r7, r7, #(0xffff0fff - (0xffff0f60 + (1b - __kuser_cmpxchg64)))
907 subs r8, r4, r7
908 rsbcss r8, r8, #(2b - 1b)
909 strcs r7, [sp, #S_PC]
910#if __LINUX_ARM_ARCH__ < 6
911 bcc kuser_cmpxchg32_fixup
912#endif
913 ret lr
914 .previous
915
916#else
917#warning "NPTL on non MMU needs fixing"
918 mov r0, #-1
919 adds r0, r0, #0
920 usr_ret lr
921#endif
922
923#else
924#error "incoherent kernel configuration"
925#endif
926
927 kuser_pad __kuser_cmpxchg64, 64
928
929__kuser_memory_barrier: @ 0xffff0fa0
930 smp_dmb arm
931 usr_ret lr
932
933 kuser_pad __kuser_memory_barrier, 32
934
935__kuser_cmpxchg: @ 0xffff0fc0
936
937#if __LINUX_ARM_ARCH__ < 6
938
939#ifdef CONFIG_MMU
940
941 /*
942 * The only thing that can break atomicity in this cmpxchg
943 * implementation is either an IRQ or a data abort exception
944 * causing another process/thread to be scheduled in the middle
945 * of the critical sequence. To prevent this, code is added to
946 * the IRQ and data abort exception handlers to set the pc back
947 * to the beginning of the critical section if it is found to be
948 * within that critical section (see kuser_cmpxchg_fixup).
949 */
9501: ldr r3, [r2] @ load current val
951 subs r3, r3, r0 @ compare with oldval
9522: streq r1, [r2] @ store newval if eq
953 rsbs r0, r3, #0 @ set return val and C flag
954 usr_ret lr
955
956 .text
957kuser_cmpxchg32_fixup:
958 @ Called from kuser_cmpxchg_check macro.
959 @ r4 = address of interrupted insn (must be preserved).
960 @ sp = saved regs. r7 and r8 are clobbered.
961 @ 1b = first critical insn, 2b = last critical insn.
962 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b.
963 mov r7, #0xffff0fff
964 sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg)))
965 subs r8, r4, r7
966 rsbcss r8, r8, #(2b - 1b)
967 strcs r7, [sp, #S_PC]
968 ret lr
969 .previous
970
971#else
972#warning "NPTL on non MMU needs fixing"
973 mov r0, #-1
974 adds r0, r0, #0
975 usr_ret lr
976#endif
977
978#else
979
980 smp_dmb arm
9811: ldrex r3, [r2]
982 subs r3, r3, r0
983 strexeq r3, r1, [r2]
984 teqeq r3, #1
985 beq 1b
986 rsbs r0, r3, #0
987 /* beware -- each __kuser slot must be 8 instructions max */
988 ALT_SMP(b __kuser_memory_barrier)
989 ALT_UP(usr_ret lr)
990
991#endif
992
993 kuser_pad __kuser_cmpxchg, 32
994
995__kuser_get_tls: @ 0xffff0fe0
996 ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init
997 usr_ret lr
998 mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code
999 kuser_pad __kuser_get_tls, 16
1000 .rep 3
1001 .word 0 @ 0xffff0ff0 software TLS value, then
1002 .endr @ pad up to __kuser_helper_version
1003
1004__kuser_helper_version: @ 0xffff0ffc
1005 .word ((__kuser_helper_end - __kuser_helper_start) >> 5)
1006
1007 .globl __kuser_helper_end
1008__kuser_helper_end:
1009
1010#endif
1011
1012 THUMB( .thumb )
1013
1014/*
1015 * Vector stubs.
1016 *
1017 * This code is copied to 0xffff1000 so we can use branches in the
1018 * vectors, rather than ldr's. Note that this code must not exceed
1019 * a page size.
1020 *
1021 * Common stub entry macro:
1022 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1023 *
1024 * SP points to a minimal amount of processor-private memory, the address
1025 * of which is copied into r0 for the mode specific abort handler.
1026 */
1027 .macro vector_stub, name, mode, correction=0
1028 .align 5
1029
1030vector_\name:
1031 .if \correction
1032 sub lr, lr, #\correction
1033 .endif
1034
1035 @
1036 @ Save r0, lr_<exception> (parent PC) and spsr_<exception>
1037 @ (parent CPSR)
1038 @
1039 stmia sp, {r0, lr} @ save r0, lr
1040 mrs lr, spsr
1041 str lr, [sp, #8] @ save spsr
1042
1043 @
1044 @ Prepare for SVC32 mode. IRQs remain disabled.
1045 @
1046 mrs r0, cpsr
1047 eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE)
1048 msr spsr_cxsf, r0
1049
1050 @
1051 @ the branch table must immediately follow this code
1052 @
1053 and lr, lr, #0x0f
1054 THUMB( adr r0, 1f )
1055 THUMB( ldr lr, [r0, lr, lsl #2] )
1056 mov r0, sp
1057 ARM( ldr lr, [pc, lr, lsl #2] )
1058 movs pc, lr @ branch to handler in SVC mode
1059ENDPROC(vector_\name)
1060
1061 .align 2
1062 @ handler addresses follow this label
10631:
1064 .endm
1065
1066 .section .stubs, "ax", %progbits
1067 @ This must be the first word
1068 .word vector_swi
1069
1070vector_rst:
1071 ARM( swi SYS_ERROR0 )
1072 THUMB( svc #0 )
1073 THUMB( nop )
1074 b vector_und
1075
1076/*
1077 * Interrupt dispatcher
1078 */
1079 vector_stub irq, IRQ_MODE, 4
1080
1081 .long __irq_usr @ 0 (USR_26 / USR_32)
1082 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32)
1083 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32)
1084 .long __irq_svc @ 3 (SVC_26 / SVC_32)
1085 .long __irq_invalid @ 4
1086 .long __irq_invalid @ 5
1087 .long __irq_invalid @ 6
1088 .long __irq_invalid @ 7
1089 .long __irq_invalid @ 8
1090 .long __irq_invalid @ 9
1091 .long __irq_invalid @ a
1092 .long __irq_invalid @ b
1093 .long __irq_invalid @ c
1094 .long __irq_invalid @ d
1095 .long __irq_invalid @ e
1096 .long __irq_invalid @ f
1097
1098/*
1099 * Data abort dispatcher
1100 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1101 */
1102 vector_stub dabt, ABT_MODE, 8
1103
1104 .long __dabt_usr @ 0 (USR_26 / USR_32)
1105 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32)
1106 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32)
1107 .long __dabt_svc @ 3 (SVC_26 / SVC_32)
1108 .long __dabt_invalid @ 4
1109 .long __dabt_invalid @ 5
1110 .long __dabt_invalid @ 6
1111 .long __dabt_invalid @ 7
1112 .long __dabt_invalid @ 8
1113 .long __dabt_invalid @ 9
1114 .long __dabt_invalid @ a
1115 .long __dabt_invalid @ b
1116 .long __dabt_invalid @ c
1117 .long __dabt_invalid @ d
1118 .long __dabt_invalid @ e
1119 .long __dabt_invalid @ f
1120
1121/*
1122 * Prefetch abort dispatcher
1123 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1124 */
1125 vector_stub pabt, ABT_MODE, 4
1126
1127 .long __pabt_usr @ 0 (USR_26 / USR_32)
1128 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32)
1129 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32)
1130 .long __pabt_svc @ 3 (SVC_26 / SVC_32)
1131 .long __pabt_invalid @ 4
1132 .long __pabt_invalid @ 5
1133 .long __pabt_invalid @ 6
1134 .long __pabt_invalid @ 7
1135 .long __pabt_invalid @ 8
1136 .long __pabt_invalid @ 9
1137 .long __pabt_invalid @ a
1138 .long __pabt_invalid @ b
1139 .long __pabt_invalid @ c
1140 .long __pabt_invalid @ d
1141 .long __pabt_invalid @ e
1142 .long __pabt_invalid @ f
1143
1144/*
1145 * Undef instr entry dispatcher
1146 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1147 */
1148 vector_stub und, UND_MODE
1149
1150 .long __und_usr @ 0 (USR_26 / USR_32)
1151 .long __und_invalid @ 1 (FIQ_26 / FIQ_32)
1152 .long __und_invalid @ 2 (IRQ_26 / IRQ_32)
1153 .long __und_svc @ 3 (SVC_26 / SVC_32)
1154 .long __und_invalid @ 4
1155 .long __und_invalid @ 5
1156 .long __und_invalid @ 6
1157 .long __und_invalid @ 7
1158 .long __und_invalid @ 8
1159 .long __und_invalid @ 9
1160 .long __und_invalid @ a
1161 .long __und_invalid @ b
1162 .long __und_invalid @ c
1163 .long __und_invalid @ d
1164 .long __und_invalid @ e
1165 .long __und_invalid @ f
1166
1167 .align 5
1168
1169/*=============================================================================
1170 * Address exception handler
1171 *-----------------------------------------------------------------------------
1172 * These aren't too critical.
1173 * (they're not supposed to happen, and won't happen in 32-bit data mode).
1174 */
1175
1176vector_addrexcptn:
1177 b vector_addrexcptn
1178
1179/*=============================================================================
1180 * FIQ "NMI" handler
1181 *-----------------------------------------------------------------------------
1182 * Handle a FIQ using the SVC stack allowing FIQ act like NMI on x86
1183 * systems.
1184 */
1185 vector_stub fiq, FIQ_MODE, 4
1186
1187 .long __fiq_usr @ 0 (USR_26 / USR_32)
1188 .long __fiq_svc @ 1 (FIQ_26 / FIQ_32)
1189 .long __fiq_svc @ 2 (IRQ_26 / IRQ_32)
1190 .long __fiq_svc @ 3 (SVC_26 / SVC_32)
1191 .long __fiq_svc @ 4
1192 .long __fiq_svc @ 5
1193 .long __fiq_svc @ 6
1194 .long __fiq_abt @ 7
1195 .long __fiq_svc @ 8
1196 .long __fiq_svc @ 9
1197 .long __fiq_svc @ a
1198 .long __fiq_svc @ b
1199 .long __fiq_svc @ c
1200 .long __fiq_svc @ d
1201 .long __fiq_svc @ e
1202 .long __fiq_svc @ f
1203
1204 .globl vector_fiq
1205
1206 .section .vectors, "ax", %progbits
1207.L__vectors_start:
1208 W(b) vector_rst
1209 W(b) vector_und
1210 W(ldr) pc, .L__vectors_start + 0x1000
1211 W(b) vector_pabt
1212 W(b) vector_dabt
1213 W(b) vector_addrexcptn
1214 W(b) vector_irq
1215 W(b) vector_fiq
1216
1217 .data
1218
1219 .globl cr_alignment
1220cr_alignment:
1221 .space 4
1222
1223#ifdef CONFIG_MULTI_IRQ_HANDLER
1224 .globl handle_arch_irq
1225handle_arch_irq:
1226 .space 4
1227#endif
1/*
2 * linux/arch/arm/kernel/entry-armv.S
3 *
4 * Copyright (C) 1996,1997,1998 Russell King.
5 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk)
6 * nommu support by Hyok S. Choi (hyok.choi@samsung.com)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Low-level vector interface routines
13 *
14 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction
15 * that causes it to save wrong values... Be aware!
16 */
17
18#include <linux/init.h>
19
20#include <asm/assembler.h>
21#include <asm/memory.h>
22#include <asm/glue-df.h>
23#include <asm/glue-pf.h>
24#include <asm/vfpmacros.h>
25#ifndef CONFIG_MULTI_IRQ_HANDLER
26#include <mach/entry-macro.S>
27#endif
28#include <asm/thread_notify.h>
29#include <asm/unwind.h>
30#include <asm/unistd.h>
31#include <asm/tls.h>
32#include <asm/system_info.h>
33
34#include "entry-header.S"
35#include <asm/entry-macro-multi.S>
36#include <asm/probes.h>
37
38/*
39 * Interrupt handling.
40 */
41 .macro irq_handler
42#ifdef CONFIG_MULTI_IRQ_HANDLER
43 ldr r1, =handle_arch_irq
44 mov r0, sp
45 badr lr, 9997f
46 ldr pc, [r1]
47#else
48 arch_irq_handler_default
49#endif
509997:
51 .endm
52
53 .macro pabt_helper
54 @ PABORT handler takes pt_regs in r2, fault address in r4 and psr in r5
55#ifdef MULTI_PABORT
56 ldr ip, .LCprocfns
57 mov lr, pc
58 ldr pc, [ip, #PROCESSOR_PABT_FUNC]
59#else
60 bl CPU_PABORT_HANDLER
61#endif
62 .endm
63
64 .macro dabt_helper
65
66 @
67 @ Call the processor-specific abort handler:
68 @
69 @ r2 - pt_regs
70 @ r4 - aborted context pc
71 @ r5 - aborted context psr
72 @
73 @ The abort handler must return the aborted address in r0, and
74 @ the fault status register in r1. r9 must be preserved.
75 @
76#ifdef MULTI_DABORT
77 ldr ip, .LCprocfns
78 mov lr, pc
79 ldr pc, [ip, #PROCESSOR_DABT_FUNC]
80#else
81 bl CPU_DABORT_HANDLER
82#endif
83 .endm
84
85 .section .entry.text,"ax",%progbits
86
87/*
88 * Invalid mode handlers
89 */
90 .macro inv_entry, reason
91 sub sp, sp, #PT_REGS_SIZE
92 ARM( stmib sp, {r1 - lr} )
93 THUMB( stmia sp, {r0 - r12} )
94 THUMB( str sp, [sp, #S_SP] )
95 THUMB( str lr, [sp, #S_LR] )
96 mov r1, #\reason
97 .endm
98
99__pabt_invalid:
100 inv_entry BAD_PREFETCH
101 b common_invalid
102ENDPROC(__pabt_invalid)
103
104__dabt_invalid:
105 inv_entry BAD_DATA
106 b common_invalid
107ENDPROC(__dabt_invalid)
108
109__irq_invalid:
110 inv_entry BAD_IRQ
111 b common_invalid
112ENDPROC(__irq_invalid)
113
114__und_invalid:
115 inv_entry BAD_UNDEFINSTR
116
117 @
118 @ XXX fall through to common_invalid
119 @
120
121@
122@ common_invalid - generic code for failed exception (re-entrant version of handlers)
123@
124common_invalid:
125 zero_fp
126
127 ldmia r0, {r4 - r6}
128 add r0, sp, #S_PC @ here for interlock avoidance
129 mov r7, #-1 @ "" "" "" ""
130 str r4, [sp] @ save preserved r0
131 stmia r0, {r5 - r7} @ lr_<exception>,
132 @ cpsr_<exception>, "old_r0"
133
134 mov r0, sp
135 b bad_mode
136ENDPROC(__und_invalid)
137
138/*
139 * SVC mode handlers
140 */
141
142#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
143#define SPFIX(code...) code
144#else
145#define SPFIX(code...)
146#endif
147
148 .macro svc_entry, stack_hole=0, trace=1, uaccess=1
149 UNWIND(.fnstart )
150 UNWIND(.save {r0 - pc} )
151 sub sp, sp, #(SVC_REGS_SIZE + \stack_hole - 4)
152#ifdef CONFIG_THUMB2_KERNEL
153 SPFIX( str r0, [sp] ) @ temporarily saved
154 SPFIX( mov r0, sp )
155 SPFIX( tst r0, #4 ) @ test original stack alignment
156 SPFIX( ldr r0, [sp] ) @ restored
157#else
158 SPFIX( tst sp, #4 )
159#endif
160 SPFIX( subeq sp, sp, #4 )
161 stmia sp, {r1 - r12}
162
163 ldmia r0, {r3 - r5}
164 add r7, sp, #S_SP - 4 @ here for interlock avoidance
165 mov r6, #-1 @ "" "" "" ""
166 add r2, sp, #(SVC_REGS_SIZE + \stack_hole - 4)
167 SPFIX( addeq r2, r2, #4 )
168 str r3, [sp, #-4]! @ save the "real" r0 copied
169 @ from the exception stack
170
171 mov r3, lr
172
173 @
174 @ We are now ready to fill in the remaining blanks on the stack:
175 @
176 @ r2 - sp_svc
177 @ r3 - lr_svc
178 @ r4 - lr_<exception>, already fixed up for correct return/restart
179 @ r5 - spsr_<exception>
180 @ r6 - orig_r0 (see pt_regs definition in ptrace.h)
181 @
182 stmia r7, {r2 - r6}
183
184 get_thread_info tsk
185 ldr r0, [tsk, #TI_ADDR_LIMIT]
186 mov r1, #TASK_SIZE
187 str r1, [tsk, #TI_ADDR_LIMIT]
188 str r0, [sp, #SVC_ADDR_LIMIT]
189
190 uaccess_save r0
191 .if \uaccess
192 uaccess_disable r0
193 .endif
194
195 .if \trace
196#ifdef CONFIG_TRACE_IRQFLAGS
197 bl trace_hardirqs_off
198#endif
199 .endif
200 .endm
201
202 .align 5
203__dabt_svc:
204 svc_entry uaccess=0
205 mov r2, sp
206 dabt_helper
207 THUMB( ldr r5, [sp, #S_PSR] ) @ potentially updated CPSR
208 svc_exit r5 @ return from exception
209 UNWIND(.fnend )
210ENDPROC(__dabt_svc)
211
212 .align 5
213__irq_svc:
214 svc_entry
215 irq_handler
216
217#ifdef CONFIG_PREEMPT
218 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
219 ldr r0, [tsk, #TI_FLAGS] @ get flags
220 teq r8, #0 @ if preempt count != 0
221 movne r0, #0 @ force flags to 0
222 tst r0, #_TIF_NEED_RESCHED
223 blne svc_preempt
224#endif
225
226 svc_exit r5, irq = 1 @ return from exception
227 UNWIND(.fnend )
228ENDPROC(__irq_svc)
229
230 .ltorg
231
232#ifdef CONFIG_PREEMPT
233svc_preempt:
234 mov r8, lr
2351: bl preempt_schedule_irq @ irq en/disable is done inside
236 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS
237 tst r0, #_TIF_NEED_RESCHED
238 reteq r8 @ go again
239 b 1b
240#endif
241
242__und_fault:
243 @ Correct the PC such that it is pointing at the instruction
244 @ which caused the fault. If the faulting instruction was ARM
245 @ the PC will be pointing at the next instruction, and have to
246 @ subtract 4. Otherwise, it is Thumb, and the PC will be
247 @ pointing at the second half of the Thumb instruction. We
248 @ have to subtract 2.
249 ldr r2, [r0, #S_PC]
250 sub r2, r2, r1
251 str r2, [r0, #S_PC]
252 b do_undefinstr
253ENDPROC(__und_fault)
254
255 .align 5
256__und_svc:
257#ifdef CONFIG_KPROBES
258 @ If a kprobe is about to simulate a "stmdb sp..." instruction,
259 @ it obviously needs free stack space which then will belong to
260 @ the saved context.
261 svc_entry MAX_STACK_SIZE
262#else
263 svc_entry
264#endif
265 @
266 @ call emulation code, which returns using r9 if it has emulated
267 @ the instruction, or the more conventional lr if we are to treat
268 @ this as a real undefined instruction
269 @
270 @ r0 - instruction
271 @
272#ifndef CONFIG_THUMB2_KERNEL
273 ldr r0, [r4, #-4]
274#else
275 mov r1, #2
276 ldrh r0, [r4, #-2] @ Thumb instruction at LR - 2
277 cmp r0, #0xe800 @ 32-bit instruction if xx >= 0
278 blo __und_svc_fault
279 ldrh r9, [r4] @ bottom 16 bits
280 add r4, r4, #2
281 str r4, [sp, #S_PC]
282 orr r0, r9, r0, lsl #16
283#endif
284 badr r9, __und_svc_finish
285 mov r2, r4
286 bl call_fpe
287
288 mov r1, #4 @ PC correction to apply
289__und_svc_fault:
290 mov r0, sp @ struct pt_regs *regs
291 bl __und_fault
292
293__und_svc_finish:
294 get_thread_info tsk
295 ldr r5, [sp, #S_PSR] @ Get SVC cpsr
296 svc_exit r5 @ return from exception
297 UNWIND(.fnend )
298ENDPROC(__und_svc)
299
300 .align 5
301__pabt_svc:
302 svc_entry
303 mov r2, sp @ regs
304 pabt_helper
305 svc_exit r5 @ return from exception
306 UNWIND(.fnend )
307ENDPROC(__pabt_svc)
308
309 .align 5
310__fiq_svc:
311 svc_entry trace=0
312 mov r0, sp @ struct pt_regs *regs
313 bl handle_fiq_as_nmi
314 svc_exit_via_fiq
315 UNWIND(.fnend )
316ENDPROC(__fiq_svc)
317
318 .align 5
319.LCcralign:
320 .word cr_alignment
321#ifdef MULTI_DABORT
322.LCprocfns:
323 .word processor
324#endif
325.LCfp:
326 .word fp_enter
327
328/*
329 * Abort mode handlers
330 */
331
332@
333@ Taking a FIQ in abort mode is similar to taking a FIQ in SVC mode
334@ and reuses the same macros. However in abort mode we must also
335@ save/restore lr_abt and spsr_abt to make nested aborts safe.
336@
337 .align 5
338__fiq_abt:
339 svc_entry trace=0
340
341 ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
342 THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
343 THUMB( msr cpsr_c, r0 )
344 mov r1, lr @ Save lr_abt
345 mrs r2, spsr @ Save spsr_abt, abort is now safe
346 ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
347 THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
348 THUMB( msr cpsr_c, r0 )
349 stmfd sp!, {r1 - r2}
350
351 add r0, sp, #8 @ struct pt_regs *regs
352 bl handle_fiq_as_nmi
353
354 ldmfd sp!, {r1 - r2}
355 ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
356 THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
357 THUMB( msr cpsr_c, r0 )
358 mov lr, r1 @ Restore lr_abt, abort is unsafe
359 msr spsr_cxsf, r2 @ Restore spsr_abt
360 ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
361 THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
362 THUMB( msr cpsr_c, r0 )
363
364 svc_exit_via_fiq
365 UNWIND(.fnend )
366ENDPROC(__fiq_abt)
367
368/*
369 * User mode handlers
370 *
371 * EABI note: sp_svc is always 64-bit aligned here, so should PT_REGS_SIZE
372 */
373
374#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (PT_REGS_SIZE & 7)
375#error "sizeof(struct pt_regs) must be a multiple of 8"
376#endif
377
378 .macro usr_entry, trace=1, uaccess=1
379 UNWIND(.fnstart )
380 UNWIND(.cantunwind ) @ don't unwind the user space
381 sub sp, sp, #PT_REGS_SIZE
382 ARM( stmib sp, {r1 - r12} )
383 THUMB( stmia sp, {r0 - r12} )
384
385 ATRAP( mrc p15, 0, r7, c1, c0, 0)
386 ATRAP( ldr r8, .LCcralign)
387
388 ldmia r0, {r3 - r5}
389 add r0, sp, #S_PC @ here for interlock avoidance
390 mov r6, #-1 @ "" "" "" ""
391
392 str r3, [sp] @ save the "real" r0 copied
393 @ from the exception stack
394
395 ATRAP( ldr r8, [r8, #0])
396
397 @
398 @ We are now ready to fill in the remaining blanks on the stack:
399 @
400 @ r4 - lr_<exception>, already fixed up for correct return/restart
401 @ r5 - spsr_<exception>
402 @ r6 - orig_r0 (see pt_regs definition in ptrace.h)
403 @
404 @ Also, separately save sp_usr and lr_usr
405 @
406 stmia r0, {r4 - r6}
407 ARM( stmdb r0, {sp, lr}^ )
408 THUMB( store_user_sp_lr r0, r1, S_SP - S_PC )
409
410 .if \uaccess
411 uaccess_disable ip
412 .endif
413
414 @ Enable the alignment trap while in kernel mode
415 ATRAP( teq r8, r7)
416 ATRAP( mcrne p15, 0, r8, c1, c0, 0)
417
418 @
419 @ Clear FP to mark the first stack frame
420 @
421 zero_fp
422
423 .if \trace
424#ifdef CONFIG_TRACE_IRQFLAGS
425 bl trace_hardirqs_off
426#endif
427 ct_user_exit save = 0
428 .endif
429 .endm
430
431 .macro kuser_cmpxchg_check
432#if !defined(CONFIG_CPU_32v6K) && defined(CONFIG_KUSER_HELPERS)
433#ifndef CONFIG_MMU
434#warning "NPTL on non MMU needs fixing"
435#else
436 @ Make sure our user space atomic helper is restarted
437 @ if it was interrupted in a critical region. Here we
438 @ perform a quick test inline since it should be false
439 @ 99.9999% of the time. The rest is done out of line.
440 cmp r4, #TASK_SIZE
441 blhs kuser_cmpxchg64_fixup
442#endif
443#endif
444 .endm
445
446 .align 5
447__dabt_usr:
448 usr_entry uaccess=0
449 kuser_cmpxchg_check
450 mov r2, sp
451 dabt_helper
452 b ret_from_exception
453 UNWIND(.fnend )
454ENDPROC(__dabt_usr)
455
456 .align 5
457__irq_usr:
458 usr_entry
459 kuser_cmpxchg_check
460 irq_handler
461 get_thread_info tsk
462 mov why, #0
463 b ret_to_user_from_irq
464 UNWIND(.fnend )
465ENDPROC(__irq_usr)
466
467 .ltorg
468
469 .align 5
470__und_usr:
471 usr_entry uaccess=0
472
473 mov r2, r4
474 mov r3, r5
475
476 @ r2 = regs->ARM_pc, which is either 2 or 4 bytes ahead of the
477 @ faulting instruction depending on Thumb mode.
478 @ r3 = regs->ARM_cpsr
479 @
480 @ The emulation code returns using r9 if it has emulated the
481 @ instruction, or the more conventional lr if we are to treat
482 @ this as a real undefined instruction
483 @
484 badr r9, ret_from_exception
485
486 @ IRQs must be enabled before attempting to read the instruction from
487 @ user space since that could cause a page/translation fault if the
488 @ page table was modified by another CPU.
489 enable_irq
490
491 tst r3, #PSR_T_BIT @ Thumb mode?
492 bne __und_usr_thumb
493 sub r4, r2, #4 @ ARM instr at LR - 4
4941: ldrt r0, [r4]
495 ARM_BE8(rev r0, r0) @ little endian instruction
496
497 uaccess_disable ip
498
499 @ r0 = 32-bit ARM instruction which caused the exception
500 @ r2 = PC value for the following instruction (:= regs->ARM_pc)
501 @ r4 = PC value for the faulting instruction
502 @ lr = 32-bit undefined instruction function
503 badr lr, __und_usr_fault_32
504 b call_fpe
505
506__und_usr_thumb:
507 @ Thumb instruction
508 sub r4, r2, #2 @ First half of thumb instr at LR - 2
509#if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7
510/*
511 * Thumb-2 instruction handling. Note that because pre-v6 and >= v6 platforms
512 * can never be supported in a single kernel, this code is not applicable at
513 * all when __LINUX_ARM_ARCH__ < 6. This allows simplifying assumptions to be
514 * made about .arch directives.
515 */
516#if __LINUX_ARM_ARCH__ < 7
517/* If the target CPU may not be Thumb-2-capable, a run-time check is needed: */
518#define NEED_CPU_ARCHITECTURE
519 ldr r5, .LCcpu_architecture
520 ldr r5, [r5]
521 cmp r5, #CPU_ARCH_ARMv7
522 blo __und_usr_fault_16 @ 16bit undefined instruction
523/*
524 * The following code won't get run unless the running CPU really is v7, so
525 * coding round the lack of ldrht on older arches is pointless. Temporarily
526 * override the assembler target arch with the minimum required instead:
527 */
528 .arch armv6t2
529#endif
5302: ldrht r5, [r4]
531ARM_BE8(rev16 r5, r5) @ little endian instruction
532 cmp r5, #0xe800 @ 32bit instruction if xx != 0
533 blo __und_usr_fault_16_pan @ 16bit undefined instruction
5343: ldrht r0, [r2]
535ARM_BE8(rev16 r0, r0) @ little endian instruction
536 uaccess_disable ip
537 add r2, r2, #2 @ r2 is PC + 2, make it PC + 4
538 str r2, [sp, #S_PC] @ it's a 2x16bit instr, update
539 orr r0, r0, r5, lsl #16
540 badr lr, __und_usr_fault_32
541 @ r0 = the two 16-bit Thumb instructions which caused the exception
542 @ r2 = PC value for the following Thumb instruction (:= regs->ARM_pc)
543 @ r4 = PC value for the first 16-bit Thumb instruction
544 @ lr = 32bit undefined instruction function
545
546#if __LINUX_ARM_ARCH__ < 7
547/* If the target arch was overridden, change it back: */
548#ifdef CONFIG_CPU_32v6K
549 .arch armv6k
550#else
551 .arch armv6
552#endif
553#endif /* __LINUX_ARM_ARCH__ < 7 */
554#else /* !(CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7) */
555 b __und_usr_fault_16
556#endif
557 UNWIND(.fnend)
558ENDPROC(__und_usr)
559
560/*
561 * The out of line fixup for the ldrt instructions above.
562 */
563 .pushsection .text.fixup, "ax"
564 .align 2
5654: str r4, [sp, #S_PC] @ retry current instruction
566 ret r9
567 .popsection
568 .pushsection __ex_table,"a"
569 .long 1b, 4b
570#if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7
571 .long 2b, 4b
572 .long 3b, 4b
573#endif
574 .popsection
575
576/*
577 * Check whether the instruction is a co-processor instruction.
578 * If yes, we need to call the relevant co-processor handler.
579 *
580 * Note that we don't do a full check here for the co-processor
581 * instructions; all instructions with bit 27 set are well
582 * defined. The only instructions that should fault are the
583 * co-processor instructions. However, we have to watch out
584 * for the ARM6/ARM7 SWI bug.
585 *
586 * NEON is a special case that has to be handled here. Not all
587 * NEON instructions are co-processor instructions, so we have
588 * to make a special case of checking for them. Plus, there's
589 * five groups of them, so we have a table of mask/opcode pairs
590 * to check against, and if any match then we branch off into the
591 * NEON handler code.
592 *
593 * Emulators may wish to make use of the following registers:
594 * r0 = instruction opcode (32-bit ARM or two 16-bit Thumb)
595 * r2 = PC value to resume execution after successful emulation
596 * r9 = normal "successful" return address
597 * r10 = this threads thread_info structure
598 * lr = unrecognised instruction return address
599 * IRQs enabled, FIQs enabled.
600 */
601 @
602 @ Fall-through from Thumb-2 __und_usr
603 @
604#ifdef CONFIG_NEON
605 get_thread_info r10 @ get current thread
606 adr r6, .LCneon_thumb_opcodes
607 b 2f
608#endif
609call_fpe:
610 get_thread_info r10 @ get current thread
611#ifdef CONFIG_NEON
612 adr r6, .LCneon_arm_opcodes
6132: ldr r5, [r6], #4 @ mask value
614 ldr r7, [r6], #4 @ opcode bits matching in mask
615 cmp r5, #0 @ end mask?
616 beq 1f
617 and r8, r0, r5
618 cmp r8, r7 @ NEON instruction?
619 bne 2b
620 mov r7, #1
621 strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used
622 strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used
623 b do_vfp @ let VFP handler handle this
6241:
625#endif
626 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
627 tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2
628 reteq lr
629 and r8, r0, #0x00000f00 @ mask out CP number
630 THUMB( lsr r8, r8, #8 )
631 mov r7, #1
632 add r6, r10, #TI_USED_CP
633 ARM( strb r7, [r6, r8, lsr #8] ) @ set appropriate used_cp[]
634 THUMB( strb r7, [r6, r8] ) @ set appropriate used_cp[]
635#ifdef CONFIG_IWMMXT
636 @ Test if we need to give access to iWMMXt coprocessors
637 ldr r5, [r10, #TI_FLAGS]
638 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only
639 movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1)
640 bcs iwmmxt_task_enable
641#endif
642 ARM( add pc, pc, r8, lsr #6 )
643 THUMB( lsl r8, r8, #2 )
644 THUMB( add pc, r8 )
645 nop
646
647 ret.w lr @ CP#0
648 W(b) do_fpe @ CP#1 (FPE)
649 W(b) do_fpe @ CP#2 (FPE)
650 ret.w lr @ CP#3
651#ifdef CONFIG_CRUNCH
652 b crunch_task_enable @ CP#4 (MaverickCrunch)
653 b crunch_task_enable @ CP#5 (MaverickCrunch)
654 b crunch_task_enable @ CP#6 (MaverickCrunch)
655#else
656 ret.w lr @ CP#4
657 ret.w lr @ CP#5
658 ret.w lr @ CP#6
659#endif
660 ret.w lr @ CP#7
661 ret.w lr @ CP#8
662 ret.w lr @ CP#9
663#ifdef CONFIG_VFP
664 W(b) do_vfp @ CP#10 (VFP)
665 W(b) do_vfp @ CP#11 (VFP)
666#else
667 ret.w lr @ CP#10 (VFP)
668 ret.w lr @ CP#11 (VFP)
669#endif
670 ret.w lr @ CP#12
671 ret.w lr @ CP#13
672 ret.w lr @ CP#14 (Debug)
673 ret.w lr @ CP#15 (Control)
674
675#ifdef NEED_CPU_ARCHITECTURE
676 .align 2
677.LCcpu_architecture:
678 .word __cpu_architecture
679#endif
680
681#ifdef CONFIG_NEON
682 .align 6
683
684.LCneon_arm_opcodes:
685 .word 0xfe000000 @ mask
686 .word 0xf2000000 @ opcode
687
688 .word 0xff100000 @ mask
689 .word 0xf4000000 @ opcode
690
691 .word 0x00000000 @ mask
692 .word 0x00000000 @ opcode
693
694.LCneon_thumb_opcodes:
695 .word 0xef000000 @ mask
696 .word 0xef000000 @ opcode
697
698 .word 0xff100000 @ mask
699 .word 0xf9000000 @ opcode
700
701 .word 0x00000000 @ mask
702 .word 0x00000000 @ opcode
703#endif
704
705do_fpe:
706 ldr r4, .LCfp
707 add r10, r10, #TI_FPSTATE @ r10 = workspace
708 ldr pc, [r4] @ Call FP module USR entry point
709
710/*
711 * The FP module is called with these registers set:
712 * r0 = instruction
713 * r2 = PC+4
714 * r9 = normal "successful" return address
715 * r10 = FP workspace
716 * lr = unrecognised FP instruction return address
717 */
718
719 .pushsection .data
720 .align 2
721ENTRY(fp_enter)
722 .word no_fp
723 .popsection
724
725ENTRY(no_fp)
726 ret lr
727ENDPROC(no_fp)
728
729__und_usr_fault_32:
730 mov r1, #4
731 b 1f
732__und_usr_fault_16_pan:
733 uaccess_disable ip
734__und_usr_fault_16:
735 mov r1, #2
7361: mov r0, sp
737 badr lr, ret_from_exception
738 b __und_fault
739ENDPROC(__und_usr_fault_32)
740ENDPROC(__und_usr_fault_16)
741
742 .align 5
743__pabt_usr:
744 usr_entry
745 mov r2, sp @ regs
746 pabt_helper
747 UNWIND(.fnend )
748 /* fall through */
749/*
750 * This is the return code to user mode for abort handlers
751 */
752ENTRY(ret_from_exception)
753 UNWIND(.fnstart )
754 UNWIND(.cantunwind )
755 get_thread_info tsk
756 mov why, #0
757 b ret_to_user
758 UNWIND(.fnend )
759ENDPROC(__pabt_usr)
760ENDPROC(ret_from_exception)
761
762 .align 5
763__fiq_usr:
764 usr_entry trace=0
765 kuser_cmpxchg_check
766 mov r0, sp @ struct pt_regs *regs
767 bl handle_fiq_as_nmi
768 get_thread_info tsk
769 restore_user_regs fast = 0, offset = 0
770 UNWIND(.fnend )
771ENDPROC(__fiq_usr)
772
773/*
774 * Register switch for ARMv3 and ARMv4 processors
775 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
776 * previous and next are guaranteed not to be the same.
777 */
778ENTRY(__switch_to)
779 UNWIND(.fnstart )
780 UNWIND(.cantunwind )
781 add ip, r1, #TI_CPU_SAVE
782 ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack
783 THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack
784 THUMB( str sp, [ip], #4 )
785 THUMB( str lr, [ip], #4 )
786 ldr r4, [r2, #TI_TP_VALUE]
787 ldr r5, [r2, #TI_TP_VALUE + 4]
788#ifdef CONFIG_CPU_USE_DOMAINS
789 mrc p15, 0, r6, c3, c0, 0 @ Get domain register
790 str r6, [r1, #TI_CPU_DOMAIN] @ Save old domain register
791 ldr r6, [r2, #TI_CPU_DOMAIN]
792#endif
793 switch_tls r1, r4, r5, r3, r7
794#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
795 ldr r7, [r2, #TI_TASK]
796 ldr r8, =__stack_chk_guard
797 .if (TSK_STACK_CANARY > IMM12_MASK)
798 add r7, r7, #TSK_STACK_CANARY & ~IMM12_MASK
799 .endif
800 ldr r7, [r7, #TSK_STACK_CANARY & IMM12_MASK]
801#endif
802#ifdef CONFIG_CPU_USE_DOMAINS
803 mcr p15, 0, r6, c3, c0, 0 @ Set domain register
804#endif
805 mov r5, r0
806 add r4, r2, #TI_CPU_SAVE
807 ldr r0, =thread_notify_head
808 mov r1, #THREAD_NOTIFY_SWITCH
809 bl atomic_notifier_call_chain
810#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
811 str r7, [r8]
812#endif
813 THUMB( mov ip, r4 )
814 mov r0, r5
815 ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously
816 THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously
817 THUMB( ldr sp, [ip], #4 )
818 THUMB( ldr pc, [ip] )
819 UNWIND(.fnend )
820ENDPROC(__switch_to)
821
822 __INIT
823
824/*
825 * User helpers.
826 *
827 * Each segment is 32-byte aligned and will be moved to the top of the high
828 * vector page. New segments (if ever needed) must be added in front of
829 * existing ones. This mechanism should be used only for things that are
830 * really small and justified, and not be abused freely.
831 *
832 * See Documentation/arm/kernel_user_helpers.txt for formal definitions.
833 */
834 THUMB( .arm )
835
836 .macro usr_ret, reg
837#ifdef CONFIG_ARM_THUMB
838 bx \reg
839#else
840 ret \reg
841#endif
842 .endm
843
844 .macro kuser_pad, sym, size
845 .if (. - \sym) & 3
846 .rept 4 - (. - \sym) & 3
847 .byte 0
848 .endr
849 .endif
850 .rept (\size - (. - \sym)) / 4
851 .word 0xe7fddef1
852 .endr
853 .endm
854
855#ifdef CONFIG_KUSER_HELPERS
856 .align 5
857 .globl __kuser_helper_start
858__kuser_helper_start:
859
860/*
861 * Due to the length of some sequences, __kuser_cmpxchg64 spans 2 regular
862 * kuser "slots", therefore 0xffff0f80 is not used as a valid entry point.
863 */
864
865__kuser_cmpxchg64: @ 0xffff0f60
866
867#if defined(CONFIG_CPU_32v6K)
868
869 stmfd sp!, {r4, r5, r6, r7}
870 ldrd r4, r5, [r0] @ load old val
871 ldrd r6, r7, [r1] @ load new val
872 smp_dmb arm
8731: ldrexd r0, r1, [r2] @ load current val
874 eors r3, r0, r4 @ compare with oldval (1)
875 eoreqs r3, r1, r5 @ compare with oldval (2)
876 strexdeq r3, r6, r7, [r2] @ store newval if eq
877 teqeq r3, #1 @ success?
878 beq 1b @ if no then retry
879 smp_dmb arm
880 rsbs r0, r3, #0 @ set returned val and C flag
881 ldmfd sp!, {r4, r5, r6, r7}
882 usr_ret lr
883
884#elif !defined(CONFIG_SMP)
885
886#ifdef CONFIG_MMU
887
888 /*
889 * The only thing that can break atomicity in this cmpxchg64
890 * implementation is either an IRQ or a data abort exception
891 * causing another process/thread to be scheduled in the middle of
892 * the critical sequence. The same strategy as for cmpxchg is used.
893 */
894 stmfd sp!, {r4, r5, r6, lr}
895 ldmia r0, {r4, r5} @ load old val
896 ldmia r1, {r6, lr} @ load new val
8971: ldmia r2, {r0, r1} @ load current val
898 eors r3, r0, r4 @ compare with oldval (1)
899 eoreqs r3, r1, r5 @ compare with oldval (2)
9002: stmeqia r2, {r6, lr} @ store newval if eq
901 rsbs r0, r3, #0 @ set return val and C flag
902 ldmfd sp!, {r4, r5, r6, pc}
903
904 .text
905kuser_cmpxchg64_fixup:
906 @ Called from kuser_cmpxchg_fixup.
907 @ r4 = address of interrupted insn (must be preserved).
908 @ sp = saved regs. r7 and r8 are clobbered.
909 @ 1b = first critical insn, 2b = last critical insn.
910 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b.
911 mov r7, #0xffff0fff
912 sub r7, r7, #(0xffff0fff - (0xffff0f60 + (1b - __kuser_cmpxchg64)))
913 subs r8, r4, r7
914 rsbcss r8, r8, #(2b - 1b)
915 strcs r7, [sp, #S_PC]
916#if __LINUX_ARM_ARCH__ < 6
917 bcc kuser_cmpxchg32_fixup
918#endif
919 ret lr
920 .previous
921
922#else
923#warning "NPTL on non MMU needs fixing"
924 mov r0, #-1
925 adds r0, r0, #0
926 usr_ret lr
927#endif
928
929#else
930#error "incoherent kernel configuration"
931#endif
932
933 kuser_pad __kuser_cmpxchg64, 64
934
935__kuser_memory_barrier: @ 0xffff0fa0
936 smp_dmb arm
937 usr_ret lr
938
939 kuser_pad __kuser_memory_barrier, 32
940
941__kuser_cmpxchg: @ 0xffff0fc0
942
943#if __LINUX_ARM_ARCH__ < 6
944
945#ifdef CONFIG_MMU
946
947 /*
948 * The only thing that can break atomicity in this cmpxchg
949 * implementation is either an IRQ or a data abort exception
950 * causing another process/thread to be scheduled in the middle
951 * of the critical sequence. To prevent this, code is added to
952 * the IRQ and data abort exception handlers to set the pc back
953 * to the beginning of the critical section if it is found to be
954 * within that critical section (see kuser_cmpxchg_fixup).
955 */
9561: ldr r3, [r2] @ load current val
957 subs r3, r3, r0 @ compare with oldval
9582: streq r1, [r2] @ store newval if eq
959 rsbs r0, r3, #0 @ set return val and C flag
960 usr_ret lr
961
962 .text
963kuser_cmpxchg32_fixup:
964 @ Called from kuser_cmpxchg_check macro.
965 @ r4 = address of interrupted insn (must be preserved).
966 @ sp = saved regs. r7 and r8 are clobbered.
967 @ 1b = first critical insn, 2b = last critical insn.
968 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b.
969 mov r7, #0xffff0fff
970 sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg)))
971 subs r8, r4, r7
972 rsbcss r8, r8, #(2b - 1b)
973 strcs r7, [sp, #S_PC]
974 ret lr
975 .previous
976
977#else
978#warning "NPTL on non MMU needs fixing"
979 mov r0, #-1
980 adds r0, r0, #0
981 usr_ret lr
982#endif
983
984#else
985
986 smp_dmb arm
9871: ldrex r3, [r2]
988 subs r3, r3, r0
989 strexeq r3, r1, [r2]
990 teqeq r3, #1
991 beq 1b
992 rsbs r0, r3, #0
993 /* beware -- each __kuser slot must be 8 instructions max */
994 ALT_SMP(b __kuser_memory_barrier)
995 ALT_UP(usr_ret lr)
996
997#endif
998
999 kuser_pad __kuser_cmpxchg, 32
1000
1001__kuser_get_tls: @ 0xffff0fe0
1002 ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init
1003 usr_ret lr
1004 mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code
1005 kuser_pad __kuser_get_tls, 16
1006 .rep 3
1007 .word 0 @ 0xffff0ff0 software TLS value, then
1008 .endr @ pad up to __kuser_helper_version
1009
1010__kuser_helper_version: @ 0xffff0ffc
1011 .word ((__kuser_helper_end - __kuser_helper_start) >> 5)
1012
1013 .globl __kuser_helper_end
1014__kuser_helper_end:
1015
1016#endif
1017
1018 THUMB( .thumb )
1019
1020/*
1021 * Vector stubs.
1022 *
1023 * This code is copied to 0xffff1000 so we can use branches in the
1024 * vectors, rather than ldr's. Note that this code must not exceed
1025 * a page size.
1026 *
1027 * Common stub entry macro:
1028 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1029 *
1030 * SP points to a minimal amount of processor-private memory, the address
1031 * of which is copied into r0 for the mode specific abort handler.
1032 */
1033 .macro vector_stub, name, mode, correction=0
1034 .align 5
1035
1036vector_\name:
1037 .if \correction
1038 sub lr, lr, #\correction
1039 .endif
1040
1041 @
1042 @ Save r0, lr_<exception> (parent PC) and spsr_<exception>
1043 @ (parent CPSR)
1044 @
1045 stmia sp, {r0, lr} @ save r0, lr
1046 mrs lr, spsr
1047 str lr, [sp, #8] @ save spsr
1048
1049 @
1050 @ Prepare for SVC32 mode. IRQs remain disabled.
1051 @
1052 mrs r0, cpsr
1053 eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE)
1054 msr spsr_cxsf, r0
1055
1056 @
1057 @ the branch table must immediately follow this code
1058 @
1059 and lr, lr, #0x0f
1060 THUMB( adr r0, 1f )
1061 THUMB( ldr lr, [r0, lr, lsl #2] )
1062 mov r0, sp
1063 ARM( ldr lr, [pc, lr, lsl #2] )
1064 movs pc, lr @ branch to handler in SVC mode
1065ENDPROC(vector_\name)
1066
1067 .align 2
1068 @ handler addresses follow this label
10691:
1070 .endm
1071
1072 .section .stubs, "ax", %progbits
1073 @ This must be the first word
1074 .word vector_swi
1075
1076vector_rst:
1077 ARM( swi SYS_ERROR0 )
1078 THUMB( svc #0 )
1079 THUMB( nop )
1080 b vector_und
1081
1082/*
1083 * Interrupt dispatcher
1084 */
1085 vector_stub irq, IRQ_MODE, 4
1086
1087 .long __irq_usr @ 0 (USR_26 / USR_32)
1088 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32)
1089 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32)
1090 .long __irq_svc @ 3 (SVC_26 / SVC_32)
1091 .long __irq_invalid @ 4
1092 .long __irq_invalid @ 5
1093 .long __irq_invalid @ 6
1094 .long __irq_invalid @ 7
1095 .long __irq_invalid @ 8
1096 .long __irq_invalid @ 9
1097 .long __irq_invalid @ a
1098 .long __irq_invalid @ b
1099 .long __irq_invalid @ c
1100 .long __irq_invalid @ d
1101 .long __irq_invalid @ e
1102 .long __irq_invalid @ f
1103
1104/*
1105 * Data abort dispatcher
1106 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1107 */
1108 vector_stub dabt, ABT_MODE, 8
1109
1110 .long __dabt_usr @ 0 (USR_26 / USR_32)
1111 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32)
1112 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32)
1113 .long __dabt_svc @ 3 (SVC_26 / SVC_32)
1114 .long __dabt_invalid @ 4
1115 .long __dabt_invalid @ 5
1116 .long __dabt_invalid @ 6
1117 .long __dabt_invalid @ 7
1118 .long __dabt_invalid @ 8
1119 .long __dabt_invalid @ 9
1120 .long __dabt_invalid @ a
1121 .long __dabt_invalid @ b
1122 .long __dabt_invalid @ c
1123 .long __dabt_invalid @ d
1124 .long __dabt_invalid @ e
1125 .long __dabt_invalid @ f
1126
1127/*
1128 * Prefetch abort dispatcher
1129 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1130 */
1131 vector_stub pabt, ABT_MODE, 4
1132
1133 .long __pabt_usr @ 0 (USR_26 / USR_32)
1134 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32)
1135 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32)
1136 .long __pabt_svc @ 3 (SVC_26 / SVC_32)
1137 .long __pabt_invalid @ 4
1138 .long __pabt_invalid @ 5
1139 .long __pabt_invalid @ 6
1140 .long __pabt_invalid @ 7
1141 .long __pabt_invalid @ 8
1142 .long __pabt_invalid @ 9
1143 .long __pabt_invalid @ a
1144 .long __pabt_invalid @ b
1145 .long __pabt_invalid @ c
1146 .long __pabt_invalid @ d
1147 .long __pabt_invalid @ e
1148 .long __pabt_invalid @ f
1149
1150/*
1151 * Undef instr entry dispatcher
1152 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1153 */
1154 vector_stub und, UND_MODE
1155
1156 .long __und_usr @ 0 (USR_26 / USR_32)
1157 .long __und_invalid @ 1 (FIQ_26 / FIQ_32)
1158 .long __und_invalid @ 2 (IRQ_26 / IRQ_32)
1159 .long __und_svc @ 3 (SVC_26 / SVC_32)
1160 .long __und_invalid @ 4
1161 .long __und_invalid @ 5
1162 .long __und_invalid @ 6
1163 .long __und_invalid @ 7
1164 .long __und_invalid @ 8
1165 .long __und_invalid @ 9
1166 .long __und_invalid @ a
1167 .long __und_invalid @ b
1168 .long __und_invalid @ c
1169 .long __und_invalid @ d
1170 .long __und_invalid @ e
1171 .long __und_invalid @ f
1172
1173 .align 5
1174
1175/*=============================================================================
1176 * Address exception handler
1177 *-----------------------------------------------------------------------------
1178 * These aren't too critical.
1179 * (they're not supposed to happen, and won't happen in 32-bit data mode).
1180 */
1181
1182vector_addrexcptn:
1183 b vector_addrexcptn
1184
1185/*=============================================================================
1186 * FIQ "NMI" handler
1187 *-----------------------------------------------------------------------------
1188 * Handle a FIQ using the SVC stack allowing FIQ act like NMI on x86
1189 * systems.
1190 */
1191 vector_stub fiq, FIQ_MODE, 4
1192
1193 .long __fiq_usr @ 0 (USR_26 / USR_32)
1194 .long __fiq_svc @ 1 (FIQ_26 / FIQ_32)
1195 .long __fiq_svc @ 2 (IRQ_26 / IRQ_32)
1196 .long __fiq_svc @ 3 (SVC_26 / SVC_32)
1197 .long __fiq_svc @ 4
1198 .long __fiq_svc @ 5
1199 .long __fiq_svc @ 6
1200 .long __fiq_abt @ 7
1201 .long __fiq_svc @ 8
1202 .long __fiq_svc @ 9
1203 .long __fiq_svc @ a
1204 .long __fiq_svc @ b
1205 .long __fiq_svc @ c
1206 .long __fiq_svc @ d
1207 .long __fiq_svc @ e
1208 .long __fiq_svc @ f
1209
1210 .globl vector_fiq
1211
1212 .section .vectors, "ax", %progbits
1213.L__vectors_start:
1214 W(b) vector_rst
1215 W(b) vector_und
1216 W(ldr) pc, .L__vectors_start + 0x1000
1217 W(b) vector_pabt
1218 W(b) vector_dabt
1219 W(b) vector_addrexcptn
1220 W(b) vector_irq
1221 W(b) vector_fiq
1222
1223 .data
1224 .align 2
1225
1226 .globl cr_alignment
1227cr_alignment:
1228 .space 4
1229
1230#ifdef CONFIG_MULTI_IRQ_HANDLER
1231 .globl handle_arch_irq
1232handle_arch_irq:
1233 .space 4
1234#endif