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1/*
2 * linux/arch/arm/kernel/entry-armv.S
3 *
4 * Copyright (C) 1996,1997,1998 Russell King.
5 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk)
6 * nommu support by Hyok S. Choi (hyok.choi@samsung.com)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Low-level vector interface routines
13 *
14 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction
15 * that causes it to save wrong values... Be aware!
16 */
17
18#include <linux/init.h>
19
20#include <asm/assembler.h>
21#include <asm/memory.h>
22#include <asm/glue-df.h>
23#include <asm/glue-pf.h>
24#include <asm/vfpmacros.h>
25#ifndef CONFIG_MULTI_IRQ_HANDLER
26#include <mach/entry-macro.S>
27#endif
28#include <asm/thread_notify.h>
29#include <asm/unwind.h>
30#include <asm/unistd.h>
31#include <asm/tls.h>
32#include <asm/system_info.h>
33
34#include "entry-header.S"
35#include <asm/entry-macro-multi.S>
36#include <asm/probes.h>
37
38/*
39 * Interrupt handling.
40 */
41 .macro irq_handler
42#ifdef CONFIG_MULTI_IRQ_HANDLER
43 ldr r1, =handle_arch_irq
44 mov r0, sp
45 badr lr, 9997f
46 ldr pc, [r1]
47#else
48 arch_irq_handler_default
49#endif
509997:
51 .endm
52
53 .macro pabt_helper
54 @ PABORT handler takes pt_regs in r2, fault address in r4 and psr in r5
55#ifdef MULTI_PABORT
56 ldr ip, .LCprocfns
57 mov lr, pc
58 ldr pc, [ip, #PROCESSOR_PABT_FUNC]
59#else
60 bl CPU_PABORT_HANDLER
61#endif
62 .endm
63
64 .macro dabt_helper
65
66 @
67 @ Call the processor-specific abort handler:
68 @
69 @ r2 - pt_regs
70 @ r4 - aborted context pc
71 @ r5 - aborted context psr
72 @
73 @ The abort handler must return the aborted address in r0, and
74 @ the fault status register in r1. r9 must be preserved.
75 @
76#ifdef MULTI_DABORT
77 ldr ip, .LCprocfns
78 mov lr, pc
79 ldr pc, [ip, #PROCESSOR_DABT_FUNC]
80#else
81 bl CPU_DABORT_HANDLER
82#endif
83 .endm
84
85#ifdef CONFIG_KPROBES
86 .section .kprobes.text,"ax",%progbits
87#else
88 .text
89#endif
90
91/*
92 * Invalid mode handlers
93 */
94 .macro inv_entry, reason
95 sub sp, sp, #S_FRAME_SIZE
96 ARM( stmib sp, {r1 - lr} )
97 THUMB( stmia sp, {r0 - r12} )
98 THUMB( str sp, [sp, #S_SP] )
99 THUMB( str lr, [sp, #S_LR] )
100 mov r1, #\reason
101 .endm
102
103__pabt_invalid:
104 inv_entry BAD_PREFETCH
105 b common_invalid
106ENDPROC(__pabt_invalid)
107
108__dabt_invalid:
109 inv_entry BAD_DATA
110 b common_invalid
111ENDPROC(__dabt_invalid)
112
113__irq_invalid:
114 inv_entry BAD_IRQ
115 b common_invalid
116ENDPROC(__irq_invalid)
117
118__und_invalid:
119 inv_entry BAD_UNDEFINSTR
120
121 @
122 @ XXX fall through to common_invalid
123 @
124
125@
126@ common_invalid - generic code for failed exception (re-entrant version of handlers)
127@
128common_invalid:
129 zero_fp
130
131 ldmia r0, {r4 - r6}
132 add r0, sp, #S_PC @ here for interlock avoidance
133 mov r7, #-1 @ "" "" "" ""
134 str r4, [sp] @ save preserved r0
135 stmia r0, {r5 - r7} @ lr_<exception>,
136 @ cpsr_<exception>, "old_r0"
137
138 mov r0, sp
139 b bad_mode
140ENDPROC(__und_invalid)
141
142/*
143 * SVC mode handlers
144 */
145
146#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
147#define SPFIX(code...) code
148#else
149#define SPFIX(code...)
150#endif
151
152 .macro svc_entry, stack_hole=0, trace=1, uaccess=1
153 UNWIND(.fnstart )
154 UNWIND(.save {r0 - pc} )
155 sub sp, sp, #(S_FRAME_SIZE + 8 + \stack_hole - 4)
156#ifdef CONFIG_THUMB2_KERNEL
157 SPFIX( str r0, [sp] ) @ temporarily saved
158 SPFIX( mov r0, sp )
159 SPFIX( tst r0, #4 ) @ test original stack alignment
160 SPFIX( ldr r0, [sp] ) @ restored
161#else
162 SPFIX( tst sp, #4 )
163#endif
164 SPFIX( subeq sp, sp, #4 )
165 stmia sp, {r1 - r12}
166
167 ldmia r0, {r3 - r5}
168 add r7, sp, #S_SP - 4 @ here for interlock avoidance
169 mov r6, #-1 @ "" "" "" ""
170 add r2, sp, #(S_FRAME_SIZE + 8 + \stack_hole - 4)
171 SPFIX( addeq r2, r2, #4 )
172 str r3, [sp, #-4]! @ save the "real" r0 copied
173 @ from the exception stack
174
175 mov r3, lr
176
177 @
178 @ We are now ready to fill in the remaining blanks on the stack:
179 @
180 @ r2 - sp_svc
181 @ r3 - lr_svc
182 @ r4 - lr_<exception>, already fixed up for correct return/restart
183 @ r5 - spsr_<exception>
184 @ r6 - orig_r0 (see pt_regs definition in ptrace.h)
185 @
186 stmia r7, {r2 - r6}
187
188 uaccess_save r0
189 .if \uaccess
190 uaccess_disable r0
191 .endif
192
193 .if \trace
194#ifdef CONFIG_TRACE_IRQFLAGS
195 bl trace_hardirqs_off
196#endif
197 .endif
198 .endm
199
200 .align 5
201__dabt_svc:
202 svc_entry uaccess=0
203 mov r2, sp
204 dabt_helper
205 THUMB( ldr r5, [sp, #S_PSR] ) @ potentially updated CPSR
206 svc_exit r5 @ return from exception
207 UNWIND(.fnend )
208ENDPROC(__dabt_svc)
209
210 .align 5
211__irq_svc:
212 svc_entry
213 irq_handler
214
215#ifdef CONFIG_PREEMPT
216 get_thread_info tsk
217 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
218 ldr r0, [tsk, #TI_FLAGS] @ get flags
219 teq r8, #0 @ if preempt count != 0
220 movne r0, #0 @ force flags to 0
221 tst r0, #_TIF_NEED_RESCHED
222 blne svc_preempt
223#endif
224
225 svc_exit r5, irq = 1 @ return from exception
226 UNWIND(.fnend )
227ENDPROC(__irq_svc)
228
229 .ltorg
230
231#ifdef CONFIG_PREEMPT
232svc_preempt:
233 mov r8, lr
2341: bl preempt_schedule_irq @ irq en/disable is done inside
235 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS
236 tst r0, #_TIF_NEED_RESCHED
237 reteq r8 @ go again
238 b 1b
239#endif
240
241__und_fault:
242 @ Correct the PC such that it is pointing at the instruction
243 @ which caused the fault. If the faulting instruction was ARM
244 @ the PC will be pointing at the next instruction, and have to
245 @ subtract 4. Otherwise, it is Thumb, and the PC will be
246 @ pointing at the second half of the Thumb instruction. We
247 @ have to subtract 2.
248 ldr r2, [r0, #S_PC]
249 sub r2, r2, r1
250 str r2, [r0, #S_PC]
251 b do_undefinstr
252ENDPROC(__und_fault)
253
254 .align 5
255__und_svc:
256#ifdef CONFIG_KPROBES
257 @ If a kprobe is about to simulate a "stmdb sp..." instruction,
258 @ it obviously needs free stack space which then will belong to
259 @ the saved context.
260 svc_entry MAX_STACK_SIZE
261#else
262 svc_entry
263#endif
264 @
265 @ call emulation code, which returns using r9 if it has emulated
266 @ the instruction, or the more conventional lr if we are to treat
267 @ this as a real undefined instruction
268 @
269 @ r0 - instruction
270 @
271#ifndef CONFIG_THUMB2_KERNEL
272 ldr r0, [r4, #-4]
273#else
274 mov r1, #2
275 ldrh r0, [r4, #-2] @ Thumb instruction at LR - 2
276 cmp r0, #0xe800 @ 32-bit instruction if xx >= 0
277 blo __und_svc_fault
278 ldrh r9, [r4] @ bottom 16 bits
279 add r4, r4, #2
280 str r4, [sp, #S_PC]
281 orr r0, r9, r0, lsl #16
282#endif
283 badr r9, __und_svc_finish
284 mov r2, r4
285 bl call_fpe
286
287 mov r1, #4 @ PC correction to apply
288__und_svc_fault:
289 mov r0, sp @ struct pt_regs *regs
290 bl __und_fault
291
292__und_svc_finish:
293 ldr r5, [sp, #S_PSR] @ Get SVC cpsr
294 svc_exit r5 @ return from exception
295 UNWIND(.fnend )
296ENDPROC(__und_svc)
297
298 .align 5
299__pabt_svc:
300 svc_entry
301 mov r2, sp @ regs
302 pabt_helper
303 svc_exit r5 @ return from exception
304 UNWIND(.fnend )
305ENDPROC(__pabt_svc)
306
307 .align 5
308__fiq_svc:
309 svc_entry trace=0
310 mov r0, sp @ struct pt_regs *regs
311 bl handle_fiq_as_nmi
312 svc_exit_via_fiq
313 UNWIND(.fnend )
314ENDPROC(__fiq_svc)
315
316 .align 5
317.LCcralign:
318 .word cr_alignment
319#ifdef MULTI_DABORT
320.LCprocfns:
321 .word processor
322#endif
323.LCfp:
324 .word fp_enter
325
326/*
327 * Abort mode handlers
328 */
329
330@
331@ Taking a FIQ in abort mode is similar to taking a FIQ in SVC mode
332@ and reuses the same macros. However in abort mode we must also
333@ save/restore lr_abt and spsr_abt to make nested aborts safe.
334@
335 .align 5
336__fiq_abt:
337 svc_entry trace=0
338
339 ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
340 THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
341 THUMB( msr cpsr_c, r0 )
342 mov r1, lr @ Save lr_abt
343 mrs r2, spsr @ Save spsr_abt, abort is now safe
344 ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
345 THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
346 THUMB( msr cpsr_c, r0 )
347 stmfd sp!, {r1 - r2}
348
349 add r0, sp, #8 @ struct pt_regs *regs
350 bl handle_fiq_as_nmi
351
352 ldmfd sp!, {r1 - r2}
353 ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
354 THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
355 THUMB( msr cpsr_c, r0 )
356 mov lr, r1 @ Restore lr_abt, abort is unsafe
357 msr spsr_cxsf, r2 @ Restore spsr_abt
358 ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
359 THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
360 THUMB( msr cpsr_c, r0 )
361
362 svc_exit_via_fiq
363 UNWIND(.fnend )
364ENDPROC(__fiq_abt)
365
366/*
367 * User mode handlers
368 *
369 * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE
370 */
371
372#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7)
373#error "sizeof(struct pt_regs) must be a multiple of 8"
374#endif
375
376 .macro usr_entry, trace=1, uaccess=1
377 UNWIND(.fnstart )
378 UNWIND(.cantunwind ) @ don't unwind the user space
379 sub sp, sp, #S_FRAME_SIZE
380 ARM( stmib sp, {r1 - r12} )
381 THUMB( stmia sp, {r0 - r12} )
382
383 ATRAP( mrc p15, 0, r7, c1, c0, 0)
384 ATRAP( ldr r8, .LCcralign)
385
386 ldmia r0, {r3 - r5}
387 add r0, sp, #S_PC @ here for interlock avoidance
388 mov r6, #-1 @ "" "" "" ""
389
390 str r3, [sp] @ save the "real" r0 copied
391 @ from the exception stack
392
393 ATRAP( ldr r8, [r8, #0])
394
395 @
396 @ We are now ready to fill in the remaining blanks on the stack:
397 @
398 @ r4 - lr_<exception>, already fixed up for correct return/restart
399 @ r5 - spsr_<exception>
400 @ r6 - orig_r0 (see pt_regs definition in ptrace.h)
401 @
402 @ Also, separately save sp_usr and lr_usr
403 @
404 stmia r0, {r4 - r6}
405 ARM( stmdb r0, {sp, lr}^ )
406 THUMB( store_user_sp_lr r0, r1, S_SP - S_PC )
407
408 .if \uaccess
409 uaccess_disable ip
410 .endif
411
412 @ Enable the alignment trap while in kernel mode
413 ATRAP( teq r8, r7)
414 ATRAP( mcrne p15, 0, r8, c1, c0, 0)
415
416 @
417 @ Clear FP to mark the first stack frame
418 @
419 zero_fp
420
421 .if \trace
422#ifdef CONFIG_TRACE_IRQFLAGS
423 bl trace_hardirqs_off
424#endif
425 ct_user_exit save = 0
426 .endif
427 .endm
428
429 .macro kuser_cmpxchg_check
430#if !defined(CONFIG_CPU_32v6K) && defined(CONFIG_KUSER_HELPERS)
431#ifndef CONFIG_MMU
432#warning "NPTL on non MMU needs fixing"
433#else
434 @ Make sure our user space atomic helper is restarted
435 @ if it was interrupted in a critical region. Here we
436 @ perform a quick test inline since it should be false
437 @ 99.9999% of the time. The rest is done out of line.
438 cmp r4, #TASK_SIZE
439 blhs kuser_cmpxchg64_fixup
440#endif
441#endif
442 .endm
443
444 .align 5
445__dabt_usr:
446 usr_entry uaccess=0
447 kuser_cmpxchg_check
448 mov r2, sp
449 dabt_helper
450 b ret_from_exception
451 UNWIND(.fnend )
452ENDPROC(__dabt_usr)
453
454 .align 5
455__irq_usr:
456 usr_entry
457 kuser_cmpxchg_check
458 irq_handler
459 get_thread_info tsk
460 mov why, #0
461 b ret_to_user_from_irq
462 UNWIND(.fnend )
463ENDPROC(__irq_usr)
464
465 .ltorg
466
467 .align 5
468__und_usr:
469 usr_entry uaccess=0
470
471 mov r2, r4
472 mov r3, r5
473
474 @ r2 = regs->ARM_pc, which is either 2 or 4 bytes ahead of the
475 @ faulting instruction depending on Thumb mode.
476 @ r3 = regs->ARM_cpsr
477 @
478 @ The emulation code returns using r9 if it has emulated the
479 @ instruction, or the more conventional lr if we are to treat
480 @ this as a real undefined instruction
481 @
482 badr r9, ret_from_exception
483
484 @ IRQs must be enabled before attempting to read the instruction from
485 @ user space since that could cause a page/translation fault if the
486 @ page table was modified by another CPU.
487 enable_irq
488
489 tst r3, #PSR_T_BIT @ Thumb mode?
490 bne __und_usr_thumb
491 sub r4, r2, #4 @ ARM instr at LR - 4
4921: ldrt r0, [r4]
493 ARM_BE8(rev r0, r0) @ little endian instruction
494
495 uaccess_disable ip
496
497 @ r0 = 32-bit ARM instruction which caused the exception
498 @ r2 = PC value for the following instruction (:= regs->ARM_pc)
499 @ r4 = PC value for the faulting instruction
500 @ lr = 32-bit undefined instruction function
501 badr lr, __und_usr_fault_32
502 b call_fpe
503
504__und_usr_thumb:
505 @ Thumb instruction
506 sub r4, r2, #2 @ First half of thumb instr at LR - 2
507#if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7
508/*
509 * Thumb-2 instruction handling. Note that because pre-v6 and >= v6 platforms
510 * can never be supported in a single kernel, this code is not applicable at
511 * all when __LINUX_ARM_ARCH__ < 6. This allows simplifying assumptions to be
512 * made about .arch directives.
513 */
514#if __LINUX_ARM_ARCH__ < 7
515/* If the target CPU may not be Thumb-2-capable, a run-time check is needed: */
516#define NEED_CPU_ARCHITECTURE
517 ldr r5, .LCcpu_architecture
518 ldr r5, [r5]
519 cmp r5, #CPU_ARCH_ARMv7
520 blo __und_usr_fault_16 @ 16bit undefined instruction
521/*
522 * The following code won't get run unless the running CPU really is v7, so
523 * coding round the lack of ldrht on older arches is pointless. Temporarily
524 * override the assembler target arch with the minimum required instead:
525 */
526 .arch armv6t2
527#endif
5282: ldrht r5, [r4]
529ARM_BE8(rev16 r5, r5) @ little endian instruction
530 cmp r5, #0xe800 @ 32bit instruction if xx != 0
531 blo __und_usr_fault_16_pan @ 16bit undefined instruction
5323: ldrht r0, [r2]
533ARM_BE8(rev16 r0, r0) @ little endian instruction
534 uaccess_disable ip
535 add r2, r2, #2 @ r2 is PC + 2, make it PC + 4
536 str r2, [sp, #S_PC] @ it's a 2x16bit instr, update
537 orr r0, r0, r5, lsl #16
538 badr lr, __und_usr_fault_32
539 @ r0 = the two 16-bit Thumb instructions which caused the exception
540 @ r2 = PC value for the following Thumb instruction (:= regs->ARM_pc)
541 @ r4 = PC value for the first 16-bit Thumb instruction
542 @ lr = 32bit undefined instruction function
543
544#if __LINUX_ARM_ARCH__ < 7
545/* If the target arch was overridden, change it back: */
546#ifdef CONFIG_CPU_32v6K
547 .arch armv6k
548#else
549 .arch armv6
550#endif
551#endif /* __LINUX_ARM_ARCH__ < 7 */
552#else /* !(CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7) */
553 b __und_usr_fault_16
554#endif
555 UNWIND(.fnend)
556ENDPROC(__und_usr)
557
558/*
559 * The out of line fixup for the ldrt instructions above.
560 */
561 .pushsection .text.fixup, "ax"
562 .align 2
5634: str r4, [sp, #S_PC] @ retry current instruction
564 ret r9
565 .popsection
566 .pushsection __ex_table,"a"
567 .long 1b, 4b
568#if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7
569 .long 2b, 4b
570 .long 3b, 4b
571#endif
572 .popsection
573
574/*
575 * Check whether the instruction is a co-processor instruction.
576 * If yes, we need to call the relevant co-processor handler.
577 *
578 * Note that we don't do a full check here for the co-processor
579 * instructions; all instructions with bit 27 set are well
580 * defined. The only instructions that should fault are the
581 * co-processor instructions. However, we have to watch out
582 * for the ARM6/ARM7 SWI bug.
583 *
584 * NEON is a special case that has to be handled here. Not all
585 * NEON instructions are co-processor instructions, so we have
586 * to make a special case of checking for them. Plus, there's
587 * five groups of them, so we have a table of mask/opcode pairs
588 * to check against, and if any match then we branch off into the
589 * NEON handler code.
590 *
591 * Emulators may wish to make use of the following registers:
592 * r0 = instruction opcode (32-bit ARM or two 16-bit Thumb)
593 * r2 = PC value to resume execution after successful emulation
594 * r9 = normal "successful" return address
595 * r10 = this threads thread_info structure
596 * lr = unrecognised instruction return address
597 * IRQs enabled, FIQs enabled.
598 */
599 @
600 @ Fall-through from Thumb-2 __und_usr
601 @
602#ifdef CONFIG_NEON
603 get_thread_info r10 @ get current thread
604 adr r6, .LCneon_thumb_opcodes
605 b 2f
606#endif
607call_fpe:
608 get_thread_info r10 @ get current thread
609#ifdef CONFIG_NEON
610 adr r6, .LCneon_arm_opcodes
6112: ldr r5, [r6], #4 @ mask value
612 ldr r7, [r6], #4 @ opcode bits matching in mask
613 cmp r5, #0 @ end mask?
614 beq 1f
615 and r8, r0, r5
616 cmp r8, r7 @ NEON instruction?
617 bne 2b
618 mov r7, #1
619 strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used
620 strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used
621 b do_vfp @ let VFP handler handle this
6221:
623#endif
624 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
625 tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2
626 reteq lr
627 and r8, r0, #0x00000f00 @ mask out CP number
628 THUMB( lsr r8, r8, #8 )
629 mov r7, #1
630 add r6, r10, #TI_USED_CP
631 ARM( strb r7, [r6, r8, lsr #8] ) @ set appropriate used_cp[]
632 THUMB( strb r7, [r6, r8] ) @ set appropriate used_cp[]
633#ifdef CONFIG_IWMMXT
634 @ Test if we need to give access to iWMMXt coprocessors
635 ldr r5, [r10, #TI_FLAGS]
636 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only
637 movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1)
638 bcs iwmmxt_task_enable
639#endif
640 ARM( add pc, pc, r8, lsr #6 )
641 THUMB( lsl r8, r8, #2 )
642 THUMB( add pc, r8 )
643 nop
644
645 ret.w lr @ CP#0
646 W(b) do_fpe @ CP#1 (FPE)
647 W(b) do_fpe @ CP#2 (FPE)
648 ret.w lr @ CP#3
649#ifdef CONFIG_CRUNCH
650 b crunch_task_enable @ CP#4 (MaverickCrunch)
651 b crunch_task_enable @ CP#5 (MaverickCrunch)
652 b crunch_task_enable @ CP#6 (MaverickCrunch)
653#else
654 ret.w lr @ CP#4
655 ret.w lr @ CP#5
656 ret.w lr @ CP#6
657#endif
658 ret.w lr @ CP#7
659 ret.w lr @ CP#8
660 ret.w lr @ CP#9
661#ifdef CONFIG_VFP
662 W(b) do_vfp @ CP#10 (VFP)
663 W(b) do_vfp @ CP#11 (VFP)
664#else
665 ret.w lr @ CP#10 (VFP)
666 ret.w lr @ CP#11 (VFP)
667#endif
668 ret.w lr @ CP#12
669 ret.w lr @ CP#13
670 ret.w lr @ CP#14 (Debug)
671 ret.w lr @ CP#15 (Control)
672
673#ifdef NEED_CPU_ARCHITECTURE
674 .align 2
675.LCcpu_architecture:
676 .word __cpu_architecture
677#endif
678
679#ifdef CONFIG_NEON
680 .align 6
681
682.LCneon_arm_opcodes:
683 .word 0xfe000000 @ mask
684 .word 0xf2000000 @ opcode
685
686 .word 0xff100000 @ mask
687 .word 0xf4000000 @ opcode
688
689 .word 0x00000000 @ mask
690 .word 0x00000000 @ opcode
691
692.LCneon_thumb_opcodes:
693 .word 0xef000000 @ mask
694 .word 0xef000000 @ opcode
695
696 .word 0xff100000 @ mask
697 .word 0xf9000000 @ opcode
698
699 .word 0x00000000 @ mask
700 .word 0x00000000 @ opcode
701#endif
702
703do_fpe:
704 ldr r4, .LCfp
705 add r10, r10, #TI_FPSTATE @ r10 = workspace
706 ldr pc, [r4] @ Call FP module USR entry point
707
708/*
709 * The FP module is called with these registers set:
710 * r0 = instruction
711 * r2 = PC+4
712 * r9 = normal "successful" return address
713 * r10 = FP workspace
714 * lr = unrecognised FP instruction return address
715 */
716
717 .pushsection .data
718ENTRY(fp_enter)
719 .word no_fp
720 .popsection
721
722ENTRY(no_fp)
723 ret lr
724ENDPROC(no_fp)
725
726__und_usr_fault_32:
727 mov r1, #4
728 b 1f
729__und_usr_fault_16_pan:
730 uaccess_disable ip
731__und_usr_fault_16:
732 mov r1, #2
7331: mov r0, sp
734 badr lr, ret_from_exception
735 b __und_fault
736ENDPROC(__und_usr_fault_32)
737ENDPROC(__und_usr_fault_16)
738
739 .align 5
740__pabt_usr:
741 usr_entry
742 mov r2, sp @ regs
743 pabt_helper
744 UNWIND(.fnend )
745 /* fall through */
746/*
747 * This is the return code to user mode for abort handlers
748 */
749ENTRY(ret_from_exception)
750 UNWIND(.fnstart )
751 UNWIND(.cantunwind )
752 get_thread_info tsk
753 mov why, #0
754 b ret_to_user
755 UNWIND(.fnend )
756ENDPROC(__pabt_usr)
757ENDPROC(ret_from_exception)
758
759 .align 5
760__fiq_usr:
761 usr_entry trace=0
762 kuser_cmpxchg_check
763 mov r0, sp @ struct pt_regs *regs
764 bl handle_fiq_as_nmi
765 get_thread_info tsk
766 restore_user_regs fast = 0, offset = 0
767 UNWIND(.fnend )
768ENDPROC(__fiq_usr)
769
770/*
771 * Register switch for ARMv3 and ARMv4 processors
772 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
773 * previous and next are guaranteed not to be the same.
774 */
775ENTRY(__switch_to)
776 UNWIND(.fnstart )
777 UNWIND(.cantunwind )
778 add ip, r1, #TI_CPU_SAVE
779 ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack
780 THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack
781 THUMB( str sp, [ip], #4 )
782 THUMB( str lr, [ip], #4 )
783 ldr r4, [r2, #TI_TP_VALUE]
784 ldr r5, [r2, #TI_TP_VALUE + 4]
785#ifdef CONFIG_CPU_USE_DOMAINS
786 mrc p15, 0, r6, c3, c0, 0 @ Get domain register
787 str r6, [r1, #TI_CPU_DOMAIN] @ Save old domain register
788 ldr r6, [r2, #TI_CPU_DOMAIN]
789#endif
790 switch_tls r1, r4, r5, r3, r7
791#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
792 ldr r7, [r2, #TI_TASK]
793 ldr r8, =__stack_chk_guard
794 ldr r7, [r7, #TSK_STACK_CANARY]
795#endif
796#ifdef CONFIG_CPU_USE_DOMAINS
797 mcr p15, 0, r6, c3, c0, 0 @ Set domain register
798#endif
799 mov r5, r0
800 add r4, r2, #TI_CPU_SAVE
801 ldr r0, =thread_notify_head
802 mov r1, #THREAD_NOTIFY_SWITCH
803 bl atomic_notifier_call_chain
804#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
805 str r7, [r8]
806#endif
807 THUMB( mov ip, r4 )
808 mov r0, r5
809 ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously
810 THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously
811 THUMB( ldr sp, [ip], #4 )
812 THUMB( ldr pc, [ip] )
813 UNWIND(.fnend )
814ENDPROC(__switch_to)
815
816 __INIT
817
818/*
819 * User helpers.
820 *
821 * Each segment is 32-byte aligned and will be moved to the top of the high
822 * vector page. New segments (if ever needed) must be added in front of
823 * existing ones. This mechanism should be used only for things that are
824 * really small and justified, and not be abused freely.
825 *
826 * See Documentation/arm/kernel_user_helpers.txt for formal definitions.
827 */
828 THUMB( .arm )
829
830 .macro usr_ret, reg
831#ifdef CONFIG_ARM_THUMB
832 bx \reg
833#else
834 ret \reg
835#endif
836 .endm
837
838 .macro kuser_pad, sym, size
839 .if (. - \sym) & 3
840 .rept 4 - (. - \sym) & 3
841 .byte 0
842 .endr
843 .endif
844 .rept (\size - (. - \sym)) / 4
845 .word 0xe7fddef1
846 .endr
847 .endm
848
849#ifdef CONFIG_KUSER_HELPERS
850 .align 5
851 .globl __kuser_helper_start
852__kuser_helper_start:
853
854/*
855 * Due to the length of some sequences, __kuser_cmpxchg64 spans 2 regular
856 * kuser "slots", therefore 0xffff0f80 is not used as a valid entry point.
857 */
858
859__kuser_cmpxchg64: @ 0xffff0f60
860
861#if defined(CONFIG_CPU_32v6K)
862
863 stmfd sp!, {r4, r5, r6, r7}
864 ldrd r4, r5, [r0] @ load old val
865 ldrd r6, r7, [r1] @ load new val
866 smp_dmb arm
8671: ldrexd r0, r1, [r2] @ load current val
868 eors r3, r0, r4 @ compare with oldval (1)
869 eoreqs r3, r1, r5 @ compare with oldval (2)
870 strexdeq r3, r6, r7, [r2] @ store newval if eq
871 teqeq r3, #1 @ success?
872 beq 1b @ if no then retry
873 smp_dmb arm
874 rsbs r0, r3, #0 @ set returned val and C flag
875 ldmfd sp!, {r4, r5, r6, r7}
876 usr_ret lr
877
878#elif !defined(CONFIG_SMP)
879
880#ifdef CONFIG_MMU
881
882 /*
883 * The only thing that can break atomicity in this cmpxchg64
884 * implementation is either an IRQ or a data abort exception
885 * causing another process/thread to be scheduled in the middle of
886 * the critical sequence. The same strategy as for cmpxchg is used.
887 */
888 stmfd sp!, {r4, r5, r6, lr}
889 ldmia r0, {r4, r5} @ load old val
890 ldmia r1, {r6, lr} @ load new val
8911: ldmia r2, {r0, r1} @ load current val
892 eors r3, r0, r4 @ compare with oldval (1)
893 eoreqs r3, r1, r5 @ compare with oldval (2)
8942: stmeqia r2, {r6, lr} @ store newval if eq
895 rsbs r0, r3, #0 @ set return val and C flag
896 ldmfd sp!, {r4, r5, r6, pc}
897
898 .text
899kuser_cmpxchg64_fixup:
900 @ Called from kuser_cmpxchg_fixup.
901 @ r4 = address of interrupted insn (must be preserved).
902 @ sp = saved regs. r7 and r8 are clobbered.
903 @ 1b = first critical insn, 2b = last critical insn.
904 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b.
905 mov r7, #0xffff0fff
906 sub r7, r7, #(0xffff0fff - (0xffff0f60 + (1b - __kuser_cmpxchg64)))
907 subs r8, r4, r7
908 rsbcss r8, r8, #(2b - 1b)
909 strcs r7, [sp, #S_PC]
910#if __LINUX_ARM_ARCH__ < 6
911 bcc kuser_cmpxchg32_fixup
912#endif
913 ret lr
914 .previous
915
916#else
917#warning "NPTL on non MMU needs fixing"
918 mov r0, #-1
919 adds r0, r0, #0
920 usr_ret lr
921#endif
922
923#else
924#error "incoherent kernel configuration"
925#endif
926
927 kuser_pad __kuser_cmpxchg64, 64
928
929__kuser_memory_barrier: @ 0xffff0fa0
930 smp_dmb arm
931 usr_ret lr
932
933 kuser_pad __kuser_memory_barrier, 32
934
935__kuser_cmpxchg: @ 0xffff0fc0
936
937#if __LINUX_ARM_ARCH__ < 6
938
939#ifdef CONFIG_MMU
940
941 /*
942 * The only thing that can break atomicity in this cmpxchg
943 * implementation is either an IRQ or a data abort exception
944 * causing another process/thread to be scheduled in the middle
945 * of the critical sequence. To prevent this, code is added to
946 * the IRQ and data abort exception handlers to set the pc back
947 * to the beginning of the critical section if it is found to be
948 * within that critical section (see kuser_cmpxchg_fixup).
949 */
9501: ldr r3, [r2] @ load current val
951 subs r3, r3, r0 @ compare with oldval
9522: streq r1, [r2] @ store newval if eq
953 rsbs r0, r3, #0 @ set return val and C flag
954 usr_ret lr
955
956 .text
957kuser_cmpxchg32_fixup:
958 @ Called from kuser_cmpxchg_check macro.
959 @ r4 = address of interrupted insn (must be preserved).
960 @ sp = saved regs. r7 and r8 are clobbered.
961 @ 1b = first critical insn, 2b = last critical insn.
962 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b.
963 mov r7, #0xffff0fff
964 sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg)))
965 subs r8, r4, r7
966 rsbcss r8, r8, #(2b - 1b)
967 strcs r7, [sp, #S_PC]
968 ret lr
969 .previous
970
971#else
972#warning "NPTL on non MMU needs fixing"
973 mov r0, #-1
974 adds r0, r0, #0
975 usr_ret lr
976#endif
977
978#else
979
980 smp_dmb arm
9811: ldrex r3, [r2]
982 subs r3, r3, r0
983 strexeq r3, r1, [r2]
984 teqeq r3, #1
985 beq 1b
986 rsbs r0, r3, #0
987 /* beware -- each __kuser slot must be 8 instructions max */
988 ALT_SMP(b __kuser_memory_barrier)
989 ALT_UP(usr_ret lr)
990
991#endif
992
993 kuser_pad __kuser_cmpxchg, 32
994
995__kuser_get_tls: @ 0xffff0fe0
996 ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init
997 usr_ret lr
998 mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code
999 kuser_pad __kuser_get_tls, 16
1000 .rep 3
1001 .word 0 @ 0xffff0ff0 software TLS value, then
1002 .endr @ pad up to __kuser_helper_version
1003
1004__kuser_helper_version: @ 0xffff0ffc
1005 .word ((__kuser_helper_end - __kuser_helper_start) >> 5)
1006
1007 .globl __kuser_helper_end
1008__kuser_helper_end:
1009
1010#endif
1011
1012 THUMB( .thumb )
1013
1014/*
1015 * Vector stubs.
1016 *
1017 * This code is copied to 0xffff1000 so we can use branches in the
1018 * vectors, rather than ldr's. Note that this code must not exceed
1019 * a page size.
1020 *
1021 * Common stub entry macro:
1022 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1023 *
1024 * SP points to a minimal amount of processor-private memory, the address
1025 * of which is copied into r0 for the mode specific abort handler.
1026 */
1027 .macro vector_stub, name, mode, correction=0
1028 .align 5
1029
1030vector_\name:
1031 .if \correction
1032 sub lr, lr, #\correction
1033 .endif
1034
1035 @
1036 @ Save r0, lr_<exception> (parent PC) and spsr_<exception>
1037 @ (parent CPSR)
1038 @
1039 stmia sp, {r0, lr} @ save r0, lr
1040 mrs lr, spsr
1041 str lr, [sp, #8] @ save spsr
1042
1043 @
1044 @ Prepare for SVC32 mode. IRQs remain disabled.
1045 @
1046 mrs r0, cpsr
1047 eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE)
1048 msr spsr_cxsf, r0
1049
1050 @
1051 @ the branch table must immediately follow this code
1052 @
1053 and lr, lr, #0x0f
1054 THUMB( adr r0, 1f )
1055 THUMB( ldr lr, [r0, lr, lsl #2] )
1056 mov r0, sp
1057 ARM( ldr lr, [pc, lr, lsl #2] )
1058 movs pc, lr @ branch to handler in SVC mode
1059ENDPROC(vector_\name)
1060
1061 .align 2
1062 @ handler addresses follow this label
10631:
1064 .endm
1065
1066 .section .stubs, "ax", %progbits
1067 @ This must be the first word
1068 .word vector_swi
1069
1070vector_rst:
1071 ARM( swi SYS_ERROR0 )
1072 THUMB( svc #0 )
1073 THUMB( nop )
1074 b vector_und
1075
1076/*
1077 * Interrupt dispatcher
1078 */
1079 vector_stub irq, IRQ_MODE, 4
1080
1081 .long __irq_usr @ 0 (USR_26 / USR_32)
1082 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32)
1083 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32)
1084 .long __irq_svc @ 3 (SVC_26 / SVC_32)
1085 .long __irq_invalid @ 4
1086 .long __irq_invalid @ 5
1087 .long __irq_invalid @ 6
1088 .long __irq_invalid @ 7
1089 .long __irq_invalid @ 8
1090 .long __irq_invalid @ 9
1091 .long __irq_invalid @ a
1092 .long __irq_invalid @ b
1093 .long __irq_invalid @ c
1094 .long __irq_invalid @ d
1095 .long __irq_invalid @ e
1096 .long __irq_invalid @ f
1097
1098/*
1099 * Data abort dispatcher
1100 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1101 */
1102 vector_stub dabt, ABT_MODE, 8
1103
1104 .long __dabt_usr @ 0 (USR_26 / USR_32)
1105 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32)
1106 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32)
1107 .long __dabt_svc @ 3 (SVC_26 / SVC_32)
1108 .long __dabt_invalid @ 4
1109 .long __dabt_invalid @ 5
1110 .long __dabt_invalid @ 6
1111 .long __dabt_invalid @ 7
1112 .long __dabt_invalid @ 8
1113 .long __dabt_invalid @ 9
1114 .long __dabt_invalid @ a
1115 .long __dabt_invalid @ b
1116 .long __dabt_invalid @ c
1117 .long __dabt_invalid @ d
1118 .long __dabt_invalid @ e
1119 .long __dabt_invalid @ f
1120
1121/*
1122 * Prefetch abort dispatcher
1123 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1124 */
1125 vector_stub pabt, ABT_MODE, 4
1126
1127 .long __pabt_usr @ 0 (USR_26 / USR_32)
1128 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32)
1129 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32)
1130 .long __pabt_svc @ 3 (SVC_26 / SVC_32)
1131 .long __pabt_invalid @ 4
1132 .long __pabt_invalid @ 5
1133 .long __pabt_invalid @ 6
1134 .long __pabt_invalid @ 7
1135 .long __pabt_invalid @ 8
1136 .long __pabt_invalid @ 9
1137 .long __pabt_invalid @ a
1138 .long __pabt_invalid @ b
1139 .long __pabt_invalid @ c
1140 .long __pabt_invalid @ d
1141 .long __pabt_invalid @ e
1142 .long __pabt_invalid @ f
1143
1144/*
1145 * Undef instr entry dispatcher
1146 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1147 */
1148 vector_stub und, UND_MODE
1149
1150 .long __und_usr @ 0 (USR_26 / USR_32)
1151 .long __und_invalid @ 1 (FIQ_26 / FIQ_32)
1152 .long __und_invalid @ 2 (IRQ_26 / IRQ_32)
1153 .long __und_svc @ 3 (SVC_26 / SVC_32)
1154 .long __und_invalid @ 4
1155 .long __und_invalid @ 5
1156 .long __und_invalid @ 6
1157 .long __und_invalid @ 7
1158 .long __und_invalid @ 8
1159 .long __und_invalid @ 9
1160 .long __und_invalid @ a
1161 .long __und_invalid @ b
1162 .long __und_invalid @ c
1163 .long __und_invalid @ d
1164 .long __und_invalid @ e
1165 .long __und_invalid @ f
1166
1167 .align 5
1168
1169/*=============================================================================
1170 * Address exception handler
1171 *-----------------------------------------------------------------------------
1172 * These aren't too critical.
1173 * (they're not supposed to happen, and won't happen in 32-bit data mode).
1174 */
1175
1176vector_addrexcptn:
1177 b vector_addrexcptn
1178
1179/*=============================================================================
1180 * FIQ "NMI" handler
1181 *-----------------------------------------------------------------------------
1182 * Handle a FIQ using the SVC stack allowing FIQ act like NMI on x86
1183 * systems.
1184 */
1185 vector_stub fiq, FIQ_MODE, 4
1186
1187 .long __fiq_usr @ 0 (USR_26 / USR_32)
1188 .long __fiq_svc @ 1 (FIQ_26 / FIQ_32)
1189 .long __fiq_svc @ 2 (IRQ_26 / IRQ_32)
1190 .long __fiq_svc @ 3 (SVC_26 / SVC_32)
1191 .long __fiq_svc @ 4
1192 .long __fiq_svc @ 5
1193 .long __fiq_svc @ 6
1194 .long __fiq_abt @ 7
1195 .long __fiq_svc @ 8
1196 .long __fiq_svc @ 9
1197 .long __fiq_svc @ a
1198 .long __fiq_svc @ b
1199 .long __fiq_svc @ c
1200 .long __fiq_svc @ d
1201 .long __fiq_svc @ e
1202 .long __fiq_svc @ f
1203
1204 .globl vector_fiq
1205
1206 .section .vectors, "ax", %progbits
1207.L__vectors_start:
1208 W(b) vector_rst
1209 W(b) vector_und
1210 W(ldr) pc, .L__vectors_start + 0x1000
1211 W(b) vector_pabt
1212 W(b) vector_dabt
1213 W(b) vector_addrexcptn
1214 W(b) vector_irq
1215 W(b) vector_fiq
1216
1217 .data
1218
1219 .globl cr_alignment
1220cr_alignment:
1221 .space 4
1222
1223#ifdef CONFIG_MULTI_IRQ_HANDLER
1224 .globl handle_arch_irq
1225handle_arch_irq:
1226 .space 4
1227#endif
1/*
2 * linux/arch/arm/kernel/entry-armv.S
3 *
4 * Copyright (C) 1996,1997,1998 Russell King.
5 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk)
6 * nommu support by Hyok S. Choi (hyok.choi@samsung.com)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Low-level vector interface routines
13 *
14 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction
15 * that causes it to save wrong values... Be aware!
16 */
17
18#include <asm/assembler.h>
19#include <asm/memory.h>
20#include <asm/glue-df.h>
21#include <asm/glue-pf.h>
22#include <asm/vfpmacros.h>
23#ifndef CONFIG_MULTI_IRQ_HANDLER
24#include <mach/entry-macro.S>
25#endif
26#include <asm/thread_notify.h>
27#include <asm/unwind.h>
28#include <asm/unistd.h>
29#include <asm/tls.h>
30#include <asm/system_info.h>
31
32#include "entry-header.S"
33#include <asm/entry-macro-multi.S>
34
35/*
36 * Interrupt handling.
37 */
38 .macro irq_handler
39#ifdef CONFIG_MULTI_IRQ_HANDLER
40 ldr r1, =handle_arch_irq
41 mov r0, sp
42 adr lr, BSYM(9997f)
43 ldr pc, [r1]
44#else
45 arch_irq_handler_default
46#endif
479997:
48 .endm
49
50 .macro pabt_helper
51 @ PABORT handler takes pt_regs in r2, fault address in r4 and psr in r5
52#ifdef MULTI_PABORT
53 ldr ip, .LCprocfns
54 mov lr, pc
55 ldr pc, [ip, #PROCESSOR_PABT_FUNC]
56#else
57 bl CPU_PABORT_HANDLER
58#endif
59 .endm
60
61 .macro dabt_helper
62
63 @
64 @ Call the processor-specific abort handler:
65 @
66 @ r2 - pt_regs
67 @ r4 - aborted context pc
68 @ r5 - aborted context psr
69 @
70 @ The abort handler must return the aborted address in r0, and
71 @ the fault status register in r1. r9 must be preserved.
72 @
73#ifdef MULTI_DABORT
74 ldr ip, .LCprocfns
75 mov lr, pc
76 ldr pc, [ip, #PROCESSOR_DABT_FUNC]
77#else
78 bl CPU_DABORT_HANDLER
79#endif
80 .endm
81
82#ifdef CONFIG_KPROBES
83 .section .kprobes.text,"ax",%progbits
84#else
85 .text
86#endif
87
88/*
89 * Invalid mode handlers
90 */
91 .macro inv_entry, reason
92 sub sp, sp, #S_FRAME_SIZE
93 ARM( stmib sp, {r1 - lr} )
94 THUMB( stmia sp, {r0 - r12} )
95 THUMB( str sp, [sp, #S_SP] )
96 THUMB( str lr, [sp, #S_LR] )
97 mov r1, #\reason
98 .endm
99
100__pabt_invalid:
101 inv_entry BAD_PREFETCH
102 b common_invalid
103ENDPROC(__pabt_invalid)
104
105__dabt_invalid:
106 inv_entry BAD_DATA
107 b common_invalid
108ENDPROC(__dabt_invalid)
109
110__irq_invalid:
111 inv_entry BAD_IRQ
112 b common_invalid
113ENDPROC(__irq_invalid)
114
115__und_invalid:
116 inv_entry BAD_UNDEFINSTR
117
118 @
119 @ XXX fall through to common_invalid
120 @
121
122@
123@ common_invalid - generic code for failed exception (re-entrant version of handlers)
124@
125common_invalid:
126 zero_fp
127
128 ldmia r0, {r4 - r6}
129 add r0, sp, #S_PC @ here for interlock avoidance
130 mov r7, #-1 @ "" "" "" ""
131 str r4, [sp] @ save preserved r0
132 stmia r0, {r5 - r7} @ lr_<exception>,
133 @ cpsr_<exception>, "old_r0"
134
135 mov r0, sp
136 b bad_mode
137ENDPROC(__und_invalid)
138
139/*
140 * SVC mode handlers
141 */
142
143#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
144#define SPFIX(code...) code
145#else
146#define SPFIX(code...)
147#endif
148
149 .macro svc_entry, stack_hole=0
150 UNWIND(.fnstart )
151 UNWIND(.save {r0 - pc} )
152 sub sp, sp, #(S_FRAME_SIZE + \stack_hole - 4)
153#ifdef CONFIG_THUMB2_KERNEL
154 SPFIX( str r0, [sp] ) @ temporarily saved
155 SPFIX( mov r0, sp )
156 SPFIX( tst r0, #4 ) @ test original stack alignment
157 SPFIX( ldr r0, [sp] ) @ restored
158#else
159 SPFIX( tst sp, #4 )
160#endif
161 SPFIX( subeq sp, sp, #4 )
162 stmia sp, {r1 - r12}
163
164 ldmia r0, {r3 - r5}
165 add r7, sp, #S_SP - 4 @ here for interlock avoidance
166 mov r6, #-1 @ "" "" "" ""
167 add r2, sp, #(S_FRAME_SIZE + \stack_hole - 4)
168 SPFIX( addeq r2, r2, #4 )
169 str r3, [sp, #-4]! @ save the "real" r0 copied
170 @ from the exception stack
171
172 mov r3, lr
173
174 @
175 @ We are now ready to fill in the remaining blanks on the stack:
176 @
177 @ r2 - sp_svc
178 @ r3 - lr_svc
179 @ r4 - lr_<exception>, already fixed up for correct return/restart
180 @ r5 - spsr_<exception>
181 @ r6 - orig_r0 (see pt_regs definition in ptrace.h)
182 @
183 stmia r7, {r2 - r6}
184
185#ifdef CONFIG_TRACE_IRQFLAGS
186 bl trace_hardirqs_off
187#endif
188 .endm
189
190 .align 5
191__dabt_svc:
192 svc_entry
193 mov r2, sp
194 dabt_helper
195 THUMB( ldr r5, [sp, #S_PSR] ) @ potentially updated CPSR
196 svc_exit r5 @ return from exception
197 UNWIND(.fnend )
198ENDPROC(__dabt_svc)
199
200 .align 5
201__irq_svc:
202 svc_entry
203 irq_handler
204
205#ifdef CONFIG_PREEMPT
206 get_thread_info tsk
207 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
208 ldr r0, [tsk, #TI_FLAGS] @ get flags
209 teq r8, #0 @ if preempt count != 0
210 movne r0, #0 @ force flags to 0
211 tst r0, #_TIF_NEED_RESCHED
212 blne svc_preempt
213#endif
214
215 svc_exit r5, irq = 1 @ return from exception
216 UNWIND(.fnend )
217ENDPROC(__irq_svc)
218
219 .ltorg
220
221#ifdef CONFIG_PREEMPT
222svc_preempt:
223 mov r8, lr
2241: bl preempt_schedule_irq @ irq en/disable is done inside
225 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS
226 tst r0, #_TIF_NEED_RESCHED
227 moveq pc, r8 @ go again
228 b 1b
229#endif
230
231__und_fault:
232 @ Correct the PC such that it is pointing at the instruction
233 @ which caused the fault. If the faulting instruction was ARM
234 @ the PC will be pointing at the next instruction, and have to
235 @ subtract 4. Otherwise, it is Thumb, and the PC will be
236 @ pointing at the second half of the Thumb instruction. We
237 @ have to subtract 2.
238 ldr r2, [r0, #S_PC]
239 sub r2, r2, r1
240 str r2, [r0, #S_PC]
241 b do_undefinstr
242ENDPROC(__und_fault)
243
244 .align 5
245__und_svc:
246#ifdef CONFIG_KPROBES
247 @ If a kprobe is about to simulate a "stmdb sp..." instruction,
248 @ it obviously needs free stack space which then will belong to
249 @ the saved context.
250 svc_entry 64
251#else
252 svc_entry
253#endif
254 @
255 @ call emulation code, which returns using r9 if it has emulated
256 @ the instruction, or the more conventional lr if we are to treat
257 @ this as a real undefined instruction
258 @
259 @ r0 - instruction
260 @
261#ifndef CONFIG_THUMB2_KERNEL
262 ldr r0, [r4, #-4]
263#else
264 mov r1, #2
265 ldrh r0, [r4, #-2] @ Thumb instruction at LR - 2
266 cmp r0, #0xe800 @ 32-bit instruction if xx >= 0
267 blo __und_svc_fault
268 ldrh r9, [r4] @ bottom 16 bits
269 add r4, r4, #2
270 str r4, [sp, #S_PC]
271 orr r0, r9, r0, lsl #16
272#endif
273 adr r9, BSYM(__und_svc_finish)
274 mov r2, r4
275 bl call_fpe
276
277 mov r1, #4 @ PC correction to apply
278__und_svc_fault:
279 mov r0, sp @ struct pt_regs *regs
280 bl __und_fault
281
282__und_svc_finish:
283 ldr r5, [sp, #S_PSR] @ Get SVC cpsr
284 svc_exit r5 @ return from exception
285 UNWIND(.fnend )
286ENDPROC(__und_svc)
287
288 .align 5
289__pabt_svc:
290 svc_entry
291 mov r2, sp @ regs
292 pabt_helper
293 svc_exit r5 @ return from exception
294 UNWIND(.fnend )
295ENDPROC(__pabt_svc)
296
297 .align 5
298.LCcralign:
299 .word cr_alignment
300#ifdef MULTI_DABORT
301.LCprocfns:
302 .word processor
303#endif
304.LCfp:
305 .word fp_enter
306
307/*
308 * User mode handlers
309 *
310 * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE
311 */
312
313#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7)
314#error "sizeof(struct pt_regs) must be a multiple of 8"
315#endif
316
317 .macro usr_entry
318 UNWIND(.fnstart )
319 UNWIND(.cantunwind ) @ don't unwind the user space
320 sub sp, sp, #S_FRAME_SIZE
321 ARM( stmib sp, {r1 - r12} )
322 THUMB( stmia sp, {r0 - r12} )
323
324 ldmia r0, {r3 - r5}
325 add r0, sp, #S_PC @ here for interlock avoidance
326 mov r6, #-1 @ "" "" "" ""
327
328 str r3, [sp] @ save the "real" r0 copied
329 @ from the exception stack
330
331 @
332 @ We are now ready to fill in the remaining blanks on the stack:
333 @
334 @ r4 - lr_<exception>, already fixed up for correct return/restart
335 @ r5 - spsr_<exception>
336 @ r6 - orig_r0 (see pt_regs definition in ptrace.h)
337 @
338 @ Also, separately save sp_usr and lr_usr
339 @
340 stmia r0, {r4 - r6}
341 ARM( stmdb r0, {sp, lr}^ )
342 THUMB( store_user_sp_lr r0, r1, S_SP - S_PC )
343
344 @
345 @ Enable the alignment trap while in kernel mode
346 @
347 alignment_trap r0
348
349 @
350 @ Clear FP to mark the first stack frame
351 @
352 zero_fp
353
354#ifdef CONFIG_IRQSOFF_TRACER
355 bl trace_hardirqs_off
356#endif
357 ct_user_exit save = 0
358 .endm
359
360 .macro kuser_cmpxchg_check
361#if !defined(CONFIG_CPU_32v6K) && defined(CONFIG_KUSER_HELPERS) && \
362 !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
363#ifndef CONFIG_MMU
364#warning "NPTL on non MMU needs fixing"
365#else
366 @ Make sure our user space atomic helper is restarted
367 @ if it was interrupted in a critical region. Here we
368 @ perform a quick test inline since it should be false
369 @ 99.9999% of the time. The rest is done out of line.
370 cmp r4, #TASK_SIZE
371 blhs kuser_cmpxchg64_fixup
372#endif
373#endif
374 .endm
375
376 .align 5
377__dabt_usr:
378 usr_entry
379 kuser_cmpxchg_check
380 mov r2, sp
381 dabt_helper
382 b ret_from_exception
383 UNWIND(.fnend )
384ENDPROC(__dabt_usr)
385
386 .align 5
387__irq_usr:
388 usr_entry
389 kuser_cmpxchg_check
390 irq_handler
391 get_thread_info tsk
392 mov why, #0
393 b ret_to_user_from_irq
394 UNWIND(.fnend )
395ENDPROC(__irq_usr)
396
397 .ltorg
398
399 .align 5
400__und_usr:
401 usr_entry
402
403 mov r2, r4
404 mov r3, r5
405
406 @ r2 = regs->ARM_pc, which is either 2 or 4 bytes ahead of the
407 @ faulting instruction depending on Thumb mode.
408 @ r3 = regs->ARM_cpsr
409 @
410 @ The emulation code returns using r9 if it has emulated the
411 @ instruction, or the more conventional lr if we are to treat
412 @ this as a real undefined instruction
413 @
414 adr r9, BSYM(ret_from_exception)
415
416 tst r3, #PSR_T_BIT @ Thumb mode?
417 bne __und_usr_thumb
418 sub r4, r2, #4 @ ARM instr at LR - 4
4191: ldrt r0, [r4]
420 ARM_BE8(rev r0, r0) @ little endian instruction
421
422 @ r0 = 32-bit ARM instruction which caused the exception
423 @ r2 = PC value for the following instruction (:= regs->ARM_pc)
424 @ r4 = PC value for the faulting instruction
425 @ lr = 32-bit undefined instruction function
426 adr lr, BSYM(__und_usr_fault_32)
427 b call_fpe
428
429__und_usr_thumb:
430 @ Thumb instruction
431 sub r4, r2, #2 @ First half of thumb instr at LR - 2
432#if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7
433/*
434 * Thumb-2 instruction handling. Note that because pre-v6 and >= v6 platforms
435 * can never be supported in a single kernel, this code is not applicable at
436 * all when __LINUX_ARM_ARCH__ < 6. This allows simplifying assumptions to be
437 * made about .arch directives.
438 */
439#if __LINUX_ARM_ARCH__ < 7
440/* If the target CPU may not be Thumb-2-capable, a run-time check is needed: */
441#define NEED_CPU_ARCHITECTURE
442 ldr r5, .LCcpu_architecture
443 ldr r5, [r5]
444 cmp r5, #CPU_ARCH_ARMv7
445 blo __und_usr_fault_16 @ 16bit undefined instruction
446/*
447 * The following code won't get run unless the running CPU really is v7, so
448 * coding round the lack of ldrht on older arches is pointless. Temporarily
449 * override the assembler target arch with the minimum required instead:
450 */
451 .arch armv6t2
452#endif
4532: ldrht r5, [r4]
454ARM_BE8(rev16 r5, r5) @ little endian instruction
455 cmp r5, #0xe800 @ 32bit instruction if xx != 0
456 blo __und_usr_fault_16 @ 16bit undefined instruction
4573: ldrht r0, [r2]
458ARM_BE8(rev16 r0, r0) @ little endian instruction
459 add r2, r2, #2 @ r2 is PC + 2, make it PC + 4
460 str r2, [sp, #S_PC] @ it's a 2x16bit instr, update
461 orr r0, r0, r5, lsl #16
462 adr lr, BSYM(__und_usr_fault_32)
463 @ r0 = the two 16-bit Thumb instructions which caused the exception
464 @ r2 = PC value for the following Thumb instruction (:= regs->ARM_pc)
465 @ r4 = PC value for the first 16-bit Thumb instruction
466 @ lr = 32bit undefined instruction function
467
468#if __LINUX_ARM_ARCH__ < 7
469/* If the target arch was overridden, change it back: */
470#ifdef CONFIG_CPU_32v6K
471 .arch armv6k
472#else
473 .arch armv6
474#endif
475#endif /* __LINUX_ARM_ARCH__ < 7 */
476#else /* !(CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7) */
477 b __und_usr_fault_16
478#endif
479 UNWIND(.fnend)
480ENDPROC(__und_usr)
481
482/*
483 * The out of line fixup for the ldrt instructions above.
484 */
485 .pushsection .fixup, "ax"
486 .align 2
4874: mov pc, r9
488 .popsection
489 .pushsection __ex_table,"a"
490 .long 1b, 4b
491#if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7
492 .long 2b, 4b
493 .long 3b, 4b
494#endif
495 .popsection
496
497/*
498 * Check whether the instruction is a co-processor instruction.
499 * If yes, we need to call the relevant co-processor handler.
500 *
501 * Note that we don't do a full check here for the co-processor
502 * instructions; all instructions with bit 27 set are well
503 * defined. The only instructions that should fault are the
504 * co-processor instructions. However, we have to watch out
505 * for the ARM6/ARM7 SWI bug.
506 *
507 * NEON is a special case that has to be handled here. Not all
508 * NEON instructions are co-processor instructions, so we have
509 * to make a special case of checking for them. Plus, there's
510 * five groups of them, so we have a table of mask/opcode pairs
511 * to check against, and if any match then we branch off into the
512 * NEON handler code.
513 *
514 * Emulators may wish to make use of the following registers:
515 * r0 = instruction opcode (32-bit ARM or two 16-bit Thumb)
516 * r2 = PC value to resume execution after successful emulation
517 * r9 = normal "successful" return address
518 * r10 = this threads thread_info structure
519 * lr = unrecognised instruction return address
520 * IRQs disabled, FIQs enabled.
521 */
522 @
523 @ Fall-through from Thumb-2 __und_usr
524 @
525#ifdef CONFIG_NEON
526 get_thread_info r10 @ get current thread
527 adr r6, .LCneon_thumb_opcodes
528 b 2f
529#endif
530call_fpe:
531 get_thread_info r10 @ get current thread
532#ifdef CONFIG_NEON
533 adr r6, .LCneon_arm_opcodes
5342: ldr r5, [r6], #4 @ mask value
535 ldr r7, [r6], #4 @ opcode bits matching in mask
536 cmp r5, #0 @ end mask?
537 beq 1f
538 and r8, r0, r5
539 cmp r8, r7 @ NEON instruction?
540 bne 2b
541 mov r7, #1
542 strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used
543 strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used
544 b do_vfp @ let VFP handler handle this
5451:
546#endif
547 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
548 tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2
549 moveq pc, lr
550 and r8, r0, #0x00000f00 @ mask out CP number
551 THUMB( lsr r8, r8, #8 )
552 mov r7, #1
553 add r6, r10, #TI_USED_CP
554 ARM( strb r7, [r6, r8, lsr #8] ) @ set appropriate used_cp[]
555 THUMB( strb r7, [r6, r8] ) @ set appropriate used_cp[]
556#ifdef CONFIG_IWMMXT
557 @ Test if we need to give access to iWMMXt coprocessors
558 ldr r5, [r10, #TI_FLAGS]
559 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only
560 movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1)
561 bcs iwmmxt_task_enable
562#endif
563 ARM( add pc, pc, r8, lsr #6 )
564 THUMB( lsl r8, r8, #2 )
565 THUMB( add pc, r8 )
566 nop
567
568 movw_pc lr @ CP#0
569 W(b) do_fpe @ CP#1 (FPE)
570 W(b) do_fpe @ CP#2 (FPE)
571 movw_pc lr @ CP#3
572#ifdef CONFIG_CRUNCH
573 b crunch_task_enable @ CP#4 (MaverickCrunch)
574 b crunch_task_enable @ CP#5 (MaverickCrunch)
575 b crunch_task_enable @ CP#6 (MaverickCrunch)
576#else
577 movw_pc lr @ CP#4
578 movw_pc lr @ CP#5
579 movw_pc lr @ CP#6
580#endif
581 movw_pc lr @ CP#7
582 movw_pc lr @ CP#8
583 movw_pc lr @ CP#9
584#ifdef CONFIG_VFP
585 W(b) do_vfp @ CP#10 (VFP)
586 W(b) do_vfp @ CP#11 (VFP)
587#else
588 movw_pc lr @ CP#10 (VFP)
589 movw_pc lr @ CP#11 (VFP)
590#endif
591 movw_pc lr @ CP#12
592 movw_pc lr @ CP#13
593 movw_pc lr @ CP#14 (Debug)
594 movw_pc lr @ CP#15 (Control)
595
596#ifdef NEED_CPU_ARCHITECTURE
597 .align 2
598.LCcpu_architecture:
599 .word __cpu_architecture
600#endif
601
602#ifdef CONFIG_NEON
603 .align 6
604
605.LCneon_arm_opcodes:
606 .word 0xfe000000 @ mask
607 .word 0xf2000000 @ opcode
608
609 .word 0xff100000 @ mask
610 .word 0xf4000000 @ opcode
611
612 .word 0x00000000 @ mask
613 .word 0x00000000 @ opcode
614
615.LCneon_thumb_opcodes:
616 .word 0xef000000 @ mask
617 .word 0xef000000 @ opcode
618
619 .word 0xff100000 @ mask
620 .word 0xf9000000 @ opcode
621
622 .word 0x00000000 @ mask
623 .word 0x00000000 @ opcode
624#endif
625
626do_fpe:
627 enable_irq
628 ldr r4, .LCfp
629 add r10, r10, #TI_FPSTATE @ r10 = workspace
630 ldr pc, [r4] @ Call FP module USR entry point
631
632/*
633 * The FP module is called with these registers set:
634 * r0 = instruction
635 * r2 = PC+4
636 * r9 = normal "successful" return address
637 * r10 = FP workspace
638 * lr = unrecognised FP instruction return address
639 */
640
641 .pushsection .data
642ENTRY(fp_enter)
643 .word no_fp
644 .popsection
645
646ENTRY(no_fp)
647 mov pc, lr
648ENDPROC(no_fp)
649
650__und_usr_fault_32:
651 mov r1, #4
652 b 1f
653__und_usr_fault_16:
654 mov r1, #2
6551: enable_irq
656 mov r0, sp
657 adr lr, BSYM(ret_from_exception)
658 b __und_fault
659ENDPROC(__und_usr_fault_32)
660ENDPROC(__und_usr_fault_16)
661
662 .align 5
663__pabt_usr:
664 usr_entry
665 mov r2, sp @ regs
666 pabt_helper
667 UNWIND(.fnend )
668 /* fall through */
669/*
670 * This is the return code to user mode for abort handlers
671 */
672ENTRY(ret_from_exception)
673 UNWIND(.fnstart )
674 UNWIND(.cantunwind )
675 get_thread_info tsk
676 mov why, #0
677 b ret_to_user
678 UNWIND(.fnend )
679ENDPROC(__pabt_usr)
680ENDPROC(ret_from_exception)
681
682/*
683 * Register switch for ARMv3 and ARMv4 processors
684 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
685 * previous and next are guaranteed not to be the same.
686 */
687ENTRY(__switch_to)
688 UNWIND(.fnstart )
689 UNWIND(.cantunwind )
690 add ip, r1, #TI_CPU_SAVE
691 ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack
692 THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack
693 THUMB( str sp, [ip], #4 )
694 THUMB( str lr, [ip], #4 )
695 ldr r4, [r2, #TI_TP_VALUE]
696 ldr r5, [r2, #TI_TP_VALUE + 4]
697#ifdef CONFIG_CPU_USE_DOMAINS
698 ldr r6, [r2, #TI_CPU_DOMAIN]
699#endif
700 switch_tls r1, r4, r5, r3, r7
701#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
702 ldr r7, [r2, #TI_TASK]
703 ldr r8, =__stack_chk_guard
704 ldr r7, [r7, #TSK_STACK_CANARY]
705#endif
706#ifdef CONFIG_CPU_USE_DOMAINS
707 mcr p15, 0, r6, c3, c0, 0 @ Set domain register
708#endif
709 mov r5, r0
710 add r4, r2, #TI_CPU_SAVE
711 ldr r0, =thread_notify_head
712 mov r1, #THREAD_NOTIFY_SWITCH
713 bl atomic_notifier_call_chain
714#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
715 str r7, [r8]
716#endif
717 THUMB( mov ip, r4 )
718 mov r0, r5
719 ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously
720 THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously
721 THUMB( ldr sp, [ip], #4 )
722 THUMB( ldr pc, [ip] )
723 UNWIND(.fnend )
724ENDPROC(__switch_to)
725
726 __INIT
727
728/*
729 * User helpers.
730 *
731 * Each segment is 32-byte aligned and will be moved to the top of the high
732 * vector page. New segments (if ever needed) must be added in front of
733 * existing ones. This mechanism should be used only for things that are
734 * really small and justified, and not be abused freely.
735 *
736 * See Documentation/arm/kernel_user_helpers.txt for formal definitions.
737 */
738 THUMB( .arm )
739
740 .macro usr_ret, reg
741#ifdef CONFIG_ARM_THUMB
742 bx \reg
743#else
744 mov pc, \reg
745#endif
746 .endm
747
748 .macro kuser_pad, sym, size
749 .if (. - \sym) & 3
750 .rept 4 - (. - \sym) & 3
751 .byte 0
752 .endr
753 .endif
754 .rept (\size - (. - \sym)) / 4
755 .word 0xe7fddef1
756 .endr
757 .endm
758
759#ifdef CONFIG_KUSER_HELPERS
760 .align 5
761 .globl __kuser_helper_start
762__kuser_helper_start:
763
764/*
765 * Due to the length of some sequences, __kuser_cmpxchg64 spans 2 regular
766 * kuser "slots", therefore 0xffff0f80 is not used as a valid entry point.
767 */
768
769__kuser_cmpxchg64: @ 0xffff0f60
770
771#if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
772
773 /*
774 * Poor you. No fast solution possible...
775 * The kernel itself must perform the operation.
776 * A special ghost syscall is used for that (see traps.c).
777 */
778 stmfd sp!, {r7, lr}
779 ldr r7, 1f @ it's 20 bits
780 swi __ARM_NR_cmpxchg64
781 ldmfd sp!, {r7, pc}
7821: .word __ARM_NR_cmpxchg64
783
784#elif defined(CONFIG_CPU_32v6K)
785
786 stmfd sp!, {r4, r5, r6, r7}
787 ldrd r4, r5, [r0] @ load old val
788 ldrd r6, r7, [r1] @ load new val
789 smp_dmb arm
7901: ldrexd r0, r1, [r2] @ load current val
791 eors r3, r0, r4 @ compare with oldval (1)
792 eoreqs r3, r1, r5 @ compare with oldval (2)
793 strexdeq r3, r6, r7, [r2] @ store newval if eq
794 teqeq r3, #1 @ success?
795 beq 1b @ if no then retry
796 smp_dmb arm
797 rsbs r0, r3, #0 @ set returned val and C flag
798 ldmfd sp!, {r4, r5, r6, r7}
799 usr_ret lr
800
801#elif !defined(CONFIG_SMP)
802
803#ifdef CONFIG_MMU
804
805 /*
806 * The only thing that can break atomicity in this cmpxchg64
807 * implementation is either an IRQ or a data abort exception
808 * causing another process/thread to be scheduled in the middle of
809 * the critical sequence. The same strategy as for cmpxchg is used.
810 */
811 stmfd sp!, {r4, r5, r6, lr}
812 ldmia r0, {r4, r5} @ load old val
813 ldmia r1, {r6, lr} @ load new val
8141: ldmia r2, {r0, r1} @ load current val
815 eors r3, r0, r4 @ compare with oldval (1)
816 eoreqs r3, r1, r5 @ compare with oldval (2)
8172: stmeqia r2, {r6, lr} @ store newval if eq
818 rsbs r0, r3, #0 @ set return val and C flag
819 ldmfd sp!, {r4, r5, r6, pc}
820
821 .text
822kuser_cmpxchg64_fixup:
823 @ Called from kuser_cmpxchg_fixup.
824 @ r4 = address of interrupted insn (must be preserved).
825 @ sp = saved regs. r7 and r8 are clobbered.
826 @ 1b = first critical insn, 2b = last critical insn.
827 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b.
828 mov r7, #0xffff0fff
829 sub r7, r7, #(0xffff0fff - (0xffff0f60 + (1b - __kuser_cmpxchg64)))
830 subs r8, r4, r7
831 rsbcss r8, r8, #(2b - 1b)
832 strcs r7, [sp, #S_PC]
833#if __LINUX_ARM_ARCH__ < 6
834 bcc kuser_cmpxchg32_fixup
835#endif
836 mov pc, lr
837 .previous
838
839#else
840#warning "NPTL on non MMU needs fixing"
841 mov r0, #-1
842 adds r0, r0, #0
843 usr_ret lr
844#endif
845
846#else
847#error "incoherent kernel configuration"
848#endif
849
850 kuser_pad __kuser_cmpxchg64, 64
851
852__kuser_memory_barrier: @ 0xffff0fa0
853 smp_dmb arm
854 usr_ret lr
855
856 kuser_pad __kuser_memory_barrier, 32
857
858__kuser_cmpxchg: @ 0xffff0fc0
859
860#if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
861
862 /*
863 * Poor you. No fast solution possible...
864 * The kernel itself must perform the operation.
865 * A special ghost syscall is used for that (see traps.c).
866 */
867 stmfd sp!, {r7, lr}
868 ldr r7, 1f @ it's 20 bits
869 swi __ARM_NR_cmpxchg
870 ldmfd sp!, {r7, pc}
8711: .word __ARM_NR_cmpxchg
872
873#elif __LINUX_ARM_ARCH__ < 6
874
875#ifdef CONFIG_MMU
876
877 /*
878 * The only thing that can break atomicity in this cmpxchg
879 * implementation is either an IRQ or a data abort exception
880 * causing another process/thread to be scheduled in the middle
881 * of the critical sequence. To prevent this, code is added to
882 * the IRQ and data abort exception handlers to set the pc back
883 * to the beginning of the critical section if it is found to be
884 * within that critical section (see kuser_cmpxchg_fixup).
885 */
8861: ldr r3, [r2] @ load current val
887 subs r3, r3, r0 @ compare with oldval
8882: streq r1, [r2] @ store newval if eq
889 rsbs r0, r3, #0 @ set return val and C flag
890 usr_ret lr
891
892 .text
893kuser_cmpxchg32_fixup:
894 @ Called from kuser_cmpxchg_check macro.
895 @ r4 = address of interrupted insn (must be preserved).
896 @ sp = saved regs. r7 and r8 are clobbered.
897 @ 1b = first critical insn, 2b = last critical insn.
898 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b.
899 mov r7, #0xffff0fff
900 sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg)))
901 subs r8, r4, r7
902 rsbcss r8, r8, #(2b - 1b)
903 strcs r7, [sp, #S_PC]
904 mov pc, lr
905 .previous
906
907#else
908#warning "NPTL on non MMU needs fixing"
909 mov r0, #-1
910 adds r0, r0, #0
911 usr_ret lr
912#endif
913
914#else
915
916 smp_dmb arm
9171: ldrex r3, [r2]
918 subs r3, r3, r0
919 strexeq r3, r1, [r2]
920 teqeq r3, #1
921 beq 1b
922 rsbs r0, r3, #0
923 /* beware -- each __kuser slot must be 8 instructions max */
924 ALT_SMP(b __kuser_memory_barrier)
925 ALT_UP(usr_ret lr)
926
927#endif
928
929 kuser_pad __kuser_cmpxchg, 32
930
931__kuser_get_tls: @ 0xffff0fe0
932 ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init
933 usr_ret lr
934 mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code
935 kuser_pad __kuser_get_tls, 16
936 .rep 3
937 .word 0 @ 0xffff0ff0 software TLS value, then
938 .endr @ pad up to __kuser_helper_version
939
940__kuser_helper_version: @ 0xffff0ffc
941 .word ((__kuser_helper_end - __kuser_helper_start) >> 5)
942
943 .globl __kuser_helper_end
944__kuser_helper_end:
945
946#endif
947
948 THUMB( .thumb )
949
950/*
951 * Vector stubs.
952 *
953 * This code is copied to 0xffff1000 so we can use branches in the
954 * vectors, rather than ldr's. Note that this code must not exceed
955 * a page size.
956 *
957 * Common stub entry macro:
958 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
959 *
960 * SP points to a minimal amount of processor-private memory, the address
961 * of which is copied into r0 for the mode specific abort handler.
962 */
963 .macro vector_stub, name, mode, correction=0
964 .align 5
965
966vector_\name:
967 .if \correction
968 sub lr, lr, #\correction
969 .endif
970
971 @
972 @ Save r0, lr_<exception> (parent PC) and spsr_<exception>
973 @ (parent CPSR)
974 @
975 stmia sp, {r0, lr} @ save r0, lr
976 mrs lr, spsr
977 str lr, [sp, #8] @ save spsr
978
979 @
980 @ Prepare for SVC32 mode. IRQs remain disabled.
981 @
982 mrs r0, cpsr
983 eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE)
984 msr spsr_cxsf, r0
985
986 @
987 @ the branch table must immediately follow this code
988 @
989 and lr, lr, #0x0f
990 THUMB( adr r0, 1f )
991 THUMB( ldr lr, [r0, lr, lsl #2] )
992 mov r0, sp
993 ARM( ldr lr, [pc, lr, lsl #2] )
994 movs pc, lr @ branch to handler in SVC mode
995ENDPROC(vector_\name)
996
997 .align 2
998 @ handler addresses follow this label
9991:
1000 .endm
1001
1002 .section .stubs, "ax", %progbits
1003__stubs_start:
1004 @ This must be the first word
1005 .word vector_swi
1006
1007vector_rst:
1008 ARM( swi SYS_ERROR0 )
1009 THUMB( svc #0 )
1010 THUMB( nop )
1011 b vector_und
1012
1013/*
1014 * Interrupt dispatcher
1015 */
1016 vector_stub irq, IRQ_MODE, 4
1017
1018 .long __irq_usr @ 0 (USR_26 / USR_32)
1019 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32)
1020 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32)
1021 .long __irq_svc @ 3 (SVC_26 / SVC_32)
1022 .long __irq_invalid @ 4
1023 .long __irq_invalid @ 5
1024 .long __irq_invalid @ 6
1025 .long __irq_invalid @ 7
1026 .long __irq_invalid @ 8
1027 .long __irq_invalid @ 9
1028 .long __irq_invalid @ a
1029 .long __irq_invalid @ b
1030 .long __irq_invalid @ c
1031 .long __irq_invalid @ d
1032 .long __irq_invalid @ e
1033 .long __irq_invalid @ f
1034
1035/*
1036 * Data abort dispatcher
1037 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1038 */
1039 vector_stub dabt, ABT_MODE, 8
1040
1041 .long __dabt_usr @ 0 (USR_26 / USR_32)
1042 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32)
1043 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32)
1044 .long __dabt_svc @ 3 (SVC_26 / SVC_32)
1045 .long __dabt_invalid @ 4
1046 .long __dabt_invalid @ 5
1047 .long __dabt_invalid @ 6
1048 .long __dabt_invalid @ 7
1049 .long __dabt_invalid @ 8
1050 .long __dabt_invalid @ 9
1051 .long __dabt_invalid @ a
1052 .long __dabt_invalid @ b
1053 .long __dabt_invalid @ c
1054 .long __dabt_invalid @ d
1055 .long __dabt_invalid @ e
1056 .long __dabt_invalid @ f
1057
1058/*
1059 * Prefetch abort dispatcher
1060 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1061 */
1062 vector_stub pabt, ABT_MODE, 4
1063
1064 .long __pabt_usr @ 0 (USR_26 / USR_32)
1065 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32)
1066 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32)
1067 .long __pabt_svc @ 3 (SVC_26 / SVC_32)
1068 .long __pabt_invalid @ 4
1069 .long __pabt_invalid @ 5
1070 .long __pabt_invalid @ 6
1071 .long __pabt_invalid @ 7
1072 .long __pabt_invalid @ 8
1073 .long __pabt_invalid @ 9
1074 .long __pabt_invalid @ a
1075 .long __pabt_invalid @ b
1076 .long __pabt_invalid @ c
1077 .long __pabt_invalid @ d
1078 .long __pabt_invalid @ e
1079 .long __pabt_invalid @ f
1080
1081/*
1082 * Undef instr entry dispatcher
1083 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1084 */
1085 vector_stub und, UND_MODE
1086
1087 .long __und_usr @ 0 (USR_26 / USR_32)
1088 .long __und_invalid @ 1 (FIQ_26 / FIQ_32)
1089 .long __und_invalid @ 2 (IRQ_26 / IRQ_32)
1090 .long __und_svc @ 3 (SVC_26 / SVC_32)
1091 .long __und_invalid @ 4
1092 .long __und_invalid @ 5
1093 .long __und_invalid @ 6
1094 .long __und_invalid @ 7
1095 .long __und_invalid @ 8
1096 .long __und_invalid @ 9
1097 .long __und_invalid @ a
1098 .long __und_invalid @ b
1099 .long __und_invalid @ c
1100 .long __und_invalid @ d
1101 .long __und_invalid @ e
1102 .long __und_invalid @ f
1103
1104 .align 5
1105
1106/*=============================================================================
1107 * Address exception handler
1108 *-----------------------------------------------------------------------------
1109 * These aren't too critical.
1110 * (they're not supposed to happen, and won't happen in 32-bit data mode).
1111 */
1112
1113vector_addrexcptn:
1114 b vector_addrexcptn
1115
1116/*=============================================================================
1117 * Undefined FIQs
1118 *-----------------------------------------------------------------------------
1119 * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC
1120 * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg.
1121 * Basically to switch modes, we *HAVE* to clobber one register... brain
1122 * damage alert! I don't think that we can execute any code in here in any
1123 * other mode than FIQ... Ok you can switch to another mode, but you can't
1124 * get out of that mode without clobbering one register.
1125 */
1126vector_fiq:
1127 subs pc, lr, #4
1128
1129 .globl vector_fiq_offset
1130 .equ vector_fiq_offset, vector_fiq
1131
1132 .section .vectors, "ax", %progbits
1133__vectors_start:
1134 W(b) vector_rst
1135 W(b) vector_und
1136 W(ldr) pc, __vectors_start + 0x1000
1137 W(b) vector_pabt
1138 W(b) vector_dabt
1139 W(b) vector_addrexcptn
1140 W(b) vector_irq
1141 W(b) vector_fiq
1142
1143 .data
1144
1145 .globl cr_alignment
1146 .globl cr_no_alignment
1147cr_alignment:
1148 .space 4
1149cr_no_alignment:
1150 .space 4
1151
1152#ifdef CONFIG_MULTI_IRQ_HANDLER
1153 .globl handle_arch_irq
1154handle_arch_irq:
1155 .space 4
1156#endif