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1/*
2 * Copyright (C) 2012 Texas Instruments
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#ifndef __TILCDC_DRV_H__
19#define __TILCDC_DRV_H__
20
21#include <linux/clk.h>
22#include <linux/cpufreq.h>
23#include <linux/module.h>
24#include <linux/platform_device.h>
25#include <linux/pm.h>
26#include <linux/pm_runtime.h>
27#include <linux/slab.h>
28#include <linux/of.h>
29#include <linux/of_device.h>
30#include <linux/list.h>
31
32#include <drm/drmP.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_gem_cma_helper.h>
35#include <drm/drm_fb_cma_helper.h>
36
37/* Defaulting to pixel clock defined on AM335x */
38#define TILCDC_DEFAULT_MAX_PIXELCLOCK 126000
39/* Defaulting to max width as defined on AM335x */
40#define TILCDC_DEFAULT_MAX_WIDTH 2048
41/*
42 * This may need some tweaking, but want to allow at least 1280x1024@60
43 * with optimized DDR & EMIF settings tweaked 1920x1080@24 appears to
44 * be supportable
45 */
46#define TILCDC_DEFAULT_MAX_BANDWIDTH (1280*1024*60)
47
48
49struct tilcdc_drm_private {
50 void __iomem *mmio;
51
52 struct clk *clk; /* functional clock */
53 int rev; /* IP revision */
54
55 /* don't attempt resolutions w/ higher W * H * Hz: */
56 uint32_t max_bandwidth;
57 /*
58 * Pixel Clock will be restricted to some value as
59 * defined in the device datasheet measured in KHz
60 */
61 uint32_t max_pixelclock;
62 /*
63 * Max allowable width is limited on a per device basis
64 * measured in pixels
65 */
66 uint32_t max_width;
67
68 /* register contents saved across suspend/resume: */
69 u32 *saved_register;
70 bool ctx_valid;
71
72#ifdef CONFIG_CPU_FREQ
73 struct notifier_block freq_transition;
74 unsigned int lcd_fck_rate;
75#endif
76
77 struct workqueue_struct *wq;
78
79 struct drm_fbdev_cma *fbdev;
80
81 struct drm_crtc *crtc;
82
83 unsigned int num_encoders;
84 struct drm_encoder *encoders[8];
85
86 unsigned int num_connectors;
87 struct drm_connector *connectors[8];
88 const struct drm_connector_helper_funcs *connector_funcs[8];
89
90 bool is_componentized;
91};
92
93/* Sub-module for display. Since we don't know at compile time what panels
94 * or display adapter(s) might be present (for ex, off chip dvi/tfp410,
95 * hdmi encoder, various lcd panels), the connector/encoder(s) are split into
96 * separate drivers. If they are probed and found to be present, they
97 * register themselves with tilcdc_register_module().
98 */
99struct tilcdc_module;
100
101struct tilcdc_module_ops {
102 /* create appropriate encoders/connectors: */
103 int (*modeset_init)(struct tilcdc_module *mod, struct drm_device *dev);
104#ifdef CONFIG_DEBUG_FS
105 /* create debugfs nodes (can be NULL): */
106 int (*debugfs_init)(struct tilcdc_module *mod, struct drm_minor *minor);
107 /* cleanup debugfs nodes (can be NULL): */
108 void (*debugfs_cleanup)(struct tilcdc_module *mod, struct drm_minor *minor);
109#endif
110};
111
112struct tilcdc_module {
113 const char *name;
114 struct list_head list;
115 const struct tilcdc_module_ops *funcs;
116 unsigned int preferred_bpp;
117};
118
119void tilcdc_module_init(struct tilcdc_module *mod, const char *name,
120 const struct tilcdc_module_ops *funcs);
121void tilcdc_module_cleanup(struct tilcdc_module *mod);
122
123/* Panel config that needs to be set in the crtc, but is not coming from
124 * the mode timings. The display module is expected to call
125 * tilcdc_crtc_set_panel_info() to set this during modeset.
126 */
127struct tilcdc_panel_info {
128
129 /* AC Bias Pin Frequency */
130 uint32_t ac_bias;
131
132 /* AC Bias Pin Transitions per Interrupt */
133 uint32_t ac_bias_intrpt;
134
135 /* DMA burst size */
136 uint32_t dma_burst_sz;
137
138 /* Bits per pixel */
139 uint32_t bpp;
140
141 /* FIFO DMA Request Delay */
142 uint32_t fdd;
143
144 /* TFT Alternative Signal Mapping (Only for active) */
145 bool tft_alt_mode;
146
147 /* Invert pixel clock */
148 bool invert_pxl_clk;
149
150 /* Horizontal and Vertical Sync Edge: 0=rising 1=falling */
151 uint32_t sync_edge;
152
153 /* Horizontal and Vertical Sync: Control: 0=ignore */
154 uint32_t sync_ctrl;
155
156 /* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */
157 uint32_t raster_order;
158
159 /* DMA FIFO threshold */
160 uint32_t fifo_th;
161};
162
163#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
164
165struct drm_crtc *tilcdc_crtc_create(struct drm_device *dev);
166irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc);
167void tilcdc_crtc_update_clk(struct drm_crtc *crtc);
168void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc,
169 const struct tilcdc_panel_info *info);
170void tilcdc_crtc_set_simulate_vesa_sync(struct drm_crtc *crtc,
171 bool simulate_vesa_sync);
172int tilcdc_crtc_mode_valid(struct drm_crtc *crtc, struct drm_display_mode *mode);
173int tilcdc_crtc_max_width(struct drm_crtc *crtc);
174void tilcdc_crtc_dpms(struct drm_crtc *crtc, int mode);
175
176#endif /* __TILCDC_DRV_H__ */
1/*
2 * Copyright (C) 2012 Texas Instruments
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#ifndef __TILCDC_DRV_H__
19#define __TILCDC_DRV_H__
20
21#include <linux/clk.h>
22#include <linux/cpufreq.h>
23#include <linux/module.h>
24#include <linux/platform_device.h>
25#include <linux/pm.h>
26#include <linux/pm_runtime.h>
27#include <linux/slab.h>
28#include <linux/of.h>
29#include <linux/of_device.h>
30#include <linux/list.h>
31
32#include <drm/drmP.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_gem_cma_helper.h>
35#include <drm/drm_fb_cma_helper.h>
36#include <drm/drm_bridge.h>
37
38/* Defaulting to pixel clock defined on AM335x */
39#define TILCDC_DEFAULT_MAX_PIXELCLOCK 126000
40/* Defaulting to max width as defined on AM335x */
41#define TILCDC_DEFAULT_MAX_WIDTH 2048
42/*
43 * This may need some tweaking, but want to allow at least 1280x1024@60
44 * with optimized DDR & EMIF settings tweaked 1920x1080@24 appears to
45 * be supportable
46 */
47#define TILCDC_DEFAULT_MAX_BANDWIDTH (1280*1024*60)
48
49
50struct tilcdc_drm_private {
51 void __iomem *mmio;
52
53 struct clk *clk; /* functional clock */
54 int rev; /* IP revision */
55
56 /* don't attempt resolutions w/ higher W * H * Hz: */
57 uint32_t max_bandwidth;
58 /*
59 * Pixel Clock will be restricted to some value as
60 * defined in the device datasheet measured in KHz
61 */
62 uint32_t max_pixelclock;
63 /*
64 * Max allowable width is limited on a per device basis
65 * measured in pixels
66 */
67 uint32_t max_width;
68
69 /* Supported pixel formats */
70 const uint32_t *pixelformats;
71 uint32_t num_pixelformats;
72
73 /* The context for pm susped/resume cycle is stored here */
74 struct drm_atomic_state *saved_state;
75
76#ifdef CONFIG_CPU_FREQ
77 struct notifier_block freq_transition;
78#endif
79
80 struct workqueue_struct *wq;
81
82 struct drm_crtc *crtc;
83
84 unsigned int num_encoders;
85 struct drm_encoder *encoders[8];
86
87 unsigned int num_connectors;
88 struct drm_connector *connectors[8];
89
90 struct drm_encoder *external_encoder;
91 struct drm_connector *external_connector;
92 const struct drm_connector_helper_funcs *connector_funcs;
93
94 bool is_registered;
95 bool is_componentized;
96};
97
98/* Sub-module for display. Since we don't know at compile time what panels
99 * or display adapter(s) might be present (for ex, off chip dvi/tfp410,
100 * hdmi encoder, various lcd panels), the connector/encoder(s) are split into
101 * separate drivers. If they are probed and found to be present, they
102 * register themselves with tilcdc_register_module().
103 */
104struct tilcdc_module;
105
106struct tilcdc_module_ops {
107 /* create appropriate encoders/connectors: */
108 int (*modeset_init)(struct tilcdc_module *mod, struct drm_device *dev);
109#ifdef CONFIG_DEBUG_FS
110 /* create debugfs nodes (can be NULL): */
111 int (*debugfs_init)(struct tilcdc_module *mod, struct drm_minor *minor);
112#endif
113};
114
115struct tilcdc_module {
116 const char *name;
117 struct list_head list;
118 const struct tilcdc_module_ops *funcs;
119};
120
121void tilcdc_module_init(struct tilcdc_module *mod, const char *name,
122 const struct tilcdc_module_ops *funcs);
123void tilcdc_module_cleanup(struct tilcdc_module *mod);
124
125/* Panel config that needs to be set in the crtc, but is not coming from
126 * the mode timings. The display module is expected to call
127 * tilcdc_crtc_set_panel_info() to set this during modeset.
128 */
129struct tilcdc_panel_info {
130
131 /* AC Bias Pin Frequency */
132 uint32_t ac_bias;
133
134 /* AC Bias Pin Transitions per Interrupt */
135 uint32_t ac_bias_intrpt;
136
137 /* DMA burst size */
138 uint32_t dma_burst_sz;
139
140 /* Bits per pixel */
141 uint32_t bpp;
142
143 /* FIFO DMA Request Delay */
144 uint32_t fdd;
145
146 /* TFT Alternative Signal Mapping (Only for active) */
147 bool tft_alt_mode;
148
149 /* Invert pixel clock */
150 bool invert_pxl_clk;
151
152 /* Horizontal and Vertical Sync Edge: 0=rising 1=falling */
153 uint32_t sync_edge;
154
155 /* Horizontal and Vertical Sync: Control: 0=ignore */
156 uint32_t sync_ctrl;
157
158 /* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */
159 uint32_t raster_order;
160
161 /* DMA FIFO threshold */
162 uint32_t fifo_th;
163};
164
165#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
166
167int tilcdc_crtc_create(struct drm_device *dev);
168irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc);
169void tilcdc_crtc_update_clk(struct drm_crtc *crtc);
170void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc,
171 const struct tilcdc_panel_info *info);
172void tilcdc_crtc_set_simulate_vesa_sync(struct drm_crtc *crtc,
173 bool simulate_vesa_sync);
174int tilcdc_crtc_mode_valid(struct drm_crtc *crtc, struct drm_display_mode *mode);
175int tilcdc_crtc_max_width(struct drm_crtc *crtc);
176void tilcdc_crtc_shutdown(struct drm_crtc *crtc);
177int tilcdc_crtc_update_fb(struct drm_crtc *crtc,
178 struct drm_framebuffer *fb,
179 struct drm_pending_vblank_event *event);
180
181int tilcdc_plane_init(struct drm_device *dev, struct drm_plane *plane);
182
183#endif /* __TILCDC_DRV_H__ */