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1/*
2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/clk.h>
11
12#include <drm/drm_atomic_helper.h>
13#include <drm/drm_panel.h>
14
15#include "drm.h"
16#include "dc.h"
17
18struct tegra_rgb {
19 struct tegra_output output;
20 struct tegra_dc *dc;
21
22 struct clk *clk_parent;
23 struct clk *clk;
24};
25
26static inline struct tegra_rgb *to_rgb(struct tegra_output *output)
27{
28 return container_of(output, struct tegra_rgb, output);
29}
30
31struct reg_entry {
32 unsigned long offset;
33 unsigned long value;
34};
35
36static const struct reg_entry rgb_enable[] = {
37 { DC_COM_PIN_OUTPUT_ENABLE(0), 0x00000000 },
38 { DC_COM_PIN_OUTPUT_ENABLE(1), 0x00000000 },
39 { DC_COM_PIN_OUTPUT_ENABLE(2), 0x00000000 },
40 { DC_COM_PIN_OUTPUT_ENABLE(3), 0x00000000 },
41 { DC_COM_PIN_OUTPUT_POLARITY(0), 0x00000000 },
42 { DC_COM_PIN_OUTPUT_POLARITY(1), 0x01000000 },
43 { DC_COM_PIN_OUTPUT_POLARITY(2), 0x00000000 },
44 { DC_COM_PIN_OUTPUT_POLARITY(3), 0x00000000 },
45 { DC_COM_PIN_OUTPUT_DATA(0), 0x00000000 },
46 { DC_COM_PIN_OUTPUT_DATA(1), 0x00000000 },
47 { DC_COM_PIN_OUTPUT_DATA(2), 0x00000000 },
48 { DC_COM_PIN_OUTPUT_DATA(3), 0x00000000 },
49 { DC_COM_PIN_OUTPUT_SELECT(0), 0x00000000 },
50 { DC_COM_PIN_OUTPUT_SELECT(1), 0x00000000 },
51 { DC_COM_PIN_OUTPUT_SELECT(2), 0x00000000 },
52 { DC_COM_PIN_OUTPUT_SELECT(3), 0x00000000 },
53 { DC_COM_PIN_OUTPUT_SELECT(4), 0x00210222 },
54 { DC_COM_PIN_OUTPUT_SELECT(5), 0x00002200 },
55 { DC_COM_PIN_OUTPUT_SELECT(6), 0x00020000 },
56};
57
58static const struct reg_entry rgb_disable[] = {
59 { DC_COM_PIN_OUTPUT_SELECT(6), 0x00000000 },
60 { DC_COM_PIN_OUTPUT_SELECT(5), 0x00000000 },
61 { DC_COM_PIN_OUTPUT_SELECT(4), 0x00000000 },
62 { DC_COM_PIN_OUTPUT_SELECT(3), 0x00000000 },
63 { DC_COM_PIN_OUTPUT_SELECT(2), 0x00000000 },
64 { DC_COM_PIN_OUTPUT_SELECT(1), 0x00000000 },
65 { DC_COM_PIN_OUTPUT_SELECT(0), 0x00000000 },
66 { DC_COM_PIN_OUTPUT_DATA(3), 0xaaaaaaaa },
67 { DC_COM_PIN_OUTPUT_DATA(2), 0xaaaaaaaa },
68 { DC_COM_PIN_OUTPUT_DATA(1), 0xaaaaaaaa },
69 { DC_COM_PIN_OUTPUT_DATA(0), 0xaaaaaaaa },
70 { DC_COM_PIN_OUTPUT_POLARITY(3), 0x00000000 },
71 { DC_COM_PIN_OUTPUT_POLARITY(2), 0x00000000 },
72 { DC_COM_PIN_OUTPUT_POLARITY(1), 0x00000000 },
73 { DC_COM_PIN_OUTPUT_POLARITY(0), 0x00000000 },
74 { DC_COM_PIN_OUTPUT_ENABLE(3), 0x55555555 },
75 { DC_COM_PIN_OUTPUT_ENABLE(2), 0x55555555 },
76 { DC_COM_PIN_OUTPUT_ENABLE(1), 0x55150005 },
77 { DC_COM_PIN_OUTPUT_ENABLE(0), 0x55555555 },
78};
79
80static void tegra_dc_write_regs(struct tegra_dc *dc,
81 const struct reg_entry *table,
82 unsigned int num)
83{
84 unsigned int i;
85
86 for (i = 0; i < num; i++)
87 tegra_dc_writel(dc, table[i].value, table[i].offset);
88}
89
90static const struct drm_connector_funcs tegra_rgb_connector_funcs = {
91 .dpms = drm_atomic_helper_connector_dpms,
92 .reset = drm_atomic_helper_connector_reset,
93 .detect = tegra_output_connector_detect,
94 .fill_modes = drm_helper_probe_single_connector_modes,
95 .destroy = tegra_output_connector_destroy,
96 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
97 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
98};
99
100static enum drm_mode_status
101tegra_rgb_connector_mode_valid(struct drm_connector *connector,
102 struct drm_display_mode *mode)
103{
104 /*
105 * FIXME: For now, always assume that the mode is okay. There are
106 * unresolved issues with clk_round_rate(), which doesn't always
107 * reliably report whether a frequency can be set or not.
108 */
109 return MODE_OK;
110}
111
112static const struct drm_connector_helper_funcs tegra_rgb_connector_helper_funcs = {
113 .get_modes = tegra_output_connector_get_modes,
114 .mode_valid = tegra_rgb_connector_mode_valid,
115 .best_encoder = tegra_output_connector_best_encoder,
116};
117
118static const struct drm_encoder_funcs tegra_rgb_encoder_funcs = {
119 .destroy = tegra_output_encoder_destroy,
120};
121
122static void tegra_rgb_encoder_disable(struct drm_encoder *encoder)
123{
124 struct tegra_output *output = encoder_to_output(encoder);
125 struct tegra_rgb *rgb = to_rgb(output);
126
127 if (output->panel)
128 drm_panel_disable(output->panel);
129
130 tegra_dc_write_regs(rgb->dc, rgb_disable, ARRAY_SIZE(rgb_disable));
131 tegra_dc_commit(rgb->dc);
132
133 if (output->panel)
134 drm_panel_unprepare(output->panel);
135}
136
137static void tegra_rgb_encoder_enable(struct drm_encoder *encoder)
138{
139 struct tegra_output *output = encoder_to_output(encoder);
140 struct tegra_rgb *rgb = to_rgb(output);
141 u32 value;
142
143 if (output->panel)
144 drm_panel_prepare(output->panel);
145
146 tegra_dc_write_regs(rgb->dc, rgb_enable, ARRAY_SIZE(rgb_enable));
147
148 value = DE_SELECT_ACTIVE | DE_CONTROL_NORMAL;
149 tegra_dc_writel(rgb->dc, value, DC_DISP_DATA_ENABLE_OPTIONS);
150
151 /* XXX: parameterize? */
152 value = tegra_dc_readl(rgb->dc, DC_COM_PIN_OUTPUT_POLARITY(1));
153 value &= ~LVS_OUTPUT_POLARITY_LOW;
154 value &= ~LHS_OUTPUT_POLARITY_LOW;
155 tegra_dc_writel(rgb->dc, value, DC_COM_PIN_OUTPUT_POLARITY(1));
156
157 /* XXX: parameterize? */
158 value = DISP_DATA_FORMAT_DF1P1C | DISP_ALIGNMENT_MSB |
159 DISP_ORDER_RED_BLUE;
160 tegra_dc_writel(rgb->dc, value, DC_DISP_DISP_INTERFACE_CONTROL);
161
162 /* XXX: parameterize? */
163 value = SC0_H_QUALIFIER_NONE | SC1_H_QUALIFIER_NONE;
164 tegra_dc_writel(rgb->dc, value, DC_DISP_SHIFT_CLOCK_OPTIONS);
165
166 tegra_dc_commit(rgb->dc);
167
168 if (output->panel)
169 drm_panel_enable(output->panel);
170}
171
172static int
173tegra_rgb_encoder_atomic_check(struct drm_encoder *encoder,
174 struct drm_crtc_state *crtc_state,
175 struct drm_connector_state *conn_state)
176{
177 struct tegra_output *output = encoder_to_output(encoder);
178 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
179 unsigned long pclk = crtc_state->mode.clock * 1000;
180 struct tegra_rgb *rgb = to_rgb(output);
181 unsigned int div;
182 int err;
183
184 /*
185 * We may not want to change the frequency of the parent clock, since
186 * it may be a parent for other peripherals. This is due to the fact
187 * that on Tegra20 there's only a single clock dedicated to display
188 * (pll_d_out0), whereas later generations have a second one that can
189 * be used to independently drive a second output (pll_d2_out0).
190 *
191 * As a way to support multiple outputs on Tegra20 as well, pll_p is
192 * typically used as the parent clock for the display controllers.
193 * But this comes at a cost: pll_p is the parent of several other
194 * peripherals, so its frequency shouldn't change out of the blue.
195 *
196 * The best we can do at this point is to use the shift clock divider
197 * and hope that the desired frequency can be matched (or at least
198 * matched sufficiently close that the panel will still work).
199 */
200 div = ((clk_get_rate(rgb->clk) * 2) / pclk) - 2;
201 pclk = 0;
202
203 err = tegra_dc_state_setup_clock(dc, crtc_state, rgb->clk_parent,
204 pclk, div);
205 if (err < 0) {
206 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
207 return err;
208 }
209
210 return err;
211}
212
213static const struct drm_encoder_helper_funcs tegra_rgb_encoder_helper_funcs = {
214 .disable = tegra_rgb_encoder_disable,
215 .enable = tegra_rgb_encoder_enable,
216 .atomic_check = tegra_rgb_encoder_atomic_check,
217};
218
219int tegra_dc_rgb_probe(struct tegra_dc *dc)
220{
221 struct device_node *np;
222 struct tegra_rgb *rgb;
223 int err;
224
225 np = of_get_child_by_name(dc->dev->of_node, "rgb");
226 if (!np || !of_device_is_available(np))
227 return -ENODEV;
228
229 rgb = devm_kzalloc(dc->dev, sizeof(*rgb), GFP_KERNEL);
230 if (!rgb)
231 return -ENOMEM;
232
233 rgb->output.dev = dc->dev;
234 rgb->output.of_node = np;
235 rgb->dc = dc;
236
237 err = tegra_output_probe(&rgb->output);
238 if (err < 0)
239 return err;
240
241 rgb->clk = devm_clk_get(dc->dev, NULL);
242 if (IS_ERR(rgb->clk)) {
243 dev_err(dc->dev, "failed to get clock\n");
244 return PTR_ERR(rgb->clk);
245 }
246
247 rgb->clk_parent = devm_clk_get(dc->dev, "parent");
248 if (IS_ERR(rgb->clk_parent)) {
249 dev_err(dc->dev, "failed to get parent clock\n");
250 return PTR_ERR(rgb->clk_parent);
251 }
252
253 err = clk_set_parent(rgb->clk, rgb->clk_parent);
254 if (err < 0) {
255 dev_err(dc->dev, "failed to set parent clock: %d\n", err);
256 return err;
257 }
258
259 dc->rgb = &rgb->output;
260
261 return 0;
262}
263
264int tegra_dc_rgb_remove(struct tegra_dc *dc)
265{
266 if (!dc->rgb)
267 return 0;
268
269 tegra_output_remove(dc->rgb);
270 dc->rgb = NULL;
271
272 return 0;
273}
274
275int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc)
276{
277 struct tegra_output *output = dc->rgb;
278 int err;
279
280 if (!dc->rgb)
281 return -ENODEV;
282
283 drm_connector_init(drm, &output->connector, &tegra_rgb_connector_funcs,
284 DRM_MODE_CONNECTOR_LVDS);
285 drm_connector_helper_add(&output->connector,
286 &tegra_rgb_connector_helper_funcs);
287 output->connector.dpms = DRM_MODE_DPMS_OFF;
288
289 drm_encoder_init(drm, &output->encoder, &tegra_rgb_encoder_funcs,
290 DRM_MODE_ENCODER_LVDS, NULL);
291 drm_encoder_helper_add(&output->encoder,
292 &tegra_rgb_encoder_helper_funcs);
293
294 drm_mode_connector_attach_encoder(&output->connector,
295 &output->encoder);
296 drm_connector_register(&output->connector);
297
298 err = tegra_output_init(drm, output);
299 if (err < 0) {
300 dev_err(output->dev, "failed to initialize output: %d\n", err);
301 return err;
302 }
303
304 /*
305 * Other outputs can be attached to either display controller. The RGB
306 * outputs are an exception and work only with their parent display
307 * controller.
308 */
309 output->encoder.possible_crtcs = drm_crtc_mask(&dc->base);
310
311 return 0;
312}
313
314int tegra_dc_rgb_exit(struct tegra_dc *dc)
315{
316 if (dc->rgb)
317 tegra_output_exit(dc->rgb);
318
319 return 0;
320}
1/*
2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/clk.h>
11
12#include <drm/drm_atomic_helper.h>
13#include <drm/drm_panel.h>
14
15#include "drm.h"
16#include "dc.h"
17
18struct tegra_rgb {
19 struct tegra_output output;
20 struct tegra_dc *dc;
21
22 struct clk *clk_parent;
23 struct clk *clk;
24};
25
26static inline struct tegra_rgb *to_rgb(struct tegra_output *output)
27{
28 return container_of(output, struct tegra_rgb, output);
29}
30
31struct reg_entry {
32 unsigned long offset;
33 unsigned long value;
34};
35
36static const struct reg_entry rgb_enable[] = {
37 { DC_COM_PIN_OUTPUT_ENABLE(0), 0x00000000 },
38 { DC_COM_PIN_OUTPUT_ENABLE(1), 0x00000000 },
39 { DC_COM_PIN_OUTPUT_ENABLE(2), 0x00000000 },
40 { DC_COM_PIN_OUTPUT_ENABLE(3), 0x00000000 },
41 { DC_COM_PIN_OUTPUT_POLARITY(0), 0x00000000 },
42 { DC_COM_PIN_OUTPUT_POLARITY(1), 0x01000000 },
43 { DC_COM_PIN_OUTPUT_POLARITY(2), 0x00000000 },
44 { DC_COM_PIN_OUTPUT_POLARITY(3), 0x00000000 },
45 { DC_COM_PIN_OUTPUT_DATA(0), 0x00000000 },
46 { DC_COM_PIN_OUTPUT_DATA(1), 0x00000000 },
47 { DC_COM_PIN_OUTPUT_DATA(2), 0x00000000 },
48 { DC_COM_PIN_OUTPUT_DATA(3), 0x00000000 },
49 { DC_COM_PIN_OUTPUT_SELECT(0), 0x00000000 },
50 { DC_COM_PIN_OUTPUT_SELECT(1), 0x00000000 },
51 { DC_COM_PIN_OUTPUT_SELECT(2), 0x00000000 },
52 { DC_COM_PIN_OUTPUT_SELECT(3), 0x00000000 },
53 { DC_COM_PIN_OUTPUT_SELECT(4), 0x00210222 },
54 { DC_COM_PIN_OUTPUT_SELECT(5), 0x00002200 },
55 { DC_COM_PIN_OUTPUT_SELECT(6), 0x00020000 },
56};
57
58static const struct reg_entry rgb_disable[] = {
59 { DC_COM_PIN_OUTPUT_SELECT(6), 0x00000000 },
60 { DC_COM_PIN_OUTPUT_SELECT(5), 0x00000000 },
61 { DC_COM_PIN_OUTPUT_SELECT(4), 0x00000000 },
62 { DC_COM_PIN_OUTPUT_SELECT(3), 0x00000000 },
63 { DC_COM_PIN_OUTPUT_SELECT(2), 0x00000000 },
64 { DC_COM_PIN_OUTPUT_SELECT(1), 0x00000000 },
65 { DC_COM_PIN_OUTPUT_SELECT(0), 0x00000000 },
66 { DC_COM_PIN_OUTPUT_DATA(3), 0xaaaaaaaa },
67 { DC_COM_PIN_OUTPUT_DATA(2), 0xaaaaaaaa },
68 { DC_COM_PIN_OUTPUT_DATA(1), 0xaaaaaaaa },
69 { DC_COM_PIN_OUTPUT_DATA(0), 0xaaaaaaaa },
70 { DC_COM_PIN_OUTPUT_POLARITY(3), 0x00000000 },
71 { DC_COM_PIN_OUTPUT_POLARITY(2), 0x00000000 },
72 { DC_COM_PIN_OUTPUT_POLARITY(1), 0x00000000 },
73 { DC_COM_PIN_OUTPUT_POLARITY(0), 0x00000000 },
74 { DC_COM_PIN_OUTPUT_ENABLE(3), 0x55555555 },
75 { DC_COM_PIN_OUTPUT_ENABLE(2), 0x55555555 },
76 { DC_COM_PIN_OUTPUT_ENABLE(1), 0x55150005 },
77 { DC_COM_PIN_OUTPUT_ENABLE(0), 0x55555555 },
78};
79
80static void tegra_dc_write_regs(struct tegra_dc *dc,
81 const struct reg_entry *table,
82 unsigned int num)
83{
84 unsigned int i;
85
86 for (i = 0; i < num; i++)
87 tegra_dc_writel(dc, table[i].value, table[i].offset);
88}
89
90static const struct drm_connector_funcs tegra_rgb_connector_funcs = {
91 .reset = drm_atomic_helper_connector_reset,
92 .detect = tegra_output_connector_detect,
93 .fill_modes = drm_helper_probe_single_connector_modes,
94 .destroy = tegra_output_connector_destroy,
95 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
96 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
97};
98
99static enum drm_mode_status
100tegra_rgb_connector_mode_valid(struct drm_connector *connector,
101 struct drm_display_mode *mode)
102{
103 /*
104 * FIXME: For now, always assume that the mode is okay. There are
105 * unresolved issues with clk_round_rate(), which doesn't always
106 * reliably report whether a frequency can be set or not.
107 */
108 return MODE_OK;
109}
110
111static const struct drm_connector_helper_funcs tegra_rgb_connector_helper_funcs = {
112 .get_modes = tegra_output_connector_get_modes,
113 .mode_valid = tegra_rgb_connector_mode_valid,
114};
115
116static const struct drm_encoder_funcs tegra_rgb_encoder_funcs = {
117 .destroy = tegra_output_encoder_destroy,
118};
119
120static void tegra_rgb_encoder_disable(struct drm_encoder *encoder)
121{
122 struct tegra_output *output = encoder_to_output(encoder);
123 struct tegra_rgb *rgb = to_rgb(output);
124
125 if (output->panel)
126 drm_panel_disable(output->panel);
127
128 tegra_dc_write_regs(rgb->dc, rgb_disable, ARRAY_SIZE(rgb_disable));
129 tegra_dc_commit(rgb->dc);
130
131 if (output->panel)
132 drm_panel_unprepare(output->panel);
133}
134
135static void tegra_rgb_encoder_enable(struct drm_encoder *encoder)
136{
137 struct tegra_output *output = encoder_to_output(encoder);
138 struct tegra_rgb *rgb = to_rgb(output);
139 u32 value;
140
141 if (output->panel)
142 drm_panel_prepare(output->panel);
143
144 tegra_dc_write_regs(rgb->dc, rgb_enable, ARRAY_SIZE(rgb_enable));
145
146 value = DE_SELECT_ACTIVE | DE_CONTROL_NORMAL;
147 tegra_dc_writel(rgb->dc, value, DC_DISP_DATA_ENABLE_OPTIONS);
148
149 /* XXX: parameterize? */
150 value = tegra_dc_readl(rgb->dc, DC_COM_PIN_OUTPUT_POLARITY(1));
151 value &= ~LVS_OUTPUT_POLARITY_LOW;
152 value &= ~LHS_OUTPUT_POLARITY_LOW;
153 tegra_dc_writel(rgb->dc, value, DC_COM_PIN_OUTPUT_POLARITY(1));
154
155 /* XXX: parameterize? */
156 value = DISP_DATA_FORMAT_DF1P1C | DISP_ALIGNMENT_MSB |
157 DISP_ORDER_RED_BLUE;
158 tegra_dc_writel(rgb->dc, value, DC_DISP_DISP_INTERFACE_CONTROL);
159
160 /* XXX: parameterize? */
161 value = SC0_H_QUALIFIER_NONE | SC1_H_QUALIFIER_NONE;
162 tegra_dc_writel(rgb->dc, value, DC_DISP_SHIFT_CLOCK_OPTIONS);
163
164 tegra_dc_commit(rgb->dc);
165
166 if (output->panel)
167 drm_panel_enable(output->panel);
168}
169
170static int
171tegra_rgb_encoder_atomic_check(struct drm_encoder *encoder,
172 struct drm_crtc_state *crtc_state,
173 struct drm_connector_state *conn_state)
174{
175 struct tegra_output *output = encoder_to_output(encoder);
176 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
177 unsigned long pclk = crtc_state->mode.clock * 1000;
178 struct tegra_rgb *rgb = to_rgb(output);
179 unsigned int div;
180 int err;
181
182 /*
183 * We may not want to change the frequency of the parent clock, since
184 * it may be a parent for other peripherals. This is due to the fact
185 * that on Tegra20 there's only a single clock dedicated to display
186 * (pll_d_out0), whereas later generations have a second one that can
187 * be used to independently drive a second output (pll_d2_out0).
188 *
189 * As a way to support multiple outputs on Tegra20 as well, pll_p is
190 * typically used as the parent clock for the display controllers.
191 * But this comes at a cost: pll_p is the parent of several other
192 * peripherals, so its frequency shouldn't change out of the blue.
193 *
194 * The best we can do at this point is to use the shift clock divider
195 * and hope that the desired frequency can be matched (or at least
196 * matched sufficiently close that the panel will still work).
197 */
198 div = ((clk_get_rate(rgb->clk) * 2) / pclk) - 2;
199 pclk = 0;
200
201 err = tegra_dc_state_setup_clock(dc, crtc_state, rgb->clk_parent,
202 pclk, div);
203 if (err < 0) {
204 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
205 return err;
206 }
207
208 return err;
209}
210
211static const struct drm_encoder_helper_funcs tegra_rgb_encoder_helper_funcs = {
212 .disable = tegra_rgb_encoder_disable,
213 .enable = tegra_rgb_encoder_enable,
214 .atomic_check = tegra_rgb_encoder_atomic_check,
215};
216
217int tegra_dc_rgb_probe(struct tegra_dc *dc)
218{
219 struct device_node *np;
220 struct tegra_rgb *rgb;
221 int err;
222
223 np = of_get_child_by_name(dc->dev->of_node, "rgb");
224 if (!np || !of_device_is_available(np))
225 return -ENODEV;
226
227 rgb = devm_kzalloc(dc->dev, sizeof(*rgb), GFP_KERNEL);
228 if (!rgb)
229 return -ENOMEM;
230
231 rgb->output.dev = dc->dev;
232 rgb->output.of_node = np;
233 rgb->dc = dc;
234
235 err = tegra_output_probe(&rgb->output);
236 if (err < 0)
237 return err;
238
239 rgb->clk = devm_clk_get(dc->dev, NULL);
240 if (IS_ERR(rgb->clk)) {
241 dev_err(dc->dev, "failed to get clock\n");
242 return PTR_ERR(rgb->clk);
243 }
244
245 rgb->clk_parent = devm_clk_get(dc->dev, "parent");
246 if (IS_ERR(rgb->clk_parent)) {
247 dev_err(dc->dev, "failed to get parent clock\n");
248 return PTR_ERR(rgb->clk_parent);
249 }
250
251 err = clk_set_parent(rgb->clk, rgb->clk_parent);
252 if (err < 0) {
253 dev_err(dc->dev, "failed to set parent clock: %d\n", err);
254 return err;
255 }
256
257 dc->rgb = &rgb->output;
258
259 return 0;
260}
261
262int tegra_dc_rgb_remove(struct tegra_dc *dc)
263{
264 if (!dc->rgb)
265 return 0;
266
267 tegra_output_remove(dc->rgb);
268 dc->rgb = NULL;
269
270 return 0;
271}
272
273int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc)
274{
275 struct tegra_output *output = dc->rgb;
276 int err;
277
278 if (!dc->rgb)
279 return -ENODEV;
280
281 drm_connector_init(drm, &output->connector, &tegra_rgb_connector_funcs,
282 DRM_MODE_CONNECTOR_LVDS);
283 drm_connector_helper_add(&output->connector,
284 &tegra_rgb_connector_helper_funcs);
285 output->connector.dpms = DRM_MODE_DPMS_OFF;
286
287 drm_encoder_init(drm, &output->encoder, &tegra_rgb_encoder_funcs,
288 DRM_MODE_ENCODER_LVDS, NULL);
289 drm_encoder_helper_add(&output->encoder,
290 &tegra_rgb_encoder_helper_funcs);
291
292 drm_mode_connector_attach_encoder(&output->connector,
293 &output->encoder);
294 drm_connector_register(&output->connector);
295
296 err = tegra_output_init(drm, output);
297 if (err < 0) {
298 dev_err(output->dev, "failed to initialize output: %d\n", err);
299 return err;
300 }
301
302 /*
303 * Other outputs can be attached to either display controller. The RGB
304 * outputs are an exception and work only with their parent display
305 * controller.
306 */
307 output->encoder.possible_crtcs = drm_crtc_mask(&dc->base);
308
309 return 0;
310}
311
312int tegra_dc_rgb_exit(struct tegra_dc *dc)
313{
314 if (dc->rgb)
315 tegra_output_exit(dc->rgb);
316
317 return 0;
318}