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1/*
2 * linux/drivers/video/omap2/dss/dispc.h
3 *
4 * Copyright (C) 2011 Texas Instruments
5 * Author: Archit Taneja <archit@ti.com>
6 *
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published by
10 * the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#ifndef __OMAP2_DISPC_REG_H
22#define __OMAP2_DISPC_REG_H
23
24/* DISPC common registers */
25#define DISPC_REVISION 0x0000
26#define DISPC_SYSCONFIG 0x0010
27#define DISPC_SYSSTATUS 0x0014
28#define DISPC_IRQSTATUS 0x0018
29#define DISPC_IRQENABLE 0x001C
30#define DISPC_CONTROL 0x0040
31#define DISPC_CONFIG 0x0044
32#define DISPC_CAPABLE 0x0048
33#define DISPC_LINE_STATUS 0x005C
34#define DISPC_LINE_NUMBER 0x0060
35#define DISPC_GLOBAL_ALPHA 0x0074
36#define DISPC_CONTROL2 0x0238
37#define DISPC_CONFIG2 0x0620
38#define DISPC_DIVISOR 0x0804
39#define DISPC_GLOBAL_BUFFER 0x0800
40#define DISPC_CONTROL3 0x0848
41#define DISPC_CONFIG3 0x084C
42#define DISPC_MSTANDBY_CTRL 0x0858
43#define DISPC_GLOBAL_MFLAG_ATTRIBUTE 0x085C
44
45/* DISPC overlay registers */
46#define DISPC_OVL_BA0(n) (DISPC_OVL_BASE(n) + \
47 DISPC_BA0_OFFSET(n))
48#define DISPC_OVL_BA1(n) (DISPC_OVL_BASE(n) + \
49 DISPC_BA1_OFFSET(n))
50#define DISPC_OVL_BA0_UV(n) (DISPC_OVL_BASE(n) + \
51 DISPC_BA0_UV_OFFSET(n))
52#define DISPC_OVL_BA1_UV(n) (DISPC_OVL_BASE(n) + \
53 DISPC_BA1_UV_OFFSET(n))
54#define DISPC_OVL_POSITION(n) (DISPC_OVL_BASE(n) + \
55 DISPC_POS_OFFSET(n))
56#define DISPC_OVL_SIZE(n) (DISPC_OVL_BASE(n) + \
57 DISPC_SIZE_OFFSET(n))
58#define DISPC_OVL_ATTRIBUTES(n) (DISPC_OVL_BASE(n) + \
59 DISPC_ATTR_OFFSET(n))
60#define DISPC_OVL_ATTRIBUTES2(n) (DISPC_OVL_BASE(n) + \
61 DISPC_ATTR2_OFFSET(n))
62#define DISPC_OVL_FIFO_THRESHOLD(n) (DISPC_OVL_BASE(n) + \
63 DISPC_FIFO_THRESH_OFFSET(n))
64#define DISPC_OVL_FIFO_SIZE_STATUS(n) (DISPC_OVL_BASE(n) + \
65 DISPC_FIFO_SIZE_STATUS_OFFSET(n))
66#define DISPC_OVL_ROW_INC(n) (DISPC_OVL_BASE(n) + \
67 DISPC_ROW_INC_OFFSET(n))
68#define DISPC_OVL_PIXEL_INC(n) (DISPC_OVL_BASE(n) + \
69 DISPC_PIX_INC_OFFSET(n))
70#define DISPC_OVL_WINDOW_SKIP(n) (DISPC_OVL_BASE(n) + \
71 DISPC_WINDOW_SKIP_OFFSET(n))
72#define DISPC_OVL_TABLE_BA(n) (DISPC_OVL_BASE(n) + \
73 DISPC_TABLE_BA_OFFSET(n))
74#define DISPC_OVL_FIR(n) (DISPC_OVL_BASE(n) + \
75 DISPC_FIR_OFFSET(n))
76#define DISPC_OVL_FIR2(n) (DISPC_OVL_BASE(n) + \
77 DISPC_FIR2_OFFSET(n))
78#define DISPC_OVL_PICTURE_SIZE(n) (DISPC_OVL_BASE(n) + \
79 DISPC_PIC_SIZE_OFFSET(n))
80#define DISPC_OVL_ACCU0(n) (DISPC_OVL_BASE(n) + \
81 DISPC_ACCU0_OFFSET(n))
82#define DISPC_OVL_ACCU1(n) (DISPC_OVL_BASE(n) + \
83 DISPC_ACCU1_OFFSET(n))
84#define DISPC_OVL_ACCU2_0(n) (DISPC_OVL_BASE(n) + \
85 DISPC_ACCU2_0_OFFSET(n))
86#define DISPC_OVL_ACCU2_1(n) (DISPC_OVL_BASE(n) + \
87 DISPC_ACCU2_1_OFFSET(n))
88#define DISPC_OVL_FIR_COEF_H(n, i) (DISPC_OVL_BASE(n) + \
89 DISPC_FIR_COEF_H_OFFSET(n, i))
90#define DISPC_OVL_FIR_COEF_HV(n, i) (DISPC_OVL_BASE(n) + \
91 DISPC_FIR_COEF_HV_OFFSET(n, i))
92#define DISPC_OVL_FIR_COEF_H2(n, i) (DISPC_OVL_BASE(n) + \
93 DISPC_FIR_COEF_H2_OFFSET(n, i))
94#define DISPC_OVL_FIR_COEF_HV2(n, i) (DISPC_OVL_BASE(n) + \
95 DISPC_FIR_COEF_HV2_OFFSET(n, i))
96#define DISPC_OVL_CONV_COEF(n, i) (DISPC_OVL_BASE(n) + \
97 DISPC_CONV_COEF_OFFSET(n, i))
98#define DISPC_OVL_FIR_COEF_V(n, i) (DISPC_OVL_BASE(n) + \
99 DISPC_FIR_COEF_V_OFFSET(n, i))
100#define DISPC_OVL_FIR_COEF_V2(n, i) (DISPC_OVL_BASE(n) + \
101 DISPC_FIR_COEF_V2_OFFSET(n, i))
102#define DISPC_OVL_PRELOAD(n) (DISPC_OVL_BASE(n) + \
103 DISPC_PRELOAD_OFFSET(n))
104#define DISPC_OVL_MFLAG_THRESHOLD(n) DISPC_MFLAG_THRESHOLD_OFFSET(n)
105
106/* DISPC up/downsampling FIR filter coefficient structure */
107struct dispc_coef {
108 s8 hc4_vc22;
109 s8 hc3_vc2;
110 u8 hc2_vc1;
111 s8 hc1_vc0;
112 s8 hc0_vc00;
113};
114
115const struct dispc_coef *dispc_ovl_get_scale_coef(int inc, int five_taps);
116
117/* DISPC manager/channel specific registers */
118static inline u16 DISPC_DEFAULT_COLOR(enum omap_channel channel)
119{
120 switch (channel) {
121 case OMAP_DSS_CHANNEL_LCD:
122 return 0x004C;
123 case OMAP_DSS_CHANNEL_DIGIT:
124 return 0x0050;
125 case OMAP_DSS_CHANNEL_LCD2:
126 return 0x03AC;
127 case OMAP_DSS_CHANNEL_LCD3:
128 return 0x0814;
129 default:
130 BUG();
131 return 0;
132 }
133}
134
135static inline u16 DISPC_TRANS_COLOR(enum omap_channel channel)
136{
137 switch (channel) {
138 case OMAP_DSS_CHANNEL_LCD:
139 return 0x0054;
140 case OMAP_DSS_CHANNEL_DIGIT:
141 return 0x0058;
142 case OMAP_DSS_CHANNEL_LCD2:
143 return 0x03B0;
144 case OMAP_DSS_CHANNEL_LCD3:
145 return 0x0818;
146 default:
147 BUG();
148 return 0;
149 }
150}
151
152static inline u16 DISPC_TIMING_H(enum omap_channel channel)
153{
154 switch (channel) {
155 case OMAP_DSS_CHANNEL_LCD:
156 return 0x0064;
157 case OMAP_DSS_CHANNEL_DIGIT:
158 BUG();
159 return 0;
160 case OMAP_DSS_CHANNEL_LCD2:
161 return 0x0400;
162 case OMAP_DSS_CHANNEL_LCD3:
163 return 0x0840;
164 default:
165 BUG();
166 return 0;
167 }
168}
169
170static inline u16 DISPC_TIMING_V(enum omap_channel channel)
171{
172 switch (channel) {
173 case OMAP_DSS_CHANNEL_LCD:
174 return 0x0068;
175 case OMAP_DSS_CHANNEL_DIGIT:
176 BUG();
177 return 0;
178 case OMAP_DSS_CHANNEL_LCD2:
179 return 0x0404;
180 case OMAP_DSS_CHANNEL_LCD3:
181 return 0x0844;
182 default:
183 BUG();
184 return 0;
185 }
186}
187
188static inline u16 DISPC_POL_FREQ(enum omap_channel channel)
189{
190 switch (channel) {
191 case OMAP_DSS_CHANNEL_LCD:
192 return 0x006C;
193 case OMAP_DSS_CHANNEL_DIGIT:
194 BUG();
195 return 0;
196 case OMAP_DSS_CHANNEL_LCD2:
197 return 0x0408;
198 case OMAP_DSS_CHANNEL_LCD3:
199 return 0x083C;
200 default:
201 BUG();
202 return 0;
203 }
204}
205
206static inline u16 DISPC_DIVISORo(enum omap_channel channel)
207{
208 switch (channel) {
209 case OMAP_DSS_CHANNEL_LCD:
210 return 0x0070;
211 case OMAP_DSS_CHANNEL_DIGIT:
212 BUG();
213 return 0;
214 case OMAP_DSS_CHANNEL_LCD2:
215 return 0x040C;
216 case OMAP_DSS_CHANNEL_LCD3:
217 return 0x0838;
218 default:
219 BUG();
220 return 0;
221 }
222}
223
224/* Named as DISPC_SIZE_LCD, DISPC_SIZE_DIGIT and DISPC_SIZE_LCD2 in TRM */
225static inline u16 DISPC_SIZE_MGR(enum omap_channel channel)
226{
227 switch (channel) {
228 case OMAP_DSS_CHANNEL_LCD:
229 return 0x007C;
230 case OMAP_DSS_CHANNEL_DIGIT:
231 return 0x0078;
232 case OMAP_DSS_CHANNEL_LCD2:
233 return 0x03CC;
234 case OMAP_DSS_CHANNEL_LCD3:
235 return 0x0834;
236 default:
237 BUG();
238 return 0;
239 }
240}
241
242static inline u16 DISPC_DATA_CYCLE1(enum omap_channel channel)
243{
244 switch (channel) {
245 case OMAP_DSS_CHANNEL_LCD:
246 return 0x01D4;
247 case OMAP_DSS_CHANNEL_DIGIT:
248 BUG();
249 return 0;
250 case OMAP_DSS_CHANNEL_LCD2:
251 return 0x03C0;
252 case OMAP_DSS_CHANNEL_LCD3:
253 return 0x0828;
254 default:
255 BUG();
256 return 0;
257 }
258}
259
260static inline u16 DISPC_DATA_CYCLE2(enum omap_channel channel)
261{
262 switch (channel) {
263 case OMAP_DSS_CHANNEL_LCD:
264 return 0x01D8;
265 case OMAP_DSS_CHANNEL_DIGIT:
266 BUG();
267 return 0;
268 case OMAP_DSS_CHANNEL_LCD2:
269 return 0x03C4;
270 case OMAP_DSS_CHANNEL_LCD3:
271 return 0x082C;
272 default:
273 BUG();
274 return 0;
275 }
276}
277
278static inline u16 DISPC_DATA_CYCLE3(enum omap_channel channel)
279{
280 switch (channel) {
281 case OMAP_DSS_CHANNEL_LCD:
282 return 0x01DC;
283 case OMAP_DSS_CHANNEL_DIGIT:
284 BUG();
285 return 0;
286 case OMAP_DSS_CHANNEL_LCD2:
287 return 0x03C8;
288 case OMAP_DSS_CHANNEL_LCD3:
289 return 0x0830;
290 default:
291 BUG();
292 return 0;
293 }
294}
295
296static inline u16 DISPC_CPR_COEF_R(enum omap_channel channel)
297{
298 switch (channel) {
299 case OMAP_DSS_CHANNEL_LCD:
300 return 0x0220;
301 case OMAP_DSS_CHANNEL_DIGIT:
302 BUG();
303 return 0;
304 case OMAP_DSS_CHANNEL_LCD2:
305 return 0x03BC;
306 case OMAP_DSS_CHANNEL_LCD3:
307 return 0x0824;
308 default:
309 BUG();
310 return 0;
311 }
312}
313
314static inline u16 DISPC_CPR_COEF_G(enum omap_channel channel)
315{
316 switch (channel) {
317 case OMAP_DSS_CHANNEL_LCD:
318 return 0x0224;
319 case OMAP_DSS_CHANNEL_DIGIT:
320 BUG();
321 return 0;
322 case OMAP_DSS_CHANNEL_LCD2:
323 return 0x03B8;
324 case OMAP_DSS_CHANNEL_LCD3:
325 return 0x0820;
326 default:
327 BUG();
328 return 0;
329 }
330}
331
332static inline u16 DISPC_CPR_COEF_B(enum omap_channel channel)
333{
334 switch (channel) {
335 case OMAP_DSS_CHANNEL_LCD:
336 return 0x0228;
337 case OMAP_DSS_CHANNEL_DIGIT:
338 BUG();
339 return 0;
340 case OMAP_DSS_CHANNEL_LCD2:
341 return 0x03B4;
342 case OMAP_DSS_CHANNEL_LCD3:
343 return 0x081C;
344 default:
345 BUG();
346 return 0;
347 }
348}
349
350/* DISPC overlay register base addresses */
351static inline u16 DISPC_OVL_BASE(enum omap_plane plane)
352{
353 switch (plane) {
354 case OMAP_DSS_GFX:
355 return 0x0080;
356 case OMAP_DSS_VIDEO1:
357 return 0x00BC;
358 case OMAP_DSS_VIDEO2:
359 return 0x014C;
360 case OMAP_DSS_VIDEO3:
361 return 0x0300;
362 case OMAP_DSS_WB:
363 return 0x0500;
364 default:
365 BUG();
366 return 0;
367 }
368}
369
370/* DISPC overlay register offsets */
371static inline u16 DISPC_BA0_OFFSET(enum omap_plane plane)
372{
373 switch (plane) {
374 case OMAP_DSS_GFX:
375 case OMAP_DSS_VIDEO1:
376 case OMAP_DSS_VIDEO2:
377 return 0x0000;
378 case OMAP_DSS_VIDEO3:
379 case OMAP_DSS_WB:
380 return 0x0008;
381 default:
382 BUG();
383 return 0;
384 }
385}
386
387static inline u16 DISPC_BA1_OFFSET(enum omap_plane plane)
388{
389 switch (plane) {
390 case OMAP_DSS_GFX:
391 case OMAP_DSS_VIDEO1:
392 case OMAP_DSS_VIDEO2:
393 return 0x0004;
394 case OMAP_DSS_VIDEO3:
395 case OMAP_DSS_WB:
396 return 0x000C;
397 default:
398 BUG();
399 return 0;
400 }
401}
402
403static inline u16 DISPC_BA0_UV_OFFSET(enum omap_plane plane)
404{
405 switch (plane) {
406 case OMAP_DSS_GFX:
407 BUG();
408 return 0;
409 case OMAP_DSS_VIDEO1:
410 return 0x0544;
411 case OMAP_DSS_VIDEO2:
412 return 0x04BC;
413 case OMAP_DSS_VIDEO3:
414 return 0x0310;
415 case OMAP_DSS_WB:
416 return 0x0118;
417 default:
418 BUG();
419 return 0;
420 }
421}
422
423static inline u16 DISPC_BA1_UV_OFFSET(enum omap_plane plane)
424{
425 switch (plane) {
426 case OMAP_DSS_GFX:
427 BUG();
428 return 0;
429 case OMAP_DSS_VIDEO1:
430 return 0x0548;
431 case OMAP_DSS_VIDEO2:
432 return 0x04C0;
433 case OMAP_DSS_VIDEO3:
434 return 0x0314;
435 case OMAP_DSS_WB:
436 return 0x011C;
437 default:
438 BUG();
439 return 0;
440 }
441}
442
443static inline u16 DISPC_POS_OFFSET(enum omap_plane plane)
444{
445 switch (plane) {
446 case OMAP_DSS_GFX:
447 case OMAP_DSS_VIDEO1:
448 case OMAP_DSS_VIDEO2:
449 return 0x0008;
450 case OMAP_DSS_VIDEO3:
451 return 0x009C;
452 default:
453 BUG();
454 return 0;
455 }
456}
457
458static inline u16 DISPC_SIZE_OFFSET(enum omap_plane plane)
459{
460 switch (plane) {
461 case OMAP_DSS_GFX:
462 case OMAP_DSS_VIDEO1:
463 case OMAP_DSS_VIDEO2:
464 return 0x000C;
465 case OMAP_DSS_VIDEO3:
466 case OMAP_DSS_WB:
467 return 0x00A8;
468 default:
469 BUG();
470 return 0;
471 }
472}
473
474static inline u16 DISPC_ATTR_OFFSET(enum omap_plane plane)
475{
476 switch (plane) {
477 case OMAP_DSS_GFX:
478 return 0x0020;
479 case OMAP_DSS_VIDEO1:
480 case OMAP_DSS_VIDEO2:
481 return 0x0010;
482 case OMAP_DSS_VIDEO3:
483 case OMAP_DSS_WB:
484 return 0x0070;
485 default:
486 BUG();
487 return 0;
488 }
489}
490
491static inline u16 DISPC_ATTR2_OFFSET(enum omap_plane plane)
492{
493 switch (plane) {
494 case OMAP_DSS_GFX:
495 BUG();
496 return 0;
497 case OMAP_DSS_VIDEO1:
498 return 0x0568;
499 case OMAP_DSS_VIDEO2:
500 return 0x04DC;
501 case OMAP_DSS_VIDEO3:
502 return 0x032C;
503 case OMAP_DSS_WB:
504 return 0x0310;
505 default:
506 BUG();
507 return 0;
508 }
509}
510
511static inline u16 DISPC_FIFO_THRESH_OFFSET(enum omap_plane plane)
512{
513 switch (plane) {
514 case OMAP_DSS_GFX:
515 return 0x0024;
516 case OMAP_DSS_VIDEO1:
517 case OMAP_DSS_VIDEO2:
518 return 0x0014;
519 case OMAP_DSS_VIDEO3:
520 case OMAP_DSS_WB:
521 return 0x008C;
522 default:
523 BUG();
524 return 0;
525 }
526}
527
528static inline u16 DISPC_FIFO_SIZE_STATUS_OFFSET(enum omap_plane plane)
529{
530 switch (plane) {
531 case OMAP_DSS_GFX:
532 return 0x0028;
533 case OMAP_DSS_VIDEO1:
534 case OMAP_DSS_VIDEO2:
535 return 0x0018;
536 case OMAP_DSS_VIDEO3:
537 case OMAP_DSS_WB:
538 return 0x0088;
539 default:
540 BUG();
541 return 0;
542 }
543}
544
545static inline u16 DISPC_ROW_INC_OFFSET(enum omap_plane plane)
546{
547 switch (plane) {
548 case OMAP_DSS_GFX:
549 return 0x002C;
550 case OMAP_DSS_VIDEO1:
551 case OMAP_DSS_VIDEO2:
552 return 0x001C;
553 case OMAP_DSS_VIDEO3:
554 case OMAP_DSS_WB:
555 return 0x00A4;
556 default:
557 BUG();
558 return 0;
559 }
560}
561
562static inline u16 DISPC_PIX_INC_OFFSET(enum omap_plane plane)
563{
564 switch (plane) {
565 case OMAP_DSS_GFX:
566 return 0x0030;
567 case OMAP_DSS_VIDEO1:
568 case OMAP_DSS_VIDEO2:
569 return 0x0020;
570 case OMAP_DSS_VIDEO3:
571 case OMAP_DSS_WB:
572 return 0x0098;
573 default:
574 BUG();
575 return 0;
576 }
577}
578
579static inline u16 DISPC_WINDOW_SKIP_OFFSET(enum omap_plane plane)
580{
581 switch (plane) {
582 case OMAP_DSS_GFX:
583 return 0x0034;
584 case OMAP_DSS_VIDEO1:
585 case OMAP_DSS_VIDEO2:
586 case OMAP_DSS_VIDEO3:
587 BUG();
588 return 0;
589 default:
590 BUG();
591 return 0;
592 }
593}
594
595static inline u16 DISPC_TABLE_BA_OFFSET(enum omap_plane plane)
596{
597 switch (plane) {
598 case OMAP_DSS_GFX:
599 return 0x0038;
600 case OMAP_DSS_VIDEO1:
601 case OMAP_DSS_VIDEO2:
602 case OMAP_DSS_VIDEO3:
603 BUG();
604 return 0;
605 default:
606 BUG();
607 return 0;
608 }
609}
610
611static inline u16 DISPC_FIR_OFFSET(enum omap_plane plane)
612{
613 switch (plane) {
614 case OMAP_DSS_GFX:
615 BUG();
616 return 0;
617 case OMAP_DSS_VIDEO1:
618 case OMAP_DSS_VIDEO2:
619 return 0x0024;
620 case OMAP_DSS_VIDEO3:
621 case OMAP_DSS_WB:
622 return 0x0090;
623 default:
624 BUG();
625 return 0;
626 }
627}
628
629static inline u16 DISPC_FIR2_OFFSET(enum omap_plane plane)
630{
631 switch (plane) {
632 case OMAP_DSS_GFX:
633 BUG();
634 return 0;
635 case OMAP_DSS_VIDEO1:
636 return 0x0580;
637 case OMAP_DSS_VIDEO2:
638 return 0x055C;
639 case OMAP_DSS_VIDEO3:
640 return 0x0424;
641 case OMAP_DSS_WB:
642 return 0x290;
643 default:
644 BUG();
645 return 0;
646 }
647}
648
649static inline u16 DISPC_PIC_SIZE_OFFSET(enum omap_plane plane)
650{
651 switch (plane) {
652 case OMAP_DSS_GFX:
653 BUG();
654 return 0;
655 case OMAP_DSS_VIDEO1:
656 case OMAP_DSS_VIDEO2:
657 return 0x0028;
658 case OMAP_DSS_VIDEO3:
659 case OMAP_DSS_WB:
660 return 0x0094;
661 default:
662 BUG();
663 return 0;
664 }
665}
666
667
668static inline u16 DISPC_ACCU0_OFFSET(enum omap_plane plane)
669{
670 switch (plane) {
671 case OMAP_DSS_GFX:
672 BUG();
673 return 0;
674 case OMAP_DSS_VIDEO1:
675 case OMAP_DSS_VIDEO2:
676 return 0x002C;
677 case OMAP_DSS_VIDEO3:
678 case OMAP_DSS_WB:
679 return 0x0000;
680 default:
681 BUG();
682 return 0;
683 }
684}
685
686static inline u16 DISPC_ACCU2_0_OFFSET(enum omap_plane plane)
687{
688 switch (plane) {
689 case OMAP_DSS_GFX:
690 BUG();
691 return 0;
692 case OMAP_DSS_VIDEO1:
693 return 0x0584;
694 case OMAP_DSS_VIDEO2:
695 return 0x0560;
696 case OMAP_DSS_VIDEO3:
697 return 0x0428;
698 case OMAP_DSS_WB:
699 return 0x0294;
700 default:
701 BUG();
702 return 0;
703 }
704}
705
706static inline u16 DISPC_ACCU1_OFFSET(enum omap_plane plane)
707{
708 switch (plane) {
709 case OMAP_DSS_GFX:
710 BUG();
711 return 0;
712 case OMAP_DSS_VIDEO1:
713 case OMAP_DSS_VIDEO2:
714 return 0x0030;
715 case OMAP_DSS_VIDEO3:
716 case OMAP_DSS_WB:
717 return 0x0004;
718 default:
719 BUG();
720 return 0;
721 }
722}
723
724static inline u16 DISPC_ACCU2_1_OFFSET(enum omap_plane plane)
725{
726 switch (plane) {
727 case OMAP_DSS_GFX:
728 BUG();
729 return 0;
730 case OMAP_DSS_VIDEO1:
731 return 0x0588;
732 case OMAP_DSS_VIDEO2:
733 return 0x0564;
734 case OMAP_DSS_VIDEO3:
735 return 0x042C;
736 case OMAP_DSS_WB:
737 return 0x0298;
738 default:
739 BUG();
740 return 0;
741 }
742}
743
744/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
745static inline u16 DISPC_FIR_COEF_H_OFFSET(enum omap_plane plane, u16 i)
746{
747 switch (plane) {
748 case OMAP_DSS_GFX:
749 BUG();
750 return 0;
751 case OMAP_DSS_VIDEO1:
752 case OMAP_DSS_VIDEO2:
753 return 0x0034 + i * 0x8;
754 case OMAP_DSS_VIDEO3:
755 case OMAP_DSS_WB:
756 return 0x0010 + i * 0x8;
757 default:
758 BUG();
759 return 0;
760 }
761}
762
763/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
764static inline u16 DISPC_FIR_COEF_H2_OFFSET(enum omap_plane plane, u16 i)
765{
766 switch (plane) {
767 case OMAP_DSS_GFX:
768 BUG();
769 return 0;
770 case OMAP_DSS_VIDEO1:
771 return 0x058C + i * 0x8;
772 case OMAP_DSS_VIDEO2:
773 return 0x0568 + i * 0x8;
774 case OMAP_DSS_VIDEO3:
775 return 0x0430 + i * 0x8;
776 case OMAP_DSS_WB:
777 return 0x02A0 + i * 0x8;
778 default:
779 BUG();
780 return 0;
781 }
782}
783
784/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
785static inline u16 DISPC_FIR_COEF_HV_OFFSET(enum omap_plane plane, u16 i)
786{
787 switch (plane) {
788 case OMAP_DSS_GFX:
789 BUG();
790 return 0;
791 case OMAP_DSS_VIDEO1:
792 case OMAP_DSS_VIDEO2:
793 return 0x0038 + i * 0x8;
794 case OMAP_DSS_VIDEO3:
795 case OMAP_DSS_WB:
796 return 0x0014 + i * 0x8;
797 default:
798 BUG();
799 return 0;
800 }
801}
802
803/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
804static inline u16 DISPC_FIR_COEF_HV2_OFFSET(enum omap_plane plane, u16 i)
805{
806 switch (plane) {
807 case OMAP_DSS_GFX:
808 BUG();
809 return 0;
810 case OMAP_DSS_VIDEO1:
811 return 0x0590 + i * 8;
812 case OMAP_DSS_VIDEO2:
813 return 0x056C + i * 0x8;
814 case OMAP_DSS_VIDEO3:
815 return 0x0434 + i * 0x8;
816 case OMAP_DSS_WB:
817 return 0x02A4 + i * 0x8;
818 default:
819 BUG();
820 return 0;
821 }
822}
823
824/* coef index i = {0, 1, 2, 3, 4,} */
825static inline u16 DISPC_CONV_COEF_OFFSET(enum omap_plane plane, u16 i)
826{
827 switch (plane) {
828 case OMAP_DSS_GFX:
829 BUG();
830 return 0;
831 case OMAP_DSS_VIDEO1:
832 case OMAP_DSS_VIDEO2:
833 case OMAP_DSS_VIDEO3:
834 case OMAP_DSS_WB:
835 return 0x0074 + i * 0x4;
836 default:
837 BUG();
838 return 0;
839 }
840}
841
842/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
843static inline u16 DISPC_FIR_COEF_V_OFFSET(enum omap_plane plane, u16 i)
844{
845 switch (plane) {
846 case OMAP_DSS_GFX:
847 BUG();
848 return 0;
849 case OMAP_DSS_VIDEO1:
850 return 0x0124 + i * 0x4;
851 case OMAP_DSS_VIDEO2:
852 return 0x00B4 + i * 0x4;
853 case OMAP_DSS_VIDEO3:
854 case OMAP_DSS_WB:
855 return 0x0050 + i * 0x4;
856 default:
857 BUG();
858 return 0;
859 }
860}
861
862/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
863static inline u16 DISPC_FIR_COEF_V2_OFFSET(enum omap_plane plane, u16 i)
864{
865 switch (plane) {
866 case OMAP_DSS_GFX:
867 BUG();
868 return 0;
869 case OMAP_DSS_VIDEO1:
870 return 0x05CC + i * 0x4;
871 case OMAP_DSS_VIDEO2:
872 return 0x05A8 + i * 0x4;
873 case OMAP_DSS_VIDEO3:
874 return 0x0470 + i * 0x4;
875 case OMAP_DSS_WB:
876 return 0x02E0 + i * 0x4;
877 default:
878 BUG();
879 return 0;
880 }
881}
882
883static inline u16 DISPC_PRELOAD_OFFSET(enum omap_plane plane)
884{
885 switch (plane) {
886 case OMAP_DSS_GFX:
887 return 0x01AC;
888 case OMAP_DSS_VIDEO1:
889 return 0x0174;
890 case OMAP_DSS_VIDEO2:
891 return 0x00E8;
892 case OMAP_DSS_VIDEO3:
893 return 0x00A0;
894 default:
895 BUG();
896 return 0;
897 }
898}
899
900static inline u16 DISPC_MFLAG_THRESHOLD_OFFSET(enum omap_plane plane)
901{
902 switch (plane) {
903 case OMAP_DSS_GFX:
904 return 0x0860;
905 case OMAP_DSS_VIDEO1:
906 return 0x0864;
907 case OMAP_DSS_VIDEO2:
908 return 0x0868;
909 case OMAP_DSS_VIDEO3:
910 return 0x086c;
911 case OMAP_DSS_WB:
912 return 0x0870;
913 default:
914 BUG();
915 return 0;
916 }
917}
918#endif
1/*
2 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
3 * Author: Archit Taneja <archit@ti.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#ifndef __OMAP2_DISPC_REG_H
19#define __OMAP2_DISPC_REG_H
20
21/* DISPC common registers */
22#define DISPC_REVISION 0x0000
23#define DISPC_SYSCONFIG 0x0010
24#define DISPC_SYSSTATUS 0x0014
25#define DISPC_IRQSTATUS 0x0018
26#define DISPC_IRQENABLE 0x001C
27#define DISPC_CONTROL 0x0040
28#define DISPC_CONFIG 0x0044
29#define DISPC_CAPABLE 0x0048
30#define DISPC_LINE_STATUS 0x005C
31#define DISPC_LINE_NUMBER 0x0060
32#define DISPC_GLOBAL_ALPHA 0x0074
33#define DISPC_CONTROL2 0x0238
34#define DISPC_CONFIG2 0x0620
35#define DISPC_DIVISOR 0x0804
36#define DISPC_GLOBAL_BUFFER 0x0800
37#define DISPC_CONTROL3 0x0848
38#define DISPC_CONFIG3 0x084C
39#define DISPC_MSTANDBY_CTRL 0x0858
40#define DISPC_GLOBAL_MFLAG_ATTRIBUTE 0x085C
41
42#define DISPC_GAMMA_TABLE0 0x0630
43#define DISPC_GAMMA_TABLE1 0x0634
44#define DISPC_GAMMA_TABLE2 0x0638
45#define DISPC_GAMMA_TABLE3 0x0850
46
47/* DISPC overlay registers */
48#define DISPC_OVL_BA0(n) (DISPC_OVL_BASE(n) + \
49 DISPC_BA0_OFFSET(n))
50#define DISPC_OVL_BA1(n) (DISPC_OVL_BASE(n) + \
51 DISPC_BA1_OFFSET(n))
52#define DISPC_OVL_BA0_UV(n) (DISPC_OVL_BASE(n) + \
53 DISPC_BA0_UV_OFFSET(n))
54#define DISPC_OVL_BA1_UV(n) (DISPC_OVL_BASE(n) + \
55 DISPC_BA1_UV_OFFSET(n))
56#define DISPC_OVL_POSITION(n) (DISPC_OVL_BASE(n) + \
57 DISPC_POS_OFFSET(n))
58#define DISPC_OVL_SIZE(n) (DISPC_OVL_BASE(n) + \
59 DISPC_SIZE_OFFSET(n))
60#define DISPC_OVL_ATTRIBUTES(n) (DISPC_OVL_BASE(n) + \
61 DISPC_ATTR_OFFSET(n))
62#define DISPC_OVL_ATTRIBUTES2(n) (DISPC_OVL_BASE(n) + \
63 DISPC_ATTR2_OFFSET(n))
64#define DISPC_OVL_FIFO_THRESHOLD(n) (DISPC_OVL_BASE(n) + \
65 DISPC_FIFO_THRESH_OFFSET(n))
66#define DISPC_OVL_FIFO_SIZE_STATUS(n) (DISPC_OVL_BASE(n) + \
67 DISPC_FIFO_SIZE_STATUS_OFFSET(n))
68#define DISPC_OVL_ROW_INC(n) (DISPC_OVL_BASE(n) + \
69 DISPC_ROW_INC_OFFSET(n))
70#define DISPC_OVL_PIXEL_INC(n) (DISPC_OVL_BASE(n) + \
71 DISPC_PIX_INC_OFFSET(n))
72#define DISPC_OVL_WINDOW_SKIP(n) (DISPC_OVL_BASE(n) + \
73 DISPC_WINDOW_SKIP_OFFSET(n))
74#define DISPC_OVL_TABLE_BA(n) (DISPC_OVL_BASE(n) + \
75 DISPC_TABLE_BA_OFFSET(n))
76#define DISPC_OVL_FIR(n) (DISPC_OVL_BASE(n) + \
77 DISPC_FIR_OFFSET(n))
78#define DISPC_OVL_FIR2(n) (DISPC_OVL_BASE(n) + \
79 DISPC_FIR2_OFFSET(n))
80#define DISPC_OVL_PICTURE_SIZE(n) (DISPC_OVL_BASE(n) + \
81 DISPC_PIC_SIZE_OFFSET(n))
82#define DISPC_OVL_ACCU0(n) (DISPC_OVL_BASE(n) + \
83 DISPC_ACCU0_OFFSET(n))
84#define DISPC_OVL_ACCU1(n) (DISPC_OVL_BASE(n) + \
85 DISPC_ACCU1_OFFSET(n))
86#define DISPC_OVL_ACCU2_0(n) (DISPC_OVL_BASE(n) + \
87 DISPC_ACCU2_0_OFFSET(n))
88#define DISPC_OVL_ACCU2_1(n) (DISPC_OVL_BASE(n) + \
89 DISPC_ACCU2_1_OFFSET(n))
90#define DISPC_OVL_FIR_COEF_H(n, i) (DISPC_OVL_BASE(n) + \
91 DISPC_FIR_COEF_H_OFFSET(n, i))
92#define DISPC_OVL_FIR_COEF_HV(n, i) (DISPC_OVL_BASE(n) + \
93 DISPC_FIR_COEF_HV_OFFSET(n, i))
94#define DISPC_OVL_FIR_COEF_H2(n, i) (DISPC_OVL_BASE(n) + \
95 DISPC_FIR_COEF_H2_OFFSET(n, i))
96#define DISPC_OVL_FIR_COEF_HV2(n, i) (DISPC_OVL_BASE(n) + \
97 DISPC_FIR_COEF_HV2_OFFSET(n, i))
98#define DISPC_OVL_CONV_COEF(n, i) (DISPC_OVL_BASE(n) + \
99 DISPC_CONV_COEF_OFFSET(n, i))
100#define DISPC_OVL_FIR_COEF_V(n, i) (DISPC_OVL_BASE(n) + \
101 DISPC_FIR_COEF_V_OFFSET(n, i))
102#define DISPC_OVL_FIR_COEF_V2(n, i) (DISPC_OVL_BASE(n) + \
103 DISPC_FIR_COEF_V2_OFFSET(n, i))
104#define DISPC_OVL_PRELOAD(n) (DISPC_OVL_BASE(n) + \
105 DISPC_PRELOAD_OFFSET(n))
106#define DISPC_OVL_MFLAG_THRESHOLD(n) DISPC_MFLAG_THRESHOLD_OFFSET(n)
107
108/* DISPC up/downsampling FIR filter coefficient structure */
109struct dispc_coef {
110 s8 hc4_vc22;
111 s8 hc3_vc2;
112 u8 hc2_vc1;
113 s8 hc1_vc0;
114 s8 hc0_vc00;
115};
116
117const struct dispc_coef *dispc_ovl_get_scale_coef(int inc, int five_taps);
118
119/* DISPC manager/channel specific registers */
120static inline u16 DISPC_DEFAULT_COLOR(enum omap_channel channel)
121{
122 switch (channel) {
123 case OMAP_DSS_CHANNEL_LCD:
124 return 0x004C;
125 case OMAP_DSS_CHANNEL_DIGIT:
126 return 0x0050;
127 case OMAP_DSS_CHANNEL_LCD2:
128 return 0x03AC;
129 case OMAP_DSS_CHANNEL_LCD3:
130 return 0x0814;
131 default:
132 BUG();
133 return 0;
134 }
135}
136
137static inline u16 DISPC_TRANS_COLOR(enum omap_channel channel)
138{
139 switch (channel) {
140 case OMAP_DSS_CHANNEL_LCD:
141 return 0x0054;
142 case OMAP_DSS_CHANNEL_DIGIT:
143 return 0x0058;
144 case OMAP_DSS_CHANNEL_LCD2:
145 return 0x03B0;
146 case OMAP_DSS_CHANNEL_LCD3:
147 return 0x0818;
148 default:
149 BUG();
150 return 0;
151 }
152}
153
154static inline u16 DISPC_TIMING_H(enum omap_channel channel)
155{
156 switch (channel) {
157 case OMAP_DSS_CHANNEL_LCD:
158 return 0x0064;
159 case OMAP_DSS_CHANNEL_DIGIT:
160 BUG();
161 return 0;
162 case OMAP_DSS_CHANNEL_LCD2:
163 return 0x0400;
164 case OMAP_DSS_CHANNEL_LCD3:
165 return 0x0840;
166 default:
167 BUG();
168 return 0;
169 }
170}
171
172static inline u16 DISPC_TIMING_V(enum omap_channel channel)
173{
174 switch (channel) {
175 case OMAP_DSS_CHANNEL_LCD:
176 return 0x0068;
177 case OMAP_DSS_CHANNEL_DIGIT:
178 BUG();
179 return 0;
180 case OMAP_DSS_CHANNEL_LCD2:
181 return 0x0404;
182 case OMAP_DSS_CHANNEL_LCD3:
183 return 0x0844;
184 default:
185 BUG();
186 return 0;
187 }
188}
189
190static inline u16 DISPC_POL_FREQ(enum omap_channel channel)
191{
192 switch (channel) {
193 case OMAP_DSS_CHANNEL_LCD:
194 return 0x006C;
195 case OMAP_DSS_CHANNEL_DIGIT:
196 BUG();
197 return 0;
198 case OMAP_DSS_CHANNEL_LCD2:
199 return 0x0408;
200 case OMAP_DSS_CHANNEL_LCD3:
201 return 0x083C;
202 default:
203 BUG();
204 return 0;
205 }
206}
207
208static inline u16 DISPC_DIVISORo(enum omap_channel channel)
209{
210 switch (channel) {
211 case OMAP_DSS_CHANNEL_LCD:
212 return 0x0070;
213 case OMAP_DSS_CHANNEL_DIGIT:
214 BUG();
215 return 0;
216 case OMAP_DSS_CHANNEL_LCD2:
217 return 0x040C;
218 case OMAP_DSS_CHANNEL_LCD3:
219 return 0x0838;
220 default:
221 BUG();
222 return 0;
223 }
224}
225
226/* Named as DISPC_SIZE_LCD, DISPC_SIZE_DIGIT and DISPC_SIZE_LCD2 in TRM */
227static inline u16 DISPC_SIZE_MGR(enum omap_channel channel)
228{
229 switch (channel) {
230 case OMAP_DSS_CHANNEL_LCD:
231 return 0x007C;
232 case OMAP_DSS_CHANNEL_DIGIT:
233 return 0x0078;
234 case OMAP_DSS_CHANNEL_LCD2:
235 return 0x03CC;
236 case OMAP_DSS_CHANNEL_LCD3:
237 return 0x0834;
238 default:
239 BUG();
240 return 0;
241 }
242}
243
244static inline u16 DISPC_DATA_CYCLE1(enum omap_channel channel)
245{
246 switch (channel) {
247 case OMAP_DSS_CHANNEL_LCD:
248 return 0x01D4;
249 case OMAP_DSS_CHANNEL_DIGIT:
250 BUG();
251 return 0;
252 case OMAP_DSS_CHANNEL_LCD2:
253 return 0x03C0;
254 case OMAP_DSS_CHANNEL_LCD3:
255 return 0x0828;
256 default:
257 BUG();
258 return 0;
259 }
260}
261
262static inline u16 DISPC_DATA_CYCLE2(enum omap_channel channel)
263{
264 switch (channel) {
265 case OMAP_DSS_CHANNEL_LCD:
266 return 0x01D8;
267 case OMAP_DSS_CHANNEL_DIGIT:
268 BUG();
269 return 0;
270 case OMAP_DSS_CHANNEL_LCD2:
271 return 0x03C4;
272 case OMAP_DSS_CHANNEL_LCD3:
273 return 0x082C;
274 default:
275 BUG();
276 return 0;
277 }
278}
279
280static inline u16 DISPC_DATA_CYCLE3(enum omap_channel channel)
281{
282 switch (channel) {
283 case OMAP_DSS_CHANNEL_LCD:
284 return 0x01DC;
285 case OMAP_DSS_CHANNEL_DIGIT:
286 BUG();
287 return 0;
288 case OMAP_DSS_CHANNEL_LCD2:
289 return 0x03C8;
290 case OMAP_DSS_CHANNEL_LCD3:
291 return 0x0830;
292 default:
293 BUG();
294 return 0;
295 }
296}
297
298static inline u16 DISPC_CPR_COEF_R(enum omap_channel channel)
299{
300 switch (channel) {
301 case OMAP_DSS_CHANNEL_LCD:
302 return 0x0220;
303 case OMAP_DSS_CHANNEL_DIGIT:
304 BUG();
305 return 0;
306 case OMAP_DSS_CHANNEL_LCD2:
307 return 0x03BC;
308 case OMAP_DSS_CHANNEL_LCD3:
309 return 0x0824;
310 default:
311 BUG();
312 return 0;
313 }
314}
315
316static inline u16 DISPC_CPR_COEF_G(enum omap_channel channel)
317{
318 switch (channel) {
319 case OMAP_DSS_CHANNEL_LCD:
320 return 0x0224;
321 case OMAP_DSS_CHANNEL_DIGIT:
322 BUG();
323 return 0;
324 case OMAP_DSS_CHANNEL_LCD2:
325 return 0x03B8;
326 case OMAP_DSS_CHANNEL_LCD3:
327 return 0x0820;
328 default:
329 BUG();
330 return 0;
331 }
332}
333
334static inline u16 DISPC_CPR_COEF_B(enum omap_channel channel)
335{
336 switch (channel) {
337 case OMAP_DSS_CHANNEL_LCD:
338 return 0x0228;
339 case OMAP_DSS_CHANNEL_DIGIT:
340 BUG();
341 return 0;
342 case OMAP_DSS_CHANNEL_LCD2:
343 return 0x03B4;
344 case OMAP_DSS_CHANNEL_LCD3:
345 return 0x081C;
346 default:
347 BUG();
348 return 0;
349 }
350}
351
352/* DISPC overlay register base addresses */
353static inline u16 DISPC_OVL_BASE(enum omap_plane_id plane)
354{
355 switch (plane) {
356 case OMAP_DSS_GFX:
357 return 0x0080;
358 case OMAP_DSS_VIDEO1:
359 return 0x00BC;
360 case OMAP_DSS_VIDEO2:
361 return 0x014C;
362 case OMAP_DSS_VIDEO3:
363 return 0x0300;
364 case OMAP_DSS_WB:
365 return 0x0500;
366 default:
367 BUG();
368 return 0;
369 }
370}
371
372/* DISPC overlay register offsets */
373static inline u16 DISPC_BA0_OFFSET(enum omap_plane_id plane)
374{
375 switch (plane) {
376 case OMAP_DSS_GFX:
377 case OMAP_DSS_VIDEO1:
378 case OMAP_DSS_VIDEO2:
379 return 0x0000;
380 case OMAP_DSS_VIDEO3:
381 case OMAP_DSS_WB:
382 return 0x0008;
383 default:
384 BUG();
385 return 0;
386 }
387}
388
389static inline u16 DISPC_BA1_OFFSET(enum omap_plane_id plane)
390{
391 switch (plane) {
392 case OMAP_DSS_GFX:
393 case OMAP_DSS_VIDEO1:
394 case OMAP_DSS_VIDEO2:
395 return 0x0004;
396 case OMAP_DSS_VIDEO3:
397 case OMAP_DSS_WB:
398 return 0x000C;
399 default:
400 BUG();
401 return 0;
402 }
403}
404
405static inline u16 DISPC_BA0_UV_OFFSET(enum omap_plane_id plane)
406{
407 switch (plane) {
408 case OMAP_DSS_GFX:
409 BUG();
410 return 0;
411 case OMAP_DSS_VIDEO1:
412 return 0x0544;
413 case OMAP_DSS_VIDEO2:
414 return 0x04BC;
415 case OMAP_DSS_VIDEO3:
416 return 0x0310;
417 case OMAP_DSS_WB:
418 return 0x0118;
419 default:
420 BUG();
421 return 0;
422 }
423}
424
425static inline u16 DISPC_BA1_UV_OFFSET(enum omap_plane_id plane)
426{
427 switch (plane) {
428 case OMAP_DSS_GFX:
429 BUG();
430 return 0;
431 case OMAP_DSS_VIDEO1:
432 return 0x0548;
433 case OMAP_DSS_VIDEO2:
434 return 0x04C0;
435 case OMAP_DSS_VIDEO3:
436 return 0x0314;
437 case OMAP_DSS_WB:
438 return 0x011C;
439 default:
440 BUG();
441 return 0;
442 }
443}
444
445static inline u16 DISPC_POS_OFFSET(enum omap_plane_id plane)
446{
447 switch (plane) {
448 case OMAP_DSS_GFX:
449 case OMAP_DSS_VIDEO1:
450 case OMAP_DSS_VIDEO2:
451 return 0x0008;
452 case OMAP_DSS_VIDEO3:
453 return 0x009C;
454 default:
455 BUG();
456 return 0;
457 }
458}
459
460static inline u16 DISPC_SIZE_OFFSET(enum omap_plane_id plane)
461{
462 switch (plane) {
463 case OMAP_DSS_GFX:
464 case OMAP_DSS_VIDEO1:
465 case OMAP_DSS_VIDEO2:
466 return 0x000C;
467 case OMAP_DSS_VIDEO3:
468 case OMAP_DSS_WB:
469 return 0x00A8;
470 default:
471 BUG();
472 return 0;
473 }
474}
475
476static inline u16 DISPC_ATTR_OFFSET(enum omap_plane_id plane)
477{
478 switch (plane) {
479 case OMAP_DSS_GFX:
480 return 0x0020;
481 case OMAP_DSS_VIDEO1:
482 case OMAP_DSS_VIDEO2:
483 return 0x0010;
484 case OMAP_DSS_VIDEO3:
485 case OMAP_DSS_WB:
486 return 0x0070;
487 default:
488 BUG();
489 return 0;
490 }
491}
492
493static inline u16 DISPC_ATTR2_OFFSET(enum omap_plane_id plane)
494{
495 switch (plane) {
496 case OMAP_DSS_GFX:
497 BUG();
498 return 0;
499 case OMAP_DSS_VIDEO1:
500 return 0x0568;
501 case OMAP_DSS_VIDEO2:
502 return 0x04DC;
503 case OMAP_DSS_VIDEO3:
504 return 0x032C;
505 case OMAP_DSS_WB:
506 return 0x0310;
507 default:
508 BUG();
509 return 0;
510 }
511}
512
513static inline u16 DISPC_FIFO_THRESH_OFFSET(enum omap_plane_id plane)
514{
515 switch (plane) {
516 case OMAP_DSS_GFX:
517 return 0x0024;
518 case OMAP_DSS_VIDEO1:
519 case OMAP_DSS_VIDEO2:
520 return 0x0014;
521 case OMAP_DSS_VIDEO3:
522 case OMAP_DSS_WB:
523 return 0x008C;
524 default:
525 BUG();
526 return 0;
527 }
528}
529
530static inline u16 DISPC_FIFO_SIZE_STATUS_OFFSET(enum omap_plane_id plane)
531{
532 switch (plane) {
533 case OMAP_DSS_GFX:
534 return 0x0028;
535 case OMAP_DSS_VIDEO1:
536 case OMAP_DSS_VIDEO2:
537 return 0x0018;
538 case OMAP_DSS_VIDEO3:
539 case OMAP_DSS_WB:
540 return 0x0088;
541 default:
542 BUG();
543 return 0;
544 }
545}
546
547static inline u16 DISPC_ROW_INC_OFFSET(enum omap_plane_id plane)
548{
549 switch (plane) {
550 case OMAP_DSS_GFX:
551 return 0x002C;
552 case OMAP_DSS_VIDEO1:
553 case OMAP_DSS_VIDEO2:
554 return 0x001C;
555 case OMAP_DSS_VIDEO3:
556 case OMAP_DSS_WB:
557 return 0x00A4;
558 default:
559 BUG();
560 return 0;
561 }
562}
563
564static inline u16 DISPC_PIX_INC_OFFSET(enum omap_plane_id plane)
565{
566 switch (plane) {
567 case OMAP_DSS_GFX:
568 return 0x0030;
569 case OMAP_DSS_VIDEO1:
570 case OMAP_DSS_VIDEO2:
571 return 0x0020;
572 case OMAP_DSS_VIDEO3:
573 case OMAP_DSS_WB:
574 return 0x0098;
575 default:
576 BUG();
577 return 0;
578 }
579}
580
581static inline u16 DISPC_WINDOW_SKIP_OFFSET(enum omap_plane_id plane)
582{
583 switch (plane) {
584 case OMAP_DSS_GFX:
585 return 0x0034;
586 case OMAP_DSS_VIDEO1:
587 case OMAP_DSS_VIDEO2:
588 case OMAP_DSS_VIDEO3:
589 BUG();
590 return 0;
591 default:
592 BUG();
593 return 0;
594 }
595}
596
597static inline u16 DISPC_TABLE_BA_OFFSET(enum omap_plane_id plane)
598{
599 switch (plane) {
600 case OMAP_DSS_GFX:
601 return 0x0038;
602 case OMAP_DSS_VIDEO1:
603 case OMAP_DSS_VIDEO2:
604 case OMAP_DSS_VIDEO3:
605 BUG();
606 return 0;
607 default:
608 BUG();
609 return 0;
610 }
611}
612
613static inline u16 DISPC_FIR_OFFSET(enum omap_plane_id plane)
614{
615 switch (plane) {
616 case OMAP_DSS_GFX:
617 BUG();
618 return 0;
619 case OMAP_DSS_VIDEO1:
620 case OMAP_DSS_VIDEO2:
621 return 0x0024;
622 case OMAP_DSS_VIDEO3:
623 case OMAP_DSS_WB:
624 return 0x0090;
625 default:
626 BUG();
627 return 0;
628 }
629}
630
631static inline u16 DISPC_FIR2_OFFSET(enum omap_plane_id plane)
632{
633 switch (plane) {
634 case OMAP_DSS_GFX:
635 BUG();
636 return 0;
637 case OMAP_DSS_VIDEO1:
638 return 0x0580;
639 case OMAP_DSS_VIDEO2:
640 return 0x055C;
641 case OMAP_DSS_VIDEO3:
642 return 0x0424;
643 case OMAP_DSS_WB:
644 return 0x290;
645 default:
646 BUG();
647 return 0;
648 }
649}
650
651static inline u16 DISPC_PIC_SIZE_OFFSET(enum omap_plane_id plane)
652{
653 switch (plane) {
654 case OMAP_DSS_GFX:
655 BUG();
656 return 0;
657 case OMAP_DSS_VIDEO1:
658 case OMAP_DSS_VIDEO2:
659 return 0x0028;
660 case OMAP_DSS_VIDEO3:
661 case OMAP_DSS_WB:
662 return 0x0094;
663 default:
664 BUG();
665 return 0;
666 }
667}
668
669
670static inline u16 DISPC_ACCU0_OFFSET(enum omap_plane_id plane)
671{
672 switch (plane) {
673 case OMAP_DSS_GFX:
674 BUG();
675 return 0;
676 case OMAP_DSS_VIDEO1:
677 case OMAP_DSS_VIDEO2:
678 return 0x002C;
679 case OMAP_DSS_VIDEO3:
680 case OMAP_DSS_WB:
681 return 0x0000;
682 default:
683 BUG();
684 return 0;
685 }
686}
687
688static inline u16 DISPC_ACCU2_0_OFFSET(enum omap_plane_id plane)
689{
690 switch (plane) {
691 case OMAP_DSS_GFX:
692 BUG();
693 return 0;
694 case OMAP_DSS_VIDEO1:
695 return 0x0584;
696 case OMAP_DSS_VIDEO2:
697 return 0x0560;
698 case OMAP_DSS_VIDEO3:
699 return 0x0428;
700 case OMAP_DSS_WB:
701 return 0x0294;
702 default:
703 BUG();
704 return 0;
705 }
706}
707
708static inline u16 DISPC_ACCU1_OFFSET(enum omap_plane_id plane)
709{
710 switch (plane) {
711 case OMAP_DSS_GFX:
712 BUG();
713 return 0;
714 case OMAP_DSS_VIDEO1:
715 case OMAP_DSS_VIDEO2:
716 return 0x0030;
717 case OMAP_DSS_VIDEO3:
718 case OMAP_DSS_WB:
719 return 0x0004;
720 default:
721 BUG();
722 return 0;
723 }
724}
725
726static inline u16 DISPC_ACCU2_1_OFFSET(enum omap_plane_id plane)
727{
728 switch (plane) {
729 case OMAP_DSS_GFX:
730 BUG();
731 return 0;
732 case OMAP_DSS_VIDEO1:
733 return 0x0588;
734 case OMAP_DSS_VIDEO2:
735 return 0x0564;
736 case OMAP_DSS_VIDEO3:
737 return 0x042C;
738 case OMAP_DSS_WB:
739 return 0x0298;
740 default:
741 BUG();
742 return 0;
743 }
744}
745
746/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
747static inline u16 DISPC_FIR_COEF_H_OFFSET(enum omap_plane_id plane, u16 i)
748{
749 switch (plane) {
750 case OMAP_DSS_GFX:
751 BUG();
752 return 0;
753 case OMAP_DSS_VIDEO1:
754 case OMAP_DSS_VIDEO2:
755 return 0x0034 + i * 0x8;
756 case OMAP_DSS_VIDEO3:
757 case OMAP_DSS_WB:
758 return 0x0010 + i * 0x8;
759 default:
760 BUG();
761 return 0;
762 }
763}
764
765/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
766static inline u16 DISPC_FIR_COEF_H2_OFFSET(enum omap_plane_id plane, u16 i)
767{
768 switch (plane) {
769 case OMAP_DSS_GFX:
770 BUG();
771 return 0;
772 case OMAP_DSS_VIDEO1:
773 return 0x058C + i * 0x8;
774 case OMAP_DSS_VIDEO2:
775 return 0x0568 + i * 0x8;
776 case OMAP_DSS_VIDEO3:
777 return 0x0430 + i * 0x8;
778 case OMAP_DSS_WB:
779 return 0x02A0 + i * 0x8;
780 default:
781 BUG();
782 return 0;
783 }
784}
785
786/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
787static inline u16 DISPC_FIR_COEF_HV_OFFSET(enum omap_plane_id plane, u16 i)
788{
789 switch (plane) {
790 case OMAP_DSS_GFX:
791 BUG();
792 return 0;
793 case OMAP_DSS_VIDEO1:
794 case OMAP_DSS_VIDEO2:
795 return 0x0038 + i * 0x8;
796 case OMAP_DSS_VIDEO3:
797 case OMAP_DSS_WB:
798 return 0x0014 + i * 0x8;
799 default:
800 BUG();
801 return 0;
802 }
803}
804
805/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
806static inline u16 DISPC_FIR_COEF_HV2_OFFSET(enum omap_plane_id plane, u16 i)
807{
808 switch (plane) {
809 case OMAP_DSS_GFX:
810 BUG();
811 return 0;
812 case OMAP_DSS_VIDEO1:
813 return 0x0590 + i * 8;
814 case OMAP_DSS_VIDEO2:
815 return 0x056C + i * 0x8;
816 case OMAP_DSS_VIDEO3:
817 return 0x0434 + i * 0x8;
818 case OMAP_DSS_WB:
819 return 0x02A4 + i * 0x8;
820 default:
821 BUG();
822 return 0;
823 }
824}
825
826/* coef index i = {0, 1, 2, 3, 4,} */
827static inline u16 DISPC_CONV_COEF_OFFSET(enum omap_plane_id plane, u16 i)
828{
829 switch (plane) {
830 case OMAP_DSS_GFX:
831 BUG();
832 return 0;
833 case OMAP_DSS_VIDEO1:
834 case OMAP_DSS_VIDEO2:
835 case OMAP_DSS_VIDEO3:
836 case OMAP_DSS_WB:
837 return 0x0074 + i * 0x4;
838 default:
839 BUG();
840 return 0;
841 }
842}
843
844/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
845static inline u16 DISPC_FIR_COEF_V_OFFSET(enum omap_plane_id plane, u16 i)
846{
847 switch (plane) {
848 case OMAP_DSS_GFX:
849 BUG();
850 return 0;
851 case OMAP_DSS_VIDEO1:
852 return 0x0124 + i * 0x4;
853 case OMAP_DSS_VIDEO2:
854 return 0x00B4 + i * 0x4;
855 case OMAP_DSS_VIDEO3:
856 case OMAP_DSS_WB:
857 return 0x0050 + i * 0x4;
858 default:
859 BUG();
860 return 0;
861 }
862}
863
864/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
865static inline u16 DISPC_FIR_COEF_V2_OFFSET(enum omap_plane_id plane, u16 i)
866{
867 switch (plane) {
868 case OMAP_DSS_GFX:
869 BUG();
870 return 0;
871 case OMAP_DSS_VIDEO1:
872 return 0x05CC + i * 0x4;
873 case OMAP_DSS_VIDEO2:
874 return 0x05A8 + i * 0x4;
875 case OMAP_DSS_VIDEO3:
876 return 0x0470 + i * 0x4;
877 case OMAP_DSS_WB:
878 return 0x02E0 + i * 0x4;
879 default:
880 BUG();
881 return 0;
882 }
883}
884
885static inline u16 DISPC_PRELOAD_OFFSET(enum omap_plane_id plane)
886{
887 switch (plane) {
888 case OMAP_DSS_GFX:
889 return 0x01AC;
890 case OMAP_DSS_VIDEO1:
891 return 0x0174;
892 case OMAP_DSS_VIDEO2:
893 return 0x00E8;
894 case OMAP_DSS_VIDEO3:
895 return 0x00A0;
896 default:
897 BUG();
898 return 0;
899 }
900}
901
902static inline u16 DISPC_MFLAG_THRESHOLD_OFFSET(enum omap_plane_id plane)
903{
904 switch (plane) {
905 case OMAP_DSS_GFX:
906 return 0x0860;
907 case OMAP_DSS_VIDEO1:
908 return 0x0864;
909 case OMAP_DSS_VIDEO2:
910 return 0x0868;
911 case OMAP_DSS_VIDEO3:
912 return 0x086c;
913 case OMAP_DSS_WB:
914 return 0x0870;
915 default:
916 BUG();
917 return 0;
918 }
919}
920#endif