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1/*
2 * linux/drivers/video/omap2/dss/dispc.h
3 *
4 * Copyright (C) 2011 Texas Instruments
5 * Author: Archit Taneja <archit@ti.com>
6 *
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published by
10 * the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#ifndef __OMAP2_DISPC_REG_H
22#define __OMAP2_DISPC_REG_H
23
24/* DISPC common registers */
25#define DISPC_REVISION 0x0000
26#define DISPC_SYSCONFIG 0x0010
27#define DISPC_SYSSTATUS 0x0014
28#define DISPC_IRQSTATUS 0x0018
29#define DISPC_IRQENABLE 0x001C
30#define DISPC_CONTROL 0x0040
31#define DISPC_CONFIG 0x0044
32#define DISPC_CAPABLE 0x0048
33#define DISPC_LINE_STATUS 0x005C
34#define DISPC_LINE_NUMBER 0x0060
35#define DISPC_GLOBAL_ALPHA 0x0074
36#define DISPC_CONTROL2 0x0238
37#define DISPC_CONFIG2 0x0620
38#define DISPC_DIVISOR 0x0804
39#define DISPC_GLOBAL_BUFFER 0x0800
40#define DISPC_CONTROL3 0x0848
41#define DISPC_CONFIG3 0x084C
42#define DISPC_MSTANDBY_CTRL 0x0858
43#define DISPC_GLOBAL_MFLAG_ATTRIBUTE 0x085C
44
45/* DISPC overlay registers */
46#define DISPC_OVL_BA0(n) (DISPC_OVL_BASE(n) + \
47 DISPC_BA0_OFFSET(n))
48#define DISPC_OVL_BA1(n) (DISPC_OVL_BASE(n) + \
49 DISPC_BA1_OFFSET(n))
50#define DISPC_OVL_BA0_UV(n) (DISPC_OVL_BASE(n) + \
51 DISPC_BA0_UV_OFFSET(n))
52#define DISPC_OVL_BA1_UV(n) (DISPC_OVL_BASE(n) + \
53 DISPC_BA1_UV_OFFSET(n))
54#define DISPC_OVL_POSITION(n) (DISPC_OVL_BASE(n) + \
55 DISPC_POS_OFFSET(n))
56#define DISPC_OVL_SIZE(n) (DISPC_OVL_BASE(n) + \
57 DISPC_SIZE_OFFSET(n))
58#define DISPC_OVL_ATTRIBUTES(n) (DISPC_OVL_BASE(n) + \
59 DISPC_ATTR_OFFSET(n))
60#define DISPC_OVL_ATTRIBUTES2(n) (DISPC_OVL_BASE(n) + \
61 DISPC_ATTR2_OFFSET(n))
62#define DISPC_OVL_FIFO_THRESHOLD(n) (DISPC_OVL_BASE(n) + \
63 DISPC_FIFO_THRESH_OFFSET(n))
64#define DISPC_OVL_FIFO_SIZE_STATUS(n) (DISPC_OVL_BASE(n) + \
65 DISPC_FIFO_SIZE_STATUS_OFFSET(n))
66#define DISPC_OVL_ROW_INC(n) (DISPC_OVL_BASE(n) + \
67 DISPC_ROW_INC_OFFSET(n))
68#define DISPC_OVL_PIXEL_INC(n) (DISPC_OVL_BASE(n) + \
69 DISPC_PIX_INC_OFFSET(n))
70#define DISPC_OVL_WINDOW_SKIP(n) (DISPC_OVL_BASE(n) + \
71 DISPC_WINDOW_SKIP_OFFSET(n))
72#define DISPC_OVL_TABLE_BA(n) (DISPC_OVL_BASE(n) + \
73 DISPC_TABLE_BA_OFFSET(n))
74#define DISPC_OVL_FIR(n) (DISPC_OVL_BASE(n) + \
75 DISPC_FIR_OFFSET(n))
76#define DISPC_OVL_FIR2(n) (DISPC_OVL_BASE(n) + \
77 DISPC_FIR2_OFFSET(n))
78#define DISPC_OVL_PICTURE_SIZE(n) (DISPC_OVL_BASE(n) + \
79 DISPC_PIC_SIZE_OFFSET(n))
80#define DISPC_OVL_ACCU0(n) (DISPC_OVL_BASE(n) + \
81 DISPC_ACCU0_OFFSET(n))
82#define DISPC_OVL_ACCU1(n) (DISPC_OVL_BASE(n) + \
83 DISPC_ACCU1_OFFSET(n))
84#define DISPC_OVL_ACCU2_0(n) (DISPC_OVL_BASE(n) + \
85 DISPC_ACCU2_0_OFFSET(n))
86#define DISPC_OVL_ACCU2_1(n) (DISPC_OVL_BASE(n) + \
87 DISPC_ACCU2_1_OFFSET(n))
88#define DISPC_OVL_FIR_COEF_H(n, i) (DISPC_OVL_BASE(n) + \
89 DISPC_FIR_COEF_H_OFFSET(n, i))
90#define DISPC_OVL_FIR_COEF_HV(n, i) (DISPC_OVL_BASE(n) + \
91 DISPC_FIR_COEF_HV_OFFSET(n, i))
92#define DISPC_OVL_FIR_COEF_H2(n, i) (DISPC_OVL_BASE(n) + \
93 DISPC_FIR_COEF_H2_OFFSET(n, i))
94#define DISPC_OVL_FIR_COEF_HV2(n, i) (DISPC_OVL_BASE(n) + \
95 DISPC_FIR_COEF_HV2_OFFSET(n, i))
96#define DISPC_OVL_CONV_COEF(n, i) (DISPC_OVL_BASE(n) + \
97 DISPC_CONV_COEF_OFFSET(n, i))
98#define DISPC_OVL_FIR_COEF_V(n, i) (DISPC_OVL_BASE(n) + \
99 DISPC_FIR_COEF_V_OFFSET(n, i))
100#define DISPC_OVL_FIR_COEF_V2(n, i) (DISPC_OVL_BASE(n) + \
101 DISPC_FIR_COEF_V2_OFFSET(n, i))
102#define DISPC_OVL_PRELOAD(n) (DISPC_OVL_BASE(n) + \
103 DISPC_PRELOAD_OFFSET(n))
104#define DISPC_OVL_MFLAG_THRESHOLD(n) DISPC_MFLAG_THRESHOLD_OFFSET(n)
105
106/* DISPC up/downsampling FIR filter coefficient structure */
107struct dispc_coef {
108 s8 hc4_vc22;
109 s8 hc3_vc2;
110 u8 hc2_vc1;
111 s8 hc1_vc0;
112 s8 hc0_vc00;
113};
114
115const struct dispc_coef *dispc_ovl_get_scale_coef(int inc, int five_taps);
116
117/* DISPC manager/channel specific registers */
118static inline u16 DISPC_DEFAULT_COLOR(enum omap_channel channel)
119{
120 switch (channel) {
121 case OMAP_DSS_CHANNEL_LCD:
122 return 0x004C;
123 case OMAP_DSS_CHANNEL_DIGIT:
124 return 0x0050;
125 case OMAP_DSS_CHANNEL_LCD2:
126 return 0x03AC;
127 case OMAP_DSS_CHANNEL_LCD3:
128 return 0x0814;
129 default:
130 BUG();
131 return 0;
132 }
133}
134
135static inline u16 DISPC_TRANS_COLOR(enum omap_channel channel)
136{
137 switch (channel) {
138 case OMAP_DSS_CHANNEL_LCD:
139 return 0x0054;
140 case OMAP_DSS_CHANNEL_DIGIT:
141 return 0x0058;
142 case OMAP_DSS_CHANNEL_LCD2:
143 return 0x03B0;
144 case OMAP_DSS_CHANNEL_LCD3:
145 return 0x0818;
146 default:
147 BUG();
148 return 0;
149 }
150}
151
152static inline u16 DISPC_TIMING_H(enum omap_channel channel)
153{
154 switch (channel) {
155 case OMAP_DSS_CHANNEL_LCD:
156 return 0x0064;
157 case OMAP_DSS_CHANNEL_DIGIT:
158 BUG();
159 return 0;
160 case OMAP_DSS_CHANNEL_LCD2:
161 return 0x0400;
162 case OMAP_DSS_CHANNEL_LCD3:
163 return 0x0840;
164 default:
165 BUG();
166 return 0;
167 }
168}
169
170static inline u16 DISPC_TIMING_V(enum omap_channel channel)
171{
172 switch (channel) {
173 case OMAP_DSS_CHANNEL_LCD:
174 return 0x0068;
175 case OMAP_DSS_CHANNEL_DIGIT:
176 BUG();
177 return 0;
178 case OMAP_DSS_CHANNEL_LCD2:
179 return 0x0404;
180 case OMAP_DSS_CHANNEL_LCD3:
181 return 0x0844;
182 default:
183 BUG();
184 return 0;
185 }
186}
187
188static inline u16 DISPC_POL_FREQ(enum omap_channel channel)
189{
190 switch (channel) {
191 case OMAP_DSS_CHANNEL_LCD:
192 return 0x006C;
193 case OMAP_DSS_CHANNEL_DIGIT:
194 BUG();
195 return 0;
196 case OMAP_DSS_CHANNEL_LCD2:
197 return 0x0408;
198 case OMAP_DSS_CHANNEL_LCD3:
199 return 0x083C;
200 default:
201 BUG();
202 return 0;
203 }
204}
205
206static inline u16 DISPC_DIVISORo(enum omap_channel channel)
207{
208 switch (channel) {
209 case OMAP_DSS_CHANNEL_LCD:
210 return 0x0070;
211 case OMAP_DSS_CHANNEL_DIGIT:
212 BUG();
213 return 0;
214 case OMAP_DSS_CHANNEL_LCD2:
215 return 0x040C;
216 case OMAP_DSS_CHANNEL_LCD3:
217 return 0x0838;
218 default:
219 BUG();
220 return 0;
221 }
222}
223
224/* Named as DISPC_SIZE_LCD, DISPC_SIZE_DIGIT and DISPC_SIZE_LCD2 in TRM */
225static inline u16 DISPC_SIZE_MGR(enum omap_channel channel)
226{
227 switch (channel) {
228 case OMAP_DSS_CHANNEL_LCD:
229 return 0x007C;
230 case OMAP_DSS_CHANNEL_DIGIT:
231 return 0x0078;
232 case OMAP_DSS_CHANNEL_LCD2:
233 return 0x03CC;
234 case OMAP_DSS_CHANNEL_LCD3:
235 return 0x0834;
236 default:
237 BUG();
238 return 0;
239 }
240}
241
242static inline u16 DISPC_DATA_CYCLE1(enum omap_channel channel)
243{
244 switch (channel) {
245 case OMAP_DSS_CHANNEL_LCD:
246 return 0x01D4;
247 case OMAP_DSS_CHANNEL_DIGIT:
248 BUG();
249 return 0;
250 case OMAP_DSS_CHANNEL_LCD2:
251 return 0x03C0;
252 case OMAP_DSS_CHANNEL_LCD3:
253 return 0x0828;
254 default:
255 BUG();
256 return 0;
257 }
258}
259
260static inline u16 DISPC_DATA_CYCLE2(enum omap_channel channel)
261{
262 switch (channel) {
263 case OMAP_DSS_CHANNEL_LCD:
264 return 0x01D8;
265 case OMAP_DSS_CHANNEL_DIGIT:
266 BUG();
267 return 0;
268 case OMAP_DSS_CHANNEL_LCD2:
269 return 0x03C4;
270 case OMAP_DSS_CHANNEL_LCD3:
271 return 0x082C;
272 default:
273 BUG();
274 return 0;
275 }
276}
277
278static inline u16 DISPC_DATA_CYCLE3(enum omap_channel channel)
279{
280 switch (channel) {
281 case OMAP_DSS_CHANNEL_LCD:
282 return 0x01DC;
283 case OMAP_DSS_CHANNEL_DIGIT:
284 BUG();
285 return 0;
286 case OMAP_DSS_CHANNEL_LCD2:
287 return 0x03C8;
288 case OMAP_DSS_CHANNEL_LCD3:
289 return 0x0830;
290 default:
291 BUG();
292 return 0;
293 }
294}
295
296static inline u16 DISPC_CPR_COEF_R(enum omap_channel channel)
297{
298 switch (channel) {
299 case OMAP_DSS_CHANNEL_LCD:
300 return 0x0220;
301 case OMAP_DSS_CHANNEL_DIGIT:
302 BUG();
303 return 0;
304 case OMAP_DSS_CHANNEL_LCD2:
305 return 0x03BC;
306 case OMAP_DSS_CHANNEL_LCD3:
307 return 0x0824;
308 default:
309 BUG();
310 return 0;
311 }
312}
313
314static inline u16 DISPC_CPR_COEF_G(enum omap_channel channel)
315{
316 switch (channel) {
317 case OMAP_DSS_CHANNEL_LCD:
318 return 0x0224;
319 case OMAP_DSS_CHANNEL_DIGIT:
320 BUG();
321 return 0;
322 case OMAP_DSS_CHANNEL_LCD2:
323 return 0x03B8;
324 case OMAP_DSS_CHANNEL_LCD3:
325 return 0x0820;
326 default:
327 BUG();
328 return 0;
329 }
330}
331
332static inline u16 DISPC_CPR_COEF_B(enum omap_channel channel)
333{
334 switch (channel) {
335 case OMAP_DSS_CHANNEL_LCD:
336 return 0x0228;
337 case OMAP_DSS_CHANNEL_DIGIT:
338 BUG();
339 return 0;
340 case OMAP_DSS_CHANNEL_LCD2:
341 return 0x03B4;
342 case OMAP_DSS_CHANNEL_LCD3:
343 return 0x081C;
344 default:
345 BUG();
346 return 0;
347 }
348}
349
350/* DISPC overlay register base addresses */
351static inline u16 DISPC_OVL_BASE(enum omap_plane plane)
352{
353 switch (plane) {
354 case OMAP_DSS_GFX:
355 return 0x0080;
356 case OMAP_DSS_VIDEO1:
357 return 0x00BC;
358 case OMAP_DSS_VIDEO2:
359 return 0x014C;
360 case OMAP_DSS_VIDEO3:
361 return 0x0300;
362 case OMAP_DSS_WB:
363 return 0x0500;
364 default:
365 BUG();
366 return 0;
367 }
368}
369
370/* DISPC overlay register offsets */
371static inline u16 DISPC_BA0_OFFSET(enum omap_plane plane)
372{
373 switch (plane) {
374 case OMAP_DSS_GFX:
375 case OMAP_DSS_VIDEO1:
376 case OMAP_DSS_VIDEO2:
377 return 0x0000;
378 case OMAP_DSS_VIDEO3:
379 case OMAP_DSS_WB:
380 return 0x0008;
381 default:
382 BUG();
383 return 0;
384 }
385}
386
387static inline u16 DISPC_BA1_OFFSET(enum omap_plane plane)
388{
389 switch (plane) {
390 case OMAP_DSS_GFX:
391 case OMAP_DSS_VIDEO1:
392 case OMAP_DSS_VIDEO2:
393 return 0x0004;
394 case OMAP_DSS_VIDEO3:
395 case OMAP_DSS_WB:
396 return 0x000C;
397 default:
398 BUG();
399 return 0;
400 }
401}
402
403static inline u16 DISPC_BA0_UV_OFFSET(enum omap_plane plane)
404{
405 switch (plane) {
406 case OMAP_DSS_GFX:
407 BUG();
408 return 0;
409 case OMAP_DSS_VIDEO1:
410 return 0x0544;
411 case OMAP_DSS_VIDEO2:
412 return 0x04BC;
413 case OMAP_DSS_VIDEO3:
414 return 0x0310;
415 case OMAP_DSS_WB:
416 return 0x0118;
417 default:
418 BUG();
419 return 0;
420 }
421}
422
423static inline u16 DISPC_BA1_UV_OFFSET(enum omap_plane plane)
424{
425 switch (plane) {
426 case OMAP_DSS_GFX:
427 BUG();
428 return 0;
429 case OMAP_DSS_VIDEO1:
430 return 0x0548;
431 case OMAP_DSS_VIDEO2:
432 return 0x04C0;
433 case OMAP_DSS_VIDEO3:
434 return 0x0314;
435 case OMAP_DSS_WB:
436 return 0x011C;
437 default:
438 BUG();
439 return 0;
440 }
441}
442
443static inline u16 DISPC_POS_OFFSET(enum omap_plane plane)
444{
445 switch (plane) {
446 case OMAP_DSS_GFX:
447 case OMAP_DSS_VIDEO1:
448 case OMAP_DSS_VIDEO2:
449 return 0x0008;
450 case OMAP_DSS_VIDEO3:
451 return 0x009C;
452 default:
453 BUG();
454 return 0;
455 }
456}
457
458static inline u16 DISPC_SIZE_OFFSET(enum omap_plane plane)
459{
460 switch (plane) {
461 case OMAP_DSS_GFX:
462 case OMAP_DSS_VIDEO1:
463 case OMAP_DSS_VIDEO2:
464 return 0x000C;
465 case OMAP_DSS_VIDEO3:
466 case OMAP_DSS_WB:
467 return 0x00A8;
468 default:
469 BUG();
470 return 0;
471 }
472}
473
474static inline u16 DISPC_ATTR_OFFSET(enum omap_plane plane)
475{
476 switch (plane) {
477 case OMAP_DSS_GFX:
478 return 0x0020;
479 case OMAP_DSS_VIDEO1:
480 case OMAP_DSS_VIDEO2:
481 return 0x0010;
482 case OMAP_DSS_VIDEO3:
483 case OMAP_DSS_WB:
484 return 0x0070;
485 default:
486 BUG();
487 return 0;
488 }
489}
490
491static inline u16 DISPC_ATTR2_OFFSET(enum omap_plane plane)
492{
493 switch (plane) {
494 case OMAP_DSS_GFX:
495 BUG();
496 return 0;
497 case OMAP_DSS_VIDEO1:
498 return 0x0568;
499 case OMAP_DSS_VIDEO2:
500 return 0x04DC;
501 case OMAP_DSS_VIDEO3:
502 return 0x032C;
503 case OMAP_DSS_WB:
504 return 0x0310;
505 default:
506 BUG();
507 return 0;
508 }
509}
510
511static inline u16 DISPC_FIFO_THRESH_OFFSET(enum omap_plane plane)
512{
513 switch (plane) {
514 case OMAP_DSS_GFX:
515 return 0x0024;
516 case OMAP_DSS_VIDEO1:
517 case OMAP_DSS_VIDEO2:
518 return 0x0014;
519 case OMAP_DSS_VIDEO3:
520 case OMAP_DSS_WB:
521 return 0x008C;
522 default:
523 BUG();
524 return 0;
525 }
526}
527
528static inline u16 DISPC_FIFO_SIZE_STATUS_OFFSET(enum omap_plane plane)
529{
530 switch (plane) {
531 case OMAP_DSS_GFX:
532 return 0x0028;
533 case OMAP_DSS_VIDEO1:
534 case OMAP_DSS_VIDEO2:
535 return 0x0018;
536 case OMAP_DSS_VIDEO3:
537 case OMAP_DSS_WB:
538 return 0x0088;
539 default:
540 BUG();
541 return 0;
542 }
543}
544
545static inline u16 DISPC_ROW_INC_OFFSET(enum omap_plane plane)
546{
547 switch (plane) {
548 case OMAP_DSS_GFX:
549 return 0x002C;
550 case OMAP_DSS_VIDEO1:
551 case OMAP_DSS_VIDEO2:
552 return 0x001C;
553 case OMAP_DSS_VIDEO3:
554 case OMAP_DSS_WB:
555 return 0x00A4;
556 default:
557 BUG();
558 return 0;
559 }
560}
561
562static inline u16 DISPC_PIX_INC_OFFSET(enum omap_plane plane)
563{
564 switch (plane) {
565 case OMAP_DSS_GFX:
566 return 0x0030;
567 case OMAP_DSS_VIDEO1:
568 case OMAP_DSS_VIDEO2:
569 return 0x0020;
570 case OMAP_DSS_VIDEO3:
571 case OMAP_DSS_WB:
572 return 0x0098;
573 default:
574 BUG();
575 return 0;
576 }
577}
578
579static inline u16 DISPC_WINDOW_SKIP_OFFSET(enum omap_plane plane)
580{
581 switch (plane) {
582 case OMAP_DSS_GFX:
583 return 0x0034;
584 case OMAP_DSS_VIDEO1:
585 case OMAP_DSS_VIDEO2:
586 case OMAP_DSS_VIDEO3:
587 BUG();
588 return 0;
589 default:
590 BUG();
591 return 0;
592 }
593}
594
595static inline u16 DISPC_TABLE_BA_OFFSET(enum omap_plane plane)
596{
597 switch (plane) {
598 case OMAP_DSS_GFX:
599 return 0x0038;
600 case OMAP_DSS_VIDEO1:
601 case OMAP_DSS_VIDEO2:
602 case OMAP_DSS_VIDEO3:
603 BUG();
604 return 0;
605 default:
606 BUG();
607 return 0;
608 }
609}
610
611static inline u16 DISPC_FIR_OFFSET(enum omap_plane plane)
612{
613 switch (plane) {
614 case OMAP_DSS_GFX:
615 BUG();
616 return 0;
617 case OMAP_DSS_VIDEO1:
618 case OMAP_DSS_VIDEO2:
619 return 0x0024;
620 case OMAP_DSS_VIDEO3:
621 case OMAP_DSS_WB:
622 return 0x0090;
623 default:
624 BUG();
625 return 0;
626 }
627}
628
629static inline u16 DISPC_FIR2_OFFSET(enum omap_plane plane)
630{
631 switch (plane) {
632 case OMAP_DSS_GFX:
633 BUG();
634 return 0;
635 case OMAP_DSS_VIDEO1:
636 return 0x0580;
637 case OMAP_DSS_VIDEO2:
638 return 0x055C;
639 case OMAP_DSS_VIDEO3:
640 return 0x0424;
641 case OMAP_DSS_WB:
642 return 0x290;
643 default:
644 BUG();
645 return 0;
646 }
647}
648
649static inline u16 DISPC_PIC_SIZE_OFFSET(enum omap_plane plane)
650{
651 switch (plane) {
652 case OMAP_DSS_GFX:
653 BUG();
654 return 0;
655 case OMAP_DSS_VIDEO1:
656 case OMAP_DSS_VIDEO2:
657 return 0x0028;
658 case OMAP_DSS_VIDEO3:
659 case OMAP_DSS_WB:
660 return 0x0094;
661 default:
662 BUG();
663 return 0;
664 }
665}
666
667
668static inline u16 DISPC_ACCU0_OFFSET(enum omap_plane plane)
669{
670 switch (plane) {
671 case OMAP_DSS_GFX:
672 BUG();
673 return 0;
674 case OMAP_DSS_VIDEO1:
675 case OMAP_DSS_VIDEO2:
676 return 0x002C;
677 case OMAP_DSS_VIDEO3:
678 case OMAP_DSS_WB:
679 return 0x0000;
680 default:
681 BUG();
682 return 0;
683 }
684}
685
686static inline u16 DISPC_ACCU2_0_OFFSET(enum omap_plane plane)
687{
688 switch (plane) {
689 case OMAP_DSS_GFX:
690 BUG();
691 return 0;
692 case OMAP_DSS_VIDEO1:
693 return 0x0584;
694 case OMAP_DSS_VIDEO2:
695 return 0x0560;
696 case OMAP_DSS_VIDEO3:
697 return 0x0428;
698 case OMAP_DSS_WB:
699 return 0x0294;
700 default:
701 BUG();
702 return 0;
703 }
704}
705
706static inline u16 DISPC_ACCU1_OFFSET(enum omap_plane plane)
707{
708 switch (plane) {
709 case OMAP_DSS_GFX:
710 BUG();
711 return 0;
712 case OMAP_DSS_VIDEO1:
713 case OMAP_DSS_VIDEO2:
714 return 0x0030;
715 case OMAP_DSS_VIDEO3:
716 case OMAP_DSS_WB:
717 return 0x0004;
718 default:
719 BUG();
720 return 0;
721 }
722}
723
724static inline u16 DISPC_ACCU2_1_OFFSET(enum omap_plane plane)
725{
726 switch (plane) {
727 case OMAP_DSS_GFX:
728 BUG();
729 return 0;
730 case OMAP_DSS_VIDEO1:
731 return 0x0588;
732 case OMAP_DSS_VIDEO2:
733 return 0x0564;
734 case OMAP_DSS_VIDEO3:
735 return 0x042C;
736 case OMAP_DSS_WB:
737 return 0x0298;
738 default:
739 BUG();
740 return 0;
741 }
742}
743
744/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
745static inline u16 DISPC_FIR_COEF_H_OFFSET(enum omap_plane plane, u16 i)
746{
747 switch (plane) {
748 case OMAP_DSS_GFX:
749 BUG();
750 return 0;
751 case OMAP_DSS_VIDEO1:
752 case OMAP_DSS_VIDEO2:
753 return 0x0034 + i * 0x8;
754 case OMAP_DSS_VIDEO3:
755 case OMAP_DSS_WB:
756 return 0x0010 + i * 0x8;
757 default:
758 BUG();
759 return 0;
760 }
761}
762
763/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
764static inline u16 DISPC_FIR_COEF_H2_OFFSET(enum omap_plane plane, u16 i)
765{
766 switch (plane) {
767 case OMAP_DSS_GFX:
768 BUG();
769 return 0;
770 case OMAP_DSS_VIDEO1:
771 return 0x058C + i * 0x8;
772 case OMAP_DSS_VIDEO2:
773 return 0x0568 + i * 0x8;
774 case OMAP_DSS_VIDEO3:
775 return 0x0430 + i * 0x8;
776 case OMAP_DSS_WB:
777 return 0x02A0 + i * 0x8;
778 default:
779 BUG();
780 return 0;
781 }
782}
783
784/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
785static inline u16 DISPC_FIR_COEF_HV_OFFSET(enum omap_plane plane, u16 i)
786{
787 switch (plane) {
788 case OMAP_DSS_GFX:
789 BUG();
790 return 0;
791 case OMAP_DSS_VIDEO1:
792 case OMAP_DSS_VIDEO2:
793 return 0x0038 + i * 0x8;
794 case OMAP_DSS_VIDEO3:
795 case OMAP_DSS_WB:
796 return 0x0014 + i * 0x8;
797 default:
798 BUG();
799 return 0;
800 }
801}
802
803/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
804static inline u16 DISPC_FIR_COEF_HV2_OFFSET(enum omap_plane plane, u16 i)
805{
806 switch (plane) {
807 case OMAP_DSS_GFX:
808 BUG();
809 return 0;
810 case OMAP_DSS_VIDEO1:
811 return 0x0590 + i * 8;
812 case OMAP_DSS_VIDEO2:
813 return 0x056C + i * 0x8;
814 case OMAP_DSS_VIDEO3:
815 return 0x0434 + i * 0x8;
816 case OMAP_DSS_WB:
817 return 0x02A4 + i * 0x8;
818 default:
819 BUG();
820 return 0;
821 }
822}
823
824/* coef index i = {0, 1, 2, 3, 4,} */
825static inline u16 DISPC_CONV_COEF_OFFSET(enum omap_plane plane, u16 i)
826{
827 switch (plane) {
828 case OMAP_DSS_GFX:
829 BUG();
830 return 0;
831 case OMAP_DSS_VIDEO1:
832 case OMAP_DSS_VIDEO2:
833 case OMAP_DSS_VIDEO3:
834 case OMAP_DSS_WB:
835 return 0x0074 + i * 0x4;
836 default:
837 BUG();
838 return 0;
839 }
840}
841
842/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
843static inline u16 DISPC_FIR_COEF_V_OFFSET(enum omap_plane plane, u16 i)
844{
845 switch (plane) {
846 case OMAP_DSS_GFX:
847 BUG();
848 return 0;
849 case OMAP_DSS_VIDEO1:
850 return 0x0124 + i * 0x4;
851 case OMAP_DSS_VIDEO2:
852 return 0x00B4 + i * 0x4;
853 case OMAP_DSS_VIDEO3:
854 case OMAP_DSS_WB:
855 return 0x0050 + i * 0x4;
856 default:
857 BUG();
858 return 0;
859 }
860}
861
862/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
863static inline u16 DISPC_FIR_COEF_V2_OFFSET(enum omap_plane plane, u16 i)
864{
865 switch (plane) {
866 case OMAP_DSS_GFX:
867 BUG();
868 return 0;
869 case OMAP_DSS_VIDEO1:
870 return 0x05CC + i * 0x4;
871 case OMAP_DSS_VIDEO2:
872 return 0x05A8 + i * 0x4;
873 case OMAP_DSS_VIDEO3:
874 return 0x0470 + i * 0x4;
875 case OMAP_DSS_WB:
876 return 0x02E0 + i * 0x4;
877 default:
878 BUG();
879 return 0;
880 }
881}
882
883static inline u16 DISPC_PRELOAD_OFFSET(enum omap_plane plane)
884{
885 switch (plane) {
886 case OMAP_DSS_GFX:
887 return 0x01AC;
888 case OMAP_DSS_VIDEO1:
889 return 0x0174;
890 case OMAP_DSS_VIDEO2:
891 return 0x00E8;
892 case OMAP_DSS_VIDEO3:
893 return 0x00A0;
894 default:
895 BUG();
896 return 0;
897 }
898}
899
900static inline u16 DISPC_MFLAG_THRESHOLD_OFFSET(enum omap_plane plane)
901{
902 switch (plane) {
903 case OMAP_DSS_GFX:
904 return 0x0860;
905 case OMAP_DSS_VIDEO1:
906 return 0x0864;
907 case OMAP_DSS_VIDEO2:
908 return 0x0868;
909 case OMAP_DSS_VIDEO3:
910 return 0x086c;
911 case OMAP_DSS_WB:
912 return 0x0870;
913 default:
914 BUG();
915 return 0;
916 }
917}
918#endif
1/*
2 * linux/drivers/video/omap2/dss/dispc.h
3 *
4 * Copyright (C) 2011 Texas Instruments
5 * Author: Archit Taneja <archit@ti.com>
6 *
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published by
10 * the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#ifndef __OMAP2_DISPC_REG_H
22#define __OMAP2_DISPC_REG_H
23
24/* DISPC common registers */
25#define DISPC_REVISION 0x0000
26#define DISPC_SYSCONFIG 0x0010
27#define DISPC_SYSSTATUS 0x0014
28#define DISPC_IRQSTATUS 0x0018
29#define DISPC_IRQENABLE 0x001C
30#define DISPC_CONTROL 0x0040
31#define DISPC_CONFIG 0x0044
32#define DISPC_CAPABLE 0x0048
33#define DISPC_LINE_STATUS 0x005C
34#define DISPC_LINE_NUMBER 0x0060
35#define DISPC_GLOBAL_ALPHA 0x0074
36#define DISPC_CONTROL2 0x0238
37#define DISPC_CONFIG2 0x0620
38#define DISPC_DIVISOR 0x0804
39#define DISPC_GLOBAL_BUFFER 0x0800
40#define DISPC_CONTROL3 0x0848
41#define DISPC_CONFIG3 0x084C
42#define DISPC_MSTANDBY_CTRL 0x0858
43#define DISPC_GLOBAL_MFLAG_ATTRIBUTE 0x085C
44
45#define DISPC_GAMMA_TABLE0 0x0630
46#define DISPC_GAMMA_TABLE1 0x0634
47#define DISPC_GAMMA_TABLE2 0x0638
48#define DISPC_GAMMA_TABLE3 0x0850
49
50/* DISPC overlay registers */
51#define DISPC_OVL_BA0(n) (DISPC_OVL_BASE(n) + \
52 DISPC_BA0_OFFSET(n))
53#define DISPC_OVL_BA1(n) (DISPC_OVL_BASE(n) + \
54 DISPC_BA1_OFFSET(n))
55#define DISPC_OVL_BA0_UV(n) (DISPC_OVL_BASE(n) + \
56 DISPC_BA0_UV_OFFSET(n))
57#define DISPC_OVL_BA1_UV(n) (DISPC_OVL_BASE(n) + \
58 DISPC_BA1_UV_OFFSET(n))
59#define DISPC_OVL_POSITION(n) (DISPC_OVL_BASE(n) + \
60 DISPC_POS_OFFSET(n))
61#define DISPC_OVL_SIZE(n) (DISPC_OVL_BASE(n) + \
62 DISPC_SIZE_OFFSET(n))
63#define DISPC_OVL_ATTRIBUTES(n) (DISPC_OVL_BASE(n) + \
64 DISPC_ATTR_OFFSET(n))
65#define DISPC_OVL_ATTRIBUTES2(n) (DISPC_OVL_BASE(n) + \
66 DISPC_ATTR2_OFFSET(n))
67#define DISPC_OVL_FIFO_THRESHOLD(n) (DISPC_OVL_BASE(n) + \
68 DISPC_FIFO_THRESH_OFFSET(n))
69#define DISPC_OVL_FIFO_SIZE_STATUS(n) (DISPC_OVL_BASE(n) + \
70 DISPC_FIFO_SIZE_STATUS_OFFSET(n))
71#define DISPC_OVL_ROW_INC(n) (DISPC_OVL_BASE(n) + \
72 DISPC_ROW_INC_OFFSET(n))
73#define DISPC_OVL_PIXEL_INC(n) (DISPC_OVL_BASE(n) + \
74 DISPC_PIX_INC_OFFSET(n))
75#define DISPC_OVL_WINDOW_SKIP(n) (DISPC_OVL_BASE(n) + \
76 DISPC_WINDOW_SKIP_OFFSET(n))
77#define DISPC_OVL_TABLE_BA(n) (DISPC_OVL_BASE(n) + \
78 DISPC_TABLE_BA_OFFSET(n))
79#define DISPC_OVL_FIR(n) (DISPC_OVL_BASE(n) + \
80 DISPC_FIR_OFFSET(n))
81#define DISPC_OVL_FIR2(n) (DISPC_OVL_BASE(n) + \
82 DISPC_FIR2_OFFSET(n))
83#define DISPC_OVL_PICTURE_SIZE(n) (DISPC_OVL_BASE(n) + \
84 DISPC_PIC_SIZE_OFFSET(n))
85#define DISPC_OVL_ACCU0(n) (DISPC_OVL_BASE(n) + \
86 DISPC_ACCU0_OFFSET(n))
87#define DISPC_OVL_ACCU1(n) (DISPC_OVL_BASE(n) + \
88 DISPC_ACCU1_OFFSET(n))
89#define DISPC_OVL_ACCU2_0(n) (DISPC_OVL_BASE(n) + \
90 DISPC_ACCU2_0_OFFSET(n))
91#define DISPC_OVL_ACCU2_1(n) (DISPC_OVL_BASE(n) + \
92 DISPC_ACCU2_1_OFFSET(n))
93#define DISPC_OVL_FIR_COEF_H(n, i) (DISPC_OVL_BASE(n) + \
94 DISPC_FIR_COEF_H_OFFSET(n, i))
95#define DISPC_OVL_FIR_COEF_HV(n, i) (DISPC_OVL_BASE(n) + \
96 DISPC_FIR_COEF_HV_OFFSET(n, i))
97#define DISPC_OVL_FIR_COEF_H2(n, i) (DISPC_OVL_BASE(n) + \
98 DISPC_FIR_COEF_H2_OFFSET(n, i))
99#define DISPC_OVL_FIR_COEF_HV2(n, i) (DISPC_OVL_BASE(n) + \
100 DISPC_FIR_COEF_HV2_OFFSET(n, i))
101#define DISPC_OVL_CONV_COEF(n, i) (DISPC_OVL_BASE(n) + \
102 DISPC_CONV_COEF_OFFSET(n, i))
103#define DISPC_OVL_FIR_COEF_V(n, i) (DISPC_OVL_BASE(n) + \
104 DISPC_FIR_COEF_V_OFFSET(n, i))
105#define DISPC_OVL_FIR_COEF_V2(n, i) (DISPC_OVL_BASE(n) + \
106 DISPC_FIR_COEF_V2_OFFSET(n, i))
107#define DISPC_OVL_PRELOAD(n) (DISPC_OVL_BASE(n) + \
108 DISPC_PRELOAD_OFFSET(n))
109#define DISPC_OVL_MFLAG_THRESHOLD(n) DISPC_MFLAG_THRESHOLD_OFFSET(n)
110
111/* DISPC up/downsampling FIR filter coefficient structure */
112struct dispc_coef {
113 s8 hc4_vc22;
114 s8 hc3_vc2;
115 u8 hc2_vc1;
116 s8 hc1_vc0;
117 s8 hc0_vc00;
118};
119
120const struct dispc_coef *dispc_ovl_get_scale_coef(int inc, int five_taps);
121
122/* DISPC manager/channel specific registers */
123static inline u16 DISPC_DEFAULT_COLOR(enum omap_channel channel)
124{
125 switch (channel) {
126 case OMAP_DSS_CHANNEL_LCD:
127 return 0x004C;
128 case OMAP_DSS_CHANNEL_DIGIT:
129 return 0x0050;
130 case OMAP_DSS_CHANNEL_LCD2:
131 return 0x03AC;
132 case OMAP_DSS_CHANNEL_LCD3:
133 return 0x0814;
134 default:
135 BUG();
136 return 0;
137 }
138}
139
140static inline u16 DISPC_TRANS_COLOR(enum omap_channel channel)
141{
142 switch (channel) {
143 case OMAP_DSS_CHANNEL_LCD:
144 return 0x0054;
145 case OMAP_DSS_CHANNEL_DIGIT:
146 return 0x0058;
147 case OMAP_DSS_CHANNEL_LCD2:
148 return 0x03B0;
149 case OMAP_DSS_CHANNEL_LCD3:
150 return 0x0818;
151 default:
152 BUG();
153 return 0;
154 }
155}
156
157static inline u16 DISPC_TIMING_H(enum omap_channel channel)
158{
159 switch (channel) {
160 case OMAP_DSS_CHANNEL_LCD:
161 return 0x0064;
162 case OMAP_DSS_CHANNEL_DIGIT:
163 BUG();
164 return 0;
165 case OMAP_DSS_CHANNEL_LCD2:
166 return 0x0400;
167 case OMAP_DSS_CHANNEL_LCD3:
168 return 0x0840;
169 default:
170 BUG();
171 return 0;
172 }
173}
174
175static inline u16 DISPC_TIMING_V(enum omap_channel channel)
176{
177 switch (channel) {
178 case OMAP_DSS_CHANNEL_LCD:
179 return 0x0068;
180 case OMAP_DSS_CHANNEL_DIGIT:
181 BUG();
182 return 0;
183 case OMAP_DSS_CHANNEL_LCD2:
184 return 0x0404;
185 case OMAP_DSS_CHANNEL_LCD3:
186 return 0x0844;
187 default:
188 BUG();
189 return 0;
190 }
191}
192
193static inline u16 DISPC_POL_FREQ(enum omap_channel channel)
194{
195 switch (channel) {
196 case OMAP_DSS_CHANNEL_LCD:
197 return 0x006C;
198 case OMAP_DSS_CHANNEL_DIGIT:
199 BUG();
200 return 0;
201 case OMAP_DSS_CHANNEL_LCD2:
202 return 0x0408;
203 case OMAP_DSS_CHANNEL_LCD3:
204 return 0x083C;
205 default:
206 BUG();
207 return 0;
208 }
209}
210
211static inline u16 DISPC_DIVISORo(enum omap_channel channel)
212{
213 switch (channel) {
214 case OMAP_DSS_CHANNEL_LCD:
215 return 0x0070;
216 case OMAP_DSS_CHANNEL_DIGIT:
217 BUG();
218 return 0;
219 case OMAP_DSS_CHANNEL_LCD2:
220 return 0x040C;
221 case OMAP_DSS_CHANNEL_LCD3:
222 return 0x0838;
223 default:
224 BUG();
225 return 0;
226 }
227}
228
229/* Named as DISPC_SIZE_LCD, DISPC_SIZE_DIGIT and DISPC_SIZE_LCD2 in TRM */
230static inline u16 DISPC_SIZE_MGR(enum omap_channel channel)
231{
232 switch (channel) {
233 case OMAP_DSS_CHANNEL_LCD:
234 return 0x007C;
235 case OMAP_DSS_CHANNEL_DIGIT:
236 return 0x0078;
237 case OMAP_DSS_CHANNEL_LCD2:
238 return 0x03CC;
239 case OMAP_DSS_CHANNEL_LCD3:
240 return 0x0834;
241 default:
242 BUG();
243 return 0;
244 }
245}
246
247static inline u16 DISPC_DATA_CYCLE1(enum omap_channel channel)
248{
249 switch (channel) {
250 case OMAP_DSS_CHANNEL_LCD:
251 return 0x01D4;
252 case OMAP_DSS_CHANNEL_DIGIT:
253 BUG();
254 return 0;
255 case OMAP_DSS_CHANNEL_LCD2:
256 return 0x03C0;
257 case OMAP_DSS_CHANNEL_LCD3:
258 return 0x0828;
259 default:
260 BUG();
261 return 0;
262 }
263}
264
265static inline u16 DISPC_DATA_CYCLE2(enum omap_channel channel)
266{
267 switch (channel) {
268 case OMAP_DSS_CHANNEL_LCD:
269 return 0x01D8;
270 case OMAP_DSS_CHANNEL_DIGIT:
271 BUG();
272 return 0;
273 case OMAP_DSS_CHANNEL_LCD2:
274 return 0x03C4;
275 case OMAP_DSS_CHANNEL_LCD3:
276 return 0x082C;
277 default:
278 BUG();
279 return 0;
280 }
281}
282
283static inline u16 DISPC_DATA_CYCLE3(enum omap_channel channel)
284{
285 switch (channel) {
286 case OMAP_DSS_CHANNEL_LCD:
287 return 0x01DC;
288 case OMAP_DSS_CHANNEL_DIGIT:
289 BUG();
290 return 0;
291 case OMAP_DSS_CHANNEL_LCD2:
292 return 0x03C8;
293 case OMAP_DSS_CHANNEL_LCD3:
294 return 0x0830;
295 default:
296 BUG();
297 return 0;
298 }
299}
300
301static inline u16 DISPC_CPR_COEF_R(enum omap_channel channel)
302{
303 switch (channel) {
304 case OMAP_DSS_CHANNEL_LCD:
305 return 0x0220;
306 case OMAP_DSS_CHANNEL_DIGIT:
307 BUG();
308 return 0;
309 case OMAP_DSS_CHANNEL_LCD2:
310 return 0x03BC;
311 case OMAP_DSS_CHANNEL_LCD3:
312 return 0x0824;
313 default:
314 BUG();
315 return 0;
316 }
317}
318
319static inline u16 DISPC_CPR_COEF_G(enum omap_channel channel)
320{
321 switch (channel) {
322 case OMAP_DSS_CHANNEL_LCD:
323 return 0x0224;
324 case OMAP_DSS_CHANNEL_DIGIT:
325 BUG();
326 return 0;
327 case OMAP_DSS_CHANNEL_LCD2:
328 return 0x03B8;
329 case OMAP_DSS_CHANNEL_LCD3:
330 return 0x0820;
331 default:
332 BUG();
333 return 0;
334 }
335}
336
337static inline u16 DISPC_CPR_COEF_B(enum omap_channel channel)
338{
339 switch (channel) {
340 case OMAP_DSS_CHANNEL_LCD:
341 return 0x0228;
342 case OMAP_DSS_CHANNEL_DIGIT:
343 BUG();
344 return 0;
345 case OMAP_DSS_CHANNEL_LCD2:
346 return 0x03B4;
347 case OMAP_DSS_CHANNEL_LCD3:
348 return 0x081C;
349 default:
350 BUG();
351 return 0;
352 }
353}
354
355/* DISPC overlay register base addresses */
356static inline u16 DISPC_OVL_BASE(enum omap_plane plane)
357{
358 switch (plane) {
359 case OMAP_DSS_GFX:
360 return 0x0080;
361 case OMAP_DSS_VIDEO1:
362 return 0x00BC;
363 case OMAP_DSS_VIDEO2:
364 return 0x014C;
365 case OMAP_DSS_VIDEO3:
366 return 0x0300;
367 case OMAP_DSS_WB:
368 return 0x0500;
369 default:
370 BUG();
371 return 0;
372 }
373}
374
375/* DISPC overlay register offsets */
376static inline u16 DISPC_BA0_OFFSET(enum omap_plane plane)
377{
378 switch (plane) {
379 case OMAP_DSS_GFX:
380 case OMAP_DSS_VIDEO1:
381 case OMAP_DSS_VIDEO2:
382 return 0x0000;
383 case OMAP_DSS_VIDEO3:
384 case OMAP_DSS_WB:
385 return 0x0008;
386 default:
387 BUG();
388 return 0;
389 }
390}
391
392static inline u16 DISPC_BA1_OFFSET(enum omap_plane plane)
393{
394 switch (plane) {
395 case OMAP_DSS_GFX:
396 case OMAP_DSS_VIDEO1:
397 case OMAP_DSS_VIDEO2:
398 return 0x0004;
399 case OMAP_DSS_VIDEO3:
400 case OMAP_DSS_WB:
401 return 0x000C;
402 default:
403 BUG();
404 return 0;
405 }
406}
407
408static inline u16 DISPC_BA0_UV_OFFSET(enum omap_plane plane)
409{
410 switch (plane) {
411 case OMAP_DSS_GFX:
412 BUG();
413 return 0;
414 case OMAP_DSS_VIDEO1:
415 return 0x0544;
416 case OMAP_DSS_VIDEO2:
417 return 0x04BC;
418 case OMAP_DSS_VIDEO3:
419 return 0x0310;
420 case OMAP_DSS_WB:
421 return 0x0118;
422 default:
423 BUG();
424 return 0;
425 }
426}
427
428static inline u16 DISPC_BA1_UV_OFFSET(enum omap_plane plane)
429{
430 switch (plane) {
431 case OMAP_DSS_GFX:
432 BUG();
433 return 0;
434 case OMAP_DSS_VIDEO1:
435 return 0x0548;
436 case OMAP_DSS_VIDEO2:
437 return 0x04C0;
438 case OMAP_DSS_VIDEO3:
439 return 0x0314;
440 case OMAP_DSS_WB:
441 return 0x011C;
442 default:
443 BUG();
444 return 0;
445 }
446}
447
448static inline u16 DISPC_POS_OFFSET(enum omap_plane plane)
449{
450 switch (plane) {
451 case OMAP_DSS_GFX:
452 case OMAP_DSS_VIDEO1:
453 case OMAP_DSS_VIDEO2:
454 return 0x0008;
455 case OMAP_DSS_VIDEO3:
456 return 0x009C;
457 default:
458 BUG();
459 return 0;
460 }
461}
462
463static inline u16 DISPC_SIZE_OFFSET(enum omap_plane plane)
464{
465 switch (plane) {
466 case OMAP_DSS_GFX:
467 case OMAP_DSS_VIDEO1:
468 case OMAP_DSS_VIDEO2:
469 return 0x000C;
470 case OMAP_DSS_VIDEO3:
471 case OMAP_DSS_WB:
472 return 0x00A8;
473 default:
474 BUG();
475 return 0;
476 }
477}
478
479static inline u16 DISPC_ATTR_OFFSET(enum omap_plane plane)
480{
481 switch (plane) {
482 case OMAP_DSS_GFX:
483 return 0x0020;
484 case OMAP_DSS_VIDEO1:
485 case OMAP_DSS_VIDEO2:
486 return 0x0010;
487 case OMAP_DSS_VIDEO3:
488 case OMAP_DSS_WB:
489 return 0x0070;
490 default:
491 BUG();
492 return 0;
493 }
494}
495
496static inline u16 DISPC_ATTR2_OFFSET(enum omap_plane plane)
497{
498 switch (plane) {
499 case OMAP_DSS_GFX:
500 BUG();
501 return 0;
502 case OMAP_DSS_VIDEO1:
503 return 0x0568;
504 case OMAP_DSS_VIDEO2:
505 return 0x04DC;
506 case OMAP_DSS_VIDEO3:
507 return 0x032C;
508 case OMAP_DSS_WB:
509 return 0x0310;
510 default:
511 BUG();
512 return 0;
513 }
514}
515
516static inline u16 DISPC_FIFO_THRESH_OFFSET(enum omap_plane plane)
517{
518 switch (plane) {
519 case OMAP_DSS_GFX:
520 return 0x0024;
521 case OMAP_DSS_VIDEO1:
522 case OMAP_DSS_VIDEO2:
523 return 0x0014;
524 case OMAP_DSS_VIDEO3:
525 case OMAP_DSS_WB:
526 return 0x008C;
527 default:
528 BUG();
529 return 0;
530 }
531}
532
533static inline u16 DISPC_FIFO_SIZE_STATUS_OFFSET(enum omap_plane plane)
534{
535 switch (plane) {
536 case OMAP_DSS_GFX:
537 return 0x0028;
538 case OMAP_DSS_VIDEO1:
539 case OMAP_DSS_VIDEO2:
540 return 0x0018;
541 case OMAP_DSS_VIDEO3:
542 case OMAP_DSS_WB:
543 return 0x0088;
544 default:
545 BUG();
546 return 0;
547 }
548}
549
550static inline u16 DISPC_ROW_INC_OFFSET(enum omap_plane plane)
551{
552 switch (plane) {
553 case OMAP_DSS_GFX:
554 return 0x002C;
555 case OMAP_DSS_VIDEO1:
556 case OMAP_DSS_VIDEO2:
557 return 0x001C;
558 case OMAP_DSS_VIDEO3:
559 case OMAP_DSS_WB:
560 return 0x00A4;
561 default:
562 BUG();
563 return 0;
564 }
565}
566
567static inline u16 DISPC_PIX_INC_OFFSET(enum omap_plane plane)
568{
569 switch (plane) {
570 case OMAP_DSS_GFX:
571 return 0x0030;
572 case OMAP_DSS_VIDEO1:
573 case OMAP_DSS_VIDEO2:
574 return 0x0020;
575 case OMAP_DSS_VIDEO3:
576 case OMAP_DSS_WB:
577 return 0x0098;
578 default:
579 BUG();
580 return 0;
581 }
582}
583
584static inline u16 DISPC_WINDOW_SKIP_OFFSET(enum omap_plane plane)
585{
586 switch (plane) {
587 case OMAP_DSS_GFX:
588 return 0x0034;
589 case OMAP_DSS_VIDEO1:
590 case OMAP_DSS_VIDEO2:
591 case OMAP_DSS_VIDEO3:
592 BUG();
593 return 0;
594 default:
595 BUG();
596 return 0;
597 }
598}
599
600static inline u16 DISPC_TABLE_BA_OFFSET(enum omap_plane plane)
601{
602 switch (plane) {
603 case OMAP_DSS_GFX:
604 return 0x0038;
605 case OMAP_DSS_VIDEO1:
606 case OMAP_DSS_VIDEO2:
607 case OMAP_DSS_VIDEO3:
608 BUG();
609 return 0;
610 default:
611 BUG();
612 return 0;
613 }
614}
615
616static inline u16 DISPC_FIR_OFFSET(enum omap_plane plane)
617{
618 switch (plane) {
619 case OMAP_DSS_GFX:
620 BUG();
621 return 0;
622 case OMAP_DSS_VIDEO1:
623 case OMAP_DSS_VIDEO2:
624 return 0x0024;
625 case OMAP_DSS_VIDEO3:
626 case OMAP_DSS_WB:
627 return 0x0090;
628 default:
629 BUG();
630 return 0;
631 }
632}
633
634static inline u16 DISPC_FIR2_OFFSET(enum omap_plane plane)
635{
636 switch (plane) {
637 case OMAP_DSS_GFX:
638 BUG();
639 return 0;
640 case OMAP_DSS_VIDEO1:
641 return 0x0580;
642 case OMAP_DSS_VIDEO2:
643 return 0x055C;
644 case OMAP_DSS_VIDEO3:
645 return 0x0424;
646 case OMAP_DSS_WB:
647 return 0x290;
648 default:
649 BUG();
650 return 0;
651 }
652}
653
654static inline u16 DISPC_PIC_SIZE_OFFSET(enum omap_plane plane)
655{
656 switch (plane) {
657 case OMAP_DSS_GFX:
658 BUG();
659 return 0;
660 case OMAP_DSS_VIDEO1:
661 case OMAP_DSS_VIDEO2:
662 return 0x0028;
663 case OMAP_DSS_VIDEO3:
664 case OMAP_DSS_WB:
665 return 0x0094;
666 default:
667 BUG();
668 return 0;
669 }
670}
671
672
673static inline u16 DISPC_ACCU0_OFFSET(enum omap_plane plane)
674{
675 switch (plane) {
676 case OMAP_DSS_GFX:
677 BUG();
678 return 0;
679 case OMAP_DSS_VIDEO1:
680 case OMAP_DSS_VIDEO2:
681 return 0x002C;
682 case OMAP_DSS_VIDEO3:
683 case OMAP_DSS_WB:
684 return 0x0000;
685 default:
686 BUG();
687 return 0;
688 }
689}
690
691static inline u16 DISPC_ACCU2_0_OFFSET(enum omap_plane plane)
692{
693 switch (plane) {
694 case OMAP_DSS_GFX:
695 BUG();
696 return 0;
697 case OMAP_DSS_VIDEO1:
698 return 0x0584;
699 case OMAP_DSS_VIDEO2:
700 return 0x0560;
701 case OMAP_DSS_VIDEO3:
702 return 0x0428;
703 case OMAP_DSS_WB:
704 return 0x0294;
705 default:
706 BUG();
707 return 0;
708 }
709}
710
711static inline u16 DISPC_ACCU1_OFFSET(enum omap_plane plane)
712{
713 switch (plane) {
714 case OMAP_DSS_GFX:
715 BUG();
716 return 0;
717 case OMAP_DSS_VIDEO1:
718 case OMAP_DSS_VIDEO2:
719 return 0x0030;
720 case OMAP_DSS_VIDEO3:
721 case OMAP_DSS_WB:
722 return 0x0004;
723 default:
724 BUG();
725 return 0;
726 }
727}
728
729static inline u16 DISPC_ACCU2_1_OFFSET(enum omap_plane plane)
730{
731 switch (plane) {
732 case OMAP_DSS_GFX:
733 BUG();
734 return 0;
735 case OMAP_DSS_VIDEO1:
736 return 0x0588;
737 case OMAP_DSS_VIDEO2:
738 return 0x0564;
739 case OMAP_DSS_VIDEO3:
740 return 0x042C;
741 case OMAP_DSS_WB:
742 return 0x0298;
743 default:
744 BUG();
745 return 0;
746 }
747}
748
749/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
750static inline u16 DISPC_FIR_COEF_H_OFFSET(enum omap_plane plane, u16 i)
751{
752 switch (plane) {
753 case OMAP_DSS_GFX:
754 BUG();
755 return 0;
756 case OMAP_DSS_VIDEO1:
757 case OMAP_DSS_VIDEO2:
758 return 0x0034 + i * 0x8;
759 case OMAP_DSS_VIDEO3:
760 case OMAP_DSS_WB:
761 return 0x0010 + i * 0x8;
762 default:
763 BUG();
764 return 0;
765 }
766}
767
768/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
769static inline u16 DISPC_FIR_COEF_H2_OFFSET(enum omap_plane plane, u16 i)
770{
771 switch (plane) {
772 case OMAP_DSS_GFX:
773 BUG();
774 return 0;
775 case OMAP_DSS_VIDEO1:
776 return 0x058C + i * 0x8;
777 case OMAP_DSS_VIDEO2:
778 return 0x0568 + i * 0x8;
779 case OMAP_DSS_VIDEO3:
780 return 0x0430 + i * 0x8;
781 case OMAP_DSS_WB:
782 return 0x02A0 + i * 0x8;
783 default:
784 BUG();
785 return 0;
786 }
787}
788
789/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
790static inline u16 DISPC_FIR_COEF_HV_OFFSET(enum omap_plane plane, u16 i)
791{
792 switch (plane) {
793 case OMAP_DSS_GFX:
794 BUG();
795 return 0;
796 case OMAP_DSS_VIDEO1:
797 case OMAP_DSS_VIDEO2:
798 return 0x0038 + i * 0x8;
799 case OMAP_DSS_VIDEO3:
800 case OMAP_DSS_WB:
801 return 0x0014 + i * 0x8;
802 default:
803 BUG();
804 return 0;
805 }
806}
807
808/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
809static inline u16 DISPC_FIR_COEF_HV2_OFFSET(enum omap_plane plane, u16 i)
810{
811 switch (plane) {
812 case OMAP_DSS_GFX:
813 BUG();
814 return 0;
815 case OMAP_DSS_VIDEO1:
816 return 0x0590 + i * 8;
817 case OMAP_DSS_VIDEO2:
818 return 0x056C + i * 0x8;
819 case OMAP_DSS_VIDEO3:
820 return 0x0434 + i * 0x8;
821 case OMAP_DSS_WB:
822 return 0x02A4 + i * 0x8;
823 default:
824 BUG();
825 return 0;
826 }
827}
828
829/* coef index i = {0, 1, 2, 3, 4,} */
830static inline u16 DISPC_CONV_COEF_OFFSET(enum omap_plane plane, u16 i)
831{
832 switch (plane) {
833 case OMAP_DSS_GFX:
834 BUG();
835 return 0;
836 case OMAP_DSS_VIDEO1:
837 case OMAP_DSS_VIDEO2:
838 case OMAP_DSS_VIDEO3:
839 case OMAP_DSS_WB:
840 return 0x0074 + i * 0x4;
841 default:
842 BUG();
843 return 0;
844 }
845}
846
847/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
848static inline u16 DISPC_FIR_COEF_V_OFFSET(enum omap_plane plane, u16 i)
849{
850 switch (plane) {
851 case OMAP_DSS_GFX:
852 BUG();
853 return 0;
854 case OMAP_DSS_VIDEO1:
855 return 0x0124 + i * 0x4;
856 case OMAP_DSS_VIDEO2:
857 return 0x00B4 + i * 0x4;
858 case OMAP_DSS_VIDEO3:
859 case OMAP_DSS_WB:
860 return 0x0050 + i * 0x4;
861 default:
862 BUG();
863 return 0;
864 }
865}
866
867/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
868static inline u16 DISPC_FIR_COEF_V2_OFFSET(enum omap_plane plane, u16 i)
869{
870 switch (plane) {
871 case OMAP_DSS_GFX:
872 BUG();
873 return 0;
874 case OMAP_DSS_VIDEO1:
875 return 0x05CC + i * 0x4;
876 case OMAP_DSS_VIDEO2:
877 return 0x05A8 + i * 0x4;
878 case OMAP_DSS_VIDEO3:
879 return 0x0470 + i * 0x4;
880 case OMAP_DSS_WB:
881 return 0x02E0 + i * 0x4;
882 default:
883 BUG();
884 return 0;
885 }
886}
887
888static inline u16 DISPC_PRELOAD_OFFSET(enum omap_plane plane)
889{
890 switch (plane) {
891 case OMAP_DSS_GFX:
892 return 0x01AC;
893 case OMAP_DSS_VIDEO1:
894 return 0x0174;
895 case OMAP_DSS_VIDEO2:
896 return 0x00E8;
897 case OMAP_DSS_VIDEO3:
898 return 0x00A0;
899 default:
900 BUG();
901 return 0;
902 }
903}
904
905static inline u16 DISPC_MFLAG_THRESHOLD_OFFSET(enum omap_plane plane)
906{
907 switch (plane) {
908 case OMAP_DSS_GFX:
909 return 0x0860;
910 case OMAP_DSS_VIDEO1:
911 return 0x0864;
912 case OMAP_DSS_VIDEO2:
913 return 0x0868;
914 case OMAP_DSS_VIDEO3:
915 return 0x086c;
916 case OMAP_DSS_WB:
917 return 0x0870;
918 default:
919 BUG();
920 return 0;
921 }
922}
923#endif