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1/*
2 * Copyright (C) 2013-2014 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include "adreno_gpu.h"
21
22#define ANY_ID 0xff
23
24bool hang_debug = false;
25MODULE_PARM_DESC(hang_debug, "Dump registers when hang is detected (can be slow!)");
26module_param_named(hang_debug, hang_debug, bool, 0600);
27
28struct msm_gpu *a3xx_gpu_init(struct drm_device *dev);
29struct msm_gpu *a4xx_gpu_init(struct drm_device *dev);
30
31static const struct adreno_info gpulist[] = {
32 {
33 .rev = ADRENO_REV(3, 0, 5, ANY_ID),
34 .revn = 305,
35 .name = "A305",
36 .pm4fw = "a300_pm4.fw",
37 .pfpfw = "a300_pfp.fw",
38 .gmem = SZ_256K,
39 .init = a3xx_gpu_init,
40 }, {
41 .rev = ADRENO_REV(3, 0, 6, 0),
42 .revn = 307, /* because a305c is revn==306 */
43 .name = "A306",
44 .pm4fw = "a300_pm4.fw",
45 .pfpfw = "a300_pfp.fw",
46 .gmem = SZ_128K,
47 .init = a3xx_gpu_init,
48 }, {
49 .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID),
50 .revn = 320,
51 .name = "A320",
52 .pm4fw = "a300_pm4.fw",
53 .pfpfw = "a300_pfp.fw",
54 .gmem = SZ_512K,
55 .init = a3xx_gpu_init,
56 }, {
57 .rev = ADRENO_REV(3, 3, 0, ANY_ID),
58 .revn = 330,
59 .name = "A330",
60 .pm4fw = "a330_pm4.fw",
61 .pfpfw = "a330_pfp.fw",
62 .gmem = SZ_1M,
63 .init = a3xx_gpu_init,
64 }, {
65 .rev = ADRENO_REV(4, 2, 0, ANY_ID),
66 .revn = 420,
67 .name = "A420",
68 .pm4fw = "a420_pm4.fw",
69 .pfpfw = "a420_pfp.fw",
70 .gmem = (SZ_1M + SZ_512K),
71 .init = a4xx_gpu_init,
72 }, {
73 .rev = ADRENO_REV(4, 3, 0, ANY_ID),
74 .revn = 430,
75 .name = "A430",
76 .pm4fw = "a420_pm4.fw",
77 .pfpfw = "a420_pfp.fw",
78 .gmem = (SZ_1M + SZ_512K),
79 .init = a4xx_gpu_init,
80 },
81};
82
83MODULE_FIRMWARE("a300_pm4.fw");
84MODULE_FIRMWARE("a300_pfp.fw");
85MODULE_FIRMWARE("a330_pm4.fw");
86MODULE_FIRMWARE("a330_pfp.fw");
87MODULE_FIRMWARE("a420_pm4.fw");
88MODULE_FIRMWARE("a420_pfp.fw");
89
90static inline bool _rev_match(uint8_t entry, uint8_t id)
91{
92 return (entry == ANY_ID) || (entry == id);
93}
94
95const struct adreno_info *adreno_info(struct adreno_rev rev)
96{
97 int i;
98
99 /* identify gpu: */
100 for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
101 const struct adreno_info *info = &gpulist[i];
102 if (_rev_match(info->rev.core, rev.core) &&
103 _rev_match(info->rev.major, rev.major) &&
104 _rev_match(info->rev.minor, rev.minor) &&
105 _rev_match(info->rev.patchid, rev.patchid))
106 return info;
107 }
108
109 return NULL;
110}
111
112struct msm_gpu *adreno_load_gpu(struct drm_device *dev)
113{
114 struct msm_drm_private *priv = dev->dev_private;
115 struct platform_device *pdev = priv->gpu_pdev;
116 struct adreno_platform_config *config;
117 struct adreno_rev rev;
118 const struct adreno_info *info;
119 struct msm_gpu *gpu = NULL;
120
121 if (!pdev) {
122 dev_err(dev->dev, "no adreno device\n");
123 return NULL;
124 }
125
126 config = pdev->dev.platform_data;
127 rev = config->rev;
128 info = adreno_info(config->rev);
129
130 if (!info) {
131 dev_warn(dev->dev, "Unknown GPU revision: %u.%u.%u.%u\n",
132 rev.core, rev.major, rev.minor, rev.patchid);
133 return NULL;
134 }
135
136 DBG("Found GPU: %u.%u.%u.%u", rev.core, rev.major,
137 rev.minor, rev.patchid);
138
139 gpu = info->init(dev);
140 if (IS_ERR(gpu)) {
141 dev_warn(dev->dev, "failed to load adreno gpu\n");
142 gpu = NULL;
143 /* not fatal */
144 }
145
146 if (gpu) {
147 int ret;
148 mutex_lock(&dev->struct_mutex);
149 gpu->funcs->pm_resume(gpu);
150 mutex_unlock(&dev->struct_mutex);
151 ret = gpu->funcs->hw_init(gpu);
152 if (ret) {
153 dev_err(dev->dev, "gpu hw init failed: %d\n", ret);
154 gpu->funcs->destroy(gpu);
155 gpu = NULL;
156 } else {
157 /* give inactive pm a chance to kick in: */
158 msm_gpu_retire(gpu);
159 }
160 }
161
162 return gpu;
163}
164
165static void set_gpu_pdev(struct drm_device *dev,
166 struct platform_device *pdev)
167{
168 struct msm_drm_private *priv = dev->dev_private;
169 priv->gpu_pdev = pdev;
170}
171
172static int adreno_bind(struct device *dev, struct device *master, void *data)
173{
174 static struct adreno_platform_config config = {};
175 struct device_node *child, *node = dev->of_node;
176 u32 val;
177 int ret;
178
179 ret = of_property_read_u32(node, "qcom,chipid", &val);
180 if (ret) {
181 dev_err(dev, "could not find chipid: %d\n", ret);
182 return ret;
183 }
184
185 config.rev = ADRENO_REV((val >> 24) & 0xff,
186 (val >> 16) & 0xff, (val >> 8) & 0xff, val & 0xff);
187
188 /* find clock rates: */
189 config.fast_rate = 0;
190 config.slow_rate = ~0;
191 for_each_child_of_node(node, child) {
192 if (of_device_is_compatible(child, "qcom,gpu-pwrlevels")) {
193 struct device_node *pwrlvl;
194 for_each_child_of_node(child, pwrlvl) {
195 ret = of_property_read_u32(pwrlvl, "qcom,gpu-freq", &val);
196 if (ret) {
197 dev_err(dev, "could not find gpu-freq: %d\n", ret);
198 return ret;
199 }
200 config.fast_rate = max(config.fast_rate, val);
201 config.slow_rate = min(config.slow_rate, val);
202 }
203 }
204 }
205
206 if (!config.fast_rate) {
207 dev_err(dev, "could not find clk rates\n");
208 return -ENXIO;
209 }
210
211 dev->platform_data = &config;
212 set_gpu_pdev(dev_get_drvdata(master), to_platform_device(dev));
213 return 0;
214}
215
216static void adreno_unbind(struct device *dev, struct device *master,
217 void *data)
218{
219 set_gpu_pdev(dev_get_drvdata(master), NULL);
220}
221
222static const struct component_ops a3xx_ops = {
223 .bind = adreno_bind,
224 .unbind = adreno_unbind,
225};
226
227static int adreno_probe(struct platform_device *pdev)
228{
229 return component_add(&pdev->dev, &a3xx_ops);
230}
231
232static int adreno_remove(struct platform_device *pdev)
233{
234 component_del(&pdev->dev, &a3xx_ops);
235 return 0;
236}
237
238static const struct of_device_id dt_match[] = {
239 { .compatible = "qcom,adreno-3xx" },
240 /* for backwards compat w/ downstream kgsl DT files: */
241 { .compatible = "qcom,kgsl-3d0" },
242 {}
243};
244
245static struct platform_driver adreno_driver = {
246 .probe = adreno_probe,
247 .remove = adreno_remove,
248 .driver = {
249 .name = "adreno",
250 .of_match_table = dt_match,
251 },
252};
253
254void __init adreno_register(void)
255{
256 platform_driver_register(&adreno_driver);
257}
258
259void __exit adreno_unregister(void)
260{
261 platform_driver_unregister(&adreno_driver);
262}
1/*
2 * Copyright (C) 2013-2014 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include "adreno_gpu.h"
21
22#define ANY_ID 0xff
23
24bool hang_debug = false;
25MODULE_PARM_DESC(hang_debug, "Dump registers when hang is detected (can be slow!)");
26module_param_named(hang_debug, hang_debug, bool, 0600);
27
28static const struct adreno_info gpulist[] = {
29 {
30 .rev = ADRENO_REV(3, 0, 5, ANY_ID),
31 .revn = 305,
32 .name = "A305",
33 .fw = {
34 [ADRENO_FW_PM4] = "a300_pm4.fw",
35 [ADRENO_FW_PFP] = "a300_pfp.fw",
36 },
37 .gmem = SZ_256K,
38 .init = a3xx_gpu_init,
39 }, {
40 .rev = ADRENO_REV(3, 0, 6, 0),
41 .revn = 307, /* because a305c is revn==306 */
42 .name = "A306",
43 .fw = {
44 [ADRENO_FW_PM4] = "a300_pm4.fw",
45 [ADRENO_FW_PFP] = "a300_pfp.fw",
46 },
47 .gmem = SZ_128K,
48 .init = a3xx_gpu_init,
49 }, {
50 .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID),
51 .revn = 320,
52 .name = "A320",
53 .fw = {
54 [ADRENO_FW_PM4] = "a300_pm4.fw",
55 [ADRENO_FW_PFP] = "a300_pfp.fw",
56 },
57 .gmem = SZ_512K,
58 .init = a3xx_gpu_init,
59 }, {
60 .rev = ADRENO_REV(3, 3, 0, ANY_ID),
61 .revn = 330,
62 .name = "A330",
63 .fw = {
64 [ADRENO_FW_PM4] = "a330_pm4.fw",
65 [ADRENO_FW_PFP] = "a330_pfp.fw",
66 },
67 .gmem = SZ_1M,
68 .init = a3xx_gpu_init,
69 }, {
70 .rev = ADRENO_REV(4, 2, 0, ANY_ID),
71 .revn = 420,
72 .name = "A420",
73 .fw = {
74 [ADRENO_FW_PM4] = "a420_pm4.fw",
75 [ADRENO_FW_PFP] = "a420_pfp.fw",
76 },
77 .gmem = (SZ_1M + SZ_512K),
78 .init = a4xx_gpu_init,
79 }, {
80 .rev = ADRENO_REV(4, 3, 0, ANY_ID),
81 .revn = 430,
82 .name = "A430",
83 .fw = {
84 [ADRENO_FW_PM4] = "a420_pm4.fw",
85 [ADRENO_FW_PFP] = "a420_pfp.fw",
86 },
87 .gmem = (SZ_1M + SZ_512K),
88 .init = a4xx_gpu_init,
89 }, {
90 .rev = ADRENO_REV(5, 3, 0, 2),
91 .revn = 530,
92 .name = "A530",
93 .fw = {
94 [ADRENO_FW_PM4] = "a530_pm4.fw",
95 [ADRENO_FW_PFP] = "a530_pfp.fw",
96 [ADRENO_FW_GPMU] = "a530v3_gpmu.fw2",
97 },
98 .gmem = SZ_1M,
99 .quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI |
100 ADRENO_QUIRK_FAULT_DETECT_MASK,
101 .init = a5xx_gpu_init,
102 .zapfw = "a530_zap.mdt",
103 },
104};
105
106MODULE_FIRMWARE("qcom/a300_pm4.fw");
107MODULE_FIRMWARE("qcom/a300_pfp.fw");
108MODULE_FIRMWARE("qcom/a330_pm4.fw");
109MODULE_FIRMWARE("qcom/a330_pfp.fw");
110MODULE_FIRMWARE("qcom/a420_pm4.fw");
111MODULE_FIRMWARE("qcom/a420_pfp.fw");
112MODULE_FIRMWARE("qcom/a530_pm4.fw");
113MODULE_FIRMWARE("qcom/a530_pfp.fw");
114MODULE_FIRMWARE("qcom/a530v3_gpmu.fw2");
115MODULE_FIRMWARE("qcom/a530_zap.mdt");
116MODULE_FIRMWARE("qcom/a530_zap.b00");
117MODULE_FIRMWARE("qcom/a530_zap.b01");
118MODULE_FIRMWARE("qcom/a530_zap.b02");
119
120static inline bool _rev_match(uint8_t entry, uint8_t id)
121{
122 return (entry == ANY_ID) || (entry == id);
123}
124
125const struct adreno_info *adreno_info(struct adreno_rev rev)
126{
127 int i;
128
129 /* identify gpu: */
130 for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
131 const struct adreno_info *info = &gpulist[i];
132 if (_rev_match(info->rev.core, rev.core) &&
133 _rev_match(info->rev.major, rev.major) &&
134 _rev_match(info->rev.minor, rev.minor) &&
135 _rev_match(info->rev.patchid, rev.patchid))
136 return info;
137 }
138
139 return NULL;
140}
141
142struct msm_gpu *adreno_load_gpu(struct drm_device *dev)
143{
144 struct msm_drm_private *priv = dev->dev_private;
145 struct platform_device *pdev = priv->gpu_pdev;
146 struct msm_gpu *gpu = NULL;
147 int ret;
148
149 if (pdev)
150 gpu = platform_get_drvdata(pdev);
151
152 if (!gpu) {
153 dev_err_once(dev->dev, "no GPU device was found\n");
154 return NULL;
155 }
156
157 pm_runtime_get_sync(&pdev->dev);
158 mutex_lock(&dev->struct_mutex);
159 ret = msm_gpu_hw_init(gpu);
160 mutex_unlock(&dev->struct_mutex);
161 pm_runtime_put_sync(&pdev->dev);
162 if (ret) {
163 dev_err(dev->dev, "gpu hw init failed: %d\n", ret);
164 return NULL;
165 }
166
167#ifdef CONFIG_DEBUG_FS
168 if (gpu->funcs->debugfs_init) {
169 gpu->funcs->debugfs_init(gpu, dev->primary);
170 gpu->funcs->debugfs_init(gpu, dev->render);
171 gpu->funcs->debugfs_init(gpu, dev->control);
172 }
173#endif
174
175 return gpu;
176}
177
178static void set_gpu_pdev(struct drm_device *dev,
179 struct platform_device *pdev)
180{
181 struct msm_drm_private *priv = dev->dev_private;
182 priv->gpu_pdev = pdev;
183}
184
185static int find_chipid(struct device *dev, struct adreno_rev *rev)
186{
187 struct device_node *node = dev->of_node;
188 const char *compat;
189 int ret;
190 u32 chipid;
191
192 /* first search the compat strings for qcom,adreno-XYZ.W: */
193 ret = of_property_read_string_index(node, "compatible", 0, &compat);
194 if (ret == 0) {
195 unsigned int r, patch;
196
197 if (sscanf(compat, "qcom,adreno-%u.%u", &r, &patch) == 2) {
198 rev->core = r / 100;
199 r %= 100;
200 rev->major = r / 10;
201 r %= 10;
202 rev->minor = r;
203 rev->patchid = patch;
204
205 return 0;
206 }
207 }
208
209 /* and if that fails, fall back to legacy "qcom,chipid" property: */
210 ret = of_property_read_u32(node, "qcom,chipid", &chipid);
211 if (ret) {
212 dev_err(dev, "could not parse qcom,chipid: %d\n", ret);
213 return ret;
214 }
215
216 rev->core = (chipid >> 24) & 0xff;
217 rev->major = (chipid >> 16) & 0xff;
218 rev->minor = (chipid >> 8) & 0xff;
219 rev->patchid = (chipid & 0xff);
220
221 dev_warn(dev, "Using legacy qcom,chipid binding!\n");
222 dev_warn(dev, "Use compatible qcom,adreno-%u%u%u.%u instead.\n",
223 rev->core, rev->major, rev->minor, rev->patchid);
224
225 return 0;
226}
227
228static int adreno_bind(struct device *dev, struct device *master, void *data)
229{
230 static struct adreno_platform_config config = {};
231 const struct adreno_info *info;
232 struct drm_device *drm = dev_get_drvdata(master);
233 struct msm_gpu *gpu;
234 int ret;
235
236 ret = find_chipid(dev, &config.rev);
237 if (ret)
238 return ret;
239
240 dev->platform_data = &config;
241 set_gpu_pdev(drm, to_platform_device(dev));
242
243 info = adreno_info(config.rev);
244
245 if (!info) {
246 dev_warn(drm->dev, "Unknown GPU revision: %u.%u.%u.%u\n",
247 config.rev.core, config.rev.major,
248 config.rev.minor, config.rev.patchid);
249 return -ENXIO;
250 }
251
252 DBG("Found GPU: %u.%u.%u.%u", config.rev.core, config.rev.major,
253 config.rev.minor, config.rev.patchid);
254
255 gpu = info->init(drm);
256 if (IS_ERR(gpu)) {
257 dev_warn(drm->dev, "failed to load adreno gpu\n");
258 return PTR_ERR(gpu);
259 }
260
261 dev_set_drvdata(dev, gpu);
262
263 return 0;
264}
265
266static void adreno_unbind(struct device *dev, struct device *master,
267 void *data)
268{
269 struct msm_gpu *gpu = dev_get_drvdata(dev);
270
271 gpu->funcs->pm_suspend(gpu);
272 gpu->funcs->destroy(gpu);
273
274 set_gpu_pdev(dev_get_drvdata(master), NULL);
275}
276
277static const struct component_ops a3xx_ops = {
278 .bind = adreno_bind,
279 .unbind = adreno_unbind,
280};
281
282static int adreno_probe(struct platform_device *pdev)
283{
284 return component_add(&pdev->dev, &a3xx_ops);
285}
286
287static int adreno_remove(struct platform_device *pdev)
288{
289 component_del(&pdev->dev, &a3xx_ops);
290 return 0;
291}
292
293static const struct of_device_id dt_match[] = {
294 { .compatible = "qcom,adreno" },
295 { .compatible = "qcom,adreno-3xx" },
296 /* for backwards compat w/ downstream kgsl DT files: */
297 { .compatible = "qcom,kgsl-3d0" },
298 {}
299};
300
301#ifdef CONFIG_PM
302static int adreno_resume(struct device *dev)
303{
304 struct platform_device *pdev = to_platform_device(dev);
305 struct msm_gpu *gpu = platform_get_drvdata(pdev);
306
307 return gpu->funcs->pm_resume(gpu);
308}
309
310static int adreno_suspend(struct device *dev)
311{
312 struct platform_device *pdev = to_platform_device(dev);
313 struct msm_gpu *gpu = platform_get_drvdata(pdev);
314
315 return gpu->funcs->pm_suspend(gpu);
316}
317#endif
318
319static const struct dev_pm_ops adreno_pm_ops = {
320 SET_RUNTIME_PM_OPS(adreno_suspend, adreno_resume, NULL)
321};
322
323static struct platform_driver adreno_driver = {
324 .probe = adreno_probe,
325 .remove = adreno_remove,
326 .driver = {
327 .name = "adreno",
328 .of_match_table = dt_match,
329 .pm = &adreno_pm_ops,
330 },
331};
332
333void __init adreno_register(void)
334{
335 platform_driver_register(&adreno_driver);
336}
337
338void __exit adreno_unregister(void)
339{
340 platform_driver_unregister(&adreno_driver);
341}