1/*
  2 * Copyright (C) 2013-2014 Red Hat
  3 * Author: Rob Clark <robdclark@gmail.com>
  4 *
  5 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
  6 *
  7 * This program is free software; you can redistribute it and/or modify it
  8 * under the terms of the GNU General Public License version 2 as published by
  9 * the Free Software Foundation.
 10 *
 11 * This program is distributed in the hope that it will be useful, but WITHOUT
 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 13 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 14 * more details.
 15 *
 16 * You should have received a copy of the GNU General Public License along with
 17 * this program.  If not, see <http://www.gnu.org/licenses/>.
 18 */
 19
 20#include "adreno_gpu.h"
 21
 22#define ANY_ID 0xff
 23
 24bool hang_debug = false;
 25MODULE_PARM_DESC(hang_debug, "Dump registers when hang is detected (can be slow!)");
 26module_param_named(hang_debug, hang_debug, bool, 0600);
 27
 28struct msm_gpu *a3xx_gpu_init(struct drm_device *dev);
 29struct msm_gpu *a4xx_gpu_init(struct drm_device *dev);
 30
 31static const struct adreno_info gpulist[] = {
 32	{
 33		.rev   = ADRENO_REV(3, 0, 5, ANY_ID),
 34		.revn  = 305,
 35		.name  = "A305",
 36		.pm4fw = "a300_pm4.fw",
 37		.pfpfw = "a300_pfp.fw",
 38		.gmem  = SZ_256K,
 39		.init  = a3xx_gpu_init,
 40	}, {
 41		.rev   = ADRENO_REV(3, 0, 6, 0),
 42		.revn  = 307,        /* because a305c is revn==306 */
 43		.name  = "A306",
 44		.pm4fw = "a300_pm4.fw",
 45		.pfpfw = "a300_pfp.fw",
 46		.gmem  = SZ_128K,
 47		.init  = a3xx_gpu_init,
 48	}, {
 49		.rev   = ADRENO_REV(3, 2, ANY_ID, ANY_ID),
 50		.revn  = 320,
 51		.name  = "A320",
 52		.pm4fw = "a300_pm4.fw",
 53		.pfpfw = "a300_pfp.fw",
 54		.gmem  = SZ_512K,
 55		.init  = a3xx_gpu_init,
 56	}, {
 57		.rev   = ADRENO_REV(3, 3, 0, ANY_ID),
 58		.revn  = 330,
 59		.name  = "A330",
 60		.pm4fw = "a330_pm4.fw",
 61		.pfpfw = "a330_pfp.fw",
 62		.gmem  = SZ_1M,
 63		.init  = a3xx_gpu_init,
 64	}, {
 65		.rev   = ADRENO_REV(4, 2, 0, ANY_ID),
 66		.revn  = 420,
 67		.name  = "A420",
 68		.pm4fw = "a420_pm4.fw",
 69		.pfpfw = "a420_pfp.fw",
 70		.gmem  = (SZ_1M + SZ_512K),
 71		.init  = a4xx_gpu_init,
 72	}, {
 73		.rev   = ADRENO_REV(4, 3, 0, ANY_ID),
 74		.revn  = 430,
 75		.name  = "A430",
 76		.pm4fw = "a420_pm4.fw",
 77		.pfpfw = "a420_pfp.fw",
 78		.gmem  = (SZ_1M + SZ_512K),
 79		.init  = a4xx_gpu_init,
 80	},
 81};
 82
 83MODULE_FIRMWARE("a300_pm4.fw");
 84MODULE_FIRMWARE("a300_pfp.fw");
 85MODULE_FIRMWARE("a330_pm4.fw");
 86MODULE_FIRMWARE("a330_pfp.fw");
 87MODULE_FIRMWARE("a420_pm4.fw");
 88MODULE_FIRMWARE("a420_pfp.fw");
 89
 90static inline bool _rev_match(uint8_t entry, uint8_t id)
 91{
 92	return (entry == ANY_ID) || (entry == id);
 93}
 94
 95const struct adreno_info *adreno_info(struct adreno_rev rev)
 96{
 97	int i;
 98
 99	/* identify gpu: */
100	for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
101		const struct adreno_info *info = &gpulist[i];
102		if (_rev_match(info->rev.core, rev.core) &&
103				_rev_match(info->rev.major, rev.major) &&
104				_rev_match(info->rev.minor, rev.minor) &&
105				_rev_match(info->rev.patchid, rev.patchid))
106			return info;
107	}
108
109	return NULL;
110}
111
112struct msm_gpu *adreno_load_gpu(struct drm_device *dev)
113{
114	struct msm_drm_private *priv = dev->dev_private;
115	struct platform_device *pdev = priv->gpu_pdev;
116	struct adreno_platform_config *config;
117	struct adreno_rev rev;
118	const struct adreno_info *info;
119	struct msm_gpu *gpu = NULL;
120
121	if (!pdev) {
122		dev_err(dev->dev, "no adreno device\n");
123		return NULL;
124	}
125
126	config = pdev->dev.platform_data;
127	rev = config->rev;
128	info = adreno_info(config->rev);
129
130	if (!info) {
131		dev_warn(dev->dev, "Unknown GPU revision: %u.%u.%u.%u\n",
132				rev.core, rev.major, rev.minor, rev.patchid);
133		return NULL;
134	}
135
136	DBG("Found GPU: %u.%u.%u.%u",  rev.core, rev.major,
137			rev.minor, rev.patchid);
138
139	gpu = info->init(dev);
140	if (IS_ERR(gpu)) {
141		dev_warn(dev->dev, "failed to load adreno gpu\n");
142		gpu = NULL;
143		/* not fatal */
144	}
145
146	if (gpu) {
147		int ret;
148		mutex_lock(&dev->struct_mutex);
149		gpu->funcs->pm_resume(gpu);
150		mutex_unlock(&dev->struct_mutex);
151		ret = gpu->funcs->hw_init(gpu);
152		if (ret) {
153			dev_err(dev->dev, "gpu hw init failed: %d\n", ret);
154			gpu->funcs->destroy(gpu);
155			gpu = NULL;
156		} else {
157			/* give inactive pm a chance to kick in: */
158			msm_gpu_retire(gpu);
159		}
160	}
161
162	return gpu;
163}
164
165static void set_gpu_pdev(struct drm_device *dev,
166		struct platform_device *pdev)
167{
168	struct msm_drm_private *priv = dev->dev_private;
169	priv->gpu_pdev = pdev;
170}
171
172static int adreno_bind(struct device *dev, struct device *master, void *data)
173{
174	static struct adreno_platform_config config = {};
175	struct device_node *child, *node = dev->of_node;
176	u32 val;
177	int ret;
178
179	ret = of_property_read_u32(node, "qcom,chipid", &val);
180	if (ret) {
181		dev_err(dev, "could not find chipid: %d\n", ret);
182		return ret;
183	}
184
185	config.rev = ADRENO_REV((val >> 24) & 0xff,
186			(val >> 16) & 0xff, (val >> 8) & 0xff, val & 0xff);
187
188	/* find clock rates: */
189	config.fast_rate = 0;
190	config.slow_rate = ~0;
191	for_each_child_of_node(node, child) {
192		if (of_device_is_compatible(child, "qcom,gpu-pwrlevels")) {
193			struct device_node *pwrlvl;
194			for_each_child_of_node(child, pwrlvl) {
195				ret = of_property_read_u32(pwrlvl, "qcom,gpu-freq", &val);
196				if (ret) {
197					dev_err(dev, "could not find gpu-freq: %d\n", ret);
198					return ret;
199				}
200				config.fast_rate = max(config.fast_rate, val);
201				config.slow_rate = min(config.slow_rate, val);
202			}
203		}
204	}
205
206	if (!config.fast_rate) {
207		dev_err(dev, "could not find clk rates\n");
208		return -ENXIO;
209	}
210
211	dev->platform_data = &config;
212	set_gpu_pdev(dev_get_drvdata(master), to_platform_device(dev));
213	return 0;
214}
215
216static void adreno_unbind(struct device *dev, struct device *master,
217		void *data)
218{
219	set_gpu_pdev(dev_get_drvdata(master), NULL);
220}
221
222static const struct component_ops a3xx_ops = {
223		.bind   = adreno_bind,
224		.unbind = adreno_unbind,
225};
226
227static int adreno_probe(struct platform_device *pdev)
228{
229	return component_add(&pdev->dev, &a3xx_ops);
230}
231
232static int adreno_remove(struct platform_device *pdev)
233{
234	component_del(&pdev->dev, &a3xx_ops);
235	return 0;
236}
237
238static const struct of_device_id dt_match[] = {
239	{ .compatible = "qcom,adreno-3xx" },
240	/* for backwards compat w/ downstream kgsl DT files: */
241	{ .compatible = "qcom,kgsl-3d0" },
242	{}
243};
244
245static struct platform_driver adreno_driver = {
246	.probe = adreno_probe,
247	.remove = adreno_remove,
248	.driver = {
249		.name = "adreno",
250		.of_match_table = dt_match,
251	},
252};
253
254void __init adreno_register(void)
255{
256	platform_driver_register(&adreno_driver);
257}
258
259void __exit adreno_unregister(void)
260{
261	platform_driver_unregister(&adreno_driver);
262}