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1/*
2 * MUSB OTG driver core code
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35/*
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
37 *
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
42 *
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
47 *
48 *
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
53 *
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
56 *
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
61 *
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
66 * each direction.
67 *
68 * RESULT: one device may be perceived as blocking another one.
69 *
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
74 *
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
80 */
81
82/*
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific information
87 * (plus recentrly, SOC or family details)
88 *
89 * Most of the conditional compilation will (someday) vanish.
90 */
91
92#include <linux/module.h>
93#include <linux/kernel.h>
94#include <linux/sched.h>
95#include <linux/slab.h>
96#include <linux/list.h>
97#include <linux/kobject.h>
98#include <linux/prefetch.h>
99#include <linux/platform_device.h>
100#include <linux/io.h>
101#include <linux/dma-mapping.h>
102#include <linux/usb.h>
103
104#include "musb_core.h"
105
106#define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
107
108
109#define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
110#define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
111
112#define MUSB_VERSION "6.0"
113
114#define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
115
116#define MUSB_DRIVER_NAME "musb-hdrc"
117const char musb_driver_name[] = MUSB_DRIVER_NAME;
118
119MODULE_DESCRIPTION(DRIVER_INFO);
120MODULE_AUTHOR(DRIVER_AUTHOR);
121MODULE_LICENSE("GPL");
122MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
123
124
125/*-------------------------------------------------------------------------*/
126
127static inline struct musb *dev_to_musb(struct device *dev)
128{
129 return dev_get_drvdata(dev);
130}
131
132/*-------------------------------------------------------------------------*/
133
134#ifndef CONFIG_BLACKFIN
135static int musb_ulpi_read(struct usb_phy *phy, u32 reg)
136{
137 void __iomem *addr = phy->io_priv;
138 int i = 0;
139 u8 r;
140 u8 power;
141 int ret;
142
143 pm_runtime_get_sync(phy->io_dev);
144
145 /* Make sure the transceiver is not in low power mode */
146 power = musb_readb(addr, MUSB_POWER);
147 power &= ~MUSB_POWER_SUSPENDM;
148 musb_writeb(addr, MUSB_POWER, power);
149
150 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
151 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
152 */
153
154 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg);
155 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
156 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
157
158 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
159 & MUSB_ULPI_REG_CMPLT)) {
160 i++;
161 if (i == 10000) {
162 ret = -ETIMEDOUT;
163 goto out;
164 }
165
166 }
167 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
168 r &= ~MUSB_ULPI_REG_CMPLT;
169 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
170
171 ret = musb_readb(addr, MUSB_ULPI_REG_DATA);
172
173out:
174 pm_runtime_put(phy->io_dev);
175
176 return ret;
177}
178
179static int musb_ulpi_write(struct usb_phy *phy, u32 val, u32 reg)
180{
181 void __iomem *addr = phy->io_priv;
182 int i = 0;
183 u8 r = 0;
184 u8 power;
185 int ret = 0;
186
187 pm_runtime_get_sync(phy->io_dev);
188
189 /* Make sure the transceiver is not in low power mode */
190 power = musb_readb(addr, MUSB_POWER);
191 power &= ~MUSB_POWER_SUSPENDM;
192 musb_writeb(addr, MUSB_POWER, power);
193
194 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg);
195 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)val);
196 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
197
198 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
199 & MUSB_ULPI_REG_CMPLT)) {
200 i++;
201 if (i == 10000) {
202 ret = -ETIMEDOUT;
203 goto out;
204 }
205 }
206
207 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
208 r &= ~MUSB_ULPI_REG_CMPLT;
209 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
210
211out:
212 pm_runtime_put(phy->io_dev);
213
214 return ret;
215}
216#else
217#define musb_ulpi_read NULL
218#define musb_ulpi_write NULL
219#endif
220
221static struct usb_phy_io_ops musb_ulpi_access = {
222 .read = musb_ulpi_read,
223 .write = musb_ulpi_write,
224};
225
226/*-------------------------------------------------------------------------*/
227
228static u32 musb_default_fifo_offset(u8 epnum)
229{
230 return 0x20 + (epnum * 4);
231}
232
233/* "flat" mapping: each endpoint has its own i/o address */
234static void musb_flat_ep_select(void __iomem *mbase, u8 epnum)
235{
236}
237
238static u32 musb_flat_ep_offset(u8 epnum, u16 offset)
239{
240 return 0x100 + (0x10 * epnum) + offset;
241}
242
243/* "indexed" mapping: INDEX register controls register bank select */
244static void musb_indexed_ep_select(void __iomem *mbase, u8 epnum)
245{
246 musb_writeb(mbase, MUSB_INDEX, epnum);
247}
248
249static u32 musb_indexed_ep_offset(u8 epnum, u16 offset)
250{
251 return 0x10 + offset;
252}
253
254static u32 musb_default_busctl_offset(u8 epnum, u16 offset)
255{
256 return 0x80 + (0x08 * epnum) + offset;
257}
258
259static u8 musb_default_readb(const void __iomem *addr, unsigned offset)
260{
261 return __raw_readb(addr + offset);
262}
263
264static void musb_default_writeb(void __iomem *addr, unsigned offset, u8 data)
265{
266 __raw_writeb(data, addr + offset);
267}
268
269static u16 musb_default_readw(const void __iomem *addr, unsigned offset)
270{
271 return __raw_readw(addr + offset);
272}
273
274static void musb_default_writew(void __iomem *addr, unsigned offset, u16 data)
275{
276 __raw_writew(data, addr + offset);
277}
278
279static u32 musb_default_readl(const void __iomem *addr, unsigned offset)
280{
281 return __raw_readl(addr + offset);
282}
283
284static void musb_default_writel(void __iomem *addr, unsigned offset, u32 data)
285{
286 __raw_writel(data, addr + offset);
287}
288
289/*
290 * Load an endpoint's FIFO
291 */
292static void musb_default_write_fifo(struct musb_hw_ep *hw_ep, u16 len,
293 const u8 *src)
294{
295 struct musb *musb = hw_ep->musb;
296 void __iomem *fifo = hw_ep->fifo;
297
298 if (unlikely(len == 0))
299 return;
300
301 prefetch((u8 *)src);
302
303 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
304 'T', hw_ep->epnum, fifo, len, src);
305
306 /* we can't assume unaligned reads work */
307 if (likely((0x01 & (unsigned long) src) == 0)) {
308 u16 index = 0;
309
310 /* best case is 32bit-aligned source address */
311 if ((0x02 & (unsigned long) src) == 0) {
312 if (len >= 4) {
313 iowrite32_rep(fifo, src + index, len >> 2);
314 index += len & ~0x03;
315 }
316 if (len & 0x02) {
317 __raw_writew(*(u16 *)&src[index], fifo);
318 index += 2;
319 }
320 } else {
321 if (len >= 2) {
322 iowrite16_rep(fifo, src + index, len >> 1);
323 index += len & ~0x01;
324 }
325 }
326 if (len & 0x01)
327 __raw_writeb(src[index], fifo);
328 } else {
329 /* byte aligned */
330 iowrite8_rep(fifo, src, len);
331 }
332}
333
334/*
335 * Unload an endpoint's FIFO
336 */
337static void musb_default_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
338{
339 struct musb *musb = hw_ep->musb;
340 void __iomem *fifo = hw_ep->fifo;
341
342 if (unlikely(len == 0))
343 return;
344
345 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
346 'R', hw_ep->epnum, fifo, len, dst);
347
348 /* we can't assume unaligned writes work */
349 if (likely((0x01 & (unsigned long) dst) == 0)) {
350 u16 index = 0;
351
352 /* best case is 32bit-aligned destination address */
353 if ((0x02 & (unsigned long) dst) == 0) {
354 if (len >= 4) {
355 ioread32_rep(fifo, dst, len >> 2);
356 index = len & ~0x03;
357 }
358 if (len & 0x02) {
359 *(u16 *)&dst[index] = __raw_readw(fifo);
360 index += 2;
361 }
362 } else {
363 if (len >= 2) {
364 ioread16_rep(fifo, dst, len >> 1);
365 index = len & ~0x01;
366 }
367 }
368 if (len & 0x01)
369 dst[index] = __raw_readb(fifo);
370 } else {
371 /* byte aligned */
372 ioread8_rep(fifo, dst, len);
373 }
374}
375
376/*
377 * Old style IO functions
378 */
379u8 (*musb_readb)(const void __iomem *addr, unsigned offset);
380EXPORT_SYMBOL_GPL(musb_readb);
381
382void (*musb_writeb)(void __iomem *addr, unsigned offset, u8 data);
383EXPORT_SYMBOL_GPL(musb_writeb);
384
385u16 (*musb_readw)(const void __iomem *addr, unsigned offset);
386EXPORT_SYMBOL_GPL(musb_readw);
387
388void (*musb_writew)(void __iomem *addr, unsigned offset, u16 data);
389EXPORT_SYMBOL_GPL(musb_writew);
390
391u32 (*musb_readl)(const void __iomem *addr, unsigned offset);
392EXPORT_SYMBOL_GPL(musb_readl);
393
394void (*musb_writel)(void __iomem *addr, unsigned offset, u32 data);
395EXPORT_SYMBOL_GPL(musb_writel);
396
397#ifndef CONFIG_MUSB_PIO_ONLY
398struct dma_controller *
399(*musb_dma_controller_create)(struct musb *musb, void __iomem *base);
400EXPORT_SYMBOL(musb_dma_controller_create);
401
402void (*musb_dma_controller_destroy)(struct dma_controller *c);
403EXPORT_SYMBOL(musb_dma_controller_destroy);
404#endif
405
406/*
407 * New style IO functions
408 */
409void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
410{
411 return hw_ep->musb->io.read_fifo(hw_ep, len, dst);
412}
413
414void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
415{
416 return hw_ep->musb->io.write_fifo(hw_ep, len, src);
417}
418
419/*-------------------------------------------------------------------------*/
420
421/* for high speed test mode; see USB 2.0 spec 7.1.20 */
422static const u8 musb_test_packet[53] = {
423 /* implicit SYNC then DATA0 to start */
424
425 /* JKJKJKJK x9 */
426 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
427 /* JJKKJJKK x8 */
428 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
429 /* JJJJKKKK x8 */
430 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
431 /* JJJJJJJKKKKKKK x8 */
432 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
433 /* JJJJJJJK x8 */
434 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
435 /* JKKKKKKK x10, JK */
436 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
437
438 /* implicit CRC16 then EOP to end */
439};
440
441void musb_load_testpacket(struct musb *musb)
442{
443 void __iomem *regs = musb->endpoints[0].regs;
444
445 musb_ep_select(musb->mregs, 0);
446 musb_write_fifo(musb->control_ep,
447 sizeof(musb_test_packet), musb_test_packet);
448 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
449}
450
451/*-------------------------------------------------------------------------*/
452
453/*
454 * Handles OTG hnp timeouts, such as b_ase0_brst
455 */
456static void musb_otg_timer_func(unsigned long data)
457{
458 struct musb *musb = (struct musb *)data;
459 unsigned long flags;
460
461 spin_lock_irqsave(&musb->lock, flags);
462 switch (musb->xceiv->otg->state) {
463 case OTG_STATE_B_WAIT_ACON:
464 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n");
465 musb_g_disconnect(musb);
466 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
467 musb->is_active = 0;
468 break;
469 case OTG_STATE_A_SUSPEND:
470 case OTG_STATE_A_WAIT_BCON:
471 dev_dbg(musb->controller, "HNP: %s timeout\n",
472 usb_otg_state_string(musb->xceiv->otg->state));
473 musb_platform_set_vbus(musb, 0);
474 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
475 break;
476 default:
477 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
478 usb_otg_state_string(musb->xceiv->otg->state));
479 }
480 spin_unlock_irqrestore(&musb->lock, flags);
481}
482
483/*
484 * Stops the HNP transition. Caller must take care of locking.
485 */
486void musb_hnp_stop(struct musb *musb)
487{
488 struct usb_hcd *hcd = musb->hcd;
489 void __iomem *mbase = musb->mregs;
490 u8 reg;
491
492 dev_dbg(musb->controller, "HNP: stop from %s\n",
493 usb_otg_state_string(musb->xceiv->otg->state));
494
495 switch (musb->xceiv->otg->state) {
496 case OTG_STATE_A_PERIPHERAL:
497 musb_g_disconnect(musb);
498 dev_dbg(musb->controller, "HNP: back to %s\n",
499 usb_otg_state_string(musb->xceiv->otg->state));
500 break;
501 case OTG_STATE_B_HOST:
502 dev_dbg(musb->controller, "HNP: Disabling HR\n");
503 if (hcd)
504 hcd->self.is_b_host = 0;
505 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
506 MUSB_DEV_MODE(musb);
507 reg = musb_readb(mbase, MUSB_POWER);
508 reg |= MUSB_POWER_SUSPENDM;
509 musb_writeb(mbase, MUSB_POWER, reg);
510 /* REVISIT: Start SESSION_REQUEST here? */
511 break;
512 default:
513 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n",
514 usb_otg_state_string(musb->xceiv->otg->state));
515 }
516
517 /*
518 * When returning to A state after HNP, avoid hub_port_rebounce(),
519 * which cause occasional OPT A "Did not receive reset after connect"
520 * errors.
521 */
522 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
523}
524
525static void musb_recover_from_babble(struct musb *musb);
526
527/*
528 * Interrupt Service Routine to record USB "global" interrupts.
529 * Since these do not happen often and signify things of
530 * paramount importance, it seems OK to check them individually;
531 * the order of the tests is specified in the manual
532 *
533 * @param musb instance pointer
534 * @param int_usb register contents
535 * @param devctl
536 * @param power
537 */
538
539static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
540 u8 devctl)
541{
542 irqreturn_t handled = IRQ_NONE;
543
544 dev_dbg(musb->controller, "<== DevCtl=%02x, int_usb=0x%x\n", devctl,
545 int_usb);
546
547 /* in host mode, the peripheral may issue remote wakeup.
548 * in peripheral mode, the host may resume the link.
549 * spurious RESUME irqs happen too, paired with SUSPEND.
550 */
551 if (int_usb & MUSB_INTR_RESUME) {
552 handled = IRQ_HANDLED;
553 dev_dbg(musb->controller, "RESUME (%s)\n",
554 usb_otg_state_string(musb->xceiv->otg->state));
555
556 if (devctl & MUSB_DEVCTL_HM) {
557 switch (musb->xceiv->otg->state) {
558 case OTG_STATE_A_SUSPEND:
559 /* remote wakeup? later, GetPortStatus
560 * will stop RESUME signaling
561 */
562
563 musb->port1_status |=
564 (USB_PORT_STAT_C_SUSPEND << 16)
565 | MUSB_PORT_STAT_RESUME;
566 musb->rh_timer = jiffies
567 + msecs_to_jiffies(USB_RESUME_TIMEOUT);
568 musb->need_finish_resume = 1;
569
570 musb->xceiv->otg->state = OTG_STATE_A_HOST;
571 musb->is_active = 1;
572 musb_host_resume_root_hub(musb);
573 break;
574 case OTG_STATE_B_WAIT_ACON:
575 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
576 musb->is_active = 1;
577 MUSB_DEV_MODE(musb);
578 break;
579 default:
580 WARNING("bogus %s RESUME (%s)\n",
581 "host",
582 usb_otg_state_string(musb->xceiv->otg->state));
583 }
584 } else {
585 switch (musb->xceiv->otg->state) {
586 case OTG_STATE_A_SUSPEND:
587 /* possibly DISCONNECT is upcoming */
588 musb->xceiv->otg->state = OTG_STATE_A_HOST;
589 musb_host_resume_root_hub(musb);
590 break;
591 case OTG_STATE_B_WAIT_ACON:
592 case OTG_STATE_B_PERIPHERAL:
593 /* disconnect while suspended? we may
594 * not get a disconnect irq...
595 */
596 if ((devctl & MUSB_DEVCTL_VBUS)
597 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
598 ) {
599 musb->int_usb |= MUSB_INTR_DISCONNECT;
600 musb->int_usb &= ~MUSB_INTR_SUSPEND;
601 break;
602 }
603 musb_g_resume(musb);
604 break;
605 case OTG_STATE_B_IDLE:
606 musb->int_usb &= ~MUSB_INTR_SUSPEND;
607 break;
608 default:
609 WARNING("bogus %s RESUME (%s)\n",
610 "peripheral",
611 usb_otg_state_string(musb->xceiv->otg->state));
612 }
613 }
614 }
615
616 /* see manual for the order of the tests */
617 if (int_usb & MUSB_INTR_SESSREQ) {
618 void __iomem *mbase = musb->mregs;
619
620 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
621 && (devctl & MUSB_DEVCTL_BDEVICE)) {
622 dev_dbg(musb->controller, "SessReq while on B state\n");
623 return IRQ_HANDLED;
624 }
625
626 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n",
627 usb_otg_state_string(musb->xceiv->otg->state));
628
629 /* IRQ arrives from ID pin sense or (later, if VBUS power
630 * is removed) SRP. responses are time critical:
631 * - turn on VBUS (with silicon-specific mechanism)
632 * - go through A_WAIT_VRISE
633 * - ... to A_WAIT_BCON.
634 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
635 */
636 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
637 musb->ep0_stage = MUSB_EP0_START;
638 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
639 MUSB_HST_MODE(musb);
640 musb_platform_set_vbus(musb, 1);
641
642 handled = IRQ_HANDLED;
643 }
644
645 if (int_usb & MUSB_INTR_VBUSERROR) {
646 int ignore = 0;
647
648 /* During connection as an A-Device, we may see a short
649 * current spikes causing voltage drop, because of cable
650 * and peripheral capacitance combined with vbus draw.
651 * (So: less common with truly self-powered devices, where
652 * vbus doesn't act like a power supply.)
653 *
654 * Such spikes are short; usually less than ~500 usec, max
655 * of ~2 msec. That is, they're not sustained overcurrent
656 * errors, though they're reported using VBUSERROR irqs.
657 *
658 * Workarounds: (a) hardware: use self powered devices.
659 * (b) software: ignore non-repeated VBUS errors.
660 *
661 * REVISIT: do delays from lots of DEBUG_KERNEL checks
662 * make trouble here, keeping VBUS < 4.4V ?
663 */
664 switch (musb->xceiv->otg->state) {
665 case OTG_STATE_A_HOST:
666 /* recovery is dicey once we've gotten past the
667 * initial stages of enumeration, but if VBUS
668 * stayed ok at the other end of the link, and
669 * another reset is due (at least for high speed,
670 * to redo the chirp etc), it might work OK...
671 */
672 case OTG_STATE_A_WAIT_BCON:
673 case OTG_STATE_A_WAIT_VRISE:
674 if (musb->vbuserr_retry) {
675 void __iomem *mbase = musb->mregs;
676
677 musb->vbuserr_retry--;
678 ignore = 1;
679 devctl |= MUSB_DEVCTL_SESSION;
680 musb_writeb(mbase, MUSB_DEVCTL, devctl);
681 } else {
682 musb->port1_status |=
683 USB_PORT_STAT_OVERCURRENT
684 | (USB_PORT_STAT_C_OVERCURRENT << 16);
685 }
686 break;
687 default:
688 break;
689 }
690
691 dev_printk(ignore ? KERN_DEBUG : KERN_ERR, musb->controller,
692 "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
693 usb_otg_state_string(musb->xceiv->otg->state),
694 devctl,
695 ({ char *s;
696 switch (devctl & MUSB_DEVCTL_VBUS) {
697 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
698 s = "<SessEnd"; break;
699 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
700 s = "<AValid"; break;
701 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
702 s = "<VBusValid"; break;
703 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
704 default:
705 s = "VALID"; break;
706 } s; }),
707 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
708 musb->port1_status);
709
710 /* go through A_WAIT_VFALL then start a new session */
711 if (!ignore)
712 musb_platform_set_vbus(musb, 0);
713 handled = IRQ_HANDLED;
714 }
715
716 if (int_usb & MUSB_INTR_SUSPEND) {
717 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x\n",
718 usb_otg_state_string(musb->xceiv->otg->state), devctl);
719 handled = IRQ_HANDLED;
720
721 switch (musb->xceiv->otg->state) {
722 case OTG_STATE_A_PERIPHERAL:
723 /* We also come here if the cable is removed, since
724 * this silicon doesn't report ID-no-longer-grounded.
725 *
726 * We depend on T(a_wait_bcon) to shut us down, and
727 * hope users don't do anything dicey during this
728 * undesired detour through A_WAIT_BCON.
729 */
730 musb_hnp_stop(musb);
731 musb_host_resume_root_hub(musb);
732 musb_root_disconnect(musb);
733 musb_platform_try_idle(musb, jiffies
734 + msecs_to_jiffies(musb->a_wait_bcon
735 ? : OTG_TIME_A_WAIT_BCON));
736
737 break;
738 case OTG_STATE_B_IDLE:
739 if (!musb->is_active)
740 break;
741 case OTG_STATE_B_PERIPHERAL:
742 musb_g_suspend(musb);
743 musb->is_active = musb->g.b_hnp_enable;
744 if (musb->is_active) {
745 musb->xceiv->otg->state = OTG_STATE_B_WAIT_ACON;
746 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
747 mod_timer(&musb->otg_timer, jiffies
748 + msecs_to_jiffies(
749 OTG_TIME_B_ASE0_BRST));
750 }
751 break;
752 case OTG_STATE_A_WAIT_BCON:
753 if (musb->a_wait_bcon != 0)
754 musb_platform_try_idle(musb, jiffies
755 + msecs_to_jiffies(musb->a_wait_bcon));
756 break;
757 case OTG_STATE_A_HOST:
758 musb->xceiv->otg->state = OTG_STATE_A_SUSPEND;
759 musb->is_active = musb->hcd->self.b_hnp_enable;
760 break;
761 case OTG_STATE_B_HOST:
762 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
763 dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n");
764 break;
765 default:
766 /* "should not happen" */
767 musb->is_active = 0;
768 break;
769 }
770 }
771
772 if (int_usb & MUSB_INTR_CONNECT) {
773 struct usb_hcd *hcd = musb->hcd;
774
775 handled = IRQ_HANDLED;
776 musb->is_active = 1;
777
778 musb->ep0_stage = MUSB_EP0_START;
779
780 musb->intrtxe = musb->epmask;
781 musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe);
782 musb->intrrxe = musb->epmask & 0xfffe;
783 musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe);
784 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
785 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
786 |USB_PORT_STAT_HIGH_SPEED
787 |USB_PORT_STAT_ENABLE
788 );
789 musb->port1_status |= USB_PORT_STAT_CONNECTION
790 |(USB_PORT_STAT_C_CONNECTION << 16);
791
792 /* high vs full speed is just a guess until after reset */
793 if (devctl & MUSB_DEVCTL_LSDEV)
794 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
795
796 /* indicate new connection to OTG machine */
797 switch (musb->xceiv->otg->state) {
798 case OTG_STATE_B_PERIPHERAL:
799 if (int_usb & MUSB_INTR_SUSPEND) {
800 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
801 int_usb &= ~MUSB_INTR_SUSPEND;
802 goto b_host;
803 } else
804 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
805 break;
806 case OTG_STATE_B_WAIT_ACON:
807 dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n");
808b_host:
809 musb->xceiv->otg->state = OTG_STATE_B_HOST;
810 if (musb->hcd)
811 musb->hcd->self.is_b_host = 1;
812 del_timer(&musb->otg_timer);
813 break;
814 default:
815 if ((devctl & MUSB_DEVCTL_VBUS)
816 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
817 musb->xceiv->otg->state = OTG_STATE_A_HOST;
818 if (hcd)
819 hcd->self.is_b_host = 0;
820 }
821 break;
822 }
823
824 musb_host_poke_root_hub(musb);
825
826 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",
827 usb_otg_state_string(musb->xceiv->otg->state), devctl);
828 }
829
830 if (int_usb & MUSB_INTR_DISCONNECT) {
831 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n",
832 usb_otg_state_string(musb->xceiv->otg->state),
833 MUSB_MODE(musb), devctl);
834 handled = IRQ_HANDLED;
835
836 switch (musb->xceiv->otg->state) {
837 case OTG_STATE_A_HOST:
838 case OTG_STATE_A_SUSPEND:
839 musb_host_resume_root_hub(musb);
840 musb_root_disconnect(musb);
841 if (musb->a_wait_bcon != 0)
842 musb_platform_try_idle(musb, jiffies
843 + msecs_to_jiffies(musb->a_wait_bcon));
844 break;
845 case OTG_STATE_B_HOST:
846 /* REVISIT this behaves for "real disconnect"
847 * cases; make sure the other transitions from
848 * from B_HOST act right too. The B_HOST code
849 * in hnp_stop() is currently not used...
850 */
851 musb_root_disconnect(musb);
852 if (musb->hcd)
853 musb->hcd->self.is_b_host = 0;
854 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
855 MUSB_DEV_MODE(musb);
856 musb_g_disconnect(musb);
857 break;
858 case OTG_STATE_A_PERIPHERAL:
859 musb_hnp_stop(musb);
860 musb_root_disconnect(musb);
861 /* FALLTHROUGH */
862 case OTG_STATE_B_WAIT_ACON:
863 /* FALLTHROUGH */
864 case OTG_STATE_B_PERIPHERAL:
865 case OTG_STATE_B_IDLE:
866 musb_g_disconnect(musb);
867 break;
868 default:
869 WARNING("unhandled DISCONNECT transition (%s)\n",
870 usb_otg_state_string(musb->xceiv->otg->state));
871 break;
872 }
873 }
874
875 /* mentor saves a bit: bus reset and babble share the same irq.
876 * only host sees babble; only peripheral sees bus reset.
877 */
878 if (int_usb & MUSB_INTR_RESET) {
879 handled = IRQ_HANDLED;
880 if (devctl & MUSB_DEVCTL_HM) {
881 /*
882 * When BABBLE happens what we can depends on which
883 * platform MUSB is running, because some platforms
884 * implemented proprietary means for 'recovering' from
885 * Babble conditions. One such platform is AM335x. In
886 * most cases, however, the only thing we can do is
887 * drop the session.
888 */
889 dev_err(musb->controller, "Babble\n");
890
891 if (is_host_active(musb))
892 musb_recover_from_babble(musb);
893 } else {
894 dev_dbg(musb->controller, "BUS RESET as %s\n",
895 usb_otg_state_string(musb->xceiv->otg->state));
896 switch (musb->xceiv->otg->state) {
897 case OTG_STATE_A_SUSPEND:
898 musb_g_reset(musb);
899 /* FALLTHROUGH */
900 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
901 /* never use invalid T(a_wait_bcon) */
902 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n",
903 usb_otg_state_string(musb->xceiv->otg->state),
904 TA_WAIT_BCON(musb));
905 mod_timer(&musb->otg_timer, jiffies
906 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
907 break;
908 case OTG_STATE_A_PERIPHERAL:
909 del_timer(&musb->otg_timer);
910 musb_g_reset(musb);
911 break;
912 case OTG_STATE_B_WAIT_ACON:
913 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",
914 usb_otg_state_string(musb->xceiv->otg->state));
915 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
916 musb_g_reset(musb);
917 break;
918 case OTG_STATE_B_IDLE:
919 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
920 /* FALLTHROUGH */
921 case OTG_STATE_B_PERIPHERAL:
922 musb_g_reset(musb);
923 break;
924 default:
925 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n",
926 usb_otg_state_string(musb->xceiv->otg->state));
927 }
928 }
929 }
930
931#if 0
932/* REVISIT ... this would be for multiplexing periodic endpoints, or
933 * supporting transfer phasing to prevent exceeding ISO bandwidth
934 * limits of a given frame or microframe.
935 *
936 * It's not needed for peripheral side, which dedicates endpoints;
937 * though it _might_ use SOF irqs for other purposes.
938 *
939 * And it's not currently needed for host side, which also dedicates
940 * endpoints, relies on TX/RX interval registers, and isn't claimed
941 * to support ISO transfers yet.
942 */
943 if (int_usb & MUSB_INTR_SOF) {
944 void __iomem *mbase = musb->mregs;
945 struct musb_hw_ep *ep;
946 u8 epnum;
947 u16 frame;
948
949 dev_dbg(musb->controller, "START_OF_FRAME\n");
950 handled = IRQ_HANDLED;
951
952 /* start any periodic Tx transfers waiting for current frame */
953 frame = musb_readw(mbase, MUSB_FRAME);
954 ep = musb->endpoints;
955 for (epnum = 1; (epnum < musb->nr_endpoints)
956 && (musb->epmask >= (1 << epnum));
957 epnum++, ep++) {
958 /*
959 * FIXME handle framecounter wraps (12 bits)
960 * eliminate duplicated StartUrb logic
961 */
962 if (ep->dwWaitFrame >= frame) {
963 ep->dwWaitFrame = 0;
964 pr_debug("SOF --> periodic TX%s on %d\n",
965 ep->tx_channel ? " DMA" : "",
966 epnum);
967 if (!ep->tx_channel)
968 musb_h_tx_start(musb, epnum);
969 else
970 cppi_hostdma_start(musb, epnum);
971 }
972 } /* end of for loop */
973 }
974#endif
975
976 schedule_work(&musb->irq_work);
977
978 return handled;
979}
980
981/*-------------------------------------------------------------------------*/
982
983static void musb_disable_interrupts(struct musb *musb)
984{
985 void __iomem *mbase = musb->mregs;
986 u16 temp;
987
988 /* disable interrupts */
989 musb_writeb(mbase, MUSB_INTRUSBE, 0);
990 musb->intrtxe = 0;
991 musb_writew(mbase, MUSB_INTRTXE, 0);
992 musb->intrrxe = 0;
993 musb_writew(mbase, MUSB_INTRRXE, 0);
994
995 /* flush pending interrupts */
996 temp = musb_readb(mbase, MUSB_INTRUSB);
997 temp = musb_readw(mbase, MUSB_INTRTX);
998 temp = musb_readw(mbase, MUSB_INTRRX);
999}
1000
1001static void musb_enable_interrupts(struct musb *musb)
1002{
1003 void __iomem *regs = musb->mregs;
1004
1005 /* Set INT enable registers, enable interrupts */
1006 musb->intrtxe = musb->epmask;
1007 musb_writew(regs, MUSB_INTRTXE, musb->intrtxe);
1008 musb->intrrxe = musb->epmask & 0xfffe;
1009 musb_writew(regs, MUSB_INTRRXE, musb->intrrxe);
1010 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
1011
1012}
1013
1014static void musb_generic_disable(struct musb *musb)
1015{
1016 void __iomem *mbase = musb->mregs;
1017
1018 musb_disable_interrupts(musb);
1019
1020 /* off */
1021 musb_writeb(mbase, MUSB_DEVCTL, 0);
1022}
1023
1024/*
1025 * Program the HDRC to start (enable interrupts, dma, etc.).
1026 */
1027void musb_start(struct musb *musb)
1028{
1029 void __iomem *regs = musb->mregs;
1030 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
1031 u8 power;
1032
1033 dev_dbg(musb->controller, "<== devctl %02x\n", devctl);
1034
1035 musb_enable_interrupts(musb);
1036 musb_writeb(regs, MUSB_TESTMODE, 0);
1037
1038 power = MUSB_POWER_ISOUPDATE;
1039 /*
1040 * treating UNKNOWN as unspecified maximum speed, in which case
1041 * we will default to high-speed.
1042 */
1043 if (musb->config->maximum_speed == USB_SPEED_HIGH ||
1044 musb->config->maximum_speed == USB_SPEED_UNKNOWN)
1045 power |= MUSB_POWER_HSENAB;
1046 musb_writeb(regs, MUSB_POWER, power);
1047
1048 musb->is_active = 0;
1049 devctl = musb_readb(regs, MUSB_DEVCTL);
1050 devctl &= ~MUSB_DEVCTL_SESSION;
1051
1052 /* session started after:
1053 * (a) ID-grounded irq, host mode;
1054 * (b) vbus present/connect IRQ, peripheral mode;
1055 * (c) peripheral initiates, using SRP
1056 */
1057 if (musb->port_mode != MUSB_PORT_MODE_HOST &&
1058 musb->xceiv->otg->state != OTG_STATE_A_WAIT_BCON &&
1059 (devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) {
1060 musb->is_active = 1;
1061 } else {
1062 devctl |= MUSB_DEVCTL_SESSION;
1063 }
1064
1065 musb_platform_enable(musb);
1066 musb_writeb(regs, MUSB_DEVCTL, devctl);
1067}
1068
1069/*
1070 * Make the HDRC stop (disable interrupts, etc.);
1071 * reversible by musb_start
1072 * called on gadget driver unregister
1073 * with controller locked, irqs blocked
1074 * acts as a NOP unless some role activated the hardware
1075 */
1076void musb_stop(struct musb *musb)
1077{
1078 /* stop IRQs, timers, ... */
1079 musb_platform_disable(musb);
1080 musb_generic_disable(musb);
1081 dev_dbg(musb->controller, "HDRC disabled\n");
1082
1083 /* FIXME
1084 * - mark host and/or peripheral drivers unusable/inactive
1085 * - disable DMA (and enable it in HdrcStart)
1086 * - make sure we can musb_start() after musb_stop(); with
1087 * OTG mode, gadget driver module rmmod/modprobe cycles that
1088 * - ...
1089 */
1090 musb_platform_try_idle(musb, 0);
1091}
1092
1093static void musb_shutdown(struct platform_device *pdev)
1094{
1095 struct musb *musb = dev_to_musb(&pdev->dev);
1096 unsigned long flags;
1097
1098 pm_runtime_get_sync(musb->controller);
1099
1100 musb_host_cleanup(musb);
1101 musb_gadget_cleanup(musb);
1102
1103 spin_lock_irqsave(&musb->lock, flags);
1104 musb_platform_disable(musb);
1105 musb_generic_disable(musb);
1106 spin_unlock_irqrestore(&musb->lock, flags);
1107
1108 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1109 musb_platform_exit(musb);
1110
1111 pm_runtime_put(musb->controller);
1112 /* FIXME power down */
1113}
1114
1115
1116/*-------------------------------------------------------------------------*/
1117
1118/*
1119 * The silicon either has hard-wired endpoint configurations, or else
1120 * "dynamic fifo" sizing. The driver has support for both, though at this
1121 * writing only the dynamic sizing is very well tested. Since we switched
1122 * away from compile-time hardware parameters, we can no longer rely on
1123 * dead code elimination to leave only the relevant one in the object file.
1124 *
1125 * We don't currently use dynamic fifo setup capability to do anything
1126 * more than selecting one of a bunch of predefined configurations.
1127 */
1128static ushort fifo_mode;
1129
1130/* "modprobe ... fifo_mode=1" etc */
1131module_param(fifo_mode, ushort, 0);
1132MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1133
1134/*
1135 * tables defining fifo_mode values. define more if you like.
1136 * for host side, make sure both halves of ep1 are set up.
1137 */
1138
1139/* mode 0 - fits in 2KB */
1140static struct musb_fifo_cfg mode_0_cfg[] = {
1141{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1142{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1143{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1144{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1145{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1146};
1147
1148/* mode 1 - fits in 4KB */
1149static struct musb_fifo_cfg mode_1_cfg[] = {
1150{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1151{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1152{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1153{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1154{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1155};
1156
1157/* mode 2 - fits in 4KB */
1158static struct musb_fifo_cfg mode_2_cfg[] = {
1159{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1160{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1161{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1162{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1163{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1164{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1165};
1166
1167/* mode 3 - fits in 4KB */
1168static struct musb_fifo_cfg mode_3_cfg[] = {
1169{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1170{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1171{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1172{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1173{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1174{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1175};
1176
1177/* mode 4 - fits in 16KB */
1178static struct musb_fifo_cfg mode_4_cfg[] = {
1179{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1180{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1181{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1182{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1183{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1184{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1185{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1186{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1187{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1188{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1189{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1190{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1191{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1192{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1193{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1194{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1195{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1196{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1197{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1198{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1199{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1200{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1201{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1202{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1203{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1204{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1205{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1206};
1207
1208/* mode 5 - fits in 8KB */
1209static struct musb_fifo_cfg mode_5_cfg[] = {
1210{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1211{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1212{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1213{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1214{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1215{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1216{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1217{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1218{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1219{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1220{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1221{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1222{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1223{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1224{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1225{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1226{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1227{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1228{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1229{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1230{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1231{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1232{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1233{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1234{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1235{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1236{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1237};
1238
1239/*
1240 * configure a fifo; for non-shared endpoints, this may be called
1241 * once for a tx fifo and once for an rx fifo.
1242 *
1243 * returns negative errno or offset for next fifo.
1244 */
1245static int
1246fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1247 const struct musb_fifo_cfg *cfg, u16 offset)
1248{
1249 void __iomem *mbase = musb->mregs;
1250 int size = 0;
1251 u16 maxpacket = cfg->maxpacket;
1252 u16 c_off = offset >> 3;
1253 u8 c_size;
1254
1255 /* expect hw_ep has already been zero-initialized */
1256
1257 size = ffs(max(maxpacket, (u16) 8)) - 1;
1258 maxpacket = 1 << size;
1259
1260 c_size = size - 3;
1261 if (cfg->mode == BUF_DOUBLE) {
1262 if ((offset + (maxpacket << 1)) >
1263 (1 << (musb->config->ram_bits + 2)))
1264 return -EMSGSIZE;
1265 c_size |= MUSB_FIFOSZ_DPB;
1266 } else {
1267 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1268 return -EMSGSIZE;
1269 }
1270
1271 /* configure the FIFO */
1272 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1273
1274 /* EP0 reserved endpoint for control, bidirectional;
1275 * EP1 reserved for bulk, two unidirectional halves.
1276 */
1277 if (hw_ep->epnum == 1)
1278 musb->bulk_ep = hw_ep;
1279 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1280 switch (cfg->style) {
1281 case FIFO_TX:
1282 musb_write_txfifosz(mbase, c_size);
1283 musb_write_txfifoadd(mbase, c_off);
1284 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1285 hw_ep->max_packet_sz_tx = maxpacket;
1286 break;
1287 case FIFO_RX:
1288 musb_write_rxfifosz(mbase, c_size);
1289 musb_write_rxfifoadd(mbase, c_off);
1290 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1291 hw_ep->max_packet_sz_rx = maxpacket;
1292 break;
1293 case FIFO_RXTX:
1294 musb_write_txfifosz(mbase, c_size);
1295 musb_write_txfifoadd(mbase, c_off);
1296 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1297 hw_ep->max_packet_sz_rx = maxpacket;
1298
1299 musb_write_rxfifosz(mbase, c_size);
1300 musb_write_rxfifoadd(mbase, c_off);
1301 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1302 hw_ep->max_packet_sz_tx = maxpacket;
1303
1304 hw_ep->is_shared_fifo = true;
1305 break;
1306 }
1307
1308 /* NOTE rx and tx endpoint irqs aren't managed separately,
1309 * which happens to be ok
1310 */
1311 musb->epmask |= (1 << hw_ep->epnum);
1312
1313 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1314}
1315
1316static struct musb_fifo_cfg ep0_cfg = {
1317 .style = FIFO_RXTX, .maxpacket = 64,
1318};
1319
1320static int ep_config_from_table(struct musb *musb)
1321{
1322 const struct musb_fifo_cfg *cfg;
1323 unsigned i, n;
1324 int offset;
1325 struct musb_hw_ep *hw_ep = musb->endpoints;
1326
1327 if (musb->config->fifo_cfg) {
1328 cfg = musb->config->fifo_cfg;
1329 n = musb->config->fifo_cfg_size;
1330 goto done;
1331 }
1332
1333 switch (fifo_mode) {
1334 default:
1335 fifo_mode = 0;
1336 /* FALLTHROUGH */
1337 case 0:
1338 cfg = mode_0_cfg;
1339 n = ARRAY_SIZE(mode_0_cfg);
1340 break;
1341 case 1:
1342 cfg = mode_1_cfg;
1343 n = ARRAY_SIZE(mode_1_cfg);
1344 break;
1345 case 2:
1346 cfg = mode_2_cfg;
1347 n = ARRAY_SIZE(mode_2_cfg);
1348 break;
1349 case 3:
1350 cfg = mode_3_cfg;
1351 n = ARRAY_SIZE(mode_3_cfg);
1352 break;
1353 case 4:
1354 cfg = mode_4_cfg;
1355 n = ARRAY_SIZE(mode_4_cfg);
1356 break;
1357 case 5:
1358 cfg = mode_5_cfg;
1359 n = ARRAY_SIZE(mode_5_cfg);
1360 break;
1361 }
1362
1363 pr_debug("%s: setup fifo_mode %d\n", musb_driver_name, fifo_mode);
1364
1365
1366done:
1367 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1368 /* assert(offset > 0) */
1369
1370 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1371 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1372 */
1373
1374 for (i = 0; i < n; i++) {
1375 u8 epn = cfg->hw_ep_num;
1376
1377 if (epn >= musb->config->num_eps) {
1378 pr_debug("%s: invalid ep %d\n",
1379 musb_driver_name, epn);
1380 return -EINVAL;
1381 }
1382 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1383 if (offset < 0) {
1384 pr_debug("%s: mem overrun, ep %d\n",
1385 musb_driver_name, epn);
1386 return offset;
1387 }
1388 epn++;
1389 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1390 }
1391
1392 pr_debug("%s: %d/%d max ep, %d/%d memory\n",
1393 musb_driver_name,
1394 n + 1, musb->config->num_eps * 2 - 1,
1395 offset, (1 << (musb->config->ram_bits + 2)));
1396
1397 if (!musb->bulk_ep) {
1398 pr_debug("%s: missing bulk\n", musb_driver_name);
1399 return -EINVAL;
1400 }
1401
1402 return 0;
1403}
1404
1405
1406/*
1407 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1408 * @param musb the controller
1409 */
1410static int ep_config_from_hw(struct musb *musb)
1411{
1412 u8 epnum = 0;
1413 struct musb_hw_ep *hw_ep;
1414 void __iomem *mbase = musb->mregs;
1415 int ret = 0;
1416
1417 dev_dbg(musb->controller, "<== static silicon ep config\n");
1418
1419 /* FIXME pick up ep0 maxpacket size */
1420
1421 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1422 musb_ep_select(mbase, epnum);
1423 hw_ep = musb->endpoints + epnum;
1424
1425 ret = musb_read_fifosize(musb, hw_ep, epnum);
1426 if (ret < 0)
1427 break;
1428
1429 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1430
1431 /* pick an RX/TX endpoint for bulk */
1432 if (hw_ep->max_packet_sz_tx < 512
1433 || hw_ep->max_packet_sz_rx < 512)
1434 continue;
1435
1436 /* REVISIT: this algorithm is lazy, we should at least
1437 * try to pick a double buffered endpoint.
1438 */
1439 if (musb->bulk_ep)
1440 continue;
1441 musb->bulk_ep = hw_ep;
1442 }
1443
1444 if (!musb->bulk_ep) {
1445 pr_debug("%s: missing bulk\n", musb_driver_name);
1446 return -EINVAL;
1447 }
1448
1449 return 0;
1450}
1451
1452enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1453
1454/* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1455 * configure endpoints, or take their config from silicon
1456 */
1457static int musb_core_init(u16 musb_type, struct musb *musb)
1458{
1459 u8 reg;
1460 char *type;
1461 char aInfo[90], aRevision[32], aDate[12];
1462 void __iomem *mbase = musb->mregs;
1463 int status = 0;
1464 int i;
1465
1466 /* log core options (read using indexed model) */
1467 reg = musb_read_configdata(mbase);
1468
1469 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1470 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1471 strcat(aInfo, ", dyn FIFOs");
1472 musb->dyn_fifo = true;
1473 }
1474 if (reg & MUSB_CONFIGDATA_MPRXE) {
1475 strcat(aInfo, ", bulk combine");
1476 musb->bulk_combine = true;
1477 }
1478 if (reg & MUSB_CONFIGDATA_MPTXE) {
1479 strcat(aInfo, ", bulk split");
1480 musb->bulk_split = true;
1481 }
1482 if (reg & MUSB_CONFIGDATA_HBRXE) {
1483 strcat(aInfo, ", HB-ISO Rx");
1484 musb->hb_iso_rx = true;
1485 }
1486 if (reg & MUSB_CONFIGDATA_HBTXE) {
1487 strcat(aInfo, ", HB-ISO Tx");
1488 musb->hb_iso_tx = true;
1489 }
1490 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1491 strcat(aInfo, ", SoftConn");
1492
1493 pr_debug("%s: ConfigData=0x%02x (%s)\n", musb_driver_name, reg, aInfo);
1494
1495 aDate[0] = 0;
1496 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1497 musb->is_multipoint = 1;
1498 type = "M";
1499 } else {
1500 musb->is_multipoint = 0;
1501 type = "";
1502#ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1503 pr_err("%s: kernel must blacklist external hubs\n",
1504 musb_driver_name);
1505#endif
1506 }
1507
1508 /* log release info */
1509 musb->hwvers = musb_read_hwvers(mbase);
1510 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1511 MUSB_HWVERS_MINOR(musb->hwvers),
1512 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1513 pr_debug("%s: %sHDRC RTL version %s %s\n",
1514 musb_driver_name, type, aRevision, aDate);
1515
1516 /* configure ep0 */
1517 musb_configure_ep0(musb);
1518
1519 /* discover endpoint configuration */
1520 musb->nr_endpoints = 1;
1521 musb->epmask = 1;
1522
1523 if (musb->dyn_fifo)
1524 status = ep_config_from_table(musb);
1525 else
1526 status = ep_config_from_hw(musb);
1527
1528 if (status < 0)
1529 return status;
1530
1531 /* finish init, and print endpoint config */
1532 for (i = 0; i < musb->nr_endpoints; i++) {
1533 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1534
1535 hw_ep->fifo = musb->io.fifo_offset(i) + mbase;
1536#if IS_ENABLED(CONFIG_USB_MUSB_TUSB6010)
1537 if (musb->io.quirks & MUSB_IN_TUSB) {
1538 hw_ep->fifo_async = musb->async + 0x400 +
1539 musb->io.fifo_offset(i);
1540 hw_ep->fifo_sync = musb->sync + 0x400 +
1541 musb->io.fifo_offset(i);
1542 hw_ep->fifo_sync_va =
1543 musb->sync_va + 0x400 + musb->io.fifo_offset(i);
1544
1545 if (i == 0)
1546 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1547 else
1548 hw_ep->conf = mbase + 0x400 +
1549 (((i - 1) & 0xf) << 2);
1550 }
1551#endif
1552
1553 hw_ep->regs = musb->io.ep_offset(i, 0) + mbase;
1554 hw_ep->rx_reinit = 1;
1555 hw_ep->tx_reinit = 1;
1556
1557 if (hw_ep->max_packet_sz_tx) {
1558 dev_dbg(musb->controller,
1559 "%s: hw_ep %d%s, %smax %d\n",
1560 musb_driver_name, i,
1561 hw_ep->is_shared_fifo ? "shared" : "tx",
1562 hw_ep->tx_double_buffered
1563 ? "doublebuffer, " : "",
1564 hw_ep->max_packet_sz_tx);
1565 }
1566 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1567 dev_dbg(musb->controller,
1568 "%s: hw_ep %d%s, %smax %d\n",
1569 musb_driver_name, i,
1570 "rx",
1571 hw_ep->rx_double_buffered
1572 ? "doublebuffer, " : "",
1573 hw_ep->max_packet_sz_rx);
1574 }
1575 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1576 dev_dbg(musb->controller, "hw_ep %d not configured\n", i);
1577 }
1578
1579 return 0;
1580}
1581
1582/*-------------------------------------------------------------------------*/
1583
1584/*
1585 * handle all the irqs defined by the HDRC core. for now we expect: other
1586 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1587 * will be assigned, and the irq will already have been acked.
1588 *
1589 * called in irq context with spinlock held, irqs blocked
1590 */
1591irqreturn_t musb_interrupt(struct musb *musb)
1592{
1593 irqreturn_t retval = IRQ_NONE;
1594 unsigned long status;
1595 unsigned long epnum;
1596 u8 devctl;
1597
1598 if (!musb->int_usb && !musb->int_tx && !musb->int_rx)
1599 return IRQ_NONE;
1600
1601 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1602
1603 dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n",
1604 is_host_active(musb) ? "host" : "peripheral",
1605 musb->int_usb, musb->int_tx, musb->int_rx);
1606
1607 /**
1608 * According to Mentor Graphics' documentation, flowchart on page 98,
1609 * IRQ should be handled as follows:
1610 *
1611 * . Resume IRQ
1612 * . Session Request IRQ
1613 * . VBUS Error IRQ
1614 * . Suspend IRQ
1615 * . Connect IRQ
1616 * . Disconnect IRQ
1617 * . Reset/Babble IRQ
1618 * . SOF IRQ (we're not using this one)
1619 * . Endpoint 0 IRQ
1620 * . TX Endpoints
1621 * . RX Endpoints
1622 *
1623 * We will be following that flowchart in order to avoid any problems
1624 * that might arise with internal Finite State Machine.
1625 */
1626
1627 if (musb->int_usb)
1628 retval |= musb_stage0_irq(musb, musb->int_usb, devctl);
1629
1630 if (musb->int_tx & 1) {
1631 if (is_host_active(musb))
1632 retval |= musb_h_ep0_irq(musb);
1633 else
1634 retval |= musb_g_ep0_irq(musb);
1635
1636 /* we have just handled endpoint 0 IRQ, clear it */
1637 musb->int_tx &= ~BIT(0);
1638 }
1639
1640 status = musb->int_tx;
1641
1642 for_each_set_bit(epnum, &status, 16) {
1643 retval = IRQ_HANDLED;
1644 if (is_host_active(musb))
1645 musb_host_tx(musb, epnum);
1646 else
1647 musb_g_tx(musb, epnum);
1648 }
1649
1650 status = musb->int_rx;
1651
1652 for_each_set_bit(epnum, &status, 16) {
1653 retval = IRQ_HANDLED;
1654 if (is_host_active(musb))
1655 musb_host_rx(musb, epnum);
1656 else
1657 musb_g_rx(musb, epnum);
1658 }
1659
1660 return retval;
1661}
1662EXPORT_SYMBOL_GPL(musb_interrupt);
1663
1664#ifndef CONFIG_MUSB_PIO_ONLY
1665static bool use_dma = 1;
1666
1667/* "modprobe ... use_dma=0" etc */
1668module_param(use_dma, bool, 0644);
1669MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1670
1671void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1672{
1673 /* called with controller lock already held */
1674
1675 if (!epnum) {
1676 if (!is_cppi_enabled(musb)) {
1677 /* endpoint 0 */
1678 if (is_host_active(musb))
1679 musb_h_ep0_irq(musb);
1680 else
1681 musb_g_ep0_irq(musb);
1682 }
1683 } else {
1684 /* endpoints 1..15 */
1685 if (transmit) {
1686 if (is_host_active(musb))
1687 musb_host_tx(musb, epnum);
1688 else
1689 musb_g_tx(musb, epnum);
1690 } else {
1691 /* receive */
1692 if (is_host_active(musb))
1693 musb_host_rx(musb, epnum);
1694 else
1695 musb_g_rx(musb, epnum);
1696 }
1697 }
1698}
1699EXPORT_SYMBOL_GPL(musb_dma_completion);
1700
1701#else
1702#define use_dma 0
1703#endif
1704
1705static void (*musb_phy_callback)(enum musb_vbus_id_status status);
1706
1707/*
1708 * musb_mailbox - optional phy notifier function
1709 * @status phy state change
1710 *
1711 * Optionally gets called from the USB PHY. Note that the USB PHY must be
1712 * disabled at the point the phy_callback is registered or unregistered.
1713 */
1714void musb_mailbox(enum musb_vbus_id_status status)
1715{
1716 if (musb_phy_callback)
1717 musb_phy_callback(status);
1718
1719};
1720EXPORT_SYMBOL_GPL(musb_mailbox);
1721
1722/*-------------------------------------------------------------------------*/
1723
1724static ssize_t
1725musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1726{
1727 struct musb *musb = dev_to_musb(dev);
1728 unsigned long flags;
1729 int ret = -EINVAL;
1730
1731 spin_lock_irqsave(&musb->lock, flags);
1732 ret = sprintf(buf, "%s\n", usb_otg_state_string(musb->xceiv->otg->state));
1733 spin_unlock_irqrestore(&musb->lock, flags);
1734
1735 return ret;
1736}
1737
1738static ssize_t
1739musb_mode_store(struct device *dev, struct device_attribute *attr,
1740 const char *buf, size_t n)
1741{
1742 struct musb *musb = dev_to_musb(dev);
1743 unsigned long flags;
1744 int status;
1745
1746 spin_lock_irqsave(&musb->lock, flags);
1747 if (sysfs_streq(buf, "host"))
1748 status = musb_platform_set_mode(musb, MUSB_HOST);
1749 else if (sysfs_streq(buf, "peripheral"))
1750 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1751 else if (sysfs_streq(buf, "otg"))
1752 status = musb_platform_set_mode(musb, MUSB_OTG);
1753 else
1754 status = -EINVAL;
1755 spin_unlock_irqrestore(&musb->lock, flags);
1756
1757 return (status == 0) ? n : status;
1758}
1759static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1760
1761static ssize_t
1762musb_vbus_store(struct device *dev, struct device_attribute *attr,
1763 const char *buf, size_t n)
1764{
1765 struct musb *musb = dev_to_musb(dev);
1766 unsigned long flags;
1767 unsigned long val;
1768
1769 if (sscanf(buf, "%lu", &val) < 1) {
1770 dev_err(dev, "Invalid VBUS timeout ms value\n");
1771 return -EINVAL;
1772 }
1773
1774 spin_lock_irqsave(&musb->lock, flags);
1775 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1776 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1777 if (musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)
1778 musb->is_active = 0;
1779 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1780 spin_unlock_irqrestore(&musb->lock, flags);
1781
1782 return n;
1783}
1784
1785static ssize_t
1786musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1787{
1788 struct musb *musb = dev_to_musb(dev);
1789 unsigned long flags;
1790 unsigned long val;
1791 int vbus;
1792 u8 devctl;
1793
1794 spin_lock_irqsave(&musb->lock, flags);
1795 val = musb->a_wait_bcon;
1796 vbus = musb_platform_get_vbus_status(musb);
1797 if (vbus < 0) {
1798 /* Use default MUSB method by means of DEVCTL register */
1799 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1800 if ((devctl & MUSB_DEVCTL_VBUS)
1801 == (3 << MUSB_DEVCTL_VBUS_SHIFT))
1802 vbus = 1;
1803 else
1804 vbus = 0;
1805 }
1806 spin_unlock_irqrestore(&musb->lock, flags);
1807
1808 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1809 vbus ? "on" : "off", val);
1810}
1811static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1812
1813/* Gadget drivers can't know that a host is connected so they might want
1814 * to start SRP, but users can. This allows userspace to trigger SRP.
1815 */
1816static ssize_t
1817musb_srp_store(struct device *dev, struct device_attribute *attr,
1818 const char *buf, size_t n)
1819{
1820 struct musb *musb = dev_to_musb(dev);
1821 unsigned short srp;
1822
1823 if (sscanf(buf, "%hu", &srp) != 1
1824 || (srp != 1)) {
1825 dev_err(dev, "SRP: Value must be 1\n");
1826 return -EINVAL;
1827 }
1828
1829 if (srp == 1)
1830 musb_g_wakeup(musb);
1831
1832 return n;
1833}
1834static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1835
1836static struct attribute *musb_attributes[] = {
1837 &dev_attr_mode.attr,
1838 &dev_attr_vbus.attr,
1839 &dev_attr_srp.attr,
1840 NULL
1841};
1842
1843static const struct attribute_group musb_attr_group = {
1844 .attrs = musb_attributes,
1845};
1846
1847/* Only used to provide driver mode change events */
1848static void musb_irq_work(struct work_struct *data)
1849{
1850 struct musb *musb = container_of(data, struct musb, irq_work);
1851
1852 if (musb->xceiv->otg->state != musb->xceiv_old_state) {
1853 musb->xceiv_old_state = musb->xceiv->otg->state;
1854 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1855 }
1856}
1857
1858static void musb_recover_from_babble(struct musb *musb)
1859{
1860 int ret;
1861 u8 devctl;
1862
1863 musb_disable_interrupts(musb);
1864
1865 /*
1866 * wait at least 320 cycles of 60MHz clock. That's 5.3us, we will give
1867 * it some slack and wait for 10us.
1868 */
1869 udelay(10);
1870
1871 ret = musb_platform_recover(musb);
1872 if (ret) {
1873 musb_enable_interrupts(musb);
1874 return;
1875 }
1876
1877 /* drop session bit */
1878 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1879 devctl &= ~MUSB_DEVCTL_SESSION;
1880 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
1881
1882 /* tell usbcore about it */
1883 musb_root_disconnect(musb);
1884
1885 /*
1886 * When a babble condition occurs, the musb controller
1887 * removes the session bit and the endpoint config is lost.
1888 */
1889 if (musb->dyn_fifo)
1890 ret = ep_config_from_table(musb);
1891 else
1892 ret = ep_config_from_hw(musb);
1893
1894 /* restart session */
1895 if (ret == 0)
1896 musb_start(musb);
1897}
1898
1899/* --------------------------------------------------------------------------
1900 * Init support
1901 */
1902
1903static struct musb *allocate_instance(struct device *dev,
1904 const struct musb_hdrc_config *config, void __iomem *mbase)
1905{
1906 struct musb *musb;
1907 struct musb_hw_ep *ep;
1908 int epnum;
1909 int ret;
1910
1911 musb = devm_kzalloc(dev, sizeof(*musb), GFP_KERNEL);
1912 if (!musb)
1913 return NULL;
1914
1915 INIT_LIST_HEAD(&musb->control);
1916 INIT_LIST_HEAD(&musb->in_bulk);
1917 INIT_LIST_HEAD(&musb->out_bulk);
1918
1919 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1920 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
1921 musb->mregs = mbase;
1922 musb->ctrl_base = mbase;
1923 musb->nIrq = -ENODEV;
1924 musb->config = config;
1925 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
1926 for (epnum = 0, ep = musb->endpoints;
1927 epnum < musb->config->num_eps;
1928 epnum++, ep++) {
1929 ep->musb = musb;
1930 ep->epnum = epnum;
1931 }
1932
1933 musb->controller = dev;
1934
1935 ret = musb_host_alloc(musb);
1936 if (ret < 0)
1937 goto err_free;
1938
1939 dev_set_drvdata(dev, musb);
1940
1941 return musb;
1942
1943err_free:
1944 return NULL;
1945}
1946
1947static void musb_free(struct musb *musb)
1948{
1949 /* this has multiple entry modes. it handles fault cleanup after
1950 * probe(), where things may be partially set up, as well as rmmod
1951 * cleanup after everything's been de-activated.
1952 */
1953
1954#ifdef CONFIG_SYSFS
1955 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
1956#endif
1957
1958 if (musb->nIrq >= 0) {
1959 if (musb->irq_wake)
1960 disable_irq_wake(musb->nIrq);
1961 free_irq(musb->nIrq, musb);
1962 }
1963
1964 musb_host_free(musb);
1965}
1966
1967static void musb_deassert_reset(struct work_struct *work)
1968{
1969 struct musb *musb;
1970 unsigned long flags;
1971
1972 musb = container_of(work, struct musb, deassert_reset_work.work);
1973
1974 spin_lock_irqsave(&musb->lock, flags);
1975
1976 if (musb->port1_status & USB_PORT_STAT_RESET)
1977 musb_port_reset(musb, false);
1978
1979 spin_unlock_irqrestore(&musb->lock, flags);
1980}
1981
1982/*
1983 * Perform generic per-controller initialization.
1984 *
1985 * @dev: the controller (already clocked, etc)
1986 * @nIrq: IRQ number
1987 * @ctrl: virtual address of controller registers,
1988 * not yet corrected for platform-specific offsets
1989 */
1990static int
1991musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1992{
1993 int status;
1994 struct musb *musb;
1995 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
1996
1997 /* The driver might handle more features than the board; OK.
1998 * Fail when the board needs a feature that's not enabled.
1999 */
2000 if (!plat) {
2001 dev_dbg(dev, "no platform_data?\n");
2002 status = -ENODEV;
2003 goto fail0;
2004 }
2005
2006 /* allocate */
2007 musb = allocate_instance(dev, plat->config, ctrl);
2008 if (!musb) {
2009 status = -ENOMEM;
2010 goto fail0;
2011 }
2012
2013 spin_lock_init(&musb->lock);
2014 musb->board_set_power = plat->set_power;
2015 musb->min_power = plat->min_power;
2016 musb->ops = plat->platform_ops;
2017 musb->port_mode = plat->mode;
2018
2019 /*
2020 * Initialize the default IO functions. At least omap2430 needs
2021 * these early. We initialize the platform specific IO functions
2022 * later on.
2023 */
2024 musb_readb = musb_default_readb;
2025 musb_writeb = musb_default_writeb;
2026 musb_readw = musb_default_readw;
2027 musb_writew = musb_default_writew;
2028 musb_readl = musb_default_readl;
2029 musb_writel = musb_default_writel;
2030
2031 /* We need musb_read/write functions initialized for PM */
2032 pm_runtime_use_autosuspend(musb->controller);
2033 pm_runtime_set_autosuspend_delay(musb->controller, 200);
2034 pm_runtime_enable(musb->controller);
2035
2036 /* The musb_platform_init() call:
2037 * - adjusts musb->mregs
2038 * - sets the musb->isr
2039 * - may initialize an integrated transceiver
2040 * - initializes musb->xceiv, usually by otg_get_phy()
2041 * - stops powering VBUS
2042 *
2043 * There are various transceiver configurations. Blackfin,
2044 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
2045 * external/discrete ones in various flavors (twl4030 family,
2046 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
2047 */
2048 status = musb_platform_init(musb);
2049 if (status < 0)
2050 goto fail1;
2051
2052 if (!musb->isr) {
2053 status = -ENODEV;
2054 goto fail2;
2055 }
2056
2057 if (musb->ops->quirks)
2058 musb->io.quirks = musb->ops->quirks;
2059
2060 /* Most devices use indexed offset or flat offset */
2061 if (musb->io.quirks & MUSB_INDEXED_EP) {
2062 musb->io.ep_offset = musb_indexed_ep_offset;
2063 musb->io.ep_select = musb_indexed_ep_select;
2064 } else {
2065 musb->io.ep_offset = musb_flat_ep_offset;
2066 musb->io.ep_select = musb_flat_ep_select;
2067 }
2068 /* And override them with platform specific ops if specified. */
2069 if (musb->ops->ep_offset)
2070 musb->io.ep_offset = musb->ops->ep_offset;
2071 if (musb->ops->ep_select)
2072 musb->io.ep_select = musb->ops->ep_select;
2073
2074 /* At least tusb6010 has its own offsets */
2075 if (musb->ops->ep_offset)
2076 musb->io.ep_offset = musb->ops->ep_offset;
2077 if (musb->ops->ep_select)
2078 musb->io.ep_select = musb->ops->ep_select;
2079
2080 if (musb->ops->fifo_mode)
2081 fifo_mode = musb->ops->fifo_mode;
2082 else
2083 fifo_mode = 4;
2084
2085 if (musb->ops->fifo_offset)
2086 musb->io.fifo_offset = musb->ops->fifo_offset;
2087 else
2088 musb->io.fifo_offset = musb_default_fifo_offset;
2089
2090 if (musb->ops->busctl_offset)
2091 musb->io.busctl_offset = musb->ops->busctl_offset;
2092 else
2093 musb->io.busctl_offset = musb_default_busctl_offset;
2094
2095 if (musb->ops->readb)
2096 musb_readb = musb->ops->readb;
2097 if (musb->ops->writeb)
2098 musb_writeb = musb->ops->writeb;
2099 if (musb->ops->readw)
2100 musb_readw = musb->ops->readw;
2101 if (musb->ops->writew)
2102 musb_writew = musb->ops->writew;
2103 if (musb->ops->readl)
2104 musb_readl = musb->ops->readl;
2105 if (musb->ops->writel)
2106 musb_writel = musb->ops->writel;
2107
2108#ifndef CONFIG_MUSB_PIO_ONLY
2109 if (!musb->ops->dma_init || !musb->ops->dma_exit) {
2110 dev_err(dev, "DMA controller not set\n");
2111 status = -ENODEV;
2112 goto fail2;
2113 }
2114 musb_dma_controller_create = musb->ops->dma_init;
2115 musb_dma_controller_destroy = musb->ops->dma_exit;
2116#endif
2117
2118 if (musb->ops->read_fifo)
2119 musb->io.read_fifo = musb->ops->read_fifo;
2120 else
2121 musb->io.read_fifo = musb_default_read_fifo;
2122
2123 if (musb->ops->write_fifo)
2124 musb->io.write_fifo = musb->ops->write_fifo;
2125 else
2126 musb->io.write_fifo = musb_default_write_fifo;
2127
2128 if (!musb->xceiv->io_ops) {
2129 musb->xceiv->io_dev = musb->controller;
2130 musb->xceiv->io_priv = musb->mregs;
2131 musb->xceiv->io_ops = &musb_ulpi_access;
2132 }
2133
2134 if (musb->ops->phy_callback)
2135 musb_phy_callback = musb->ops->phy_callback;
2136
2137 pm_runtime_get_sync(musb->controller);
2138
2139 status = usb_phy_init(musb->xceiv);
2140 if (status < 0)
2141 goto err_usb_phy_init;
2142
2143 if (use_dma && dev->dma_mask) {
2144 musb->dma_controller =
2145 musb_dma_controller_create(musb, musb->mregs);
2146 if (IS_ERR(musb->dma_controller)) {
2147 status = PTR_ERR(musb->dma_controller);
2148 goto fail2_5;
2149 }
2150 }
2151
2152 /* be sure interrupts are disabled before connecting ISR */
2153 musb_platform_disable(musb);
2154 musb_generic_disable(musb);
2155
2156 /* Init IRQ workqueue before request_irq */
2157 INIT_WORK(&musb->irq_work, musb_irq_work);
2158 INIT_DELAYED_WORK(&musb->deassert_reset_work, musb_deassert_reset);
2159 INIT_DELAYED_WORK(&musb->finish_resume_work, musb_host_finish_resume);
2160
2161 /* setup musb parts of the core (especially endpoints) */
2162 status = musb_core_init(plat->config->multipoint
2163 ? MUSB_CONTROLLER_MHDRC
2164 : MUSB_CONTROLLER_HDRC, musb);
2165 if (status < 0)
2166 goto fail3;
2167
2168 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
2169
2170 /* attach to the IRQ */
2171 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
2172 dev_err(dev, "request_irq %d failed!\n", nIrq);
2173 status = -ENODEV;
2174 goto fail3;
2175 }
2176 musb->nIrq = nIrq;
2177 /* FIXME this handles wakeup irqs wrong */
2178 if (enable_irq_wake(nIrq) == 0) {
2179 musb->irq_wake = 1;
2180 device_init_wakeup(dev, 1);
2181 } else {
2182 musb->irq_wake = 0;
2183 }
2184
2185 /* program PHY to use external vBus if required */
2186 if (plat->extvbus) {
2187 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
2188 busctl |= MUSB_ULPI_USE_EXTVBUS;
2189 musb_write_ulpi_buscontrol(musb->mregs, busctl);
2190 }
2191
2192 if (musb->xceiv->otg->default_a) {
2193 MUSB_HST_MODE(musb);
2194 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
2195 } else {
2196 MUSB_DEV_MODE(musb);
2197 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
2198 }
2199
2200 switch (musb->port_mode) {
2201 case MUSB_PORT_MODE_HOST:
2202 status = musb_host_setup(musb, plat->power);
2203 if (status < 0)
2204 goto fail3;
2205 status = musb_platform_set_mode(musb, MUSB_HOST);
2206 break;
2207 case MUSB_PORT_MODE_GADGET:
2208 status = musb_gadget_setup(musb);
2209 if (status < 0)
2210 goto fail3;
2211 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
2212 break;
2213 case MUSB_PORT_MODE_DUAL_ROLE:
2214 status = musb_host_setup(musb, plat->power);
2215 if (status < 0)
2216 goto fail3;
2217 status = musb_gadget_setup(musb);
2218 if (status) {
2219 musb_host_cleanup(musb);
2220 goto fail3;
2221 }
2222 status = musb_platform_set_mode(musb, MUSB_OTG);
2223 break;
2224 default:
2225 dev_err(dev, "unsupported port mode %d\n", musb->port_mode);
2226 break;
2227 }
2228
2229 if (status < 0)
2230 goto fail3;
2231
2232 status = musb_init_debugfs(musb);
2233 if (status < 0)
2234 goto fail4;
2235
2236 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
2237 if (status)
2238 goto fail5;
2239
2240 pm_runtime_put(musb->controller);
2241
2242 /*
2243 * For why this is currently needed, see commit 3e43a0725637
2244 * ("usb: musb: core: add pm_runtime_irq_safe()")
2245 */
2246 pm_runtime_irq_safe(musb->controller);
2247
2248 return 0;
2249
2250fail5:
2251 musb_exit_debugfs(musb);
2252
2253fail4:
2254 musb_gadget_cleanup(musb);
2255 musb_host_cleanup(musb);
2256
2257fail3:
2258 cancel_work_sync(&musb->irq_work);
2259 cancel_delayed_work_sync(&musb->finish_resume_work);
2260 cancel_delayed_work_sync(&musb->deassert_reset_work);
2261 if (musb->dma_controller)
2262 musb_dma_controller_destroy(musb->dma_controller);
2263
2264fail2_5:
2265 usb_phy_shutdown(musb->xceiv);
2266
2267err_usb_phy_init:
2268 pm_runtime_put_sync(musb->controller);
2269
2270fail2:
2271 if (musb->irq_wake)
2272 device_init_wakeup(dev, 0);
2273 musb_platform_exit(musb);
2274
2275fail1:
2276 pm_runtime_disable(musb->controller);
2277 dev_err(musb->controller,
2278 "musb_init_controller failed with status %d\n", status);
2279
2280 musb_free(musb);
2281
2282fail0:
2283
2284 return status;
2285
2286}
2287
2288/*-------------------------------------------------------------------------*/
2289
2290/* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2291 * bridge to a platform device; this driver then suffices.
2292 */
2293static int musb_probe(struct platform_device *pdev)
2294{
2295 struct device *dev = &pdev->dev;
2296 int irq = platform_get_irq_byname(pdev, "mc");
2297 struct resource *iomem;
2298 void __iomem *base;
2299
2300 if (irq <= 0)
2301 return -ENODEV;
2302
2303 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2304 base = devm_ioremap_resource(dev, iomem);
2305 if (IS_ERR(base))
2306 return PTR_ERR(base);
2307
2308 return musb_init_controller(dev, irq, base);
2309}
2310
2311static int musb_remove(struct platform_device *pdev)
2312{
2313 struct device *dev = &pdev->dev;
2314 struct musb *musb = dev_to_musb(dev);
2315
2316 /* this gets called on rmmod.
2317 * - Host mode: host may still be active
2318 * - Peripheral mode: peripheral is deactivated (or never-activated)
2319 * - OTG mode: both roles are deactivated (or never-activated)
2320 */
2321 musb_exit_debugfs(musb);
2322 musb_shutdown(pdev);
2323 musb_phy_callback = NULL;
2324
2325 if (musb->dma_controller)
2326 musb_dma_controller_destroy(musb->dma_controller);
2327
2328 usb_phy_shutdown(musb->xceiv);
2329
2330 cancel_work_sync(&musb->irq_work);
2331 cancel_delayed_work_sync(&musb->finish_resume_work);
2332 cancel_delayed_work_sync(&musb->deassert_reset_work);
2333 musb_free(musb);
2334 device_init_wakeup(dev, 0);
2335 return 0;
2336}
2337
2338#ifdef CONFIG_PM
2339
2340static void musb_save_context(struct musb *musb)
2341{
2342 int i;
2343 void __iomem *musb_base = musb->mregs;
2344 void __iomem *epio;
2345
2346 musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2347 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2348 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
2349 musb->context.power = musb_readb(musb_base, MUSB_POWER);
2350 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2351 musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2352 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2353
2354 for (i = 0; i < musb->config->num_eps; ++i) {
2355 struct musb_hw_ep *hw_ep;
2356
2357 hw_ep = &musb->endpoints[i];
2358 if (!hw_ep)
2359 continue;
2360
2361 epio = hw_ep->regs;
2362 if (!epio)
2363 continue;
2364
2365 musb_writeb(musb_base, MUSB_INDEX, i);
2366 musb->context.index_regs[i].txmaxp =
2367 musb_readw(epio, MUSB_TXMAXP);
2368 musb->context.index_regs[i].txcsr =
2369 musb_readw(epio, MUSB_TXCSR);
2370 musb->context.index_regs[i].rxmaxp =
2371 musb_readw(epio, MUSB_RXMAXP);
2372 musb->context.index_regs[i].rxcsr =
2373 musb_readw(epio, MUSB_RXCSR);
2374
2375 if (musb->dyn_fifo) {
2376 musb->context.index_regs[i].txfifoadd =
2377 musb_read_txfifoadd(musb_base);
2378 musb->context.index_regs[i].rxfifoadd =
2379 musb_read_rxfifoadd(musb_base);
2380 musb->context.index_regs[i].txfifosz =
2381 musb_read_txfifosz(musb_base);
2382 musb->context.index_regs[i].rxfifosz =
2383 musb_read_rxfifosz(musb_base);
2384 }
2385
2386 musb->context.index_regs[i].txtype =
2387 musb_readb(epio, MUSB_TXTYPE);
2388 musb->context.index_regs[i].txinterval =
2389 musb_readb(epio, MUSB_TXINTERVAL);
2390 musb->context.index_regs[i].rxtype =
2391 musb_readb(epio, MUSB_RXTYPE);
2392 musb->context.index_regs[i].rxinterval =
2393 musb_readb(epio, MUSB_RXINTERVAL);
2394
2395 musb->context.index_regs[i].txfunaddr =
2396 musb_read_txfunaddr(musb, i);
2397 musb->context.index_regs[i].txhubaddr =
2398 musb_read_txhubaddr(musb, i);
2399 musb->context.index_regs[i].txhubport =
2400 musb_read_txhubport(musb, i);
2401
2402 musb->context.index_regs[i].rxfunaddr =
2403 musb_read_rxfunaddr(musb, i);
2404 musb->context.index_regs[i].rxhubaddr =
2405 musb_read_rxhubaddr(musb, i);
2406 musb->context.index_regs[i].rxhubport =
2407 musb_read_rxhubport(musb, i);
2408 }
2409}
2410
2411static void musb_restore_context(struct musb *musb)
2412{
2413 int i;
2414 void __iomem *musb_base = musb->mregs;
2415 void __iomem *epio;
2416 u8 power;
2417
2418 musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2419 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2420 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
2421
2422 /* Don't affect SUSPENDM/RESUME bits in POWER reg */
2423 power = musb_readb(musb_base, MUSB_POWER);
2424 power &= MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME;
2425 musb->context.power &= ~(MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME);
2426 power |= musb->context.power;
2427 musb_writeb(musb_base, MUSB_POWER, power);
2428
2429 musb_writew(musb_base, MUSB_INTRTXE, musb->intrtxe);
2430 musb_writew(musb_base, MUSB_INTRRXE, musb->intrrxe);
2431 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2432 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
2433
2434 for (i = 0; i < musb->config->num_eps; ++i) {
2435 struct musb_hw_ep *hw_ep;
2436
2437 hw_ep = &musb->endpoints[i];
2438 if (!hw_ep)
2439 continue;
2440
2441 epio = hw_ep->regs;
2442 if (!epio)
2443 continue;
2444
2445 musb_writeb(musb_base, MUSB_INDEX, i);
2446 musb_writew(epio, MUSB_TXMAXP,
2447 musb->context.index_regs[i].txmaxp);
2448 musb_writew(epio, MUSB_TXCSR,
2449 musb->context.index_regs[i].txcsr);
2450 musb_writew(epio, MUSB_RXMAXP,
2451 musb->context.index_regs[i].rxmaxp);
2452 musb_writew(epio, MUSB_RXCSR,
2453 musb->context.index_regs[i].rxcsr);
2454
2455 if (musb->dyn_fifo) {
2456 musb_write_txfifosz(musb_base,
2457 musb->context.index_regs[i].txfifosz);
2458 musb_write_rxfifosz(musb_base,
2459 musb->context.index_regs[i].rxfifosz);
2460 musb_write_txfifoadd(musb_base,
2461 musb->context.index_regs[i].txfifoadd);
2462 musb_write_rxfifoadd(musb_base,
2463 musb->context.index_regs[i].rxfifoadd);
2464 }
2465
2466 musb_writeb(epio, MUSB_TXTYPE,
2467 musb->context.index_regs[i].txtype);
2468 musb_writeb(epio, MUSB_TXINTERVAL,
2469 musb->context.index_regs[i].txinterval);
2470 musb_writeb(epio, MUSB_RXTYPE,
2471 musb->context.index_regs[i].rxtype);
2472 musb_writeb(epio, MUSB_RXINTERVAL,
2473
2474 musb->context.index_regs[i].rxinterval);
2475 musb_write_txfunaddr(musb, i,
2476 musb->context.index_regs[i].txfunaddr);
2477 musb_write_txhubaddr(musb, i,
2478 musb->context.index_regs[i].txhubaddr);
2479 musb_write_txhubport(musb, i,
2480 musb->context.index_regs[i].txhubport);
2481
2482 musb_write_rxfunaddr(musb, i,
2483 musb->context.index_regs[i].rxfunaddr);
2484 musb_write_rxhubaddr(musb, i,
2485 musb->context.index_regs[i].rxhubaddr);
2486 musb_write_rxhubport(musb, i,
2487 musb->context.index_regs[i].rxhubport);
2488 }
2489 musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
2490}
2491
2492static int musb_suspend(struct device *dev)
2493{
2494 struct musb *musb = dev_to_musb(dev);
2495 unsigned long flags;
2496
2497 musb_platform_disable(musb);
2498 musb_generic_disable(musb);
2499
2500 spin_lock_irqsave(&musb->lock, flags);
2501
2502 if (is_peripheral_active(musb)) {
2503 /* FIXME force disconnect unless we know USB will wake
2504 * the system up quickly enough to respond ...
2505 */
2506 } else if (is_host_active(musb)) {
2507 /* we know all the children are suspended; sometimes
2508 * they will even be wakeup-enabled.
2509 */
2510 }
2511
2512 musb_save_context(musb);
2513
2514 spin_unlock_irqrestore(&musb->lock, flags);
2515 return 0;
2516}
2517
2518static int musb_resume(struct device *dev)
2519{
2520 struct musb *musb = dev_to_musb(dev);
2521 u8 devctl;
2522 u8 mask;
2523
2524 /*
2525 * For static cmos like DaVinci, register values were preserved
2526 * unless for some reason the whole soc powered down or the USB
2527 * module got reset through the PSC (vs just being disabled).
2528 *
2529 * For the DSPS glue layer though, a full register restore has to
2530 * be done. As it shouldn't harm other platforms, we do it
2531 * unconditionally.
2532 */
2533
2534 musb_restore_context(musb);
2535
2536 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2537 mask = MUSB_DEVCTL_BDEVICE | MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV;
2538 if ((devctl & mask) != (musb->context.devctl & mask))
2539 musb->port1_status = 0;
2540 if (musb->need_finish_resume) {
2541 musb->need_finish_resume = 0;
2542 schedule_delayed_work(&musb->finish_resume_work,
2543 msecs_to_jiffies(USB_RESUME_TIMEOUT));
2544 }
2545
2546 /*
2547 * The USB HUB code expects the device to be in RPM_ACTIVE once it came
2548 * out of suspend
2549 */
2550 pm_runtime_disable(dev);
2551 pm_runtime_set_active(dev);
2552 pm_runtime_enable(dev);
2553
2554 musb_start(musb);
2555
2556 return 0;
2557}
2558
2559static int musb_runtime_suspend(struct device *dev)
2560{
2561 struct musb *musb = dev_to_musb(dev);
2562
2563 musb_save_context(musb);
2564
2565 return 0;
2566}
2567
2568static int musb_runtime_resume(struct device *dev)
2569{
2570 struct musb *musb = dev_to_musb(dev);
2571 static int first = 1;
2572
2573 /*
2574 * When pm_runtime_get_sync called for the first time in driver
2575 * init, some of the structure is still not initialized which is
2576 * used in restore function. But clock needs to be
2577 * enabled before any register access, so
2578 * pm_runtime_get_sync has to be called.
2579 * Also context restore without save does not make
2580 * any sense
2581 */
2582 if (!first)
2583 musb_restore_context(musb);
2584 first = 0;
2585
2586 if (musb->need_finish_resume) {
2587 musb->need_finish_resume = 0;
2588 schedule_delayed_work(&musb->finish_resume_work,
2589 msecs_to_jiffies(USB_RESUME_TIMEOUT));
2590 }
2591
2592 return 0;
2593}
2594
2595static const struct dev_pm_ops musb_dev_pm_ops = {
2596 .suspend = musb_suspend,
2597 .resume = musb_resume,
2598 .runtime_suspend = musb_runtime_suspend,
2599 .runtime_resume = musb_runtime_resume,
2600};
2601
2602#define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2603#else
2604#define MUSB_DEV_PM_OPS NULL
2605#endif
2606
2607static struct platform_driver musb_driver = {
2608 .driver = {
2609 .name = (char *)musb_driver_name,
2610 .bus = &platform_bus_type,
2611 .pm = MUSB_DEV_PM_OPS,
2612 },
2613 .probe = musb_probe,
2614 .remove = musb_remove,
2615 .shutdown = musb_shutdown,
2616};
2617
2618module_platform_driver(musb_driver);
1/*
2 * MUSB OTG driver core code
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35/*
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
37 *
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
42 *
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
47 *
48 *
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
53 *
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
56 *
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
61 *
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
66 * each direction.
67 *
68 * RESULT: one device may be perceived as blocking another one.
69 *
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
74 *
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
80 */
81
82/*
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific information
87 * (plus recentrly, SOC or family details)
88 *
89 * Most of the conditional compilation will (someday) vanish.
90 */
91
92#include <linux/module.h>
93#include <linux/kernel.h>
94#include <linux/sched.h>
95#include <linux/slab.h>
96#include <linux/list.h>
97#include <linux/kobject.h>
98#include <linux/prefetch.h>
99#include <linux/platform_device.h>
100#include <linux/io.h>
101#include <linux/dma-mapping.h>
102#include <linux/usb.h>
103#include <linux/usb/of.h>
104
105#include "musb_core.h"
106#include "musb_trace.h"
107
108#define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
109
110
111#define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
112#define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
113
114#define MUSB_VERSION "6.0"
115
116#define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
117
118#define MUSB_DRIVER_NAME "musb-hdrc"
119const char musb_driver_name[] = MUSB_DRIVER_NAME;
120
121MODULE_DESCRIPTION(DRIVER_INFO);
122MODULE_AUTHOR(DRIVER_AUTHOR);
123MODULE_LICENSE("GPL");
124MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
125
126
127/*-------------------------------------------------------------------------*/
128
129static inline struct musb *dev_to_musb(struct device *dev)
130{
131 return dev_get_drvdata(dev);
132}
133
134enum musb_mode musb_get_mode(struct device *dev)
135{
136 enum usb_dr_mode mode;
137
138 mode = usb_get_dr_mode(dev);
139 switch (mode) {
140 case USB_DR_MODE_HOST:
141 return MUSB_HOST;
142 case USB_DR_MODE_PERIPHERAL:
143 return MUSB_PERIPHERAL;
144 case USB_DR_MODE_OTG:
145 case USB_DR_MODE_UNKNOWN:
146 default:
147 return MUSB_OTG;
148 }
149}
150EXPORT_SYMBOL_GPL(musb_get_mode);
151
152/*-------------------------------------------------------------------------*/
153
154#ifndef CONFIG_BLACKFIN
155static int musb_ulpi_read(struct usb_phy *phy, u32 reg)
156{
157 void __iomem *addr = phy->io_priv;
158 int i = 0;
159 u8 r;
160 u8 power;
161 int ret;
162
163 pm_runtime_get_sync(phy->io_dev);
164
165 /* Make sure the transceiver is not in low power mode */
166 power = musb_readb(addr, MUSB_POWER);
167 power &= ~MUSB_POWER_SUSPENDM;
168 musb_writeb(addr, MUSB_POWER, power);
169
170 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
171 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
172 */
173
174 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg);
175 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
176 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
177
178 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
179 & MUSB_ULPI_REG_CMPLT)) {
180 i++;
181 if (i == 10000) {
182 ret = -ETIMEDOUT;
183 goto out;
184 }
185
186 }
187 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
188 r &= ~MUSB_ULPI_REG_CMPLT;
189 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
190
191 ret = musb_readb(addr, MUSB_ULPI_REG_DATA);
192
193out:
194 pm_runtime_put(phy->io_dev);
195
196 return ret;
197}
198
199static int musb_ulpi_write(struct usb_phy *phy, u32 val, u32 reg)
200{
201 void __iomem *addr = phy->io_priv;
202 int i = 0;
203 u8 r = 0;
204 u8 power;
205 int ret = 0;
206
207 pm_runtime_get_sync(phy->io_dev);
208
209 /* Make sure the transceiver is not in low power mode */
210 power = musb_readb(addr, MUSB_POWER);
211 power &= ~MUSB_POWER_SUSPENDM;
212 musb_writeb(addr, MUSB_POWER, power);
213
214 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg);
215 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)val);
216 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
217
218 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
219 & MUSB_ULPI_REG_CMPLT)) {
220 i++;
221 if (i == 10000) {
222 ret = -ETIMEDOUT;
223 goto out;
224 }
225 }
226
227 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
228 r &= ~MUSB_ULPI_REG_CMPLT;
229 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
230
231out:
232 pm_runtime_put(phy->io_dev);
233
234 return ret;
235}
236#else
237#define musb_ulpi_read NULL
238#define musb_ulpi_write NULL
239#endif
240
241static struct usb_phy_io_ops musb_ulpi_access = {
242 .read = musb_ulpi_read,
243 .write = musb_ulpi_write,
244};
245
246/*-------------------------------------------------------------------------*/
247
248static u32 musb_default_fifo_offset(u8 epnum)
249{
250 return 0x20 + (epnum * 4);
251}
252
253/* "flat" mapping: each endpoint has its own i/o address */
254static void musb_flat_ep_select(void __iomem *mbase, u8 epnum)
255{
256}
257
258static u32 musb_flat_ep_offset(u8 epnum, u16 offset)
259{
260 return 0x100 + (0x10 * epnum) + offset;
261}
262
263/* "indexed" mapping: INDEX register controls register bank select */
264static void musb_indexed_ep_select(void __iomem *mbase, u8 epnum)
265{
266 musb_writeb(mbase, MUSB_INDEX, epnum);
267}
268
269static u32 musb_indexed_ep_offset(u8 epnum, u16 offset)
270{
271 return 0x10 + offset;
272}
273
274static u32 musb_default_busctl_offset(u8 epnum, u16 offset)
275{
276 return 0x80 + (0x08 * epnum) + offset;
277}
278
279static u8 musb_default_readb(const void __iomem *addr, unsigned offset)
280{
281 u8 data = __raw_readb(addr + offset);
282
283 trace_musb_readb(__builtin_return_address(0), addr, offset, data);
284 return data;
285}
286
287static void musb_default_writeb(void __iomem *addr, unsigned offset, u8 data)
288{
289 trace_musb_writeb(__builtin_return_address(0), addr, offset, data);
290 __raw_writeb(data, addr + offset);
291}
292
293static u16 musb_default_readw(const void __iomem *addr, unsigned offset)
294{
295 u16 data = __raw_readw(addr + offset);
296
297 trace_musb_readw(__builtin_return_address(0), addr, offset, data);
298 return data;
299}
300
301static void musb_default_writew(void __iomem *addr, unsigned offset, u16 data)
302{
303 trace_musb_writew(__builtin_return_address(0), addr, offset, data);
304 __raw_writew(data, addr + offset);
305}
306
307static u32 musb_default_readl(const void __iomem *addr, unsigned offset)
308{
309 u32 data = __raw_readl(addr + offset);
310
311 trace_musb_readl(__builtin_return_address(0), addr, offset, data);
312 return data;
313}
314
315static void musb_default_writel(void __iomem *addr, unsigned offset, u32 data)
316{
317 trace_musb_writel(__builtin_return_address(0), addr, offset, data);
318 __raw_writel(data, addr + offset);
319}
320
321/*
322 * Load an endpoint's FIFO
323 */
324static void musb_default_write_fifo(struct musb_hw_ep *hw_ep, u16 len,
325 const u8 *src)
326{
327 struct musb *musb = hw_ep->musb;
328 void __iomem *fifo = hw_ep->fifo;
329
330 if (unlikely(len == 0))
331 return;
332
333 prefetch((u8 *)src);
334
335 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
336 'T', hw_ep->epnum, fifo, len, src);
337
338 /* we can't assume unaligned reads work */
339 if (likely((0x01 & (unsigned long) src) == 0)) {
340 u16 index = 0;
341
342 /* best case is 32bit-aligned source address */
343 if ((0x02 & (unsigned long) src) == 0) {
344 if (len >= 4) {
345 iowrite32_rep(fifo, src + index, len >> 2);
346 index += len & ~0x03;
347 }
348 if (len & 0x02) {
349 __raw_writew(*(u16 *)&src[index], fifo);
350 index += 2;
351 }
352 } else {
353 if (len >= 2) {
354 iowrite16_rep(fifo, src + index, len >> 1);
355 index += len & ~0x01;
356 }
357 }
358 if (len & 0x01)
359 __raw_writeb(src[index], fifo);
360 } else {
361 /* byte aligned */
362 iowrite8_rep(fifo, src, len);
363 }
364}
365
366/*
367 * Unload an endpoint's FIFO
368 */
369static void musb_default_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
370{
371 struct musb *musb = hw_ep->musb;
372 void __iomem *fifo = hw_ep->fifo;
373
374 if (unlikely(len == 0))
375 return;
376
377 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
378 'R', hw_ep->epnum, fifo, len, dst);
379
380 /* we can't assume unaligned writes work */
381 if (likely((0x01 & (unsigned long) dst) == 0)) {
382 u16 index = 0;
383
384 /* best case is 32bit-aligned destination address */
385 if ((0x02 & (unsigned long) dst) == 0) {
386 if (len >= 4) {
387 ioread32_rep(fifo, dst, len >> 2);
388 index = len & ~0x03;
389 }
390 if (len & 0x02) {
391 *(u16 *)&dst[index] = __raw_readw(fifo);
392 index += 2;
393 }
394 } else {
395 if (len >= 2) {
396 ioread16_rep(fifo, dst, len >> 1);
397 index = len & ~0x01;
398 }
399 }
400 if (len & 0x01)
401 dst[index] = __raw_readb(fifo);
402 } else {
403 /* byte aligned */
404 ioread8_rep(fifo, dst, len);
405 }
406}
407
408/*
409 * Old style IO functions
410 */
411u8 (*musb_readb)(const void __iomem *addr, unsigned offset);
412EXPORT_SYMBOL_GPL(musb_readb);
413
414void (*musb_writeb)(void __iomem *addr, unsigned offset, u8 data);
415EXPORT_SYMBOL_GPL(musb_writeb);
416
417u16 (*musb_readw)(const void __iomem *addr, unsigned offset);
418EXPORT_SYMBOL_GPL(musb_readw);
419
420void (*musb_writew)(void __iomem *addr, unsigned offset, u16 data);
421EXPORT_SYMBOL_GPL(musb_writew);
422
423u32 (*musb_readl)(const void __iomem *addr, unsigned offset);
424EXPORT_SYMBOL_GPL(musb_readl);
425
426void (*musb_writel)(void __iomem *addr, unsigned offset, u32 data);
427EXPORT_SYMBOL_GPL(musb_writel);
428
429#ifndef CONFIG_MUSB_PIO_ONLY
430struct dma_controller *
431(*musb_dma_controller_create)(struct musb *musb, void __iomem *base);
432EXPORT_SYMBOL(musb_dma_controller_create);
433
434void (*musb_dma_controller_destroy)(struct dma_controller *c);
435EXPORT_SYMBOL(musb_dma_controller_destroy);
436#endif
437
438/*
439 * New style IO functions
440 */
441void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
442{
443 return hw_ep->musb->io.read_fifo(hw_ep, len, dst);
444}
445
446void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
447{
448 return hw_ep->musb->io.write_fifo(hw_ep, len, src);
449}
450
451/*-------------------------------------------------------------------------*/
452
453/* for high speed test mode; see USB 2.0 spec 7.1.20 */
454static const u8 musb_test_packet[53] = {
455 /* implicit SYNC then DATA0 to start */
456
457 /* JKJKJKJK x9 */
458 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
459 /* JJKKJJKK x8 */
460 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
461 /* JJJJKKKK x8 */
462 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
463 /* JJJJJJJKKKKKKK x8 */
464 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
465 /* JJJJJJJK x8 */
466 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
467 /* JKKKKKKK x10, JK */
468 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
469
470 /* implicit CRC16 then EOP to end */
471};
472
473void musb_load_testpacket(struct musb *musb)
474{
475 void __iomem *regs = musb->endpoints[0].regs;
476
477 musb_ep_select(musb->mregs, 0);
478 musb_write_fifo(musb->control_ep,
479 sizeof(musb_test_packet), musb_test_packet);
480 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
481}
482
483/*-------------------------------------------------------------------------*/
484
485/*
486 * Handles OTG hnp timeouts, such as b_ase0_brst
487 */
488static void musb_otg_timer_func(unsigned long data)
489{
490 struct musb *musb = (struct musb *)data;
491 unsigned long flags;
492
493 spin_lock_irqsave(&musb->lock, flags);
494 switch (musb->xceiv->otg->state) {
495 case OTG_STATE_B_WAIT_ACON:
496 musb_dbg(musb,
497 "HNP: b_wait_acon timeout; back to b_peripheral");
498 musb_g_disconnect(musb);
499 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
500 musb->is_active = 0;
501 break;
502 case OTG_STATE_A_SUSPEND:
503 case OTG_STATE_A_WAIT_BCON:
504 musb_dbg(musb, "HNP: %s timeout",
505 usb_otg_state_string(musb->xceiv->otg->state));
506 musb_platform_set_vbus(musb, 0);
507 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
508 break;
509 default:
510 musb_dbg(musb, "HNP: Unhandled mode %s",
511 usb_otg_state_string(musb->xceiv->otg->state));
512 }
513 spin_unlock_irqrestore(&musb->lock, flags);
514}
515
516/*
517 * Stops the HNP transition. Caller must take care of locking.
518 */
519void musb_hnp_stop(struct musb *musb)
520{
521 struct usb_hcd *hcd = musb->hcd;
522 void __iomem *mbase = musb->mregs;
523 u8 reg;
524
525 musb_dbg(musb, "HNP: stop from %s",
526 usb_otg_state_string(musb->xceiv->otg->state));
527
528 switch (musb->xceiv->otg->state) {
529 case OTG_STATE_A_PERIPHERAL:
530 musb_g_disconnect(musb);
531 musb_dbg(musb, "HNP: back to %s",
532 usb_otg_state_string(musb->xceiv->otg->state));
533 break;
534 case OTG_STATE_B_HOST:
535 musb_dbg(musb, "HNP: Disabling HR");
536 if (hcd)
537 hcd->self.is_b_host = 0;
538 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
539 MUSB_DEV_MODE(musb);
540 reg = musb_readb(mbase, MUSB_POWER);
541 reg |= MUSB_POWER_SUSPENDM;
542 musb_writeb(mbase, MUSB_POWER, reg);
543 /* REVISIT: Start SESSION_REQUEST here? */
544 break;
545 default:
546 musb_dbg(musb, "HNP: Stopping in unknown state %s",
547 usb_otg_state_string(musb->xceiv->otg->state));
548 }
549
550 /*
551 * When returning to A state after HNP, avoid hub_port_rebounce(),
552 * which cause occasional OPT A "Did not receive reset after connect"
553 * errors.
554 */
555 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
556}
557
558static void musb_recover_from_babble(struct musb *musb);
559
560/*
561 * Interrupt Service Routine to record USB "global" interrupts.
562 * Since these do not happen often and signify things of
563 * paramount importance, it seems OK to check them individually;
564 * the order of the tests is specified in the manual
565 *
566 * @param musb instance pointer
567 * @param int_usb register contents
568 * @param devctl
569 * @param power
570 */
571
572static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
573 u8 devctl)
574{
575 irqreturn_t handled = IRQ_NONE;
576
577 musb_dbg(musb, "<== DevCtl=%02x, int_usb=0x%x", devctl, int_usb);
578
579 /* in host mode, the peripheral may issue remote wakeup.
580 * in peripheral mode, the host may resume the link.
581 * spurious RESUME irqs happen too, paired with SUSPEND.
582 */
583 if (int_usb & MUSB_INTR_RESUME) {
584 handled = IRQ_HANDLED;
585 musb_dbg(musb, "RESUME (%s)",
586 usb_otg_state_string(musb->xceiv->otg->state));
587
588 if (devctl & MUSB_DEVCTL_HM) {
589 switch (musb->xceiv->otg->state) {
590 case OTG_STATE_A_SUSPEND:
591 /* remote wakeup? */
592 musb->port1_status |=
593 (USB_PORT_STAT_C_SUSPEND << 16)
594 | MUSB_PORT_STAT_RESUME;
595 musb->rh_timer = jiffies
596 + msecs_to_jiffies(USB_RESUME_TIMEOUT);
597 musb->xceiv->otg->state = OTG_STATE_A_HOST;
598 musb->is_active = 1;
599 musb_host_resume_root_hub(musb);
600 schedule_delayed_work(&musb->finish_resume_work,
601 msecs_to_jiffies(USB_RESUME_TIMEOUT));
602 break;
603 case OTG_STATE_B_WAIT_ACON:
604 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
605 musb->is_active = 1;
606 MUSB_DEV_MODE(musb);
607 break;
608 default:
609 WARNING("bogus %s RESUME (%s)\n",
610 "host",
611 usb_otg_state_string(musb->xceiv->otg->state));
612 }
613 } else {
614 switch (musb->xceiv->otg->state) {
615 case OTG_STATE_A_SUSPEND:
616 /* possibly DISCONNECT is upcoming */
617 musb->xceiv->otg->state = OTG_STATE_A_HOST;
618 musb_host_resume_root_hub(musb);
619 break;
620 case OTG_STATE_B_WAIT_ACON:
621 case OTG_STATE_B_PERIPHERAL:
622 /* disconnect while suspended? we may
623 * not get a disconnect irq...
624 */
625 if ((devctl & MUSB_DEVCTL_VBUS)
626 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
627 ) {
628 musb->int_usb |= MUSB_INTR_DISCONNECT;
629 musb->int_usb &= ~MUSB_INTR_SUSPEND;
630 break;
631 }
632 musb_g_resume(musb);
633 break;
634 case OTG_STATE_B_IDLE:
635 musb->int_usb &= ~MUSB_INTR_SUSPEND;
636 break;
637 default:
638 WARNING("bogus %s RESUME (%s)\n",
639 "peripheral",
640 usb_otg_state_string(musb->xceiv->otg->state));
641 }
642 }
643 }
644
645 /* see manual for the order of the tests */
646 if (int_usb & MUSB_INTR_SESSREQ) {
647 void __iomem *mbase = musb->mregs;
648
649 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
650 && (devctl & MUSB_DEVCTL_BDEVICE)) {
651 musb_dbg(musb, "SessReq while on B state");
652 return IRQ_HANDLED;
653 }
654
655 musb_dbg(musb, "SESSION_REQUEST (%s)",
656 usb_otg_state_string(musb->xceiv->otg->state));
657
658 /* IRQ arrives from ID pin sense or (later, if VBUS power
659 * is removed) SRP. responses are time critical:
660 * - turn on VBUS (with silicon-specific mechanism)
661 * - go through A_WAIT_VRISE
662 * - ... to A_WAIT_BCON.
663 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
664 */
665 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
666 musb->ep0_stage = MUSB_EP0_START;
667 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
668 MUSB_HST_MODE(musb);
669 musb_platform_set_vbus(musb, 1);
670
671 handled = IRQ_HANDLED;
672 }
673
674 if (int_usb & MUSB_INTR_VBUSERROR) {
675 int ignore = 0;
676
677 /* During connection as an A-Device, we may see a short
678 * current spikes causing voltage drop, because of cable
679 * and peripheral capacitance combined with vbus draw.
680 * (So: less common with truly self-powered devices, where
681 * vbus doesn't act like a power supply.)
682 *
683 * Such spikes are short; usually less than ~500 usec, max
684 * of ~2 msec. That is, they're not sustained overcurrent
685 * errors, though they're reported using VBUSERROR irqs.
686 *
687 * Workarounds: (a) hardware: use self powered devices.
688 * (b) software: ignore non-repeated VBUS errors.
689 *
690 * REVISIT: do delays from lots of DEBUG_KERNEL checks
691 * make trouble here, keeping VBUS < 4.4V ?
692 */
693 switch (musb->xceiv->otg->state) {
694 case OTG_STATE_A_HOST:
695 /* recovery is dicey once we've gotten past the
696 * initial stages of enumeration, but if VBUS
697 * stayed ok at the other end of the link, and
698 * another reset is due (at least for high speed,
699 * to redo the chirp etc), it might work OK...
700 */
701 case OTG_STATE_A_WAIT_BCON:
702 case OTG_STATE_A_WAIT_VRISE:
703 if (musb->vbuserr_retry) {
704 void __iomem *mbase = musb->mregs;
705
706 musb->vbuserr_retry--;
707 ignore = 1;
708 devctl |= MUSB_DEVCTL_SESSION;
709 musb_writeb(mbase, MUSB_DEVCTL, devctl);
710 } else {
711 musb->port1_status |=
712 USB_PORT_STAT_OVERCURRENT
713 | (USB_PORT_STAT_C_OVERCURRENT << 16);
714 }
715 break;
716 default:
717 break;
718 }
719
720 dev_printk(ignore ? KERN_DEBUG : KERN_ERR, musb->controller,
721 "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
722 usb_otg_state_string(musb->xceiv->otg->state),
723 devctl,
724 ({ char *s;
725 switch (devctl & MUSB_DEVCTL_VBUS) {
726 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
727 s = "<SessEnd"; break;
728 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
729 s = "<AValid"; break;
730 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
731 s = "<VBusValid"; break;
732 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
733 default:
734 s = "VALID"; break;
735 } s; }),
736 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
737 musb->port1_status);
738
739 /* go through A_WAIT_VFALL then start a new session */
740 if (!ignore)
741 musb_platform_set_vbus(musb, 0);
742 handled = IRQ_HANDLED;
743 }
744
745 if (int_usb & MUSB_INTR_SUSPEND) {
746 musb_dbg(musb, "SUSPEND (%s) devctl %02x",
747 usb_otg_state_string(musb->xceiv->otg->state), devctl);
748 handled = IRQ_HANDLED;
749
750 switch (musb->xceiv->otg->state) {
751 case OTG_STATE_A_PERIPHERAL:
752 /* We also come here if the cable is removed, since
753 * this silicon doesn't report ID-no-longer-grounded.
754 *
755 * We depend on T(a_wait_bcon) to shut us down, and
756 * hope users don't do anything dicey during this
757 * undesired detour through A_WAIT_BCON.
758 */
759 musb_hnp_stop(musb);
760 musb_host_resume_root_hub(musb);
761 musb_root_disconnect(musb);
762 musb_platform_try_idle(musb, jiffies
763 + msecs_to_jiffies(musb->a_wait_bcon
764 ? : OTG_TIME_A_WAIT_BCON));
765
766 break;
767 case OTG_STATE_B_IDLE:
768 if (!musb->is_active)
769 break;
770 case OTG_STATE_B_PERIPHERAL:
771 musb_g_suspend(musb);
772 musb->is_active = musb->g.b_hnp_enable;
773 if (musb->is_active) {
774 musb->xceiv->otg->state = OTG_STATE_B_WAIT_ACON;
775 musb_dbg(musb, "HNP: Setting timer for b_ase0_brst");
776 mod_timer(&musb->otg_timer, jiffies
777 + msecs_to_jiffies(
778 OTG_TIME_B_ASE0_BRST));
779 }
780 break;
781 case OTG_STATE_A_WAIT_BCON:
782 if (musb->a_wait_bcon != 0)
783 musb_platform_try_idle(musb, jiffies
784 + msecs_to_jiffies(musb->a_wait_bcon));
785 break;
786 case OTG_STATE_A_HOST:
787 musb->xceiv->otg->state = OTG_STATE_A_SUSPEND;
788 musb->is_active = musb->hcd->self.b_hnp_enable;
789 break;
790 case OTG_STATE_B_HOST:
791 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
792 musb_dbg(musb, "REVISIT: SUSPEND as B_HOST");
793 break;
794 default:
795 /* "should not happen" */
796 musb->is_active = 0;
797 break;
798 }
799 }
800
801 if (int_usb & MUSB_INTR_CONNECT) {
802 struct usb_hcd *hcd = musb->hcd;
803
804 handled = IRQ_HANDLED;
805 musb->is_active = 1;
806
807 musb->ep0_stage = MUSB_EP0_START;
808
809 musb->intrtxe = musb->epmask;
810 musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe);
811 musb->intrrxe = musb->epmask & 0xfffe;
812 musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe);
813 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
814 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
815 |USB_PORT_STAT_HIGH_SPEED
816 |USB_PORT_STAT_ENABLE
817 );
818 musb->port1_status |= USB_PORT_STAT_CONNECTION
819 |(USB_PORT_STAT_C_CONNECTION << 16);
820
821 /* high vs full speed is just a guess until after reset */
822 if (devctl & MUSB_DEVCTL_LSDEV)
823 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
824
825 /* indicate new connection to OTG machine */
826 switch (musb->xceiv->otg->state) {
827 case OTG_STATE_B_PERIPHERAL:
828 if (int_usb & MUSB_INTR_SUSPEND) {
829 musb_dbg(musb, "HNP: SUSPEND+CONNECT, now b_host");
830 int_usb &= ~MUSB_INTR_SUSPEND;
831 goto b_host;
832 } else
833 musb_dbg(musb, "CONNECT as b_peripheral???");
834 break;
835 case OTG_STATE_B_WAIT_ACON:
836 musb_dbg(musb, "HNP: CONNECT, now b_host");
837b_host:
838 musb->xceiv->otg->state = OTG_STATE_B_HOST;
839 if (musb->hcd)
840 musb->hcd->self.is_b_host = 1;
841 del_timer(&musb->otg_timer);
842 break;
843 default:
844 if ((devctl & MUSB_DEVCTL_VBUS)
845 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
846 musb->xceiv->otg->state = OTG_STATE_A_HOST;
847 if (hcd)
848 hcd->self.is_b_host = 0;
849 }
850 break;
851 }
852
853 musb_host_poke_root_hub(musb);
854
855 musb_dbg(musb, "CONNECT (%s) devctl %02x",
856 usb_otg_state_string(musb->xceiv->otg->state), devctl);
857 }
858
859 if (int_usb & MUSB_INTR_DISCONNECT) {
860 musb_dbg(musb, "DISCONNECT (%s) as %s, devctl %02x",
861 usb_otg_state_string(musb->xceiv->otg->state),
862 MUSB_MODE(musb), devctl);
863 handled = IRQ_HANDLED;
864
865 switch (musb->xceiv->otg->state) {
866 case OTG_STATE_A_HOST:
867 case OTG_STATE_A_SUSPEND:
868 musb_host_resume_root_hub(musb);
869 musb_root_disconnect(musb);
870 if (musb->a_wait_bcon != 0)
871 musb_platform_try_idle(musb, jiffies
872 + msecs_to_jiffies(musb->a_wait_bcon));
873 break;
874 case OTG_STATE_B_HOST:
875 /* REVISIT this behaves for "real disconnect"
876 * cases; make sure the other transitions from
877 * from B_HOST act right too. The B_HOST code
878 * in hnp_stop() is currently not used...
879 */
880 musb_root_disconnect(musb);
881 if (musb->hcd)
882 musb->hcd->self.is_b_host = 0;
883 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
884 MUSB_DEV_MODE(musb);
885 musb_g_disconnect(musb);
886 break;
887 case OTG_STATE_A_PERIPHERAL:
888 musb_hnp_stop(musb);
889 musb_root_disconnect(musb);
890 /* FALLTHROUGH */
891 case OTG_STATE_B_WAIT_ACON:
892 /* FALLTHROUGH */
893 case OTG_STATE_B_PERIPHERAL:
894 case OTG_STATE_B_IDLE:
895 musb_g_disconnect(musb);
896 break;
897 default:
898 WARNING("unhandled DISCONNECT transition (%s)\n",
899 usb_otg_state_string(musb->xceiv->otg->state));
900 break;
901 }
902 }
903
904 /* mentor saves a bit: bus reset and babble share the same irq.
905 * only host sees babble; only peripheral sees bus reset.
906 */
907 if (int_usb & MUSB_INTR_RESET) {
908 handled = IRQ_HANDLED;
909 if (devctl & MUSB_DEVCTL_HM) {
910 /*
911 * When BABBLE happens what we can depends on which
912 * platform MUSB is running, because some platforms
913 * implemented proprietary means for 'recovering' from
914 * Babble conditions. One such platform is AM335x. In
915 * most cases, however, the only thing we can do is
916 * drop the session.
917 */
918 dev_err(musb->controller, "Babble\n");
919
920 if (is_host_active(musb))
921 musb_recover_from_babble(musb);
922 } else {
923 musb_dbg(musb, "BUS RESET as %s",
924 usb_otg_state_string(musb->xceiv->otg->state));
925 switch (musb->xceiv->otg->state) {
926 case OTG_STATE_A_SUSPEND:
927 musb_g_reset(musb);
928 /* FALLTHROUGH */
929 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
930 /* never use invalid T(a_wait_bcon) */
931 musb_dbg(musb, "HNP: in %s, %d msec timeout",
932 usb_otg_state_string(musb->xceiv->otg->state),
933 TA_WAIT_BCON(musb));
934 mod_timer(&musb->otg_timer, jiffies
935 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
936 break;
937 case OTG_STATE_A_PERIPHERAL:
938 del_timer(&musb->otg_timer);
939 musb_g_reset(musb);
940 break;
941 case OTG_STATE_B_WAIT_ACON:
942 musb_dbg(musb, "HNP: RESET (%s), to b_peripheral",
943 usb_otg_state_string(musb->xceiv->otg->state));
944 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
945 musb_g_reset(musb);
946 break;
947 case OTG_STATE_B_IDLE:
948 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
949 /* FALLTHROUGH */
950 case OTG_STATE_B_PERIPHERAL:
951 musb_g_reset(musb);
952 break;
953 default:
954 musb_dbg(musb, "Unhandled BUS RESET as %s",
955 usb_otg_state_string(musb->xceiv->otg->state));
956 }
957 }
958 }
959
960#if 0
961/* REVISIT ... this would be for multiplexing periodic endpoints, or
962 * supporting transfer phasing to prevent exceeding ISO bandwidth
963 * limits of a given frame or microframe.
964 *
965 * It's not needed for peripheral side, which dedicates endpoints;
966 * though it _might_ use SOF irqs for other purposes.
967 *
968 * And it's not currently needed for host side, which also dedicates
969 * endpoints, relies on TX/RX interval registers, and isn't claimed
970 * to support ISO transfers yet.
971 */
972 if (int_usb & MUSB_INTR_SOF) {
973 void __iomem *mbase = musb->mregs;
974 struct musb_hw_ep *ep;
975 u8 epnum;
976 u16 frame;
977
978 dev_dbg(musb->controller, "START_OF_FRAME\n");
979 handled = IRQ_HANDLED;
980
981 /* start any periodic Tx transfers waiting for current frame */
982 frame = musb_readw(mbase, MUSB_FRAME);
983 ep = musb->endpoints;
984 for (epnum = 1; (epnum < musb->nr_endpoints)
985 && (musb->epmask >= (1 << epnum));
986 epnum++, ep++) {
987 /*
988 * FIXME handle framecounter wraps (12 bits)
989 * eliminate duplicated StartUrb logic
990 */
991 if (ep->dwWaitFrame >= frame) {
992 ep->dwWaitFrame = 0;
993 pr_debug("SOF --> periodic TX%s on %d\n",
994 ep->tx_channel ? " DMA" : "",
995 epnum);
996 if (!ep->tx_channel)
997 musb_h_tx_start(musb, epnum);
998 else
999 cppi_hostdma_start(musb, epnum);
1000 }
1001 } /* end of for loop */
1002 }
1003#endif
1004
1005 schedule_delayed_work(&musb->irq_work, 0);
1006
1007 return handled;
1008}
1009
1010/*-------------------------------------------------------------------------*/
1011
1012static void musb_disable_interrupts(struct musb *musb)
1013{
1014 void __iomem *mbase = musb->mregs;
1015 u16 temp;
1016
1017 /* disable interrupts */
1018 musb_writeb(mbase, MUSB_INTRUSBE, 0);
1019 musb->intrtxe = 0;
1020 musb_writew(mbase, MUSB_INTRTXE, 0);
1021 musb->intrrxe = 0;
1022 musb_writew(mbase, MUSB_INTRRXE, 0);
1023
1024 /* flush pending interrupts */
1025 temp = musb_readb(mbase, MUSB_INTRUSB);
1026 temp = musb_readw(mbase, MUSB_INTRTX);
1027 temp = musb_readw(mbase, MUSB_INTRRX);
1028}
1029
1030static void musb_enable_interrupts(struct musb *musb)
1031{
1032 void __iomem *regs = musb->mregs;
1033
1034 /* Set INT enable registers, enable interrupts */
1035 musb->intrtxe = musb->epmask;
1036 musb_writew(regs, MUSB_INTRTXE, musb->intrtxe);
1037 musb->intrrxe = musb->epmask & 0xfffe;
1038 musb_writew(regs, MUSB_INTRRXE, musb->intrrxe);
1039 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
1040
1041}
1042
1043static void musb_generic_disable(struct musb *musb)
1044{
1045 void __iomem *mbase = musb->mregs;
1046
1047 musb_disable_interrupts(musb);
1048
1049 /* off */
1050 musb_writeb(mbase, MUSB_DEVCTL, 0);
1051}
1052
1053/*
1054 * Program the HDRC to start (enable interrupts, dma, etc.).
1055 */
1056void musb_start(struct musb *musb)
1057{
1058 void __iomem *regs = musb->mregs;
1059 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
1060 u8 power;
1061
1062 musb_dbg(musb, "<== devctl %02x", devctl);
1063
1064 musb_enable_interrupts(musb);
1065 musb_writeb(regs, MUSB_TESTMODE, 0);
1066
1067 power = MUSB_POWER_ISOUPDATE;
1068 /*
1069 * treating UNKNOWN as unspecified maximum speed, in which case
1070 * we will default to high-speed.
1071 */
1072 if (musb->config->maximum_speed == USB_SPEED_HIGH ||
1073 musb->config->maximum_speed == USB_SPEED_UNKNOWN)
1074 power |= MUSB_POWER_HSENAB;
1075 musb_writeb(regs, MUSB_POWER, power);
1076
1077 musb->is_active = 0;
1078 devctl = musb_readb(regs, MUSB_DEVCTL);
1079 devctl &= ~MUSB_DEVCTL_SESSION;
1080
1081 /* session started after:
1082 * (a) ID-grounded irq, host mode;
1083 * (b) vbus present/connect IRQ, peripheral mode;
1084 * (c) peripheral initiates, using SRP
1085 */
1086 if (musb->port_mode != MUSB_PORT_MODE_HOST &&
1087 musb->xceiv->otg->state != OTG_STATE_A_WAIT_BCON &&
1088 (devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) {
1089 musb->is_active = 1;
1090 } else {
1091 devctl |= MUSB_DEVCTL_SESSION;
1092 }
1093
1094 musb_platform_enable(musb);
1095 musb_writeb(regs, MUSB_DEVCTL, devctl);
1096}
1097
1098/*
1099 * Make the HDRC stop (disable interrupts, etc.);
1100 * reversible by musb_start
1101 * called on gadget driver unregister
1102 * with controller locked, irqs blocked
1103 * acts as a NOP unless some role activated the hardware
1104 */
1105void musb_stop(struct musb *musb)
1106{
1107 /* stop IRQs, timers, ... */
1108 musb_platform_disable(musb);
1109 musb_generic_disable(musb);
1110 musb_dbg(musb, "HDRC disabled");
1111
1112 /* FIXME
1113 * - mark host and/or peripheral drivers unusable/inactive
1114 * - disable DMA (and enable it in HdrcStart)
1115 * - make sure we can musb_start() after musb_stop(); with
1116 * OTG mode, gadget driver module rmmod/modprobe cycles that
1117 * - ...
1118 */
1119 musb_platform_try_idle(musb, 0);
1120}
1121
1122/*-------------------------------------------------------------------------*/
1123
1124/*
1125 * The silicon either has hard-wired endpoint configurations, or else
1126 * "dynamic fifo" sizing. The driver has support for both, though at this
1127 * writing only the dynamic sizing is very well tested. Since we switched
1128 * away from compile-time hardware parameters, we can no longer rely on
1129 * dead code elimination to leave only the relevant one in the object file.
1130 *
1131 * We don't currently use dynamic fifo setup capability to do anything
1132 * more than selecting one of a bunch of predefined configurations.
1133 */
1134static ushort fifo_mode;
1135
1136/* "modprobe ... fifo_mode=1" etc */
1137module_param(fifo_mode, ushort, 0);
1138MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1139
1140/*
1141 * tables defining fifo_mode values. define more if you like.
1142 * for host side, make sure both halves of ep1 are set up.
1143 */
1144
1145/* mode 0 - fits in 2KB */
1146static struct musb_fifo_cfg mode_0_cfg[] = {
1147{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1148{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1149{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1150{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1151{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1152};
1153
1154/* mode 1 - fits in 4KB */
1155static struct musb_fifo_cfg mode_1_cfg[] = {
1156{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1157{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1158{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1159{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1160{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1161};
1162
1163/* mode 2 - fits in 4KB */
1164static struct musb_fifo_cfg mode_2_cfg[] = {
1165{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1166{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1167{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1168{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1169{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1170{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1171};
1172
1173/* mode 3 - fits in 4KB */
1174static struct musb_fifo_cfg mode_3_cfg[] = {
1175{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1176{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1177{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1178{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1179{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1180{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1181};
1182
1183/* mode 4 - fits in 16KB */
1184static struct musb_fifo_cfg mode_4_cfg[] = {
1185{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1186{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1187{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1188{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1189{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1190{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1191{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1192{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1193{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1194{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1195{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1196{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1197{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1198{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1199{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1200{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1201{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1202{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1203{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1204{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1205{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1206{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1207{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1208{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1209{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1210{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1211{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1212};
1213
1214/* mode 5 - fits in 8KB */
1215static struct musb_fifo_cfg mode_5_cfg[] = {
1216{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1217{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1218{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1219{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1220{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1221{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1222{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1223{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1224{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1225{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1226{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1227{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1228{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1229{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1230{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1231{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1232{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1233{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1234{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1235{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1236{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1237{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1238{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1239{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1240{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1241{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1242{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1243};
1244
1245/*
1246 * configure a fifo; for non-shared endpoints, this may be called
1247 * once for a tx fifo and once for an rx fifo.
1248 *
1249 * returns negative errno or offset for next fifo.
1250 */
1251static int
1252fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1253 const struct musb_fifo_cfg *cfg, u16 offset)
1254{
1255 void __iomem *mbase = musb->mregs;
1256 int size = 0;
1257 u16 maxpacket = cfg->maxpacket;
1258 u16 c_off = offset >> 3;
1259 u8 c_size;
1260
1261 /* expect hw_ep has already been zero-initialized */
1262
1263 size = ffs(max(maxpacket, (u16) 8)) - 1;
1264 maxpacket = 1 << size;
1265
1266 c_size = size - 3;
1267 if (cfg->mode == BUF_DOUBLE) {
1268 if ((offset + (maxpacket << 1)) >
1269 (1 << (musb->config->ram_bits + 2)))
1270 return -EMSGSIZE;
1271 c_size |= MUSB_FIFOSZ_DPB;
1272 } else {
1273 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1274 return -EMSGSIZE;
1275 }
1276
1277 /* configure the FIFO */
1278 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1279
1280 /* EP0 reserved endpoint for control, bidirectional;
1281 * EP1 reserved for bulk, two unidirectional halves.
1282 */
1283 if (hw_ep->epnum == 1)
1284 musb->bulk_ep = hw_ep;
1285 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1286 switch (cfg->style) {
1287 case FIFO_TX:
1288 musb_write_txfifosz(mbase, c_size);
1289 musb_write_txfifoadd(mbase, c_off);
1290 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1291 hw_ep->max_packet_sz_tx = maxpacket;
1292 break;
1293 case FIFO_RX:
1294 musb_write_rxfifosz(mbase, c_size);
1295 musb_write_rxfifoadd(mbase, c_off);
1296 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1297 hw_ep->max_packet_sz_rx = maxpacket;
1298 break;
1299 case FIFO_RXTX:
1300 musb_write_txfifosz(mbase, c_size);
1301 musb_write_txfifoadd(mbase, c_off);
1302 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1303 hw_ep->max_packet_sz_rx = maxpacket;
1304
1305 musb_write_rxfifosz(mbase, c_size);
1306 musb_write_rxfifoadd(mbase, c_off);
1307 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1308 hw_ep->max_packet_sz_tx = maxpacket;
1309
1310 hw_ep->is_shared_fifo = true;
1311 break;
1312 }
1313
1314 /* NOTE rx and tx endpoint irqs aren't managed separately,
1315 * which happens to be ok
1316 */
1317 musb->epmask |= (1 << hw_ep->epnum);
1318
1319 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1320}
1321
1322static struct musb_fifo_cfg ep0_cfg = {
1323 .style = FIFO_RXTX, .maxpacket = 64,
1324};
1325
1326static int ep_config_from_table(struct musb *musb)
1327{
1328 const struct musb_fifo_cfg *cfg;
1329 unsigned i, n;
1330 int offset;
1331 struct musb_hw_ep *hw_ep = musb->endpoints;
1332
1333 if (musb->config->fifo_cfg) {
1334 cfg = musb->config->fifo_cfg;
1335 n = musb->config->fifo_cfg_size;
1336 goto done;
1337 }
1338
1339 switch (fifo_mode) {
1340 default:
1341 fifo_mode = 0;
1342 /* FALLTHROUGH */
1343 case 0:
1344 cfg = mode_0_cfg;
1345 n = ARRAY_SIZE(mode_0_cfg);
1346 break;
1347 case 1:
1348 cfg = mode_1_cfg;
1349 n = ARRAY_SIZE(mode_1_cfg);
1350 break;
1351 case 2:
1352 cfg = mode_2_cfg;
1353 n = ARRAY_SIZE(mode_2_cfg);
1354 break;
1355 case 3:
1356 cfg = mode_3_cfg;
1357 n = ARRAY_SIZE(mode_3_cfg);
1358 break;
1359 case 4:
1360 cfg = mode_4_cfg;
1361 n = ARRAY_SIZE(mode_4_cfg);
1362 break;
1363 case 5:
1364 cfg = mode_5_cfg;
1365 n = ARRAY_SIZE(mode_5_cfg);
1366 break;
1367 }
1368
1369 pr_debug("%s: setup fifo_mode %d\n", musb_driver_name, fifo_mode);
1370
1371
1372done:
1373 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1374 /* assert(offset > 0) */
1375
1376 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1377 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1378 */
1379
1380 for (i = 0; i < n; i++) {
1381 u8 epn = cfg->hw_ep_num;
1382
1383 if (epn >= musb->config->num_eps) {
1384 pr_debug("%s: invalid ep %d\n",
1385 musb_driver_name, epn);
1386 return -EINVAL;
1387 }
1388 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1389 if (offset < 0) {
1390 pr_debug("%s: mem overrun, ep %d\n",
1391 musb_driver_name, epn);
1392 return offset;
1393 }
1394 epn++;
1395 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1396 }
1397
1398 pr_debug("%s: %d/%d max ep, %d/%d memory\n",
1399 musb_driver_name,
1400 n + 1, musb->config->num_eps * 2 - 1,
1401 offset, (1 << (musb->config->ram_bits + 2)));
1402
1403 if (!musb->bulk_ep) {
1404 pr_debug("%s: missing bulk\n", musb_driver_name);
1405 return -EINVAL;
1406 }
1407
1408 return 0;
1409}
1410
1411
1412/*
1413 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1414 * @param musb the controller
1415 */
1416static int ep_config_from_hw(struct musb *musb)
1417{
1418 u8 epnum = 0;
1419 struct musb_hw_ep *hw_ep;
1420 void __iomem *mbase = musb->mregs;
1421 int ret = 0;
1422
1423 musb_dbg(musb, "<== static silicon ep config");
1424
1425 /* FIXME pick up ep0 maxpacket size */
1426
1427 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1428 musb_ep_select(mbase, epnum);
1429 hw_ep = musb->endpoints + epnum;
1430
1431 ret = musb_read_fifosize(musb, hw_ep, epnum);
1432 if (ret < 0)
1433 break;
1434
1435 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1436
1437 /* pick an RX/TX endpoint for bulk */
1438 if (hw_ep->max_packet_sz_tx < 512
1439 || hw_ep->max_packet_sz_rx < 512)
1440 continue;
1441
1442 /* REVISIT: this algorithm is lazy, we should at least
1443 * try to pick a double buffered endpoint.
1444 */
1445 if (musb->bulk_ep)
1446 continue;
1447 musb->bulk_ep = hw_ep;
1448 }
1449
1450 if (!musb->bulk_ep) {
1451 pr_debug("%s: missing bulk\n", musb_driver_name);
1452 return -EINVAL;
1453 }
1454
1455 return 0;
1456}
1457
1458enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1459
1460/* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1461 * configure endpoints, or take their config from silicon
1462 */
1463static int musb_core_init(u16 musb_type, struct musb *musb)
1464{
1465 u8 reg;
1466 char *type;
1467 char aInfo[90];
1468 void __iomem *mbase = musb->mregs;
1469 int status = 0;
1470 int i;
1471
1472 /* log core options (read using indexed model) */
1473 reg = musb_read_configdata(mbase);
1474
1475 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1476 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1477 strcat(aInfo, ", dyn FIFOs");
1478 musb->dyn_fifo = true;
1479 }
1480 if (reg & MUSB_CONFIGDATA_MPRXE) {
1481 strcat(aInfo, ", bulk combine");
1482 musb->bulk_combine = true;
1483 }
1484 if (reg & MUSB_CONFIGDATA_MPTXE) {
1485 strcat(aInfo, ", bulk split");
1486 musb->bulk_split = true;
1487 }
1488 if (reg & MUSB_CONFIGDATA_HBRXE) {
1489 strcat(aInfo, ", HB-ISO Rx");
1490 musb->hb_iso_rx = true;
1491 }
1492 if (reg & MUSB_CONFIGDATA_HBTXE) {
1493 strcat(aInfo, ", HB-ISO Tx");
1494 musb->hb_iso_tx = true;
1495 }
1496 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1497 strcat(aInfo, ", SoftConn");
1498
1499 pr_debug("%s: ConfigData=0x%02x (%s)\n", musb_driver_name, reg, aInfo);
1500
1501 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1502 musb->is_multipoint = 1;
1503 type = "M";
1504 } else {
1505 musb->is_multipoint = 0;
1506 type = "";
1507#ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1508 pr_err("%s: kernel must blacklist external hubs\n",
1509 musb_driver_name);
1510#endif
1511 }
1512
1513 /* log release info */
1514 musb->hwvers = musb_read_hwvers(mbase);
1515 pr_debug("%s: %sHDRC RTL version %d.%d%s\n",
1516 musb_driver_name, type, MUSB_HWVERS_MAJOR(musb->hwvers),
1517 MUSB_HWVERS_MINOR(musb->hwvers),
1518 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1519
1520 /* configure ep0 */
1521 musb_configure_ep0(musb);
1522
1523 /* discover endpoint configuration */
1524 musb->nr_endpoints = 1;
1525 musb->epmask = 1;
1526
1527 if (musb->dyn_fifo)
1528 status = ep_config_from_table(musb);
1529 else
1530 status = ep_config_from_hw(musb);
1531
1532 if (status < 0)
1533 return status;
1534
1535 /* finish init, and print endpoint config */
1536 for (i = 0; i < musb->nr_endpoints; i++) {
1537 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1538
1539 hw_ep->fifo = musb->io.fifo_offset(i) + mbase;
1540#if IS_ENABLED(CONFIG_USB_MUSB_TUSB6010)
1541 if (musb->io.quirks & MUSB_IN_TUSB) {
1542 hw_ep->fifo_async = musb->async + 0x400 +
1543 musb->io.fifo_offset(i);
1544 hw_ep->fifo_sync = musb->sync + 0x400 +
1545 musb->io.fifo_offset(i);
1546 hw_ep->fifo_sync_va =
1547 musb->sync_va + 0x400 + musb->io.fifo_offset(i);
1548
1549 if (i == 0)
1550 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1551 else
1552 hw_ep->conf = mbase + 0x400 +
1553 (((i - 1) & 0xf) << 2);
1554 }
1555#endif
1556
1557 hw_ep->regs = musb->io.ep_offset(i, 0) + mbase;
1558 hw_ep->rx_reinit = 1;
1559 hw_ep->tx_reinit = 1;
1560
1561 if (hw_ep->max_packet_sz_tx) {
1562 musb_dbg(musb, "%s: hw_ep %d%s, %smax %d",
1563 musb_driver_name, i,
1564 hw_ep->is_shared_fifo ? "shared" : "tx",
1565 hw_ep->tx_double_buffered
1566 ? "doublebuffer, " : "",
1567 hw_ep->max_packet_sz_tx);
1568 }
1569 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1570 musb_dbg(musb, "%s: hw_ep %d%s, %smax %d",
1571 musb_driver_name, i,
1572 "rx",
1573 hw_ep->rx_double_buffered
1574 ? "doublebuffer, " : "",
1575 hw_ep->max_packet_sz_rx);
1576 }
1577 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1578 musb_dbg(musb, "hw_ep %d not configured", i);
1579 }
1580
1581 return 0;
1582}
1583
1584/*-------------------------------------------------------------------------*/
1585
1586/*
1587 * handle all the irqs defined by the HDRC core. for now we expect: other
1588 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1589 * will be assigned, and the irq will already have been acked.
1590 *
1591 * called in irq context with spinlock held, irqs blocked
1592 */
1593irqreturn_t musb_interrupt(struct musb *musb)
1594{
1595 irqreturn_t retval = IRQ_NONE;
1596 unsigned long status;
1597 unsigned long epnum;
1598 u8 devctl;
1599
1600 if (!musb->int_usb && !musb->int_tx && !musb->int_rx)
1601 return IRQ_NONE;
1602
1603 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1604
1605 trace_musb_isr(musb);
1606
1607 /**
1608 * According to Mentor Graphics' documentation, flowchart on page 98,
1609 * IRQ should be handled as follows:
1610 *
1611 * . Resume IRQ
1612 * . Session Request IRQ
1613 * . VBUS Error IRQ
1614 * . Suspend IRQ
1615 * . Connect IRQ
1616 * . Disconnect IRQ
1617 * . Reset/Babble IRQ
1618 * . SOF IRQ (we're not using this one)
1619 * . Endpoint 0 IRQ
1620 * . TX Endpoints
1621 * . RX Endpoints
1622 *
1623 * We will be following that flowchart in order to avoid any problems
1624 * that might arise with internal Finite State Machine.
1625 */
1626
1627 if (musb->int_usb)
1628 retval |= musb_stage0_irq(musb, musb->int_usb, devctl);
1629
1630 if (musb->int_tx & 1) {
1631 if (is_host_active(musb))
1632 retval |= musb_h_ep0_irq(musb);
1633 else
1634 retval |= musb_g_ep0_irq(musb);
1635
1636 /* we have just handled endpoint 0 IRQ, clear it */
1637 musb->int_tx &= ~BIT(0);
1638 }
1639
1640 status = musb->int_tx;
1641
1642 for_each_set_bit(epnum, &status, 16) {
1643 retval = IRQ_HANDLED;
1644 if (is_host_active(musb))
1645 musb_host_tx(musb, epnum);
1646 else
1647 musb_g_tx(musb, epnum);
1648 }
1649
1650 status = musb->int_rx;
1651
1652 for_each_set_bit(epnum, &status, 16) {
1653 retval = IRQ_HANDLED;
1654 if (is_host_active(musb))
1655 musb_host_rx(musb, epnum);
1656 else
1657 musb_g_rx(musb, epnum);
1658 }
1659
1660 return retval;
1661}
1662EXPORT_SYMBOL_GPL(musb_interrupt);
1663
1664#ifndef CONFIG_MUSB_PIO_ONLY
1665static bool use_dma = 1;
1666
1667/* "modprobe ... use_dma=0" etc */
1668module_param(use_dma, bool, 0644);
1669MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1670
1671void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1672{
1673 /* called with controller lock already held */
1674
1675 if (!epnum) {
1676 if (!is_cppi_enabled(musb)) {
1677 /* endpoint 0 */
1678 if (is_host_active(musb))
1679 musb_h_ep0_irq(musb);
1680 else
1681 musb_g_ep0_irq(musb);
1682 }
1683 } else {
1684 /* endpoints 1..15 */
1685 if (transmit) {
1686 if (is_host_active(musb))
1687 musb_host_tx(musb, epnum);
1688 else
1689 musb_g_tx(musb, epnum);
1690 } else {
1691 /* receive */
1692 if (is_host_active(musb))
1693 musb_host_rx(musb, epnum);
1694 else
1695 musb_g_rx(musb, epnum);
1696 }
1697 }
1698}
1699EXPORT_SYMBOL_GPL(musb_dma_completion);
1700
1701#else
1702#define use_dma 0
1703#endif
1704
1705static int (*musb_phy_callback)(enum musb_vbus_id_status status);
1706
1707/*
1708 * musb_mailbox - optional phy notifier function
1709 * @status phy state change
1710 *
1711 * Optionally gets called from the USB PHY. Note that the USB PHY must be
1712 * disabled at the point the phy_callback is registered or unregistered.
1713 */
1714int musb_mailbox(enum musb_vbus_id_status status)
1715{
1716 if (musb_phy_callback)
1717 return musb_phy_callback(status);
1718
1719 return -ENODEV;
1720};
1721EXPORT_SYMBOL_GPL(musb_mailbox);
1722
1723/*-------------------------------------------------------------------------*/
1724
1725static ssize_t
1726musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1727{
1728 struct musb *musb = dev_to_musb(dev);
1729 unsigned long flags;
1730 int ret = -EINVAL;
1731
1732 spin_lock_irqsave(&musb->lock, flags);
1733 ret = sprintf(buf, "%s\n", usb_otg_state_string(musb->xceiv->otg->state));
1734 spin_unlock_irqrestore(&musb->lock, flags);
1735
1736 return ret;
1737}
1738
1739static ssize_t
1740musb_mode_store(struct device *dev, struct device_attribute *attr,
1741 const char *buf, size_t n)
1742{
1743 struct musb *musb = dev_to_musb(dev);
1744 unsigned long flags;
1745 int status;
1746
1747 spin_lock_irqsave(&musb->lock, flags);
1748 if (sysfs_streq(buf, "host"))
1749 status = musb_platform_set_mode(musb, MUSB_HOST);
1750 else if (sysfs_streq(buf, "peripheral"))
1751 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1752 else if (sysfs_streq(buf, "otg"))
1753 status = musb_platform_set_mode(musb, MUSB_OTG);
1754 else
1755 status = -EINVAL;
1756 spin_unlock_irqrestore(&musb->lock, flags);
1757
1758 return (status == 0) ? n : status;
1759}
1760static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1761
1762static ssize_t
1763musb_vbus_store(struct device *dev, struct device_attribute *attr,
1764 const char *buf, size_t n)
1765{
1766 struct musb *musb = dev_to_musb(dev);
1767 unsigned long flags;
1768 unsigned long val;
1769
1770 if (sscanf(buf, "%lu", &val) < 1) {
1771 dev_err(dev, "Invalid VBUS timeout ms value\n");
1772 return -EINVAL;
1773 }
1774
1775 spin_lock_irqsave(&musb->lock, flags);
1776 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1777 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1778 if (musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)
1779 musb->is_active = 0;
1780 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1781 spin_unlock_irqrestore(&musb->lock, flags);
1782
1783 return n;
1784}
1785
1786static ssize_t
1787musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1788{
1789 struct musb *musb = dev_to_musb(dev);
1790 unsigned long flags;
1791 unsigned long val;
1792 int vbus;
1793 u8 devctl;
1794
1795 spin_lock_irqsave(&musb->lock, flags);
1796 val = musb->a_wait_bcon;
1797 vbus = musb_platform_get_vbus_status(musb);
1798 if (vbus < 0) {
1799 /* Use default MUSB method by means of DEVCTL register */
1800 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1801 if ((devctl & MUSB_DEVCTL_VBUS)
1802 == (3 << MUSB_DEVCTL_VBUS_SHIFT))
1803 vbus = 1;
1804 else
1805 vbus = 0;
1806 }
1807 spin_unlock_irqrestore(&musb->lock, flags);
1808
1809 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1810 vbus ? "on" : "off", val);
1811}
1812static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1813
1814/* Gadget drivers can't know that a host is connected so they might want
1815 * to start SRP, but users can. This allows userspace to trigger SRP.
1816 */
1817static ssize_t
1818musb_srp_store(struct device *dev, struct device_attribute *attr,
1819 const char *buf, size_t n)
1820{
1821 struct musb *musb = dev_to_musb(dev);
1822 unsigned short srp;
1823
1824 if (sscanf(buf, "%hu", &srp) != 1
1825 || (srp != 1)) {
1826 dev_err(dev, "SRP: Value must be 1\n");
1827 return -EINVAL;
1828 }
1829
1830 if (srp == 1)
1831 musb_g_wakeup(musb);
1832
1833 return n;
1834}
1835static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1836
1837static struct attribute *musb_attributes[] = {
1838 &dev_attr_mode.attr,
1839 &dev_attr_vbus.attr,
1840 &dev_attr_srp.attr,
1841 NULL
1842};
1843
1844static const struct attribute_group musb_attr_group = {
1845 .attrs = musb_attributes,
1846};
1847
1848#define MUSB_QUIRK_B_INVALID_VBUS_91 (MUSB_DEVCTL_BDEVICE | \
1849 (2 << MUSB_DEVCTL_VBUS_SHIFT) | \
1850 MUSB_DEVCTL_SESSION)
1851#define MUSB_QUIRK_A_DISCONNECT_19 ((3 << MUSB_DEVCTL_VBUS_SHIFT) | \
1852 MUSB_DEVCTL_SESSION)
1853
1854/*
1855 * Check the musb devctl session bit to determine if we want to
1856 * allow PM runtime for the device. In general, we want to keep things
1857 * active when the session bit is set except after host disconnect.
1858 *
1859 * Only called from musb_irq_work. If this ever needs to get called
1860 * elsewhere, proper locking must be implemented for musb->session.
1861 */
1862static void musb_pm_runtime_check_session(struct musb *musb)
1863{
1864 u8 devctl, s;
1865 int error;
1866
1867 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1868
1869 /* Handle session status quirks first */
1870 s = MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV |
1871 MUSB_DEVCTL_HR;
1872 switch (devctl & ~s) {
1873 case MUSB_QUIRK_B_INVALID_VBUS_91:
1874 if (musb->quirk_retries--) {
1875 musb_dbg(musb,
1876 "Poll devctl on invalid vbus, assume no session");
1877 schedule_delayed_work(&musb->irq_work,
1878 msecs_to_jiffies(1000));
1879
1880 return;
1881 }
1882 case MUSB_QUIRK_A_DISCONNECT_19:
1883 if (musb->quirk_retries--) {
1884 musb_dbg(musb,
1885 "Poll devctl on possible host mode disconnect");
1886 schedule_delayed_work(&musb->irq_work,
1887 msecs_to_jiffies(1000));
1888
1889 return;
1890 }
1891 if (!musb->session)
1892 break;
1893 musb_dbg(musb, "Allow PM on possible host mode disconnect");
1894 pm_runtime_mark_last_busy(musb->controller);
1895 pm_runtime_put_autosuspend(musb->controller);
1896 musb->session = false;
1897 return;
1898 default:
1899 break;
1900 }
1901
1902 /* No need to do anything if session has not changed */
1903 s = devctl & MUSB_DEVCTL_SESSION;
1904 if (s == musb->session)
1905 return;
1906
1907 /* Block PM or allow PM? */
1908 if (s) {
1909 musb_dbg(musb, "Block PM on active session: %02x", devctl);
1910 error = pm_runtime_get_sync(musb->controller);
1911 if (error < 0)
1912 dev_err(musb->controller, "Could not enable: %i\n",
1913 error);
1914 musb->quirk_retries = 3;
1915 } else {
1916 musb_dbg(musb, "Allow PM with no session: %02x", devctl);
1917 pm_runtime_mark_last_busy(musb->controller);
1918 pm_runtime_put_autosuspend(musb->controller);
1919 }
1920
1921 musb->session = s;
1922}
1923
1924/* Only used to provide driver mode change events */
1925static void musb_irq_work(struct work_struct *data)
1926{
1927 struct musb *musb = container_of(data, struct musb, irq_work.work);
1928 int error;
1929
1930 error = pm_runtime_get_sync(musb->controller);
1931 if (error < 0) {
1932 dev_err(musb->controller, "Could not enable: %i\n", error);
1933
1934 return;
1935 }
1936
1937 musb_pm_runtime_check_session(musb);
1938
1939 if (musb->xceiv->otg->state != musb->xceiv_old_state) {
1940 musb->xceiv_old_state = musb->xceiv->otg->state;
1941 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1942 }
1943
1944 pm_runtime_mark_last_busy(musb->controller);
1945 pm_runtime_put_autosuspend(musb->controller);
1946}
1947
1948static void musb_recover_from_babble(struct musb *musb)
1949{
1950 int ret;
1951 u8 devctl;
1952
1953 musb_disable_interrupts(musb);
1954
1955 /*
1956 * wait at least 320 cycles of 60MHz clock. That's 5.3us, we will give
1957 * it some slack and wait for 10us.
1958 */
1959 udelay(10);
1960
1961 ret = musb_platform_recover(musb);
1962 if (ret) {
1963 musb_enable_interrupts(musb);
1964 return;
1965 }
1966
1967 /* drop session bit */
1968 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1969 devctl &= ~MUSB_DEVCTL_SESSION;
1970 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
1971
1972 /* tell usbcore about it */
1973 musb_root_disconnect(musb);
1974
1975 /*
1976 * When a babble condition occurs, the musb controller
1977 * removes the session bit and the endpoint config is lost.
1978 */
1979 if (musb->dyn_fifo)
1980 ret = ep_config_from_table(musb);
1981 else
1982 ret = ep_config_from_hw(musb);
1983
1984 /* restart session */
1985 if (ret == 0)
1986 musb_start(musb);
1987}
1988
1989/* --------------------------------------------------------------------------
1990 * Init support
1991 */
1992
1993static struct musb *allocate_instance(struct device *dev,
1994 const struct musb_hdrc_config *config, void __iomem *mbase)
1995{
1996 struct musb *musb;
1997 struct musb_hw_ep *ep;
1998 int epnum;
1999 int ret;
2000
2001 musb = devm_kzalloc(dev, sizeof(*musb), GFP_KERNEL);
2002 if (!musb)
2003 return NULL;
2004
2005 INIT_LIST_HEAD(&musb->control);
2006 INIT_LIST_HEAD(&musb->in_bulk);
2007 INIT_LIST_HEAD(&musb->out_bulk);
2008 INIT_LIST_HEAD(&musb->pending_list);
2009
2010 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
2011 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
2012 musb->mregs = mbase;
2013 musb->ctrl_base = mbase;
2014 musb->nIrq = -ENODEV;
2015 musb->config = config;
2016 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
2017 for (epnum = 0, ep = musb->endpoints;
2018 epnum < musb->config->num_eps;
2019 epnum++, ep++) {
2020 ep->musb = musb;
2021 ep->epnum = epnum;
2022 }
2023
2024 musb->controller = dev;
2025
2026 ret = musb_host_alloc(musb);
2027 if (ret < 0)
2028 goto err_free;
2029
2030 dev_set_drvdata(dev, musb);
2031
2032 return musb;
2033
2034err_free:
2035 return NULL;
2036}
2037
2038static void musb_free(struct musb *musb)
2039{
2040 /* this has multiple entry modes. it handles fault cleanup after
2041 * probe(), where things may be partially set up, as well as rmmod
2042 * cleanup after everything's been de-activated.
2043 */
2044
2045#ifdef CONFIG_SYSFS
2046 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
2047#endif
2048
2049 if (musb->nIrq >= 0) {
2050 if (musb->irq_wake)
2051 disable_irq_wake(musb->nIrq);
2052 free_irq(musb->nIrq, musb);
2053 }
2054
2055 musb_host_free(musb);
2056}
2057
2058struct musb_pending_work {
2059 int (*callback)(struct musb *musb, void *data);
2060 void *data;
2061 struct list_head node;
2062};
2063
2064#ifdef CONFIG_PM
2065/*
2066 * Called from musb_runtime_resume(), musb_resume(), and
2067 * musb_queue_resume_work(). Callers must take musb->lock.
2068 */
2069static int musb_run_resume_work(struct musb *musb)
2070{
2071 struct musb_pending_work *w, *_w;
2072 unsigned long flags;
2073 int error = 0;
2074
2075 spin_lock_irqsave(&musb->list_lock, flags);
2076 list_for_each_entry_safe(w, _w, &musb->pending_list, node) {
2077 if (w->callback) {
2078 error = w->callback(musb, w->data);
2079 if (error < 0) {
2080 dev_err(musb->controller,
2081 "resume callback %p failed: %i\n",
2082 w->callback, error);
2083 }
2084 }
2085 list_del(&w->node);
2086 devm_kfree(musb->controller, w);
2087 }
2088 spin_unlock_irqrestore(&musb->list_lock, flags);
2089
2090 return error;
2091}
2092#endif
2093
2094/*
2095 * Called to run work if device is active or else queue the work to happen
2096 * on resume. Caller must take musb->lock and must hold an RPM reference.
2097 *
2098 * Note that we cowardly refuse queuing work after musb PM runtime
2099 * resume is done calling musb_run_resume_work() and return -EINPROGRESS
2100 * instead.
2101 */
2102int musb_queue_resume_work(struct musb *musb,
2103 int (*callback)(struct musb *musb, void *data),
2104 void *data)
2105{
2106 struct musb_pending_work *w;
2107 unsigned long flags;
2108 int error;
2109
2110 if (WARN_ON(!callback))
2111 return -EINVAL;
2112
2113 if (pm_runtime_active(musb->controller))
2114 return callback(musb, data);
2115
2116 w = devm_kzalloc(musb->controller, sizeof(*w), GFP_ATOMIC);
2117 if (!w)
2118 return -ENOMEM;
2119
2120 w->callback = callback;
2121 w->data = data;
2122 spin_lock_irqsave(&musb->list_lock, flags);
2123 if (musb->is_runtime_suspended) {
2124 list_add_tail(&w->node, &musb->pending_list);
2125 error = 0;
2126 } else {
2127 dev_err(musb->controller, "could not add resume work %p\n",
2128 callback);
2129 devm_kfree(musb->controller, w);
2130 error = -EINPROGRESS;
2131 }
2132 spin_unlock_irqrestore(&musb->list_lock, flags);
2133
2134 return error;
2135}
2136EXPORT_SYMBOL_GPL(musb_queue_resume_work);
2137
2138static void musb_deassert_reset(struct work_struct *work)
2139{
2140 struct musb *musb;
2141 unsigned long flags;
2142
2143 musb = container_of(work, struct musb, deassert_reset_work.work);
2144
2145 spin_lock_irqsave(&musb->lock, flags);
2146
2147 if (musb->port1_status & USB_PORT_STAT_RESET)
2148 musb_port_reset(musb, false);
2149
2150 spin_unlock_irqrestore(&musb->lock, flags);
2151}
2152
2153/*
2154 * Perform generic per-controller initialization.
2155 *
2156 * @dev: the controller (already clocked, etc)
2157 * @nIrq: IRQ number
2158 * @ctrl: virtual address of controller registers,
2159 * not yet corrected for platform-specific offsets
2160 */
2161static int
2162musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
2163{
2164 int status;
2165 struct musb *musb;
2166 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
2167
2168 /* The driver might handle more features than the board; OK.
2169 * Fail when the board needs a feature that's not enabled.
2170 */
2171 if (!plat) {
2172 dev_err(dev, "no platform_data?\n");
2173 status = -ENODEV;
2174 goto fail0;
2175 }
2176
2177 /* allocate */
2178 musb = allocate_instance(dev, plat->config, ctrl);
2179 if (!musb) {
2180 status = -ENOMEM;
2181 goto fail0;
2182 }
2183
2184 spin_lock_init(&musb->lock);
2185 spin_lock_init(&musb->list_lock);
2186 musb->board_set_power = plat->set_power;
2187 musb->min_power = plat->min_power;
2188 musb->ops = plat->platform_ops;
2189 musb->port_mode = plat->mode;
2190
2191 /*
2192 * Initialize the default IO functions. At least omap2430 needs
2193 * these early. We initialize the platform specific IO functions
2194 * later on.
2195 */
2196 musb_readb = musb_default_readb;
2197 musb_writeb = musb_default_writeb;
2198 musb_readw = musb_default_readw;
2199 musb_writew = musb_default_writew;
2200 musb_readl = musb_default_readl;
2201 musb_writel = musb_default_writel;
2202
2203 /* The musb_platform_init() call:
2204 * - adjusts musb->mregs
2205 * - sets the musb->isr
2206 * - may initialize an integrated transceiver
2207 * - initializes musb->xceiv, usually by otg_get_phy()
2208 * - stops powering VBUS
2209 *
2210 * There are various transceiver configurations. Blackfin,
2211 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
2212 * external/discrete ones in various flavors (twl4030 family,
2213 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
2214 */
2215 status = musb_platform_init(musb);
2216 if (status < 0)
2217 goto fail1;
2218
2219 if (!musb->isr) {
2220 status = -ENODEV;
2221 goto fail2;
2222 }
2223
2224 if (musb->ops->quirks)
2225 musb->io.quirks = musb->ops->quirks;
2226
2227 /* Most devices use indexed offset or flat offset */
2228 if (musb->io.quirks & MUSB_INDEXED_EP) {
2229 musb->io.ep_offset = musb_indexed_ep_offset;
2230 musb->io.ep_select = musb_indexed_ep_select;
2231 } else {
2232 musb->io.ep_offset = musb_flat_ep_offset;
2233 musb->io.ep_select = musb_flat_ep_select;
2234 }
2235
2236 /* At least tusb6010 has its own offsets */
2237 if (musb->ops->ep_offset)
2238 musb->io.ep_offset = musb->ops->ep_offset;
2239 if (musb->ops->ep_select)
2240 musb->io.ep_select = musb->ops->ep_select;
2241
2242 if (musb->ops->fifo_mode)
2243 fifo_mode = musb->ops->fifo_mode;
2244 else
2245 fifo_mode = 4;
2246
2247 if (musb->ops->fifo_offset)
2248 musb->io.fifo_offset = musb->ops->fifo_offset;
2249 else
2250 musb->io.fifo_offset = musb_default_fifo_offset;
2251
2252 if (musb->ops->busctl_offset)
2253 musb->io.busctl_offset = musb->ops->busctl_offset;
2254 else
2255 musb->io.busctl_offset = musb_default_busctl_offset;
2256
2257 if (musb->ops->readb)
2258 musb_readb = musb->ops->readb;
2259 if (musb->ops->writeb)
2260 musb_writeb = musb->ops->writeb;
2261 if (musb->ops->readw)
2262 musb_readw = musb->ops->readw;
2263 if (musb->ops->writew)
2264 musb_writew = musb->ops->writew;
2265 if (musb->ops->readl)
2266 musb_readl = musb->ops->readl;
2267 if (musb->ops->writel)
2268 musb_writel = musb->ops->writel;
2269
2270#ifndef CONFIG_MUSB_PIO_ONLY
2271 if (!musb->ops->dma_init || !musb->ops->dma_exit) {
2272 dev_err(dev, "DMA controller not set\n");
2273 status = -ENODEV;
2274 goto fail2;
2275 }
2276 musb_dma_controller_create = musb->ops->dma_init;
2277 musb_dma_controller_destroy = musb->ops->dma_exit;
2278#endif
2279
2280 if (musb->ops->read_fifo)
2281 musb->io.read_fifo = musb->ops->read_fifo;
2282 else
2283 musb->io.read_fifo = musb_default_read_fifo;
2284
2285 if (musb->ops->write_fifo)
2286 musb->io.write_fifo = musb->ops->write_fifo;
2287 else
2288 musb->io.write_fifo = musb_default_write_fifo;
2289
2290 if (!musb->xceiv->io_ops) {
2291 musb->xceiv->io_dev = musb->controller;
2292 musb->xceiv->io_priv = musb->mregs;
2293 musb->xceiv->io_ops = &musb_ulpi_access;
2294 }
2295
2296 if (musb->ops->phy_callback)
2297 musb_phy_callback = musb->ops->phy_callback;
2298
2299 /*
2300 * We need musb_read/write functions initialized for PM.
2301 * Note that at least 2430 glue needs autosuspend delay
2302 * somewhere above 300 ms for the hardware to idle properly
2303 * after disconnecting the cable in host mode. Let's use
2304 * 500 ms for some margin.
2305 */
2306 pm_runtime_use_autosuspend(musb->controller);
2307 pm_runtime_set_autosuspend_delay(musb->controller, 500);
2308 pm_runtime_enable(musb->controller);
2309 pm_runtime_get_sync(musb->controller);
2310
2311 status = usb_phy_init(musb->xceiv);
2312 if (status < 0)
2313 goto err_usb_phy_init;
2314
2315 if (use_dma && dev->dma_mask) {
2316 musb->dma_controller =
2317 musb_dma_controller_create(musb, musb->mregs);
2318 if (IS_ERR(musb->dma_controller)) {
2319 status = PTR_ERR(musb->dma_controller);
2320 goto fail2_5;
2321 }
2322 }
2323
2324 /* be sure interrupts are disabled before connecting ISR */
2325 musb_platform_disable(musb);
2326 musb_generic_disable(musb);
2327
2328 /* Init IRQ workqueue before request_irq */
2329 INIT_DELAYED_WORK(&musb->irq_work, musb_irq_work);
2330 INIT_DELAYED_WORK(&musb->deassert_reset_work, musb_deassert_reset);
2331 INIT_DELAYED_WORK(&musb->finish_resume_work, musb_host_finish_resume);
2332
2333 /* setup musb parts of the core (especially endpoints) */
2334 status = musb_core_init(plat->config->multipoint
2335 ? MUSB_CONTROLLER_MHDRC
2336 : MUSB_CONTROLLER_HDRC, musb);
2337 if (status < 0)
2338 goto fail3;
2339
2340 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
2341
2342 /* attach to the IRQ */
2343 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
2344 dev_err(dev, "request_irq %d failed!\n", nIrq);
2345 status = -ENODEV;
2346 goto fail3;
2347 }
2348 musb->nIrq = nIrq;
2349 /* FIXME this handles wakeup irqs wrong */
2350 if (enable_irq_wake(nIrq) == 0) {
2351 musb->irq_wake = 1;
2352 device_init_wakeup(dev, 1);
2353 } else {
2354 musb->irq_wake = 0;
2355 }
2356
2357 /* program PHY to use external vBus if required */
2358 if (plat->extvbus) {
2359 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
2360 busctl |= MUSB_ULPI_USE_EXTVBUS;
2361 musb_write_ulpi_buscontrol(musb->mregs, busctl);
2362 }
2363
2364 if (musb->xceiv->otg->default_a) {
2365 MUSB_HST_MODE(musb);
2366 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
2367 } else {
2368 MUSB_DEV_MODE(musb);
2369 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
2370 }
2371
2372 switch (musb->port_mode) {
2373 case MUSB_PORT_MODE_HOST:
2374 status = musb_host_setup(musb, plat->power);
2375 if (status < 0)
2376 goto fail3;
2377 status = musb_platform_set_mode(musb, MUSB_HOST);
2378 break;
2379 case MUSB_PORT_MODE_GADGET:
2380 status = musb_gadget_setup(musb);
2381 if (status < 0)
2382 goto fail3;
2383 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
2384 break;
2385 case MUSB_PORT_MODE_DUAL_ROLE:
2386 status = musb_host_setup(musb, plat->power);
2387 if (status < 0)
2388 goto fail3;
2389 status = musb_gadget_setup(musb);
2390 if (status) {
2391 musb_host_cleanup(musb);
2392 goto fail3;
2393 }
2394 status = musb_platform_set_mode(musb, MUSB_OTG);
2395 break;
2396 default:
2397 dev_err(dev, "unsupported port mode %d\n", musb->port_mode);
2398 break;
2399 }
2400
2401 if (status < 0)
2402 goto fail3;
2403
2404 status = musb_init_debugfs(musb);
2405 if (status < 0)
2406 goto fail4;
2407
2408 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
2409 if (status)
2410 goto fail5;
2411
2412 musb->is_initialized = 1;
2413 pm_runtime_mark_last_busy(musb->controller);
2414 pm_runtime_put_autosuspend(musb->controller);
2415
2416 return 0;
2417
2418fail5:
2419 musb_exit_debugfs(musb);
2420
2421fail4:
2422 musb_gadget_cleanup(musb);
2423 musb_host_cleanup(musb);
2424
2425fail3:
2426 cancel_delayed_work_sync(&musb->irq_work);
2427 cancel_delayed_work_sync(&musb->finish_resume_work);
2428 cancel_delayed_work_sync(&musb->deassert_reset_work);
2429 if (musb->dma_controller)
2430 musb_dma_controller_destroy(musb->dma_controller);
2431
2432fail2_5:
2433 usb_phy_shutdown(musb->xceiv);
2434
2435err_usb_phy_init:
2436 pm_runtime_dont_use_autosuspend(musb->controller);
2437 pm_runtime_put_sync(musb->controller);
2438 pm_runtime_disable(musb->controller);
2439
2440fail2:
2441 if (musb->irq_wake)
2442 device_init_wakeup(dev, 0);
2443 musb_platform_exit(musb);
2444
2445fail1:
2446 if (status != -EPROBE_DEFER)
2447 dev_err(musb->controller,
2448 "%s failed with status %d\n", __func__, status);
2449
2450 musb_free(musb);
2451
2452fail0:
2453
2454 return status;
2455
2456}
2457
2458/*-------------------------------------------------------------------------*/
2459
2460/* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2461 * bridge to a platform device; this driver then suffices.
2462 */
2463static int musb_probe(struct platform_device *pdev)
2464{
2465 struct device *dev = &pdev->dev;
2466 int irq = platform_get_irq_byname(pdev, "mc");
2467 struct resource *iomem;
2468 void __iomem *base;
2469
2470 if (irq <= 0)
2471 return -ENODEV;
2472
2473 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2474 base = devm_ioremap_resource(dev, iomem);
2475 if (IS_ERR(base))
2476 return PTR_ERR(base);
2477
2478 return musb_init_controller(dev, irq, base);
2479}
2480
2481static int musb_remove(struct platform_device *pdev)
2482{
2483 struct device *dev = &pdev->dev;
2484 struct musb *musb = dev_to_musb(dev);
2485 unsigned long flags;
2486
2487 /* this gets called on rmmod.
2488 * - Host mode: host may still be active
2489 * - Peripheral mode: peripheral is deactivated (or never-activated)
2490 * - OTG mode: both roles are deactivated (or never-activated)
2491 */
2492 musb_exit_debugfs(musb);
2493
2494 cancel_delayed_work_sync(&musb->irq_work);
2495 cancel_delayed_work_sync(&musb->finish_resume_work);
2496 cancel_delayed_work_sync(&musb->deassert_reset_work);
2497 pm_runtime_get_sync(musb->controller);
2498 musb_host_cleanup(musb);
2499 musb_gadget_cleanup(musb);
2500 musb_platform_disable(musb);
2501 spin_lock_irqsave(&musb->lock, flags);
2502 musb_generic_disable(musb);
2503 spin_unlock_irqrestore(&musb->lock, flags);
2504 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
2505 pm_runtime_dont_use_autosuspend(musb->controller);
2506 pm_runtime_put_sync(musb->controller);
2507 pm_runtime_disable(musb->controller);
2508 musb_platform_exit(musb);
2509 musb_phy_callback = NULL;
2510 if (musb->dma_controller)
2511 musb_dma_controller_destroy(musb->dma_controller);
2512 usb_phy_shutdown(musb->xceiv);
2513 musb_free(musb);
2514 device_init_wakeup(dev, 0);
2515 return 0;
2516}
2517
2518#ifdef CONFIG_PM
2519
2520static void musb_save_context(struct musb *musb)
2521{
2522 int i;
2523 void __iomem *musb_base = musb->mregs;
2524 void __iomem *epio;
2525
2526 musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2527 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2528 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
2529 musb->context.power = musb_readb(musb_base, MUSB_POWER);
2530 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2531 musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2532 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2533
2534 for (i = 0; i < musb->config->num_eps; ++i) {
2535 struct musb_hw_ep *hw_ep;
2536
2537 hw_ep = &musb->endpoints[i];
2538 if (!hw_ep)
2539 continue;
2540
2541 epio = hw_ep->regs;
2542 if (!epio)
2543 continue;
2544
2545 musb_writeb(musb_base, MUSB_INDEX, i);
2546 musb->context.index_regs[i].txmaxp =
2547 musb_readw(epio, MUSB_TXMAXP);
2548 musb->context.index_regs[i].txcsr =
2549 musb_readw(epio, MUSB_TXCSR);
2550 musb->context.index_regs[i].rxmaxp =
2551 musb_readw(epio, MUSB_RXMAXP);
2552 musb->context.index_regs[i].rxcsr =
2553 musb_readw(epio, MUSB_RXCSR);
2554
2555 if (musb->dyn_fifo) {
2556 musb->context.index_regs[i].txfifoadd =
2557 musb_read_txfifoadd(musb_base);
2558 musb->context.index_regs[i].rxfifoadd =
2559 musb_read_rxfifoadd(musb_base);
2560 musb->context.index_regs[i].txfifosz =
2561 musb_read_txfifosz(musb_base);
2562 musb->context.index_regs[i].rxfifosz =
2563 musb_read_rxfifosz(musb_base);
2564 }
2565
2566 musb->context.index_regs[i].txtype =
2567 musb_readb(epio, MUSB_TXTYPE);
2568 musb->context.index_regs[i].txinterval =
2569 musb_readb(epio, MUSB_TXINTERVAL);
2570 musb->context.index_regs[i].rxtype =
2571 musb_readb(epio, MUSB_RXTYPE);
2572 musb->context.index_regs[i].rxinterval =
2573 musb_readb(epio, MUSB_RXINTERVAL);
2574
2575 musb->context.index_regs[i].txfunaddr =
2576 musb_read_txfunaddr(musb, i);
2577 musb->context.index_regs[i].txhubaddr =
2578 musb_read_txhubaddr(musb, i);
2579 musb->context.index_regs[i].txhubport =
2580 musb_read_txhubport(musb, i);
2581
2582 musb->context.index_regs[i].rxfunaddr =
2583 musb_read_rxfunaddr(musb, i);
2584 musb->context.index_regs[i].rxhubaddr =
2585 musb_read_rxhubaddr(musb, i);
2586 musb->context.index_regs[i].rxhubport =
2587 musb_read_rxhubport(musb, i);
2588 }
2589}
2590
2591static void musb_restore_context(struct musb *musb)
2592{
2593 int i;
2594 void __iomem *musb_base = musb->mregs;
2595 void __iomem *epio;
2596 u8 power;
2597
2598 musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2599 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2600 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
2601
2602 /* Don't affect SUSPENDM/RESUME bits in POWER reg */
2603 power = musb_readb(musb_base, MUSB_POWER);
2604 power &= MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME;
2605 musb->context.power &= ~(MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME);
2606 power |= musb->context.power;
2607 musb_writeb(musb_base, MUSB_POWER, power);
2608
2609 musb_writew(musb_base, MUSB_INTRTXE, musb->intrtxe);
2610 musb_writew(musb_base, MUSB_INTRRXE, musb->intrrxe);
2611 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2612 if (musb->context.devctl & MUSB_DEVCTL_SESSION)
2613 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
2614
2615 for (i = 0; i < musb->config->num_eps; ++i) {
2616 struct musb_hw_ep *hw_ep;
2617
2618 hw_ep = &musb->endpoints[i];
2619 if (!hw_ep)
2620 continue;
2621
2622 epio = hw_ep->regs;
2623 if (!epio)
2624 continue;
2625
2626 musb_writeb(musb_base, MUSB_INDEX, i);
2627 musb_writew(epio, MUSB_TXMAXP,
2628 musb->context.index_regs[i].txmaxp);
2629 musb_writew(epio, MUSB_TXCSR,
2630 musb->context.index_regs[i].txcsr);
2631 musb_writew(epio, MUSB_RXMAXP,
2632 musb->context.index_regs[i].rxmaxp);
2633 musb_writew(epio, MUSB_RXCSR,
2634 musb->context.index_regs[i].rxcsr);
2635
2636 if (musb->dyn_fifo) {
2637 musb_write_txfifosz(musb_base,
2638 musb->context.index_regs[i].txfifosz);
2639 musb_write_rxfifosz(musb_base,
2640 musb->context.index_regs[i].rxfifosz);
2641 musb_write_txfifoadd(musb_base,
2642 musb->context.index_regs[i].txfifoadd);
2643 musb_write_rxfifoadd(musb_base,
2644 musb->context.index_regs[i].rxfifoadd);
2645 }
2646
2647 musb_writeb(epio, MUSB_TXTYPE,
2648 musb->context.index_regs[i].txtype);
2649 musb_writeb(epio, MUSB_TXINTERVAL,
2650 musb->context.index_regs[i].txinterval);
2651 musb_writeb(epio, MUSB_RXTYPE,
2652 musb->context.index_regs[i].rxtype);
2653 musb_writeb(epio, MUSB_RXINTERVAL,
2654
2655 musb->context.index_regs[i].rxinterval);
2656 musb_write_txfunaddr(musb, i,
2657 musb->context.index_regs[i].txfunaddr);
2658 musb_write_txhubaddr(musb, i,
2659 musb->context.index_regs[i].txhubaddr);
2660 musb_write_txhubport(musb, i,
2661 musb->context.index_regs[i].txhubport);
2662
2663 musb_write_rxfunaddr(musb, i,
2664 musb->context.index_regs[i].rxfunaddr);
2665 musb_write_rxhubaddr(musb, i,
2666 musb->context.index_regs[i].rxhubaddr);
2667 musb_write_rxhubport(musb, i,
2668 musb->context.index_regs[i].rxhubport);
2669 }
2670 musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
2671}
2672
2673static int musb_suspend(struct device *dev)
2674{
2675 struct musb *musb = dev_to_musb(dev);
2676 unsigned long flags;
2677
2678 musb_platform_disable(musb);
2679 musb_generic_disable(musb);
2680 WARN_ON(!list_empty(&musb->pending_list));
2681
2682 spin_lock_irqsave(&musb->lock, flags);
2683
2684 if (is_peripheral_active(musb)) {
2685 /* FIXME force disconnect unless we know USB will wake
2686 * the system up quickly enough to respond ...
2687 */
2688 } else if (is_host_active(musb)) {
2689 /* we know all the children are suspended; sometimes
2690 * they will even be wakeup-enabled.
2691 */
2692 }
2693
2694 musb_save_context(musb);
2695
2696 spin_unlock_irqrestore(&musb->lock, flags);
2697 return 0;
2698}
2699
2700static int musb_resume(struct device *dev)
2701{
2702 struct musb *musb = dev_to_musb(dev);
2703 unsigned long flags;
2704 int error;
2705 u8 devctl;
2706 u8 mask;
2707
2708 /*
2709 * For static cmos like DaVinci, register values were preserved
2710 * unless for some reason the whole soc powered down or the USB
2711 * module got reset through the PSC (vs just being disabled).
2712 *
2713 * For the DSPS glue layer though, a full register restore has to
2714 * be done. As it shouldn't harm other platforms, we do it
2715 * unconditionally.
2716 */
2717
2718 musb_restore_context(musb);
2719
2720 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2721 mask = MUSB_DEVCTL_BDEVICE | MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV;
2722 if ((devctl & mask) != (musb->context.devctl & mask))
2723 musb->port1_status = 0;
2724
2725 /*
2726 * The USB HUB code expects the device to be in RPM_ACTIVE once it came
2727 * out of suspend
2728 */
2729 pm_runtime_disable(dev);
2730 pm_runtime_set_active(dev);
2731 pm_runtime_enable(dev);
2732
2733 musb_start(musb);
2734
2735 spin_lock_irqsave(&musb->lock, flags);
2736 error = musb_run_resume_work(musb);
2737 if (error)
2738 dev_err(musb->controller, "resume work failed with %i\n",
2739 error);
2740 spin_unlock_irqrestore(&musb->lock, flags);
2741
2742 return 0;
2743}
2744
2745static int musb_runtime_suspend(struct device *dev)
2746{
2747 struct musb *musb = dev_to_musb(dev);
2748
2749 musb_save_context(musb);
2750 musb->is_runtime_suspended = 1;
2751
2752 return 0;
2753}
2754
2755static int musb_runtime_resume(struct device *dev)
2756{
2757 struct musb *musb = dev_to_musb(dev);
2758 unsigned long flags;
2759 int error;
2760
2761 /*
2762 * When pm_runtime_get_sync called for the first time in driver
2763 * init, some of the structure is still not initialized which is
2764 * used in restore function. But clock needs to be
2765 * enabled before any register access, so
2766 * pm_runtime_get_sync has to be called.
2767 * Also context restore without save does not make
2768 * any sense
2769 */
2770 if (!musb->is_initialized)
2771 return 0;
2772
2773 musb_restore_context(musb);
2774
2775 spin_lock_irqsave(&musb->lock, flags);
2776 error = musb_run_resume_work(musb);
2777 if (error)
2778 dev_err(musb->controller, "resume work failed with %i\n",
2779 error);
2780 musb->is_runtime_suspended = 0;
2781 spin_unlock_irqrestore(&musb->lock, flags);
2782
2783 return 0;
2784}
2785
2786static const struct dev_pm_ops musb_dev_pm_ops = {
2787 .suspend = musb_suspend,
2788 .resume = musb_resume,
2789 .runtime_suspend = musb_runtime_suspend,
2790 .runtime_resume = musb_runtime_resume,
2791};
2792
2793#define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2794#else
2795#define MUSB_DEV_PM_OPS NULL
2796#endif
2797
2798static struct platform_driver musb_driver = {
2799 .driver = {
2800 .name = (char *)musb_driver_name,
2801 .bus = &platform_bus_type,
2802 .pm = MUSB_DEV_PM_OPS,
2803 },
2804 .probe = musb_probe,
2805 .remove = musb_remove,
2806};
2807
2808module_platform_driver(musb_driver);