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1/*
2 * MUSB OTG driver core code
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35/*
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
37 *
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
42 *
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
47 *
48 *
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
53 *
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
56 *
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
61 *
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
66 * each direction.
67 *
68 * RESULT: one device may be perceived as blocking another one.
69 *
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
74 *
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
80 */
81
82/*
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific information
87 * (plus recentrly, SOC or family details)
88 *
89 * Most of the conditional compilation will (someday) vanish.
90 */
91
92#include <linux/module.h>
93#include <linux/kernel.h>
94#include <linux/sched.h>
95#include <linux/slab.h>
96#include <linux/list.h>
97#include <linux/kobject.h>
98#include <linux/prefetch.h>
99#include <linux/platform_device.h>
100#include <linux/io.h>
101#include <linux/dma-mapping.h>
102#include <linux/usb.h>
103
104#include "musb_core.h"
105
106#define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
107
108
109#define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
110#define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
111
112#define MUSB_VERSION "6.0"
113
114#define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
115
116#define MUSB_DRIVER_NAME "musb-hdrc"
117const char musb_driver_name[] = MUSB_DRIVER_NAME;
118
119MODULE_DESCRIPTION(DRIVER_INFO);
120MODULE_AUTHOR(DRIVER_AUTHOR);
121MODULE_LICENSE("GPL");
122MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
123
124
125/*-------------------------------------------------------------------------*/
126
127static inline struct musb *dev_to_musb(struct device *dev)
128{
129 return dev_get_drvdata(dev);
130}
131
132/*-------------------------------------------------------------------------*/
133
134#ifndef CONFIG_BLACKFIN
135static int musb_ulpi_read(struct usb_phy *phy, u32 reg)
136{
137 void __iomem *addr = phy->io_priv;
138 int i = 0;
139 u8 r;
140 u8 power;
141 int ret;
142
143 pm_runtime_get_sync(phy->io_dev);
144
145 /* Make sure the transceiver is not in low power mode */
146 power = musb_readb(addr, MUSB_POWER);
147 power &= ~MUSB_POWER_SUSPENDM;
148 musb_writeb(addr, MUSB_POWER, power);
149
150 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
151 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
152 */
153
154 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg);
155 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
156 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
157
158 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
159 & MUSB_ULPI_REG_CMPLT)) {
160 i++;
161 if (i == 10000) {
162 ret = -ETIMEDOUT;
163 goto out;
164 }
165
166 }
167 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
168 r &= ~MUSB_ULPI_REG_CMPLT;
169 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
170
171 ret = musb_readb(addr, MUSB_ULPI_REG_DATA);
172
173out:
174 pm_runtime_put(phy->io_dev);
175
176 return ret;
177}
178
179static int musb_ulpi_write(struct usb_phy *phy, u32 val, u32 reg)
180{
181 void __iomem *addr = phy->io_priv;
182 int i = 0;
183 u8 r = 0;
184 u8 power;
185 int ret = 0;
186
187 pm_runtime_get_sync(phy->io_dev);
188
189 /* Make sure the transceiver is not in low power mode */
190 power = musb_readb(addr, MUSB_POWER);
191 power &= ~MUSB_POWER_SUSPENDM;
192 musb_writeb(addr, MUSB_POWER, power);
193
194 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg);
195 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)val);
196 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
197
198 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
199 & MUSB_ULPI_REG_CMPLT)) {
200 i++;
201 if (i == 10000) {
202 ret = -ETIMEDOUT;
203 goto out;
204 }
205 }
206
207 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
208 r &= ~MUSB_ULPI_REG_CMPLT;
209 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
210
211out:
212 pm_runtime_put(phy->io_dev);
213
214 return ret;
215}
216#else
217#define musb_ulpi_read NULL
218#define musb_ulpi_write NULL
219#endif
220
221static struct usb_phy_io_ops musb_ulpi_access = {
222 .read = musb_ulpi_read,
223 .write = musb_ulpi_write,
224};
225
226/*-------------------------------------------------------------------------*/
227
228static u32 musb_default_fifo_offset(u8 epnum)
229{
230 return 0x20 + (epnum * 4);
231}
232
233/* "flat" mapping: each endpoint has its own i/o address */
234static void musb_flat_ep_select(void __iomem *mbase, u8 epnum)
235{
236}
237
238static u32 musb_flat_ep_offset(u8 epnum, u16 offset)
239{
240 return 0x100 + (0x10 * epnum) + offset;
241}
242
243/* "indexed" mapping: INDEX register controls register bank select */
244static void musb_indexed_ep_select(void __iomem *mbase, u8 epnum)
245{
246 musb_writeb(mbase, MUSB_INDEX, epnum);
247}
248
249static u32 musb_indexed_ep_offset(u8 epnum, u16 offset)
250{
251 return 0x10 + offset;
252}
253
254static u32 musb_default_busctl_offset(u8 epnum, u16 offset)
255{
256 return 0x80 + (0x08 * epnum) + offset;
257}
258
259static u8 musb_default_readb(const void __iomem *addr, unsigned offset)
260{
261 return __raw_readb(addr + offset);
262}
263
264static void musb_default_writeb(void __iomem *addr, unsigned offset, u8 data)
265{
266 __raw_writeb(data, addr + offset);
267}
268
269static u16 musb_default_readw(const void __iomem *addr, unsigned offset)
270{
271 return __raw_readw(addr + offset);
272}
273
274static void musb_default_writew(void __iomem *addr, unsigned offset, u16 data)
275{
276 __raw_writew(data, addr + offset);
277}
278
279static u32 musb_default_readl(const void __iomem *addr, unsigned offset)
280{
281 return __raw_readl(addr + offset);
282}
283
284static void musb_default_writel(void __iomem *addr, unsigned offset, u32 data)
285{
286 __raw_writel(data, addr + offset);
287}
288
289/*
290 * Load an endpoint's FIFO
291 */
292static void musb_default_write_fifo(struct musb_hw_ep *hw_ep, u16 len,
293 const u8 *src)
294{
295 struct musb *musb = hw_ep->musb;
296 void __iomem *fifo = hw_ep->fifo;
297
298 if (unlikely(len == 0))
299 return;
300
301 prefetch((u8 *)src);
302
303 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
304 'T', hw_ep->epnum, fifo, len, src);
305
306 /* we can't assume unaligned reads work */
307 if (likely((0x01 & (unsigned long) src) == 0)) {
308 u16 index = 0;
309
310 /* best case is 32bit-aligned source address */
311 if ((0x02 & (unsigned long) src) == 0) {
312 if (len >= 4) {
313 iowrite32_rep(fifo, src + index, len >> 2);
314 index += len & ~0x03;
315 }
316 if (len & 0x02) {
317 __raw_writew(*(u16 *)&src[index], fifo);
318 index += 2;
319 }
320 } else {
321 if (len >= 2) {
322 iowrite16_rep(fifo, src + index, len >> 1);
323 index += len & ~0x01;
324 }
325 }
326 if (len & 0x01)
327 __raw_writeb(src[index], fifo);
328 } else {
329 /* byte aligned */
330 iowrite8_rep(fifo, src, len);
331 }
332}
333
334/*
335 * Unload an endpoint's FIFO
336 */
337static void musb_default_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
338{
339 struct musb *musb = hw_ep->musb;
340 void __iomem *fifo = hw_ep->fifo;
341
342 if (unlikely(len == 0))
343 return;
344
345 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
346 'R', hw_ep->epnum, fifo, len, dst);
347
348 /* we can't assume unaligned writes work */
349 if (likely((0x01 & (unsigned long) dst) == 0)) {
350 u16 index = 0;
351
352 /* best case is 32bit-aligned destination address */
353 if ((0x02 & (unsigned long) dst) == 0) {
354 if (len >= 4) {
355 ioread32_rep(fifo, dst, len >> 2);
356 index = len & ~0x03;
357 }
358 if (len & 0x02) {
359 *(u16 *)&dst[index] = __raw_readw(fifo);
360 index += 2;
361 }
362 } else {
363 if (len >= 2) {
364 ioread16_rep(fifo, dst, len >> 1);
365 index = len & ~0x01;
366 }
367 }
368 if (len & 0x01)
369 dst[index] = __raw_readb(fifo);
370 } else {
371 /* byte aligned */
372 ioread8_rep(fifo, dst, len);
373 }
374}
375
376/*
377 * Old style IO functions
378 */
379u8 (*musb_readb)(const void __iomem *addr, unsigned offset);
380EXPORT_SYMBOL_GPL(musb_readb);
381
382void (*musb_writeb)(void __iomem *addr, unsigned offset, u8 data);
383EXPORT_SYMBOL_GPL(musb_writeb);
384
385u16 (*musb_readw)(const void __iomem *addr, unsigned offset);
386EXPORT_SYMBOL_GPL(musb_readw);
387
388void (*musb_writew)(void __iomem *addr, unsigned offset, u16 data);
389EXPORT_SYMBOL_GPL(musb_writew);
390
391u32 (*musb_readl)(const void __iomem *addr, unsigned offset);
392EXPORT_SYMBOL_GPL(musb_readl);
393
394void (*musb_writel)(void __iomem *addr, unsigned offset, u32 data);
395EXPORT_SYMBOL_GPL(musb_writel);
396
397#ifndef CONFIG_MUSB_PIO_ONLY
398struct dma_controller *
399(*musb_dma_controller_create)(struct musb *musb, void __iomem *base);
400EXPORT_SYMBOL(musb_dma_controller_create);
401
402void (*musb_dma_controller_destroy)(struct dma_controller *c);
403EXPORT_SYMBOL(musb_dma_controller_destroy);
404#endif
405
406/*
407 * New style IO functions
408 */
409void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
410{
411 return hw_ep->musb->io.read_fifo(hw_ep, len, dst);
412}
413
414void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
415{
416 return hw_ep->musb->io.write_fifo(hw_ep, len, src);
417}
418
419/*-------------------------------------------------------------------------*/
420
421/* for high speed test mode; see USB 2.0 spec 7.1.20 */
422static const u8 musb_test_packet[53] = {
423 /* implicit SYNC then DATA0 to start */
424
425 /* JKJKJKJK x9 */
426 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
427 /* JJKKJJKK x8 */
428 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
429 /* JJJJKKKK x8 */
430 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
431 /* JJJJJJJKKKKKKK x8 */
432 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
433 /* JJJJJJJK x8 */
434 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
435 /* JKKKKKKK x10, JK */
436 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
437
438 /* implicit CRC16 then EOP to end */
439};
440
441void musb_load_testpacket(struct musb *musb)
442{
443 void __iomem *regs = musb->endpoints[0].regs;
444
445 musb_ep_select(musb->mregs, 0);
446 musb_write_fifo(musb->control_ep,
447 sizeof(musb_test_packet), musb_test_packet);
448 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
449}
450
451/*-------------------------------------------------------------------------*/
452
453/*
454 * Handles OTG hnp timeouts, such as b_ase0_brst
455 */
456static void musb_otg_timer_func(unsigned long data)
457{
458 struct musb *musb = (struct musb *)data;
459 unsigned long flags;
460
461 spin_lock_irqsave(&musb->lock, flags);
462 switch (musb->xceiv->otg->state) {
463 case OTG_STATE_B_WAIT_ACON:
464 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n");
465 musb_g_disconnect(musb);
466 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
467 musb->is_active = 0;
468 break;
469 case OTG_STATE_A_SUSPEND:
470 case OTG_STATE_A_WAIT_BCON:
471 dev_dbg(musb->controller, "HNP: %s timeout\n",
472 usb_otg_state_string(musb->xceiv->otg->state));
473 musb_platform_set_vbus(musb, 0);
474 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
475 break;
476 default:
477 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
478 usb_otg_state_string(musb->xceiv->otg->state));
479 }
480 spin_unlock_irqrestore(&musb->lock, flags);
481}
482
483/*
484 * Stops the HNP transition. Caller must take care of locking.
485 */
486void musb_hnp_stop(struct musb *musb)
487{
488 struct usb_hcd *hcd = musb->hcd;
489 void __iomem *mbase = musb->mregs;
490 u8 reg;
491
492 dev_dbg(musb->controller, "HNP: stop from %s\n",
493 usb_otg_state_string(musb->xceiv->otg->state));
494
495 switch (musb->xceiv->otg->state) {
496 case OTG_STATE_A_PERIPHERAL:
497 musb_g_disconnect(musb);
498 dev_dbg(musb->controller, "HNP: back to %s\n",
499 usb_otg_state_string(musb->xceiv->otg->state));
500 break;
501 case OTG_STATE_B_HOST:
502 dev_dbg(musb->controller, "HNP: Disabling HR\n");
503 if (hcd)
504 hcd->self.is_b_host = 0;
505 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
506 MUSB_DEV_MODE(musb);
507 reg = musb_readb(mbase, MUSB_POWER);
508 reg |= MUSB_POWER_SUSPENDM;
509 musb_writeb(mbase, MUSB_POWER, reg);
510 /* REVISIT: Start SESSION_REQUEST here? */
511 break;
512 default:
513 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n",
514 usb_otg_state_string(musb->xceiv->otg->state));
515 }
516
517 /*
518 * When returning to A state after HNP, avoid hub_port_rebounce(),
519 * which cause occasional OPT A "Did not receive reset after connect"
520 * errors.
521 */
522 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
523}
524
525static void musb_recover_from_babble(struct musb *musb);
526
527/*
528 * Interrupt Service Routine to record USB "global" interrupts.
529 * Since these do not happen often and signify things of
530 * paramount importance, it seems OK to check them individually;
531 * the order of the tests is specified in the manual
532 *
533 * @param musb instance pointer
534 * @param int_usb register contents
535 * @param devctl
536 * @param power
537 */
538
539static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
540 u8 devctl)
541{
542 irqreturn_t handled = IRQ_NONE;
543
544 dev_dbg(musb->controller, "<== DevCtl=%02x, int_usb=0x%x\n", devctl,
545 int_usb);
546
547 /* in host mode, the peripheral may issue remote wakeup.
548 * in peripheral mode, the host may resume the link.
549 * spurious RESUME irqs happen too, paired with SUSPEND.
550 */
551 if (int_usb & MUSB_INTR_RESUME) {
552 handled = IRQ_HANDLED;
553 dev_dbg(musb->controller, "RESUME (%s)\n",
554 usb_otg_state_string(musb->xceiv->otg->state));
555
556 if (devctl & MUSB_DEVCTL_HM) {
557 switch (musb->xceiv->otg->state) {
558 case OTG_STATE_A_SUSPEND:
559 /* remote wakeup? later, GetPortStatus
560 * will stop RESUME signaling
561 */
562
563 musb->port1_status |=
564 (USB_PORT_STAT_C_SUSPEND << 16)
565 | MUSB_PORT_STAT_RESUME;
566 musb->rh_timer = jiffies
567 + msecs_to_jiffies(USB_RESUME_TIMEOUT);
568 musb->need_finish_resume = 1;
569
570 musb->xceiv->otg->state = OTG_STATE_A_HOST;
571 musb->is_active = 1;
572 musb_host_resume_root_hub(musb);
573 break;
574 case OTG_STATE_B_WAIT_ACON:
575 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
576 musb->is_active = 1;
577 MUSB_DEV_MODE(musb);
578 break;
579 default:
580 WARNING("bogus %s RESUME (%s)\n",
581 "host",
582 usb_otg_state_string(musb->xceiv->otg->state));
583 }
584 } else {
585 switch (musb->xceiv->otg->state) {
586 case OTG_STATE_A_SUSPEND:
587 /* possibly DISCONNECT is upcoming */
588 musb->xceiv->otg->state = OTG_STATE_A_HOST;
589 musb_host_resume_root_hub(musb);
590 break;
591 case OTG_STATE_B_WAIT_ACON:
592 case OTG_STATE_B_PERIPHERAL:
593 /* disconnect while suspended? we may
594 * not get a disconnect irq...
595 */
596 if ((devctl & MUSB_DEVCTL_VBUS)
597 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
598 ) {
599 musb->int_usb |= MUSB_INTR_DISCONNECT;
600 musb->int_usb &= ~MUSB_INTR_SUSPEND;
601 break;
602 }
603 musb_g_resume(musb);
604 break;
605 case OTG_STATE_B_IDLE:
606 musb->int_usb &= ~MUSB_INTR_SUSPEND;
607 break;
608 default:
609 WARNING("bogus %s RESUME (%s)\n",
610 "peripheral",
611 usb_otg_state_string(musb->xceiv->otg->state));
612 }
613 }
614 }
615
616 /* see manual for the order of the tests */
617 if (int_usb & MUSB_INTR_SESSREQ) {
618 void __iomem *mbase = musb->mregs;
619
620 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
621 && (devctl & MUSB_DEVCTL_BDEVICE)) {
622 dev_dbg(musb->controller, "SessReq while on B state\n");
623 return IRQ_HANDLED;
624 }
625
626 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n",
627 usb_otg_state_string(musb->xceiv->otg->state));
628
629 /* IRQ arrives from ID pin sense or (later, if VBUS power
630 * is removed) SRP. responses are time critical:
631 * - turn on VBUS (with silicon-specific mechanism)
632 * - go through A_WAIT_VRISE
633 * - ... to A_WAIT_BCON.
634 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
635 */
636 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
637 musb->ep0_stage = MUSB_EP0_START;
638 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
639 MUSB_HST_MODE(musb);
640 musb_platform_set_vbus(musb, 1);
641
642 handled = IRQ_HANDLED;
643 }
644
645 if (int_usb & MUSB_INTR_VBUSERROR) {
646 int ignore = 0;
647
648 /* During connection as an A-Device, we may see a short
649 * current spikes causing voltage drop, because of cable
650 * and peripheral capacitance combined with vbus draw.
651 * (So: less common with truly self-powered devices, where
652 * vbus doesn't act like a power supply.)
653 *
654 * Such spikes are short; usually less than ~500 usec, max
655 * of ~2 msec. That is, they're not sustained overcurrent
656 * errors, though they're reported using VBUSERROR irqs.
657 *
658 * Workarounds: (a) hardware: use self powered devices.
659 * (b) software: ignore non-repeated VBUS errors.
660 *
661 * REVISIT: do delays from lots of DEBUG_KERNEL checks
662 * make trouble here, keeping VBUS < 4.4V ?
663 */
664 switch (musb->xceiv->otg->state) {
665 case OTG_STATE_A_HOST:
666 /* recovery is dicey once we've gotten past the
667 * initial stages of enumeration, but if VBUS
668 * stayed ok at the other end of the link, and
669 * another reset is due (at least for high speed,
670 * to redo the chirp etc), it might work OK...
671 */
672 case OTG_STATE_A_WAIT_BCON:
673 case OTG_STATE_A_WAIT_VRISE:
674 if (musb->vbuserr_retry) {
675 void __iomem *mbase = musb->mregs;
676
677 musb->vbuserr_retry--;
678 ignore = 1;
679 devctl |= MUSB_DEVCTL_SESSION;
680 musb_writeb(mbase, MUSB_DEVCTL, devctl);
681 } else {
682 musb->port1_status |=
683 USB_PORT_STAT_OVERCURRENT
684 | (USB_PORT_STAT_C_OVERCURRENT << 16);
685 }
686 break;
687 default:
688 break;
689 }
690
691 dev_printk(ignore ? KERN_DEBUG : KERN_ERR, musb->controller,
692 "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
693 usb_otg_state_string(musb->xceiv->otg->state),
694 devctl,
695 ({ char *s;
696 switch (devctl & MUSB_DEVCTL_VBUS) {
697 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
698 s = "<SessEnd"; break;
699 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
700 s = "<AValid"; break;
701 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
702 s = "<VBusValid"; break;
703 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
704 default:
705 s = "VALID"; break;
706 } s; }),
707 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
708 musb->port1_status);
709
710 /* go through A_WAIT_VFALL then start a new session */
711 if (!ignore)
712 musb_platform_set_vbus(musb, 0);
713 handled = IRQ_HANDLED;
714 }
715
716 if (int_usb & MUSB_INTR_SUSPEND) {
717 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x\n",
718 usb_otg_state_string(musb->xceiv->otg->state), devctl);
719 handled = IRQ_HANDLED;
720
721 switch (musb->xceiv->otg->state) {
722 case OTG_STATE_A_PERIPHERAL:
723 /* We also come here if the cable is removed, since
724 * this silicon doesn't report ID-no-longer-grounded.
725 *
726 * We depend on T(a_wait_bcon) to shut us down, and
727 * hope users don't do anything dicey during this
728 * undesired detour through A_WAIT_BCON.
729 */
730 musb_hnp_stop(musb);
731 musb_host_resume_root_hub(musb);
732 musb_root_disconnect(musb);
733 musb_platform_try_idle(musb, jiffies
734 + msecs_to_jiffies(musb->a_wait_bcon
735 ? : OTG_TIME_A_WAIT_BCON));
736
737 break;
738 case OTG_STATE_B_IDLE:
739 if (!musb->is_active)
740 break;
741 case OTG_STATE_B_PERIPHERAL:
742 musb_g_suspend(musb);
743 musb->is_active = musb->g.b_hnp_enable;
744 if (musb->is_active) {
745 musb->xceiv->otg->state = OTG_STATE_B_WAIT_ACON;
746 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
747 mod_timer(&musb->otg_timer, jiffies
748 + msecs_to_jiffies(
749 OTG_TIME_B_ASE0_BRST));
750 }
751 break;
752 case OTG_STATE_A_WAIT_BCON:
753 if (musb->a_wait_bcon != 0)
754 musb_platform_try_idle(musb, jiffies
755 + msecs_to_jiffies(musb->a_wait_bcon));
756 break;
757 case OTG_STATE_A_HOST:
758 musb->xceiv->otg->state = OTG_STATE_A_SUSPEND;
759 musb->is_active = musb->hcd->self.b_hnp_enable;
760 break;
761 case OTG_STATE_B_HOST:
762 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
763 dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n");
764 break;
765 default:
766 /* "should not happen" */
767 musb->is_active = 0;
768 break;
769 }
770 }
771
772 if (int_usb & MUSB_INTR_CONNECT) {
773 struct usb_hcd *hcd = musb->hcd;
774
775 handled = IRQ_HANDLED;
776 musb->is_active = 1;
777
778 musb->ep0_stage = MUSB_EP0_START;
779
780 musb->intrtxe = musb->epmask;
781 musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe);
782 musb->intrrxe = musb->epmask & 0xfffe;
783 musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe);
784 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
785 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
786 |USB_PORT_STAT_HIGH_SPEED
787 |USB_PORT_STAT_ENABLE
788 );
789 musb->port1_status |= USB_PORT_STAT_CONNECTION
790 |(USB_PORT_STAT_C_CONNECTION << 16);
791
792 /* high vs full speed is just a guess until after reset */
793 if (devctl & MUSB_DEVCTL_LSDEV)
794 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
795
796 /* indicate new connection to OTG machine */
797 switch (musb->xceiv->otg->state) {
798 case OTG_STATE_B_PERIPHERAL:
799 if (int_usb & MUSB_INTR_SUSPEND) {
800 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
801 int_usb &= ~MUSB_INTR_SUSPEND;
802 goto b_host;
803 } else
804 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
805 break;
806 case OTG_STATE_B_WAIT_ACON:
807 dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n");
808b_host:
809 musb->xceiv->otg->state = OTG_STATE_B_HOST;
810 if (musb->hcd)
811 musb->hcd->self.is_b_host = 1;
812 del_timer(&musb->otg_timer);
813 break;
814 default:
815 if ((devctl & MUSB_DEVCTL_VBUS)
816 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
817 musb->xceiv->otg->state = OTG_STATE_A_HOST;
818 if (hcd)
819 hcd->self.is_b_host = 0;
820 }
821 break;
822 }
823
824 musb_host_poke_root_hub(musb);
825
826 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",
827 usb_otg_state_string(musb->xceiv->otg->state), devctl);
828 }
829
830 if (int_usb & MUSB_INTR_DISCONNECT) {
831 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n",
832 usb_otg_state_string(musb->xceiv->otg->state),
833 MUSB_MODE(musb), devctl);
834 handled = IRQ_HANDLED;
835
836 switch (musb->xceiv->otg->state) {
837 case OTG_STATE_A_HOST:
838 case OTG_STATE_A_SUSPEND:
839 musb_host_resume_root_hub(musb);
840 musb_root_disconnect(musb);
841 if (musb->a_wait_bcon != 0)
842 musb_platform_try_idle(musb, jiffies
843 + msecs_to_jiffies(musb->a_wait_bcon));
844 break;
845 case OTG_STATE_B_HOST:
846 /* REVISIT this behaves for "real disconnect"
847 * cases; make sure the other transitions from
848 * from B_HOST act right too. The B_HOST code
849 * in hnp_stop() is currently not used...
850 */
851 musb_root_disconnect(musb);
852 if (musb->hcd)
853 musb->hcd->self.is_b_host = 0;
854 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
855 MUSB_DEV_MODE(musb);
856 musb_g_disconnect(musb);
857 break;
858 case OTG_STATE_A_PERIPHERAL:
859 musb_hnp_stop(musb);
860 musb_root_disconnect(musb);
861 /* FALLTHROUGH */
862 case OTG_STATE_B_WAIT_ACON:
863 /* FALLTHROUGH */
864 case OTG_STATE_B_PERIPHERAL:
865 case OTG_STATE_B_IDLE:
866 musb_g_disconnect(musb);
867 break;
868 default:
869 WARNING("unhandled DISCONNECT transition (%s)\n",
870 usb_otg_state_string(musb->xceiv->otg->state));
871 break;
872 }
873 }
874
875 /* mentor saves a bit: bus reset and babble share the same irq.
876 * only host sees babble; only peripheral sees bus reset.
877 */
878 if (int_usb & MUSB_INTR_RESET) {
879 handled = IRQ_HANDLED;
880 if (devctl & MUSB_DEVCTL_HM) {
881 /*
882 * When BABBLE happens what we can depends on which
883 * platform MUSB is running, because some platforms
884 * implemented proprietary means for 'recovering' from
885 * Babble conditions. One such platform is AM335x. In
886 * most cases, however, the only thing we can do is
887 * drop the session.
888 */
889 dev_err(musb->controller, "Babble\n");
890
891 if (is_host_active(musb))
892 musb_recover_from_babble(musb);
893 } else {
894 dev_dbg(musb->controller, "BUS RESET as %s\n",
895 usb_otg_state_string(musb->xceiv->otg->state));
896 switch (musb->xceiv->otg->state) {
897 case OTG_STATE_A_SUSPEND:
898 musb_g_reset(musb);
899 /* FALLTHROUGH */
900 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
901 /* never use invalid T(a_wait_bcon) */
902 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n",
903 usb_otg_state_string(musb->xceiv->otg->state),
904 TA_WAIT_BCON(musb));
905 mod_timer(&musb->otg_timer, jiffies
906 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
907 break;
908 case OTG_STATE_A_PERIPHERAL:
909 del_timer(&musb->otg_timer);
910 musb_g_reset(musb);
911 break;
912 case OTG_STATE_B_WAIT_ACON:
913 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",
914 usb_otg_state_string(musb->xceiv->otg->state));
915 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
916 musb_g_reset(musb);
917 break;
918 case OTG_STATE_B_IDLE:
919 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
920 /* FALLTHROUGH */
921 case OTG_STATE_B_PERIPHERAL:
922 musb_g_reset(musb);
923 break;
924 default:
925 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n",
926 usb_otg_state_string(musb->xceiv->otg->state));
927 }
928 }
929 }
930
931#if 0
932/* REVISIT ... this would be for multiplexing periodic endpoints, or
933 * supporting transfer phasing to prevent exceeding ISO bandwidth
934 * limits of a given frame or microframe.
935 *
936 * It's not needed for peripheral side, which dedicates endpoints;
937 * though it _might_ use SOF irqs for other purposes.
938 *
939 * And it's not currently needed for host side, which also dedicates
940 * endpoints, relies on TX/RX interval registers, and isn't claimed
941 * to support ISO transfers yet.
942 */
943 if (int_usb & MUSB_INTR_SOF) {
944 void __iomem *mbase = musb->mregs;
945 struct musb_hw_ep *ep;
946 u8 epnum;
947 u16 frame;
948
949 dev_dbg(musb->controller, "START_OF_FRAME\n");
950 handled = IRQ_HANDLED;
951
952 /* start any periodic Tx transfers waiting for current frame */
953 frame = musb_readw(mbase, MUSB_FRAME);
954 ep = musb->endpoints;
955 for (epnum = 1; (epnum < musb->nr_endpoints)
956 && (musb->epmask >= (1 << epnum));
957 epnum++, ep++) {
958 /*
959 * FIXME handle framecounter wraps (12 bits)
960 * eliminate duplicated StartUrb logic
961 */
962 if (ep->dwWaitFrame >= frame) {
963 ep->dwWaitFrame = 0;
964 pr_debug("SOF --> periodic TX%s on %d\n",
965 ep->tx_channel ? " DMA" : "",
966 epnum);
967 if (!ep->tx_channel)
968 musb_h_tx_start(musb, epnum);
969 else
970 cppi_hostdma_start(musb, epnum);
971 }
972 } /* end of for loop */
973 }
974#endif
975
976 schedule_work(&musb->irq_work);
977
978 return handled;
979}
980
981/*-------------------------------------------------------------------------*/
982
983static void musb_disable_interrupts(struct musb *musb)
984{
985 void __iomem *mbase = musb->mregs;
986 u16 temp;
987
988 /* disable interrupts */
989 musb_writeb(mbase, MUSB_INTRUSBE, 0);
990 musb->intrtxe = 0;
991 musb_writew(mbase, MUSB_INTRTXE, 0);
992 musb->intrrxe = 0;
993 musb_writew(mbase, MUSB_INTRRXE, 0);
994
995 /* flush pending interrupts */
996 temp = musb_readb(mbase, MUSB_INTRUSB);
997 temp = musb_readw(mbase, MUSB_INTRTX);
998 temp = musb_readw(mbase, MUSB_INTRRX);
999}
1000
1001static void musb_enable_interrupts(struct musb *musb)
1002{
1003 void __iomem *regs = musb->mregs;
1004
1005 /* Set INT enable registers, enable interrupts */
1006 musb->intrtxe = musb->epmask;
1007 musb_writew(regs, MUSB_INTRTXE, musb->intrtxe);
1008 musb->intrrxe = musb->epmask & 0xfffe;
1009 musb_writew(regs, MUSB_INTRRXE, musb->intrrxe);
1010 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
1011
1012}
1013
1014static void musb_generic_disable(struct musb *musb)
1015{
1016 void __iomem *mbase = musb->mregs;
1017
1018 musb_disable_interrupts(musb);
1019
1020 /* off */
1021 musb_writeb(mbase, MUSB_DEVCTL, 0);
1022}
1023
1024/*
1025 * Program the HDRC to start (enable interrupts, dma, etc.).
1026 */
1027void musb_start(struct musb *musb)
1028{
1029 void __iomem *regs = musb->mregs;
1030 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
1031 u8 power;
1032
1033 dev_dbg(musb->controller, "<== devctl %02x\n", devctl);
1034
1035 musb_enable_interrupts(musb);
1036 musb_writeb(regs, MUSB_TESTMODE, 0);
1037
1038 power = MUSB_POWER_ISOUPDATE;
1039 /*
1040 * treating UNKNOWN as unspecified maximum speed, in which case
1041 * we will default to high-speed.
1042 */
1043 if (musb->config->maximum_speed == USB_SPEED_HIGH ||
1044 musb->config->maximum_speed == USB_SPEED_UNKNOWN)
1045 power |= MUSB_POWER_HSENAB;
1046 musb_writeb(regs, MUSB_POWER, power);
1047
1048 musb->is_active = 0;
1049 devctl = musb_readb(regs, MUSB_DEVCTL);
1050 devctl &= ~MUSB_DEVCTL_SESSION;
1051
1052 /* session started after:
1053 * (a) ID-grounded irq, host mode;
1054 * (b) vbus present/connect IRQ, peripheral mode;
1055 * (c) peripheral initiates, using SRP
1056 */
1057 if (musb->port_mode != MUSB_PORT_MODE_HOST &&
1058 musb->xceiv->otg->state != OTG_STATE_A_WAIT_BCON &&
1059 (devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) {
1060 musb->is_active = 1;
1061 } else {
1062 devctl |= MUSB_DEVCTL_SESSION;
1063 }
1064
1065 musb_platform_enable(musb);
1066 musb_writeb(regs, MUSB_DEVCTL, devctl);
1067}
1068
1069/*
1070 * Make the HDRC stop (disable interrupts, etc.);
1071 * reversible by musb_start
1072 * called on gadget driver unregister
1073 * with controller locked, irqs blocked
1074 * acts as a NOP unless some role activated the hardware
1075 */
1076void musb_stop(struct musb *musb)
1077{
1078 /* stop IRQs, timers, ... */
1079 musb_platform_disable(musb);
1080 musb_generic_disable(musb);
1081 dev_dbg(musb->controller, "HDRC disabled\n");
1082
1083 /* FIXME
1084 * - mark host and/or peripheral drivers unusable/inactive
1085 * - disable DMA (and enable it in HdrcStart)
1086 * - make sure we can musb_start() after musb_stop(); with
1087 * OTG mode, gadget driver module rmmod/modprobe cycles that
1088 * - ...
1089 */
1090 musb_platform_try_idle(musb, 0);
1091}
1092
1093static void musb_shutdown(struct platform_device *pdev)
1094{
1095 struct musb *musb = dev_to_musb(&pdev->dev);
1096 unsigned long flags;
1097
1098 pm_runtime_get_sync(musb->controller);
1099
1100 musb_host_cleanup(musb);
1101 musb_gadget_cleanup(musb);
1102
1103 spin_lock_irqsave(&musb->lock, flags);
1104 musb_platform_disable(musb);
1105 musb_generic_disable(musb);
1106 spin_unlock_irqrestore(&musb->lock, flags);
1107
1108 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1109 musb_platform_exit(musb);
1110
1111 pm_runtime_put(musb->controller);
1112 /* FIXME power down */
1113}
1114
1115
1116/*-------------------------------------------------------------------------*/
1117
1118/*
1119 * The silicon either has hard-wired endpoint configurations, or else
1120 * "dynamic fifo" sizing. The driver has support for both, though at this
1121 * writing only the dynamic sizing is very well tested. Since we switched
1122 * away from compile-time hardware parameters, we can no longer rely on
1123 * dead code elimination to leave only the relevant one in the object file.
1124 *
1125 * We don't currently use dynamic fifo setup capability to do anything
1126 * more than selecting one of a bunch of predefined configurations.
1127 */
1128static ushort fifo_mode;
1129
1130/* "modprobe ... fifo_mode=1" etc */
1131module_param(fifo_mode, ushort, 0);
1132MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1133
1134/*
1135 * tables defining fifo_mode values. define more if you like.
1136 * for host side, make sure both halves of ep1 are set up.
1137 */
1138
1139/* mode 0 - fits in 2KB */
1140static struct musb_fifo_cfg mode_0_cfg[] = {
1141{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1142{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1143{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1144{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1145{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1146};
1147
1148/* mode 1 - fits in 4KB */
1149static struct musb_fifo_cfg mode_1_cfg[] = {
1150{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1151{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1152{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1153{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1154{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1155};
1156
1157/* mode 2 - fits in 4KB */
1158static struct musb_fifo_cfg mode_2_cfg[] = {
1159{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1160{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1161{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1162{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1163{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1164{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1165};
1166
1167/* mode 3 - fits in 4KB */
1168static struct musb_fifo_cfg mode_3_cfg[] = {
1169{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1170{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1171{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1172{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1173{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1174{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1175};
1176
1177/* mode 4 - fits in 16KB */
1178static struct musb_fifo_cfg mode_4_cfg[] = {
1179{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1180{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1181{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1182{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1183{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1184{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1185{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1186{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1187{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1188{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1189{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1190{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1191{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1192{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1193{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1194{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1195{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1196{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1197{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1198{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1199{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1200{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1201{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1202{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1203{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1204{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1205{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1206};
1207
1208/* mode 5 - fits in 8KB */
1209static struct musb_fifo_cfg mode_5_cfg[] = {
1210{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1211{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1212{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1213{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1214{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1215{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1216{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1217{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1218{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1219{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1220{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1221{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1222{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1223{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1224{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1225{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1226{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1227{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1228{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1229{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1230{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1231{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1232{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1233{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1234{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1235{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1236{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1237};
1238
1239/*
1240 * configure a fifo; for non-shared endpoints, this may be called
1241 * once for a tx fifo and once for an rx fifo.
1242 *
1243 * returns negative errno or offset for next fifo.
1244 */
1245static int
1246fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1247 const struct musb_fifo_cfg *cfg, u16 offset)
1248{
1249 void __iomem *mbase = musb->mregs;
1250 int size = 0;
1251 u16 maxpacket = cfg->maxpacket;
1252 u16 c_off = offset >> 3;
1253 u8 c_size;
1254
1255 /* expect hw_ep has already been zero-initialized */
1256
1257 size = ffs(max(maxpacket, (u16) 8)) - 1;
1258 maxpacket = 1 << size;
1259
1260 c_size = size - 3;
1261 if (cfg->mode == BUF_DOUBLE) {
1262 if ((offset + (maxpacket << 1)) >
1263 (1 << (musb->config->ram_bits + 2)))
1264 return -EMSGSIZE;
1265 c_size |= MUSB_FIFOSZ_DPB;
1266 } else {
1267 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1268 return -EMSGSIZE;
1269 }
1270
1271 /* configure the FIFO */
1272 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1273
1274 /* EP0 reserved endpoint for control, bidirectional;
1275 * EP1 reserved for bulk, two unidirectional halves.
1276 */
1277 if (hw_ep->epnum == 1)
1278 musb->bulk_ep = hw_ep;
1279 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1280 switch (cfg->style) {
1281 case FIFO_TX:
1282 musb_write_txfifosz(mbase, c_size);
1283 musb_write_txfifoadd(mbase, c_off);
1284 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1285 hw_ep->max_packet_sz_tx = maxpacket;
1286 break;
1287 case FIFO_RX:
1288 musb_write_rxfifosz(mbase, c_size);
1289 musb_write_rxfifoadd(mbase, c_off);
1290 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1291 hw_ep->max_packet_sz_rx = maxpacket;
1292 break;
1293 case FIFO_RXTX:
1294 musb_write_txfifosz(mbase, c_size);
1295 musb_write_txfifoadd(mbase, c_off);
1296 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1297 hw_ep->max_packet_sz_rx = maxpacket;
1298
1299 musb_write_rxfifosz(mbase, c_size);
1300 musb_write_rxfifoadd(mbase, c_off);
1301 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1302 hw_ep->max_packet_sz_tx = maxpacket;
1303
1304 hw_ep->is_shared_fifo = true;
1305 break;
1306 }
1307
1308 /* NOTE rx and tx endpoint irqs aren't managed separately,
1309 * which happens to be ok
1310 */
1311 musb->epmask |= (1 << hw_ep->epnum);
1312
1313 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1314}
1315
1316static struct musb_fifo_cfg ep0_cfg = {
1317 .style = FIFO_RXTX, .maxpacket = 64,
1318};
1319
1320static int ep_config_from_table(struct musb *musb)
1321{
1322 const struct musb_fifo_cfg *cfg;
1323 unsigned i, n;
1324 int offset;
1325 struct musb_hw_ep *hw_ep = musb->endpoints;
1326
1327 if (musb->config->fifo_cfg) {
1328 cfg = musb->config->fifo_cfg;
1329 n = musb->config->fifo_cfg_size;
1330 goto done;
1331 }
1332
1333 switch (fifo_mode) {
1334 default:
1335 fifo_mode = 0;
1336 /* FALLTHROUGH */
1337 case 0:
1338 cfg = mode_0_cfg;
1339 n = ARRAY_SIZE(mode_0_cfg);
1340 break;
1341 case 1:
1342 cfg = mode_1_cfg;
1343 n = ARRAY_SIZE(mode_1_cfg);
1344 break;
1345 case 2:
1346 cfg = mode_2_cfg;
1347 n = ARRAY_SIZE(mode_2_cfg);
1348 break;
1349 case 3:
1350 cfg = mode_3_cfg;
1351 n = ARRAY_SIZE(mode_3_cfg);
1352 break;
1353 case 4:
1354 cfg = mode_4_cfg;
1355 n = ARRAY_SIZE(mode_4_cfg);
1356 break;
1357 case 5:
1358 cfg = mode_5_cfg;
1359 n = ARRAY_SIZE(mode_5_cfg);
1360 break;
1361 }
1362
1363 pr_debug("%s: setup fifo_mode %d\n", musb_driver_name, fifo_mode);
1364
1365
1366done:
1367 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1368 /* assert(offset > 0) */
1369
1370 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1371 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1372 */
1373
1374 for (i = 0; i < n; i++) {
1375 u8 epn = cfg->hw_ep_num;
1376
1377 if (epn >= musb->config->num_eps) {
1378 pr_debug("%s: invalid ep %d\n",
1379 musb_driver_name, epn);
1380 return -EINVAL;
1381 }
1382 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1383 if (offset < 0) {
1384 pr_debug("%s: mem overrun, ep %d\n",
1385 musb_driver_name, epn);
1386 return offset;
1387 }
1388 epn++;
1389 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1390 }
1391
1392 pr_debug("%s: %d/%d max ep, %d/%d memory\n",
1393 musb_driver_name,
1394 n + 1, musb->config->num_eps * 2 - 1,
1395 offset, (1 << (musb->config->ram_bits + 2)));
1396
1397 if (!musb->bulk_ep) {
1398 pr_debug("%s: missing bulk\n", musb_driver_name);
1399 return -EINVAL;
1400 }
1401
1402 return 0;
1403}
1404
1405
1406/*
1407 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1408 * @param musb the controller
1409 */
1410static int ep_config_from_hw(struct musb *musb)
1411{
1412 u8 epnum = 0;
1413 struct musb_hw_ep *hw_ep;
1414 void __iomem *mbase = musb->mregs;
1415 int ret = 0;
1416
1417 dev_dbg(musb->controller, "<== static silicon ep config\n");
1418
1419 /* FIXME pick up ep0 maxpacket size */
1420
1421 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1422 musb_ep_select(mbase, epnum);
1423 hw_ep = musb->endpoints + epnum;
1424
1425 ret = musb_read_fifosize(musb, hw_ep, epnum);
1426 if (ret < 0)
1427 break;
1428
1429 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1430
1431 /* pick an RX/TX endpoint for bulk */
1432 if (hw_ep->max_packet_sz_tx < 512
1433 || hw_ep->max_packet_sz_rx < 512)
1434 continue;
1435
1436 /* REVISIT: this algorithm is lazy, we should at least
1437 * try to pick a double buffered endpoint.
1438 */
1439 if (musb->bulk_ep)
1440 continue;
1441 musb->bulk_ep = hw_ep;
1442 }
1443
1444 if (!musb->bulk_ep) {
1445 pr_debug("%s: missing bulk\n", musb_driver_name);
1446 return -EINVAL;
1447 }
1448
1449 return 0;
1450}
1451
1452enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1453
1454/* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1455 * configure endpoints, or take their config from silicon
1456 */
1457static int musb_core_init(u16 musb_type, struct musb *musb)
1458{
1459 u8 reg;
1460 char *type;
1461 char aInfo[90], aRevision[32], aDate[12];
1462 void __iomem *mbase = musb->mregs;
1463 int status = 0;
1464 int i;
1465
1466 /* log core options (read using indexed model) */
1467 reg = musb_read_configdata(mbase);
1468
1469 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1470 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1471 strcat(aInfo, ", dyn FIFOs");
1472 musb->dyn_fifo = true;
1473 }
1474 if (reg & MUSB_CONFIGDATA_MPRXE) {
1475 strcat(aInfo, ", bulk combine");
1476 musb->bulk_combine = true;
1477 }
1478 if (reg & MUSB_CONFIGDATA_MPTXE) {
1479 strcat(aInfo, ", bulk split");
1480 musb->bulk_split = true;
1481 }
1482 if (reg & MUSB_CONFIGDATA_HBRXE) {
1483 strcat(aInfo, ", HB-ISO Rx");
1484 musb->hb_iso_rx = true;
1485 }
1486 if (reg & MUSB_CONFIGDATA_HBTXE) {
1487 strcat(aInfo, ", HB-ISO Tx");
1488 musb->hb_iso_tx = true;
1489 }
1490 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1491 strcat(aInfo, ", SoftConn");
1492
1493 pr_debug("%s: ConfigData=0x%02x (%s)\n", musb_driver_name, reg, aInfo);
1494
1495 aDate[0] = 0;
1496 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1497 musb->is_multipoint = 1;
1498 type = "M";
1499 } else {
1500 musb->is_multipoint = 0;
1501 type = "";
1502#ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1503 pr_err("%s: kernel must blacklist external hubs\n",
1504 musb_driver_name);
1505#endif
1506 }
1507
1508 /* log release info */
1509 musb->hwvers = musb_read_hwvers(mbase);
1510 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1511 MUSB_HWVERS_MINOR(musb->hwvers),
1512 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1513 pr_debug("%s: %sHDRC RTL version %s %s\n",
1514 musb_driver_name, type, aRevision, aDate);
1515
1516 /* configure ep0 */
1517 musb_configure_ep0(musb);
1518
1519 /* discover endpoint configuration */
1520 musb->nr_endpoints = 1;
1521 musb->epmask = 1;
1522
1523 if (musb->dyn_fifo)
1524 status = ep_config_from_table(musb);
1525 else
1526 status = ep_config_from_hw(musb);
1527
1528 if (status < 0)
1529 return status;
1530
1531 /* finish init, and print endpoint config */
1532 for (i = 0; i < musb->nr_endpoints; i++) {
1533 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1534
1535 hw_ep->fifo = musb->io.fifo_offset(i) + mbase;
1536#if IS_ENABLED(CONFIG_USB_MUSB_TUSB6010)
1537 if (musb->io.quirks & MUSB_IN_TUSB) {
1538 hw_ep->fifo_async = musb->async + 0x400 +
1539 musb->io.fifo_offset(i);
1540 hw_ep->fifo_sync = musb->sync + 0x400 +
1541 musb->io.fifo_offset(i);
1542 hw_ep->fifo_sync_va =
1543 musb->sync_va + 0x400 + musb->io.fifo_offset(i);
1544
1545 if (i == 0)
1546 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1547 else
1548 hw_ep->conf = mbase + 0x400 +
1549 (((i - 1) & 0xf) << 2);
1550 }
1551#endif
1552
1553 hw_ep->regs = musb->io.ep_offset(i, 0) + mbase;
1554 hw_ep->rx_reinit = 1;
1555 hw_ep->tx_reinit = 1;
1556
1557 if (hw_ep->max_packet_sz_tx) {
1558 dev_dbg(musb->controller,
1559 "%s: hw_ep %d%s, %smax %d\n",
1560 musb_driver_name, i,
1561 hw_ep->is_shared_fifo ? "shared" : "tx",
1562 hw_ep->tx_double_buffered
1563 ? "doublebuffer, " : "",
1564 hw_ep->max_packet_sz_tx);
1565 }
1566 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1567 dev_dbg(musb->controller,
1568 "%s: hw_ep %d%s, %smax %d\n",
1569 musb_driver_name, i,
1570 "rx",
1571 hw_ep->rx_double_buffered
1572 ? "doublebuffer, " : "",
1573 hw_ep->max_packet_sz_rx);
1574 }
1575 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1576 dev_dbg(musb->controller, "hw_ep %d not configured\n", i);
1577 }
1578
1579 return 0;
1580}
1581
1582/*-------------------------------------------------------------------------*/
1583
1584/*
1585 * handle all the irqs defined by the HDRC core. for now we expect: other
1586 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1587 * will be assigned, and the irq will already have been acked.
1588 *
1589 * called in irq context with spinlock held, irqs blocked
1590 */
1591irqreturn_t musb_interrupt(struct musb *musb)
1592{
1593 irqreturn_t retval = IRQ_NONE;
1594 unsigned long status;
1595 unsigned long epnum;
1596 u8 devctl;
1597
1598 if (!musb->int_usb && !musb->int_tx && !musb->int_rx)
1599 return IRQ_NONE;
1600
1601 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1602
1603 dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n",
1604 is_host_active(musb) ? "host" : "peripheral",
1605 musb->int_usb, musb->int_tx, musb->int_rx);
1606
1607 /**
1608 * According to Mentor Graphics' documentation, flowchart on page 98,
1609 * IRQ should be handled as follows:
1610 *
1611 * . Resume IRQ
1612 * . Session Request IRQ
1613 * . VBUS Error IRQ
1614 * . Suspend IRQ
1615 * . Connect IRQ
1616 * . Disconnect IRQ
1617 * . Reset/Babble IRQ
1618 * . SOF IRQ (we're not using this one)
1619 * . Endpoint 0 IRQ
1620 * . TX Endpoints
1621 * . RX Endpoints
1622 *
1623 * We will be following that flowchart in order to avoid any problems
1624 * that might arise with internal Finite State Machine.
1625 */
1626
1627 if (musb->int_usb)
1628 retval |= musb_stage0_irq(musb, musb->int_usb, devctl);
1629
1630 if (musb->int_tx & 1) {
1631 if (is_host_active(musb))
1632 retval |= musb_h_ep0_irq(musb);
1633 else
1634 retval |= musb_g_ep0_irq(musb);
1635
1636 /* we have just handled endpoint 0 IRQ, clear it */
1637 musb->int_tx &= ~BIT(0);
1638 }
1639
1640 status = musb->int_tx;
1641
1642 for_each_set_bit(epnum, &status, 16) {
1643 retval = IRQ_HANDLED;
1644 if (is_host_active(musb))
1645 musb_host_tx(musb, epnum);
1646 else
1647 musb_g_tx(musb, epnum);
1648 }
1649
1650 status = musb->int_rx;
1651
1652 for_each_set_bit(epnum, &status, 16) {
1653 retval = IRQ_HANDLED;
1654 if (is_host_active(musb))
1655 musb_host_rx(musb, epnum);
1656 else
1657 musb_g_rx(musb, epnum);
1658 }
1659
1660 return retval;
1661}
1662EXPORT_SYMBOL_GPL(musb_interrupt);
1663
1664#ifndef CONFIG_MUSB_PIO_ONLY
1665static bool use_dma = 1;
1666
1667/* "modprobe ... use_dma=0" etc */
1668module_param(use_dma, bool, 0644);
1669MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1670
1671void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1672{
1673 /* called with controller lock already held */
1674
1675 if (!epnum) {
1676 if (!is_cppi_enabled(musb)) {
1677 /* endpoint 0 */
1678 if (is_host_active(musb))
1679 musb_h_ep0_irq(musb);
1680 else
1681 musb_g_ep0_irq(musb);
1682 }
1683 } else {
1684 /* endpoints 1..15 */
1685 if (transmit) {
1686 if (is_host_active(musb))
1687 musb_host_tx(musb, epnum);
1688 else
1689 musb_g_tx(musb, epnum);
1690 } else {
1691 /* receive */
1692 if (is_host_active(musb))
1693 musb_host_rx(musb, epnum);
1694 else
1695 musb_g_rx(musb, epnum);
1696 }
1697 }
1698}
1699EXPORT_SYMBOL_GPL(musb_dma_completion);
1700
1701#else
1702#define use_dma 0
1703#endif
1704
1705static void (*musb_phy_callback)(enum musb_vbus_id_status status);
1706
1707/*
1708 * musb_mailbox - optional phy notifier function
1709 * @status phy state change
1710 *
1711 * Optionally gets called from the USB PHY. Note that the USB PHY must be
1712 * disabled at the point the phy_callback is registered or unregistered.
1713 */
1714void musb_mailbox(enum musb_vbus_id_status status)
1715{
1716 if (musb_phy_callback)
1717 musb_phy_callback(status);
1718
1719};
1720EXPORT_SYMBOL_GPL(musb_mailbox);
1721
1722/*-------------------------------------------------------------------------*/
1723
1724static ssize_t
1725musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1726{
1727 struct musb *musb = dev_to_musb(dev);
1728 unsigned long flags;
1729 int ret = -EINVAL;
1730
1731 spin_lock_irqsave(&musb->lock, flags);
1732 ret = sprintf(buf, "%s\n", usb_otg_state_string(musb->xceiv->otg->state));
1733 spin_unlock_irqrestore(&musb->lock, flags);
1734
1735 return ret;
1736}
1737
1738static ssize_t
1739musb_mode_store(struct device *dev, struct device_attribute *attr,
1740 const char *buf, size_t n)
1741{
1742 struct musb *musb = dev_to_musb(dev);
1743 unsigned long flags;
1744 int status;
1745
1746 spin_lock_irqsave(&musb->lock, flags);
1747 if (sysfs_streq(buf, "host"))
1748 status = musb_platform_set_mode(musb, MUSB_HOST);
1749 else if (sysfs_streq(buf, "peripheral"))
1750 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1751 else if (sysfs_streq(buf, "otg"))
1752 status = musb_platform_set_mode(musb, MUSB_OTG);
1753 else
1754 status = -EINVAL;
1755 spin_unlock_irqrestore(&musb->lock, flags);
1756
1757 return (status == 0) ? n : status;
1758}
1759static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1760
1761static ssize_t
1762musb_vbus_store(struct device *dev, struct device_attribute *attr,
1763 const char *buf, size_t n)
1764{
1765 struct musb *musb = dev_to_musb(dev);
1766 unsigned long flags;
1767 unsigned long val;
1768
1769 if (sscanf(buf, "%lu", &val) < 1) {
1770 dev_err(dev, "Invalid VBUS timeout ms value\n");
1771 return -EINVAL;
1772 }
1773
1774 spin_lock_irqsave(&musb->lock, flags);
1775 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1776 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1777 if (musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)
1778 musb->is_active = 0;
1779 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1780 spin_unlock_irqrestore(&musb->lock, flags);
1781
1782 return n;
1783}
1784
1785static ssize_t
1786musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1787{
1788 struct musb *musb = dev_to_musb(dev);
1789 unsigned long flags;
1790 unsigned long val;
1791 int vbus;
1792 u8 devctl;
1793
1794 spin_lock_irqsave(&musb->lock, flags);
1795 val = musb->a_wait_bcon;
1796 vbus = musb_platform_get_vbus_status(musb);
1797 if (vbus < 0) {
1798 /* Use default MUSB method by means of DEVCTL register */
1799 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1800 if ((devctl & MUSB_DEVCTL_VBUS)
1801 == (3 << MUSB_DEVCTL_VBUS_SHIFT))
1802 vbus = 1;
1803 else
1804 vbus = 0;
1805 }
1806 spin_unlock_irqrestore(&musb->lock, flags);
1807
1808 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1809 vbus ? "on" : "off", val);
1810}
1811static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1812
1813/* Gadget drivers can't know that a host is connected so they might want
1814 * to start SRP, but users can. This allows userspace to trigger SRP.
1815 */
1816static ssize_t
1817musb_srp_store(struct device *dev, struct device_attribute *attr,
1818 const char *buf, size_t n)
1819{
1820 struct musb *musb = dev_to_musb(dev);
1821 unsigned short srp;
1822
1823 if (sscanf(buf, "%hu", &srp) != 1
1824 || (srp != 1)) {
1825 dev_err(dev, "SRP: Value must be 1\n");
1826 return -EINVAL;
1827 }
1828
1829 if (srp == 1)
1830 musb_g_wakeup(musb);
1831
1832 return n;
1833}
1834static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1835
1836static struct attribute *musb_attributes[] = {
1837 &dev_attr_mode.attr,
1838 &dev_attr_vbus.attr,
1839 &dev_attr_srp.attr,
1840 NULL
1841};
1842
1843static const struct attribute_group musb_attr_group = {
1844 .attrs = musb_attributes,
1845};
1846
1847/* Only used to provide driver mode change events */
1848static void musb_irq_work(struct work_struct *data)
1849{
1850 struct musb *musb = container_of(data, struct musb, irq_work);
1851
1852 if (musb->xceiv->otg->state != musb->xceiv_old_state) {
1853 musb->xceiv_old_state = musb->xceiv->otg->state;
1854 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1855 }
1856}
1857
1858static void musb_recover_from_babble(struct musb *musb)
1859{
1860 int ret;
1861 u8 devctl;
1862
1863 musb_disable_interrupts(musb);
1864
1865 /*
1866 * wait at least 320 cycles of 60MHz clock. That's 5.3us, we will give
1867 * it some slack and wait for 10us.
1868 */
1869 udelay(10);
1870
1871 ret = musb_platform_recover(musb);
1872 if (ret) {
1873 musb_enable_interrupts(musb);
1874 return;
1875 }
1876
1877 /* drop session bit */
1878 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1879 devctl &= ~MUSB_DEVCTL_SESSION;
1880 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
1881
1882 /* tell usbcore about it */
1883 musb_root_disconnect(musb);
1884
1885 /*
1886 * When a babble condition occurs, the musb controller
1887 * removes the session bit and the endpoint config is lost.
1888 */
1889 if (musb->dyn_fifo)
1890 ret = ep_config_from_table(musb);
1891 else
1892 ret = ep_config_from_hw(musb);
1893
1894 /* restart session */
1895 if (ret == 0)
1896 musb_start(musb);
1897}
1898
1899/* --------------------------------------------------------------------------
1900 * Init support
1901 */
1902
1903static struct musb *allocate_instance(struct device *dev,
1904 const struct musb_hdrc_config *config, void __iomem *mbase)
1905{
1906 struct musb *musb;
1907 struct musb_hw_ep *ep;
1908 int epnum;
1909 int ret;
1910
1911 musb = devm_kzalloc(dev, sizeof(*musb), GFP_KERNEL);
1912 if (!musb)
1913 return NULL;
1914
1915 INIT_LIST_HEAD(&musb->control);
1916 INIT_LIST_HEAD(&musb->in_bulk);
1917 INIT_LIST_HEAD(&musb->out_bulk);
1918
1919 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1920 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
1921 musb->mregs = mbase;
1922 musb->ctrl_base = mbase;
1923 musb->nIrq = -ENODEV;
1924 musb->config = config;
1925 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
1926 for (epnum = 0, ep = musb->endpoints;
1927 epnum < musb->config->num_eps;
1928 epnum++, ep++) {
1929 ep->musb = musb;
1930 ep->epnum = epnum;
1931 }
1932
1933 musb->controller = dev;
1934
1935 ret = musb_host_alloc(musb);
1936 if (ret < 0)
1937 goto err_free;
1938
1939 dev_set_drvdata(dev, musb);
1940
1941 return musb;
1942
1943err_free:
1944 return NULL;
1945}
1946
1947static void musb_free(struct musb *musb)
1948{
1949 /* this has multiple entry modes. it handles fault cleanup after
1950 * probe(), where things may be partially set up, as well as rmmod
1951 * cleanup after everything's been de-activated.
1952 */
1953
1954#ifdef CONFIG_SYSFS
1955 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
1956#endif
1957
1958 if (musb->nIrq >= 0) {
1959 if (musb->irq_wake)
1960 disable_irq_wake(musb->nIrq);
1961 free_irq(musb->nIrq, musb);
1962 }
1963
1964 musb_host_free(musb);
1965}
1966
1967static void musb_deassert_reset(struct work_struct *work)
1968{
1969 struct musb *musb;
1970 unsigned long flags;
1971
1972 musb = container_of(work, struct musb, deassert_reset_work.work);
1973
1974 spin_lock_irqsave(&musb->lock, flags);
1975
1976 if (musb->port1_status & USB_PORT_STAT_RESET)
1977 musb_port_reset(musb, false);
1978
1979 spin_unlock_irqrestore(&musb->lock, flags);
1980}
1981
1982/*
1983 * Perform generic per-controller initialization.
1984 *
1985 * @dev: the controller (already clocked, etc)
1986 * @nIrq: IRQ number
1987 * @ctrl: virtual address of controller registers,
1988 * not yet corrected for platform-specific offsets
1989 */
1990static int
1991musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1992{
1993 int status;
1994 struct musb *musb;
1995 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
1996
1997 /* The driver might handle more features than the board; OK.
1998 * Fail when the board needs a feature that's not enabled.
1999 */
2000 if (!plat) {
2001 dev_dbg(dev, "no platform_data?\n");
2002 status = -ENODEV;
2003 goto fail0;
2004 }
2005
2006 /* allocate */
2007 musb = allocate_instance(dev, plat->config, ctrl);
2008 if (!musb) {
2009 status = -ENOMEM;
2010 goto fail0;
2011 }
2012
2013 spin_lock_init(&musb->lock);
2014 musb->board_set_power = plat->set_power;
2015 musb->min_power = plat->min_power;
2016 musb->ops = plat->platform_ops;
2017 musb->port_mode = plat->mode;
2018
2019 /*
2020 * Initialize the default IO functions. At least omap2430 needs
2021 * these early. We initialize the platform specific IO functions
2022 * later on.
2023 */
2024 musb_readb = musb_default_readb;
2025 musb_writeb = musb_default_writeb;
2026 musb_readw = musb_default_readw;
2027 musb_writew = musb_default_writew;
2028 musb_readl = musb_default_readl;
2029 musb_writel = musb_default_writel;
2030
2031 /* We need musb_read/write functions initialized for PM */
2032 pm_runtime_use_autosuspend(musb->controller);
2033 pm_runtime_set_autosuspend_delay(musb->controller, 200);
2034 pm_runtime_enable(musb->controller);
2035
2036 /* The musb_platform_init() call:
2037 * - adjusts musb->mregs
2038 * - sets the musb->isr
2039 * - may initialize an integrated transceiver
2040 * - initializes musb->xceiv, usually by otg_get_phy()
2041 * - stops powering VBUS
2042 *
2043 * There are various transceiver configurations. Blackfin,
2044 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
2045 * external/discrete ones in various flavors (twl4030 family,
2046 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
2047 */
2048 status = musb_platform_init(musb);
2049 if (status < 0)
2050 goto fail1;
2051
2052 if (!musb->isr) {
2053 status = -ENODEV;
2054 goto fail2;
2055 }
2056
2057 if (musb->ops->quirks)
2058 musb->io.quirks = musb->ops->quirks;
2059
2060 /* Most devices use indexed offset or flat offset */
2061 if (musb->io.quirks & MUSB_INDEXED_EP) {
2062 musb->io.ep_offset = musb_indexed_ep_offset;
2063 musb->io.ep_select = musb_indexed_ep_select;
2064 } else {
2065 musb->io.ep_offset = musb_flat_ep_offset;
2066 musb->io.ep_select = musb_flat_ep_select;
2067 }
2068 /* And override them with platform specific ops if specified. */
2069 if (musb->ops->ep_offset)
2070 musb->io.ep_offset = musb->ops->ep_offset;
2071 if (musb->ops->ep_select)
2072 musb->io.ep_select = musb->ops->ep_select;
2073
2074 /* At least tusb6010 has its own offsets */
2075 if (musb->ops->ep_offset)
2076 musb->io.ep_offset = musb->ops->ep_offset;
2077 if (musb->ops->ep_select)
2078 musb->io.ep_select = musb->ops->ep_select;
2079
2080 if (musb->ops->fifo_mode)
2081 fifo_mode = musb->ops->fifo_mode;
2082 else
2083 fifo_mode = 4;
2084
2085 if (musb->ops->fifo_offset)
2086 musb->io.fifo_offset = musb->ops->fifo_offset;
2087 else
2088 musb->io.fifo_offset = musb_default_fifo_offset;
2089
2090 if (musb->ops->busctl_offset)
2091 musb->io.busctl_offset = musb->ops->busctl_offset;
2092 else
2093 musb->io.busctl_offset = musb_default_busctl_offset;
2094
2095 if (musb->ops->readb)
2096 musb_readb = musb->ops->readb;
2097 if (musb->ops->writeb)
2098 musb_writeb = musb->ops->writeb;
2099 if (musb->ops->readw)
2100 musb_readw = musb->ops->readw;
2101 if (musb->ops->writew)
2102 musb_writew = musb->ops->writew;
2103 if (musb->ops->readl)
2104 musb_readl = musb->ops->readl;
2105 if (musb->ops->writel)
2106 musb_writel = musb->ops->writel;
2107
2108#ifndef CONFIG_MUSB_PIO_ONLY
2109 if (!musb->ops->dma_init || !musb->ops->dma_exit) {
2110 dev_err(dev, "DMA controller not set\n");
2111 status = -ENODEV;
2112 goto fail2;
2113 }
2114 musb_dma_controller_create = musb->ops->dma_init;
2115 musb_dma_controller_destroy = musb->ops->dma_exit;
2116#endif
2117
2118 if (musb->ops->read_fifo)
2119 musb->io.read_fifo = musb->ops->read_fifo;
2120 else
2121 musb->io.read_fifo = musb_default_read_fifo;
2122
2123 if (musb->ops->write_fifo)
2124 musb->io.write_fifo = musb->ops->write_fifo;
2125 else
2126 musb->io.write_fifo = musb_default_write_fifo;
2127
2128 if (!musb->xceiv->io_ops) {
2129 musb->xceiv->io_dev = musb->controller;
2130 musb->xceiv->io_priv = musb->mregs;
2131 musb->xceiv->io_ops = &musb_ulpi_access;
2132 }
2133
2134 if (musb->ops->phy_callback)
2135 musb_phy_callback = musb->ops->phy_callback;
2136
2137 pm_runtime_get_sync(musb->controller);
2138
2139 status = usb_phy_init(musb->xceiv);
2140 if (status < 0)
2141 goto err_usb_phy_init;
2142
2143 if (use_dma && dev->dma_mask) {
2144 musb->dma_controller =
2145 musb_dma_controller_create(musb, musb->mregs);
2146 if (IS_ERR(musb->dma_controller)) {
2147 status = PTR_ERR(musb->dma_controller);
2148 goto fail2_5;
2149 }
2150 }
2151
2152 /* be sure interrupts are disabled before connecting ISR */
2153 musb_platform_disable(musb);
2154 musb_generic_disable(musb);
2155
2156 /* Init IRQ workqueue before request_irq */
2157 INIT_WORK(&musb->irq_work, musb_irq_work);
2158 INIT_DELAYED_WORK(&musb->deassert_reset_work, musb_deassert_reset);
2159 INIT_DELAYED_WORK(&musb->finish_resume_work, musb_host_finish_resume);
2160
2161 /* setup musb parts of the core (especially endpoints) */
2162 status = musb_core_init(plat->config->multipoint
2163 ? MUSB_CONTROLLER_MHDRC
2164 : MUSB_CONTROLLER_HDRC, musb);
2165 if (status < 0)
2166 goto fail3;
2167
2168 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
2169
2170 /* attach to the IRQ */
2171 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
2172 dev_err(dev, "request_irq %d failed!\n", nIrq);
2173 status = -ENODEV;
2174 goto fail3;
2175 }
2176 musb->nIrq = nIrq;
2177 /* FIXME this handles wakeup irqs wrong */
2178 if (enable_irq_wake(nIrq) == 0) {
2179 musb->irq_wake = 1;
2180 device_init_wakeup(dev, 1);
2181 } else {
2182 musb->irq_wake = 0;
2183 }
2184
2185 /* program PHY to use external vBus if required */
2186 if (plat->extvbus) {
2187 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
2188 busctl |= MUSB_ULPI_USE_EXTVBUS;
2189 musb_write_ulpi_buscontrol(musb->mregs, busctl);
2190 }
2191
2192 if (musb->xceiv->otg->default_a) {
2193 MUSB_HST_MODE(musb);
2194 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
2195 } else {
2196 MUSB_DEV_MODE(musb);
2197 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
2198 }
2199
2200 switch (musb->port_mode) {
2201 case MUSB_PORT_MODE_HOST:
2202 status = musb_host_setup(musb, plat->power);
2203 if (status < 0)
2204 goto fail3;
2205 status = musb_platform_set_mode(musb, MUSB_HOST);
2206 break;
2207 case MUSB_PORT_MODE_GADGET:
2208 status = musb_gadget_setup(musb);
2209 if (status < 0)
2210 goto fail3;
2211 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
2212 break;
2213 case MUSB_PORT_MODE_DUAL_ROLE:
2214 status = musb_host_setup(musb, plat->power);
2215 if (status < 0)
2216 goto fail3;
2217 status = musb_gadget_setup(musb);
2218 if (status) {
2219 musb_host_cleanup(musb);
2220 goto fail3;
2221 }
2222 status = musb_platform_set_mode(musb, MUSB_OTG);
2223 break;
2224 default:
2225 dev_err(dev, "unsupported port mode %d\n", musb->port_mode);
2226 break;
2227 }
2228
2229 if (status < 0)
2230 goto fail3;
2231
2232 status = musb_init_debugfs(musb);
2233 if (status < 0)
2234 goto fail4;
2235
2236 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
2237 if (status)
2238 goto fail5;
2239
2240 pm_runtime_put(musb->controller);
2241
2242 /*
2243 * For why this is currently needed, see commit 3e43a0725637
2244 * ("usb: musb: core: add pm_runtime_irq_safe()")
2245 */
2246 pm_runtime_irq_safe(musb->controller);
2247
2248 return 0;
2249
2250fail5:
2251 musb_exit_debugfs(musb);
2252
2253fail4:
2254 musb_gadget_cleanup(musb);
2255 musb_host_cleanup(musb);
2256
2257fail3:
2258 cancel_work_sync(&musb->irq_work);
2259 cancel_delayed_work_sync(&musb->finish_resume_work);
2260 cancel_delayed_work_sync(&musb->deassert_reset_work);
2261 if (musb->dma_controller)
2262 musb_dma_controller_destroy(musb->dma_controller);
2263
2264fail2_5:
2265 usb_phy_shutdown(musb->xceiv);
2266
2267err_usb_phy_init:
2268 pm_runtime_put_sync(musb->controller);
2269
2270fail2:
2271 if (musb->irq_wake)
2272 device_init_wakeup(dev, 0);
2273 musb_platform_exit(musb);
2274
2275fail1:
2276 pm_runtime_disable(musb->controller);
2277 dev_err(musb->controller,
2278 "musb_init_controller failed with status %d\n", status);
2279
2280 musb_free(musb);
2281
2282fail0:
2283
2284 return status;
2285
2286}
2287
2288/*-------------------------------------------------------------------------*/
2289
2290/* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2291 * bridge to a platform device; this driver then suffices.
2292 */
2293static int musb_probe(struct platform_device *pdev)
2294{
2295 struct device *dev = &pdev->dev;
2296 int irq = platform_get_irq_byname(pdev, "mc");
2297 struct resource *iomem;
2298 void __iomem *base;
2299
2300 if (irq <= 0)
2301 return -ENODEV;
2302
2303 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2304 base = devm_ioremap_resource(dev, iomem);
2305 if (IS_ERR(base))
2306 return PTR_ERR(base);
2307
2308 return musb_init_controller(dev, irq, base);
2309}
2310
2311static int musb_remove(struct platform_device *pdev)
2312{
2313 struct device *dev = &pdev->dev;
2314 struct musb *musb = dev_to_musb(dev);
2315
2316 /* this gets called on rmmod.
2317 * - Host mode: host may still be active
2318 * - Peripheral mode: peripheral is deactivated (or never-activated)
2319 * - OTG mode: both roles are deactivated (or never-activated)
2320 */
2321 musb_exit_debugfs(musb);
2322 musb_shutdown(pdev);
2323 musb_phy_callback = NULL;
2324
2325 if (musb->dma_controller)
2326 musb_dma_controller_destroy(musb->dma_controller);
2327
2328 usb_phy_shutdown(musb->xceiv);
2329
2330 cancel_work_sync(&musb->irq_work);
2331 cancel_delayed_work_sync(&musb->finish_resume_work);
2332 cancel_delayed_work_sync(&musb->deassert_reset_work);
2333 musb_free(musb);
2334 device_init_wakeup(dev, 0);
2335 return 0;
2336}
2337
2338#ifdef CONFIG_PM
2339
2340static void musb_save_context(struct musb *musb)
2341{
2342 int i;
2343 void __iomem *musb_base = musb->mregs;
2344 void __iomem *epio;
2345
2346 musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2347 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2348 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
2349 musb->context.power = musb_readb(musb_base, MUSB_POWER);
2350 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2351 musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2352 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2353
2354 for (i = 0; i < musb->config->num_eps; ++i) {
2355 struct musb_hw_ep *hw_ep;
2356
2357 hw_ep = &musb->endpoints[i];
2358 if (!hw_ep)
2359 continue;
2360
2361 epio = hw_ep->regs;
2362 if (!epio)
2363 continue;
2364
2365 musb_writeb(musb_base, MUSB_INDEX, i);
2366 musb->context.index_regs[i].txmaxp =
2367 musb_readw(epio, MUSB_TXMAXP);
2368 musb->context.index_regs[i].txcsr =
2369 musb_readw(epio, MUSB_TXCSR);
2370 musb->context.index_regs[i].rxmaxp =
2371 musb_readw(epio, MUSB_RXMAXP);
2372 musb->context.index_regs[i].rxcsr =
2373 musb_readw(epio, MUSB_RXCSR);
2374
2375 if (musb->dyn_fifo) {
2376 musb->context.index_regs[i].txfifoadd =
2377 musb_read_txfifoadd(musb_base);
2378 musb->context.index_regs[i].rxfifoadd =
2379 musb_read_rxfifoadd(musb_base);
2380 musb->context.index_regs[i].txfifosz =
2381 musb_read_txfifosz(musb_base);
2382 musb->context.index_regs[i].rxfifosz =
2383 musb_read_rxfifosz(musb_base);
2384 }
2385
2386 musb->context.index_regs[i].txtype =
2387 musb_readb(epio, MUSB_TXTYPE);
2388 musb->context.index_regs[i].txinterval =
2389 musb_readb(epio, MUSB_TXINTERVAL);
2390 musb->context.index_regs[i].rxtype =
2391 musb_readb(epio, MUSB_RXTYPE);
2392 musb->context.index_regs[i].rxinterval =
2393 musb_readb(epio, MUSB_RXINTERVAL);
2394
2395 musb->context.index_regs[i].txfunaddr =
2396 musb_read_txfunaddr(musb, i);
2397 musb->context.index_regs[i].txhubaddr =
2398 musb_read_txhubaddr(musb, i);
2399 musb->context.index_regs[i].txhubport =
2400 musb_read_txhubport(musb, i);
2401
2402 musb->context.index_regs[i].rxfunaddr =
2403 musb_read_rxfunaddr(musb, i);
2404 musb->context.index_regs[i].rxhubaddr =
2405 musb_read_rxhubaddr(musb, i);
2406 musb->context.index_regs[i].rxhubport =
2407 musb_read_rxhubport(musb, i);
2408 }
2409}
2410
2411static void musb_restore_context(struct musb *musb)
2412{
2413 int i;
2414 void __iomem *musb_base = musb->mregs;
2415 void __iomem *epio;
2416 u8 power;
2417
2418 musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2419 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2420 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
2421
2422 /* Don't affect SUSPENDM/RESUME bits in POWER reg */
2423 power = musb_readb(musb_base, MUSB_POWER);
2424 power &= MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME;
2425 musb->context.power &= ~(MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME);
2426 power |= musb->context.power;
2427 musb_writeb(musb_base, MUSB_POWER, power);
2428
2429 musb_writew(musb_base, MUSB_INTRTXE, musb->intrtxe);
2430 musb_writew(musb_base, MUSB_INTRRXE, musb->intrrxe);
2431 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2432 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
2433
2434 for (i = 0; i < musb->config->num_eps; ++i) {
2435 struct musb_hw_ep *hw_ep;
2436
2437 hw_ep = &musb->endpoints[i];
2438 if (!hw_ep)
2439 continue;
2440
2441 epio = hw_ep->regs;
2442 if (!epio)
2443 continue;
2444
2445 musb_writeb(musb_base, MUSB_INDEX, i);
2446 musb_writew(epio, MUSB_TXMAXP,
2447 musb->context.index_regs[i].txmaxp);
2448 musb_writew(epio, MUSB_TXCSR,
2449 musb->context.index_regs[i].txcsr);
2450 musb_writew(epio, MUSB_RXMAXP,
2451 musb->context.index_regs[i].rxmaxp);
2452 musb_writew(epio, MUSB_RXCSR,
2453 musb->context.index_regs[i].rxcsr);
2454
2455 if (musb->dyn_fifo) {
2456 musb_write_txfifosz(musb_base,
2457 musb->context.index_regs[i].txfifosz);
2458 musb_write_rxfifosz(musb_base,
2459 musb->context.index_regs[i].rxfifosz);
2460 musb_write_txfifoadd(musb_base,
2461 musb->context.index_regs[i].txfifoadd);
2462 musb_write_rxfifoadd(musb_base,
2463 musb->context.index_regs[i].rxfifoadd);
2464 }
2465
2466 musb_writeb(epio, MUSB_TXTYPE,
2467 musb->context.index_regs[i].txtype);
2468 musb_writeb(epio, MUSB_TXINTERVAL,
2469 musb->context.index_regs[i].txinterval);
2470 musb_writeb(epio, MUSB_RXTYPE,
2471 musb->context.index_regs[i].rxtype);
2472 musb_writeb(epio, MUSB_RXINTERVAL,
2473
2474 musb->context.index_regs[i].rxinterval);
2475 musb_write_txfunaddr(musb, i,
2476 musb->context.index_regs[i].txfunaddr);
2477 musb_write_txhubaddr(musb, i,
2478 musb->context.index_regs[i].txhubaddr);
2479 musb_write_txhubport(musb, i,
2480 musb->context.index_regs[i].txhubport);
2481
2482 musb_write_rxfunaddr(musb, i,
2483 musb->context.index_regs[i].rxfunaddr);
2484 musb_write_rxhubaddr(musb, i,
2485 musb->context.index_regs[i].rxhubaddr);
2486 musb_write_rxhubport(musb, i,
2487 musb->context.index_regs[i].rxhubport);
2488 }
2489 musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
2490}
2491
2492static int musb_suspend(struct device *dev)
2493{
2494 struct musb *musb = dev_to_musb(dev);
2495 unsigned long flags;
2496
2497 musb_platform_disable(musb);
2498 musb_generic_disable(musb);
2499
2500 spin_lock_irqsave(&musb->lock, flags);
2501
2502 if (is_peripheral_active(musb)) {
2503 /* FIXME force disconnect unless we know USB will wake
2504 * the system up quickly enough to respond ...
2505 */
2506 } else if (is_host_active(musb)) {
2507 /* we know all the children are suspended; sometimes
2508 * they will even be wakeup-enabled.
2509 */
2510 }
2511
2512 musb_save_context(musb);
2513
2514 spin_unlock_irqrestore(&musb->lock, flags);
2515 return 0;
2516}
2517
2518static int musb_resume(struct device *dev)
2519{
2520 struct musb *musb = dev_to_musb(dev);
2521 u8 devctl;
2522 u8 mask;
2523
2524 /*
2525 * For static cmos like DaVinci, register values were preserved
2526 * unless for some reason the whole soc powered down or the USB
2527 * module got reset through the PSC (vs just being disabled).
2528 *
2529 * For the DSPS glue layer though, a full register restore has to
2530 * be done. As it shouldn't harm other platforms, we do it
2531 * unconditionally.
2532 */
2533
2534 musb_restore_context(musb);
2535
2536 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2537 mask = MUSB_DEVCTL_BDEVICE | MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV;
2538 if ((devctl & mask) != (musb->context.devctl & mask))
2539 musb->port1_status = 0;
2540 if (musb->need_finish_resume) {
2541 musb->need_finish_resume = 0;
2542 schedule_delayed_work(&musb->finish_resume_work,
2543 msecs_to_jiffies(USB_RESUME_TIMEOUT));
2544 }
2545
2546 /*
2547 * The USB HUB code expects the device to be in RPM_ACTIVE once it came
2548 * out of suspend
2549 */
2550 pm_runtime_disable(dev);
2551 pm_runtime_set_active(dev);
2552 pm_runtime_enable(dev);
2553
2554 musb_start(musb);
2555
2556 return 0;
2557}
2558
2559static int musb_runtime_suspend(struct device *dev)
2560{
2561 struct musb *musb = dev_to_musb(dev);
2562
2563 musb_save_context(musb);
2564
2565 return 0;
2566}
2567
2568static int musb_runtime_resume(struct device *dev)
2569{
2570 struct musb *musb = dev_to_musb(dev);
2571 static int first = 1;
2572
2573 /*
2574 * When pm_runtime_get_sync called for the first time in driver
2575 * init, some of the structure is still not initialized which is
2576 * used in restore function. But clock needs to be
2577 * enabled before any register access, so
2578 * pm_runtime_get_sync has to be called.
2579 * Also context restore without save does not make
2580 * any sense
2581 */
2582 if (!first)
2583 musb_restore_context(musb);
2584 first = 0;
2585
2586 if (musb->need_finish_resume) {
2587 musb->need_finish_resume = 0;
2588 schedule_delayed_work(&musb->finish_resume_work,
2589 msecs_to_jiffies(USB_RESUME_TIMEOUT));
2590 }
2591
2592 return 0;
2593}
2594
2595static const struct dev_pm_ops musb_dev_pm_ops = {
2596 .suspend = musb_suspend,
2597 .resume = musb_resume,
2598 .runtime_suspend = musb_runtime_suspend,
2599 .runtime_resume = musb_runtime_resume,
2600};
2601
2602#define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2603#else
2604#define MUSB_DEV_PM_OPS NULL
2605#endif
2606
2607static struct platform_driver musb_driver = {
2608 .driver = {
2609 .name = (char *)musb_driver_name,
2610 .bus = &platform_bus_type,
2611 .pm = MUSB_DEV_PM_OPS,
2612 },
2613 .probe = musb_probe,
2614 .remove = musb_remove,
2615 .shutdown = musb_shutdown,
2616};
2617
2618module_platform_driver(musb_driver);
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * MUSB OTG driver core code
4 *
5 * Copyright 2005 Mentor Graphics Corporation
6 * Copyright (C) 2005-2006 by Texas Instruments
7 * Copyright (C) 2006-2007 Nokia Corporation
8 */
9
10/*
11 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
12 *
13 * This consists of a Host Controller Driver (HCD) and a peripheral
14 * controller driver implementing the "Gadget" API; OTG support is
15 * in the works. These are normal Linux-USB controller drivers which
16 * use IRQs and have no dedicated thread.
17 *
18 * This version of the driver has only been used with products from
19 * Texas Instruments. Those products integrate the Inventra logic
20 * with other DMA, IRQ, and bus modules, as well as other logic that
21 * needs to be reflected in this driver.
22 *
23 *
24 * NOTE: the original Mentor code here was pretty much a collection
25 * of mechanisms that don't seem to have been fully integrated/working
26 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
27 * Key open issues include:
28 *
29 * - Lack of host-side transaction scheduling, for all transfer types.
30 * The hardware doesn't do it; instead, software must.
31 *
32 * This is not an issue for OTG devices that don't support external
33 * hubs, but for more "normal" USB hosts it's a user issue that the
34 * "multipoint" support doesn't scale in the expected ways. That
35 * includes DaVinci EVM in a common non-OTG mode.
36 *
37 * * Control and bulk use dedicated endpoints, and there's as
38 * yet no mechanism to either (a) reclaim the hardware when
39 * peripherals are NAKing, which gets complicated with bulk
40 * endpoints, or (b) use more than a single bulk endpoint in
41 * each direction.
42 *
43 * RESULT: one device may be perceived as blocking another one.
44 *
45 * * Interrupt and isochronous will dynamically allocate endpoint
46 * hardware, but (a) there's no record keeping for bandwidth;
47 * (b) in the common case that few endpoints are available, there
48 * is no mechanism to reuse endpoints to talk to multiple devices.
49 *
50 * RESULT: At one extreme, bandwidth can be overcommitted in
51 * some hardware configurations, no faults will be reported.
52 * At the other extreme, the bandwidth capabilities which do
53 * exist tend to be severely undercommitted. You can't yet hook
54 * up both a keyboard and a mouse to an external USB hub.
55 */
56
57/*
58 * This gets many kinds of configuration information:
59 * - Kconfig for everything user-configurable
60 * - platform_device for addressing, irq, and platform_data
61 * - platform_data is mostly for board-specific information
62 * (plus recentrly, SOC or family details)
63 *
64 * Most of the conditional compilation will (someday) vanish.
65 */
66
67#include <linux/module.h>
68#include <linux/kernel.h>
69#include <linux/sched.h>
70#include <linux/slab.h>
71#include <linux/list.h>
72#include <linux/kobject.h>
73#include <linux/prefetch.h>
74#include <linux/platform_device.h>
75#include <linux/io.h>
76#include <linux/iopoll.h>
77#include <linux/dma-mapping.h>
78#include <linux/usb.h>
79#include <linux/usb/of.h>
80
81#include "musb_core.h"
82#include "musb_trace.h"
83
84#define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
85
86
87#define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
88#define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
89
90#define MUSB_VERSION "6.0"
91
92#define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
93
94#define MUSB_DRIVER_NAME "musb-hdrc"
95const char musb_driver_name[] = MUSB_DRIVER_NAME;
96
97MODULE_DESCRIPTION(DRIVER_INFO);
98MODULE_AUTHOR(DRIVER_AUTHOR);
99MODULE_LICENSE("GPL");
100MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
101
102
103/*-------------------------------------------------------------------------*/
104
105static inline struct musb *dev_to_musb(struct device *dev)
106{
107 return dev_get_drvdata(dev);
108}
109
110enum musb_mode musb_get_mode(struct device *dev)
111{
112 enum usb_dr_mode mode;
113
114 mode = usb_get_dr_mode(dev);
115 switch (mode) {
116 case USB_DR_MODE_HOST:
117 return MUSB_HOST;
118 case USB_DR_MODE_PERIPHERAL:
119 return MUSB_PERIPHERAL;
120 case USB_DR_MODE_OTG:
121 case USB_DR_MODE_UNKNOWN:
122 default:
123 return MUSB_OTG;
124 }
125}
126EXPORT_SYMBOL_GPL(musb_get_mode);
127
128/*-------------------------------------------------------------------------*/
129
130static int musb_ulpi_read(struct usb_phy *phy, u32 reg)
131{
132 void __iomem *addr = phy->io_priv;
133 int i = 0;
134 u8 r;
135 u8 power;
136 int ret;
137
138 pm_runtime_get_sync(phy->io_dev);
139
140 /* Make sure the transceiver is not in low power mode */
141 power = musb_readb(addr, MUSB_POWER);
142 power &= ~MUSB_POWER_SUSPENDM;
143 musb_writeb(addr, MUSB_POWER, power);
144
145 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
146 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
147 */
148
149 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg);
150 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
151 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
152
153 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
154 & MUSB_ULPI_REG_CMPLT)) {
155 i++;
156 if (i == 10000) {
157 ret = -ETIMEDOUT;
158 goto out;
159 }
160
161 }
162 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
163 r &= ~MUSB_ULPI_REG_CMPLT;
164 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
165
166 ret = musb_readb(addr, MUSB_ULPI_REG_DATA);
167
168out:
169 pm_runtime_put(phy->io_dev);
170
171 return ret;
172}
173
174static int musb_ulpi_write(struct usb_phy *phy, u32 val, u32 reg)
175{
176 void __iomem *addr = phy->io_priv;
177 int i = 0;
178 u8 r = 0;
179 u8 power;
180 int ret = 0;
181
182 pm_runtime_get_sync(phy->io_dev);
183
184 /* Make sure the transceiver is not in low power mode */
185 power = musb_readb(addr, MUSB_POWER);
186 power &= ~MUSB_POWER_SUSPENDM;
187 musb_writeb(addr, MUSB_POWER, power);
188
189 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg);
190 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)val);
191 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
192
193 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
194 & MUSB_ULPI_REG_CMPLT)) {
195 i++;
196 if (i == 10000) {
197 ret = -ETIMEDOUT;
198 goto out;
199 }
200 }
201
202 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
203 r &= ~MUSB_ULPI_REG_CMPLT;
204 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
205
206out:
207 pm_runtime_put(phy->io_dev);
208
209 return ret;
210}
211
212static struct usb_phy_io_ops musb_ulpi_access = {
213 .read = musb_ulpi_read,
214 .write = musb_ulpi_write,
215};
216
217/*-------------------------------------------------------------------------*/
218
219static u32 musb_default_fifo_offset(u8 epnum)
220{
221 return 0x20 + (epnum * 4);
222}
223
224/* "flat" mapping: each endpoint has its own i/o address */
225static void musb_flat_ep_select(void __iomem *mbase, u8 epnum)
226{
227}
228
229static u32 musb_flat_ep_offset(u8 epnum, u16 offset)
230{
231 return 0x100 + (0x10 * epnum) + offset;
232}
233
234/* "indexed" mapping: INDEX register controls register bank select */
235static void musb_indexed_ep_select(void __iomem *mbase, u8 epnum)
236{
237 musb_writeb(mbase, MUSB_INDEX, epnum);
238}
239
240static u32 musb_indexed_ep_offset(u8 epnum, u16 offset)
241{
242 return 0x10 + offset;
243}
244
245static u32 musb_default_busctl_offset(u8 epnum, u16 offset)
246{
247 return 0x80 + (0x08 * epnum) + offset;
248}
249
250static u8 musb_default_readb(void __iomem *addr, u32 offset)
251{
252 u8 data = __raw_readb(addr + offset);
253
254 trace_musb_readb(__builtin_return_address(0), addr, offset, data);
255 return data;
256}
257
258static void musb_default_writeb(void __iomem *addr, u32 offset, u8 data)
259{
260 trace_musb_writeb(__builtin_return_address(0), addr, offset, data);
261 __raw_writeb(data, addr + offset);
262}
263
264static u16 musb_default_readw(void __iomem *addr, u32 offset)
265{
266 u16 data = __raw_readw(addr + offset);
267
268 trace_musb_readw(__builtin_return_address(0), addr, offset, data);
269 return data;
270}
271
272static void musb_default_writew(void __iomem *addr, u32 offset, u16 data)
273{
274 trace_musb_writew(__builtin_return_address(0), addr, offset, data);
275 __raw_writew(data, addr + offset);
276}
277
278static u16 musb_default_get_toggle(struct musb_qh *qh, int is_out)
279{
280 void __iomem *epio = qh->hw_ep->regs;
281 u16 csr;
282
283 if (is_out)
284 csr = musb_readw(epio, MUSB_TXCSR) & MUSB_TXCSR_H_DATATOGGLE;
285 else
286 csr = musb_readw(epio, MUSB_RXCSR) & MUSB_RXCSR_H_DATATOGGLE;
287
288 return csr;
289}
290
291static u16 musb_default_set_toggle(struct musb_qh *qh, int is_out,
292 struct urb *urb)
293{
294 u16 csr;
295 u16 toggle;
296
297 toggle = usb_gettoggle(urb->dev, qh->epnum, is_out);
298
299 if (is_out)
300 csr = toggle ? (MUSB_TXCSR_H_WR_DATATOGGLE
301 | MUSB_TXCSR_H_DATATOGGLE)
302 : MUSB_TXCSR_CLRDATATOG;
303 else
304 csr = toggle ? (MUSB_RXCSR_H_WR_DATATOGGLE
305 | MUSB_RXCSR_H_DATATOGGLE) : 0;
306
307 return csr;
308}
309
310/*
311 * Load an endpoint's FIFO
312 */
313static void musb_default_write_fifo(struct musb_hw_ep *hw_ep, u16 len,
314 const u8 *src)
315{
316 struct musb *musb = hw_ep->musb;
317 void __iomem *fifo = hw_ep->fifo;
318
319 if (unlikely(len == 0))
320 return;
321
322 prefetch((u8 *)src);
323
324 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
325 'T', hw_ep->epnum, fifo, len, src);
326
327 /* we can't assume unaligned reads work */
328 if (likely((0x01 & (unsigned long) src) == 0)) {
329 u16 index = 0;
330
331 /* best case is 32bit-aligned source address */
332 if ((0x02 & (unsigned long) src) == 0) {
333 if (len >= 4) {
334 iowrite32_rep(fifo, src + index, len >> 2);
335 index += len & ~0x03;
336 }
337 if (len & 0x02) {
338 __raw_writew(*(u16 *)&src[index], fifo);
339 index += 2;
340 }
341 } else {
342 if (len >= 2) {
343 iowrite16_rep(fifo, src + index, len >> 1);
344 index += len & ~0x01;
345 }
346 }
347 if (len & 0x01)
348 __raw_writeb(src[index], fifo);
349 } else {
350 /* byte aligned */
351 iowrite8_rep(fifo, src, len);
352 }
353}
354
355/*
356 * Unload an endpoint's FIFO
357 */
358static void musb_default_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
359{
360 struct musb *musb = hw_ep->musb;
361 void __iomem *fifo = hw_ep->fifo;
362
363 if (unlikely(len == 0))
364 return;
365
366 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
367 'R', hw_ep->epnum, fifo, len, dst);
368
369 /* we can't assume unaligned writes work */
370 if (likely((0x01 & (unsigned long) dst) == 0)) {
371 u16 index = 0;
372
373 /* best case is 32bit-aligned destination address */
374 if ((0x02 & (unsigned long) dst) == 0) {
375 if (len >= 4) {
376 ioread32_rep(fifo, dst, len >> 2);
377 index = len & ~0x03;
378 }
379 if (len & 0x02) {
380 *(u16 *)&dst[index] = __raw_readw(fifo);
381 index += 2;
382 }
383 } else {
384 if (len >= 2) {
385 ioread16_rep(fifo, dst, len >> 1);
386 index = len & ~0x01;
387 }
388 }
389 if (len & 0x01)
390 dst[index] = __raw_readb(fifo);
391 } else {
392 /* byte aligned */
393 ioread8_rep(fifo, dst, len);
394 }
395}
396
397/*
398 * Old style IO functions
399 */
400u8 (*musb_readb)(void __iomem *addr, u32 offset);
401EXPORT_SYMBOL_GPL(musb_readb);
402
403void (*musb_writeb)(void __iomem *addr, u32 offset, u8 data);
404EXPORT_SYMBOL_GPL(musb_writeb);
405
406u8 (*musb_clearb)(void __iomem *addr, u32 offset);
407EXPORT_SYMBOL_GPL(musb_clearb);
408
409u16 (*musb_readw)(void __iomem *addr, u32 offset);
410EXPORT_SYMBOL_GPL(musb_readw);
411
412void (*musb_writew)(void __iomem *addr, u32 offset, u16 data);
413EXPORT_SYMBOL_GPL(musb_writew);
414
415u16 (*musb_clearw)(void __iomem *addr, u32 offset);
416EXPORT_SYMBOL_GPL(musb_clearw);
417
418u32 musb_readl(void __iomem *addr, u32 offset)
419{
420 u32 data = __raw_readl(addr + offset);
421
422 trace_musb_readl(__builtin_return_address(0), addr, offset, data);
423 return data;
424}
425EXPORT_SYMBOL_GPL(musb_readl);
426
427void musb_writel(void __iomem *addr, u32 offset, u32 data)
428{
429 trace_musb_writel(__builtin_return_address(0), addr, offset, data);
430 __raw_writel(data, addr + offset);
431}
432EXPORT_SYMBOL_GPL(musb_writel);
433
434#ifndef CONFIG_MUSB_PIO_ONLY
435struct dma_controller *
436(*musb_dma_controller_create)(struct musb *musb, void __iomem *base);
437EXPORT_SYMBOL(musb_dma_controller_create);
438
439void (*musb_dma_controller_destroy)(struct dma_controller *c);
440EXPORT_SYMBOL(musb_dma_controller_destroy);
441#endif
442
443/*
444 * New style IO functions
445 */
446void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
447{
448 return hw_ep->musb->io.read_fifo(hw_ep, len, dst);
449}
450
451void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
452{
453 return hw_ep->musb->io.write_fifo(hw_ep, len, src);
454}
455
456static u8 musb_read_devctl(struct musb *musb)
457{
458 return musb_readb(musb->mregs, MUSB_DEVCTL);
459}
460
461/**
462 * musb_set_host - set and initialize host mode
463 * @musb: musb controller driver data
464 *
465 * At least some musb revisions need to enable devctl session bit in
466 * peripheral mode to switch to host mode. Initializes things to host
467 * mode and sets A_IDLE. SoC glue needs to advance state further
468 * based on phy provided VBUS state.
469 *
470 * Note that the SoC glue code may need to wait for musb to settle
471 * on enable before calling this to avoid babble.
472 */
473int musb_set_host(struct musb *musb)
474{
475 int error = 0;
476 u8 devctl;
477
478 if (!musb)
479 return -EINVAL;
480
481 devctl = musb_read_devctl(musb);
482 if (!(devctl & MUSB_DEVCTL_BDEVICE)) {
483 dev_info(musb->controller,
484 "%s: already in host mode: %02x\n",
485 __func__, devctl);
486 goto init_data;
487 }
488
489 devctl |= MUSB_DEVCTL_SESSION;
490 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
491
492 error = readx_poll_timeout(musb_read_devctl, musb, devctl,
493 !(devctl & MUSB_DEVCTL_BDEVICE), 5000,
494 1000000);
495 if (error) {
496 dev_err(musb->controller, "%s: could not set host: %02x\n",
497 __func__, devctl);
498
499 return error;
500 }
501
502init_data:
503 musb->is_active = 1;
504 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
505 MUSB_HST_MODE(musb);
506
507 return error;
508}
509EXPORT_SYMBOL_GPL(musb_set_host);
510
511/**
512 * musb_set_peripheral - set and initialize peripheral mode
513 * @musb: musb controller driver data
514 *
515 * Clears devctl session bit and initializes things for peripheral
516 * mode and sets B_IDLE. SoC glue needs to advance state further
517 * based on phy provided VBUS state.
518 */
519int musb_set_peripheral(struct musb *musb)
520{
521 int error = 0;
522 u8 devctl;
523
524 if (!musb)
525 return -EINVAL;
526
527 devctl = musb_read_devctl(musb);
528 if (devctl & MUSB_DEVCTL_BDEVICE) {
529 dev_info(musb->controller,
530 "%s: already in peripheral mode: %02x\n",
531 __func__, devctl);
532
533 goto init_data;
534 }
535
536 devctl &= ~MUSB_DEVCTL_SESSION;
537 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
538
539 error = readx_poll_timeout(musb_read_devctl, musb, devctl,
540 devctl & MUSB_DEVCTL_BDEVICE, 5000,
541 1000000);
542 if (error) {
543 dev_err(musb->controller, "%s: could not set peripheral: %02x\n",
544 __func__, devctl);
545
546 return error;
547 }
548
549init_data:
550 musb->is_active = 0;
551 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
552 MUSB_DEV_MODE(musb);
553
554 return error;
555}
556EXPORT_SYMBOL_GPL(musb_set_peripheral);
557
558/*-------------------------------------------------------------------------*/
559
560/* for high speed test mode; see USB 2.0 spec 7.1.20 */
561static const u8 musb_test_packet[53] = {
562 /* implicit SYNC then DATA0 to start */
563
564 /* JKJKJKJK x9 */
565 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
566 /* JJKKJJKK x8 */
567 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
568 /* JJJJKKKK x8 */
569 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
570 /* JJJJJJJKKKKKKK x8 */
571 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
572 /* JJJJJJJK x8 */
573 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
574 /* JKKKKKKK x10, JK */
575 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
576
577 /* implicit CRC16 then EOP to end */
578};
579
580void musb_load_testpacket(struct musb *musb)
581{
582 void __iomem *regs = musb->endpoints[0].regs;
583
584 musb_ep_select(musb->mregs, 0);
585 musb_write_fifo(musb->control_ep,
586 sizeof(musb_test_packet), musb_test_packet);
587 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
588}
589
590/*-------------------------------------------------------------------------*/
591
592/*
593 * Handles OTG hnp timeouts, such as b_ase0_brst
594 */
595static void musb_otg_timer_func(struct timer_list *t)
596{
597 struct musb *musb = from_timer(musb, t, otg_timer);
598 unsigned long flags;
599
600 spin_lock_irqsave(&musb->lock, flags);
601 switch (musb->xceiv->otg->state) {
602 case OTG_STATE_B_WAIT_ACON:
603 musb_dbg(musb,
604 "HNP: b_wait_acon timeout; back to b_peripheral");
605 musb_g_disconnect(musb);
606 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
607 musb->is_active = 0;
608 break;
609 case OTG_STATE_A_SUSPEND:
610 case OTG_STATE_A_WAIT_BCON:
611 musb_dbg(musb, "HNP: %s timeout",
612 usb_otg_state_string(musb->xceiv->otg->state));
613 musb_platform_set_vbus(musb, 0);
614 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
615 break;
616 default:
617 musb_dbg(musb, "HNP: Unhandled mode %s",
618 usb_otg_state_string(musb->xceiv->otg->state));
619 }
620 spin_unlock_irqrestore(&musb->lock, flags);
621}
622
623/*
624 * Stops the HNP transition. Caller must take care of locking.
625 */
626void musb_hnp_stop(struct musb *musb)
627{
628 struct usb_hcd *hcd = musb->hcd;
629 void __iomem *mbase = musb->mregs;
630 u8 reg;
631
632 musb_dbg(musb, "HNP: stop from %s",
633 usb_otg_state_string(musb->xceiv->otg->state));
634
635 switch (musb->xceiv->otg->state) {
636 case OTG_STATE_A_PERIPHERAL:
637 musb_g_disconnect(musb);
638 musb_dbg(musb, "HNP: back to %s",
639 usb_otg_state_string(musb->xceiv->otg->state));
640 break;
641 case OTG_STATE_B_HOST:
642 musb_dbg(musb, "HNP: Disabling HR");
643 if (hcd)
644 hcd->self.is_b_host = 0;
645 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
646 MUSB_DEV_MODE(musb);
647 reg = musb_readb(mbase, MUSB_POWER);
648 reg |= MUSB_POWER_SUSPENDM;
649 musb_writeb(mbase, MUSB_POWER, reg);
650 /* REVISIT: Start SESSION_REQUEST here? */
651 break;
652 default:
653 musb_dbg(musb, "HNP: Stopping in unknown state %s",
654 usb_otg_state_string(musb->xceiv->otg->state));
655 }
656
657 /*
658 * When returning to A state after HNP, avoid hub_port_rebounce(),
659 * which cause occasional OPT A "Did not receive reset after connect"
660 * errors.
661 */
662 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
663}
664
665static void musb_recover_from_babble(struct musb *musb);
666
667static void musb_handle_intr_resume(struct musb *musb, u8 devctl)
668{
669 musb_dbg(musb, "RESUME (%s)",
670 usb_otg_state_string(musb->xceiv->otg->state));
671
672 if (devctl & MUSB_DEVCTL_HM) {
673 switch (musb->xceiv->otg->state) {
674 case OTG_STATE_A_SUSPEND:
675 /* remote wakeup? */
676 musb->port1_status |=
677 (USB_PORT_STAT_C_SUSPEND << 16)
678 | MUSB_PORT_STAT_RESUME;
679 musb->rh_timer = jiffies
680 + msecs_to_jiffies(USB_RESUME_TIMEOUT);
681 musb->xceiv->otg->state = OTG_STATE_A_HOST;
682 musb->is_active = 1;
683 musb_host_resume_root_hub(musb);
684 schedule_delayed_work(&musb->finish_resume_work,
685 msecs_to_jiffies(USB_RESUME_TIMEOUT));
686 break;
687 case OTG_STATE_B_WAIT_ACON:
688 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
689 musb->is_active = 1;
690 MUSB_DEV_MODE(musb);
691 break;
692 default:
693 WARNING("bogus %s RESUME (%s)\n",
694 "host",
695 usb_otg_state_string(musb->xceiv->otg->state));
696 }
697 } else {
698 switch (musb->xceiv->otg->state) {
699 case OTG_STATE_A_SUSPEND:
700 /* possibly DISCONNECT is upcoming */
701 musb->xceiv->otg->state = OTG_STATE_A_HOST;
702 musb_host_resume_root_hub(musb);
703 break;
704 case OTG_STATE_B_WAIT_ACON:
705 case OTG_STATE_B_PERIPHERAL:
706 /* disconnect while suspended? we may
707 * not get a disconnect irq...
708 */
709 if ((devctl & MUSB_DEVCTL_VBUS)
710 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
711 ) {
712 musb->int_usb |= MUSB_INTR_DISCONNECT;
713 musb->int_usb &= ~MUSB_INTR_SUSPEND;
714 break;
715 }
716 musb_g_resume(musb);
717 break;
718 case OTG_STATE_B_IDLE:
719 musb->int_usb &= ~MUSB_INTR_SUSPEND;
720 break;
721 default:
722 WARNING("bogus %s RESUME (%s)\n",
723 "peripheral",
724 usb_otg_state_string(musb->xceiv->otg->state));
725 }
726 }
727}
728
729/* return IRQ_HANDLED to tell the caller to return immediately */
730static irqreturn_t musb_handle_intr_sessreq(struct musb *musb, u8 devctl)
731{
732 void __iomem *mbase = musb->mregs;
733
734 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
735 && (devctl & MUSB_DEVCTL_BDEVICE)) {
736 musb_dbg(musb, "SessReq while on B state");
737 return IRQ_HANDLED;
738 }
739
740 musb_dbg(musb, "SESSION_REQUEST (%s)",
741 usb_otg_state_string(musb->xceiv->otg->state));
742
743 /* IRQ arrives from ID pin sense or (later, if VBUS power
744 * is removed) SRP. responses are time critical:
745 * - turn on VBUS (with silicon-specific mechanism)
746 * - go through A_WAIT_VRISE
747 * - ... to A_WAIT_BCON.
748 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
749 */
750 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
751 musb->ep0_stage = MUSB_EP0_START;
752 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
753 MUSB_HST_MODE(musb);
754 musb_platform_set_vbus(musb, 1);
755
756 return IRQ_NONE;
757}
758
759static void musb_handle_intr_vbuserr(struct musb *musb, u8 devctl)
760{
761 int ignore = 0;
762
763 /* During connection as an A-Device, we may see a short
764 * current spikes causing voltage drop, because of cable
765 * and peripheral capacitance combined with vbus draw.
766 * (So: less common with truly self-powered devices, where
767 * vbus doesn't act like a power supply.)
768 *
769 * Such spikes are short; usually less than ~500 usec, max
770 * of ~2 msec. That is, they're not sustained overcurrent
771 * errors, though they're reported using VBUSERROR irqs.
772 *
773 * Workarounds: (a) hardware: use self powered devices.
774 * (b) software: ignore non-repeated VBUS errors.
775 *
776 * REVISIT: do delays from lots of DEBUG_KERNEL checks
777 * make trouble here, keeping VBUS < 4.4V ?
778 */
779 switch (musb->xceiv->otg->state) {
780 case OTG_STATE_A_HOST:
781 /* recovery is dicey once we've gotten past the
782 * initial stages of enumeration, but if VBUS
783 * stayed ok at the other end of the link, and
784 * another reset is due (at least for high speed,
785 * to redo the chirp etc), it might work OK...
786 */
787 case OTG_STATE_A_WAIT_BCON:
788 case OTG_STATE_A_WAIT_VRISE:
789 if (musb->vbuserr_retry) {
790 void __iomem *mbase = musb->mregs;
791
792 musb->vbuserr_retry--;
793 ignore = 1;
794 devctl |= MUSB_DEVCTL_SESSION;
795 musb_writeb(mbase, MUSB_DEVCTL, devctl);
796 } else {
797 musb->port1_status |=
798 USB_PORT_STAT_OVERCURRENT
799 | (USB_PORT_STAT_C_OVERCURRENT << 16);
800 }
801 break;
802 default:
803 break;
804 }
805
806 dev_printk(ignore ? KERN_DEBUG : KERN_ERR, musb->controller,
807 "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
808 usb_otg_state_string(musb->xceiv->otg->state),
809 devctl,
810 ({ char *s;
811 switch (devctl & MUSB_DEVCTL_VBUS) {
812 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
813 s = "<SessEnd"; break;
814 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
815 s = "<AValid"; break;
816 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
817 s = "<VBusValid"; break;
818 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
819 default:
820 s = "VALID"; break;
821 } s; }),
822 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
823 musb->port1_status);
824
825 /* go through A_WAIT_VFALL then start a new session */
826 if (!ignore)
827 musb_platform_set_vbus(musb, 0);
828}
829
830static void musb_handle_intr_suspend(struct musb *musb, u8 devctl)
831{
832 musb_dbg(musb, "SUSPEND (%s) devctl %02x",
833 usb_otg_state_string(musb->xceiv->otg->state), devctl);
834
835 switch (musb->xceiv->otg->state) {
836 case OTG_STATE_A_PERIPHERAL:
837 /* We also come here if the cable is removed, since
838 * this silicon doesn't report ID-no-longer-grounded.
839 *
840 * We depend on T(a_wait_bcon) to shut us down, and
841 * hope users don't do anything dicey during this
842 * undesired detour through A_WAIT_BCON.
843 */
844 musb_hnp_stop(musb);
845 musb_host_resume_root_hub(musb);
846 musb_root_disconnect(musb);
847 musb_platform_try_idle(musb, jiffies
848 + msecs_to_jiffies(musb->a_wait_bcon
849 ? : OTG_TIME_A_WAIT_BCON));
850
851 break;
852 case OTG_STATE_B_IDLE:
853 if (!musb->is_active)
854 break;
855 fallthrough;
856 case OTG_STATE_B_PERIPHERAL:
857 musb_g_suspend(musb);
858 musb->is_active = musb->g.b_hnp_enable;
859 if (musb->is_active) {
860 musb->xceiv->otg->state = OTG_STATE_B_WAIT_ACON;
861 musb_dbg(musb, "HNP: Setting timer for b_ase0_brst");
862 mod_timer(&musb->otg_timer, jiffies
863 + msecs_to_jiffies(
864 OTG_TIME_B_ASE0_BRST));
865 }
866 break;
867 case OTG_STATE_A_WAIT_BCON:
868 if (musb->a_wait_bcon != 0)
869 musb_platform_try_idle(musb, jiffies
870 + msecs_to_jiffies(musb->a_wait_bcon));
871 break;
872 case OTG_STATE_A_HOST:
873 musb->xceiv->otg->state = OTG_STATE_A_SUSPEND;
874 musb->is_active = musb->hcd->self.b_hnp_enable;
875 break;
876 case OTG_STATE_B_HOST:
877 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
878 musb_dbg(musb, "REVISIT: SUSPEND as B_HOST");
879 break;
880 default:
881 /* "should not happen" */
882 musb->is_active = 0;
883 break;
884 }
885}
886
887static void musb_handle_intr_connect(struct musb *musb, u8 devctl, u8 int_usb)
888{
889 struct usb_hcd *hcd = musb->hcd;
890
891 musb->is_active = 1;
892 musb->ep0_stage = MUSB_EP0_START;
893
894 musb->intrtxe = musb->epmask;
895 musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe);
896 musb->intrrxe = musb->epmask & 0xfffe;
897 musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe);
898 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
899 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
900 |USB_PORT_STAT_HIGH_SPEED
901 |USB_PORT_STAT_ENABLE
902 );
903 musb->port1_status |= USB_PORT_STAT_CONNECTION
904 |(USB_PORT_STAT_C_CONNECTION << 16);
905
906 /* high vs full speed is just a guess until after reset */
907 if (devctl & MUSB_DEVCTL_LSDEV)
908 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
909
910 /* indicate new connection to OTG machine */
911 switch (musb->xceiv->otg->state) {
912 case OTG_STATE_B_PERIPHERAL:
913 if (int_usb & MUSB_INTR_SUSPEND) {
914 musb_dbg(musb, "HNP: SUSPEND+CONNECT, now b_host");
915 int_usb &= ~MUSB_INTR_SUSPEND;
916 goto b_host;
917 } else
918 musb_dbg(musb, "CONNECT as b_peripheral???");
919 break;
920 case OTG_STATE_B_WAIT_ACON:
921 musb_dbg(musb, "HNP: CONNECT, now b_host");
922b_host:
923 musb->xceiv->otg->state = OTG_STATE_B_HOST;
924 if (musb->hcd)
925 musb->hcd->self.is_b_host = 1;
926 del_timer(&musb->otg_timer);
927 break;
928 default:
929 if ((devctl & MUSB_DEVCTL_VBUS)
930 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
931 musb->xceiv->otg->state = OTG_STATE_A_HOST;
932 if (hcd)
933 hcd->self.is_b_host = 0;
934 }
935 break;
936 }
937
938 musb_host_poke_root_hub(musb);
939
940 musb_dbg(musb, "CONNECT (%s) devctl %02x",
941 usb_otg_state_string(musb->xceiv->otg->state), devctl);
942}
943
944static void musb_handle_intr_disconnect(struct musb *musb, u8 devctl)
945{
946 musb_dbg(musb, "DISCONNECT (%s) as %s, devctl %02x",
947 usb_otg_state_string(musb->xceiv->otg->state),
948 MUSB_MODE(musb), devctl);
949
950 switch (musb->xceiv->otg->state) {
951 case OTG_STATE_A_HOST:
952 case OTG_STATE_A_SUSPEND:
953 musb_host_resume_root_hub(musb);
954 musb_root_disconnect(musb);
955 if (musb->a_wait_bcon != 0)
956 musb_platform_try_idle(musb, jiffies
957 + msecs_to_jiffies(musb->a_wait_bcon));
958 break;
959 case OTG_STATE_B_HOST:
960 /* REVISIT this behaves for "real disconnect"
961 * cases; make sure the other transitions from
962 * from B_HOST act right too. The B_HOST code
963 * in hnp_stop() is currently not used...
964 */
965 musb_root_disconnect(musb);
966 if (musb->hcd)
967 musb->hcd->self.is_b_host = 0;
968 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
969 MUSB_DEV_MODE(musb);
970 musb_g_disconnect(musb);
971 break;
972 case OTG_STATE_A_PERIPHERAL:
973 musb_hnp_stop(musb);
974 musb_root_disconnect(musb);
975 fallthrough;
976 case OTG_STATE_B_WAIT_ACON:
977 case OTG_STATE_B_PERIPHERAL:
978 case OTG_STATE_B_IDLE:
979 musb_g_disconnect(musb);
980 break;
981 default:
982 WARNING("unhandled DISCONNECT transition (%s)\n",
983 usb_otg_state_string(musb->xceiv->otg->state));
984 break;
985 }
986}
987
988/*
989 * mentor saves a bit: bus reset and babble share the same irq.
990 * only host sees babble; only peripheral sees bus reset.
991 */
992static void musb_handle_intr_reset(struct musb *musb)
993{
994 if (is_host_active(musb)) {
995 /*
996 * When BABBLE happens what we can depends on which
997 * platform MUSB is running, because some platforms
998 * implemented proprietary means for 'recovering' from
999 * Babble conditions. One such platform is AM335x. In
1000 * most cases, however, the only thing we can do is
1001 * drop the session.
1002 */
1003 dev_err(musb->controller, "Babble\n");
1004 musb_recover_from_babble(musb);
1005 } else {
1006 musb_dbg(musb, "BUS RESET as %s",
1007 usb_otg_state_string(musb->xceiv->otg->state));
1008 switch (musb->xceiv->otg->state) {
1009 case OTG_STATE_A_SUSPEND:
1010 musb_g_reset(musb);
1011 fallthrough;
1012 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
1013 /* never use invalid T(a_wait_bcon) */
1014 musb_dbg(musb, "HNP: in %s, %d msec timeout",
1015 usb_otg_state_string(musb->xceiv->otg->state),
1016 TA_WAIT_BCON(musb));
1017 mod_timer(&musb->otg_timer, jiffies
1018 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
1019 break;
1020 case OTG_STATE_A_PERIPHERAL:
1021 del_timer(&musb->otg_timer);
1022 musb_g_reset(musb);
1023 break;
1024 case OTG_STATE_B_WAIT_ACON:
1025 musb_dbg(musb, "HNP: RESET (%s), to b_peripheral",
1026 usb_otg_state_string(musb->xceiv->otg->state));
1027 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
1028 musb_g_reset(musb);
1029 break;
1030 case OTG_STATE_B_IDLE:
1031 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
1032 fallthrough;
1033 case OTG_STATE_B_PERIPHERAL:
1034 musb_g_reset(musb);
1035 break;
1036 default:
1037 musb_dbg(musb, "Unhandled BUS RESET as %s",
1038 usb_otg_state_string(musb->xceiv->otg->state));
1039 }
1040 }
1041}
1042
1043/*
1044 * Interrupt Service Routine to record USB "global" interrupts.
1045 * Since these do not happen often and signify things of
1046 * paramount importance, it seems OK to check them individually;
1047 * the order of the tests is specified in the manual
1048 *
1049 * @param musb instance pointer
1050 * @param int_usb register contents
1051 * @param devctl
1052 */
1053
1054static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
1055 u8 devctl)
1056{
1057 irqreturn_t handled = IRQ_NONE;
1058
1059 musb_dbg(musb, "<== DevCtl=%02x, int_usb=0x%x", devctl, int_usb);
1060
1061 /* in host mode, the peripheral may issue remote wakeup.
1062 * in peripheral mode, the host may resume the link.
1063 * spurious RESUME irqs happen too, paired with SUSPEND.
1064 */
1065 if (int_usb & MUSB_INTR_RESUME) {
1066 musb_handle_intr_resume(musb, devctl);
1067 handled = IRQ_HANDLED;
1068 }
1069
1070 /* see manual for the order of the tests */
1071 if (int_usb & MUSB_INTR_SESSREQ) {
1072 if (musb_handle_intr_sessreq(musb, devctl))
1073 return IRQ_HANDLED;
1074 handled = IRQ_HANDLED;
1075 }
1076
1077 if (int_usb & MUSB_INTR_VBUSERROR) {
1078 musb_handle_intr_vbuserr(musb, devctl);
1079 handled = IRQ_HANDLED;
1080 }
1081
1082 if (int_usb & MUSB_INTR_SUSPEND) {
1083 musb_handle_intr_suspend(musb, devctl);
1084 handled = IRQ_HANDLED;
1085 }
1086
1087 if (int_usb & MUSB_INTR_CONNECT) {
1088 musb_handle_intr_connect(musb, devctl, int_usb);
1089 handled = IRQ_HANDLED;
1090 }
1091
1092 if (int_usb & MUSB_INTR_DISCONNECT) {
1093 musb_handle_intr_disconnect(musb, devctl);
1094 handled = IRQ_HANDLED;
1095 }
1096
1097 if (int_usb & MUSB_INTR_RESET) {
1098 musb_handle_intr_reset(musb);
1099 handled = IRQ_HANDLED;
1100 }
1101
1102#if 0
1103/* REVISIT ... this would be for multiplexing periodic endpoints, or
1104 * supporting transfer phasing to prevent exceeding ISO bandwidth
1105 * limits of a given frame or microframe.
1106 *
1107 * It's not needed for peripheral side, which dedicates endpoints;
1108 * though it _might_ use SOF irqs for other purposes.
1109 *
1110 * And it's not currently needed for host side, which also dedicates
1111 * endpoints, relies on TX/RX interval registers, and isn't claimed
1112 * to support ISO transfers yet.
1113 */
1114 if (int_usb & MUSB_INTR_SOF) {
1115 void __iomem *mbase = musb->mregs;
1116 struct musb_hw_ep *ep;
1117 u8 epnum;
1118 u16 frame;
1119
1120 dev_dbg(musb->controller, "START_OF_FRAME\n");
1121 handled = IRQ_HANDLED;
1122
1123 /* start any periodic Tx transfers waiting for current frame */
1124 frame = musb_readw(mbase, MUSB_FRAME);
1125 ep = musb->endpoints;
1126 for (epnum = 1; (epnum < musb->nr_endpoints)
1127 && (musb->epmask >= (1 << epnum));
1128 epnum++, ep++) {
1129 /*
1130 * FIXME handle framecounter wraps (12 bits)
1131 * eliminate duplicated StartUrb logic
1132 */
1133 if (ep->dwWaitFrame >= frame) {
1134 ep->dwWaitFrame = 0;
1135 pr_debug("SOF --> periodic TX%s on %d\n",
1136 ep->tx_channel ? " DMA" : "",
1137 epnum);
1138 if (!ep->tx_channel)
1139 musb_h_tx_start(musb, epnum);
1140 else
1141 cppi_hostdma_start(musb, epnum);
1142 }
1143 } /* end of for loop */
1144 }
1145#endif
1146
1147 schedule_delayed_work(&musb->irq_work, 0);
1148
1149 return handled;
1150}
1151
1152/*-------------------------------------------------------------------------*/
1153
1154static void musb_disable_interrupts(struct musb *musb)
1155{
1156 void __iomem *mbase = musb->mregs;
1157
1158 /* disable interrupts */
1159 musb_writeb(mbase, MUSB_INTRUSBE, 0);
1160 musb->intrtxe = 0;
1161 musb_writew(mbase, MUSB_INTRTXE, 0);
1162 musb->intrrxe = 0;
1163 musb_writew(mbase, MUSB_INTRRXE, 0);
1164
1165 /* flush pending interrupts */
1166 musb_clearb(mbase, MUSB_INTRUSB);
1167 musb_clearw(mbase, MUSB_INTRTX);
1168 musb_clearw(mbase, MUSB_INTRRX);
1169}
1170
1171static void musb_enable_interrupts(struct musb *musb)
1172{
1173 void __iomem *regs = musb->mregs;
1174
1175 /* Set INT enable registers, enable interrupts */
1176 musb->intrtxe = musb->epmask;
1177 musb_writew(regs, MUSB_INTRTXE, musb->intrtxe);
1178 musb->intrrxe = musb->epmask & 0xfffe;
1179 musb_writew(regs, MUSB_INTRRXE, musb->intrrxe);
1180 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
1181
1182}
1183
1184/*
1185 * Program the HDRC to start (enable interrupts, dma, etc.).
1186 */
1187void musb_start(struct musb *musb)
1188{
1189 void __iomem *regs = musb->mregs;
1190 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
1191 u8 power;
1192
1193 musb_dbg(musb, "<== devctl %02x", devctl);
1194
1195 musb_enable_interrupts(musb);
1196 musb_writeb(regs, MUSB_TESTMODE, 0);
1197
1198 power = MUSB_POWER_ISOUPDATE;
1199 /*
1200 * treating UNKNOWN as unspecified maximum speed, in which case
1201 * we will default to high-speed.
1202 */
1203 if (musb->config->maximum_speed == USB_SPEED_HIGH ||
1204 musb->config->maximum_speed == USB_SPEED_UNKNOWN)
1205 power |= MUSB_POWER_HSENAB;
1206 musb_writeb(regs, MUSB_POWER, power);
1207
1208 musb->is_active = 0;
1209 devctl = musb_readb(regs, MUSB_DEVCTL);
1210 devctl &= ~MUSB_DEVCTL_SESSION;
1211
1212 /* session started after:
1213 * (a) ID-grounded irq, host mode;
1214 * (b) vbus present/connect IRQ, peripheral mode;
1215 * (c) peripheral initiates, using SRP
1216 */
1217 if (musb->port_mode != MUSB_HOST &&
1218 musb->xceiv->otg->state != OTG_STATE_A_WAIT_BCON &&
1219 (devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) {
1220 musb->is_active = 1;
1221 } else {
1222 devctl |= MUSB_DEVCTL_SESSION;
1223 }
1224
1225 musb_platform_enable(musb);
1226 musb_writeb(regs, MUSB_DEVCTL, devctl);
1227}
1228
1229/*
1230 * Make the HDRC stop (disable interrupts, etc.);
1231 * reversible by musb_start
1232 * called on gadget driver unregister
1233 * with controller locked, irqs blocked
1234 * acts as a NOP unless some role activated the hardware
1235 */
1236void musb_stop(struct musb *musb)
1237{
1238 /* stop IRQs, timers, ... */
1239 musb_platform_disable(musb);
1240 musb_disable_interrupts(musb);
1241 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1242
1243 /* FIXME
1244 * - mark host and/or peripheral drivers unusable/inactive
1245 * - disable DMA (and enable it in HdrcStart)
1246 * - make sure we can musb_start() after musb_stop(); with
1247 * OTG mode, gadget driver module rmmod/modprobe cycles that
1248 * - ...
1249 */
1250 musb_platform_try_idle(musb, 0);
1251}
1252
1253/*-------------------------------------------------------------------------*/
1254
1255/*
1256 * The silicon either has hard-wired endpoint configurations, or else
1257 * "dynamic fifo" sizing. The driver has support for both, though at this
1258 * writing only the dynamic sizing is very well tested. Since we switched
1259 * away from compile-time hardware parameters, we can no longer rely on
1260 * dead code elimination to leave only the relevant one in the object file.
1261 *
1262 * We don't currently use dynamic fifo setup capability to do anything
1263 * more than selecting one of a bunch of predefined configurations.
1264 */
1265static ushort fifo_mode;
1266
1267/* "modprobe ... fifo_mode=1" etc */
1268module_param(fifo_mode, ushort, 0);
1269MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1270
1271/*
1272 * tables defining fifo_mode values. define more if you like.
1273 * for host side, make sure both halves of ep1 are set up.
1274 */
1275
1276/* mode 0 - fits in 2KB */
1277static struct musb_fifo_cfg mode_0_cfg[] = {
1278{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1279{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1280{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1281{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1282{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1283};
1284
1285/* mode 1 - fits in 4KB */
1286static struct musb_fifo_cfg mode_1_cfg[] = {
1287{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1288{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1289{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1290{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1291{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1292};
1293
1294/* mode 2 - fits in 4KB */
1295static struct musb_fifo_cfg mode_2_cfg[] = {
1296{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1297{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1298{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1299{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1300{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 960, },
1301{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 1024, },
1302};
1303
1304/* mode 3 - fits in 4KB */
1305static struct musb_fifo_cfg mode_3_cfg[] = {
1306{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1307{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1308{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1309{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1310{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1311{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1312};
1313
1314/* mode 4 - fits in 16KB */
1315static struct musb_fifo_cfg mode_4_cfg[] = {
1316{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1317{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1318{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1319{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1320{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1321{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1322{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1323{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1324{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1325{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1326{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1327{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1328{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1329{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1330{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1331{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1332{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1333{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1334{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1335{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1336{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1337{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1338{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1339{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1340{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1341{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1342{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1343};
1344
1345/* mode 5 - fits in 8KB */
1346static struct musb_fifo_cfg mode_5_cfg[] = {
1347{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1348{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1349{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1350{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1351{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1352{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1353{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1354{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1355{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1356{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1357{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1358{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1359{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1360{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1361{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1362{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1363{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1364{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1365{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1366{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1367{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1368{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1369{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1370{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1371{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1372{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1373{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1374};
1375
1376/*
1377 * configure a fifo; for non-shared endpoints, this may be called
1378 * once for a tx fifo and once for an rx fifo.
1379 *
1380 * returns negative errno or offset for next fifo.
1381 */
1382static int
1383fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1384 const struct musb_fifo_cfg *cfg, u16 offset)
1385{
1386 void __iomem *mbase = musb->mregs;
1387 int size = 0;
1388 u16 maxpacket = cfg->maxpacket;
1389 u16 c_off = offset >> 3;
1390 u8 c_size;
1391
1392 /* expect hw_ep has already been zero-initialized */
1393
1394 size = ffs(max(maxpacket, (u16) 8)) - 1;
1395 maxpacket = 1 << size;
1396
1397 c_size = size - 3;
1398 if (cfg->mode == BUF_DOUBLE) {
1399 if ((offset + (maxpacket << 1)) >
1400 (1 << (musb->config->ram_bits + 2)))
1401 return -EMSGSIZE;
1402 c_size |= MUSB_FIFOSZ_DPB;
1403 } else {
1404 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1405 return -EMSGSIZE;
1406 }
1407
1408 /* configure the FIFO */
1409 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1410
1411 /* EP0 reserved endpoint for control, bidirectional;
1412 * EP1 reserved for bulk, two unidirectional halves.
1413 */
1414 if (hw_ep->epnum == 1)
1415 musb->bulk_ep = hw_ep;
1416 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1417 switch (cfg->style) {
1418 case FIFO_TX:
1419 musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
1420 musb_writew(mbase, MUSB_TXFIFOADD, c_off);
1421 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1422 hw_ep->max_packet_sz_tx = maxpacket;
1423 break;
1424 case FIFO_RX:
1425 musb_writeb(mbase, MUSB_RXFIFOSZ, c_size);
1426 musb_writew(mbase, MUSB_RXFIFOADD, c_off);
1427 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1428 hw_ep->max_packet_sz_rx = maxpacket;
1429 break;
1430 case FIFO_RXTX:
1431 musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
1432 musb_writew(mbase, MUSB_TXFIFOADD, c_off);
1433 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1434 hw_ep->max_packet_sz_rx = maxpacket;
1435
1436 musb_writeb(mbase, MUSB_RXFIFOSZ, c_size);
1437 musb_writew(mbase, MUSB_RXFIFOADD, c_off);
1438 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1439 hw_ep->max_packet_sz_tx = maxpacket;
1440
1441 hw_ep->is_shared_fifo = true;
1442 break;
1443 }
1444
1445 /* NOTE rx and tx endpoint irqs aren't managed separately,
1446 * which happens to be ok
1447 */
1448 musb->epmask |= (1 << hw_ep->epnum);
1449
1450 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1451}
1452
1453static struct musb_fifo_cfg ep0_cfg = {
1454 .style = FIFO_RXTX, .maxpacket = 64,
1455};
1456
1457static int ep_config_from_table(struct musb *musb)
1458{
1459 const struct musb_fifo_cfg *cfg;
1460 unsigned i, n;
1461 int offset;
1462 struct musb_hw_ep *hw_ep = musb->endpoints;
1463
1464 if (musb->config->fifo_cfg) {
1465 cfg = musb->config->fifo_cfg;
1466 n = musb->config->fifo_cfg_size;
1467 goto done;
1468 }
1469
1470 switch (fifo_mode) {
1471 default:
1472 fifo_mode = 0;
1473 fallthrough;
1474 case 0:
1475 cfg = mode_0_cfg;
1476 n = ARRAY_SIZE(mode_0_cfg);
1477 break;
1478 case 1:
1479 cfg = mode_1_cfg;
1480 n = ARRAY_SIZE(mode_1_cfg);
1481 break;
1482 case 2:
1483 cfg = mode_2_cfg;
1484 n = ARRAY_SIZE(mode_2_cfg);
1485 break;
1486 case 3:
1487 cfg = mode_3_cfg;
1488 n = ARRAY_SIZE(mode_3_cfg);
1489 break;
1490 case 4:
1491 cfg = mode_4_cfg;
1492 n = ARRAY_SIZE(mode_4_cfg);
1493 break;
1494 case 5:
1495 cfg = mode_5_cfg;
1496 n = ARRAY_SIZE(mode_5_cfg);
1497 break;
1498 }
1499
1500 pr_debug("%s: setup fifo_mode %d\n", musb_driver_name, fifo_mode);
1501
1502
1503done:
1504 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1505 /* assert(offset > 0) */
1506
1507 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1508 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1509 */
1510
1511 for (i = 0; i < n; i++) {
1512 u8 epn = cfg->hw_ep_num;
1513
1514 if (epn >= musb->config->num_eps) {
1515 pr_debug("%s: invalid ep %d\n",
1516 musb_driver_name, epn);
1517 return -EINVAL;
1518 }
1519 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1520 if (offset < 0) {
1521 pr_debug("%s: mem overrun, ep %d\n",
1522 musb_driver_name, epn);
1523 return offset;
1524 }
1525 epn++;
1526 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1527 }
1528
1529 pr_debug("%s: %d/%d max ep, %d/%d memory\n",
1530 musb_driver_name,
1531 n + 1, musb->config->num_eps * 2 - 1,
1532 offset, (1 << (musb->config->ram_bits + 2)));
1533
1534 if (!musb->bulk_ep) {
1535 pr_debug("%s: missing bulk\n", musb_driver_name);
1536 return -EINVAL;
1537 }
1538
1539 return 0;
1540}
1541
1542
1543/*
1544 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1545 * @param musb the controller
1546 */
1547static int ep_config_from_hw(struct musb *musb)
1548{
1549 u8 epnum = 0;
1550 struct musb_hw_ep *hw_ep;
1551 void __iomem *mbase = musb->mregs;
1552 int ret = 0;
1553
1554 musb_dbg(musb, "<== static silicon ep config");
1555
1556 /* FIXME pick up ep0 maxpacket size */
1557
1558 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1559 musb_ep_select(mbase, epnum);
1560 hw_ep = musb->endpoints + epnum;
1561
1562 ret = musb_read_fifosize(musb, hw_ep, epnum);
1563 if (ret < 0)
1564 break;
1565
1566 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1567
1568 /* pick an RX/TX endpoint for bulk */
1569 if (hw_ep->max_packet_sz_tx < 512
1570 || hw_ep->max_packet_sz_rx < 512)
1571 continue;
1572
1573 /* REVISIT: this algorithm is lazy, we should at least
1574 * try to pick a double buffered endpoint.
1575 */
1576 if (musb->bulk_ep)
1577 continue;
1578 musb->bulk_ep = hw_ep;
1579 }
1580
1581 if (!musb->bulk_ep) {
1582 pr_debug("%s: missing bulk\n", musb_driver_name);
1583 return -EINVAL;
1584 }
1585
1586 return 0;
1587}
1588
1589enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1590
1591/* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1592 * configure endpoints, or take their config from silicon
1593 */
1594static int musb_core_init(u16 musb_type, struct musb *musb)
1595{
1596 u8 reg;
1597 char *type;
1598 char aInfo[90];
1599 void __iomem *mbase = musb->mregs;
1600 int status = 0;
1601 int i;
1602
1603 /* log core options (read using indexed model) */
1604 reg = musb_read_configdata(mbase);
1605
1606 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1607 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1608 strcat(aInfo, ", dyn FIFOs");
1609 musb->dyn_fifo = true;
1610 }
1611 if (reg & MUSB_CONFIGDATA_MPRXE) {
1612 strcat(aInfo, ", bulk combine");
1613 musb->bulk_combine = true;
1614 }
1615 if (reg & MUSB_CONFIGDATA_MPTXE) {
1616 strcat(aInfo, ", bulk split");
1617 musb->bulk_split = true;
1618 }
1619 if (reg & MUSB_CONFIGDATA_HBRXE) {
1620 strcat(aInfo, ", HB-ISO Rx");
1621 musb->hb_iso_rx = true;
1622 }
1623 if (reg & MUSB_CONFIGDATA_HBTXE) {
1624 strcat(aInfo, ", HB-ISO Tx");
1625 musb->hb_iso_tx = true;
1626 }
1627 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1628 strcat(aInfo, ", SoftConn");
1629
1630 pr_debug("%s: ConfigData=0x%02x (%s)\n", musb_driver_name, reg, aInfo);
1631
1632 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1633 musb->is_multipoint = 1;
1634 type = "M";
1635 } else {
1636 musb->is_multipoint = 0;
1637 type = "";
1638 if (IS_ENABLED(CONFIG_USB) &&
1639 !IS_ENABLED(CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB)) {
1640 pr_err("%s: kernel must disable external hubs, please fix the configuration\n",
1641 musb_driver_name);
1642 }
1643 }
1644
1645 /* log release info */
1646 musb->hwvers = musb_readw(mbase, MUSB_HWVERS);
1647 pr_debug("%s: %sHDRC RTL version %d.%d%s\n",
1648 musb_driver_name, type, MUSB_HWVERS_MAJOR(musb->hwvers),
1649 MUSB_HWVERS_MINOR(musb->hwvers),
1650 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1651
1652 /* configure ep0 */
1653 musb_configure_ep0(musb);
1654
1655 /* discover endpoint configuration */
1656 musb->nr_endpoints = 1;
1657 musb->epmask = 1;
1658
1659 if (musb->dyn_fifo)
1660 status = ep_config_from_table(musb);
1661 else
1662 status = ep_config_from_hw(musb);
1663
1664 if (status < 0)
1665 return status;
1666
1667 /* finish init, and print endpoint config */
1668 for (i = 0; i < musb->nr_endpoints; i++) {
1669 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1670
1671 hw_ep->fifo = musb->io.fifo_offset(i) + mbase;
1672#if IS_ENABLED(CONFIG_USB_MUSB_TUSB6010)
1673 if (musb->ops->quirks & MUSB_IN_TUSB) {
1674 hw_ep->fifo_async = musb->async + 0x400 +
1675 musb->io.fifo_offset(i);
1676 hw_ep->fifo_sync = musb->sync + 0x400 +
1677 musb->io.fifo_offset(i);
1678 hw_ep->fifo_sync_va =
1679 musb->sync_va + 0x400 + musb->io.fifo_offset(i);
1680
1681 if (i == 0)
1682 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1683 else
1684 hw_ep->conf = mbase + 0x400 +
1685 (((i - 1) & 0xf) << 2);
1686 }
1687#endif
1688
1689 hw_ep->regs = musb->io.ep_offset(i, 0) + mbase;
1690 hw_ep->rx_reinit = 1;
1691 hw_ep->tx_reinit = 1;
1692
1693 if (hw_ep->max_packet_sz_tx) {
1694 musb_dbg(musb, "%s: hw_ep %d%s, %smax %d",
1695 musb_driver_name, i,
1696 hw_ep->is_shared_fifo ? "shared" : "tx",
1697 hw_ep->tx_double_buffered
1698 ? "doublebuffer, " : "",
1699 hw_ep->max_packet_sz_tx);
1700 }
1701 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1702 musb_dbg(musb, "%s: hw_ep %d%s, %smax %d",
1703 musb_driver_name, i,
1704 "rx",
1705 hw_ep->rx_double_buffered
1706 ? "doublebuffer, " : "",
1707 hw_ep->max_packet_sz_rx);
1708 }
1709 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1710 musb_dbg(musb, "hw_ep %d not configured", i);
1711 }
1712
1713 return 0;
1714}
1715
1716/*-------------------------------------------------------------------------*/
1717
1718/*
1719 * handle all the irqs defined by the HDRC core. for now we expect: other
1720 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1721 * will be assigned, and the irq will already have been acked.
1722 *
1723 * called in irq context with spinlock held, irqs blocked
1724 */
1725irqreturn_t musb_interrupt(struct musb *musb)
1726{
1727 irqreturn_t retval = IRQ_NONE;
1728 unsigned long status;
1729 unsigned long epnum;
1730 u8 devctl;
1731
1732 if (!musb->int_usb && !musb->int_tx && !musb->int_rx)
1733 return IRQ_NONE;
1734
1735 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1736
1737 trace_musb_isr(musb);
1738
1739 /**
1740 * According to Mentor Graphics' documentation, flowchart on page 98,
1741 * IRQ should be handled as follows:
1742 *
1743 * . Resume IRQ
1744 * . Session Request IRQ
1745 * . VBUS Error IRQ
1746 * . Suspend IRQ
1747 * . Connect IRQ
1748 * . Disconnect IRQ
1749 * . Reset/Babble IRQ
1750 * . SOF IRQ (we're not using this one)
1751 * . Endpoint 0 IRQ
1752 * . TX Endpoints
1753 * . RX Endpoints
1754 *
1755 * We will be following that flowchart in order to avoid any problems
1756 * that might arise with internal Finite State Machine.
1757 */
1758
1759 if (musb->int_usb)
1760 retval |= musb_stage0_irq(musb, musb->int_usb, devctl);
1761
1762 if (musb->int_tx & 1) {
1763 if (is_host_active(musb))
1764 retval |= musb_h_ep0_irq(musb);
1765 else
1766 retval |= musb_g_ep0_irq(musb);
1767
1768 /* we have just handled endpoint 0 IRQ, clear it */
1769 musb->int_tx &= ~BIT(0);
1770 }
1771
1772 status = musb->int_tx;
1773
1774 for_each_set_bit(epnum, &status, 16) {
1775 retval = IRQ_HANDLED;
1776 if (is_host_active(musb))
1777 musb_host_tx(musb, epnum);
1778 else
1779 musb_g_tx(musb, epnum);
1780 }
1781
1782 status = musb->int_rx;
1783
1784 for_each_set_bit(epnum, &status, 16) {
1785 retval = IRQ_HANDLED;
1786 if (is_host_active(musb))
1787 musb_host_rx(musb, epnum);
1788 else
1789 musb_g_rx(musb, epnum);
1790 }
1791
1792 return retval;
1793}
1794EXPORT_SYMBOL_GPL(musb_interrupt);
1795
1796#ifndef CONFIG_MUSB_PIO_ONLY
1797static bool use_dma = true;
1798
1799/* "modprobe ... use_dma=0" etc */
1800module_param(use_dma, bool, 0644);
1801MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1802
1803void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1804{
1805 /* called with controller lock already held */
1806
1807 if (!epnum) {
1808 if (!is_cppi_enabled(musb)) {
1809 /* endpoint 0 */
1810 if (is_host_active(musb))
1811 musb_h_ep0_irq(musb);
1812 else
1813 musb_g_ep0_irq(musb);
1814 }
1815 } else {
1816 /* endpoints 1..15 */
1817 if (transmit) {
1818 if (is_host_active(musb))
1819 musb_host_tx(musb, epnum);
1820 else
1821 musb_g_tx(musb, epnum);
1822 } else {
1823 /* receive */
1824 if (is_host_active(musb))
1825 musb_host_rx(musb, epnum);
1826 else
1827 musb_g_rx(musb, epnum);
1828 }
1829 }
1830}
1831EXPORT_SYMBOL_GPL(musb_dma_completion);
1832
1833#else
1834#define use_dma 0
1835#endif
1836
1837static int (*musb_phy_callback)(enum musb_vbus_id_status status);
1838
1839/*
1840 * musb_mailbox - optional phy notifier function
1841 * @status phy state change
1842 *
1843 * Optionally gets called from the USB PHY. Note that the USB PHY must be
1844 * disabled at the point the phy_callback is registered or unregistered.
1845 */
1846int musb_mailbox(enum musb_vbus_id_status status)
1847{
1848 if (musb_phy_callback)
1849 return musb_phy_callback(status);
1850
1851 return -ENODEV;
1852};
1853EXPORT_SYMBOL_GPL(musb_mailbox);
1854
1855/*-------------------------------------------------------------------------*/
1856
1857static ssize_t
1858mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1859{
1860 struct musb *musb = dev_to_musb(dev);
1861 unsigned long flags;
1862 int ret;
1863
1864 spin_lock_irqsave(&musb->lock, flags);
1865 ret = sprintf(buf, "%s\n", usb_otg_state_string(musb->xceiv->otg->state));
1866 spin_unlock_irqrestore(&musb->lock, flags);
1867
1868 return ret;
1869}
1870
1871static ssize_t
1872mode_store(struct device *dev, struct device_attribute *attr,
1873 const char *buf, size_t n)
1874{
1875 struct musb *musb = dev_to_musb(dev);
1876 unsigned long flags;
1877 int status;
1878
1879 spin_lock_irqsave(&musb->lock, flags);
1880 if (sysfs_streq(buf, "host"))
1881 status = musb_platform_set_mode(musb, MUSB_HOST);
1882 else if (sysfs_streq(buf, "peripheral"))
1883 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1884 else if (sysfs_streq(buf, "otg"))
1885 status = musb_platform_set_mode(musb, MUSB_OTG);
1886 else
1887 status = -EINVAL;
1888 spin_unlock_irqrestore(&musb->lock, flags);
1889
1890 return (status == 0) ? n : status;
1891}
1892static DEVICE_ATTR_RW(mode);
1893
1894static ssize_t
1895vbus_store(struct device *dev, struct device_attribute *attr,
1896 const char *buf, size_t n)
1897{
1898 struct musb *musb = dev_to_musb(dev);
1899 unsigned long flags;
1900 unsigned long val;
1901
1902 if (sscanf(buf, "%lu", &val) < 1) {
1903 dev_err(dev, "Invalid VBUS timeout ms value\n");
1904 return -EINVAL;
1905 }
1906
1907 spin_lock_irqsave(&musb->lock, flags);
1908 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1909 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1910 if (musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)
1911 musb->is_active = 0;
1912 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1913 spin_unlock_irqrestore(&musb->lock, flags);
1914
1915 return n;
1916}
1917
1918static ssize_t
1919vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1920{
1921 struct musb *musb = dev_to_musb(dev);
1922 unsigned long flags;
1923 unsigned long val;
1924 int vbus;
1925 u8 devctl;
1926
1927 pm_runtime_get_sync(dev);
1928 spin_lock_irqsave(&musb->lock, flags);
1929 val = musb->a_wait_bcon;
1930 vbus = musb_platform_get_vbus_status(musb);
1931 if (vbus < 0) {
1932 /* Use default MUSB method by means of DEVCTL register */
1933 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1934 if ((devctl & MUSB_DEVCTL_VBUS)
1935 == (3 << MUSB_DEVCTL_VBUS_SHIFT))
1936 vbus = 1;
1937 else
1938 vbus = 0;
1939 }
1940 spin_unlock_irqrestore(&musb->lock, flags);
1941 pm_runtime_put_sync(dev);
1942
1943 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1944 vbus ? "on" : "off", val);
1945}
1946static DEVICE_ATTR_RW(vbus);
1947
1948/* Gadget drivers can't know that a host is connected so they might want
1949 * to start SRP, but users can. This allows userspace to trigger SRP.
1950 */
1951static ssize_t srp_store(struct device *dev, struct device_attribute *attr,
1952 const char *buf, size_t n)
1953{
1954 struct musb *musb = dev_to_musb(dev);
1955 unsigned short srp;
1956
1957 if (sscanf(buf, "%hu", &srp) != 1
1958 || (srp != 1)) {
1959 dev_err(dev, "SRP: Value must be 1\n");
1960 return -EINVAL;
1961 }
1962
1963 if (srp == 1)
1964 musb_g_wakeup(musb);
1965
1966 return n;
1967}
1968static DEVICE_ATTR_WO(srp);
1969
1970static struct attribute *musb_attrs[] = {
1971 &dev_attr_mode.attr,
1972 &dev_attr_vbus.attr,
1973 &dev_attr_srp.attr,
1974 NULL
1975};
1976ATTRIBUTE_GROUPS(musb);
1977
1978#define MUSB_QUIRK_B_INVALID_VBUS_91 (MUSB_DEVCTL_BDEVICE | \
1979 (2 << MUSB_DEVCTL_VBUS_SHIFT) | \
1980 MUSB_DEVCTL_SESSION)
1981#define MUSB_QUIRK_B_DISCONNECT_99 (MUSB_DEVCTL_BDEVICE | \
1982 (3 << MUSB_DEVCTL_VBUS_SHIFT) | \
1983 MUSB_DEVCTL_SESSION)
1984#define MUSB_QUIRK_A_DISCONNECT_19 ((3 << MUSB_DEVCTL_VBUS_SHIFT) | \
1985 MUSB_DEVCTL_SESSION)
1986
1987/*
1988 * Check the musb devctl session bit to determine if we want to
1989 * allow PM runtime for the device. In general, we want to keep things
1990 * active when the session bit is set except after host disconnect.
1991 *
1992 * Only called from musb_irq_work. If this ever needs to get called
1993 * elsewhere, proper locking must be implemented for musb->session.
1994 */
1995static void musb_pm_runtime_check_session(struct musb *musb)
1996{
1997 u8 devctl, s;
1998 int error;
1999
2000 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2001
2002 /* Handle session status quirks first */
2003 s = MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV |
2004 MUSB_DEVCTL_HR;
2005 switch (devctl & ~s) {
2006 case MUSB_QUIRK_B_DISCONNECT_99:
2007 musb_dbg(musb, "Poll devctl in case of suspend after disconnect\n");
2008 schedule_delayed_work(&musb->irq_work,
2009 msecs_to_jiffies(1000));
2010 break;
2011 case MUSB_QUIRK_B_INVALID_VBUS_91:
2012 if (musb->quirk_retries && !musb->flush_irq_work) {
2013 musb_dbg(musb,
2014 "Poll devctl on invalid vbus, assume no session");
2015 schedule_delayed_work(&musb->irq_work,
2016 msecs_to_jiffies(1000));
2017 musb->quirk_retries--;
2018 return;
2019 }
2020 fallthrough;
2021 case MUSB_QUIRK_A_DISCONNECT_19:
2022 if (musb->quirk_retries && !musb->flush_irq_work) {
2023 musb_dbg(musb,
2024 "Poll devctl on possible host mode disconnect");
2025 schedule_delayed_work(&musb->irq_work,
2026 msecs_to_jiffies(1000));
2027 musb->quirk_retries--;
2028 return;
2029 }
2030 if (!musb->session)
2031 break;
2032 musb_dbg(musb, "Allow PM on possible host mode disconnect");
2033 pm_runtime_mark_last_busy(musb->controller);
2034 pm_runtime_put_autosuspend(musb->controller);
2035 musb->session = false;
2036 return;
2037 default:
2038 break;
2039 }
2040
2041 /* No need to do anything if session has not changed */
2042 s = devctl & MUSB_DEVCTL_SESSION;
2043 if (s == musb->session)
2044 return;
2045
2046 /* Block PM or allow PM? */
2047 if (s) {
2048 musb_dbg(musb, "Block PM on active session: %02x", devctl);
2049 error = pm_runtime_get_sync(musb->controller);
2050 if (error < 0)
2051 dev_err(musb->controller, "Could not enable: %i\n",
2052 error);
2053 musb->quirk_retries = 3;
2054 } else {
2055 musb_dbg(musb, "Allow PM with no session: %02x", devctl);
2056 pm_runtime_mark_last_busy(musb->controller);
2057 pm_runtime_put_autosuspend(musb->controller);
2058 }
2059
2060 musb->session = s;
2061}
2062
2063/* Only used to provide driver mode change events */
2064static void musb_irq_work(struct work_struct *data)
2065{
2066 struct musb *musb = container_of(data, struct musb, irq_work.work);
2067 int error;
2068
2069 error = pm_runtime_get_sync(musb->controller);
2070 if (error < 0) {
2071 dev_err(musb->controller, "Could not enable: %i\n", error);
2072
2073 return;
2074 }
2075
2076 musb_pm_runtime_check_session(musb);
2077
2078 if (musb->xceiv->otg->state != musb->xceiv_old_state) {
2079 musb->xceiv_old_state = musb->xceiv->otg->state;
2080 sysfs_notify(&musb->controller->kobj, NULL, "mode");
2081 }
2082
2083 pm_runtime_mark_last_busy(musb->controller);
2084 pm_runtime_put_autosuspend(musb->controller);
2085}
2086
2087static void musb_recover_from_babble(struct musb *musb)
2088{
2089 int ret;
2090 u8 devctl;
2091
2092 musb_disable_interrupts(musb);
2093
2094 /*
2095 * wait at least 320 cycles of 60MHz clock. That's 5.3us, we will give
2096 * it some slack and wait for 10us.
2097 */
2098 udelay(10);
2099
2100 ret = musb_platform_recover(musb);
2101 if (ret) {
2102 musb_enable_interrupts(musb);
2103 return;
2104 }
2105
2106 /* drop session bit */
2107 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2108 devctl &= ~MUSB_DEVCTL_SESSION;
2109 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
2110
2111 /* tell usbcore about it */
2112 musb_root_disconnect(musb);
2113
2114 /*
2115 * When a babble condition occurs, the musb controller
2116 * removes the session bit and the endpoint config is lost.
2117 */
2118 if (musb->dyn_fifo)
2119 ret = ep_config_from_table(musb);
2120 else
2121 ret = ep_config_from_hw(musb);
2122
2123 /* restart session */
2124 if (ret == 0)
2125 musb_start(musb);
2126}
2127
2128/* --------------------------------------------------------------------------
2129 * Init support
2130 */
2131
2132static struct musb *allocate_instance(struct device *dev,
2133 const struct musb_hdrc_config *config, void __iomem *mbase)
2134{
2135 struct musb *musb;
2136 struct musb_hw_ep *ep;
2137 int epnum;
2138 int ret;
2139
2140 musb = devm_kzalloc(dev, sizeof(*musb), GFP_KERNEL);
2141 if (!musb)
2142 return NULL;
2143
2144 INIT_LIST_HEAD(&musb->control);
2145 INIT_LIST_HEAD(&musb->in_bulk);
2146 INIT_LIST_HEAD(&musb->out_bulk);
2147 INIT_LIST_HEAD(&musb->pending_list);
2148
2149 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
2150 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
2151 musb->mregs = mbase;
2152 musb->ctrl_base = mbase;
2153 musb->nIrq = -ENODEV;
2154 musb->config = config;
2155 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
2156 for (epnum = 0, ep = musb->endpoints;
2157 epnum < musb->config->num_eps;
2158 epnum++, ep++) {
2159 ep->musb = musb;
2160 ep->epnum = epnum;
2161 }
2162
2163 musb->controller = dev;
2164
2165 ret = musb_host_alloc(musb);
2166 if (ret < 0)
2167 goto err_free;
2168
2169 dev_set_drvdata(dev, musb);
2170
2171 return musb;
2172
2173err_free:
2174 return NULL;
2175}
2176
2177static void musb_free(struct musb *musb)
2178{
2179 /* this has multiple entry modes. it handles fault cleanup after
2180 * probe(), where things may be partially set up, as well as rmmod
2181 * cleanup after everything's been de-activated.
2182 */
2183
2184 if (musb->nIrq >= 0) {
2185 if (musb->irq_wake)
2186 disable_irq_wake(musb->nIrq);
2187 free_irq(musb->nIrq, musb);
2188 }
2189
2190 musb_host_free(musb);
2191}
2192
2193struct musb_pending_work {
2194 int (*callback)(struct musb *musb, void *data);
2195 void *data;
2196 struct list_head node;
2197};
2198
2199#ifdef CONFIG_PM
2200/*
2201 * Called from musb_runtime_resume(), musb_resume(), and
2202 * musb_queue_resume_work(). Callers must take musb->lock.
2203 */
2204static int musb_run_resume_work(struct musb *musb)
2205{
2206 struct musb_pending_work *w, *_w;
2207 unsigned long flags;
2208 int error = 0;
2209
2210 spin_lock_irqsave(&musb->list_lock, flags);
2211 list_for_each_entry_safe(w, _w, &musb->pending_list, node) {
2212 if (w->callback) {
2213 error = w->callback(musb, w->data);
2214 if (error < 0) {
2215 dev_err(musb->controller,
2216 "resume callback %p failed: %i\n",
2217 w->callback, error);
2218 }
2219 }
2220 list_del(&w->node);
2221 devm_kfree(musb->controller, w);
2222 }
2223 spin_unlock_irqrestore(&musb->list_lock, flags);
2224
2225 return error;
2226}
2227#endif
2228
2229/*
2230 * Called to run work if device is active or else queue the work to happen
2231 * on resume. Caller must take musb->lock and must hold an RPM reference.
2232 *
2233 * Note that we cowardly refuse queuing work after musb PM runtime
2234 * resume is done calling musb_run_resume_work() and return -EINPROGRESS
2235 * instead.
2236 */
2237int musb_queue_resume_work(struct musb *musb,
2238 int (*callback)(struct musb *musb, void *data),
2239 void *data)
2240{
2241 struct musb_pending_work *w;
2242 unsigned long flags;
2243 int error;
2244
2245 if (WARN_ON(!callback))
2246 return -EINVAL;
2247
2248 if (pm_runtime_active(musb->controller))
2249 return callback(musb, data);
2250
2251 w = devm_kzalloc(musb->controller, sizeof(*w), GFP_ATOMIC);
2252 if (!w)
2253 return -ENOMEM;
2254
2255 w->callback = callback;
2256 w->data = data;
2257 spin_lock_irqsave(&musb->list_lock, flags);
2258 if (musb->is_runtime_suspended) {
2259 list_add_tail(&w->node, &musb->pending_list);
2260 error = 0;
2261 } else {
2262 dev_err(musb->controller, "could not add resume work %p\n",
2263 callback);
2264 devm_kfree(musb->controller, w);
2265 error = -EINPROGRESS;
2266 }
2267 spin_unlock_irqrestore(&musb->list_lock, flags);
2268
2269 return error;
2270}
2271EXPORT_SYMBOL_GPL(musb_queue_resume_work);
2272
2273static void musb_deassert_reset(struct work_struct *work)
2274{
2275 struct musb *musb;
2276 unsigned long flags;
2277
2278 musb = container_of(work, struct musb, deassert_reset_work.work);
2279
2280 spin_lock_irqsave(&musb->lock, flags);
2281
2282 if (musb->port1_status & USB_PORT_STAT_RESET)
2283 musb_port_reset(musb, false);
2284
2285 spin_unlock_irqrestore(&musb->lock, flags);
2286}
2287
2288/*
2289 * Perform generic per-controller initialization.
2290 *
2291 * @dev: the controller (already clocked, etc)
2292 * @nIrq: IRQ number
2293 * @ctrl: virtual address of controller registers,
2294 * not yet corrected for platform-specific offsets
2295 */
2296static int
2297musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
2298{
2299 int status;
2300 struct musb *musb;
2301 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
2302
2303 /* The driver might handle more features than the board; OK.
2304 * Fail when the board needs a feature that's not enabled.
2305 */
2306 if (!plat) {
2307 dev_err(dev, "no platform_data?\n");
2308 status = -ENODEV;
2309 goto fail0;
2310 }
2311
2312 /* allocate */
2313 musb = allocate_instance(dev, plat->config, ctrl);
2314 if (!musb) {
2315 status = -ENOMEM;
2316 goto fail0;
2317 }
2318
2319 spin_lock_init(&musb->lock);
2320 spin_lock_init(&musb->list_lock);
2321 musb->board_set_power = plat->set_power;
2322 musb->min_power = plat->min_power;
2323 musb->ops = plat->platform_ops;
2324 musb->port_mode = plat->mode;
2325
2326 /*
2327 * Initialize the default IO functions. At least omap2430 needs
2328 * these early. We initialize the platform specific IO functions
2329 * later on.
2330 */
2331 musb_readb = musb_default_readb;
2332 musb_writeb = musb_default_writeb;
2333 musb_readw = musb_default_readw;
2334 musb_writew = musb_default_writew;
2335
2336 /* The musb_platform_init() call:
2337 * - adjusts musb->mregs
2338 * - sets the musb->isr
2339 * - may initialize an integrated transceiver
2340 * - initializes musb->xceiv, usually by otg_get_phy()
2341 * - stops powering VBUS
2342 *
2343 * There are various transceiver configurations.
2344 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
2345 * external/discrete ones in various flavors (twl4030 family,
2346 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
2347 */
2348 status = musb_platform_init(musb);
2349 if (status < 0)
2350 goto fail1;
2351
2352 if (!musb->isr) {
2353 status = -ENODEV;
2354 goto fail2;
2355 }
2356
2357
2358 /* Most devices use indexed offset or flat offset */
2359 if (musb->ops->quirks & MUSB_INDEXED_EP) {
2360 musb->io.ep_offset = musb_indexed_ep_offset;
2361 musb->io.ep_select = musb_indexed_ep_select;
2362 } else {
2363 musb->io.ep_offset = musb_flat_ep_offset;
2364 musb->io.ep_select = musb_flat_ep_select;
2365 }
2366
2367 if (musb->ops->quirks & MUSB_G_NO_SKB_RESERVE)
2368 musb->g.quirk_avoids_skb_reserve = 1;
2369
2370 /* At least tusb6010 has its own offsets */
2371 if (musb->ops->ep_offset)
2372 musb->io.ep_offset = musb->ops->ep_offset;
2373 if (musb->ops->ep_select)
2374 musb->io.ep_select = musb->ops->ep_select;
2375
2376 if (musb->ops->fifo_mode)
2377 fifo_mode = musb->ops->fifo_mode;
2378 else
2379 fifo_mode = 4;
2380
2381 if (musb->ops->fifo_offset)
2382 musb->io.fifo_offset = musb->ops->fifo_offset;
2383 else
2384 musb->io.fifo_offset = musb_default_fifo_offset;
2385
2386 if (musb->ops->busctl_offset)
2387 musb->io.busctl_offset = musb->ops->busctl_offset;
2388 else
2389 musb->io.busctl_offset = musb_default_busctl_offset;
2390
2391 if (musb->ops->readb)
2392 musb_readb = musb->ops->readb;
2393 if (musb->ops->writeb)
2394 musb_writeb = musb->ops->writeb;
2395 if (musb->ops->clearb)
2396 musb_clearb = musb->ops->clearb;
2397 else
2398 musb_clearb = musb_readb;
2399
2400 if (musb->ops->readw)
2401 musb_readw = musb->ops->readw;
2402 if (musb->ops->writew)
2403 musb_writew = musb->ops->writew;
2404 if (musb->ops->clearw)
2405 musb_clearw = musb->ops->clearw;
2406 else
2407 musb_clearw = musb_readw;
2408
2409#ifndef CONFIG_MUSB_PIO_ONLY
2410 if (!musb->ops->dma_init || !musb->ops->dma_exit) {
2411 dev_err(dev, "DMA controller not set\n");
2412 status = -ENODEV;
2413 goto fail2;
2414 }
2415 musb_dma_controller_create = musb->ops->dma_init;
2416 musb_dma_controller_destroy = musb->ops->dma_exit;
2417#endif
2418
2419 if (musb->ops->read_fifo)
2420 musb->io.read_fifo = musb->ops->read_fifo;
2421 else
2422 musb->io.read_fifo = musb_default_read_fifo;
2423
2424 if (musb->ops->write_fifo)
2425 musb->io.write_fifo = musb->ops->write_fifo;
2426 else
2427 musb->io.write_fifo = musb_default_write_fifo;
2428
2429 if (musb->ops->get_toggle)
2430 musb->io.get_toggle = musb->ops->get_toggle;
2431 else
2432 musb->io.get_toggle = musb_default_get_toggle;
2433
2434 if (musb->ops->set_toggle)
2435 musb->io.set_toggle = musb->ops->set_toggle;
2436 else
2437 musb->io.set_toggle = musb_default_set_toggle;
2438
2439 if (!musb->xceiv->io_ops) {
2440 musb->xceiv->io_dev = musb->controller;
2441 musb->xceiv->io_priv = musb->mregs;
2442 musb->xceiv->io_ops = &musb_ulpi_access;
2443 }
2444
2445 if (musb->ops->phy_callback)
2446 musb_phy_callback = musb->ops->phy_callback;
2447
2448 /*
2449 * We need musb_read/write functions initialized for PM.
2450 * Note that at least 2430 glue needs autosuspend delay
2451 * somewhere above 300 ms for the hardware to idle properly
2452 * after disconnecting the cable in host mode. Let's use
2453 * 500 ms for some margin.
2454 */
2455 pm_runtime_use_autosuspend(musb->controller);
2456 pm_runtime_set_autosuspend_delay(musb->controller, 500);
2457 pm_runtime_enable(musb->controller);
2458 pm_runtime_get_sync(musb->controller);
2459
2460 status = usb_phy_init(musb->xceiv);
2461 if (status < 0)
2462 goto err_usb_phy_init;
2463
2464 if (use_dma && dev->dma_mask) {
2465 musb->dma_controller =
2466 musb_dma_controller_create(musb, musb->mregs);
2467 if (IS_ERR(musb->dma_controller)) {
2468 status = PTR_ERR(musb->dma_controller);
2469 goto fail2_5;
2470 }
2471 }
2472
2473 /* be sure interrupts are disabled before connecting ISR */
2474 musb_platform_disable(musb);
2475 musb_disable_interrupts(musb);
2476 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
2477
2478 /* MUSB_POWER_SOFTCONN might be already set, JZ4740 does this. */
2479 musb_writeb(musb->mregs, MUSB_POWER, 0);
2480
2481 /* Init IRQ workqueue before request_irq */
2482 INIT_DELAYED_WORK(&musb->irq_work, musb_irq_work);
2483 INIT_DELAYED_WORK(&musb->deassert_reset_work, musb_deassert_reset);
2484 INIT_DELAYED_WORK(&musb->finish_resume_work, musb_host_finish_resume);
2485
2486 /* setup musb parts of the core (especially endpoints) */
2487 status = musb_core_init(plat->config->multipoint
2488 ? MUSB_CONTROLLER_MHDRC
2489 : MUSB_CONTROLLER_HDRC, musb);
2490 if (status < 0)
2491 goto fail3;
2492
2493 timer_setup(&musb->otg_timer, musb_otg_timer_func, 0);
2494
2495 /* attach to the IRQ */
2496 if (request_irq(nIrq, musb->isr, IRQF_SHARED, dev_name(dev), musb)) {
2497 dev_err(dev, "request_irq %d failed!\n", nIrq);
2498 status = -ENODEV;
2499 goto fail3;
2500 }
2501 musb->nIrq = nIrq;
2502 /* FIXME this handles wakeup irqs wrong */
2503 if (enable_irq_wake(nIrq) == 0) {
2504 musb->irq_wake = 1;
2505 device_init_wakeup(dev, 1);
2506 } else {
2507 musb->irq_wake = 0;
2508 }
2509
2510 /* program PHY to use external vBus if required */
2511 if (plat->extvbus) {
2512 u8 busctl = musb_readb(musb->mregs, MUSB_ULPI_BUSCONTROL);
2513 busctl |= MUSB_ULPI_USE_EXTVBUS;
2514 musb_writeb(musb->mregs, MUSB_ULPI_BUSCONTROL, busctl);
2515 }
2516
2517 MUSB_DEV_MODE(musb);
2518 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
2519
2520 switch (musb->port_mode) {
2521 case MUSB_HOST:
2522 status = musb_host_setup(musb, plat->power);
2523 if (status < 0)
2524 goto fail3;
2525 status = musb_platform_set_mode(musb, MUSB_HOST);
2526 break;
2527 case MUSB_PERIPHERAL:
2528 status = musb_gadget_setup(musb);
2529 if (status < 0)
2530 goto fail3;
2531 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
2532 break;
2533 case MUSB_OTG:
2534 status = musb_host_setup(musb, plat->power);
2535 if (status < 0)
2536 goto fail3;
2537 status = musb_gadget_setup(musb);
2538 if (status) {
2539 musb_host_cleanup(musb);
2540 goto fail3;
2541 }
2542 status = musb_platform_set_mode(musb, MUSB_OTG);
2543 break;
2544 default:
2545 dev_err(dev, "unsupported port mode %d\n", musb->port_mode);
2546 break;
2547 }
2548
2549 if (status < 0)
2550 goto fail3;
2551
2552 musb_init_debugfs(musb);
2553
2554 musb->is_initialized = 1;
2555 pm_runtime_mark_last_busy(musb->controller);
2556 pm_runtime_put_autosuspend(musb->controller);
2557
2558 return 0;
2559
2560fail3:
2561 cancel_delayed_work_sync(&musb->irq_work);
2562 cancel_delayed_work_sync(&musb->finish_resume_work);
2563 cancel_delayed_work_sync(&musb->deassert_reset_work);
2564 if (musb->dma_controller)
2565 musb_dma_controller_destroy(musb->dma_controller);
2566
2567fail2_5:
2568 usb_phy_shutdown(musb->xceiv);
2569
2570err_usb_phy_init:
2571 pm_runtime_dont_use_autosuspend(musb->controller);
2572 pm_runtime_put_sync(musb->controller);
2573 pm_runtime_disable(musb->controller);
2574
2575fail2:
2576 if (musb->irq_wake)
2577 device_init_wakeup(dev, 0);
2578 musb_platform_exit(musb);
2579
2580fail1:
2581 if (status != -EPROBE_DEFER)
2582 dev_err(musb->controller,
2583 "%s failed with status %d\n", __func__, status);
2584
2585 musb_free(musb);
2586
2587fail0:
2588
2589 return status;
2590
2591}
2592
2593/*-------------------------------------------------------------------------*/
2594
2595/* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2596 * bridge to a platform device; this driver then suffices.
2597 */
2598static int musb_probe(struct platform_device *pdev)
2599{
2600 struct device *dev = &pdev->dev;
2601 int irq = platform_get_irq_byname(pdev, "mc");
2602 void __iomem *base;
2603
2604 if (irq <= 0)
2605 return -ENODEV;
2606
2607 base = devm_platform_ioremap_resource(pdev, 0);
2608 if (IS_ERR(base))
2609 return PTR_ERR(base);
2610
2611 return musb_init_controller(dev, irq, base);
2612}
2613
2614static int musb_remove(struct platform_device *pdev)
2615{
2616 struct device *dev = &pdev->dev;
2617 struct musb *musb = dev_to_musb(dev);
2618 unsigned long flags;
2619
2620 /* this gets called on rmmod.
2621 * - Host mode: host may still be active
2622 * - Peripheral mode: peripheral is deactivated (or never-activated)
2623 * - OTG mode: both roles are deactivated (or never-activated)
2624 */
2625 musb_exit_debugfs(musb);
2626
2627 cancel_delayed_work_sync(&musb->irq_work);
2628 cancel_delayed_work_sync(&musb->finish_resume_work);
2629 cancel_delayed_work_sync(&musb->deassert_reset_work);
2630 pm_runtime_get_sync(musb->controller);
2631 musb_host_cleanup(musb);
2632 musb_gadget_cleanup(musb);
2633
2634 musb_platform_disable(musb);
2635 spin_lock_irqsave(&musb->lock, flags);
2636 musb_disable_interrupts(musb);
2637 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
2638 spin_unlock_irqrestore(&musb->lock, flags);
2639 musb_platform_exit(musb);
2640
2641 pm_runtime_dont_use_autosuspend(musb->controller);
2642 pm_runtime_put_sync(musb->controller);
2643 pm_runtime_disable(musb->controller);
2644 musb_phy_callback = NULL;
2645 if (musb->dma_controller)
2646 musb_dma_controller_destroy(musb->dma_controller);
2647 usb_phy_shutdown(musb->xceiv);
2648 musb_free(musb);
2649 device_init_wakeup(dev, 0);
2650 return 0;
2651}
2652
2653#ifdef CONFIG_PM
2654
2655static void musb_save_context(struct musb *musb)
2656{
2657 int i;
2658 void __iomem *musb_base = musb->mregs;
2659 void __iomem *epio;
2660
2661 musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2662 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2663 musb->context.busctl = musb_readb(musb_base, MUSB_ULPI_BUSCONTROL);
2664 musb->context.power = musb_readb(musb_base, MUSB_POWER);
2665 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2666 musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2667 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2668
2669 for (i = 0; i < musb->config->num_eps; ++i) {
2670 struct musb_hw_ep *hw_ep;
2671
2672 hw_ep = &musb->endpoints[i];
2673 if (!hw_ep)
2674 continue;
2675
2676 epio = hw_ep->regs;
2677 if (!epio)
2678 continue;
2679
2680 musb_writeb(musb_base, MUSB_INDEX, i);
2681 musb->context.index_regs[i].txmaxp =
2682 musb_readw(epio, MUSB_TXMAXP);
2683 musb->context.index_regs[i].txcsr =
2684 musb_readw(epio, MUSB_TXCSR);
2685 musb->context.index_regs[i].rxmaxp =
2686 musb_readw(epio, MUSB_RXMAXP);
2687 musb->context.index_regs[i].rxcsr =
2688 musb_readw(epio, MUSB_RXCSR);
2689
2690 if (musb->dyn_fifo) {
2691 musb->context.index_regs[i].txfifoadd =
2692 musb_readw(musb_base, MUSB_TXFIFOADD);
2693 musb->context.index_regs[i].rxfifoadd =
2694 musb_readw(musb_base, MUSB_RXFIFOADD);
2695 musb->context.index_regs[i].txfifosz =
2696 musb_readb(musb_base, MUSB_TXFIFOSZ);
2697 musb->context.index_regs[i].rxfifosz =
2698 musb_readb(musb_base, MUSB_RXFIFOSZ);
2699 }
2700
2701 musb->context.index_regs[i].txtype =
2702 musb_readb(epio, MUSB_TXTYPE);
2703 musb->context.index_regs[i].txinterval =
2704 musb_readb(epio, MUSB_TXINTERVAL);
2705 musb->context.index_regs[i].rxtype =
2706 musb_readb(epio, MUSB_RXTYPE);
2707 musb->context.index_regs[i].rxinterval =
2708 musb_readb(epio, MUSB_RXINTERVAL);
2709
2710 musb->context.index_regs[i].txfunaddr =
2711 musb_read_txfunaddr(musb, i);
2712 musb->context.index_regs[i].txhubaddr =
2713 musb_read_txhubaddr(musb, i);
2714 musb->context.index_regs[i].txhubport =
2715 musb_read_txhubport(musb, i);
2716
2717 musb->context.index_regs[i].rxfunaddr =
2718 musb_read_rxfunaddr(musb, i);
2719 musb->context.index_regs[i].rxhubaddr =
2720 musb_read_rxhubaddr(musb, i);
2721 musb->context.index_regs[i].rxhubport =
2722 musb_read_rxhubport(musb, i);
2723 }
2724}
2725
2726static void musb_restore_context(struct musb *musb)
2727{
2728 int i;
2729 void __iomem *musb_base = musb->mregs;
2730 void __iomem *epio;
2731 u8 power;
2732
2733 musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2734 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2735 musb_writeb(musb_base, MUSB_ULPI_BUSCONTROL, musb->context.busctl);
2736
2737 /* Don't affect SUSPENDM/RESUME bits in POWER reg */
2738 power = musb_readb(musb_base, MUSB_POWER);
2739 power &= MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME;
2740 musb->context.power &= ~(MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME);
2741 power |= musb->context.power;
2742 musb_writeb(musb_base, MUSB_POWER, power);
2743
2744 musb_writew(musb_base, MUSB_INTRTXE, musb->intrtxe);
2745 musb_writew(musb_base, MUSB_INTRRXE, musb->intrrxe);
2746 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2747 if (musb->context.devctl & MUSB_DEVCTL_SESSION)
2748 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
2749
2750 for (i = 0; i < musb->config->num_eps; ++i) {
2751 struct musb_hw_ep *hw_ep;
2752
2753 hw_ep = &musb->endpoints[i];
2754 if (!hw_ep)
2755 continue;
2756
2757 epio = hw_ep->regs;
2758 if (!epio)
2759 continue;
2760
2761 musb_writeb(musb_base, MUSB_INDEX, i);
2762 musb_writew(epio, MUSB_TXMAXP,
2763 musb->context.index_regs[i].txmaxp);
2764 musb_writew(epio, MUSB_TXCSR,
2765 musb->context.index_regs[i].txcsr);
2766 musb_writew(epio, MUSB_RXMAXP,
2767 musb->context.index_regs[i].rxmaxp);
2768 musb_writew(epio, MUSB_RXCSR,
2769 musb->context.index_regs[i].rxcsr);
2770
2771 if (musb->dyn_fifo) {
2772 musb_writeb(musb_base, MUSB_TXFIFOSZ,
2773 musb->context.index_regs[i].txfifosz);
2774 musb_writeb(musb_base, MUSB_RXFIFOSZ,
2775 musb->context.index_regs[i].rxfifosz);
2776 musb_writew(musb_base, MUSB_TXFIFOADD,
2777 musb->context.index_regs[i].txfifoadd);
2778 musb_writew(musb_base, MUSB_RXFIFOADD,
2779 musb->context.index_regs[i].rxfifoadd);
2780 }
2781
2782 musb_writeb(epio, MUSB_TXTYPE,
2783 musb->context.index_regs[i].txtype);
2784 musb_writeb(epio, MUSB_TXINTERVAL,
2785 musb->context.index_regs[i].txinterval);
2786 musb_writeb(epio, MUSB_RXTYPE,
2787 musb->context.index_regs[i].rxtype);
2788 musb_writeb(epio, MUSB_RXINTERVAL,
2789
2790 musb->context.index_regs[i].rxinterval);
2791 musb_write_txfunaddr(musb, i,
2792 musb->context.index_regs[i].txfunaddr);
2793 musb_write_txhubaddr(musb, i,
2794 musb->context.index_regs[i].txhubaddr);
2795 musb_write_txhubport(musb, i,
2796 musb->context.index_regs[i].txhubport);
2797
2798 musb_write_rxfunaddr(musb, i,
2799 musb->context.index_regs[i].rxfunaddr);
2800 musb_write_rxhubaddr(musb, i,
2801 musb->context.index_regs[i].rxhubaddr);
2802 musb_write_rxhubport(musb, i,
2803 musb->context.index_regs[i].rxhubport);
2804 }
2805 musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
2806}
2807
2808static int musb_suspend(struct device *dev)
2809{
2810 struct musb *musb = dev_to_musb(dev);
2811 unsigned long flags;
2812 int ret;
2813
2814 ret = pm_runtime_get_sync(dev);
2815 if (ret < 0) {
2816 pm_runtime_put_noidle(dev);
2817 return ret;
2818 }
2819
2820 musb_platform_disable(musb);
2821 musb_disable_interrupts(musb);
2822
2823 musb->flush_irq_work = true;
2824 while (flush_delayed_work(&musb->irq_work))
2825 ;
2826 musb->flush_irq_work = false;
2827
2828 if (!(musb->ops->quirks & MUSB_PRESERVE_SESSION))
2829 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
2830
2831 WARN_ON(!list_empty(&musb->pending_list));
2832
2833 spin_lock_irqsave(&musb->lock, flags);
2834
2835 if (is_peripheral_active(musb)) {
2836 /* FIXME force disconnect unless we know USB will wake
2837 * the system up quickly enough to respond ...
2838 */
2839 } else if (is_host_active(musb)) {
2840 /* we know all the children are suspended; sometimes
2841 * they will even be wakeup-enabled.
2842 */
2843 }
2844
2845 musb_save_context(musb);
2846
2847 spin_unlock_irqrestore(&musb->lock, flags);
2848 return 0;
2849}
2850
2851static int musb_resume(struct device *dev)
2852{
2853 struct musb *musb = dev_to_musb(dev);
2854 unsigned long flags;
2855 int error;
2856 u8 devctl;
2857 u8 mask;
2858
2859 /*
2860 * For static cmos like DaVinci, register values were preserved
2861 * unless for some reason the whole soc powered down or the USB
2862 * module got reset through the PSC (vs just being disabled).
2863 *
2864 * For the DSPS glue layer though, a full register restore has to
2865 * be done. As it shouldn't harm other platforms, we do it
2866 * unconditionally.
2867 */
2868
2869 musb_restore_context(musb);
2870
2871 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2872 mask = MUSB_DEVCTL_BDEVICE | MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV;
2873 if ((devctl & mask) != (musb->context.devctl & mask))
2874 musb->port1_status = 0;
2875
2876 musb_enable_interrupts(musb);
2877 musb_platform_enable(musb);
2878
2879 /* session might be disabled in suspend */
2880 if (musb->port_mode == MUSB_HOST &&
2881 !(musb->ops->quirks & MUSB_PRESERVE_SESSION)) {
2882 devctl |= MUSB_DEVCTL_SESSION;
2883 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
2884 }
2885
2886 spin_lock_irqsave(&musb->lock, flags);
2887 error = musb_run_resume_work(musb);
2888 if (error)
2889 dev_err(musb->controller, "resume work failed with %i\n",
2890 error);
2891 spin_unlock_irqrestore(&musb->lock, flags);
2892
2893 pm_runtime_mark_last_busy(dev);
2894 pm_runtime_put_autosuspend(dev);
2895
2896 return 0;
2897}
2898
2899static int musb_runtime_suspend(struct device *dev)
2900{
2901 struct musb *musb = dev_to_musb(dev);
2902
2903 musb_save_context(musb);
2904 musb->is_runtime_suspended = 1;
2905
2906 return 0;
2907}
2908
2909static int musb_runtime_resume(struct device *dev)
2910{
2911 struct musb *musb = dev_to_musb(dev);
2912 unsigned long flags;
2913 int error;
2914
2915 /*
2916 * When pm_runtime_get_sync called for the first time in driver
2917 * init, some of the structure is still not initialized which is
2918 * used in restore function. But clock needs to be
2919 * enabled before any register access, so
2920 * pm_runtime_get_sync has to be called.
2921 * Also context restore without save does not make
2922 * any sense
2923 */
2924 if (!musb->is_initialized)
2925 return 0;
2926
2927 musb_restore_context(musb);
2928
2929 spin_lock_irqsave(&musb->lock, flags);
2930 error = musb_run_resume_work(musb);
2931 if (error)
2932 dev_err(musb->controller, "resume work failed with %i\n",
2933 error);
2934 musb->is_runtime_suspended = 0;
2935 spin_unlock_irqrestore(&musb->lock, flags);
2936
2937 return 0;
2938}
2939
2940static const struct dev_pm_ops musb_dev_pm_ops = {
2941 .suspend = musb_suspend,
2942 .resume = musb_resume,
2943 .runtime_suspend = musb_runtime_suspend,
2944 .runtime_resume = musb_runtime_resume,
2945};
2946
2947#define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2948#else
2949#define MUSB_DEV_PM_OPS NULL
2950#endif
2951
2952static struct platform_driver musb_driver = {
2953 .driver = {
2954 .name = musb_driver_name,
2955 .bus = &platform_bus_type,
2956 .pm = MUSB_DEV_PM_OPS,
2957 .dev_groups = musb_groups,
2958 },
2959 .probe = musb_probe,
2960 .remove = musb_remove,
2961};
2962
2963module_platform_driver(musb_driver);