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1/*
2 * Copyright (C) 2014 Traphandler
3 * Copyright (C) 2014 Free Electrons
4 * Copyright (C) 2014 Atmel
5 *
6 * Author: Jean-Jacques Hiblot <jjhiblot@traphandler.com>
7 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#include <linux/clk.h>
23#include <linux/irq.h>
24#include <linux/irqchip.h>
25#include <linux/module.h>
26#include <linux/pm_runtime.h>
27
28#include "atmel_hlcdc_dc.h"
29
30#define ATMEL_HLCDC_LAYER_IRQS_OFFSET 8
31
32static const struct atmel_hlcdc_layer_desc atmel_hlcdc_at91sam9n12_layers[] = {
33 {
34 .name = "base",
35 .formats = &atmel_hlcdc_plane_rgb_formats,
36 .regs_offset = 0x40,
37 .id = 0,
38 .type = ATMEL_HLCDC_BASE_LAYER,
39 .nconfigs = 5,
40 .layout = {
41 .xstride = { 2 },
42 .default_color = 3,
43 .general_config = 4,
44 },
45 },
46};
47
48static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_at91sam9n12 = {
49 .min_width = 0,
50 .min_height = 0,
51 .max_width = 1280,
52 .max_height = 860,
53 .nlayers = ARRAY_SIZE(atmel_hlcdc_at91sam9n12_layers),
54 .layers = atmel_hlcdc_at91sam9n12_layers,
55};
56
57static const struct atmel_hlcdc_layer_desc atmel_hlcdc_at91sam9x5_layers[] = {
58 {
59 .name = "base",
60 .formats = &atmel_hlcdc_plane_rgb_formats,
61 .regs_offset = 0x40,
62 .id = 0,
63 .type = ATMEL_HLCDC_BASE_LAYER,
64 .nconfigs = 5,
65 .layout = {
66 .xstride = { 2 },
67 .default_color = 3,
68 .general_config = 4,
69 .disc_pos = 5,
70 .disc_size = 6,
71 },
72 },
73 {
74 .name = "overlay1",
75 .formats = &atmel_hlcdc_plane_rgb_formats,
76 .regs_offset = 0x100,
77 .id = 1,
78 .type = ATMEL_HLCDC_OVERLAY_LAYER,
79 .nconfigs = 10,
80 .layout = {
81 .pos = 2,
82 .size = 3,
83 .xstride = { 4 },
84 .pstride = { 5 },
85 .default_color = 6,
86 .chroma_key = 7,
87 .chroma_key_mask = 8,
88 .general_config = 9,
89 },
90 },
91 {
92 .name = "high-end-overlay",
93 .formats = &atmel_hlcdc_plane_rgb_and_yuv_formats,
94 .regs_offset = 0x280,
95 .id = 2,
96 .type = ATMEL_HLCDC_OVERLAY_LAYER,
97 .nconfigs = 17,
98 .layout = {
99 .pos = 2,
100 .size = 3,
101 .memsize = 4,
102 .xstride = { 5, 7 },
103 .pstride = { 6, 8 },
104 .default_color = 9,
105 .chroma_key = 10,
106 .chroma_key_mask = 11,
107 .general_config = 12,
108 .csc = 14,
109 },
110 },
111 {
112 .name = "cursor",
113 .formats = &atmel_hlcdc_plane_rgb_formats,
114 .regs_offset = 0x340,
115 .id = 3,
116 .type = ATMEL_HLCDC_CURSOR_LAYER,
117 .nconfigs = 10,
118 .max_width = 128,
119 .max_height = 128,
120 .layout = {
121 .pos = 2,
122 .size = 3,
123 .xstride = { 4 },
124 .default_color = 6,
125 .chroma_key = 7,
126 .chroma_key_mask = 8,
127 .general_config = 9,
128 },
129 },
130};
131
132static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_at91sam9x5 = {
133 .min_width = 0,
134 .min_height = 0,
135 .max_width = 800,
136 .max_height = 600,
137 .nlayers = ARRAY_SIZE(atmel_hlcdc_at91sam9x5_layers),
138 .layers = atmel_hlcdc_at91sam9x5_layers,
139};
140
141static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sama5d3_layers[] = {
142 {
143 .name = "base",
144 .formats = &atmel_hlcdc_plane_rgb_formats,
145 .regs_offset = 0x40,
146 .id = 0,
147 .type = ATMEL_HLCDC_BASE_LAYER,
148 .nconfigs = 7,
149 .layout = {
150 .xstride = { 2 },
151 .default_color = 3,
152 .general_config = 4,
153 .disc_pos = 5,
154 .disc_size = 6,
155 },
156 },
157 {
158 .name = "overlay1",
159 .formats = &atmel_hlcdc_plane_rgb_formats,
160 .regs_offset = 0x140,
161 .id = 1,
162 .type = ATMEL_HLCDC_OVERLAY_LAYER,
163 .nconfigs = 10,
164 .layout = {
165 .pos = 2,
166 .size = 3,
167 .xstride = { 4 },
168 .pstride = { 5 },
169 .default_color = 6,
170 .chroma_key = 7,
171 .chroma_key_mask = 8,
172 .general_config = 9,
173 },
174 },
175 {
176 .name = "overlay2",
177 .formats = &atmel_hlcdc_plane_rgb_formats,
178 .regs_offset = 0x240,
179 .id = 2,
180 .type = ATMEL_HLCDC_OVERLAY_LAYER,
181 .nconfigs = 10,
182 .layout = {
183 .pos = 2,
184 .size = 3,
185 .xstride = { 4 },
186 .pstride = { 5 },
187 .default_color = 6,
188 .chroma_key = 7,
189 .chroma_key_mask = 8,
190 .general_config = 9,
191 },
192 },
193 {
194 .name = "high-end-overlay",
195 .formats = &atmel_hlcdc_plane_rgb_and_yuv_formats,
196 .regs_offset = 0x340,
197 .id = 3,
198 .type = ATMEL_HLCDC_OVERLAY_LAYER,
199 .nconfigs = 42,
200 .layout = {
201 .pos = 2,
202 .size = 3,
203 .memsize = 4,
204 .xstride = { 5, 7 },
205 .pstride = { 6, 8 },
206 .default_color = 9,
207 .chroma_key = 10,
208 .chroma_key_mask = 11,
209 .general_config = 12,
210 .csc = 14,
211 },
212 },
213 {
214 .name = "cursor",
215 .formats = &atmel_hlcdc_plane_rgb_formats,
216 .regs_offset = 0x440,
217 .id = 4,
218 .type = ATMEL_HLCDC_CURSOR_LAYER,
219 .nconfigs = 10,
220 .max_width = 128,
221 .max_height = 128,
222 .layout = {
223 .pos = 2,
224 .size = 3,
225 .xstride = { 4 },
226 .pstride = { 5 },
227 .default_color = 6,
228 .chroma_key = 7,
229 .chroma_key_mask = 8,
230 .general_config = 9,
231 },
232 },
233};
234
235static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_sama5d3 = {
236 .min_width = 0,
237 .min_height = 0,
238 .max_width = 2048,
239 .max_height = 2048,
240 .nlayers = ARRAY_SIZE(atmel_hlcdc_sama5d3_layers),
241 .layers = atmel_hlcdc_sama5d3_layers,
242};
243
244static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sama5d4_layers[] = {
245 {
246 .name = "base",
247 .formats = &atmel_hlcdc_plane_rgb_formats,
248 .regs_offset = 0x40,
249 .id = 0,
250 .type = ATMEL_HLCDC_BASE_LAYER,
251 .nconfigs = 7,
252 .layout = {
253 .xstride = { 2 },
254 .default_color = 3,
255 .general_config = 4,
256 .disc_pos = 5,
257 .disc_size = 6,
258 },
259 },
260 {
261 .name = "overlay1",
262 .formats = &atmel_hlcdc_plane_rgb_formats,
263 .regs_offset = 0x140,
264 .id = 1,
265 .type = ATMEL_HLCDC_OVERLAY_LAYER,
266 .nconfigs = 10,
267 .layout = {
268 .pos = 2,
269 .size = 3,
270 .xstride = { 4 },
271 .pstride = { 5 },
272 .default_color = 6,
273 .chroma_key = 7,
274 .chroma_key_mask = 8,
275 .general_config = 9,
276 },
277 },
278 {
279 .name = "overlay2",
280 .formats = &atmel_hlcdc_plane_rgb_formats,
281 .regs_offset = 0x240,
282 .id = 2,
283 .type = ATMEL_HLCDC_OVERLAY_LAYER,
284 .nconfigs = 10,
285 .layout = {
286 .pos = 2,
287 .size = 3,
288 .xstride = { 4 },
289 .pstride = { 5 },
290 .default_color = 6,
291 .chroma_key = 7,
292 .chroma_key_mask = 8,
293 .general_config = 9,
294 },
295 },
296 {
297 .name = "high-end-overlay",
298 .formats = &atmel_hlcdc_plane_rgb_and_yuv_formats,
299 .regs_offset = 0x340,
300 .id = 3,
301 .type = ATMEL_HLCDC_OVERLAY_LAYER,
302 .nconfigs = 42,
303 .layout = {
304 .pos = 2,
305 .size = 3,
306 .memsize = 4,
307 .xstride = { 5, 7 },
308 .pstride = { 6, 8 },
309 .default_color = 9,
310 .chroma_key = 10,
311 .chroma_key_mask = 11,
312 .general_config = 12,
313 .csc = 14,
314 },
315 },
316};
317
318static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_sama5d4 = {
319 .min_width = 0,
320 .min_height = 0,
321 .max_width = 2048,
322 .max_height = 2048,
323 .nlayers = ARRAY_SIZE(atmel_hlcdc_sama5d4_layers),
324 .layers = atmel_hlcdc_sama5d4_layers,
325};
326static const struct of_device_id atmel_hlcdc_of_match[] = {
327 {
328 .compatible = "atmel,at91sam9n12-hlcdc",
329 .data = &atmel_hlcdc_dc_at91sam9n12,
330 },
331 {
332 .compatible = "atmel,at91sam9x5-hlcdc",
333 .data = &atmel_hlcdc_dc_at91sam9x5,
334 },
335 {
336 .compatible = "atmel,sama5d2-hlcdc",
337 .data = &atmel_hlcdc_dc_sama5d4,
338 },
339 {
340 .compatible = "atmel,sama5d3-hlcdc",
341 .data = &atmel_hlcdc_dc_sama5d3,
342 },
343 {
344 .compatible = "atmel,sama5d4-hlcdc",
345 .data = &atmel_hlcdc_dc_sama5d4,
346 },
347 { /* sentinel */ },
348};
349MODULE_DEVICE_TABLE(of, atmel_hlcdc_of_match);
350
351int atmel_hlcdc_dc_mode_valid(struct atmel_hlcdc_dc *dc,
352 struct drm_display_mode *mode)
353{
354 int vfront_porch = mode->vsync_start - mode->vdisplay;
355 int vback_porch = mode->vtotal - mode->vsync_end;
356 int vsync_len = mode->vsync_end - mode->vsync_start;
357 int hfront_porch = mode->hsync_start - mode->hdisplay;
358 int hback_porch = mode->htotal - mode->hsync_end;
359 int hsync_len = mode->hsync_end - mode->hsync_start;
360
361 if (hsync_len > 0x40 || hsync_len < 1)
362 return MODE_HSYNC;
363
364 if (vsync_len > 0x40 || vsync_len < 1)
365 return MODE_VSYNC;
366
367 if (hfront_porch > 0x200 || hfront_porch < 1 ||
368 hback_porch > 0x200 || hback_porch < 1 ||
369 mode->hdisplay < 1)
370 return MODE_H_ILLEGAL;
371
372 if (vfront_porch > 0x40 || vfront_porch < 1 ||
373 vback_porch > 0x40 || vback_porch < 0 ||
374 mode->vdisplay < 1)
375 return MODE_V_ILLEGAL;
376
377 return MODE_OK;
378}
379
380static irqreturn_t atmel_hlcdc_dc_irq_handler(int irq, void *data)
381{
382 struct drm_device *dev = data;
383 struct atmel_hlcdc_dc *dc = dev->dev_private;
384 unsigned long status;
385 unsigned int imr, isr;
386 int i;
387
388 regmap_read(dc->hlcdc->regmap, ATMEL_HLCDC_IMR, &imr);
389 regmap_read(dc->hlcdc->regmap, ATMEL_HLCDC_ISR, &isr);
390 status = imr & isr;
391 if (!status)
392 return IRQ_NONE;
393
394 if (status & ATMEL_HLCDC_SOF)
395 atmel_hlcdc_crtc_irq(dc->crtc);
396
397 for (i = 0; i < ATMEL_HLCDC_MAX_LAYERS; i++) {
398 struct atmel_hlcdc_layer *layer = dc->layers[i];
399
400 if (!(ATMEL_HLCDC_LAYER_STATUS(i) & status) || !layer)
401 continue;
402
403 atmel_hlcdc_layer_irq(layer);
404 }
405
406 return IRQ_HANDLED;
407}
408
409static struct drm_framebuffer *atmel_hlcdc_fb_create(struct drm_device *dev,
410 struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd)
411{
412 return drm_fb_cma_create(dev, file_priv, mode_cmd);
413}
414
415static void atmel_hlcdc_fb_output_poll_changed(struct drm_device *dev)
416{
417 struct atmel_hlcdc_dc *dc = dev->dev_private;
418
419 if (dc->fbdev) {
420 drm_fbdev_cma_hotplug_event(dc->fbdev);
421 } else {
422 dc->fbdev = drm_fbdev_cma_init(dev, 24,
423 dev->mode_config.num_crtc,
424 dev->mode_config.num_connector);
425 if (IS_ERR(dc->fbdev))
426 dc->fbdev = NULL;
427 }
428}
429
430static const struct drm_mode_config_funcs mode_config_funcs = {
431 .fb_create = atmel_hlcdc_fb_create,
432 .output_poll_changed = atmel_hlcdc_fb_output_poll_changed,
433 .atomic_check = drm_atomic_helper_check,
434 .atomic_commit = drm_atomic_helper_commit,
435};
436
437static int atmel_hlcdc_dc_modeset_init(struct drm_device *dev)
438{
439 struct atmel_hlcdc_dc *dc = dev->dev_private;
440 struct atmel_hlcdc_planes *planes;
441 int ret;
442 int i;
443
444 drm_mode_config_init(dev);
445
446 ret = atmel_hlcdc_create_outputs(dev);
447 if (ret) {
448 dev_err(dev->dev, "failed to create panel: %d\n", ret);
449 return ret;
450 }
451
452 planes = atmel_hlcdc_create_planes(dev);
453 if (IS_ERR(planes)) {
454 dev_err(dev->dev, "failed to create planes\n");
455 return PTR_ERR(planes);
456 }
457
458 dc->planes = planes;
459
460 dc->layers[planes->primary->layer.desc->id] =
461 &planes->primary->layer;
462
463 if (planes->cursor)
464 dc->layers[planes->cursor->layer.desc->id] =
465 &planes->cursor->layer;
466
467 for (i = 0; i < planes->noverlays; i++)
468 dc->layers[planes->overlays[i]->layer.desc->id] =
469 &planes->overlays[i]->layer;
470
471 ret = atmel_hlcdc_crtc_create(dev);
472 if (ret) {
473 dev_err(dev->dev, "failed to create crtc\n");
474 return ret;
475 }
476
477 dev->mode_config.min_width = dc->desc->min_width;
478 dev->mode_config.min_height = dc->desc->min_height;
479 dev->mode_config.max_width = dc->desc->max_width;
480 dev->mode_config.max_height = dc->desc->max_height;
481 dev->mode_config.funcs = &mode_config_funcs;
482
483 return 0;
484}
485
486static int atmel_hlcdc_dc_load(struct drm_device *dev)
487{
488 struct platform_device *pdev = to_platform_device(dev->dev);
489 const struct of_device_id *match;
490 struct atmel_hlcdc_dc *dc;
491 int ret;
492
493 match = of_match_node(atmel_hlcdc_of_match, dev->dev->parent->of_node);
494 if (!match) {
495 dev_err(&pdev->dev, "invalid compatible string\n");
496 return -ENODEV;
497 }
498
499 if (!match->data) {
500 dev_err(&pdev->dev, "invalid hlcdc description\n");
501 return -EINVAL;
502 }
503
504 dc = devm_kzalloc(dev->dev, sizeof(*dc), GFP_KERNEL);
505 if (!dc)
506 return -ENOMEM;
507
508 dc->wq = alloc_ordered_workqueue("atmel-hlcdc-dc", 0);
509 if (!dc->wq)
510 return -ENOMEM;
511
512 dc->desc = match->data;
513 dc->hlcdc = dev_get_drvdata(dev->dev->parent);
514 dev->dev_private = dc;
515
516 ret = clk_prepare_enable(dc->hlcdc->periph_clk);
517 if (ret) {
518 dev_err(dev->dev, "failed to enable periph_clk\n");
519 goto err_destroy_wq;
520 }
521
522 pm_runtime_enable(dev->dev);
523
524 ret = drm_vblank_init(dev, 1);
525 if (ret < 0) {
526 dev_err(dev->dev, "failed to initialize vblank\n");
527 goto err_periph_clk_disable;
528 }
529
530 ret = atmel_hlcdc_dc_modeset_init(dev);
531 if (ret < 0) {
532 dev_err(dev->dev, "failed to initialize mode setting\n");
533 goto err_periph_clk_disable;
534 }
535
536 drm_mode_config_reset(dev);
537
538 pm_runtime_get_sync(dev->dev);
539 ret = drm_irq_install(dev, dc->hlcdc->irq);
540 pm_runtime_put_sync(dev->dev);
541 if (ret < 0) {
542 dev_err(dev->dev, "failed to install IRQ handler\n");
543 goto err_periph_clk_disable;
544 }
545
546 platform_set_drvdata(pdev, dev);
547
548 drm_kms_helper_poll_init(dev);
549
550 /* force connectors detection */
551 drm_helper_hpd_irq_event(dev);
552
553 return 0;
554
555err_periph_clk_disable:
556 pm_runtime_disable(dev->dev);
557 clk_disable_unprepare(dc->hlcdc->periph_clk);
558
559err_destroy_wq:
560 destroy_workqueue(dc->wq);
561
562 return ret;
563}
564
565static void atmel_hlcdc_dc_unload(struct drm_device *dev)
566{
567 struct atmel_hlcdc_dc *dc = dev->dev_private;
568
569 if (dc->fbdev)
570 drm_fbdev_cma_fini(dc->fbdev);
571 flush_workqueue(dc->wq);
572 drm_kms_helper_poll_fini(dev);
573 drm_mode_config_cleanup(dev);
574 drm_vblank_cleanup(dev);
575
576 pm_runtime_get_sync(dev->dev);
577 drm_irq_uninstall(dev);
578 pm_runtime_put_sync(dev->dev);
579
580 dev->dev_private = NULL;
581
582 pm_runtime_disable(dev->dev);
583 clk_disable_unprepare(dc->hlcdc->periph_clk);
584 destroy_workqueue(dc->wq);
585}
586
587static int atmel_hlcdc_dc_connector_plug_all(struct drm_device *dev)
588{
589 struct drm_connector *connector, *failed;
590 int ret;
591
592 mutex_lock(&dev->mode_config.mutex);
593 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
594 ret = drm_connector_register(connector);
595 if (ret) {
596 failed = connector;
597 goto err;
598 }
599 }
600 mutex_unlock(&dev->mode_config.mutex);
601 return 0;
602
603err:
604 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
605 if (failed == connector)
606 break;
607
608 drm_connector_unregister(connector);
609 }
610 mutex_unlock(&dev->mode_config.mutex);
611
612 return ret;
613}
614
615static void atmel_hlcdc_dc_connector_unplug_all(struct drm_device *dev)
616{
617 mutex_lock(&dev->mode_config.mutex);
618 drm_connector_unplug_all(dev);
619 mutex_unlock(&dev->mode_config.mutex);
620}
621
622static void atmel_hlcdc_dc_lastclose(struct drm_device *dev)
623{
624 struct atmel_hlcdc_dc *dc = dev->dev_private;
625
626 drm_fbdev_cma_restore_mode(dc->fbdev);
627}
628
629static int atmel_hlcdc_dc_irq_postinstall(struct drm_device *dev)
630{
631 struct atmel_hlcdc_dc *dc = dev->dev_private;
632 unsigned int cfg = 0;
633 int i;
634
635 /* Enable interrupts on activated layers */
636 for (i = 0; i < ATMEL_HLCDC_MAX_LAYERS; i++) {
637 if (dc->layers[i])
638 cfg |= ATMEL_HLCDC_LAYER_STATUS(i);
639 }
640
641 regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IER, cfg);
642
643 return 0;
644}
645
646static void atmel_hlcdc_dc_irq_uninstall(struct drm_device *dev)
647{
648 struct atmel_hlcdc_dc *dc = dev->dev_private;
649 unsigned int isr;
650
651 regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IDR, 0xffffffff);
652 regmap_read(dc->hlcdc->regmap, ATMEL_HLCDC_ISR, &isr);
653}
654
655static int atmel_hlcdc_dc_enable_vblank(struct drm_device *dev,
656 unsigned int pipe)
657{
658 struct atmel_hlcdc_dc *dc = dev->dev_private;
659
660 /* Enable SOF (Start Of Frame) interrupt for vblank counting */
661 regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IER, ATMEL_HLCDC_SOF);
662
663 return 0;
664}
665
666static void atmel_hlcdc_dc_disable_vblank(struct drm_device *dev,
667 unsigned int pipe)
668{
669 struct atmel_hlcdc_dc *dc = dev->dev_private;
670
671 regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IDR, ATMEL_HLCDC_SOF);
672}
673
674static const struct file_operations fops = {
675 .owner = THIS_MODULE,
676 .open = drm_open,
677 .release = drm_release,
678 .unlocked_ioctl = drm_ioctl,
679#ifdef CONFIG_COMPAT
680 .compat_ioctl = drm_compat_ioctl,
681#endif
682 .poll = drm_poll,
683 .read = drm_read,
684 .llseek = no_llseek,
685 .mmap = drm_gem_cma_mmap,
686};
687
688static struct drm_driver atmel_hlcdc_dc_driver = {
689 .driver_features = DRIVER_HAVE_IRQ | DRIVER_GEM |
690 DRIVER_MODESET | DRIVER_PRIME |
691 DRIVER_ATOMIC,
692 .lastclose = atmel_hlcdc_dc_lastclose,
693 .irq_handler = atmel_hlcdc_dc_irq_handler,
694 .irq_preinstall = atmel_hlcdc_dc_irq_uninstall,
695 .irq_postinstall = atmel_hlcdc_dc_irq_postinstall,
696 .irq_uninstall = atmel_hlcdc_dc_irq_uninstall,
697 .get_vblank_counter = drm_vblank_no_hw_counter,
698 .enable_vblank = atmel_hlcdc_dc_enable_vblank,
699 .disable_vblank = atmel_hlcdc_dc_disable_vblank,
700 .gem_free_object = drm_gem_cma_free_object,
701 .gem_vm_ops = &drm_gem_cma_vm_ops,
702 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
703 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
704 .gem_prime_import = drm_gem_prime_import,
705 .gem_prime_export = drm_gem_prime_export,
706 .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
707 .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
708 .gem_prime_vmap = drm_gem_cma_prime_vmap,
709 .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
710 .gem_prime_mmap = drm_gem_cma_prime_mmap,
711 .dumb_create = drm_gem_cma_dumb_create,
712 .dumb_map_offset = drm_gem_cma_dumb_map_offset,
713 .dumb_destroy = drm_gem_dumb_destroy,
714 .fops = &fops,
715 .name = "atmel-hlcdc",
716 .desc = "Atmel HLCD Controller DRM",
717 .date = "20141504",
718 .major = 1,
719 .minor = 0,
720};
721
722static int atmel_hlcdc_dc_drm_probe(struct platform_device *pdev)
723{
724 struct drm_device *ddev;
725 int ret;
726
727 ddev = drm_dev_alloc(&atmel_hlcdc_dc_driver, &pdev->dev);
728 if (!ddev)
729 return -ENOMEM;
730
731 ret = atmel_hlcdc_dc_load(ddev);
732 if (ret)
733 goto err_unref;
734
735 ret = drm_dev_register(ddev, 0);
736 if (ret)
737 goto err_unload;
738
739 ret = atmel_hlcdc_dc_connector_plug_all(ddev);
740 if (ret)
741 goto err_unregister;
742
743 return 0;
744
745err_unregister:
746 drm_dev_unregister(ddev);
747
748err_unload:
749 atmel_hlcdc_dc_unload(ddev);
750
751err_unref:
752 drm_dev_unref(ddev);
753
754 return ret;
755}
756
757static int atmel_hlcdc_dc_drm_remove(struct platform_device *pdev)
758{
759 struct drm_device *ddev = platform_get_drvdata(pdev);
760
761 atmel_hlcdc_dc_connector_unplug_all(ddev);
762 drm_dev_unregister(ddev);
763 atmel_hlcdc_dc_unload(ddev);
764 drm_dev_unref(ddev);
765
766 return 0;
767}
768
769#ifdef CONFIG_PM_SLEEP
770static int atmel_hlcdc_dc_drm_suspend(struct device *dev)
771{
772 struct drm_device *drm_dev = dev_get_drvdata(dev);
773 struct drm_crtc *crtc;
774
775 if (pm_runtime_suspended(dev))
776 return 0;
777
778 drm_modeset_lock_all(drm_dev);
779 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head)
780 atmel_hlcdc_crtc_suspend(crtc);
781 drm_modeset_unlock_all(drm_dev);
782 return 0;
783}
784
785static int atmel_hlcdc_dc_drm_resume(struct device *dev)
786{
787 struct drm_device *drm_dev = dev_get_drvdata(dev);
788 struct drm_crtc *crtc;
789
790 if (pm_runtime_suspended(dev))
791 return 0;
792
793 drm_modeset_lock_all(drm_dev);
794 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head)
795 atmel_hlcdc_crtc_resume(crtc);
796 drm_modeset_unlock_all(drm_dev);
797 return 0;
798}
799#endif
800
801static SIMPLE_DEV_PM_OPS(atmel_hlcdc_dc_drm_pm_ops,
802 atmel_hlcdc_dc_drm_suspend, atmel_hlcdc_dc_drm_resume);
803
804static const struct of_device_id atmel_hlcdc_dc_of_match[] = {
805 { .compatible = "atmel,hlcdc-display-controller" },
806 { },
807};
808
809static struct platform_driver atmel_hlcdc_dc_platform_driver = {
810 .probe = atmel_hlcdc_dc_drm_probe,
811 .remove = atmel_hlcdc_dc_drm_remove,
812 .driver = {
813 .name = "atmel-hlcdc-display-controller",
814 .pm = &atmel_hlcdc_dc_drm_pm_ops,
815 .of_match_table = atmel_hlcdc_dc_of_match,
816 },
817};
818module_platform_driver(atmel_hlcdc_dc_platform_driver);
819
820MODULE_AUTHOR("Jean-Jacques Hiblot <jjhiblot@traphandler.com>");
821MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>");
822MODULE_DESCRIPTION("Atmel HLCDC Display Controller DRM Driver");
823MODULE_LICENSE("GPL");
824MODULE_ALIAS("platform:atmel-hlcdc-dc");
1/*
2 * Copyright (C) 2014 Traphandler
3 * Copyright (C) 2014 Free Electrons
4 * Copyright (C) 2014 Atmel
5 *
6 * Author: Jean-Jacques Hiblot <jjhiblot@traphandler.com>
7 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#include <linux/clk.h>
23#include <linux/irq.h>
24#include <linux/irqchip.h>
25#include <linux/module.h>
26#include <linux/pm_runtime.h>
27
28#include "atmel_hlcdc_dc.h"
29
30#define ATMEL_HLCDC_LAYER_IRQS_OFFSET 8
31
32static const struct atmel_hlcdc_layer_desc atmel_hlcdc_at91sam9n12_layers[] = {
33 {
34 .name = "base",
35 .formats = &atmel_hlcdc_plane_rgb_formats,
36 .regs_offset = 0x40,
37 .id = 0,
38 .type = ATMEL_HLCDC_BASE_LAYER,
39 .nconfigs = 5,
40 .layout = {
41 .xstride = { 2 },
42 .default_color = 3,
43 .general_config = 4,
44 },
45 },
46};
47
48static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_at91sam9n12 = {
49 .min_width = 0,
50 .min_height = 0,
51 .max_width = 1280,
52 .max_height = 860,
53 .max_spw = 0x3f,
54 .max_vpw = 0x3f,
55 .max_hpw = 0xff,
56 .conflicting_output_formats = true,
57 .nlayers = ARRAY_SIZE(atmel_hlcdc_at91sam9n12_layers),
58 .layers = atmel_hlcdc_at91sam9n12_layers,
59};
60
61static const struct atmel_hlcdc_layer_desc atmel_hlcdc_at91sam9x5_layers[] = {
62 {
63 .name = "base",
64 .formats = &atmel_hlcdc_plane_rgb_formats,
65 .regs_offset = 0x40,
66 .id = 0,
67 .type = ATMEL_HLCDC_BASE_LAYER,
68 .nconfigs = 5,
69 .layout = {
70 .xstride = { 2 },
71 .default_color = 3,
72 .general_config = 4,
73 .disc_pos = 5,
74 .disc_size = 6,
75 },
76 },
77 {
78 .name = "overlay1",
79 .formats = &atmel_hlcdc_plane_rgb_formats,
80 .regs_offset = 0x100,
81 .id = 1,
82 .type = ATMEL_HLCDC_OVERLAY_LAYER,
83 .nconfigs = 10,
84 .layout = {
85 .pos = 2,
86 .size = 3,
87 .xstride = { 4 },
88 .pstride = { 5 },
89 .default_color = 6,
90 .chroma_key = 7,
91 .chroma_key_mask = 8,
92 .general_config = 9,
93 },
94 },
95 {
96 .name = "high-end-overlay",
97 .formats = &atmel_hlcdc_plane_rgb_and_yuv_formats,
98 .regs_offset = 0x280,
99 .id = 2,
100 .type = ATMEL_HLCDC_OVERLAY_LAYER,
101 .nconfigs = 17,
102 .layout = {
103 .pos = 2,
104 .size = 3,
105 .memsize = 4,
106 .xstride = { 5, 7 },
107 .pstride = { 6, 8 },
108 .default_color = 9,
109 .chroma_key = 10,
110 .chroma_key_mask = 11,
111 .general_config = 12,
112 .csc = 14,
113 },
114 },
115 {
116 .name = "cursor",
117 .formats = &atmel_hlcdc_plane_rgb_formats,
118 .regs_offset = 0x340,
119 .id = 3,
120 .type = ATMEL_HLCDC_CURSOR_LAYER,
121 .nconfigs = 10,
122 .max_width = 128,
123 .max_height = 128,
124 .layout = {
125 .pos = 2,
126 .size = 3,
127 .xstride = { 4 },
128 .default_color = 6,
129 .chroma_key = 7,
130 .chroma_key_mask = 8,
131 .general_config = 9,
132 },
133 },
134};
135
136static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_at91sam9x5 = {
137 .min_width = 0,
138 .min_height = 0,
139 .max_width = 800,
140 .max_height = 600,
141 .max_spw = 0x3f,
142 .max_vpw = 0x3f,
143 .max_hpw = 0xff,
144 .conflicting_output_formats = true,
145 .nlayers = ARRAY_SIZE(atmel_hlcdc_at91sam9x5_layers),
146 .layers = atmel_hlcdc_at91sam9x5_layers,
147};
148
149static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sama5d3_layers[] = {
150 {
151 .name = "base",
152 .formats = &atmel_hlcdc_plane_rgb_formats,
153 .regs_offset = 0x40,
154 .id = 0,
155 .type = ATMEL_HLCDC_BASE_LAYER,
156 .nconfigs = 7,
157 .layout = {
158 .xstride = { 2 },
159 .default_color = 3,
160 .general_config = 4,
161 .disc_pos = 5,
162 .disc_size = 6,
163 },
164 },
165 {
166 .name = "overlay1",
167 .formats = &atmel_hlcdc_plane_rgb_formats,
168 .regs_offset = 0x140,
169 .id = 1,
170 .type = ATMEL_HLCDC_OVERLAY_LAYER,
171 .nconfigs = 10,
172 .layout = {
173 .pos = 2,
174 .size = 3,
175 .xstride = { 4 },
176 .pstride = { 5 },
177 .default_color = 6,
178 .chroma_key = 7,
179 .chroma_key_mask = 8,
180 .general_config = 9,
181 },
182 },
183 {
184 .name = "overlay2",
185 .formats = &atmel_hlcdc_plane_rgb_formats,
186 .regs_offset = 0x240,
187 .id = 2,
188 .type = ATMEL_HLCDC_OVERLAY_LAYER,
189 .nconfigs = 10,
190 .layout = {
191 .pos = 2,
192 .size = 3,
193 .xstride = { 4 },
194 .pstride = { 5 },
195 .default_color = 6,
196 .chroma_key = 7,
197 .chroma_key_mask = 8,
198 .general_config = 9,
199 },
200 },
201 {
202 .name = "high-end-overlay",
203 .formats = &atmel_hlcdc_plane_rgb_and_yuv_formats,
204 .regs_offset = 0x340,
205 .id = 3,
206 .type = ATMEL_HLCDC_OVERLAY_LAYER,
207 .nconfigs = 42,
208 .layout = {
209 .pos = 2,
210 .size = 3,
211 .memsize = 4,
212 .xstride = { 5, 7 },
213 .pstride = { 6, 8 },
214 .default_color = 9,
215 .chroma_key = 10,
216 .chroma_key_mask = 11,
217 .general_config = 12,
218 .csc = 14,
219 },
220 },
221 {
222 .name = "cursor",
223 .formats = &atmel_hlcdc_plane_rgb_formats,
224 .regs_offset = 0x440,
225 .id = 4,
226 .type = ATMEL_HLCDC_CURSOR_LAYER,
227 .nconfigs = 10,
228 .max_width = 128,
229 .max_height = 128,
230 .layout = {
231 .pos = 2,
232 .size = 3,
233 .xstride = { 4 },
234 .pstride = { 5 },
235 .default_color = 6,
236 .chroma_key = 7,
237 .chroma_key_mask = 8,
238 .general_config = 9,
239 },
240 },
241};
242
243static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_sama5d3 = {
244 .min_width = 0,
245 .min_height = 0,
246 .max_width = 2048,
247 .max_height = 2048,
248 .max_spw = 0x3f,
249 .max_vpw = 0x3f,
250 .max_hpw = 0x1ff,
251 .conflicting_output_formats = true,
252 .nlayers = ARRAY_SIZE(atmel_hlcdc_sama5d3_layers),
253 .layers = atmel_hlcdc_sama5d3_layers,
254};
255
256static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sama5d4_layers[] = {
257 {
258 .name = "base",
259 .formats = &atmel_hlcdc_plane_rgb_formats,
260 .regs_offset = 0x40,
261 .id = 0,
262 .type = ATMEL_HLCDC_BASE_LAYER,
263 .nconfigs = 7,
264 .layout = {
265 .xstride = { 2 },
266 .default_color = 3,
267 .general_config = 4,
268 .disc_pos = 5,
269 .disc_size = 6,
270 },
271 },
272 {
273 .name = "overlay1",
274 .formats = &atmel_hlcdc_plane_rgb_formats,
275 .regs_offset = 0x140,
276 .id = 1,
277 .type = ATMEL_HLCDC_OVERLAY_LAYER,
278 .nconfigs = 10,
279 .layout = {
280 .pos = 2,
281 .size = 3,
282 .xstride = { 4 },
283 .pstride = { 5 },
284 .default_color = 6,
285 .chroma_key = 7,
286 .chroma_key_mask = 8,
287 .general_config = 9,
288 },
289 },
290 {
291 .name = "overlay2",
292 .formats = &atmel_hlcdc_plane_rgb_formats,
293 .regs_offset = 0x240,
294 .id = 2,
295 .type = ATMEL_HLCDC_OVERLAY_LAYER,
296 .nconfigs = 10,
297 .layout = {
298 .pos = 2,
299 .size = 3,
300 .xstride = { 4 },
301 .pstride = { 5 },
302 .default_color = 6,
303 .chroma_key = 7,
304 .chroma_key_mask = 8,
305 .general_config = 9,
306 },
307 },
308 {
309 .name = "high-end-overlay",
310 .formats = &atmel_hlcdc_plane_rgb_and_yuv_formats,
311 .regs_offset = 0x340,
312 .id = 3,
313 .type = ATMEL_HLCDC_OVERLAY_LAYER,
314 .nconfigs = 42,
315 .layout = {
316 .pos = 2,
317 .size = 3,
318 .memsize = 4,
319 .xstride = { 5, 7 },
320 .pstride = { 6, 8 },
321 .default_color = 9,
322 .chroma_key = 10,
323 .chroma_key_mask = 11,
324 .general_config = 12,
325 .csc = 14,
326 },
327 },
328};
329
330static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_sama5d4 = {
331 .min_width = 0,
332 .min_height = 0,
333 .max_width = 2048,
334 .max_height = 2048,
335 .max_spw = 0xff,
336 .max_vpw = 0xff,
337 .max_hpw = 0x3ff,
338 .nlayers = ARRAY_SIZE(atmel_hlcdc_sama5d4_layers),
339 .layers = atmel_hlcdc_sama5d4_layers,
340};
341static const struct of_device_id atmel_hlcdc_of_match[] = {
342 {
343 .compatible = "atmel,at91sam9n12-hlcdc",
344 .data = &atmel_hlcdc_dc_at91sam9n12,
345 },
346 {
347 .compatible = "atmel,at91sam9x5-hlcdc",
348 .data = &atmel_hlcdc_dc_at91sam9x5,
349 },
350 {
351 .compatible = "atmel,sama5d2-hlcdc",
352 .data = &atmel_hlcdc_dc_sama5d4,
353 },
354 {
355 .compatible = "atmel,sama5d3-hlcdc",
356 .data = &atmel_hlcdc_dc_sama5d3,
357 },
358 {
359 .compatible = "atmel,sama5d4-hlcdc",
360 .data = &atmel_hlcdc_dc_sama5d4,
361 },
362 { /* sentinel */ },
363};
364MODULE_DEVICE_TABLE(of, atmel_hlcdc_of_match);
365
366int atmel_hlcdc_dc_mode_valid(struct atmel_hlcdc_dc *dc,
367 struct drm_display_mode *mode)
368{
369 int vfront_porch = mode->vsync_start - mode->vdisplay;
370 int vback_porch = mode->vtotal - mode->vsync_end;
371 int vsync_len = mode->vsync_end - mode->vsync_start;
372 int hfront_porch = mode->hsync_start - mode->hdisplay;
373 int hback_porch = mode->htotal - mode->hsync_end;
374 int hsync_len = mode->hsync_end - mode->hsync_start;
375
376 if (hsync_len > dc->desc->max_spw + 1 || hsync_len < 1)
377 return MODE_HSYNC;
378
379 if (vsync_len > dc->desc->max_spw + 1 || vsync_len < 1)
380 return MODE_VSYNC;
381
382 if (hfront_porch > dc->desc->max_hpw + 1 || hfront_porch < 1 ||
383 hback_porch > dc->desc->max_hpw + 1 || hback_porch < 1 ||
384 mode->hdisplay < 1)
385 return MODE_H_ILLEGAL;
386
387 if (vfront_porch > dc->desc->max_vpw + 1 || vfront_porch < 1 ||
388 vback_porch > dc->desc->max_vpw || vback_porch < 0 ||
389 mode->vdisplay < 1)
390 return MODE_V_ILLEGAL;
391
392 return MODE_OK;
393}
394
395static irqreturn_t atmel_hlcdc_dc_irq_handler(int irq, void *data)
396{
397 struct drm_device *dev = data;
398 struct atmel_hlcdc_dc *dc = dev->dev_private;
399 unsigned long status;
400 unsigned int imr, isr;
401 int i;
402
403 regmap_read(dc->hlcdc->regmap, ATMEL_HLCDC_IMR, &imr);
404 regmap_read(dc->hlcdc->regmap, ATMEL_HLCDC_ISR, &isr);
405 status = imr & isr;
406 if (!status)
407 return IRQ_NONE;
408
409 if (status & ATMEL_HLCDC_SOF)
410 atmel_hlcdc_crtc_irq(dc->crtc);
411
412 for (i = 0; i < ATMEL_HLCDC_MAX_LAYERS; i++) {
413 struct atmel_hlcdc_layer *layer = dc->layers[i];
414
415 if (!(ATMEL_HLCDC_LAYER_STATUS(i) & status) || !layer)
416 continue;
417
418 atmel_hlcdc_layer_irq(layer);
419 }
420
421 return IRQ_HANDLED;
422}
423
424static struct drm_framebuffer *atmel_hlcdc_fb_create(struct drm_device *dev,
425 struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd)
426{
427 return drm_fb_cma_create(dev, file_priv, mode_cmd);
428}
429
430static void atmel_hlcdc_fb_output_poll_changed(struct drm_device *dev)
431{
432 struct atmel_hlcdc_dc *dc = dev->dev_private;
433
434 if (dc->fbdev) {
435 drm_fbdev_cma_hotplug_event(dc->fbdev);
436 } else {
437 dc->fbdev = drm_fbdev_cma_init(dev, 24,
438 dev->mode_config.num_crtc,
439 dev->mode_config.num_connector);
440 if (IS_ERR(dc->fbdev))
441 dc->fbdev = NULL;
442 }
443}
444
445struct atmel_hlcdc_dc_commit {
446 struct work_struct work;
447 struct drm_device *dev;
448 struct drm_atomic_state *state;
449};
450
451static void
452atmel_hlcdc_dc_atomic_complete(struct atmel_hlcdc_dc_commit *commit)
453{
454 struct drm_device *dev = commit->dev;
455 struct atmel_hlcdc_dc *dc = dev->dev_private;
456 struct drm_atomic_state *old_state = commit->state;
457
458 /* Apply the atomic update. */
459 drm_atomic_helper_commit_modeset_disables(dev, old_state);
460 drm_atomic_helper_commit_planes(dev, old_state, 0);
461 drm_atomic_helper_commit_modeset_enables(dev, old_state);
462
463 drm_atomic_helper_wait_for_vblanks(dev, old_state);
464
465 drm_atomic_helper_cleanup_planes(dev, old_state);
466
467 drm_atomic_state_put(old_state);
468
469 /* Complete the commit, wake up any waiter. */
470 spin_lock(&dc->commit.wait.lock);
471 dc->commit.pending = false;
472 wake_up_all_locked(&dc->commit.wait);
473 spin_unlock(&dc->commit.wait.lock);
474
475 kfree(commit);
476}
477
478static void atmel_hlcdc_dc_atomic_work(struct work_struct *work)
479{
480 struct atmel_hlcdc_dc_commit *commit =
481 container_of(work, struct atmel_hlcdc_dc_commit, work);
482
483 atmel_hlcdc_dc_atomic_complete(commit);
484}
485
486static int atmel_hlcdc_dc_atomic_commit(struct drm_device *dev,
487 struct drm_atomic_state *state,
488 bool async)
489{
490 struct atmel_hlcdc_dc *dc = dev->dev_private;
491 struct atmel_hlcdc_dc_commit *commit;
492 int ret;
493
494 ret = drm_atomic_helper_prepare_planes(dev, state);
495 if (ret)
496 return ret;
497
498 /* Allocate the commit object. */
499 commit = kzalloc(sizeof(*commit), GFP_KERNEL);
500 if (!commit) {
501 ret = -ENOMEM;
502 goto error;
503 }
504
505 INIT_WORK(&commit->work, atmel_hlcdc_dc_atomic_work);
506 commit->dev = dev;
507 commit->state = state;
508
509 spin_lock(&dc->commit.wait.lock);
510 ret = wait_event_interruptible_locked(dc->commit.wait,
511 !dc->commit.pending);
512 if (ret == 0)
513 dc->commit.pending = true;
514 spin_unlock(&dc->commit.wait.lock);
515
516 if (ret) {
517 kfree(commit);
518 goto error;
519 }
520
521 /* Swap the state, this is the point of no return. */
522 drm_atomic_helper_swap_state(state, true);
523
524 drm_atomic_state_get(state);
525 if (async)
526 queue_work(dc->wq, &commit->work);
527 else
528 atmel_hlcdc_dc_atomic_complete(commit);
529
530 return 0;
531
532error:
533 drm_atomic_helper_cleanup_planes(dev, state);
534 return ret;
535}
536
537static const struct drm_mode_config_funcs mode_config_funcs = {
538 .fb_create = atmel_hlcdc_fb_create,
539 .output_poll_changed = atmel_hlcdc_fb_output_poll_changed,
540 .atomic_check = drm_atomic_helper_check,
541 .atomic_commit = atmel_hlcdc_dc_atomic_commit,
542};
543
544static int atmel_hlcdc_dc_modeset_init(struct drm_device *dev)
545{
546 struct atmel_hlcdc_dc *dc = dev->dev_private;
547 struct atmel_hlcdc_planes *planes;
548 int ret;
549 int i;
550
551 drm_mode_config_init(dev);
552
553 ret = atmel_hlcdc_create_outputs(dev);
554 if (ret) {
555 dev_err(dev->dev, "failed to create HLCDC outputs: %d\n", ret);
556 return ret;
557 }
558
559 planes = atmel_hlcdc_create_planes(dev);
560 if (IS_ERR(planes)) {
561 dev_err(dev->dev, "failed to create planes\n");
562 return PTR_ERR(planes);
563 }
564
565 dc->planes = planes;
566
567 dc->layers[planes->primary->layer.desc->id] =
568 &planes->primary->layer;
569
570 if (planes->cursor)
571 dc->layers[planes->cursor->layer.desc->id] =
572 &planes->cursor->layer;
573
574 for (i = 0; i < planes->noverlays; i++)
575 dc->layers[planes->overlays[i]->layer.desc->id] =
576 &planes->overlays[i]->layer;
577
578 ret = atmel_hlcdc_crtc_create(dev);
579 if (ret) {
580 dev_err(dev->dev, "failed to create crtc\n");
581 return ret;
582 }
583
584 dev->mode_config.min_width = dc->desc->min_width;
585 dev->mode_config.min_height = dc->desc->min_height;
586 dev->mode_config.max_width = dc->desc->max_width;
587 dev->mode_config.max_height = dc->desc->max_height;
588 dev->mode_config.funcs = &mode_config_funcs;
589
590 return 0;
591}
592
593static int atmel_hlcdc_dc_load(struct drm_device *dev)
594{
595 struct platform_device *pdev = to_platform_device(dev->dev);
596 const struct of_device_id *match;
597 struct atmel_hlcdc_dc *dc;
598 int ret;
599
600 match = of_match_node(atmel_hlcdc_of_match, dev->dev->parent->of_node);
601 if (!match) {
602 dev_err(&pdev->dev, "invalid compatible string\n");
603 return -ENODEV;
604 }
605
606 if (!match->data) {
607 dev_err(&pdev->dev, "invalid hlcdc description\n");
608 return -EINVAL;
609 }
610
611 dc = devm_kzalloc(dev->dev, sizeof(*dc), GFP_KERNEL);
612 if (!dc)
613 return -ENOMEM;
614
615 dc->wq = alloc_ordered_workqueue("atmel-hlcdc-dc", 0);
616 if (!dc->wq)
617 return -ENOMEM;
618
619 init_waitqueue_head(&dc->commit.wait);
620 dc->desc = match->data;
621 dc->hlcdc = dev_get_drvdata(dev->dev->parent);
622 dev->dev_private = dc;
623
624 ret = clk_prepare_enable(dc->hlcdc->periph_clk);
625 if (ret) {
626 dev_err(dev->dev, "failed to enable periph_clk\n");
627 goto err_destroy_wq;
628 }
629
630 pm_runtime_enable(dev->dev);
631
632 ret = drm_vblank_init(dev, 1);
633 if (ret < 0) {
634 dev_err(dev->dev, "failed to initialize vblank\n");
635 goto err_periph_clk_disable;
636 }
637
638 ret = atmel_hlcdc_dc_modeset_init(dev);
639 if (ret < 0) {
640 dev_err(dev->dev, "failed to initialize mode setting\n");
641 goto err_periph_clk_disable;
642 }
643
644 drm_mode_config_reset(dev);
645
646 pm_runtime_get_sync(dev->dev);
647 ret = drm_irq_install(dev, dc->hlcdc->irq);
648 pm_runtime_put_sync(dev->dev);
649 if (ret < 0) {
650 dev_err(dev->dev, "failed to install IRQ handler\n");
651 goto err_periph_clk_disable;
652 }
653
654 platform_set_drvdata(pdev, dev);
655
656 drm_kms_helper_poll_init(dev);
657
658 /* force connectors detection */
659 drm_helper_hpd_irq_event(dev);
660
661 return 0;
662
663err_periph_clk_disable:
664 pm_runtime_disable(dev->dev);
665 clk_disable_unprepare(dc->hlcdc->periph_clk);
666
667err_destroy_wq:
668 destroy_workqueue(dc->wq);
669
670 return ret;
671}
672
673static void atmel_hlcdc_dc_unload(struct drm_device *dev)
674{
675 struct atmel_hlcdc_dc *dc = dev->dev_private;
676
677 if (dc->fbdev)
678 drm_fbdev_cma_fini(dc->fbdev);
679 flush_workqueue(dc->wq);
680 drm_kms_helper_poll_fini(dev);
681 drm_mode_config_cleanup(dev);
682 drm_vblank_cleanup(dev);
683
684 pm_runtime_get_sync(dev->dev);
685 drm_irq_uninstall(dev);
686 pm_runtime_put_sync(dev->dev);
687
688 dev->dev_private = NULL;
689
690 pm_runtime_disable(dev->dev);
691 clk_disable_unprepare(dc->hlcdc->periph_clk);
692 destroy_workqueue(dc->wq);
693}
694
695static void atmel_hlcdc_dc_lastclose(struct drm_device *dev)
696{
697 struct atmel_hlcdc_dc *dc = dev->dev_private;
698
699 drm_fbdev_cma_restore_mode(dc->fbdev);
700}
701
702static int atmel_hlcdc_dc_irq_postinstall(struct drm_device *dev)
703{
704 struct atmel_hlcdc_dc *dc = dev->dev_private;
705 unsigned int cfg = 0;
706 int i;
707
708 /* Enable interrupts on activated layers */
709 for (i = 0; i < ATMEL_HLCDC_MAX_LAYERS; i++) {
710 if (dc->layers[i])
711 cfg |= ATMEL_HLCDC_LAYER_STATUS(i);
712 }
713
714 regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IER, cfg);
715
716 return 0;
717}
718
719static void atmel_hlcdc_dc_irq_uninstall(struct drm_device *dev)
720{
721 struct atmel_hlcdc_dc *dc = dev->dev_private;
722 unsigned int isr;
723
724 regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IDR, 0xffffffff);
725 regmap_read(dc->hlcdc->regmap, ATMEL_HLCDC_ISR, &isr);
726}
727
728static int atmel_hlcdc_dc_enable_vblank(struct drm_device *dev,
729 unsigned int pipe)
730{
731 struct atmel_hlcdc_dc *dc = dev->dev_private;
732
733 /* Enable SOF (Start Of Frame) interrupt for vblank counting */
734 regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IER, ATMEL_HLCDC_SOF);
735
736 return 0;
737}
738
739static void atmel_hlcdc_dc_disable_vblank(struct drm_device *dev,
740 unsigned int pipe)
741{
742 struct atmel_hlcdc_dc *dc = dev->dev_private;
743
744 regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IDR, ATMEL_HLCDC_SOF);
745}
746
747static const struct file_operations fops = {
748 .owner = THIS_MODULE,
749 .open = drm_open,
750 .release = drm_release,
751 .unlocked_ioctl = drm_ioctl,
752 .compat_ioctl = drm_compat_ioctl,
753 .poll = drm_poll,
754 .read = drm_read,
755 .llseek = no_llseek,
756 .mmap = drm_gem_cma_mmap,
757};
758
759static struct drm_driver atmel_hlcdc_dc_driver = {
760 .driver_features = DRIVER_HAVE_IRQ | DRIVER_GEM |
761 DRIVER_MODESET | DRIVER_PRIME |
762 DRIVER_ATOMIC,
763 .lastclose = atmel_hlcdc_dc_lastclose,
764 .irq_handler = atmel_hlcdc_dc_irq_handler,
765 .irq_preinstall = atmel_hlcdc_dc_irq_uninstall,
766 .irq_postinstall = atmel_hlcdc_dc_irq_postinstall,
767 .irq_uninstall = atmel_hlcdc_dc_irq_uninstall,
768 .get_vblank_counter = drm_vblank_no_hw_counter,
769 .enable_vblank = atmel_hlcdc_dc_enable_vblank,
770 .disable_vblank = atmel_hlcdc_dc_disable_vblank,
771 .gem_free_object_unlocked = drm_gem_cma_free_object,
772 .gem_vm_ops = &drm_gem_cma_vm_ops,
773 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
774 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
775 .gem_prime_import = drm_gem_prime_import,
776 .gem_prime_export = drm_gem_prime_export,
777 .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
778 .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
779 .gem_prime_vmap = drm_gem_cma_prime_vmap,
780 .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
781 .gem_prime_mmap = drm_gem_cma_prime_mmap,
782 .dumb_create = drm_gem_cma_dumb_create,
783 .dumb_map_offset = drm_gem_cma_dumb_map_offset,
784 .dumb_destroy = drm_gem_dumb_destroy,
785 .fops = &fops,
786 .name = "atmel-hlcdc",
787 .desc = "Atmel HLCD Controller DRM",
788 .date = "20141504",
789 .major = 1,
790 .minor = 0,
791};
792
793static int atmel_hlcdc_dc_drm_probe(struct platform_device *pdev)
794{
795 struct drm_device *ddev;
796 int ret;
797
798 ddev = drm_dev_alloc(&atmel_hlcdc_dc_driver, &pdev->dev);
799 if (IS_ERR(ddev))
800 return PTR_ERR(ddev);
801
802 ret = atmel_hlcdc_dc_load(ddev);
803 if (ret)
804 goto err_unref;
805
806 ret = drm_dev_register(ddev, 0);
807 if (ret)
808 goto err_unload;
809
810 return 0;
811
812err_unload:
813 atmel_hlcdc_dc_unload(ddev);
814
815err_unref:
816 drm_dev_unref(ddev);
817
818 return ret;
819}
820
821static int atmel_hlcdc_dc_drm_remove(struct platform_device *pdev)
822{
823 struct drm_device *ddev = platform_get_drvdata(pdev);
824
825 drm_dev_unregister(ddev);
826 atmel_hlcdc_dc_unload(ddev);
827 drm_dev_unref(ddev);
828
829 return 0;
830}
831
832#ifdef CONFIG_PM_SLEEP
833static int atmel_hlcdc_dc_drm_suspend(struct device *dev)
834{
835 struct drm_device *drm_dev = dev_get_drvdata(dev);
836 struct drm_crtc *crtc;
837
838 if (pm_runtime_suspended(dev))
839 return 0;
840
841 drm_modeset_lock_all(drm_dev);
842 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head)
843 atmel_hlcdc_crtc_suspend(crtc);
844 drm_modeset_unlock_all(drm_dev);
845 return 0;
846}
847
848static int atmel_hlcdc_dc_drm_resume(struct device *dev)
849{
850 struct drm_device *drm_dev = dev_get_drvdata(dev);
851 struct drm_crtc *crtc;
852
853 if (pm_runtime_suspended(dev))
854 return 0;
855
856 drm_modeset_lock_all(drm_dev);
857 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head)
858 atmel_hlcdc_crtc_resume(crtc);
859 drm_modeset_unlock_all(drm_dev);
860 return 0;
861}
862#endif
863
864static SIMPLE_DEV_PM_OPS(atmel_hlcdc_dc_drm_pm_ops,
865 atmel_hlcdc_dc_drm_suspend, atmel_hlcdc_dc_drm_resume);
866
867static const struct of_device_id atmel_hlcdc_dc_of_match[] = {
868 { .compatible = "atmel,hlcdc-display-controller" },
869 { },
870};
871
872static struct platform_driver atmel_hlcdc_dc_platform_driver = {
873 .probe = atmel_hlcdc_dc_drm_probe,
874 .remove = atmel_hlcdc_dc_drm_remove,
875 .driver = {
876 .name = "atmel-hlcdc-display-controller",
877 .pm = &atmel_hlcdc_dc_drm_pm_ops,
878 .of_match_table = atmel_hlcdc_dc_of_match,
879 },
880};
881module_platform_driver(atmel_hlcdc_dc_platform_driver);
882
883MODULE_AUTHOR("Jean-Jacques Hiblot <jjhiblot@traphandler.com>");
884MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>");
885MODULE_DESCRIPTION("Atmel HLCDC Display Controller DRM Driver");
886MODULE_LICENSE("GPL");
887MODULE_ALIAS("platform:atmel-hlcdc-dc");