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1/*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30#include <linux/log2.h>
31#include <drm/drmP.h>
32#include "i915_drv.h"
33#include <drm/i915_drm.h>
34#include "i915_trace.h"
35#include "intel_drv.h"
36
37int __intel_ring_space(int head, int tail, int size)
38{
39 int space = head - tail;
40 if (space <= 0)
41 space += size;
42 return space - I915_RING_FREE_SPACE;
43}
44
45void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
46{
47 if (ringbuf->last_retired_head != -1) {
48 ringbuf->head = ringbuf->last_retired_head;
49 ringbuf->last_retired_head = -1;
50 }
51
52 ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
53 ringbuf->tail, ringbuf->size);
54}
55
56int intel_ring_space(struct intel_ringbuffer *ringbuf)
57{
58 intel_ring_update_space(ringbuf);
59 return ringbuf->space;
60}
61
62bool intel_ring_stopped(struct intel_engine_cs *ring)
63{
64 struct drm_i915_private *dev_priv = ring->dev->dev_private;
65 return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
66}
67
68static void __intel_ring_advance(struct intel_engine_cs *ring)
69{
70 struct intel_ringbuffer *ringbuf = ring->buffer;
71 ringbuf->tail &= ringbuf->size - 1;
72 if (intel_ring_stopped(ring))
73 return;
74 ring->write_tail(ring, ringbuf->tail);
75}
76
77static int
78gen2_render_ring_flush(struct drm_i915_gem_request *req,
79 u32 invalidate_domains,
80 u32 flush_domains)
81{
82 struct intel_engine_cs *ring = req->ring;
83 u32 cmd;
84 int ret;
85
86 cmd = MI_FLUSH;
87 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
88 cmd |= MI_NO_WRITE_FLUSH;
89
90 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
91 cmd |= MI_READ_FLUSH;
92
93 ret = intel_ring_begin(req, 2);
94 if (ret)
95 return ret;
96
97 intel_ring_emit(ring, cmd);
98 intel_ring_emit(ring, MI_NOOP);
99 intel_ring_advance(ring);
100
101 return 0;
102}
103
104static int
105gen4_render_ring_flush(struct drm_i915_gem_request *req,
106 u32 invalidate_domains,
107 u32 flush_domains)
108{
109 struct intel_engine_cs *ring = req->ring;
110 struct drm_device *dev = ring->dev;
111 u32 cmd;
112 int ret;
113
114 /*
115 * read/write caches:
116 *
117 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
118 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
119 * also flushed at 2d versus 3d pipeline switches.
120 *
121 * read-only caches:
122 *
123 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
124 * MI_READ_FLUSH is set, and is always flushed on 965.
125 *
126 * I915_GEM_DOMAIN_COMMAND may not exist?
127 *
128 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
129 * invalidated when MI_EXE_FLUSH is set.
130 *
131 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
132 * invalidated with every MI_FLUSH.
133 *
134 * TLBs:
135 *
136 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
137 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
138 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
139 * are flushed at any MI_FLUSH.
140 */
141
142 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
143 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
144 cmd &= ~MI_NO_WRITE_FLUSH;
145 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
146 cmd |= MI_EXE_FLUSH;
147
148 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
149 (IS_G4X(dev) || IS_GEN5(dev)))
150 cmd |= MI_INVALIDATE_ISP;
151
152 ret = intel_ring_begin(req, 2);
153 if (ret)
154 return ret;
155
156 intel_ring_emit(ring, cmd);
157 intel_ring_emit(ring, MI_NOOP);
158 intel_ring_advance(ring);
159
160 return 0;
161}
162
163/**
164 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
165 * implementing two workarounds on gen6. From section 1.4.7.1
166 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
167 *
168 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
169 * produced by non-pipelined state commands), software needs to first
170 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
171 * 0.
172 *
173 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
174 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
175 *
176 * And the workaround for these two requires this workaround first:
177 *
178 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
179 * BEFORE the pipe-control with a post-sync op and no write-cache
180 * flushes.
181 *
182 * And this last workaround is tricky because of the requirements on
183 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
184 * volume 2 part 1:
185 *
186 * "1 of the following must also be set:
187 * - Render Target Cache Flush Enable ([12] of DW1)
188 * - Depth Cache Flush Enable ([0] of DW1)
189 * - Stall at Pixel Scoreboard ([1] of DW1)
190 * - Depth Stall ([13] of DW1)
191 * - Post-Sync Operation ([13] of DW1)
192 * - Notify Enable ([8] of DW1)"
193 *
194 * The cache flushes require the workaround flush that triggered this
195 * one, so we can't use it. Depth stall would trigger the same.
196 * Post-sync nonzero is what triggered this second workaround, so we
197 * can't use that one either. Notify enable is IRQs, which aren't
198 * really our business. That leaves only stall at scoreboard.
199 */
200static int
201intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
202{
203 struct intel_engine_cs *ring = req->ring;
204 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
205 int ret;
206
207 ret = intel_ring_begin(req, 6);
208 if (ret)
209 return ret;
210
211 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
212 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
213 PIPE_CONTROL_STALL_AT_SCOREBOARD);
214 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
215 intel_ring_emit(ring, 0); /* low dword */
216 intel_ring_emit(ring, 0); /* high dword */
217 intel_ring_emit(ring, MI_NOOP);
218 intel_ring_advance(ring);
219
220 ret = intel_ring_begin(req, 6);
221 if (ret)
222 return ret;
223
224 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
225 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
226 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
227 intel_ring_emit(ring, 0);
228 intel_ring_emit(ring, 0);
229 intel_ring_emit(ring, MI_NOOP);
230 intel_ring_advance(ring);
231
232 return 0;
233}
234
235static int
236gen6_render_ring_flush(struct drm_i915_gem_request *req,
237 u32 invalidate_domains, u32 flush_domains)
238{
239 struct intel_engine_cs *ring = req->ring;
240 u32 flags = 0;
241 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
242 int ret;
243
244 /* Force SNB workarounds for PIPE_CONTROL flushes */
245 ret = intel_emit_post_sync_nonzero_flush(req);
246 if (ret)
247 return ret;
248
249 /* Just flush everything. Experiments have shown that reducing the
250 * number of bits based on the write domains has little performance
251 * impact.
252 */
253 if (flush_domains) {
254 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
255 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
256 /*
257 * Ensure that any following seqno writes only happen
258 * when the render cache is indeed flushed.
259 */
260 flags |= PIPE_CONTROL_CS_STALL;
261 }
262 if (invalidate_domains) {
263 flags |= PIPE_CONTROL_TLB_INVALIDATE;
264 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
265 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
266 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
267 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
268 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
269 /*
270 * TLB invalidate requires a post-sync write.
271 */
272 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
273 }
274
275 ret = intel_ring_begin(req, 4);
276 if (ret)
277 return ret;
278
279 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
280 intel_ring_emit(ring, flags);
281 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
282 intel_ring_emit(ring, 0);
283 intel_ring_advance(ring);
284
285 return 0;
286}
287
288static int
289gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
290{
291 struct intel_engine_cs *ring = req->ring;
292 int ret;
293
294 ret = intel_ring_begin(req, 4);
295 if (ret)
296 return ret;
297
298 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
299 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
300 PIPE_CONTROL_STALL_AT_SCOREBOARD);
301 intel_ring_emit(ring, 0);
302 intel_ring_emit(ring, 0);
303 intel_ring_advance(ring);
304
305 return 0;
306}
307
308static int
309gen7_render_ring_flush(struct drm_i915_gem_request *req,
310 u32 invalidate_domains, u32 flush_domains)
311{
312 struct intel_engine_cs *ring = req->ring;
313 u32 flags = 0;
314 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
315 int ret;
316
317 /*
318 * Ensure that any following seqno writes only happen when the render
319 * cache is indeed flushed.
320 *
321 * Workaround: 4th PIPE_CONTROL command (except the ones with only
322 * read-cache invalidate bits set) must have the CS_STALL bit set. We
323 * don't try to be clever and just set it unconditionally.
324 */
325 flags |= PIPE_CONTROL_CS_STALL;
326
327 /* Just flush everything. Experiments have shown that reducing the
328 * number of bits based on the write domains has little performance
329 * impact.
330 */
331 if (flush_domains) {
332 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
333 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
334 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
335 flags |= PIPE_CONTROL_FLUSH_ENABLE;
336 }
337 if (invalidate_domains) {
338 flags |= PIPE_CONTROL_TLB_INVALIDATE;
339 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
340 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
341 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
342 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
343 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
344 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
345 /*
346 * TLB invalidate requires a post-sync write.
347 */
348 flags |= PIPE_CONTROL_QW_WRITE;
349 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
350
351 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
352
353 /* Workaround: we must issue a pipe_control with CS-stall bit
354 * set before a pipe_control command that has the state cache
355 * invalidate bit set. */
356 gen7_render_ring_cs_stall_wa(req);
357 }
358
359 ret = intel_ring_begin(req, 4);
360 if (ret)
361 return ret;
362
363 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
364 intel_ring_emit(ring, flags);
365 intel_ring_emit(ring, scratch_addr);
366 intel_ring_emit(ring, 0);
367 intel_ring_advance(ring);
368
369 return 0;
370}
371
372static int
373gen8_emit_pipe_control(struct drm_i915_gem_request *req,
374 u32 flags, u32 scratch_addr)
375{
376 struct intel_engine_cs *ring = req->ring;
377 int ret;
378
379 ret = intel_ring_begin(req, 6);
380 if (ret)
381 return ret;
382
383 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
384 intel_ring_emit(ring, flags);
385 intel_ring_emit(ring, scratch_addr);
386 intel_ring_emit(ring, 0);
387 intel_ring_emit(ring, 0);
388 intel_ring_emit(ring, 0);
389 intel_ring_advance(ring);
390
391 return 0;
392}
393
394static int
395gen8_render_ring_flush(struct drm_i915_gem_request *req,
396 u32 invalidate_domains, u32 flush_domains)
397{
398 u32 flags = 0;
399 u32 scratch_addr = req->ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
400 int ret;
401
402 flags |= PIPE_CONTROL_CS_STALL;
403
404 if (flush_domains) {
405 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
406 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
407 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
408 flags |= PIPE_CONTROL_FLUSH_ENABLE;
409 }
410 if (invalidate_domains) {
411 flags |= PIPE_CONTROL_TLB_INVALIDATE;
412 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
413 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
414 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
415 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
416 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
417 flags |= PIPE_CONTROL_QW_WRITE;
418 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
419
420 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
421 ret = gen8_emit_pipe_control(req,
422 PIPE_CONTROL_CS_STALL |
423 PIPE_CONTROL_STALL_AT_SCOREBOARD,
424 0);
425 if (ret)
426 return ret;
427 }
428
429 return gen8_emit_pipe_control(req, flags, scratch_addr);
430}
431
432static void ring_write_tail(struct intel_engine_cs *ring,
433 u32 value)
434{
435 struct drm_i915_private *dev_priv = ring->dev->dev_private;
436 I915_WRITE_TAIL(ring, value);
437}
438
439u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
440{
441 struct drm_i915_private *dev_priv = ring->dev->dev_private;
442 u64 acthd;
443
444 if (INTEL_INFO(ring->dev)->gen >= 8)
445 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
446 RING_ACTHD_UDW(ring->mmio_base));
447 else if (INTEL_INFO(ring->dev)->gen >= 4)
448 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
449 else
450 acthd = I915_READ(ACTHD);
451
452 return acthd;
453}
454
455static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
456{
457 struct drm_i915_private *dev_priv = ring->dev->dev_private;
458 u32 addr;
459
460 addr = dev_priv->status_page_dmah->busaddr;
461 if (INTEL_INFO(ring->dev)->gen >= 4)
462 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
463 I915_WRITE(HWS_PGA, addr);
464}
465
466static void intel_ring_setup_status_page(struct intel_engine_cs *ring)
467{
468 struct drm_device *dev = ring->dev;
469 struct drm_i915_private *dev_priv = ring->dev->dev_private;
470 i915_reg_t mmio;
471
472 /* The ring status page addresses are no longer next to the rest of
473 * the ring registers as of gen7.
474 */
475 if (IS_GEN7(dev)) {
476 switch (ring->id) {
477 case RCS:
478 mmio = RENDER_HWS_PGA_GEN7;
479 break;
480 case BCS:
481 mmio = BLT_HWS_PGA_GEN7;
482 break;
483 /*
484 * VCS2 actually doesn't exist on Gen7. Only shut up
485 * gcc switch check warning
486 */
487 case VCS2:
488 case VCS:
489 mmio = BSD_HWS_PGA_GEN7;
490 break;
491 case VECS:
492 mmio = VEBOX_HWS_PGA_GEN7;
493 break;
494 }
495 } else if (IS_GEN6(ring->dev)) {
496 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
497 } else {
498 /* XXX: gen8 returns to sanity */
499 mmio = RING_HWS_PGA(ring->mmio_base);
500 }
501
502 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
503 POSTING_READ(mmio);
504
505 /*
506 * Flush the TLB for this page
507 *
508 * FIXME: These two bits have disappeared on gen8, so a question
509 * arises: do we still need this and if so how should we go about
510 * invalidating the TLB?
511 */
512 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
513 i915_reg_t reg = RING_INSTPM(ring->mmio_base);
514
515 /* ring should be idle before issuing a sync flush*/
516 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
517
518 I915_WRITE(reg,
519 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
520 INSTPM_SYNC_FLUSH));
521 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
522 1000))
523 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
524 ring->name);
525 }
526}
527
528static bool stop_ring(struct intel_engine_cs *ring)
529{
530 struct drm_i915_private *dev_priv = to_i915(ring->dev);
531
532 if (!IS_GEN2(ring->dev)) {
533 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
534 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
535 DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
536 /* Sometimes we observe that the idle flag is not
537 * set even though the ring is empty. So double
538 * check before giving up.
539 */
540 if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
541 return false;
542 }
543 }
544
545 I915_WRITE_CTL(ring, 0);
546 I915_WRITE_HEAD(ring, 0);
547 ring->write_tail(ring, 0);
548
549 if (!IS_GEN2(ring->dev)) {
550 (void)I915_READ_CTL(ring);
551 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
552 }
553
554 return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
555}
556
557static int init_ring_common(struct intel_engine_cs *ring)
558{
559 struct drm_device *dev = ring->dev;
560 struct drm_i915_private *dev_priv = dev->dev_private;
561 struct intel_ringbuffer *ringbuf = ring->buffer;
562 struct drm_i915_gem_object *obj = ringbuf->obj;
563 int ret = 0;
564
565 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
566
567 if (!stop_ring(ring)) {
568 /* G45 ring initialization often fails to reset head to zero */
569 DRM_DEBUG_KMS("%s head not reset to zero "
570 "ctl %08x head %08x tail %08x start %08x\n",
571 ring->name,
572 I915_READ_CTL(ring),
573 I915_READ_HEAD(ring),
574 I915_READ_TAIL(ring),
575 I915_READ_START(ring));
576
577 if (!stop_ring(ring)) {
578 DRM_ERROR("failed to set %s head to zero "
579 "ctl %08x head %08x tail %08x start %08x\n",
580 ring->name,
581 I915_READ_CTL(ring),
582 I915_READ_HEAD(ring),
583 I915_READ_TAIL(ring),
584 I915_READ_START(ring));
585 ret = -EIO;
586 goto out;
587 }
588 }
589
590 if (I915_NEED_GFX_HWS(dev))
591 intel_ring_setup_status_page(ring);
592 else
593 ring_setup_phys_status_page(ring);
594
595 /* Enforce ordering by reading HEAD register back */
596 I915_READ_HEAD(ring);
597
598 /* Initialize the ring. This must happen _after_ we've cleared the ring
599 * registers with the above sequence (the readback of the HEAD registers
600 * also enforces ordering), otherwise the hw might lose the new ring
601 * register values. */
602 I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
603
604 /* WaClearRingBufHeadRegAtInit:ctg,elk */
605 if (I915_READ_HEAD(ring))
606 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
607 ring->name, I915_READ_HEAD(ring));
608 I915_WRITE_HEAD(ring, 0);
609 (void)I915_READ_HEAD(ring);
610
611 I915_WRITE_CTL(ring,
612 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
613 | RING_VALID);
614
615 /* If the head is still not zero, the ring is dead */
616 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
617 I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
618 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
619 DRM_ERROR("%s initialization failed "
620 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
621 ring->name,
622 I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
623 I915_READ_HEAD(ring), I915_READ_TAIL(ring),
624 I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
625 ret = -EIO;
626 goto out;
627 }
628
629 ringbuf->last_retired_head = -1;
630 ringbuf->head = I915_READ_HEAD(ring);
631 ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
632 intel_ring_update_space(ringbuf);
633
634 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
635
636out:
637 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
638
639 return ret;
640}
641
642void
643intel_fini_pipe_control(struct intel_engine_cs *ring)
644{
645 struct drm_device *dev = ring->dev;
646
647 if (ring->scratch.obj == NULL)
648 return;
649
650 if (INTEL_INFO(dev)->gen >= 5) {
651 kunmap(sg_page(ring->scratch.obj->pages->sgl));
652 i915_gem_object_ggtt_unpin(ring->scratch.obj);
653 }
654
655 drm_gem_object_unreference(&ring->scratch.obj->base);
656 ring->scratch.obj = NULL;
657}
658
659int
660intel_init_pipe_control(struct intel_engine_cs *ring)
661{
662 int ret;
663
664 WARN_ON(ring->scratch.obj);
665
666 ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
667 if (ring->scratch.obj == NULL) {
668 DRM_ERROR("Failed to allocate seqno page\n");
669 ret = -ENOMEM;
670 goto err;
671 }
672
673 ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
674 if (ret)
675 goto err_unref;
676
677 ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
678 if (ret)
679 goto err_unref;
680
681 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
682 ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
683 if (ring->scratch.cpu_page == NULL) {
684 ret = -ENOMEM;
685 goto err_unpin;
686 }
687
688 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
689 ring->name, ring->scratch.gtt_offset);
690 return 0;
691
692err_unpin:
693 i915_gem_object_ggtt_unpin(ring->scratch.obj);
694err_unref:
695 drm_gem_object_unreference(&ring->scratch.obj->base);
696err:
697 return ret;
698}
699
700static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
701{
702 int ret, i;
703 struct intel_engine_cs *ring = req->ring;
704 struct drm_device *dev = ring->dev;
705 struct drm_i915_private *dev_priv = dev->dev_private;
706 struct i915_workarounds *w = &dev_priv->workarounds;
707
708 if (w->count == 0)
709 return 0;
710
711 ring->gpu_caches_dirty = true;
712 ret = intel_ring_flush_all_caches(req);
713 if (ret)
714 return ret;
715
716 ret = intel_ring_begin(req, (w->count * 2 + 2));
717 if (ret)
718 return ret;
719
720 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
721 for (i = 0; i < w->count; i++) {
722 intel_ring_emit_reg(ring, w->reg[i].addr);
723 intel_ring_emit(ring, w->reg[i].value);
724 }
725 intel_ring_emit(ring, MI_NOOP);
726
727 intel_ring_advance(ring);
728
729 ring->gpu_caches_dirty = true;
730 ret = intel_ring_flush_all_caches(req);
731 if (ret)
732 return ret;
733
734 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
735
736 return 0;
737}
738
739static int intel_rcs_ctx_init(struct drm_i915_gem_request *req)
740{
741 int ret;
742
743 ret = intel_ring_workarounds_emit(req);
744 if (ret != 0)
745 return ret;
746
747 ret = i915_gem_render_state_init(req);
748 if (ret)
749 return ret;
750
751 return 0;
752}
753
754static int wa_add(struct drm_i915_private *dev_priv,
755 i915_reg_t addr,
756 const u32 mask, const u32 val)
757{
758 const u32 idx = dev_priv->workarounds.count;
759
760 if (WARN_ON(idx >= I915_MAX_WA_REGS))
761 return -ENOSPC;
762
763 dev_priv->workarounds.reg[idx].addr = addr;
764 dev_priv->workarounds.reg[idx].value = val;
765 dev_priv->workarounds.reg[idx].mask = mask;
766
767 dev_priv->workarounds.count++;
768
769 return 0;
770}
771
772#define WA_REG(addr, mask, val) do { \
773 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
774 if (r) \
775 return r; \
776 } while (0)
777
778#define WA_SET_BIT_MASKED(addr, mask) \
779 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
780
781#define WA_CLR_BIT_MASKED(addr, mask) \
782 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
783
784#define WA_SET_FIELD_MASKED(addr, mask, value) \
785 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
786
787#define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
788#define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
789
790#define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
791
792static int wa_ring_whitelist_reg(struct intel_engine_cs *ring, i915_reg_t reg)
793{
794 struct drm_i915_private *dev_priv = ring->dev->dev_private;
795 struct i915_workarounds *wa = &dev_priv->workarounds;
796 const uint32_t index = wa->hw_whitelist_count[ring->id];
797
798 if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS))
799 return -EINVAL;
800
801 WA_WRITE(RING_FORCE_TO_NONPRIV(ring->mmio_base, index),
802 i915_mmio_reg_offset(reg));
803 wa->hw_whitelist_count[ring->id]++;
804
805 return 0;
806}
807
808static int gen8_init_workarounds(struct intel_engine_cs *ring)
809{
810 struct drm_device *dev = ring->dev;
811 struct drm_i915_private *dev_priv = dev->dev_private;
812
813 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
814
815 /* WaDisableAsyncFlipPerfMode:bdw,chv */
816 WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
817
818 /* WaDisablePartialInstShootdown:bdw,chv */
819 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
820 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
821
822 /* Use Force Non-Coherent whenever executing a 3D context. This is a
823 * workaround for for a possible hang in the unlikely event a TLB
824 * invalidation occurs during a PSD flush.
825 */
826 /* WaForceEnableNonCoherent:bdw,chv */
827 /* WaHdcDisableFetchWhenMasked:bdw,chv */
828 WA_SET_BIT_MASKED(HDC_CHICKEN0,
829 HDC_DONOT_FETCH_MEM_WHEN_MASKED |
830 HDC_FORCE_NON_COHERENT);
831
832 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
833 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
834 * polygons in the same 8x4 pixel/sample area to be processed without
835 * stalling waiting for the earlier ones to write to Hierarchical Z
836 * buffer."
837 *
838 * This optimization is off by default for BDW and CHV; turn it on.
839 */
840 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
841
842 /* Wa4x4STCOptimizationDisable:bdw,chv */
843 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
844
845 /*
846 * BSpec recommends 8x4 when MSAA is used,
847 * however in practice 16x4 seems fastest.
848 *
849 * Note that PS/WM thread counts depend on the WIZ hashing
850 * disable bit, which we don't touch here, but it's good
851 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
852 */
853 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
854 GEN6_WIZ_HASHING_MASK,
855 GEN6_WIZ_HASHING_16x4);
856
857 return 0;
858}
859
860static int bdw_init_workarounds(struct intel_engine_cs *ring)
861{
862 int ret;
863 struct drm_device *dev = ring->dev;
864 struct drm_i915_private *dev_priv = dev->dev_private;
865
866 ret = gen8_init_workarounds(ring);
867 if (ret)
868 return ret;
869
870 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
871 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
872
873 /* WaDisableDopClockGating:bdw */
874 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
875 DOP_CLOCK_GATING_DISABLE);
876
877 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
878 GEN8_SAMPLER_POWER_BYPASS_DIS);
879
880 WA_SET_BIT_MASKED(HDC_CHICKEN0,
881 /* WaForceContextSaveRestoreNonCoherent:bdw */
882 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
883 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
884 (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
885
886 return 0;
887}
888
889static int chv_init_workarounds(struct intel_engine_cs *ring)
890{
891 int ret;
892 struct drm_device *dev = ring->dev;
893 struct drm_i915_private *dev_priv = dev->dev_private;
894
895 ret = gen8_init_workarounds(ring);
896 if (ret)
897 return ret;
898
899 /* WaDisableThreadStallDopClockGating:chv */
900 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
901
902 /* Improve HiZ throughput on CHV. */
903 WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
904
905 return 0;
906}
907
908static int gen9_init_workarounds(struct intel_engine_cs *ring)
909{
910 struct drm_device *dev = ring->dev;
911 struct drm_i915_private *dev_priv = dev->dev_private;
912 uint32_t tmp;
913 int ret;
914
915 /* WaEnableLbsSlaRetryTimerDecrement:skl */
916 I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
917 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
918
919 /* WaDisableKillLogic:bxt,skl */
920 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
921 ECOCHK_DIS_TLB);
922
923 /* WaDisablePartialInstShootdown:skl,bxt */
924 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
925 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
926
927 /* Syncing dependencies between camera and graphics:skl,bxt */
928 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
929 GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
930
931 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
932 if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
933 IS_BXT_REVID(dev, 0, BXT_REVID_A1))
934 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
935 GEN9_DG_MIRROR_FIX_ENABLE);
936
937 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
938 if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
939 IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
940 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
941 GEN9_RHWO_OPTIMIZATION_DISABLE);
942 /*
943 * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
944 * but we do that in per ctx batchbuffer as there is an issue
945 * with this register not getting restored on ctx restore
946 */
947 }
948
949 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
950 if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER) || IS_BROXTON(dev))
951 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
952 GEN9_ENABLE_YV12_BUGFIX);
953
954 /* Wa4x4STCOptimizationDisable:skl,bxt */
955 /* WaDisablePartialResolveInVc:skl,bxt */
956 WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
957 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
958
959 /* WaCcsTlbPrefetchDisable:skl,bxt */
960 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
961 GEN9_CCS_TLB_PREFETCH_ENABLE);
962
963 /* WaDisableMaskBasedCammingInRCC:skl,bxt */
964 if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_C0) ||
965 IS_BXT_REVID(dev, 0, BXT_REVID_A1))
966 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
967 PIXEL_MASK_CAMMING_DISABLE);
968
969 /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
970 tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
971 if (IS_SKL_REVID(dev, SKL_REVID_F0, REVID_FOREVER) ||
972 IS_BXT_REVID(dev, BXT_REVID_B0, REVID_FOREVER))
973 tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
974 WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
975
976 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */
977 if (IS_SKYLAKE(dev) || IS_BXT_REVID(dev, 0, BXT_REVID_B0))
978 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
979 GEN8_SAMPLER_POWER_BYPASS_DIS);
980
981 /* WaDisableSTUnitPowerOptimization:skl,bxt */
982 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
983
984 /* WaOCLCoherentLineFlush:skl,bxt */
985 I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
986 GEN8_LQSC_FLUSH_COHERENT_LINES));
987
988 /* WaEnablePreemptionGranularityControlByUMD:skl,bxt */
989 ret= wa_ring_whitelist_reg(ring, GEN8_CS_CHICKEN1);
990 if (ret)
991 return ret;
992
993 /* WaAllowUMDToModifyHDCChicken1:skl,bxt */
994 ret = wa_ring_whitelist_reg(ring, GEN8_HDC_CHICKEN1);
995 if (ret)
996 return ret;
997
998 return 0;
999}
1000
1001static int skl_tune_iz_hashing(struct intel_engine_cs *ring)
1002{
1003 struct drm_device *dev = ring->dev;
1004 struct drm_i915_private *dev_priv = dev->dev_private;
1005 u8 vals[3] = { 0, 0, 0 };
1006 unsigned int i;
1007
1008 for (i = 0; i < 3; i++) {
1009 u8 ss;
1010
1011 /*
1012 * Only consider slices where one, and only one, subslice has 7
1013 * EUs
1014 */
1015 if (!is_power_of_2(dev_priv->info.subslice_7eu[i]))
1016 continue;
1017
1018 /*
1019 * subslice_7eu[i] != 0 (because of the check above) and
1020 * ss_max == 4 (maximum number of subslices possible per slice)
1021 *
1022 * -> 0 <= ss <= 3;
1023 */
1024 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
1025 vals[i] = 3 - ss;
1026 }
1027
1028 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
1029 return 0;
1030
1031 /* Tune IZ hashing. See intel_device_info_runtime_init() */
1032 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1033 GEN9_IZ_HASHING_MASK(2) |
1034 GEN9_IZ_HASHING_MASK(1) |
1035 GEN9_IZ_HASHING_MASK(0),
1036 GEN9_IZ_HASHING(2, vals[2]) |
1037 GEN9_IZ_HASHING(1, vals[1]) |
1038 GEN9_IZ_HASHING(0, vals[0]));
1039
1040 return 0;
1041}
1042
1043static int skl_init_workarounds(struct intel_engine_cs *ring)
1044{
1045 int ret;
1046 struct drm_device *dev = ring->dev;
1047 struct drm_i915_private *dev_priv = dev->dev_private;
1048
1049 ret = gen9_init_workarounds(ring);
1050 if (ret)
1051 return ret;
1052
1053 /*
1054 * Actual WA is to disable percontext preemption granularity control
1055 * until D0 which is the default case so this is equivalent to
1056 * !WaDisablePerCtxtPreemptionGranularityControl:skl
1057 */
1058 if (IS_SKL_REVID(dev, SKL_REVID_E0, REVID_FOREVER)) {
1059 I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
1060 _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
1061 }
1062
1063 if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) {
1064 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
1065 I915_WRITE(FF_SLICE_CS_CHICKEN2,
1066 _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
1067 }
1068
1069 /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1070 * involving this register should also be added to WA batch as required.
1071 */
1072 if (IS_SKL_REVID(dev, 0, SKL_REVID_E0))
1073 /* WaDisableLSQCROPERFforOCL:skl */
1074 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
1075 GEN8_LQSC_RO_PERF_DIS);
1076
1077 /* WaEnableGapsTsvCreditFix:skl */
1078 if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER)) {
1079 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
1080 GEN9_GAPS_TSV_CREDIT_DISABLE));
1081 }
1082
1083 /* WaDisablePowerCompilerClockGating:skl */
1084 if (IS_SKL_REVID(dev, SKL_REVID_B0, SKL_REVID_B0))
1085 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1086 BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1087
1088 /* This is tied to WaForceContextSaveRestoreNonCoherent */
1089 if (IS_SKL_REVID(dev, 0, REVID_FOREVER)) {
1090 /*
1091 *Use Force Non-Coherent whenever executing a 3D context. This
1092 * is a workaround for a possible hang in the unlikely event
1093 * a TLB invalidation occurs during a PSD flush.
1094 */
1095 /* WaForceEnableNonCoherent:skl */
1096 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1097 HDC_FORCE_NON_COHERENT);
1098
1099 /* WaDisableHDCInvalidation:skl */
1100 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
1101 BDW_DISABLE_HDC_INVALIDATION);
1102 }
1103
1104 /* WaBarrierPerformanceFixDisable:skl */
1105 if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_D0))
1106 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1107 HDC_FENCE_DEST_SLM_DISABLE |
1108 HDC_BARRIER_PERFORMANCE_DISABLE);
1109
1110 /* WaDisableSbeCacheDispatchPortSharing:skl */
1111 if (IS_SKL_REVID(dev, 0, SKL_REVID_F0))
1112 WA_SET_BIT_MASKED(
1113 GEN7_HALF_SLICE_CHICKEN1,
1114 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1115
1116 /* WaDisableLSQCROPERFforOCL:skl */
1117 ret = wa_ring_whitelist_reg(ring, GEN8_L3SQCREG4);
1118 if (ret)
1119 return ret;
1120
1121 return skl_tune_iz_hashing(ring);
1122}
1123
1124static int bxt_init_workarounds(struct intel_engine_cs *ring)
1125{
1126 int ret;
1127 struct drm_device *dev = ring->dev;
1128 struct drm_i915_private *dev_priv = dev->dev_private;
1129
1130 ret = gen9_init_workarounds(ring);
1131 if (ret)
1132 return ret;
1133
1134 /* WaStoreMultiplePTEenable:bxt */
1135 /* This is a requirement according to Hardware specification */
1136 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
1137 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
1138
1139 /* WaSetClckGatingDisableMedia:bxt */
1140 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
1141 I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
1142 ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
1143 }
1144
1145 /* WaDisableThreadStallDopClockGating:bxt */
1146 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1147 STALL_DOP_GATING_DISABLE);
1148
1149 /* WaDisableSbeCacheDispatchPortSharing:bxt */
1150 if (IS_BXT_REVID(dev, 0, BXT_REVID_B0)) {
1151 WA_SET_BIT_MASKED(
1152 GEN7_HALF_SLICE_CHICKEN1,
1153 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1154 }
1155
1156 /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */
1157 /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */
1158 /* WaDisableObjectLevelPreemtionForInstanceId:bxt */
1159 /* WaDisableLSQCROPERFforOCL:bxt */
1160 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
1161 ret = wa_ring_whitelist_reg(ring, GEN9_CS_DEBUG_MODE1);
1162 if (ret)
1163 return ret;
1164
1165 ret = wa_ring_whitelist_reg(ring, GEN8_L3SQCREG4);
1166 if (ret)
1167 return ret;
1168 }
1169
1170 return 0;
1171}
1172
1173int init_workarounds_ring(struct intel_engine_cs *ring)
1174{
1175 struct drm_device *dev = ring->dev;
1176 struct drm_i915_private *dev_priv = dev->dev_private;
1177
1178 WARN_ON(ring->id != RCS);
1179
1180 dev_priv->workarounds.count = 0;
1181 dev_priv->workarounds.hw_whitelist_count[RCS] = 0;
1182
1183 if (IS_BROADWELL(dev))
1184 return bdw_init_workarounds(ring);
1185
1186 if (IS_CHERRYVIEW(dev))
1187 return chv_init_workarounds(ring);
1188
1189 if (IS_SKYLAKE(dev))
1190 return skl_init_workarounds(ring);
1191
1192 if (IS_BROXTON(dev))
1193 return bxt_init_workarounds(ring);
1194
1195 return 0;
1196}
1197
1198static int init_render_ring(struct intel_engine_cs *ring)
1199{
1200 struct drm_device *dev = ring->dev;
1201 struct drm_i915_private *dev_priv = dev->dev_private;
1202 int ret = init_ring_common(ring);
1203 if (ret)
1204 return ret;
1205
1206 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1207 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
1208 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1209
1210 /* We need to disable the AsyncFlip performance optimisations in order
1211 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1212 * programmed to '1' on all products.
1213 *
1214 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1215 */
1216 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1217 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1218
1219 /* Required for the hardware to program scanline values for waiting */
1220 /* WaEnableFlushTlbInvalidationMode:snb */
1221 if (INTEL_INFO(dev)->gen == 6)
1222 I915_WRITE(GFX_MODE,
1223 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
1224
1225 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1226 if (IS_GEN7(dev))
1227 I915_WRITE(GFX_MODE_GEN7,
1228 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1229 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
1230
1231 if (IS_GEN6(dev)) {
1232 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1233 * "If this bit is set, STCunit will have LRA as replacement
1234 * policy. [...] This bit must be reset. LRA replacement
1235 * policy is not supported."
1236 */
1237 I915_WRITE(CACHE_MODE_0,
1238 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
1239 }
1240
1241 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1242 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1243
1244 if (HAS_L3_DPF(dev))
1245 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1246
1247 return init_workarounds_ring(ring);
1248}
1249
1250static void render_ring_cleanup(struct intel_engine_cs *ring)
1251{
1252 struct drm_device *dev = ring->dev;
1253 struct drm_i915_private *dev_priv = dev->dev_private;
1254
1255 if (dev_priv->semaphore_obj) {
1256 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1257 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1258 dev_priv->semaphore_obj = NULL;
1259 }
1260
1261 intel_fini_pipe_control(ring);
1262}
1263
1264static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
1265 unsigned int num_dwords)
1266{
1267#define MBOX_UPDATE_DWORDS 8
1268 struct intel_engine_cs *signaller = signaller_req->ring;
1269 struct drm_device *dev = signaller->dev;
1270 struct drm_i915_private *dev_priv = dev->dev_private;
1271 struct intel_engine_cs *waiter;
1272 int i, ret, num_rings;
1273
1274 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1275 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1276#undef MBOX_UPDATE_DWORDS
1277
1278 ret = intel_ring_begin(signaller_req, num_dwords);
1279 if (ret)
1280 return ret;
1281
1282 for_each_ring(waiter, dev_priv, i) {
1283 u32 seqno;
1284 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1285 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1286 continue;
1287
1288 seqno = i915_gem_request_get_seqno(signaller_req);
1289 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1290 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1291 PIPE_CONTROL_QW_WRITE |
1292 PIPE_CONTROL_FLUSH_ENABLE);
1293 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1294 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1295 intel_ring_emit(signaller, seqno);
1296 intel_ring_emit(signaller, 0);
1297 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1298 MI_SEMAPHORE_TARGET(waiter->id));
1299 intel_ring_emit(signaller, 0);
1300 }
1301
1302 return 0;
1303}
1304
1305static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
1306 unsigned int num_dwords)
1307{
1308#define MBOX_UPDATE_DWORDS 6
1309 struct intel_engine_cs *signaller = signaller_req->ring;
1310 struct drm_device *dev = signaller->dev;
1311 struct drm_i915_private *dev_priv = dev->dev_private;
1312 struct intel_engine_cs *waiter;
1313 int i, ret, num_rings;
1314
1315 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1316 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1317#undef MBOX_UPDATE_DWORDS
1318
1319 ret = intel_ring_begin(signaller_req, num_dwords);
1320 if (ret)
1321 return ret;
1322
1323 for_each_ring(waiter, dev_priv, i) {
1324 u32 seqno;
1325 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1326 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1327 continue;
1328
1329 seqno = i915_gem_request_get_seqno(signaller_req);
1330 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1331 MI_FLUSH_DW_OP_STOREDW);
1332 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1333 MI_FLUSH_DW_USE_GTT);
1334 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1335 intel_ring_emit(signaller, seqno);
1336 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1337 MI_SEMAPHORE_TARGET(waiter->id));
1338 intel_ring_emit(signaller, 0);
1339 }
1340
1341 return 0;
1342}
1343
1344static int gen6_signal(struct drm_i915_gem_request *signaller_req,
1345 unsigned int num_dwords)
1346{
1347 struct intel_engine_cs *signaller = signaller_req->ring;
1348 struct drm_device *dev = signaller->dev;
1349 struct drm_i915_private *dev_priv = dev->dev_private;
1350 struct intel_engine_cs *useless;
1351 int i, ret, num_rings;
1352
1353#define MBOX_UPDATE_DWORDS 3
1354 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1355 num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1356#undef MBOX_UPDATE_DWORDS
1357
1358 ret = intel_ring_begin(signaller_req, num_dwords);
1359 if (ret)
1360 return ret;
1361
1362 for_each_ring(useless, dev_priv, i) {
1363 i915_reg_t mbox_reg = signaller->semaphore.mbox.signal[i];
1364
1365 if (i915_mmio_reg_valid(mbox_reg)) {
1366 u32 seqno = i915_gem_request_get_seqno(signaller_req);
1367
1368 intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1369 intel_ring_emit_reg(signaller, mbox_reg);
1370 intel_ring_emit(signaller, seqno);
1371 }
1372 }
1373
1374 /* If num_dwords was rounded, make sure the tail pointer is correct */
1375 if (num_rings % 2 == 0)
1376 intel_ring_emit(signaller, MI_NOOP);
1377
1378 return 0;
1379}
1380
1381/**
1382 * gen6_add_request - Update the semaphore mailbox registers
1383 *
1384 * @request - request to write to the ring
1385 *
1386 * Update the mailbox registers in the *other* rings with the current seqno.
1387 * This acts like a signal in the canonical semaphore.
1388 */
1389static int
1390gen6_add_request(struct drm_i915_gem_request *req)
1391{
1392 struct intel_engine_cs *ring = req->ring;
1393 int ret;
1394
1395 if (ring->semaphore.signal)
1396 ret = ring->semaphore.signal(req, 4);
1397 else
1398 ret = intel_ring_begin(req, 4);
1399
1400 if (ret)
1401 return ret;
1402
1403 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1404 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1405 intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1406 intel_ring_emit(ring, MI_USER_INTERRUPT);
1407 __intel_ring_advance(ring);
1408
1409 return 0;
1410}
1411
1412static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1413 u32 seqno)
1414{
1415 struct drm_i915_private *dev_priv = dev->dev_private;
1416 return dev_priv->last_seqno < seqno;
1417}
1418
1419/**
1420 * intel_ring_sync - sync the waiter to the signaller on seqno
1421 *
1422 * @waiter - ring that is waiting
1423 * @signaller - ring which has, or will signal
1424 * @seqno - seqno which the waiter will block on
1425 */
1426
1427static int
1428gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
1429 struct intel_engine_cs *signaller,
1430 u32 seqno)
1431{
1432 struct intel_engine_cs *waiter = waiter_req->ring;
1433 struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1434 int ret;
1435
1436 ret = intel_ring_begin(waiter_req, 4);
1437 if (ret)
1438 return ret;
1439
1440 intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1441 MI_SEMAPHORE_GLOBAL_GTT |
1442 MI_SEMAPHORE_POLL |
1443 MI_SEMAPHORE_SAD_GTE_SDD);
1444 intel_ring_emit(waiter, seqno);
1445 intel_ring_emit(waiter,
1446 lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1447 intel_ring_emit(waiter,
1448 upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1449 intel_ring_advance(waiter);
1450 return 0;
1451}
1452
1453static int
1454gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
1455 struct intel_engine_cs *signaller,
1456 u32 seqno)
1457{
1458 struct intel_engine_cs *waiter = waiter_req->ring;
1459 u32 dw1 = MI_SEMAPHORE_MBOX |
1460 MI_SEMAPHORE_COMPARE |
1461 MI_SEMAPHORE_REGISTER;
1462 u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1463 int ret;
1464
1465 /* Throughout all of the GEM code, seqno passed implies our current
1466 * seqno is >= the last seqno executed. However for hardware the
1467 * comparison is strictly greater than.
1468 */
1469 seqno -= 1;
1470
1471 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
1472
1473 ret = intel_ring_begin(waiter_req, 4);
1474 if (ret)
1475 return ret;
1476
1477 /* If seqno wrap happened, omit the wait with no-ops */
1478 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
1479 intel_ring_emit(waiter, dw1 | wait_mbox);
1480 intel_ring_emit(waiter, seqno);
1481 intel_ring_emit(waiter, 0);
1482 intel_ring_emit(waiter, MI_NOOP);
1483 } else {
1484 intel_ring_emit(waiter, MI_NOOP);
1485 intel_ring_emit(waiter, MI_NOOP);
1486 intel_ring_emit(waiter, MI_NOOP);
1487 intel_ring_emit(waiter, MI_NOOP);
1488 }
1489 intel_ring_advance(waiter);
1490
1491 return 0;
1492}
1493
1494#define PIPE_CONTROL_FLUSH(ring__, addr__) \
1495do { \
1496 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1497 PIPE_CONTROL_DEPTH_STALL); \
1498 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1499 intel_ring_emit(ring__, 0); \
1500 intel_ring_emit(ring__, 0); \
1501} while (0)
1502
1503static int
1504pc_render_add_request(struct drm_i915_gem_request *req)
1505{
1506 struct intel_engine_cs *ring = req->ring;
1507 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1508 int ret;
1509
1510 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1511 * incoherent with writes to memory, i.e. completely fubar,
1512 * so we need to use PIPE_NOTIFY instead.
1513 *
1514 * However, we also need to workaround the qword write
1515 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1516 * memory before requesting an interrupt.
1517 */
1518 ret = intel_ring_begin(req, 32);
1519 if (ret)
1520 return ret;
1521
1522 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1523 PIPE_CONTROL_WRITE_FLUSH |
1524 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
1525 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1526 intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1527 intel_ring_emit(ring, 0);
1528 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1529 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
1530 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1531 scratch_addr += 2 * CACHELINE_BYTES;
1532 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1533 scratch_addr += 2 * CACHELINE_BYTES;
1534 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1535 scratch_addr += 2 * CACHELINE_BYTES;
1536 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1537 scratch_addr += 2 * CACHELINE_BYTES;
1538 PIPE_CONTROL_FLUSH(ring, scratch_addr);
1539
1540 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1541 PIPE_CONTROL_WRITE_FLUSH |
1542 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1543 PIPE_CONTROL_NOTIFY);
1544 intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1545 intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1546 intel_ring_emit(ring, 0);
1547 __intel_ring_advance(ring);
1548
1549 return 0;
1550}
1551
1552static u32
1553gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1554{
1555 /* Workaround to force correct ordering between irq and seqno writes on
1556 * ivb (and maybe also on snb) by reading from a CS register (like
1557 * ACTHD) before reading the status page. */
1558 if (!lazy_coherency) {
1559 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1560 POSTING_READ(RING_ACTHD(ring->mmio_base));
1561 }
1562
1563 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1564}
1565
1566static u32
1567ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1568{
1569 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1570}
1571
1572static void
1573ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1574{
1575 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1576}
1577
1578static u32
1579pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1580{
1581 return ring->scratch.cpu_page[0];
1582}
1583
1584static void
1585pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1586{
1587 ring->scratch.cpu_page[0] = seqno;
1588}
1589
1590static bool
1591gen5_ring_get_irq(struct intel_engine_cs *ring)
1592{
1593 struct drm_device *dev = ring->dev;
1594 struct drm_i915_private *dev_priv = dev->dev_private;
1595 unsigned long flags;
1596
1597 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1598 return false;
1599
1600 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1601 if (ring->irq_refcount++ == 0)
1602 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1603 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1604
1605 return true;
1606}
1607
1608static void
1609gen5_ring_put_irq(struct intel_engine_cs *ring)
1610{
1611 struct drm_device *dev = ring->dev;
1612 struct drm_i915_private *dev_priv = dev->dev_private;
1613 unsigned long flags;
1614
1615 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1616 if (--ring->irq_refcount == 0)
1617 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1618 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1619}
1620
1621static bool
1622i9xx_ring_get_irq(struct intel_engine_cs *ring)
1623{
1624 struct drm_device *dev = ring->dev;
1625 struct drm_i915_private *dev_priv = dev->dev_private;
1626 unsigned long flags;
1627
1628 if (!intel_irqs_enabled(dev_priv))
1629 return false;
1630
1631 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1632 if (ring->irq_refcount++ == 0) {
1633 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1634 I915_WRITE(IMR, dev_priv->irq_mask);
1635 POSTING_READ(IMR);
1636 }
1637 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1638
1639 return true;
1640}
1641
1642static void
1643i9xx_ring_put_irq(struct intel_engine_cs *ring)
1644{
1645 struct drm_device *dev = ring->dev;
1646 struct drm_i915_private *dev_priv = dev->dev_private;
1647 unsigned long flags;
1648
1649 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1650 if (--ring->irq_refcount == 0) {
1651 dev_priv->irq_mask |= ring->irq_enable_mask;
1652 I915_WRITE(IMR, dev_priv->irq_mask);
1653 POSTING_READ(IMR);
1654 }
1655 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1656}
1657
1658static bool
1659i8xx_ring_get_irq(struct intel_engine_cs *ring)
1660{
1661 struct drm_device *dev = ring->dev;
1662 struct drm_i915_private *dev_priv = dev->dev_private;
1663 unsigned long flags;
1664
1665 if (!intel_irqs_enabled(dev_priv))
1666 return false;
1667
1668 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1669 if (ring->irq_refcount++ == 0) {
1670 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1671 I915_WRITE16(IMR, dev_priv->irq_mask);
1672 POSTING_READ16(IMR);
1673 }
1674 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1675
1676 return true;
1677}
1678
1679static void
1680i8xx_ring_put_irq(struct intel_engine_cs *ring)
1681{
1682 struct drm_device *dev = ring->dev;
1683 struct drm_i915_private *dev_priv = dev->dev_private;
1684 unsigned long flags;
1685
1686 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1687 if (--ring->irq_refcount == 0) {
1688 dev_priv->irq_mask |= ring->irq_enable_mask;
1689 I915_WRITE16(IMR, dev_priv->irq_mask);
1690 POSTING_READ16(IMR);
1691 }
1692 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1693}
1694
1695static int
1696bsd_ring_flush(struct drm_i915_gem_request *req,
1697 u32 invalidate_domains,
1698 u32 flush_domains)
1699{
1700 struct intel_engine_cs *ring = req->ring;
1701 int ret;
1702
1703 ret = intel_ring_begin(req, 2);
1704 if (ret)
1705 return ret;
1706
1707 intel_ring_emit(ring, MI_FLUSH);
1708 intel_ring_emit(ring, MI_NOOP);
1709 intel_ring_advance(ring);
1710 return 0;
1711}
1712
1713static int
1714i9xx_add_request(struct drm_i915_gem_request *req)
1715{
1716 struct intel_engine_cs *ring = req->ring;
1717 int ret;
1718
1719 ret = intel_ring_begin(req, 4);
1720 if (ret)
1721 return ret;
1722
1723 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1724 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1725 intel_ring_emit(ring, i915_gem_request_get_seqno(req));
1726 intel_ring_emit(ring, MI_USER_INTERRUPT);
1727 __intel_ring_advance(ring);
1728
1729 return 0;
1730}
1731
1732static bool
1733gen6_ring_get_irq(struct intel_engine_cs *ring)
1734{
1735 struct drm_device *dev = ring->dev;
1736 struct drm_i915_private *dev_priv = dev->dev_private;
1737 unsigned long flags;
1738
1739 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1740 return false;
1741
1742 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1743 if (ring->irq_refcount++ == 0) {
1744 if (HAS_L3_DPF(dev) && ring->id == RCS)
1745 I915_WRITE_IMR(ring,
1746 ~(ring->irq_enable_mask |
1747 GT_PARITY_ERROR(dev)));
1748 else
1749 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1750 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1751 }
1752 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1753
1754 return true;
1755}
1756
1757static void
1758gen6_ring_put_irq(struct intel_engine_cs *ring)
1759{
1760 struct drm_device *dev = ring->dev;
1761 struct drm_i915_private *dev_priv = dev->dev_private;
1762 unsigned long flags;
1763
1764 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1765 if (--ring->irq_refcount == 0) {
1766 if (HAS_L3_DPF(dev) && ring->id == RCS)
1767 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1768 else
1769 I915_WRITE_IMR(ring, ~0);
1770 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1771 }
1772 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1773}
1774
1775static bool
1776hsw_vebox_get_irq(struct intel_engine_cs *ring)
1777{
1778 struct drm_device *dev = ring->dev;
1779 struct drm_i915_private *dev_priv = dev->dev_private;
1780 unsigned long flags;
1781
1782 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1783 return false;
1784
1785 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1786 if (ring->irq_refcount++ == 0) {
1787 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1788 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
1789 }
1790 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1791
1792 return true;
1793}
1794
1795static void
1796hsw_vebox_put_irq(struct intel_engine_cs *ring)
1797{
1798 struct drm_device *dev = ring->dev;
1799 struct drm_i915_private *dev_priv = dev->dev_private;
1800 unsigned long flags;
1801
1802 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1803 if (--ring->irq_refcount == 0) {
1804 I915_WRITE_IMR(ring, ~0);
1805 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
1806 }
1807 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1808}
1809
1810static bool
1811gen8_ring_get_irq(struct intel_engine_cs *ring)
1812{
1813 struct drm_device *dev = ring->dev;
1814 struct drm_i915_private *dev_priv = dev->dev_private;
1815 unsigned long flags;
1816
1817 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1818 return false;
1819
1820 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1821 if (ring->irq_refcount++ == 0) {
1822 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1823 I915_WRITE_IMR(ring,
1824 ~(ring->irq_enable_mask |
1825 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1826 } else {
1827 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1828 }
1829 POSTING_READ(RING_IMR(ring->mmio_base));
1830 }
1831 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1832
1833 return true;
1834}
1835
1836static void
1837gen8_ring_put_irq(struct intel_engine_cs *ring)
1838{
1839 struct drm_device *dev = ring->dev;
1840 struct drm_i915_private *dev_priv = dev->dev_private;
1841 unsigned long flags;
1842
1843 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1844 if (--ring->irq_refcount == 0) {
1845 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1846 I915_WRITE_IMR(ring,
1847 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1848 } else {
1849 I915_WRITE_IMR(ring, ~0);
1850 }
1851 POSTING_READ(RING_IMR(ring->mmio_base));
1852 }
1853 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1854}
1855
1856static int
1857i965_dispatch_execbuffer(struct drm_i915_gem_request *req,
1858 u64 offset, u32 length,
1859 unsigned dispatch_flags)
1860{
1861 struct intel_engine_cs *ring = req->ring;
1862 int ret;
1863
1864 ret = intel_ring_begin(req, 2);
1865 if (ret)
1866 return ret;
1867
1868 intel_ring_emit(ring,
1869 MI_BATCH_BUFFER_START |
1870 MI_BATCH_GTT |
1871 (dispatch_flags & I915_DISPATCH_SECURE ?
1872 0 : MI_BATCH_NON_SECURE_I965));
1873 intel_ring_emit(ring, offset);
1874 intel_ring_advance(ring);
1875
1876 return 0;
1877}
1878
1879/* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1880#define I830_BATCH_LIMIT (256*1024)
1881#define I830_TLB_ENTRIES (2)
1882#define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1883static int
1884i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
1885 u64 offset, u32 len,
1886 unsigned dispatch_flags)
1887{
1888 struct intel_engine_cs *ring = req->ring;
1889 u32 cs_offset = ring->scratch.gtt_offset;
1890 int ret;
1891
1892 ret = intel_ring_begin(req, 6);
1893 if (ret)
1894 return ret;
1895
1896 /* Evict the invalid PTE TLBs */
1897 intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1898 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1899 intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1900 intel_ring_emit(ring, cs_offset);
1901 intel_ring_emit(ring, 0xdeadbeef);
1902 intel_ring_emit(ring, MI_NOOP);
1903 intel_ring_advance(ring);
1904
1905 if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
1906 if (len > I830_BATCH_LIMIT)
1907 return -ENOSPC;
1908
1909 ret = intel_ring_begin(req, 6 + 2);
1910 if (ret)
1911 return ret;
1912
1913 /* Blit the batch (which has now all relocs applied) to the
1914 * stable batch scratch bo area (so that the CS never
1915 * stumbles over its tlb invalidation bug) ...
1916 */
1917 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1918 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1919 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
1920 intel_ring_emit(ring, cs_offset);
1921 intel_ring_emit(ring, 4096);
1922 intel_ring_emit(ring, offset);
1923
1924 intel_ring_emit(ring, MI_FLUSH);
1925 intel_ring_emit(ring, MI_NOOP);
1926 intel_ring_advance(ring);
1927
1928 /* ... and execute it. */
1929 offset = cs_offset;
1930 }
1931
1932 ret = intel_ring_begin(req, 2);
1933 if (ret)
1934 return ret;
1935
1936 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1937 intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1938 0 : MI_BATCH_NON_SECURE));
1939 intel_ring_advance(ring);
1940
1941 return 0;
1942}
1943
1944static int
1945i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
1946 u64 offset, u32 len,
1947 unsigned dispatch_flags)
1948{
1949 struct intel_engine_cs *ring = req->ring;
1950 int ret;
1951
1952 ret = intel_ring_begin(req, 2);
1953 if (ret)
1954 return ret;
1955
1956 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1957 intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1958 0 : MI_BATCH_NON_SECURE));
1959 intel_ring_advance(ring);
1960
1961 return 0;
1962}
1963
1964static void cleanup_phys_status_page(struct intel_engine_cs *ring)
1965{
1966 struct drm_i915_private *dev_priv = to_i915(ring->dev);
1967
1968 if (!dev_priv->status_page_dmah)
1969 return;
1970
1971 drm_pci_free(ring->dev, dev_priv->status_page_dmah);
1972 ring->status_page.page_addr = NULL;
1973}
1974
1975static void cleanup_status_page(struct intel_engine_cs *ring)
1976{
1977 struct drm_i915_gem_object *obj;
1978
1979 obj = ring->status_page.obj;
1980 if (obj == NULL)
1981 return;
1982
1983 kunmap(sg_page(obj->pages->sgl));
1984 i915_gem_object_ggtt_unpin(obj);
1985 drm_gem_object_unreference(&obj->base);
1986 ring->status_page.obj = NULL;
1987}
1988
1989static int init_status_page(struct intel_engine_cs *ring)
1990{
1991 struct drm_i915_gem_object *obj = ring->status_page.obj;
1992
1993 if (obj == NULL) {
1994 unsigned flags;
1995 int ret;
1996
1997 obj = i915_gem_alloc_object(ring->dev, 4096);
1998 if (obj == NULL) {
1999 DRM_ERROR("Failed to allocate status page\n");
2000 return -ENOMEM;
2001 }
2002
2003 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2004 if (ret)
2005 goto err_unref;
2006
2007 flags = 0;
2008 if (!HAS_LLC(ring->dev))
2009 /* On g33, we cannot place HWS above 256MiB, so
2010 * restrict its pinning to the low mappable arena.
2011 * Though this restriction is not documented for
2012 * gen4, gen5, or byt, they also behave similarly
2013 * and hang if the HWS is placed at the top of the
2014 * GTT. To generalise, it appears that all !llc
2015 * platforms have issues with us placing the HWS
2016 * above the mappable region (even though we never
2017 * actualy map it).
2018 */
2019 flags |= PIN_MAPPABLE;
2020 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
2021 if (ret) {
2022err_unref:
2023 drm_gem_object_unreference(&obj->base);
2024 return ret;
2025 }
2026
2027 ring->status_page.obj = obj;
2028 }
2029
2030 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
2031 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
2032 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
2033
2034 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
2035 ring->name, ring->status_page.gfx_addr);
2036
2037 return 0;
2038}
2039
2040static int init_phys_status_page(struct intel_engine_cs *ring)
2041{
2042 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2043
2044 if (!dev_priv->status_page_dmah) {
2045 dev_priv->status_page_dmah =
2046 drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
2047 if (!dev_priv->status_page_dmah)
2048 return -ENOMEM;
2049 }
2050
2051 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
2052 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
2053
2054 return 0;
2055}
2056
2057void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2058{
2059 if (HAS_LLC(ringbuf->obj->base.dev) && !ringbuf->obj->stolen)
2060 vunmap(ringbuf->virtual_start);
2061 else
2062 iounmap(ringbuf->virtual_start);
2063 ringbuf->virtual_start = NULL;
2064 ringbuf->vma = NULL;
2065 i915_gem_object_ggtt_unpin(ringbuf->obj);
2066}
2067
2068static u32 *vmap_obj(struct drm_i915_gem_object *obj)
2069{
2070 struct sg_page_iter sg_iter;
2071 struct page **pages;
2072 void *addr;
2073 int i;
2074
2075 pages = drm_malloc_ab(obj->base.size >> PAGE_SHIFT, sizeof(*pages));
2076 if (pages == NULL)
2077 return NULL;
2078
2079 i = 0;
2080 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0)
2081 pages[i++] = sg_page_iter_page(&sg_iter);
2082
2083 addr = vmap(pages, i, 0, PAGE_KERNEL);
2084 drm_free_large(pages);
2085
2086 return addr;
2087}
2088
2089int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
2090 struct intel_ringbuffer *ringbuf)
2091{
2092 struct drm_i915_private *dev_priv = to_i915(dev);
2093 struct drm_i915_gem_object *obj = ringbuf->obj;
2094 /* Ring wraparound at offset 0 sometimes hangs. No idea why. */
2095 unsigned flags = PIN_OFFSET_BIAS | 4096;
2096 int ret;
2097
2098 if (HAS_LLC(dev_priv) && !obj->stolen) {
2099 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, flags);
2100 if (ret)
2101 return ret;
2102
2103 ret = i915_gem_object_set_to_cpu_domain(obj, true);
2104 if (ret) {
2105 i915_gem_object_ggtt_unpin(obj);
2106 return ret;
2107 }
2108
2109 ringbuf->virtual_start = vmap_obj(obj);
2110 if (ringbuf->virtual_start == NULL) {
2111 i915_gem_object_ggtt_unpin(obj);
2112 return -ENOMEM;
2113 }
2114 } else {
2115 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE,
2116 flags | PIN_MAPPABLE);
2117 if (ret)
2118 return ret;
2119
2120 ret = i915_gem_object_set_to_gtt_domain(obj, true);
2121 if (ret) {
2122 i915_gem_object_ggtt_unpin(obj);
2123 return ret;
2124 }
2125
2126 /* Access through the GTT requires the device to be awake. */
2127 assert_rpm_wakelock_held(dev_priv);
2128
2129 ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
2130 i915_gem_obj_ggtt_offset(obj), ringbuf->size);
2131 if (ringbuf->virtual_start == NULL) {
2132 i915_gem_object_ggtt_unpin(obj);
2133 return -EINVAL;
2134 }
2135 }
2136
2137 ringbuf->vma = i915_gem_obj_to_ggtt(obj);
2138
2139 return 0;
2140}
2141
2142static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2143{
2144 drm_gem_object_unreference(&ringbuf->obj->base);
2145 ringbuf->obj = NULL;
2146}
2147
2148static int intel_alloc_ringbuffer_obj(struct drm_device *dev,
2149 struct intel_ringbuffer *ringbuf)
2150{
2151 struct drm_i915_gem_object *obj;
2152
2153 obj = NULL;
2154 if (!HAS_LLC(dev))
2155 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
2156 if (obj == NULL)
2157 obj = i915_gem_alloc_object(dev, ringbuf->size);
2158 if (obj == NULL)
2159 return -ENOMEM;
2160
2161 /* mark ring buffers as read-only from GPU side by default */
2162 obj->gt_ro = 1;
2163
2164 ringbuf->obj = obj;
2165
2166 return 0;
2167}
2168
2169struct intel_ringbuffer *
2170intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size)
2171{
2172 struct intel_ringbuffer *ring;
2173 int ret;
2174
2175 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
2176 if (ring == NULL) {
2177 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
2178 engine->name);
2179 return ERR_PTR(-ENOMEM);
2180 }
2181
2182 ring->ring = engine;
2183 list_add(&ring->link, &engine->buffers);
2184
2185 ring->size = size;
2186 /* Workaround an erratum on the i830 which causes a hang if
2187 * the TAIL pointer points to within the last 2 cachelines
2188 * of the buffer.
2189 */
2190 ring->effective_size = size;
2191 if (IS_I830(engine->dev) || IS_845G(engine->dev))
2192 ring->effective_size -= 2 * CACHELINE_BYTES;
2193
2194 ring->last_retired_head = -1;
2195 intel_ring_update_space(ring);
2196
2197 ret = intel_alloc_ringbuffer_obj(engine->dev, ring);
2198 if (ret) {
2199 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n",
2200 engine->name, ret);
2201 list_del(&ring->link);
2202 kfree(ring);
2203 return ERR_PTR(ret);
2204 }
2205
2206 return ring;
2207}
2208
2209void
2210intel_ringbuffer_free(struct intel_ringbuffer *ring)
2211{
2212 intel_destroy_ringbuffer_obj(ring);
2213 list_del(&ring->link);
2214 kfree(ring);
2215}
2216
2217static int intel_init_ring_buffer(struct drm_device *dev,
2218 struct intel_engine_cs *ring)
2219{
2220 struct intel_ringbuffer *ringbuf;
2221 int ret;
2222
2223 WARN_ON(ring->buffer);
2224
2225 ring->dev = dev;
2226 INIT_LIST_HEAD(&ring->active_list);
2227 INIT_LIST_HEAD(&ring->request_list);
2228 INIT_LIST_HEAD(&ring->execlist_queue);
2229 INIT_LIST_HEAD(&ring->buffers);
2230 i915_gem_batch_pool_init(dev, &ring->batch_pool);
2231 memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
2232
2233 init_waitqueue_head(&ring->irq_queue);
2234
2235 ringbuf = intel_engine_create_ringbuffer(ring, 32 * PAGE_SIZE);
2236 if (IS_ERR(ringbuf)) {
2237 ret = PTR_ERR(ringbuf);
2238 goto error;
2239 }
2240 ring->buffer = ringbuf;
2241
2242 if (I915_NEED_GFX_HWS(dev)) {
2243 ret = init_status_page(ring);
2244 if (ret)
2245 goto error;
2246 } else {
2247 WARN_ON(ring->id != RCS);
2248 ret = init_phys_status_page(ring);
2249 if (ret)
2250 goto error;
2251 }
2252
2253 ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
2254 if (ret) {
2255 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2256 ring->name, ret);
2257 intel_destroy_ringbuffer_obj(ringbuf);
2258 goto error;
2259 }
2260
2261 ret = i915_cmd_parser_init_ring(ring);
2262 if (ret)
2263 goto error;
2264
2265 return 0;
2266
2267error:
2268 intel_cleanup_ring_buffer(ring);
2269 return ret;
2270}
2271
2272void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
2273{
2274 struct drm_i915_private *dev_priv;
2275
2276 if (!intel_ring_initialized(ring))
2277 return;
2278
2279 dev_priv = to_i915(ring->dev);
2280
2281 if (ring->buffer) {
2282 intel_stop_ring_buffer(ring);
2283 WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
2284
2285 intel_unpin_ringbuffer_obj(ring->buffer);
2286 intel_ringbuffer_free(ring->buffer);
2287 ring->buffer = NULL;
2288 }
2289
2290 if (ring->cleanup)
2291 ring->cleanup(ring);
2292
2293 if (I915_NEED_GFX_HWS(ring->dev)) {
2294 cleanup_status_page(ring);
2295 } else {
2296 WARN_ON(ring->id != RCS);
2297 cleanup_phys_status_page(ring);
2298 }
2299
2300 i915_cmd_parser_fini_ring(ring);
2301 i915_gem_batch_pool_fini(&ring->batch_pool);
2302 ring->dev = NULL;
2303}
2304
2305static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
2306{
2307 struct intel_ringbuffer *ringbuf = ring->buffer;
2308 struct drm_i915_gem_request *request;
2309 unsigned space;
2310 int ret;
2311
2312 if (intel_ring_space(ringbuf) >= n)
2313 return 0;
2314
2315 /* The whole point of reserving space is to not wait! */
2316 WARN_ON(ringbuf->reserved_in_use);
2317
2318 list_for_each_entry(request, &ring->request_list, list) {
2319 space = __intel_ring_space(request->postfix, ringbuf->tail,
2320 ringbuf->size);
2321 if (space >= n)
2322 break;
2323 }
2324
2325 if (WARN_ON(&request->list == &ring->request_list))
2326 return -ENOSPC;
2327
2328 ret = i915_wait_request(request);
2329 if (ret)
2330 return ret;
2331
2332 ringbuf->space = space;
2333 return 0;
2334}
2335
2336static void __wrap_ring_buffer(struct intel_ringbuffer *ringbuf)
2337{
2338 uint32_t __iomem *virt;
2339 int rem = ringbuf->size - ringbuf->tail;
2340
2341 virt = ringbuf->virtual_start + ringbuf->tail;
2342 rem /= 4;
2343 while (rem--)
2344 iowrite32(MI_NOOP, virt++);
2345
2346 ringbuf->tail = 0;
2347 intel_ring_update_space(ringbuf);
2348}
2349
2350int intel_ring_idle(struct intel_engine_cs *ring)
2351{
2352 struct drm_i915_gem_request *req;
2353
2354 /* Wait upon the last request to be completed */
2355 if (list_empty(&ring->request_list))
2356 return 0;
2357
2358 req = list_entry(ring->request_list.prev,
2359 struct drm_i915_gem_request,
2360 list);
2361
2362 /* Make sure we do not trigger any retires */
2363 return __i915_wait_request(req,
2364 atomic_read(&to_i915(ring->dev)->gpu_error.reset_counter),
2365 to_i915(ring->dev)->mm.interruptible,
2366 NULL, NULL);
2367}
2368
2369int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
2370{
2371 request->ringbuf = request->ring->buffer;
2372 return 0;
2373}
2374
2375int intel_ring_reserve_space(struct drm_i915_gem_request *request)
2376{
2377 /*
2378 * The first call merely notes the reserve request and is common for
2379 * all back ends. The subsequent localised _begin() call actually
2380 * ensures that the reservation is available. Without the begin, if
2381 * the request creator immediately submitted the request without
2382 * adding any commands to it then there might not actually be
2383 * sufficient room for the submission commands.
2384 */
2385 intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST);
2386
2387 return intel_ring_begin(request, 0);
2388}
2389
2390void intel_ring_reserved_space_reserve(struct intel_ringbuffer *ringbuf, int size)
2391{
2392 WARN_ON(ringbuf->reserved_size);
2393 WARN_ON(ringbuf->reserved_in_use);
2394
2395 ringbuf->reserved_size = size;
2396}
2397
2398void intel_ring_reserved_space_cancel(struct intel_ringbuffer *ringbuf)
2399{
2400 WARN_ON(ringbuf->reserved_in_use);
2401
2402 ringbuf->reserved_size = 0;
2403 ringbuf->reserved_in_use = false;
2404}
2405
2406void intel_ring_reserved_space_use(struct intel_ringbuffer *ringbuf)
2407{
2408 WARN_ON(ringbuf->reserved_in_use);
2409
2410 ringbuf->reserved_in_use = true;
2411 ringbuf->reserved_tail = ringbuf->tail;
2412}
2413
2414void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf)
2415{
2416 WARN_ON(!ringbuf->reserved_in_use);
2417 if (ringbuf->tail > ringbuf->reserved_tail) {
2418 WARN(ringbuf->tail > ringbuf->reserved_tail + ringbuf->reserved_size,
2419 "request reserved size too small: %d vs %d!\n",
2420 ringbuf->tail - ringbuf->reserved_tail, ringbuf->reserved_size);
2421 } else {
2422 /*
2423 * The ring was wrapped while the reserved space was in use.
2424 * That means that some unknown amount of the ring tail was
2425 * no-op filled and skipped. Thus simply adding the ring size
2426 * to the tail and doing the above space check will not work.
2427 * Rather than attempt to track how much tail was skipped,
2428 * it is much simpler to say that also skipping the sanity
2429 * check every once in a while is not a big issue.
2430 */
2431 }
2432
2433 ringbuf->reserved_size = 0;
2434 ringbuf->reserved_in_use = false;
2435}
2436
2437static int __intel_ring_prepare(struct intel_engine_cs *ring, int bytes)
2438{
2439 struct intel_ringbuffer *ringbuf = ring->buffer;
2440 int remain_usable = ringbuf->effective_size - ringbuf->tail;
2441 int remain_actual = ringbuf->size - ringbuf->tail;
2442 int ret, total_bytes, wait_bytes = 0;
2443 bool need_wrap = false;
2444
2445 if (ringbuf->reserved_in_use)
2446 total_bytes = bytes;
2447 else
2448 total_bytes = bytes + ringbuf->reserved_size;
2449
2450 if (unlikely(bytes > remain_usable)) {
2451 /*
2452 * Not enough space for the basic request. So need to flush
2453 * out the remainder and then wait for base + reserved.
2454 */
2455 wait_bytes = remain_actual + total_bytes;
2456 need_wrap = true;
2457 } else {
2458 if (unlikely(total_bytes > remain_usable)) {
2459 /*
2460 * The base request will fit but the reserved space
2461 * falls off the end. So don't need an immediate wrap
2462 * and only need to effectively wait for the reserved
2463 * size space from the start of ringbuffer.
2464 */
2465 wait_bytes = remain_actual + ringbuf->reserved_size;
2466 } else if (total_bytes > ringbuf->space) {
2467 /* No wrapping required, just waiting. */
2468 wait_bytes = total_bytes;
2469 }
2470 }
2471
2472 if (wait_bytes) {
2473 ret = ring_wait_for_space(ring, wait_bytes);
2474 if (unlikely(ret))
2475 return ret;
2476
2477 if (need_wrap)
2478 __wrap_ring_buffer(ringbuf);
2479 }
2480
2481 return 0;
2482}
2483
2484int intel_ring_begin(struct drm_i915_gem_request *req,
2485 int num_dwords)
2486{
2487 struct intel_engine_cs *ring;
2488 struct drm_i915_private *dev_priv;
2489 int ret;
2490
2491 WARN_ON(req == NULL);
2492 ring = req->ring;
2493 dev_priv = ring->dev->dev_private;
2494
2495 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2496 dev_priv->mm.interruptible);
2497 if (ret)
2498 return ret;
2499
2500 ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2501 if (ret)
2502 return ret;
2503
2504 ring->buffer->space -= num_dwords * sizeof(uint32_t);
2505 return 0;
2506}
2507
2508/* Align the ring tail to a cacheline boundary */
2509int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
2510{
2511 struct intel_engine_cs *ring = req->ring;
2512 int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
2513 int ret;
2514
2515 if (num_dwords == 0)
2516 return 0;
2517
2518 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
2519 ret = intel_ring_begin(req, num_dwords);
2520 if (ret)
2521 return ret;
2522
2523 while (num_dwords--)
2524 intel_ring_emit(ring, MI_NOOP);
2525
2526 intel_ring_advance(ring);
2527
2528 return 0;
2529}
2530
2531void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
2532{
2533 struct drm_device *dev = ring->dev;
2534 struct drm_i915_private *dev_priv = dev->dev_private;
2535
2536 if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
2537 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2538 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
2539 if (HAS_VEBOX(dev))
2540 I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
2541 }
2542
2543 ring->set_seqno(ring, seqno);
2544 ring->hangcheck.seqno = seqno;
2545}
2546
2547static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
2548 u32 value)
2549{
2550 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2551
2552 /* Every tail move must follow the sequence below */
2553
2554 /* Disable notification that the ring is IDLE. The GT
2555 * will then assume that it is busy and bring it out of rc6.
2556 */
2557 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2558 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2559
2560 /* Clear the context id. Here be magic! */
2561 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
2562
2563 /* Wait for the ring not to be idle, i.e. for it to wake up. */
2564 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
2565 GEN6_BSD_SLEEP_INDICATOR) == 0,
2566 50))
2567 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2568
2569 /* Now that the ring is fully powered up, update the tail */
2570 I915_WRITE_TAIL(ring, value);
2571 POSTING_READ(RING_TAIL(ring->mmio_base));
2572
2573 /* Let the ring send IDLE messages to the GT again,
2574 * and so let it sleep to conserve power when idle.
2575 */
2576 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2577 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2578}
2579
2580static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
2581 u32 invalidate, u32 flush)
2582{
2583 struct intel_engine_cs *ring = req->ring;
2584 uint32_t cmd;
2585 int ret;
2586
2587 ret = intel_ring_begin(req, 4);
2588 if (ret)
2589 return ret;
2590
2591 cmd = MI_FLUSH_DW;
2592 if (INTEL_INFO(ring->dev)->gen >= 8)
2593 cmd += 1;
2594
2595 /* We always require a command barrier so that subsequent
2596 * commands, such as breadcrumb interrupts, are strictly ordered
2597 * wrt the contents of the write cache being flushed to memory
2598 * (and thus being coherent from the CPU).
2599 */
2600 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2601
2602 /*
2603 * Bspec vol 1c.5 - video engine command streamer:
2604 * "If ENABLED, all TLBs will be invalidated once the flush
2605 * operation is complete. This bit is only valid when the
2606 * Post-Sync Operation field is a value of 1h or 3h."
2607 */
2608 if (invalidate & I915_GEM_GPU_DOMAINS)
2609 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2610
2611 intel_ring_emit(ring, cmd);
2612 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2613 if (INTEL_INFO(ring->dev)->gen >= 8) {
2614 intel_ring_emit(ring, 0); /* upper addr */
2615 intel_ring_emit(ring, 0); /* value */
2616 } else {
2617 intel_ring_emit(ring, 0);
2618 intel_ring_emit(ring, MI_NOOP);
2619 }
2620 intel_ring_advance(ring);
2621 return 0;
2622}
2623
2624static int
2625gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2626 u64 offset, u32 len,
2627 unsigned dispatch_flags)
2628{
2629 struct intel_engine_cs *ring = req->ring;
2630 bool ppgtt = USES_PPGTT(ring->dev) &&
2631 !(dispatch_flags & I915_DISPATCH_SECURE);
2632 int ret;
2633
2634 ret = intel_ring_begin(req, 4);
2635 if (ret)
2636 return ret;
2637
2638 /* FIXME(BDW): Address space and security selectors. */
2639 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) |
2640 (dispatch_flags & I915_DISPATCH_RS ?
2641 MI_BATCH_RESOURCE_STREAMER : 0));
2642 intel_ring_emit(ring, lower_32_bits(offset));
2643 intel_ring_emit(ring, upper_32_bits(offset));
2644 intel_ring_emit(ring, MI_NOOP);
2645 intel_ring_advance(ring);
2646
2647 return 0;
2648}
2649
2650static int
2651hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2652 u64 offset, u32 len,
2653 unsigned dispatch_flags)
2654{
2655 struct intel_engine_cs *ring = req->ring;
2656 int ret;
2657
2658 ret = intel_ring_begin(req, 2);
2659 if (ret)
2660 return ret;
2661
2662 intel_ring_emit(ring,
2663 MI_BATCH_BUFFER_START |
2664 (dispatch_flags & I915_DISPATCH_SECURE ?
2665 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
2666 (dispatch_flags & I915_DISPATCH_RS ?
2667 MI_BATCH_RESOURCE_STREAMER : 0));
2668 /* bit0-7 is the length on GEN6+ */
2669 intel_ring_emit(ring, offset);
2670 intel_ring_advance(ring);
2671
2672 return 0;
2673}
2674
2675static int
2676gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2677 u64 offset, u32 len,
2678 unsigned dispatch_flags)
2679{
2680 struct intel_engine_cs *ring = req->ring;
2681 int ret;
2682
2683 ret = intel_ring_begin(req, 2);
2684 if (ret)
2685 return ret;
2686
2687 intel_ring_emit(ring,
2688 MI_BATCH_BUFFER_START |
2689 (dispatch_flags & I915_DISPATCH_SECURE ?
2690 0 : MI_BATCH_NON_SECURE_I965));
2691 /* bit0-7 is the length on GEN6+ */
2692 intel_ring_emit(ring, offset);
2693 intel_ring_advance(ring);
2694
2695 return 0;
2696}
2697
2698/* Blitter support (SandyBridge+) */
2699
2700static int gen6_ring_flush(struct drm_i915_gem_request *req,
2701 u32 invalidate, u32 flush)
2702{
2703 struct intel_engine_cs *ring = req->ring;
2704 struct drm_device *dev = ring->dev;
2705 uint32_t cmd;
2706 int ret;
2707
2708 ret = intel_ring_begin(req, 4);
2709 if (ret)
2710 return ret;
2711
2712 cmd = MI_FLUSH_DW;
2713 if (INTEL_INFO(dev)->gen >= 8)
2714 cmd += 1;
2715
2716 /* We always require a command barrier so that subsequent
2717 * commands, such as breadcrumb interrupts, are strictly ordered
2718 * wrt the contents of the write cache being flushed to memory
2719 * (and thus being coherent from the CPU).
2720 */
2721 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2722
2723 /*
2724 * Bspec vol 1c.3 - blitter engine command streamer:
2725 * "If ENABLED, all TLBs will be invalidated once the flush
2726 * operation is complete. This bit is only valid when the
2727 * Post-Sync Operation field is a value of 1h or 3h."
2728 */
2729 if (invalidate & I915_GEM_DOMAIN_RENDER)
2730 cmd |= MI_INVALIDATE_TLB;
2731 intel_ring_emit(ring, cmd);
2732 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2733 if (INTEL_INFO(dev)->gen >= 8) {
2734 intel_ring_emit(ring, 0); /* upper addr */
2735 intel_ring_emit(ring, 0); /* value */
2736 } else {
2737 intel_ring_emit(ring, 0);
2738 intel_ring_emit(ring, MI_NOOP);
2739 }
2740 intel_ring_advance(ring);
2741
2742 return 0;
2743}
2744
2745int intel_init_render_ring_buffer(struct drm_device *dev)
2746{
2747 struct drm_i915_private *dev_priv = dev->dev_private;
2748 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
2749 struct drm_i915_gem_object *obj;
2750 int ret;
2751
2752 ring->name = "render ring";
2753 ring->id = RCS;
2754 ring->exec_id = I915_EXEC_RENDER;
2755 ring->mmio_base = RENDER_RING_BASE;
2756
2757 if (INTEL_INFO(dev)->gen >= 8) {
2758 if (i915_semaphore_is_enabled(dev)) {
2759 obj = i915_gem_alloc_object(dev, 4096);
2760 if (obj == NULL) {
2761 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2762 i915.semaphores = 0;
2763 } else {
2764 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2765 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2766 if (ret != 0) {
2767 drm_gem_object_unreference(&obj->base);
2768 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2769 i915.semaphores = 0;
2770 } else
2771 dev_priv->semaphore_obj = obj;
2772 }
2773 }
2774
2775 ring->init_context = intel_rcs_ctx_init;
2776 ring->add_request = gen6_add_request;
2777 ring->flush = gen8_render_ring_flush;
2778 ring->irq_get = gen8_ring_get_irq;
2779 ring->irq_put = gen8_ring_put_irq;
2780 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2781 ring->get_seqno = gen6_ring_get_seqno;
2782 ring->set_seqno = ring_set_seqno;
2783 if (i915_semaphore_is_enabled(dev)) {
2784 WARN_ON(!dev_priv->semaphore_obj);
2785 ring->semaphore.sync_to = gen8_ring_sync;
2786 ring->semaphore.signal = gen8_rcs_signal;
2787 GEN8_RING_SEMAPHORE_INIT;
2788 }
2789 } else if (INTEL_INFO(dev)->gen >= 6) {
2790 ring->init_context = intel_rcs_ctx_init;
2791 ring->add_request = gen6_add_request;
2792 ring->flush = gen7_render_ring_flush;
2793 if (INTEL_INFO(dev)->gen == 6)
2794 ring->flush = gen6_render_ring_flush;
2795 ring->irq_get = gen6_ring_get_irq;
2796 ring->irq_put = gen6_ring_put_irq;
2797 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2798 ring->get_seqno = gen6_ring_get_seqno;
2799 ring->set_seqno = ring_set_seqno;
2800 if (i915_semaphore_is_enabled(dev)) {
2801 ring->semaphore.sync_to = gen6_ring_sync;
2802 ring->semaphore.signal = gen6_signal;
2803 /*
2804 * The current semaphore is only applied on pre-gen8
2805 * platform. And there is no VCS2 ring on the pre-gen8
2806 * platform. So the semaphore between RCS and VCS2 is
2807 * initialized as INVALID. Gen8 will initialize the
2808 * sema between VCS2 and RCS later.
2809 */
2810 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2811 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2812 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2813 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2814 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2815 ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2816 ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2817 ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2818 ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2819 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2820 }
2821 } else if (IS_GEN5(dev)) {
2822 ring->add_request = pc_render_add_request;
2823 ring->flush = gen4_render_ring_flush;
2824 ring->get_seqno = pc_render_get_seqno;
2825 ring->set_seqno = pc_render_set_seqno;
2826 ring->irq_get = gen5_ring_get_irq;
2827 ring->irq_put = gen5_ring_put_irq;
2828 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2829 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
2830 } else {
2831 ring->add_request = i9xx_add_request;
2832 if (INTEL_INFO(dev)->gen < 4)
2833 ring->flush = gen2_render_ring_flush;
2834 else
2835 ring->flush = gen4_render_ring_flush;
2836 ring->get_seqno = ring_get_seqno;
2837 ring->set_seqno = ring_set_seqno;
2838 if (IS_GEN2(dev)) {
2839 ring->irq_get = i8xx_ring_get_irq;
2840 ring->irq_put = i8xx_ring_put_irq;
2841 } else {
2842 ring->irq_get = i9xx_ring_get_irq;
2843 ring->irq_put = i9xx_ring_put_irq;
2844 }
2845 ring->irq_enable_mask = I915_USER_INTERRUPT;
2846 }
2847 ring->write_tail = ring_write_tail;
2848
2849 if (IS_HASWELL(dev))
2850 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
2851 else if (IS_GEN8(dev))
2852 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2853 else if (INTEL_INFO(dev)->gen >= 6)
2854 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2855 else if (INTEL_INFO(dev)->gen >= 4)
2856 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2857 else if (IS_I830(dev) || IS_845G(dev))
2858 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2859 else
2860 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2861 ring->init_hw = init_render_ring;
2862 ring->cleanup = render_ring_cleanup;
2863
2864 /* Workaround batchbuffer to combat CS tlb bug. */
2865 if (HAS_BROKEN_CS_TLB(dev)) {
2866 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
2867 if (obj == NULL) {
2868 DRM_ERROR("Failed to allocate batch bo\n");
2869 return -ENOMEM;
2870 }
2871
2872 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
2873 if (ret != 0) {
2874 drm_gem_object_unreference(&obj->base);
2875 DRM_ERROR("Failed to ping batch bo\n");
2876 return ret;
2877 }
2878
2879 ring->scratch.obj = obj;
2880 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2881 }
2882
2883 ret = intel_init_ring_buffer(dev, ring);
2884 if (ret)
2885 return ret;
2886
2887 if (INTEL_INFO(dev)->gen >= 5) {
2888 ret = intel_init_pipe_control(ring);
2889 if (ret)
2890 return ret;
2891 }
2892
2893 return 0;
2894}
2895
2896int intel_init_bsd_ring_buffer(struct drm_device *dev)
2897{
2898 struct drm_i915_private *dev_priv = dev->dev_private;
2899 struct intel_engine_cs *ring = &dev_priv->ring[VCS];
2900
2901 ring->name = "bsd ring";
2902 ring->id = VCS;
2903 ring->exec_id = I915_EXEC_BSD;
2904
2905 ring->write_tail = ring_write_tail;
2906 if (INTEL_INFO(dev)->gen >= 6) {
2907 ring->mmio_base = GEN6_BSD_RING_BASE;
2908 /* gen6 bsd needs a special wa for tail updates */
2909 if (IS_GEN6(dev))
2910 ring->write_tail = gen6_bsd_ring_write_tail;
2911 ring->flush = gen6_bsd_ring_flush;
2912 ring->add_request = gen6_add_request;
2913 ring->get_seqno = gen6_ring_get_seqno;
2914 ring->set_seqno = ring_set_seqno;
2915 if (INTEL_INFO(dev)->gen >= 8) {
2916 ring->irq_enable_mask =
2917 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2918 ring->irq_get = gen8_ring_get_irq;
2919 ring->irq_put = gen8_ring_put_irq;
2920 ring->dispatch_execbuffer =
2921 gen8_ring_dispatch_execbuffer;
2922 if (i915_semaphore_is_enabled(dev)) {
2923 ring->semaphore.sync_to = gen8_ring_sync;
2924 ring->semaphore.signal = gen8_xcs_signal;
2925 GEN8_RING_SEMAPHORE_INIT;
2926 }
2927 } else {
2928 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2929 ring->irq_get = gen6_ring_get_irq;
2930 ring->irq_put = gen6_ring_put_irq;
2931 ring->dispatch_execbuffer =
2932 gen6_ring_dispatch_execbuffer;
2933 if (i915_semaphore_is_enabled(dev)) {
2934 ring->semaphore.sync_to = gen6_ring_sync;
2935 ring->semaphore.signal = gen6_signal;
2936 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2937 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2938 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2939 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2940 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2941 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2942 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2943 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2944 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2945 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2946 }
2947 }
2948 } else {
2949 ring->mmio_base = BSD_RING_BASE;
2950 ring->flush = bsd_ring_flush;
2951 ring->add_request = i9xx_add_request;
2952 ring->get_seqno = ring_get_seqno;
2953 ring->set_seqno = ring_set_seqno;
2954 if (IS_GEN5(dev)) {
2955 ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2956 ring->irq_get = gen5_ring_get_irq;
2957 ring->irq_put = gen5_ring_put_irq;
2958 } else {
2959 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2960 ring->irq_get = i9xx_ring_get_irq;
2961 ring->irq_put = i9xx_ring_put_irq;
2962 }
2963 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2964 }
2965 ring->init_hw = init_ring_common;
2966
2967 return intel_init_ring_buffer(dev, ring);
2968}
2969
2970/**
2971 * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
2972 */
2973int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2974{
2975 struct drm_i915_private *dev_priv = dev->dev_private;
2976 struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
2977
2978 ring->name = "bsd2 ring";
2979 ring->id = VCS2;
2980 ring->exec_id = I915_EXEC_BSD;
2981
2982 ring->write_tail = ring_write_tail;
2983 ring->mmio_base = GEN8_BSD2_RING_BASE;
2984 ring->flush = gen6_bsd_ring_flush;
2985 ring->add_request = gen6_add_request;
2986 ring->get_seqno = gen6_ring_get_seqno;
2987 ring->set_seqno = ring_set_seqno;
2988 ring->irq_enable_mask =
2989 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2990 ring->irq_get = gen8_ring_get_irq;
2991 ring->irq_put = gen8_ring_put_irq;
2992 ring->dispatch_execbuffer =
2993 gen8_ring_dispatch_execbuffer;
2994 if (i915_semaphore_is_enabled(dev)) {
2995 ring->semaphore.sync_to = gen8_ring_sync;
2996 ring->semaphore.signal = gen8_xcs_signal;
2997 GEN8_RING_SEMAPHORE_INIT;
2998 }
2999 ring->init_hw = init_ring_common;
3000
3001 return intel_init_ring_buffer(dev, ring);
3002}
3003
3004int intel_init_blt_ring_buffer(struct drm_device *dev)
3005{
3006 struct drm_i915_private *dev_priv = dev->dev_private;
3007 struct intel_engine_cs *ring = &dev_priv->ring[BCS];
3008
3009 ring->name = "blitter ring";
3010 ring->id = BCS;
3011 ring->exec_id = I915_EXEC_BLT;
3012
3013 ring->mmio_base = BLT_RING_BASE;
3014 ring->write_tail = ring_write_tail;
3015 ring->flush = gen6_ring_flush;
3016 ring->add_request = gen6_add_request;
3017 ring->get_seqno = gen6_ring_get_seqno;
3018 ring->set_seqno = ring_set_seqno;
3019 if (INTEL_INFO(dev)->gen >= 8) {
3020 ring->irq_enable_mask =
3021 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
3022 ring->irq_get = gen8_ring_get_irq;
3023 ring->irq_put = gen8_ring_put_irq;
3024 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
3025 if (i915_semaphore_is_enabled(dev)) {
3026 ring->semaphore.sync_to = gen8_ring_sync;
3027 ring->semaphore.signal = gen8_xcs_signal;
3028 GEN8_RING_SEMAPHORE_INIT;
3029 }
3030 } else {
3031 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
3032 ring->irq_get = gen6_ring_get_irq;
3033 ring->irq_put = gen6_ring_put_irq;
3034 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
3035 if (i915_semaphore_is_enabled(dev)) {
3036 ring->semaphore.signal = gen6_signal;
3037 ring->semaphore.sync_to = gen6_ring_sync;
3038 /*
3039 * The current semaphore is only applied on pre-gen8
3040 * platform. And there is no VCS2 ring on the pre-gen8
3041 * platform. So the semaphore between BCS and VCS2 is
3042 * initialized as INVALID. Gen8 will initialize the
3043 * sema between BCS and VCS2 later.
3044 */
3045 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
3046 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
3047 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
3048 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
3049 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3050 ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
3051 ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
3052 ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
3053 ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
3054 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
3055 }
3056 }
3057 ring->init_hw = init_ring_common;
3058
3059 return intel_init_ring_buffer(dev, ring);
3060}
3061
3062int intel_init_vebox_ring_buffer(struct drm_device *dev)
3063{
3064 struct drm_i915_private *dev_priv = dev->dev_private;
3065 struct intel_engine_cs *ring = &dev_priv->ring[VECS];
3066
3067 ring->name = "video enhancement ring";
3068 ring->id = VECS;
3069 ring->exec_id = I915_EXEC_VEBOX;
3070
3071 ring->mmio_base = VEBOX_RING_BASE;
3072 ring->write_tail = ring_write_tail;
3073 ring->flush = gen6_ring_flush;
3074 ring->add_request = gen6_add_request;
3075 ring->get_seqno = gen6_ring_get_seqno;
3076 ring->set_seqno = ring_set_seqno;
3077
3078 if (INTEL_INFO(dev)->gen >= 8) {
3079 ring->irq_enable_mask =
3080 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
3081 ring->irq_get = gen8_ring_get_irq;
3082 ring->irq_put = gen8_ring_put_irq;
3083 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
3084 if (i915_semaphore_is_enabled(dev)) {
3085 ring->semaphore.sync_to = gen8_ring_sync;
3086 ring->semaphore.signal = gen8_xcs_signal;
3087 GEN8_RING_SEMAPHORE_INIT;
3088 }
3089 } else {
3090 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
3091 ring->irq_get = hsw_vebox_get_irq;
3092 ring->irq_put = hsw_vebox_put_irq;
3093 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
3094 if (i915_semaphore_is_enabled(dev)) {
3095 ring->semaphore.sync_to = gen6_ring_sync;
3096 ring->semaphore.signal = gen6_signal;
3097 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
3098 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
3099 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
3100 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
3101 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3102 ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
3103 ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
3104 ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
3105 ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
3106 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
3107 }
3108 }
3109 ring->init_hw = init_ring_common;
3110
3111 return intel_init_ring_buffer(dev, ring);
3112}
3113
3114int
3115intel_ring_flush_all_caches(struct drm_i915_gem_request *req)
3116{
3117 struct intel_engine_cs *ring = req->ring;
3118 int ret;
3119
3120 if (!ring->gpu_caches_dirty)
3121 return 0;
3122
3123 ret = ring->flush(req, 0, I915_GEM_GPU_DOMAINS);
3124 if (ret)
3125 return ret;
3126
3127 trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS);
3128
3129 ring->gpu_caches_dirty = false;
3130 return 0;
3131}
3132
3133int
3134intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
3135{
3136 struct intel_engine_cs *ring = req->ring;
3137 uint32_t flush_domains;
3138 int ret;
3139
3140 flush_domains = 0;
3141 if (ring->gpu_caches_dirty)
3142 flush_domains = I915_GEM_GPU_DOMAINS;
3143
3144 ret = ring->flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
3145 if (ret)
3146 return ret;
3147
3148 trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
3149
3150 ring->gpu_caches_dirty = false;
3151 return 0;
3152}
3153
3154void
3155intel_stop_ring_buffer(struct intel_engine_cs *ring)
3156{
3157 int ret;
3158
3159 if (!intel_ring_initialized(ring))
3160 return;
3161
3162 ret = intel_ring_idle(ring);
3163 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
3164 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
3165 ring->name, ret);
3166
3167 stop_ring(ring);
3168}
1/*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30#include <linux/log2.h>
31#include <drm/drmP.h>
32#include "i915_drv.h"
33#include <drm/i915_drm.h>
34#include "i915_trace.h"
35#include "intel_drv.h"
36
37/* Rough estimate of the typical request size, performing a flush,
38 * set-context and then emitting the batch.
39 */
40#define LEGACY_REQUEST_SIZE 200
41
42int __intel_ring_space(int head, int tail, int size)
43{
44 int space = head - tail;
45 if (space <= 0)
46 space += size;
47 return space - I915_RING_FREE_SPACE;
48}
49
50void intel_ring_update_space(struct intel_ring *ring)
51{
52 if (ring->last_retired_head != -1) {
53 ring->head = ring->last_retired_head;
54 ring->last_retired_head = -1;
55 }
56
57 ring->space = __intel_ring_space(ring->head & HEAD_ADDR,
58 ring->tail, ring->size);
59}
60
61static int
62gen2_render_ring_flush(struct drm_i915_gem_request *req, u32 mode)
63{
64 struct intel_ring *ring = req->ring;
65 u32 cmd;
66 int ret;
67
68 cmd = MI_FLUSH;
69
70 if (mode & EMIT_INVALIDATE)
71 cmd |= MI_READ_FLUSH;
72
73 ret = intel_ring_begin(req, 2);
74 if (ret)
75 return ret;
76
77 intel_ring_emit(ring, cmd);
78 intel_ring_emit(ring, MI_NOOP);
79 intel_ring_advance(ring);
80
81 return 0;
82}
83
84static int
85gen4_render_ring_flush(struct drm_i915_gem_request *req, u32 mode)
86{
87 struct intel_ring *ring = req->ring;
88 u32 cmd;
89 int ret;
90
91 /*
92 * read/write caches:
93 *
94 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
95 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
96 * also flushed at 2d versus 3d pipeline switches.
97 *
98 * read-only caches:
99 *
100 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
101 * MI_READ_FLUSH is set, and is always flushed on 965.
102 *
103 * I915_GEM_DOMAIN_COMMAND may not exist?
104 *
105 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
106 * invalidated when MI_EXE_FLUSH is set.
107 *
108 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
109 * invalidated with every MI_FLUSH.
110 *
111 * TLBs:
112 *
113 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
114 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
115 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
116 * are flushed at any MI_FLUSH.
117 */
118
119 cmd = MI_FLUSH;
120 if (mode & EMIT_INVALIDATE) {
121 cmd |= MI_EXE_FLUSH;
122 if (IS_G4X(req->i915) || IS_GEN5(req->i915))
123 cmd |= MI_INVALIDATE_ISP;
124 }
125
126 ret = intel_ring_begin(req, 2);
127 if (ret)
128 return ret;
129
130 intel_ring_emit(ring, cmd);
131 intel_ring_emit(ring, MI_NOOP);
132 intel_ring_advance(ring);
133
134 return 0;
135}
136
137/**
138 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
139 * implementing two workarounds on gen6. From section 1.4.7.1
140 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
141 *
142 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
143 * produced by non-pipelined state commands), software needs to first
144 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
145 * 0.
146 *
147 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
148 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
149 *
150 * And the workaround for these two requires this workaround first:
151 *
152 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
153 * BEFORE the pipe-control with a post-sync op and no write-cache
154 * flushes.
155 *
156 * And this last workaround is tricky because of the requirements on
157 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
158 * volume 2 part 1:
159 *
160 * "1 of the following must also be set:
161 * - Render Target Cache Flush Enable ([12] of DW1)
162 * - Depth Cache Flush Enable ([0] of DW1)
163 * - Stall at Pixel Scoreboard ([1] of DW1)
164 * - Depth Stall ([13] of DW1)
165 * - Post-Sync Operation ([13] of DW1)
166 * - Notify Enable ([8] of DW1)"
167 *
168 * The cache flushes require the workaround flush that triggered this
169 * one, so we can't use it. Depth stall would trigger the same.
170 * Post-sync nonzero is what triggered this second workaround, so we
171 * can't use that one either. Notify enable is IRQs, which aren't
172 * really our business. That leaves only stall at scoreboard.
173 */
174static int
175intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
176{
177 struct intel_ring *ring = req->ring;
178 u32 scratch_addr =
179 i915_ggtt_offset(req->engine->scratch) + 2 * CACHELINE_BYTES;
180 int ret;
181
182 ret = intel_ring_begin(req, 6);
183 if (ret)
184 return ret;
185
186 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
187 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
188 PIPE_CONTROL_STALL_AT_SCOREBOARD);
189 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
190 intel_ring_emit(ring, 0); /* low dword */
191 intel_ring_emit(ring, 0); /* high dword */
192 intel_ring_emit(ring, MI_NOOP);
193 intel_ring_advance(ring);
194
195 ret = intel_ring_begin(req, 6);
196 if (ret)
197 return ret;
198
199 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
200 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
201 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
202 intel_ring_emit(ring, 0);
203 intel_ring_emit(ring, 0);
204 intel_ring_emit(ring, MI_NOOP);
205 intel_ring_advance(ring);
206
207 return 0;
208}
209
210static int
211gen6_render_ring_flush(struct drm_i915_gem_request *req, u32 mode)
212{
213 struct intel_ring *ring = req->ring;
214 u32 scratch_addr =
215 i915_ggtt_offset(req->engine->scratch) + 2 * CACHELINE_BYTES;
216 u32 flags = 0;
217 int ret;
218
219 /* Force SNB workarounds for PIPE_CONTROL flushes */
220 ret = intel_emit_post_sync_nonzero_flush(req);
221 if (ret)
222 return ret;
223
224 /* Just flush everything. Experiments have shown that reducing the
225 * number of bits based on the write domains has little performance
226 * impact.
227 */
228 if (mode & EMIT_FLUSH) {
229 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
230 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
231 /*
232 * Ensure that any following seqno writes only happen
233 * when the render cache is indeed flushed.
234 */
235 flags |= PIPE_CONTROL_CS_STALL;
236 }
237 if (mode & EMIT_INVALIDATE) {
238 flags |= PIPE_CONTROL_TLB_INVALIDATE;
239 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
240 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
241 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
242 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
243 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
244 /*
245 * TLB invalidate requires a post-sync write.
246 */
247 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
248 }
249
250 ret = intel_ring_begin(req, 4);
251 if (ret)
252 return ret;
253
254 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
255 intel_ring_emit(ring, flags);
256 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
257 intel_ring_emit(ring, 0);
258 intel_ring_advance(ring);
259
260 return 0;
261}
262
263static int
264gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
265{
266 struct intel_ring *ring = req->ring;
267 int ret;
268
269 ret = intel_ring_begin(req, 4);
270 if (ret)
271 return ret;
272
273 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
274 intel_ring_emit(ring,
275 PIPE_CONTROL_CS_STALL |
276 PIPE_CONTROL_STALL_AT_SCOREBOARD);
277 intel_ring_emit(ring, 0);
278 intel_ring_emit(ring, 0);
279 intel_ring_advance(ring);
280
281 return 0;
282}
283
284static int
285gen7_render_ring_flush(struct drm_i915_gem_request *req, u32 mode)
286{
287 struct intel_ring *ring = req->ring;
288 u32 scratch_addr =
289 i915_ggtt_offset(req->engine->scratch) + 2 * CACHELINE_BYTES;
290 u32 flags = 0;
291 int ret;
292
293 /*
294 * Ensure that any following seqno writes only happen when the render
295 * cache is indeed flushed.
296 *
297 * Workaround: 4th PIPE_CONTROL command (except the ones with only
298 * read-cache invalidate bits set) must have the CS_STALL bit set. We
299 * don't try to be clever and just set it unconditionally.
300 */
301 flags |= PIPE_CONTROL_CS_STALL;
302
303 /* Just flush everything. Experiments have shown that reducing the
304 * number of bits based on the write domains has little performance
305 * impact.
306 */
307 if (mode & EMIT_FLUSH) {
308 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
309 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
310 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
311 flags |= PIPE_CONTROL_FLUSH_ENABLE;
312 }
313 if (mode & EMIT_INVALIDATE) {
314 flags |= PIPE_CONTROL_TLB_INVALIDATE;
315 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
316 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
317 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
318 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
319 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
320 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
321 /*
322 * TLB invalidate requires a post-sync write.
323 */
324 flags |= PIPE_CONTROL_QW_WRITE;
325 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
326
327 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
328
329 /* Workaround: we must issue a pipe_control with CS-stall bit
330 * set before a pipe_control command that has the state cache
331 * invalidate bit set. */
332 gen7_render_ring_cs_stall_wa(req);
333 }
334
335 ret = intel_ring_begin(req, 4);
336 if (ret)
337 return ret;
338
339 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
340 intel_ring_emit(ring, flags);
341 intel_ring_emit(ring, scratch_addr);
342 intel_ring_emit(ring, 0);
343 intel_ring_advance(ring);
344
345 return 0;
346}
347
348static int
349gen8_emit_pipe_control(struct drm_i915_gem_request *req,
350 u32 flags, u32 scratch_addr)
351{
352 struct intel_ring *ring = req->ring;
353 int ret;
354
355 ret = intel_ring_begin(req, 6);
356 if (ret)
357 return ret;
358
359 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
360 intel_ring_emit(ring, flags);
361 intel_ring_emit(ring, scratch_addr);
362 intel_ring_emit(ring, 0);
363 intel_ring_emit(ring, 0);
364 intel_ring_emit(ring, 0);
365 intel_ring_advance(ring);
366
367 return 0;
368}
369
370static int
371gen8_render_ring_flush(struct drm_i915_gem_request *req, u32 mode)
372{
373 u32 scratch_addr =
374 i915_ggtt_offset(req->engine->scratch) + 2 * CACHELINE_BYTES;
375 u32 flags = 0;
376 int ret;
377
378 flags |= PIPE_CONTROL_CS_STALL;
379
380 if (mode & EMIT_FLUSH) {
381 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
382 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
383 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
384 flags |= PIPE_CONTROL_FLUSH_ENABLE;
385 }
386 if (mode & EMIT_INVALIDATE) {
387 flags |= PIPE_CONTROL_TLB_INVALIDATE;
388 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
389 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
390 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
391 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
392 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
393 flags |= PIPE_CONTROL_QW_WRITE;
394 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
395
396 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
397 ret = gen8_emit_pipe_control(req,
398 PIPE_CONTROL_CS_STALL |
399 PIPE_CONTROL_STALL_AT_SCOREBOARD,
400 0);
401 if (ret)
402 return ret;
403 }
404
405 return gen8_emit_pipe_control(req, flags, scratch_addr);
406}
407
408static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
409{
410 struct drm_i915_private *dev_priv = engine->i915;
411 u32 addr;
412
413 addr = dev_priv->status_page_dmah->busaddr;
414 if (INTEL_GEN(dev_priv) >= 4)
415 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
416 I915_WRITE(HWS_PGA, addr);
417}
418
419static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
420{
421 struct drm_i915_private *dev_priv = engine->i915;
422 i915_reg_t mmio;
423
424 /* The ring status page addresses are no longer next to the rest of
425 * the ring registers as of gen7.
426 */
427 if (IS_GEN7(dev_priv)) {
428 switch (engine->id) {
429 case RCS:
430 mmio = RENDER_HWS_PGA_GEN7;
431 break;
432 case BCS:
433 mmio = BLT_HWS_PGA_GEN7;
434 break;
435 /*
436 * VCS2 actually doesn't exist on Gen7. Only shut up
437 * gcc switch check warning
438 */
439 case VCS2:
440 case VCS:
441 mmio = BSD_HWS_PGA_GEN7;
442 break;
443 case VECS:
444 mmio = VEBOX_HWS_PGA_GEN7;
445 break;
446 }
447 } else if (IS_GEN6(dev_priv)) {
448 mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
449 } else {
450 /* XXX: gen8 returns to sanity */
451 mmio = RING_HWS_PGA(engine->mmio_base);
452 }
453
454 I915_WRITE(mmio, engine->status_page.ggtt_offset);
455 POSTING_READ(mmio);
456
457 /*
458 * Flush the TLB for this page
459 *
460 * FIXME: These two bits have disappeared on gen8, so a question
461 * arises: do we still need this and if so how should we go about
462 * invalidating the TLB?
463 */
464 if (IS_GEN(dev_priv, 6, 7)) {
465 i915_reg_t reg = RING_INSTPM(engine->mmio_base);
466
467 /* ring should be idle before issuing a sync flush*/
468 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
469
470 I915_WRITE(reg,
471 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
472 INSTPM_SYNC_FLUSH));
473 if (intel_wait_for_register(dev_priv,
474 reg, INSTPM_SYNC_FLUSH, 0,
475 1000))
476 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
477 engine->name);
478 }
479}
480
481static bool stop_ring(struct intel_engine_cs *engine)
482{
483 struct drm_i915_private *dev_priv = engine->i915;
484
485 if (INTEL_GEN(dev_priv) > 2) {
486 I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));
487 if (intel_wait_for_register(dev_priv,
488 RING_MI_MODE(engine->mmio_base),
489 MODE_IDLE,
490 MODE_IDLE,
491 1000)) {
492 DRM_ERROR("%s : timed out trying to stop ring\n",
493 engine->name);
494 /* Sometimes we observe that the idle flag is not
495 * set even though the ring is empty. So double
496 * check before giving up.
497 */
498 if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine))
499 return false;
500 }
501 }
502
503 I915_WRITE_CTL(engine, 0);
504 I915_WRITE_HEAD(engine, 0);
505 I915_WRITE_TAIL(engine, 0);
506
507 if (INTEL_GEN(dev_priv) > 2) {
508 (void)I915_READ_CTL(engine);
509 I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
510 }
511
512 return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0;
513}
514
515static int init_ring_common(struct intel_engine_cs *engine)
516{
517 struct drm_i915_private *dev_priv = engine->i915;
518 struct intel_ring *ring = engine->buffer;
519 int ret = 0;
520
521 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
522
523 if (!stop_ring(engine)) {
524 /* G45 ring initialization often fails to reset head to zero */
525 DRM_DEBUG_KMS("%s head not reset to zero "
526 "ctl %08x head %08x tail %08x start %08x\n",
527 engine->name,
528 I915_READ_CTL(engine),
529 I915_READ_HEAD(engine),
530 I915_READ_TAIL(engine),
531 I915_READ_START(engine));
532
533 if (!stop_ring(engine)) {
534 DRM_ERROR("failed to set %s head to zero "
535 "ctl %08x head %08x tail %08x start %08x\n",
536 engine->name,
537 I915_READ_CTL(engine),
538 I915_READ_HEAD(engine),
539 I915_READ_TAIL(engine),
540 I915_READ_START(engine));
541 ret = -EIO;
542 goto out;
543 }
544 }
545
546 if (HWS_NEEDS_PHYSICAL(dev_priv))
547 ring_setup_phys_status_page(engine);
548 else
549 intel_ring_setup_status_page(engine);
550
551 intel_engine_reset_breadcrumbs(engine);
552
553 /* Enforce ordering by reading HEAD register back */
554 I915_READ_HEAD(engine);
555
556 /* Initialize the ring. This must happen _after_ we've cleared the ring
557 * registers with the above sequence (the readback of the HEAD registers
558 * also enforces ordering), otherwise the hw might lose the new ring
559 * register values. */
560 I915_WRITE_START(engine, i915_ggtt_offset(ring->vma));
561
562 /* WaClearRingBufHeadRegAtInit:ctg,elk */
563 if (I915_READ_HEAD(engine))
564 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
565 engine->name, I915_READ_HEAD(engine));
566
567 intel_ring_update_space(ring);
568 I915_WRITE_HEAD(engine, ring->head);
569 I915_WRITE_TAIL(engine, ring->tail);
570 (void)I915_READ_TAIL(engine);
571
572 I915_WRITE_CTL(engine, RING_CTL_SIZE(ring->size) | RING_VALID);
573
574 /* If the head is still not zero, the ring is dead */
575 if (intel_wait_for_register_fw(dev_priv, RING_CTL(engine->mmio_base),
576 RING_VALID, RING_VALID,
577 50)) {
578 DRM_ERROR("%s initialization failed "
579 "ctl %08x (valid? %d) head %08x [%08x] tail %08x [%08x] start %08x [expected %08x]\n",
580 engine->name,
581 I915_READ_CTL(engine),
582 I915_READ_CTL(engine) & RING_VALID,
583 I915_READ_HEAD(engine), ring->head,
584 I915_READ_TAIL(engine), ring->tail,
585 I915_READ_START(engine),
586 i915_ggtt_offset(ring->vma));
587 ret = -EIO;
588 goto out;
589 }
590
591 intel_engine_init_hangcheck(engine);
592
593out:
594 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
595
596 return ret;
597}
598
599static void reset_ring_common(struct intel_engine_cs *engine,
600 struct drm_i915_gem_request *request)
601{
602 struct intel_ring *ring = request->ring;
603
604 ring->head = request->postfix;
605 ring->last_retired_head = -1;
606}
607
608static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
609{
610 struct intel_ring *ring = req->ring;
611 struct i915_workarounds *w = &req->i915->workarounds;
612 int ret, i;
613
614 if (w->count == 0)
615 return 0;
616
617 ret = req->engine->emit_flush(req, EMIT_BARRIER);
618 if (ret)
619 return ret;
620
621 ret = intel_ring_begin(req, (w->count * 2 + 2));
622 if (ret)
623 return ret;
624
625 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
626 for (i = 0; i < w->count; i++) {
627 intel_ring_emit_reg(ring, w->reg[i].addr);
628 intel_ring_emit(ring, w->reg[i].value);
629 }
630 intel_ring_emit(ring, MI_NOOP);
631
632 intel_ring_advance(ring);
633
634 ret = req->engine->emit_flush(req, EMIT_BARRIER);
635 if (ret)
636 return ret;
637
638 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
639
640 return 0;
641}
642
643static int intel_rcs_ctx_init(struct drm_i915_gem_request *req)
644{
645 int ret;
646
647 ret = intel_ring_workarounds_emit(req);
648 if (ret != 0)
649 return ret;
650
651 ret = i915_gem_render_state_emit(req);
652 if (ret)
653 return ret;
654
655 return 0;
656}
657
658static int wa_add(struct drm_i915_private *dev_priv,
659 i915_reg_t addr,
660 const u32 mask, const u32 val)
661{
662 const u32 idx = dev_priv->workarounds.count;
663
664 if (WARN_ON(idx >= I915_MAX_WA_REGS))
665 return -ENOSPC;
666
667 dev_priv->workarounds.reg[idx].addr = addr;
668 dev_priv->workarounds.reg[idx].value = val;
669 dev_priv->workarounds.reg[idx].mask = mask;
670
671 dev_priv->workarounds.count++;
672
673 return 0;
674}
675
676#define WA_REG(addr, mask, val) do { \
677 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
678 if (r) \
679 return r; \
680 } while (0)
681
682#define WA_SET_BIT_MASKED(addr, mask) \
683 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
684
685#define WA_CLR_BIT_MASKED(addr, mask) \
686 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
687
688#define WA_SET_FIELD_MASKED(addr, mask, value) \
689 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
690
691#define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
692#define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
693
694#define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
695
696static int wa_ring_whitelist_reg(struct intel_engine_cs *engine,
697 i915_reg_t reg)
698{
699 struct drm_i915_private *dev_priv = engine->i915;
700 struct i915_workarounds *wa = &dev_priv->workarounds;
701 const uint32_t index = wa->hw_whitelist_count[engine->id];
702
703 if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS))
704 return -EINVAL;
705
706 WA_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index),
707 i915_mmio_reg_offset(reg));
708 wa->hw_whitelist_count[engine->id]++;
709
710 return 0;
711}
712
713static int gen8_init_workarounds(struct intel_engine_cs *engine)
714{
715 struct drm_i915_private *dev_priv = engine->i915;
716
717 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
718
719 /* WaDisableAsyncFlipPerfMode:bdw,chv */
720 WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
721
722 /* WaDisablePartialInstShootdown:bdw,chv */
723 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
724 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
725
726 /* Use Force Non-Coherent whenever executing a 3D context. This is a
727 * workaround for for a possible hang in the unlikely event a TLB
728 * invalidation occurs during a PSD flush.
729 */
730 /* WaForceEnableNonCoherent:bdw,chv */
731 /* WaHdcDisableFetchWhenMasked:bdw,chv */
732 WA_SET_BIT_MASKED(HDC_CHICKEN0,
733 HDC_DONOT_FETCH_MEM_WHEN_MASKED |
734 HDC_FORCE_NON_COHERENT);
735
736 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
737 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
738 * polygons in the same 8x4 pixel/sample area to be processed without
739 * stalling waiting for the earlier ones to write to Hierarchical Z
740 * buffer."
741 *
742 * This optimization is off by default for BDW and CHV; turn it on.
743 */
744 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
745
746 /* Wa4x4STCOptimizationDisable:bdw,chv */
747 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
748
749 /*
750 * BSpec recommends 8x4 when MSAA is used,
751 * however in practice 16x4 seems fastest.
752 *
753 * Note that PS/WM thread counts depend on the WIZ hashing
754 * disable bit, which we don't touch here, but it's good
755 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
756 */
757 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
758 GEN6_WIZ_HASHING_MASK,
759 GEN6_WIZ_HASHING_16x4);
760
761 return 0;
762}
763
764static int bdw_init_workarounds(struct intel_engine_cs *engine)
765{
766 struct drm_i915_private *dev_priv = engine->i915;
767 int ret;
768
769 ret = gen8_init_workarounds(engine);
770 if (ret)
771 return ret;
772
773 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
774 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
775
776 /* WaDisableDopClockGating:bdw */
777 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
778 DOP_CLOCK_GATING_DISABLE);
779
780 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
781 GEN8_SAMPLER_POWER_BYPASS_DIS);
782
783 WA_SET_BIT_MASKED(HDC_CHICKEN0,
784 /* WaForceContextSaveRestoreNonCoherent:bdw */
785 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
786 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
787 (IS_BDW_GT3(dev_priv) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
788
789 return 0;
790}
791
792static int chv_init_workarounds(struct intel_engine_cs *engine)
793{
794 struct drm_i915_private *dev_priv = engine->i915;
795 int ret;
796
797 ret = gen8_init_workarounds(engine);
798 if (ret)
799 return ret;
800
801 /* WaDisableThreadStallDopClockGating:chv */
802 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
803
804 /* Improve HiZ throughput on CHV. */
805 WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
806
807 return 0;
808}
809
810static int gen9_init_workarounds(struct intel_engine_cs *engine)
811{
812 struct drm_i915_private *dev_priv = engine->i915;
813 int ret;
814
815 /* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl */
816 I915_WRITE(GEN9_CSFE_CHICKEN1_RCS, _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE));
817
818 /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl */
819 I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
820 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
821
822 /* WaDisableKillLogic:bxt,skl,kbl */
823 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
824 ECOCHK_DIS_TLB);
825
826 /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl */
827 /* WaDisablePartialInstShootdown:skl,bxt,kbl */
828 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
829 FLOW_CONTROL_ENABLE |
830 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
831
832 /* Syncing dependencies between camera and graphics:skl,bxt,kbl */
833 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
834 GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
835
836 /* WaDisableDgMirrorFixInHalfSliceChicken5:bxt */
837 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
838 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
839 GEN9_DG_MIRROR_FIX_ENABLE);
840
841 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt */
842 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
843 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
844 GEN9_RHWO_OPTIMIZATION_DISABLE);
845 /*
846 * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
847 * but we do that in per ctx batchbuffer as there is an issue
848 * with this register not getting restored on ctx restore
849 */
850 }
851
852 /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl */
853 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
854 GEN9_ENABLE_GPGPU_PREEMPTION);
855
856 /* Wa4x4STCOptimizationDisable:skl,bxt,kbl */
857 /* WaDisablePartialResolveInVc:skl,bxt,kbl */
858 WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
859 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
860
861 /* WaCcsTlbPrefetchDisable:skl,bxt,kbl */
862 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
863 GEN9_CCS_TLB_PREFETCH_ENABLE);
864
865 /* WaDisableMaskBasedCammingInRCC:bxt */
866 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
867 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
868 PIXEL_MASK_CAMMING_DISABLE);
869
870 /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl */
871 WA_SET_BIT_MASKED(HDC_CHICKEN0,
872 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
873 HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE);
874
875 /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are
876 * both tied to WaForceContextSaveRestoreNonCoherent
877 * in some hsds for skl. We keep the tie for all gen9. The
878 * documentation is a bit hazy and so we want to get common behaviour,
879 * even though there is no clear evidence we would need both on kbl/bxt.
880 * This area has been source of system hangs so we play it safe
881 * and mimic the skl regardless of what bspec says.
882 *
883 * Use Force Non-Coherent whenever executing a 3D context. This
884 * is a workaround for a possible hang in the unlikely event
885 * a TLB invalidation occurs during a PSD flush.
886 */
887
888 /* WaForceEnableNonCoherent:skl,bxt,kbl */
889 WA_SET_BIT_MASKED(HDC_CHICKEN0,
890 HDC_FORCE_NON_COHERENT);
891
892 /* WaDisableHDCInvalidation:skl,bxt,kbl */
893 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
894 BDW_DISABLE_HDC_INVALIDATION);
895
896 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl */
897 if (IS_SKYLAKE(dev_priv) ||
898 IS_KABYLAKE(dev_priv) ||
899 IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
900 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
901 GEN8_SAMPLER_POWER_BYPASS_DIS);
902
903 /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl */
904 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
905
906 /* WaOCLCoherentLineFlush:skl,bxt,kbl */
907 I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
908 GEN8_LQSC_FLUSH_COHERENT_LINES));
909
910 /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt */
911 ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG);
912 if (ret)
913 return ret;
914
915 /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl */
916 ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
917 if (ret)
918 return ret;
919
920 /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl */
921 ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1);
922 if (ret)
923 return ret;
924
925 return 0;
926}
927
928static int skl_tune_iz_hashing(struct intel_engine_cs *engine)
929{
930 struct drm_i915_private *dev_priv = engine->i915;
931 u8 vals[3] = { 0, 0, 0 };
932 unsigned int i;
933
934 for (i = 0; i < 3; i++) {
935 u8 ss;
936
937 /*
938 * Only consider slices where one, and only one, subslice has 7
939 * EUs
940 */
941 if (!is_power_of_2(INTEL_INFO(dev_priv)->sseu.subslice_7eu[i]))
942 continue;
943
944 /*
945 * subslice_7eu[i] != 0 (because of the check above) and
946 * ss_max == 4 (maximum number of subslices possible per slice)
947 *
948 * -> 0 <= ss <= 3;
949 */
950 ss = ffs(INTEL_INFO(dev_priv)->sseu.subslice_7eu[i]) - 1;
951 vals[i] = 3 - ss;
952 }
953
954 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
955 return 0;
956
957 /* Tune IZ hashing. See intel_device_info_runtime_init() */
958 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
959 GEN9_IZ_HASHING_MASK(2) |
960 GEN9_IZ_HASHING_MASK(1) |
961 GEN9_IZ_HASHING_MASK(0),
962 GEN9_IZ_HASHING(2, vals[2]) |
963 GEN9_IZ_HASHING(1, vals[1]) |
964 GEN9_IZ_HASHING(0, vals[0]));
965
966 return 0;
967}
968
969static int skl_init_workarounds(struct intel_engine_cs *engine)
970{
971 struct drm_i915_private *dev_priv = engine->i915;
972 int ret;
973
974 ret = gen9_init_workarounds(engine);
975 if (ret)
976 return ret;
977
978 /*
979 * Actual WA is to disable percontext preemption granularity control
980 * until D0 which is the default case so this is equivalent to
981 * !WaDisablePerCtxtPreemptionGranularityControl:skl
982 */
983 I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
984 _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
985
986 /* WaEnableGapsTsvCreditFix:skl */
987 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
988 GEN9_GAPS_TSV_CREDIT_DISABLE));
989
990 /* WaDisableGafsUnitClkGating:skl */
991 WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
992
993 /* WaInPlaceDecompressionHang:skl */
994 if (IS_SKL_REVID(dev_priv, SKL_REVID_H0, REVID_FOREVER))
995 WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
996 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
997
998 /* WaDisableLSQCROPERFforOCL:skl */
999 ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
1000 if (ret)
1001 return ret;
1002
1003 return skl_tune_iz_hashing(engine);
1004}
1005
1006static int bxt_init_workarounds(struct intel_engine_cs *engine)
1007{
1008 struct drm_i915_private *dev_priv = engine->i915;
1009 int ret;
1010
1011 ret = gen9_init_workarounds(engine);
1012 if (ret)
1013 return ret;
1014
1015 /* WaStoreMultiplePTEenable:bxt */
1016 /* This is a requirement according to Hardware specification */
1017 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
1018 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
1019
1020 /* WaSetClckGatingDisableMedia:bxt */
1021 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
1022 I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
1023 ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
1024 }
1025
1026 /* WaDisableThreadStallDopClockGating:bxt */
1027 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1028 STALL_DOP_GATING_DISABLE);
1029
1030 /* WaDisablePooledEuLoadBalancingFix:bxt */
1031 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) {
1032 WA_SET_BIT_MASKED(FF_SLICE_CS_CHICKEN2,
1033 GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE);
1034 }
1035
1036 /* WaDisableSbeCacheDispatchPortSharing:bxt */
1037 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) {
1038 WA_SET_BIT_MASKED(
1039 GEN7_HALF_SLICE_CHICKEN1,
1040 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1041 }
1042
1043 /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */
1044 /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */
1045 /* WaDisableObjectLevelPreemtionForInstanceId:bxt */
1046 /* WaDisableLSQCROPERFforOCL:bxt */
1047 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
1048 ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1);
1049 if (ret)
1050 return ret;
1051
1052 ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
1053 if (ret)
1054 return ret;
1055 }
1056
1057 /* WaProgramL3SqcReg1DefaultForPerf:bxt */
1058 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
1059 I915_WRITE(GEN8_L3SQCREG1, L3_GENERAL_PRIO_CREDITS(62) |
1060 L3_HIGH_PRIO_CREDITS(2));
1061
1062 /* WaToEnableHwFixForPushConstHWBug:bxt */
1063 if (IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER))
1064 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
1065 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
1066
1067 /* WaInPlaceDecompressionHang:bxt */
1068 if (IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER))
1069 WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
1070 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
1071
1072 return 0;
1073}
1074
1075static int kbl_init_workarounds(struct intel_engine_cs *engine)
1076{
1077 struct drm_i915_private *dev_priv = engine->i915;
1078 int ret;
1079
1080 ret = gen9_init_workarounds(engine);
1081 if (ret)
1082 return ret;
1083
1084 /* WaEnableGapsTsvCreditFix:kbl */
1085 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
1086 GEN9_GAPS_TSV_CREDIT_DISABLE));
1087
1088 /* WaDisableDynamicCreditSharing:kbl */
1089 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
1090 WA_SET_BIT(GAMT_CHKN_BIT_REG,
1091 GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING);
1092
1093 /* WaDisableFenceDestinationToSLM:kbl (pre-prod) */
1094 if (IS_KBL_REVID(dev_priv, KBL_REVID_A0, KBL_REVID_A0))
1095 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1096 HDC_FENCE_DEST_SLM_DISABLE);
1097
1098 /* WaToEnableHwFixForPushConstHWBug:kbl */
1099 if (IS_KBL_REVID(dev_priv, KBL_REVID_C0, REVID_FOREVER))
1100 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
1101 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
1102
1103 /* WaDisableGafsUnitClkGating:kbl */
1104 WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
1105
1106 /* WaDisableSbeCacheDispatchPortSharing:kbl */
1107 WA_SET_BIT_MASKED(
1108 GEN7_HALF_SLICE_CHICKEN1,
1109 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1110
1111 /* WaInPlaceDecompressionHang:kbl */
1112 WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
1113 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
1114
1115 /* WaDisableLSQCROPERFforOCL:kbl */
1116 ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
1117 if (ret)
1118 return ret;
1119
1120 return 0;
1121}
1122
1123int init_workarounds_ring(struct intel_engine_cs *engine)
1124{
1125 struct drm_i915_private *dev_priv = engine->i915;
1126
1127 WARN_ON(engine->id != RCS);
1128
1129 dev_priv->workarounds.count = 0;
1130 dev_priv->workarounds.hw_whitelist_count[RCS] = 0;
1131
1132 if (IS_BROADWELL(dev_priv))
1133 return bdw_init_workarounds(engine);
1134
1135 if (IS_CHERRYVIEW(dev_priv))
1136 return chv_init_workarounds(engine);
1137
1138 if (IS_SKYLAKE(dev_priv))
1139 return skl_init_workarounds(engine);
1140
1141 if (IS_BROXTON(dev_priv))
1142 return bxt_init_workarounds(engine);
1143
1144 if (IS_KABYLAKE(dev_priv))
1145 return kbl_init_workarounds(engine);
1146
1147 return 0;
1148}
1149
1150static int init_render_ring(struct intel_engine_cs *engine)
1151{
1152 struct drm_i915_private *dev_priv = engine->i915;
1153 int ret = init_ring_common(engine);
1154 if (ret)
1155 return ret;
1156
1157 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1158 if (IS_GEN(dev_priv, 4, 6))
1159 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1160
1161 /* We need to disable the AsyncFlip performance optimisations in order
1162 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1163 * programmed to '1' on all products.
1164 *
1165 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1166 */
1167 if (IS_GEN(dev_priv, 6, 7))
1168 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1169
1170 /* Required for the hardware to program scanline values for waiting */
1171 /* WaEnableFlushTlbInvalidationMode:snb */
1172 if (IS_GEN6(dev_priv))
1173 I915_WRITE(GFX_MODE,
1174 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
1175
1176 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1177 if (IS_GEN7(dev_priv))
1178 I915_WRITE(GFX_MODE_GEN7,
1179 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1180 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
1181
1182 if (IS_GEN6(dev_priv)) {
1183 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1184 * "If this bit is set, STCunit will have LRA as replacement
1185 * policy. [...] This bit must be reset. LRA replacement
1186 * policy is not supported."
1187 */
1188 I915_WRITE(CACHE_MODE_0,
1189 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
1190 }
1191
1192 if (IS_GEN(dev_priv, 6, 7))
1193 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1194
1195 if (INTEL_INFO(dev_priv)->gen >= 6)
1196 I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
1197
1198 return init_workarounds_ring(engine);
1199}
1200
1201static void render_ring_cleanup(struct intel_engine_cs *engine)
1202{
1203 struct drm_i915_private *dev_priv = engine->i915;
1204
1205 i915_vma_unpin_and_release(&dev_priv->semaphore);
1206}
1207
1208static u32 *gen8_rcs_signal(struct drm_i915_gem_request *req, u32 *out)
1209{
1210 struct drm_i915_private *dev_priv = req->i915;
1211 struct intel_engine_cs *waiter;
1212 enum intel_engine_id id;
1213
1214 for_each_engine(waiter, dev_priv, id) {
1215 u64 gtt_offset = req->engine->semaphore.signal_ggtt[id];
1216 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1217 continue;
1218
1219 *out++ = GFX_OP_PIPE_CONTROL(6);
1220 *out++ = (PIPE_CONTROL_GLOBAL_GTT_IVB |
1221 PIPE_CONTROL_QW_WRITE |
1222 PIPE_CONTROL_CS_STALL);
1223 *out++ = lower_32_bits(gtt_offset);
1224 *out++ = upper_32_bits(gtt_offset);
1225 *out++ = req->global_seqno;
1226 *out++ = 0;
1227 *out++ = (MI_SEMAPHORE_SIGNAL |
1228 MI_SEMAPHORE_TARGET(waiter->hw_id));
1229 *out++ = 0;
1230 }
1231
1232 return out;
1233}
1234
1235static u32 *gen8_xcs_signal(struct drm_i915_gem_request *req, u32 *out)
1236{
1237 struct drm_i915_private *dev_priv = req->i915;
1238 struct intel_engine_cs *waiter;
1239 enum intel_engine_id id;
1240
1241 for_each_engine(waiter, dev_priv, id) {
1242 u64 gtt_offset = req->engine->semaphore.signal_ggtt[id];
1243 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1244 continue;
1245
1246 *out++ = (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW;
1247 *out++ = lower_32_bits(gtt_offset) | MI_FLUSH_DW_USE_GTT;
1248 *out++ = upper_32_bits(gtt_offset);
1249 *out++ = req->global_seqno;
1250 *out++ = (MI_SEMAPHORE_SIGNAL |
1251 MI_SEMAPHORE_TARGET(waiter->hw_id));
1252 *out++ = 0;
1253 }
1254
1255 return out;
1256}
1257
1258static u32 *gen6_signal(struct drm_i915_gem_request *req, u32 *out)
1259{
1260 struct drm_i915_private *dev_priv = req->i915;
1261 struct intel_engine_cs *engine;
1262 enum intel_engine_id id;
1263 int num_rings = 0;
1264
1265 for_each_engine(engine, dev_priv, id) {
1266 i915_reg_t mbox_reg;
1267
1268 if (!(BIT(engine->hw_id) & GEN6_SEMAPHORES_MASK))
1269 continue;
1270
1271 mbox_reg = req->engine->semaphore.mbox.signal[engine->hw_id];
1272 if (i915_mmio_reg_valid(mbox_reg)) {
1273 *out++ = MI_LOAD_REGISTER_IMM(1);
1274 *out++ = i915_mmio_reg_offset(mbox_reg);
1275 *out++ = req->global_seqno;
1276 num_rings++;
1277 }
1278 }
1279 if (num_rings & 1)
1280 *out++ = MI_NOOP;
1281
1282 return out;
1283}
1284
1285static void i9xx_submit_request(struct drm_i915_gem_request *request)
1286{
1287 struct drm_i915_private *dev_priv = request->i915;
1288
1289 i915_gem_request_submit(request);
1290
1291 I915_WRITE_TAIL(request->engine, request->tail);
1292}
1293
1294static void i9xx_emit_breadcrumb(struct drm_i915_gem_request *req,
1295 u32 *out)
1296{
1297 *out++ = MI_STORE_DWORD_INDEX;
1298 *out++ = I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT;
1299 *out++ = req->global_seqno;
1300 *out++ = MI_USER_INTERRUPT;
1301
1302 req->tail = intel_ring_offset(req->ring, out);
1303}
1304
1305static const int i9xx_emit_breadcrumb_sz = 4;
1306
1307/**
1308 * gen6_sema_emit_breadcrumb - Update the semaphore mailbox registers
1309 *
1310 * @request - request to write to the ring
1311 *
1312 * Update the mailbox registers in the *other* rings with the current seqno.
1313 * This acts like a signal in the canonical semaphore.
1314 */
1315static void gen6_sema_emit_breadcrumb(struct drm_i915_gem_request *req,
1316 u32 *out)
1317{
1318 return i9xx_emit_breadcrumb(req,
1319 req->engine->semaphore.signal(req, out));
1320}
1321
1322static void gen8_render_emit_breadcrumb(struct drm_i915_gem_request *req,
1323 u32 *out)
1324{
1325 struct intel_engine_cs *engine = req->engine;
1326
1327 if (engine->semaphore.signal)
1328 out = engine->semaphore.signal(req, out);
1329
1330 *out++ = GFX_OP_PIPE_CONTROL(6);
1331 *out++ = (PIPE_CONTROL_GLOBAL_GTT_IVB |
1332 PIPE_CONTROL_CS_STALL |
1333 PIPE_CONTROL_QW_WRITE);
1334 *out++ = intel_hws_seqno_address(engine);
1335 *out++ = 0;
1336 *out++ = req->global_seqno;
1337 /* We're thrashing one dword of HWS. */
1338 *out++ = 0;
1339 *out++ = MI_USER_INTERRUPT;
1340 *out++ = MI_NOOP;
1341
1342 req->tail = intel_ring_offset(req->ring, out);
1343}
1344
1345static const int gen8_render_emit_breadcrumb_sz = 8;
1346
1347/**
1348 * intel_ring_sync - sync the waiter to the signaller on seqno
1349 *
1350 * @waiter - ring that is waiting
1351 * @signaller - ring which has, or will signal
1352 * @seqno - seqno which the waiter will block on
1353 */
1354
1355static int
1356gen8_ring_sync_to(struct drm_i915_gem_request *req,
1357 struct drm_i915_gem_request *signal)
1358{
1359 struct intel_ring *ring = req->ring;
1360 struct drm_i915_private *dev_priv = req->i915;
1361 u64 offset = GEN8_WAIT_OFFSET(req->engine, signal->engine->id);
1362 struct i915_hw_ppgtt *ppgtt;
1363 int ret;
1364
1365 ret = intel_ring_begin(req, 4);
1366 if (ret)
1367 return ret;
1368
1369 intel_ring_emit(ring,
1370 MI_SEMAPHORE_WAIT |
1371 MI_SEMAPHORE_GLOBAL_GTT |
1372 MI_SEMAPHORE_SAD_GTE_SDD);
1373 intel_ring_emit(ring, signal->global_seqno);
1374 intel_ring_emit(ring, lower_32_bits(offset));
1375 intel_ring_emit(ring, upper_32_bits(offset));
1376 intel_ring_advance(ring);
1377
1378 /* When the !RCS engines idle waiting upon a semaphore, they lose their
1379 * pagetables and we must reload them before executing the batch.
1380 * We do this on the i915_switch_context() following the wait and
1381 * before the dispatch.
1382 */
1383 ppgtt = req->ctx->ppgtt;
1384 if (ppgtt && req->engine->id != RCS)
1385 ppgtt->pd_dirty_rings |= intel_engine_flag(req->engine);
1386 return 0;
1387}
1388
1389static int
1390gen6_ring_sync_to(struct drm_i915_gem_request *req,
1391 struct drm_i915_gem_request *signal)
1392{
1393 struct intel_ring *ring = req->ring;
1394 u32 dw1 = MI_SEMAPHORE_MBOX |
1395 MI_SEMAPHORE_COMPARE |
1396 MI_SEMAPHORE_REGISTER;
1397 u32 wait_mbox = signal->engine->semaphore.mbox.wait[req->engine->hw_id];
1398 int ret;
1399
1400 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
1401
1402 ret = intel_ring_begin(req, 4);
1403 if (ret)
1404 return ret;
1405
1406 intel_ring_emit(ring, dw1 | wait_mbox);
1407 /* Throughout all of the GEM code, seqno passed implies our current
1408 * seqno is >= the last seqno executed. However for hardware the
1409 * comparison is strictly greater than.
1410 */
1411 intel_ring_emit(ring, signal->global_seqno - 1);
1412 intel_ring_emit(ring, 0);
1413 intel_ring_emit(ring, MI_NOOP);
1414 intel_ring_advance(ring);
1415
1416 return 0;
1417}
1418
1419static void
1420gen5_seqno_barrier(struct intel_engine_cs *engine)
1421{
1422 /* MI_STORE are internally buffered by the GPU and not flushed
1423 * either by MI_FLUSH or SyncFlush or any other combination of
1424 * MI commands.
1425 *
1426 * "Only the submission of the store operation is guaranteed.
1427 * The write result will be complete (coherent) some time later
1428 * (this is practically a finite period but there is no guaranteed
1429 * latency)."
1430 *
1431 * Empirically, we observe that we need a delay of at least 75us to
1432 * be sure that the seqno write is visible by the CPU.
1433 */
1434 usleep_range(125, 250);
1435}
1436
1437static void
1438gen6_seqno_barrier(struct intel_engine_cs *engine)
1439{
1440 struct drm_i915_private *dev_priv = engine->i915;
1441
1442 /* Workaround to force correct ordering between irq and seqno writes on
1443 * ivb (and maybe also on snb) by reading from a CS register (like
1444 * ACTHD) before reading the status page.
1445 *
1446 * Note that this effectively stalls the read by the time it takes to
1447 * do a memory transaction, which more or less ensures that the write
1448 * from the GPU has sufficient time to invalidate the CPU cacheline.
1449 * Alternatively we could delay the interrupt from the CS ring to give
1450 * the write time to land, but that would incur a delay after every
1451 * batch i.e. much more frequent than a delay when waiting for the
1452 * interrupt (with the same net latency).
1453 *
1454 * Also note that to prevent whole machine hangs on gen7, we have to
1455 * take the spinlock to guard against concurrent cacheline access.
1456 */
1457 spin_lock_irq(&dev_priv->uncore.lock);
1458 POSTING_READ_FW(RING_ACTHD(engine->mmio_base));
1459 spin_unlock_irq(&dev_priv->uncore.lock);
1460}
1461
1462static void
1463gen5_irq_enable(struct intel_engine_cs *engine)
1464{
1465 gen5_enable_gt_irq(engine->i915, engine->irq_enable_mask);
1466}
1467
1468static void
1469gen5_irq_disable(struct intel_engine_cs *engine)
1470{
1471 gen5_disable_gt_irq(engine->i915, engine->irq_enable_mask);
1472}
1473
1474static void
1475i9xx_irq_enable(struct intel_engine_cs *engine)
1476{
1477 struct drm_i915_private *dev_priv = engine->i915;
1478
1479 dev_priv->irq_mask &= ~engine->irq_enable_mask;
1480 I915_WRITE(IMR, dev_priv->irq_mask);
1481 POSTING_READ_FW(RING_IMR(engine->mmio_base));
1482}
1483
1484static void
1485i9xx_irq_disable(struct intel_engine_cs *engine)
1486{
1487 struct drm_i915_private *dev_priv = engine->i915;
1488
1489 dev_priv->irq_mask |= engine->irq_enable_mask;
1490 I915_WRITE(IMR, dev_priv->irq_mask);
1491}
1492
1493static void
1494i8xx_irq_enable(struct intel_engine_cs *engine)
1495{
1496 struct drm_i915_private *dev_priv = engine->i915;
1497
1498 dev_priv->irq_mask &= ~engine->irq_enable_mask;
1499 I915_WRITE16(IMR, dev_priv->irq_mask);
1500 POSTING_READ16(RING_IMR(engine->mmio_base));
1501}
1502
1503static void
1504i8xx_irq_disable(struct intel_engine_cs *engine)
1505{
1506 struct drm_i915_private *dev_priv = engine->i915;
1507
1508 dev_priv->irq_mask |= engine->irq_enable_mask;
1509 I915_WRITE16(IMR, dev_priv->irq_mask);
1510}
1511
1512static int
1513bsd_ring_flush(struct drm_i915_gem_request *req, u32 mode)
1514{
1515 struct intel_ring *ring = req->ring;
1516 int ret;
1517
1518 ret = intel_ring_begin(req, 2);
1519 if (ret)
1520 return ret;
1521
1522 intel_ring_emit(ring, MI_FLUSH);
1523 intel_ring_emit(ring, MI_NOOP);
1524 intel_ring_advance(ring);
1525 return 0;
1526}
1527
1528static void
1529gen6_irq_enable(struct intel_engine_cs *engine)
1530{
1531 struct drm_i915_private *dev_priv = engine->i915;
1532
1533 I915_WRITE_IMR(engine,
1534 ~(engine->irq_enable_mask |
1535 engine->irq_keep_mask));
1536 gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
1537}
1538
1539static void
1540gen6_irq_disable(struct intel_engine_cs *engine)
1541{
1542 struct drm_i915_private *dev_priv = engine->i915;
1543
1544 I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
1545 gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
1546}
1547
1548static void
1549hsw_vebox_irq_enable(struct intel_engine_cs *engine)
1550{
1551 struct drm_i915_private *dev_priv = engine->i915;
1552
1553 I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1554 gen6_unmask_pm_irq(dev_priv, engine->irq_enable_mask);
1555}
1556
1557static void
1558hsw_vebox_irq_disable(struct intel_engine_cs *engine)
1559{
1560 struct drm_i915_private *dev_priv = engine->i915;
1561
1562 I915_WRITE_IMR(engine, ~0);
1563 gen6_mask_pm_irq(dev_priv, engine->irq_enable_mask);
1564}
1565
1566static void
1567gen8_irq_enable(struct intel_engine_cs *engine)
1568{
1569 struct drm_i915_private *dev_priv = engine->i915;
1570
1571 I915_WRITE_IMR(engine,
1572 ~(engine->irq_enable_mask |
1573 engine->irq_keep_mask));
1574 POSTING_READ_FW(RING_IMR(engine->mmio_base));
1575}
1576
1577static void
1578gen8_irq_disable(struct intel_engine_cs *engine)
1579{
1580 struct drm_i915_private *dev_priv = engine->i915;
1581
1582 I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
1583}
1584
1585static int
1586i965_emit_bb_start(struct drm_i915_gem_request *req,
1587 u64 offset, u32 length,
1588 unsigned int dispatch_flags)
1589{
1590 struct intel_ring *ring = req->ring;
1591 int ret;
1592
1593 ret = intel_ring_begin(req, 2);
1594 if (ret)
1595 return ret;
1596
1597 intel_ring_emit(ring,
1598 MI_BATCH_BUFFER_START |
1599 MI_BATCH_GTT |
1600 (dispatch_flags & I915_DISPATCH_SECURE ?
1601 0 : MI_BATCH_NON_SECURE_I965));
1602 intel_ring_emit(ring, offset);
1603 intel_ring_advance(ring);
1604
1605 return 0;
1606}
1607
1608/* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1609#define I830_BATCH_LIMIT (256*1024)
1610#define I830_TLB_ENTRIES (2)
1611#define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1612static int
1613i830_emit_bb_start(struct drm_i915_gem_request *req,
1614 u64 offset, u32 len,
1615 unsigned int dispatch_flags)
1616{
1617 struct intel_ring *ring = req->ring;
1618 u32 cs_offset = i915_ggtt_offset(req->engine->scratch);
1619 int ret;
1620
1621 ret = intel_ring_begin(req, 6);
1622 if (ret)
1623 return ret;
1624
1625 /* Evict the invalid PTE TLBs */
1626 intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1627 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1628 intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1629 intel_ring_emit(ring, cs_offset);
1630 intel_ring_emit(ring, 0xdeadbeef);
1631 intel_ring_emit(ring, MI_NOOP);
1632 intel_ring_advance(ring);
1633
1634 if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
1635 if (len > I830_BATCH_LIMIT)
1636 return -ENOSPC;
1637
1638 ret = intel_ring_begin(req, 6 + 2);
1639 if (ret)
1640 return ret;
1641
1642 /* Blit the batch (which has now all relocs applied) to the
1643 * stable batch scratch bo area (so that the CS never
1644 * stumbles over its tlb invalidation bug) ...
1645 */
1646 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1647 intel_ring_emit(ring,
1648 BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1649 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
1650 intel_ring_emit(ring, cs_offset);
1651 intel_ring_emit(ring, 4096);
1652 intel_ring_emit(ring, offset);
1653
1654 intel_ring_emit(ring, MI_FLUSH);
1655 intel_ring_emit(ring, MI_NOOP);
1656 intel_ring_advance(ring);
1657
1658 /* ... and execute it. */
1659 offset = cs_offset;
1660 }
1661
1662 ret = intel_ring_begin(req, 2);
1663 if (ret)
1664 return ret;
1665
1666 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1667 intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1668 0 : MI_BATCH_NON_SECURE));
1669 intel_ring_advance(ring);
1670
1671 return 0;
1672}
1673
1674static int
1675i915_emit_bb_start(struct drm_i915_gem_request *req,
1676 u64 offset, u32 len,
1677 unsigned int dispatch_flags)
1678{
1679 struct intel_ring *ring = req->ring;
1680 int ret;
1681
1682 ret = intel_ring_begin(req, 2);
1683 if (ret)
1684 return ret;
1685
1686 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1687 intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1688 0 : MI_BATCH_NON_SECURE));
1689 intel_ring_advance(ring);
1690
1691 return 0;
1692}
1693
1694static void cleanup_phys_status_page(struct intel_engine_cs *engine)
1695{
1696 struct drm_i915_private *dev_priv = engine->i915;
1697
1698 if (!dev_priv->status_page_dmah)
1699 return;
1700
1701 drm_pci_free(&dev_priv->drm, dev_priv->status_page_dmah);
1702 engine->status_page.page_addr = NULL;
1703}
1704
1705static void cleanup_status_page(struct intel_engine_cs *engine)
1706{
1707 struct i915_vma *vma;
1708 struct drm_i915_gem_object *obj;
1709
1710 vma = fetch_and_zero(&engine->status_page.vma);
1711 if (!vma)
1712 return;
1713
1714 obj = vma->obj;
1715
1716 i915_vma_unpin(vma);
1717 i915_vma_close(vma);
1718
1719 i915_gem_object_unpin_map(obj);
1720 __i915_gem_object_release_unless_active(obj);
1721}
1722
1723static int init_status_page(struct intel_engine_cs *engine)
1724{
1725 struct drm_i915_gem_object *obj;
1726 struct i915_vma *vma;
1727 unsigned int flags;
1728 void *vaddr;
1729 int ret;
1730
1731 obj = i915_gem_object_create_internal(engine->i915, 4096);
1732 if (IS_ERR(obj)) {
1733 DRM_ERROR("Failed to allocate status page\n");
1734 return PTR_ERR(obj);
1735 }
1736
1737 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1738 if (ret)
1739 goto err;
1740
1741 vma = i915_vma_create(obj, &engine->i915->ggtt.base, NULL);
1742 if (IS_ERR(vma)) {
1743 ret = PTR_ERR(vma);
1744 goto err;
1745 }
1746
1747 flags = PIN_GLOBAL;
1748 if (!HAS_LLC(engine->i915))
1749 /* On g33, we cannot place HWS above 256MiB, so
1750 * restrict its pinning to the low mappable arena.
1751 * Though this restriction is not documented for
1752 * gen4, gen5, or byt, they also behave similarly
1753 * and hang if the HWS is placed at the top of the
1754 * GTT. To generalise, it appears that all !llc
1755 * platforms have issues with us placing the HWS
1756 * above the mappable region (even though we never
1757 * actualy map it).
1758 */
1759 flags |= PIN_MAPPABLE;
1760 ret = i915_vma_pin(vma, 0, 4096, flags);
1761 if (ret)
1762 goto err;
1763
1764 vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
1765 if (IS_ERR(vaddr)) {
1766 ret = PTR_ERR(vaddr);
1767 goto err_unpin;
1768 }
1769
1770 engine->status_page.vma = vma;
1771 engine->status_page.ggtt_offset = i915_ggtt_offset(vma);
1772 engine->status_page.page_addr = memset(vaddr, 0, 4096);
1773
1774 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1775 engine->name, i915_ggtt_offset(vma));
1776 return 0;
1777
1778err_unpin:
1779 i915_vma_unpin(vma);
1780err:
1781 i915_gem_object_put(obj);
1782 return ret;
1783}
1784
1785static int init_phys_status_page(struct intel_engine_cs *engine)
1786{
1787 struct drm_i915_private *dev_priv = engine->i915;
1788
1789 dev_priv->status_page_dmah =
1790 drm_pci_alloc(&dev_priv->drm, PAGE_SIZE, PAGE_SIZE);
1791 if (!dev_priv->status_page_dmah)
1792 return -ENOMEM;
1793
1794 engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1795 memset(engine->status_page.page_addr, 0, PAGE_SIZE);
1796
1797 return 0;
1798}
1799
1800int intel_ring_pin(struct intel_ring *ring)
1801{
1802 /* Ring wraparound at offset 0 sometimes hangs. No idea why. */
1803 unsigned int flags = PIN_GLOBAL | PIN_OFFSET_BIAS | 4096;
1804 enum i915_map_type map;
1805 struct i915_vma *vma = ring->vma;
1806 void *addr;
1807 int ret;
1808
1809 GEM_BUG_ON(ring->vaddr);
1810
1811 map = HAS_LLC(ring->engine->i915) ? I915_MAP_WB : I915_MAP_WC;
1812
1813 if (vma->obj->stolen)
1814 flags |= PIN_MAPPABLE;
1815
1816 if (!(vma->flags & I915_VMA_GLOBAL_BIND)) {
1817 if (flags & PIN_MAPPABLE || map == I915_MAP_WC)
1818 ret = i915_gem_object_set_to_gtt_domain(vma->obj, true);
1819 else
1820 ret = i915_gem_object_set_to_cpu_domain(vma->obj, true);
1821 if (unlikely(ret))
1822 return ret;
1823 }
1824
1825 ret = i915_vma_pin(vma, 0, PAGE_SIZE, flags);
1826 if (unlikely(ret))
1827 return ret;
1828
1829 if (i915_vma_is_map_and_fenceable(vma))
1830 addr = (void __force *)i915_vma_pin_iomap(vma);
1831 else
1832 addr = i915_gem_object_pin_map(vma->obj, map);
1833 if (IS_ERR(addr))
1834 goto err;
1835
1836 ring->vaddr = addr;
1837 return 0;
1838
1839err:
1840 i915_vma_unpin(vma);
1841 return PTR_ERR(addr);
1842}
1843
1844void intel_ring_unpin(struct intel_ring *ring)
1845{
1846 GEM_BUG_ON(!ring->vma);
1847 GEM_BUG_ON(!ring->vaddr);
1848
1849 if (i915_vma_is_map_and_fenceable(ring->vma))
1850 i915_vma_unpin_iomap(ring->vma);
1851 else
1852 i915_gem_object_unpin_map(ring->vma->obj);
1853 ring->vaddr = NULL;
1854
1855 i915_vma_unpin(ring->vma);
1856}
1857
1858static struct i915_vma *
1859intel_ring_create_vma(struct drm_i915_private *dev_priv, int size)
1860{
1861 struct drm_i915_gem_object *obj;
1862 struct i915_vma *vma;
1863
1864 obj = i915_gem_object_create_stolen(&dev_priv->drm, size);
1865 if (!obj)
1866 obj = i915_gem_object_create(&dev_priv->drm, size);
1867 if (IS_ERR(obj))
1868 return ERR_CAST(obj);
1869
1870 /* mark ring buffers as read-only from GPU side by default */
1871 obj->gt_ro = 1;
1872
1873 vma = i915_vma_create(obj, &dev_priv->ggtt.base, NULL);
1874 if (IS_ERR(vma))
1875 goto err;
1876
1877 return vma;
1878
1879err:
1880 i915_gem_object_put(obj);
1881 return vma;
1882}
1883
1884struct intel_ring *
1885intel_engine_create_ring(struct intel_engine_cs *engine, int size)
1886{
1887 struct intel_ring *ring;
1888 struct i915_vma *vma;
1889
1890 GEM_BUG_ON(!is_power_of_2(size));
1891 GEM_BUG_ON(RING_CTL_SIZE(size) & ~RING_NR_PAGES);
1892
1893 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
1894 if (!ring)
1895 return ERR_PTR(-ENOMEM);
1896
1897 ring->engine = engine;
1898
1899 INIT_LIST_HEAD(&ring->request_list);
1900
1901 ring->size = size;
1902 /* Workaround an erratum on the i830 which causes a hang if
1903 * the TAIL pointer points to within the last 2 cachelines
1904 * of the buffer.
1905 */
1906 ring->effective_size = size;
1907 if (IS_I830(engine->i915) || IS_845G(engine->i915))
1908 ring->effective_size -= 2 * CACHELINE_BYTES;
1909
1910 ring->last_retired_head = -1;
1911 intel_ring_update_space(ring);
1912
1913 vma = intel_ring_create_vma(engine->i915, size);
1914 if (IS_ERR(vma)) {
1915 kfree(ring);
1916 return ERR_CAST(vma);
1917 }
1918 ring->vma = vma;
1919
1920 return ring;
1921}
1922
1923void
1924intel_ring_free(struct intel_ring *ring)
1925{
1926 struct drm_i915_gem_object *obj = ring->vma->obj;
1927
1928 i915_vma_close(ring->vma);
1929 __i915_gem_object_release_unless_active(obj);
1930
1931 kfree(ring);
1932}
1933
1934static int intel_ring_context_pin(struct i915_gem_context *ctx,
1935 struct intel_engine_cs *engine)
1936{
1937 struct intel_context *ce = &ctx->engine[engine->id];
1938 int ret;
1939
1940 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
1941
1942 if (ce->pin_count++)
1943 return 0;
1944
1945 if (ce->state) {
1946 struct i915_vma *vma;
1947
1948 vma = i915_gem_context_pin_legacy(ctx, PIN_HIGH);
1949 if (IS_ERR(vma)) {
1950 ret = PTR_ERR(vma);
1951 goto error;
1952 }
1953 }
1954
1955 /* The kernel context is only used as a placeholder for flushing the
1956 * active context. It is never used for submitting user rendering and
1957 * as such never requires the golden render context, and so we can skip
1958 * emitting it when we switch to the kernel context. This is required
1959 * as during eviction we cannot allocate and pin the renderstate in
1960 * order to initialise the context.
1961 */
1962 if (ctx == ctx->i915->kernel_context)
1963 ce->initialised = true;
1964
1965 i915_gem_context_get(ctx);
1966 return 0;
1967
1968error:
1969 ce->pin_count = 0;
1970 return ret;
1971}
1972
1973static void intel_ring_context_unpin(struct i915_gem_context *ctx,
1974 struct intel_engine_cs *engine)
1975{
1976 struct intel_context *ce = &ctx->engine[engine->id];
1977
1978 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
1979
1980 if (--ce->pin_count)
1981 return;
1982
1983 if (ce->state)
1984 i915_vma_unpin(ce->state);
1985
1986 i915_gem_context_put(ctx);
1987}
1988
1989static int intel_init_ring_buffer(struct intel_engine_cs *engine)
1990{
1991 struct drm_i915_private *dev_priv = engine->i915;
1992 struct intel_ring *ring;
1993 int ret;
1994
1995 WARN_ON(engine->buffer);
1996
1997 intel_engine_setup_common(engine);
1998
1999 ret = intel_engine_init_common(engine);
2000 if (ret)
2001 goto error;
2002
2003 /* We may need to do things with the shrinker which
2004 * require us to immediately switch back to the default
2005 * context. This can cause a problem as pinning the
2006 * default context also requires GTT space which may not
2007 * be available. To avoid this we always pin the default
2008 * context.
2009 */
2010 ret = intel_ring_context_pin(dev_priv->kernel_context, engine);
2011 if (ret)
2012 goto error;
2013
2014 ring = intel_engine_create_ring(engine, 32 * PAGE_SIZE);
2015 if (IS_ERR(ring)) {
2016 ret = PTR_ERR(ring);
2017 goto error;
2018 }
2019
2020 if (HWS_NEEDS_PHYSICAL(dev_priv)) {
2021 WARN_ON(engine->id != RCS);
2022 ret = init_phys_status_page(engine);
2023 if (ret)
2024 goto error;
2025 } else {
2026 ret = init_status_page(engine);
2027 if (ret)
2028 goto error;
2029 }
2030
2031 ret = intel_ring_pin(ring);
2032 if (ret) {
2033 intel_ring_free(ring);
2034 goto error;
2035 }
2036 engine->buffer = ring;
2037
2038 return 0;
2039
2040error:
2041 intel_engine_cleanup(engine);
2042 return ret;
2043}
2044
2045void intel_engine_cleanup(struct intel_engine_cs *engine)
2046{
2047 struct drm_i915_private *dev_priv;
2048
2049 dev_priv = engine->i915;
2050
2051 if (engine->buffer) {
2052 WARN_ON(INTEL_GEN(dev_priv) > 2 &&
2053 (I915_READ_MODE(engine) & MODE_IDLE) == 0);
2054
2055 intel_ring_unpin(engine->buffer);
2056 intel_ring_free(engine->buffer);
2057 engine->buffer = NULL;
2058 }
2059
2060 if (engine->cleanup)
2061 engine->cleanup(engine);
2062
2063 if (HWS_NEEDS_PHYSICAL(dev_priv)) {
2064 WARN_ON(engine->id != RCS);
2065 cleanup_phys_status_page(engine);
2066 } else {
2067 cleanup_status_page(engine);
2068 }
2069
2070 intel_engine_cleanup_common(engine);
2071
2072 intel_ring_context_unpin(dev_priv->kernel_context, engine);
2073
2074 engine->i915 = NULL;
2075 dev_priv->engine[engine->id] = NULL;
2076 kfree(engine);
2077}
2078
2079void intel_legacy_submission_resume(struct drm_i915_private *dev_priv)
2080{
2081 struct intel_engine_cs *engine;
2082 enum intel_engine_id id;
2083
2084 for_each_engine(engine, dev_priv, id) {
2085 engine->buffer->head = engine->buffer->tail;
2086 engine->buffer->last_retired_head = -1;
2087 }
2088}
2089
2090int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
2091{
2092 int ret;
2093
2094 /* Flush enough space to reduce the likelihood of waiting after
2095 * we start building the request - in which case we will just
2096 * have to repeat work.
2097 */
2098 request->reserved_space += LEGACY_REQUEST_SIZE;
2099
2100 request->ring = request->engine->buffer;
2101
2102 ret = intel_ring_begin(request, 0);
2103 if (ret)
2104 return ret;
2105
2106 request->reserved_space -= LEGACY_REQUEST_SIZE;
2107 return 0;
2108}
2109
2110static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
2111{
2112 struct intel_ring *ring = req->ring;
2113 struct drm_i915_gem_request *target;
2114 long timeout;
2115
2116 lockdep_assert_held(&req->i915->drm.struct_mutex);
2117
2118 intel_ring_update_space(ring);
2119 if (ring->space >= bytes)
2120 return 0;
2121
2122 /*
2123 * Space is reserved in the ringbuffer for finalising the request,
2124 * as that cannot be allowed to fail. During request finalisation,
2125 * reserved_space is set to 0 to stop the overallocation and the
2126 * assumption is that then we never need to wait (which has the
2127 * risk of failing with EINTR).
2128 *
2129 * See also i915_gem_request_alloc() and i915_add_request().
2130 */
2131 GEM_BUG_ON(!req->reserved_space);
2132
2133 list_for_each_entry(target, &ring->request_list, ring_link) {
2134 unsigned space;
2135
2136 /* Would completion of this request free enough space? */
2137 space = __intel_ring_space(target->postfix, ring->tail,
2138 ring->size);
2139 if (space >= bytes)
2140 break;
2141 }
2142
2143 if (WARN_ON(&target->ring_link == &ring->request_list))
2144 return -ENOSPC;
2145
2146 timeout = i915_wait_request(target,
2147 I915_WAIT_INTERRUPTIBLE | I915_WAIT_LOCKED,
2148 MAX_SCHEDULE_TIMEOUT);
2149 if (timeout < 0)
2150 return timeout;
2151
2152 i915_gem_request_retire_upto(target);
2153
2154 intel_ring_update_space(ring);
2155 GEM_BUG_ON(ring->space < bytes);
2156 return 0;
2157}
2158
2159int intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
2160{
2161 struct intel_ring *ring = req->ring;
2162 int remain_actual = ring->size - ring->tail;
2163 int remain_usable = ring->effective_size - ring->tail;
2164 int bytes = num_dwords * sizeof(u32);
2165 int total_bytes, wait_bytes;
2166 bool need_wrap = false;
2167
2168 total_bytes = bytes + req->reserved_space;
2169
2170 if (unlikely(bytes > remain_usable)) {
2171 /*
2172 * Not enough space for the basic request. So need to flush
2173 * out the remainder and then wait for base + reserved.
2174 */
2175 wait_bytes = remain_actual + total_bytes;
2176 need_wrap = true;
2177 } else if (unlikely(total_bytes > remain_usable)) {
2178 /*
2179 * The base request will fit but the reserved space
2180 * falls off the end. So we don't need an immediate wrap
2181 * and only need to effectively wait for the reserved
2182 * size space from the start of ringbuffer.
2183 */
2184 wait_bytes = remain_actual + req->reserved_space;
2185 } else {
2186 /* No wrapping required, just waiting. */
2187 wait_bytes = total_bytes;
2188 }
2189
2190 if (wait_bytes > ring->space) {
2191 int ret = wait_for_space(req, wait_bytes);
2192 if (unlikely(ret))
2193 return ret;
2194 }
2195
2196 if (unlikely(need_wrap)) {
2197 GEM_BUG_ON(remain_actual > ring->space);
2198 GEM_BUG_ON(ring->tail + remain_actual > ring->size);
2199
2200 /* Fill the tail with MI_NOOP */
2201 memset(ring->vaddr + ring->tail, 0, remain_actual);
2202 ring->tail = 0;
2203 ring->space -= remain_actual;
2204 }
2205
2206 ring->space -= bytes;
2207 GEM_BUG_ON(ring->space < 0);
2208 return 0;
2209}
2210
2211/* Align the ring tail to a cacheline boundary */
2212int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
2213{
2214 struct intel_ring *ring = req->ring;
2215 int num_dwords =
2216 (ring->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
2217 int ret;
2218
2219 if (num_dwords == 0)
2220 return 0;
2221
2222 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
2223 ret = intel_ring_begin(req, num_dwords);
2224 if (ret)
2225 return ret;
2226
2227 while (num_dwords--)
2228 intel_ring_emit(ring, MI_NOOP);
2229
2230 intel_ring_advance(ring);
2231
2232 return 0;
2233}
2234
2235static void gen6_bsd_submit_request(struct drm_i915_gem_request *request)
2236{
2237 struct drm_i915_private *dev_priv = request->i915;
2238
2239 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2240
2241 /* Every tail move must follow the sequence below */
2242
2243 /* Disable notification that the ring is IDLE. The GT
2244 * will then assume that it is busy and bring it out of rc6.
2245 */
2246 I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL,
2247 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2248
2249 /* Clear the context id. Here be magic! */
2250 I915_WRITE64_FW(GEN6_BSD_RNCID, 0x0);
2251
2252 /* Wait for the ring not to be idle, i.e. for it to wake up. */
2253 if (intel_wait_for_register_fw(dev_priv,
2254 GEN6_BSD_SLEEP_PSMI_CONTROL,
2255 GEN6_BSD_SLEEP_INDICATOR,
2256 0,
2257 50))
2258 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2259
2260 /* Now that the ring is fully powered up, update the tail */
2261 i9xx_submit_request(request);
2262
2263 /* Let the ring send IDLE messages to the GT again,
2264 * and so let it sleep to conserve power when idle.
2265 */
2266 I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL,
2267 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2268
2269 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2270}
2271
2272static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req, u32 mode)
2273{
2274 struct intel_ring *ring = req->ring;
2275 uint32_t cmd;
2276 int ret;
2277
2278 ret = intel_ring_begin(req, 4);
2279 if (ret)
2280 return ret;
2281
2282 cmd = MI_FLUSH_DW;
2283 if (INTEL_GEN(req->i915) >= 8)
2284 cmd += 1;
2285
2286 /* We always require a command barrier so that subsequent
2287 * commands, such as breadcrumb interrupts, are strictly ordered
2288 * wrt the contents of the write cache being flushed to memory
2289 * (and thus being coherent from the CPU).
2290 */
2291 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2292
2293 /*
2294 * Bspec vol 1c.5 - video engine command streamer:
2295 * "If ENABLED, all TLBs will be invalidated once the flush
2296 * operation is complete. This bit is only valid when the
2297 * Post-Sync Operation field is a value of 1h or 3h."
2298 */
2299 if (mode & EMIT_INVALIDATE)
2300 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2301
2302 intel_ring_emit(ring, cmd);
2303 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2304 if (INTEL_GEN(req->i915) >= 8) {
2305 intel_ring_emit(ring, 0); /* upper addr */
2306 intel_ring_emit(ring, 0); /* value */
2307 } else {
2308 intel_ring_emit(ring, 0);
2309 intel_ring_emit(ring, MI_NOOP);
2310 }
2311 intel_ring_advance(ring);
2312 return 0;
2313}
2314
2315static int
2316gen8_emit_bb_start(struct drm_i915_gem_request *req,
2317 u64 offset, u32 len,
2318 unsigned int dispatch_flags)
2319{
2320 struct intel_ring *ring = req->ring;
2321 bool ppgtt = USES_PPGTT(req->i915) &&
2322 !(dispatch_flags & I915_DISPATCH_SECURE);
2323 int ret;
2324
2325 ret = intel_ring_begin(req, 4);
2326 if (ret)
2327 return ret;
2328
2329 /* FIXME(BDW): Address space and security selectors. */
2330 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) |
2331 (dispatch_flags & I915_DISPATCH_RS ?
2332 MI_BATCH_RESOURCE_STREAMER : 0));
2333 intel_ring_emit(ring, lower_32_bits(offset));
2334 intel_ring_emit(ring, upper_32_bits(offset));
2335 intel_ring_emit(ring, MI_NOOP);
2336 intel_ring_advance(ring);
2337
2338 return 0;
2339}
2340
2341static int
2342hsw_emit_bb_start(struct drm_i915_gem_request *req,
2343 u64 offset, u32 len,
2344 unsigned int dispatch_flags)
2345{
2346 struct intel_ring *ring = req->ring;
2347 int ret;
2348
2349 ret = intel_ring_begin(req, 2);
2350 if (ret)
2351 return ret;
2352
2353 intel_ring_emit(ring,
2354 MI_BATCH_BUFFER_START |
2355 (dispatch_flags & I915_DISPATCH_SECURE ?
2356 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
2357 (dispatch_flags & I915_DISPATCH_RS ?
2358 MI_BATCH_RESOURCE_STREAMER : 0));
2359 /* bit0-7 is the length on GEN6+ */
2360 intel_ring_emit(ring, offset);
2361 intel_ring_advance(ring);
2362
2363 return 0;
2364}
2365
2366static int
2367gen6_emit_bb_start(struct drm_i915_gem_request *req,
2368 u64 offset, u32 len,
2369 unsigned int dispatch_flags)
2370{
2371 struct intel_ring *ring = req->ring;
2372 int ret;
2373
2374 ret = intel_ring_begin(req, 2);
2375 if (ret)
2376 return ret;
2377
2378 intel_ring_emit(ring,
2379 MI_BATCH_BUFFER_START |
2380 (dispatch_flags & I915_DISPATCH_SECURE ?
2381 0 : MI_BATCH_NON_SECURE_I965));
2382 /* bit0-7 is the length on GEN6+ */
2383 intel_ring_emit(ring, offset);
2384 intel_ring_advance(ring);
2385
2386 return 0;
2387}
2388
2389/* Blitter support (SandyBridge+) */
2390
2391static int gen6_ring_flush(struct drm_i915_gem_request *req, u32 mode)
2392{
2393 struct intel_ring *ring = req->ring;
2394 uint32_t cmd;
2395 int ret;
2396
2397 ret = intel_ring_begin(req, 4);
2398 if (ret)
2399 return ret;
2400
2401 cmd = MI_FLUSH_DW;
2402 if (INTEL_GEN(req->i915) >= 8)
2403 cmd += 1;
2404
2405 /* We always require a command barrier so that subsequent
2406 * commands, such as breadcrumb interrupts, are strictly ordered
2407 * wrt the contents of the write cache being flushed to memory
2408 * (and thus being coherent from the CPU).
2409 */
2410 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2411
2412 /*
2413 * Bspec vol 1c.3 - blitter engine command streamer:
2414 * "If ENABLED, all TLBs will be invalidated once the flush
2415 * operation is complete. This bit is only valid when the
2416 * Post-Sync Operation field is a value of 1h or 3h."
2417 */
2418 if (mode & EMIT_INVALIDATE)
2419 cmd |= MI_INVALIDATE_TLB;
2420 intel_ring_emit(ring, cmd);
2421 intel_ring_emit(ring,
2422 I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2423 if (INTEL_GEN(req->i915) >= 8) {
2424 intel_ring_emit(ring, 0); /* upper addr */
2425 intel_ring_emit(ring, 0); /* value */
2426 } else {
2427 intel_ring_emit(ring, 0);
2428 intel_ring_emit(ring, MI_NOOP);
2429 }
2430 intel_ring_advance(ring);
2431
2432 return 0;
2433}
2434
2435static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv,
2436 struct intel_engine_cs *engine)
2437{
2438 struct drm_i915_gem_object *obj;
2439 int ret, i;
2440
2441 if (!i915.semaphores)
2442 return;
2443
2444 if (INTEL_GEN(dev_priv) >= 8 && !dev_priv->semaphore) {
2445 struct i915_vma *vma;
2446
2447 obj = i915_gem_object_create(&dev_priv->drm, 4096);
2448 if (IS_ERR(obj))
2449 goto err;
2450
2451 vma = i915_vma_create(obj, &dev_priv->ggtt.base, NULL);
2452 if (IS_ERR(vma))
2453 goto err_obj;
2454
2455 ret = i915_gem_object_set_to_gtt_domain(obj, false);
2456 if (ret)
2457 goto err_obj;
2458
2459 ret = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH);
2460 if (ret)
2461 goto err_obj;
2462
2463 dev_priv->semaphore = vma;
2464 }
2465
2466 if (INTEL_GEN(dev_priv) >= 8) {
2467 u32 offset = i915_ggtt_offset(dev_priv->semaphore);
2468
2469 engine->semaphore.sync_to = gen8_ring_sync_to;
2470 engine->semaphore.signal = gen8_xcs_signal;
2471
2472 for (i = 0; i < I915_NUM_ENGINES; i++) {
2473 u32 ring_offset;
2474
2475 if (i != engine->id)
2476 ring_offset = offset + GEN8_SEMAPHORE_OFFSET(engine->id, i);
2477 else
2478 ring_offset = MI_SEMAPHORE_SYNC_INVALID;
2479
2480 engine->semaphore.signal_ggtt[i] = ring_offset;
2481 }
2482 } else if (INTEL_GEN(dev_priv) >= 6) {
2483 engine->semaphore.sync_to = gen6_ring_sync_to;
2484 engine->semaphore.signal = gen6_signal;
2485
2486 /*
2487 * The current semaphore is only applied on pre-gen8
2488 * platform. And there is no VCS2 ring on the pre-gen8
2489 * platform. So the semaphore between RCS and VCS2 is
2490 * initialized as INVALID. Gen8 will initialize the
2491 * sema between VCS2 and RCS later.
2492 */
2493 for (i = 0; i < GEN6_NUM_SEMAPHORES; i++) {
2494 static const struct {
2495 u32 wait_mbox;
2496 i915_reg_t mbox_reg;
2497 } sem_data[GEN6_NUM_SEMAPHORES][GEN6_NUM_SEMAPHORES] = {
2498 [RCS_HW] = {
2499 [VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RV, .mbox_reg = GEN6_VRSYNC },
2500 [BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RB, .mbox_reg = GEN6_BRSYNC },
2501 [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RVE, .mbox_reg = GEN6_VERSYNC },
2502 },
2503 [VCS_HW] = {
2504 [RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VR, .mbox_reg = GEN6_RVSYNC },
2505 [BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VB, .mbox_reg = GEN6_BVSYNC },
2506 [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VVE, .mbox_reg = GEN6_VEVSYNC },
2507 },
2508 [BCS_HW] = {
2509 [RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BR, .mbox_reg = GEN6_RBSYNC },
2510 [VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BV, .mbox_reg = GEN6_VBSYNC },
2511 [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BVE, .mbox_reg = GEN6_VEBSYNC },
2512 },
2513 [VECS_HW] = {
2514 [RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VER, .mbox_reg = GEN6_RVESYNC },
2515 [VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEV, .mbox_reg = GEN6_VVESYNC },
2516 [BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEB, .mbox_reg = GEN6_BVESYNC },
2517 },
2518 };
2519 u32 wait_mbox;
2520 i915_reg_t mbox_reg;
2521
2522 if (i == engine->hw_id) {
2523 wait_mbox = MI_SEMAPHORE_SYNC_INVALID;
2524 mbox_reg = GEN6_NOSYNC;
2525 } else {
2526 wait_mbox = sem_data[engine->hw_id][i].wait_mbox;
2527 mbox_reg = sem_data[engine->hw_id][i].mbox_reg;
2528 }
2529
2530 engine->semaphore.mbox.wait[i] = wait_mbox;
2531 engine->semaphore.mbox.signal[i] = mbox_reg;
2532 }
2533 }
2534
2535 return;
2536
2537err_obj:
2538 i915_gem_object_put(obj);
2539err:
2540 DRM_DEBUG_DRIVER("Failed to allocate space for semaphores, disabling\n");
2541 i915.semaphores = 0;
2542}
2543
2544static void intel_ring_init_irq(struct drm_i915_private *dev_priv,
2545 struct intel_engine_cs *engine)
2546{
2547 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << engine->irq_shift;
2548
2549 if (INTEL_GEN(dev_priv) >= 8) {
2550 engine->irq_enable = gen8_irq_enable;
2551 engine->irq_disable = gen8_irq_disable;
2552 engine->irq_seqno_barrier = gen6_seqno_barrier;
2553 } else if (INTEL_GEN(dev_priv) >= 6) {
2554 engine->irq_enable = gen6_irq_enable;
2555 engine->irq_disable = gen6_irq_disable;
2556 engine->irq_seqno_barrier = gen6_seqno_barrier;
2557 } else if (INTEL_GEN(dev_priv) >= 5) {
2558 engine->irq_enable = gen5_irq_enable;
2559 engine->irq_disable = gen5_irq_disable;
2560 engine->irq_seqno_barrier = gen5_seqno_barrier;
2561 } else if (INTEL_GEN(dev_priv) >= 3) {
2562 engine->irq_enable = i9xx_irq_enable;
2563 engine->irq_disable = i9xx_irq_disable;
2564 } else {
2565 engine->irq_enable = i8xx_irq_enable;
2566 engine->irq_disable = i8xx_irq_disable;
2567 }
2568}
2569
2570static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
2571 struct intel_engine_cs *engine)
2572{
2573 intel_ring_init_irq(dev_priv, engine);
2574 intel_ring_init_semaphores(dev_priv, engine);
2575
2576 engine->init_hw = init_ring_common;
2577 engine->reset_hw = reset_ring_common;
2578
2579 engine->emit_breadcrumb = i9xx_emit_breadcrumb;
2580 engine->emit_breadcrumb_sz = i9xx_emit_breadcrumb_sz;
2581 if (i915.semaphores) {
2582 int num_rings;
2583
2584 engine->emit_breadcrumb = gen6_sema_emit_breadcrumb;
2585
2586 num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask) - 1;
2587 if (INTEL_GEN(dev_priv) >= 8) {
2588 engine->emit_breadcrumb_sz += num_rings * 6;
2589 } else {
2590 engine->emit_breadcrumb_sz += num_rings * 3;
2591 if (num_rings & 1)
2592 engine->emit_breadcrumb_sz++;
2593 }
2594 }
2595 engine->submit_request = i9xx_submit_request;
2596
2597 if (INTEL_GEN(dev_priv) >= 8)
2598 engine->emit_bb_start = gen8_emit_bb_start;
2599 else if (INTEL_GEN(dev_priv) >= 6)
2600 engine->emit_bb_start = gen6_emit_bb_start;
2601 else if (INTEL_GEN(dev_priv) >= 4)
2602 engine->emit_bb_start = i965_emit_bb_start;
2603 else if (IS_I830(dev_priv) || IS_845G(dev_priv))
2604 engine->emit_bb_start = i830_emit_bb_start;
2605 else
2606 engine->emit_bb_start = i915_emit_bb_start;
2607}
2608
2609int intel_init_render_ring_buffer(struct intel_engine_cs *engine)
2610{
2611 struct drm_i915_private *dev_priv = engine->i915;
2612 int ret;
2613
2614 intel_ring_default_vfuncs(dev_priv, engine);
2615
2616 if (HAS_L3_DPF(dev_priv))
2617 engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
2618
2619 if (INTEL_GEN(dev_priv) >= 8) {
2620 engine->init_context = intel_rcs_ctx_init;
2621 engine->emit_breadcrumb = gen8_render_emit_breadcrumb;
2622 engine->emit_breadcrumb_sz = gen8_render_emit_breadcrumb_sz;
2623 engine->emit_flush = gen8_render_ring_flush;
2624 if (i915.semaphores) {
2625 int num_rings;
2626
2627 engine->semaphore.signal = gen8_rcs_signal;
2628
2629 num_rings =
2630 hweight32(INTEL_INFO(dev_priv)->ring_mask) - 1;
2631 engine->emit_breadcrumb_sz += num_rings * 6;
2632 }
2633 } else if (INTEL_GEN(dev_priv) >= 6) {
2634 engine->init_context = intel_rcs_ctx_init;
2635 engine->emit_flush = gen7_render_ring_flush;
2636 if (IS_GEN6(dev_priv))
2637 engine->emit_flush = gen6_render_ring_flush;
2638 } else if (IS_GEN5(dev_priv)) {
2639 engine->emit_flush = gen4_render_ring_flush;
2640 } else {
2641 if (INTEL_GEN(dev_priv) < 4)
2642 engine->emit_flush = gen2_render_ring_flush;
2643 else
2644 engine->emit_flush = gen4_render_ring_flush;
2645 engine->irq_enable_mask = I915_USER_INTERRUPT;
2646 }
2647
2648 if (IS_HASWELL(dev_priv))
2649 engine->emit_bb_start = hsw_emit_bb_start;
2650
2651 engine->init_hw = init_render_ring;
2652 engine->cleanup = render_ring_cleanup;
2653
2654 ret = intel_init_ring_buffer(engine);
2655 if (ret)
2656 return ret;
2657
2658 if (INTEL_GEN(dev_priv) >= 6) {
2659 ret = intel_engine_create_scratch(engine, 4096);
2660 if (ret)
2661 return ret;
2662 } else if (HAS_BROKEN_CS_TLB(dev_priv)) {
2663 ret = intel_engine_create_scratch(engine, I830_WA_SIZE);
2664 if (ret)
2665 return ret;
2666 }
2667
2668 return 0;
2669}
2670
2671int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine)
2672{
2673 struct drm_i915_private *dev_priv = engine->i915;
2674
2675 intel_ring_default_vfuncs(dev_priv, engine);
2676
2677 if (INTEL_GEN(dev_priv) >= 6) {
2678 /* gen6 bsd needs a special wa for tail updates */
2679 if (IS_GEN6(dev_priv))
2680 engine->submit_request = gen6_bsd_submit_request;
2681 engine->emit_flush = gen6_bsd_ring_flush;
2682 if (INTEL_GEN(dev_priv) < 8)
2683 engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2684 } else {
2685 engine->mmio_base = BSD_RING_BASE;
2686 engine->emit_flush = bsd_ring_flush;
2687 if (IS_GEN5(dev_priv))
2688 engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2689 else
2690 engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2691 }
2692
2693 return intel_init_ring_buffer(engine);
2694}
2695
2696/**
2697 * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
2698 */
2699int intel_init_bsd2_ring_buffer(struct intel_engine_cs *engine)
2700{
2701 struct drm_i915_private *dev_priv = engine->i915;
2702
2703 intel_ring_default_vfuncs(dev_priv, engine);
2704
2705 engine->emit_flush = gen6_bsd_ring_flush;
2706
2707 return intel_init_ring_buffer(engine);
2708}
2709
2710int intel_init_blt_ring_buffer(struct intel_engine_cs *engine)
2711{
2712 struct drm_i915_private *dev_priv = engine->i915;
2713
2714 intel_ring_default_vfuncs(dev_priv, engine);
2715
2716 engine->emit_flush = gen6_ring_flush;
2717 if (INTEL_GEN(dev_priv) < 8)
2718 engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2719
2720 return intel_init_ring_buffer(engine);
2721}
2722
2723int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine)
2724{
2725 struct drm_i915_private *dev_priv = engine->i915;
2726
2727 intel_ring_default_vfuncs(dev_priv, engine);
2728
2729 engine->emit_flush = gen6_ring_flush;
2730
2731 if (INTEL_GEN(dev_priv) < 8) {
2732 engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2733 engine->irq_enable = hsw_vebox_irq_enable;
2734 engine->irq_disable = hsw_vebox_irq_disable;
2735 }
2736
2737 return intel_init_ring_buffer(engine);
2738}