1/*
   2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3 * Copyright (c) 2007-2008 Intel Corporation
   4 *   Jesse Barnes <jesse.barnes@intel.com>
   5 *
   6 * Permission is hereby granted, free of charge, to any person obtaining a
   7 * copy of this software and associated documentation files (the "Software"),
   8 * to deal in the Software without restriction, including without limitation
   9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10 * and/or sell copies of the Software, and to permit persons to whom the
  11 * Software is furnished to do so, subject to the following conditions:
  12 *
  13 * The above copyright notice and this permission notice (including the next
  14 * paragraph) shall be included in all copies or substantial portions of the
  15 * Software.
  16 *
  17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23 * IN THE SOFTWARE.
  24 */
  25#ifndef __INTEL_DRV_H__
  26#define __INTEL_DRV_H__
  27
  28#include <linux/async.h>
  29#include <linux/i2c.h>
  30#include <linux/hdmi.h>
  31#include <drm/i915_drm.h>
  32#include "i915_drv.h"
  33#include <drm/drm_crtc.h>
  34#include <drm/drm_crtc_helper.h>
  35#include <drm/drm_fb_helper.h>
 
  36#include <drm/drm_dp_mst_helper.h>
  37#include <drm/drm_rect.h>
  38#include <drm/drm_atomic.h>
  39
  40/**
  41 * _wait_for - magic (register) wait macro
  42 *
  43 * Does the right thing for modeset paths when run under kdgb or similar atomic
  44 * contexts. Note that it's important that we check the condition again after
  45 * having timed out, since the timeout could be due to preemption or similar and
  46 * we've never had a chance to check the condition before the timeout.
 
 
 
 
  47 */
  48#define _wait_for(COND, MS, W) ({ \
  49	unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1;	\
  50	int ret__ = 0;							\
  51	while (!(COND)) {						\
  52		if (time_after(jiffies, timeout__)) {			\
  53			if (!(COND))					\
  54				ret__ = -ETIMEDOUT;			\
 
 
 
 
  55			break;						\
  56		}							\
  57		if ((W) && drm_can_sleep()) {				\
  58			usleep_range((W)*1000, (W)*2000);		\
  59		} else {						\
  60			cpu_relax();					\
  61		}							\
  62	}								\
  63	ret__;								\
  64})
  65
  66#define wait_for(COND, MS) _wait_for(COND, MS, 1)
  67#define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
  68#define wait_for_atomic_us(COND, US) _wait_for((COND), \
  69					       DIV_ROUND_UP((US), 1000), 0)
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  70
  71#define KHz(x) (1000 * (x))
  72#define MHz(x) KHz(1000 * (x))
  73
  74/*
  75 * Display related stuff
  76 */
  77
  78/* store information about an Ixxx DVO */
  79/* The i830->i865 use multiple DVOs with multiple i2cs */
  80/* the i915, i945 have a single sDVO i2c bus - which is different */
  81#define MAX_OUTPUTS 6
  82/* maximum connectors per crtcs in the mode set */
  83
  84/* Maximum cursor sizes */
  85#define GEN2_CURSOR_WIDTH 64
  86#define GEN2_CURSOR_HEIGHT 64
  87#define MAX_CURSOR_WIDTH 256
  88#define MAX_CURSOR_HEIGHT 256
  89
  90#define INTEL_I2C_BUS_DVO 1
  91#define INTEL_I2C_BUS_SDVO 2
  92
  93/* these are outputs from the chip - integrated only
  94   external chips are via DVO or SDVO output */
  95enum intel_output_type {
  96	INTEL_OUTPUT_UNUSED = 0,
  97	INTEL_OUTPUT_ANALOG = 1,
  98	INTEL_OUTPUT_DVO = 2,
  99	INTEL_OUTPUT_SDVO = 3,
 100	INTEL_OUTPUT_LVDS = 4,
 101	INTEL_OUTPUT_TVOUT = 5,
 102	INTEL_OUTPUT_HDMI = 6,
 103	INTEL_OUTPUT_DISPLAYPORT = 7,
 104	INTEL_OUTPUT_EDP = 8,
 105	INTEL_OUTPUT_DSI = 9,
 106	INTEL_OUTPUT_UNKNOWN = 10,
 107	INTEL_OUTPUT_DP_MST = 11,
 108};
 109
 110#define INTEL_DVO_CHIP_NONE 0
 111#define INTEL_DVO_CHIP_LVDS 1
 112#define INTEL_DVO_CHIP_TMDS 2
 113#define INTEL_DVO_CHIP_TVOUT 4
 114
 115#define INTEL_DSI_VIDEO_MODE	0
 116#define INTEL_DSI_COMMAND_MODE	1
 117
 118struct intel_framebuffer {
 119	struct drm_framebuffer base;
 120	struct drm_i915_gem_object *obj;
 
 
 
 
 
 
 
 
 
 
 
 121};
 122
 123struct intel_fbdev {
 124	struct drm_fb_helper helper;
 125	struct intel_framebuffer *fb;
 
 
 126	int preferred_bpp;
 127};
 128
 129struct intel_encoder {
 130	struct drm_encoder base;
 131
 132	enum intel_output_type type;
 
 133	unsigned int cloneable;
 134	void (*hot_plug)(struct intel_encoder *);
 135	bool (*compute_config)(struct intel_encoder *,
 136			       struct intel_crtc_state *);
 137	void (*pre_pll_enable)(struct intel_encoder *);
 138	void (*pre_enable)(struct intel_encoder *);
 139	void (*enable)(struct intel_encoder *);
 140	void (*mode_set)(struct intel_encoder *intel_encoder);
 141	void (*disable)(struct intel_encoder *);
 142	void (*post_disable)(struct intel_encoder *);
 143	void (*post_pll_disable)(struct intel_encoder *);
 
 
 
 
 
 
 
 
 
 
 
 
 144	/* Read out the current hw state of this connector, returning true if
 145	 * the encoder is active. If the encoder is enabled it also set the pipe
 146	 * it is connected to in the pipe parameter. */
 147	bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 148	/* Reconstructs the equivalent mode flags for the current hardware
 149	 * state. This must be called _after_ display->get_pipe_config has
 150	 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 151	 * be set correctly before calling this function. */
 152	void (*get_config)(struct intel_encoder *,
 153			   struct intel_crtc_state *pipe_config);
 154	/*
 155	 * Called during system suspend after all pending requests for the
 156	 * encoder are flushed (for example for DP AUX transactions) and
 157	 * device interrupts are disabled.
 158	 */
 159	void (*suspend)(struct intel_encoder *);
 160	int crtc_mask;
 161	enum hpd_pin hpd_pin;
 
 
 162};
 163
 164struct intel_panel {
 165	struct drm_display_mode *fixed_mode;
 166	struct drm_display_mode *downclock_mode;
 167	int fitting_mode;
 168
 169	/* backlight */
 170	struct {
 171		bool present;
 172		u32 level;
 173		u32 min;
 174		u32 max;
 175		bool enabled;
 176		bool combination_mode;	/* gen 2/4 only */
 177		bool active_low_pwm;
 
 178
 179		/* PWM chip */
 180		bool util_pin_active_low;	/* bxt+ */
 181		u8 controller;		/* bxt+ only */
 182		struct pwm_device *pwm;
 183
 184		struct backlight_device *device;
 185
 186		/* Connector and platform specific backlight functions */
 187		int (*setup)(struct intel_connector *connector, enum pipe pipe);
 188		uint32_t (*get)(struct intel_connector *connector);
 189		void (*set)(struct intel_connector *connector, uint32_t level);
 190		void (*disable)(struct intel_connector *connector);
 191		void (*enable)(struct intel_connector *connector);
 192		uint32_t (*hz_to_pwm)(struct intel_connector *connector,
 193				      uint32_t hz);
 194		void (*power)(struct intel_connector *, bool enable);
 195	} backlight;
 196};
 197
 198struct intel_connector {
 199	struct drm_connector base;
 200	/*
 201	 * The fixed encoder this connector is connected to.
 202	 */
 203	struct intel_encoder *encoder;
 204
 
 
 
 205	/* Reads out the current hw, returning true if the connector is enabled
 206	 * and active (i.e. dpms ON state). */
 207	bool (*get_hw_state)(struct intel_connector *);
 208
 209	/*
 210	 * Removes all interfaces through which the connector is accessible
 211	 * - like sysfs, debugfs entries -, so that no new operations can be
 212	 * started on the connector. Also makes sure all currently pending
 213	 * operations finish before returing.
 214	 */
 215	void (*unregister)(struct intel_connector *);
 216
 217	/* Panel info for eDP and LVDS */
 218	struct intel_panel panel;
 219
 220	/* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 221	struct edid *edid;
 222	struct edid *detect_edid;
 223
 224	/* since POLL and HPD connectors may use the same HPD line keep the native
 225	   state of connector->polled in case hotplug storm detection changes it */
 226	u8 polled;
 227
 228	void *port; /* store this opaque as its illegal to dereference it */
 229
 230	struct intel_dp *mst_port;
 231};
 232
 233typedef struct dpll {
 234	/* given values */
 235	int n;
 236	int m1, m2;
 237	int p1, p2;
 238	/* derived values */
 239	int	dot;
 240	int	vco;
 241	int	m;
 242	int	p;
 243} intel_clock_t;
 244
 245struct intel_atomic_state {
 246	struct drm_atomic_state base;
 247
 248	unsigned int cdclk;
 249
 250	/*
 251	 * Calculated device cdclk, can be different from cdclk
 252	 * only when all crtc's are DPMS off.
 253	 */
 254	unsigned int dev_cdclk;
 255
 256	bool dpll_set, modeset;
 257
 
 
 
 
 
 
 
 
 
 
 258	unsigned int active_crtcs;
 259	unsigned int min_pixclk[I915_MAX_PIPES];
 260
 
 
 
 261	struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
 262	struct intel_wm_config wm_config;
 
 
 
 
 
 
 
 
 
 
 
 
 263};
 264
 265struct intel_plane_state {
 266	struct drm_plane_state base;
 267	struct drm_rect src;
 268	struct drm_rect dst;
 269	struct drm_rect clip;
 270	bool visible;
 
 
 
 
 
 
 
 
 
 271
 272	/*
 273	 * scaler_id
 274	 *    = -1 : not using a scaler
 275	 *    >=  0 : using a scalers
 276	 *
 277	 * plane requiring a scaler:
 278	 *   - During check_plane, its bit is set in
 279	 *     crtc_state->scaler_state.scaler_users by calling helper function
 280	 *     update_scaler_plane.
 281	 *   - scaler_id indicates the scaler it got assigned.
 282	 *
 283	 * plane doesn't require a scaler:
 284	 *   - this can happen when scaling is no more required or plane simply
 285	 *     got disabled.
 286	 *   - During check_plane, corresponding bit is reset in
 287	 *     crtc_state->scaler_state.scaler_users by calling helper function
 288	 *     update_scaler_plane.
 289	 */
 290	int scaler_id;
 291
 292	struct drm_intel_sprite_colorkey ckey;
 293
 294	/* async flip related structures */
 295	struct drm_i915_gem_request *wait_req;
 296};
 297
 298struct intel_initial_plane_config {
 299	struct intel_framebuffer *fb;
 300	unsigned int tiling;
 301	int size;
 302	u32 base;
 303};
 304
 305#define SKL_MIN_SRC_W 8
 306#define SKL_MAX_SRC_W 4096
 307#define SKL_MIN_SRC_H 8
 308#define SKL_MAX_SRC_H 4096
 309#define SKL_MIN_DST_W 8
 310#define SKL_MAX_DST_W 4096
 311#define SKL_MIN_DST_H 8
 312#define SKL_MAX_DST_H 4096
 313
 314struct intel_scaler {
 315	int in_use;
 316	uint32_t mode;
 317};
 318
 319struct intel_crtc_scaler_state {
 320#define SKL_NUM_SCALERS 2
 321	struct intel_scaler scalers[SKL_NUM_SCALERS];
 322
 323	/*
 324	 * scaler_users: keeps track of users requesting scalers on this crtc.
 325	 *
 326	 *     If a bit is set, a user is using a scaler.
 327	 *     Here user can be a plane or crtc as defined below:
 328	 *       bits 0-30 - plane (bit position is index from drm_plane_index)
 329	 *       bit 31    - crtc
 330	 *
 331	 * Instead of creating a new index to cover planes and crtc, using
 332	 * existing drm_plane_index for planes which is well less than 31
 333	 * planes and bit 31 for crtc. This should be fine to cover all
 334	 * our platforms.
 335	 *
 336	 * intel_atomic_setup_scalers will setup available scalers to users
 337	 * requesting scalers. It will gracefully fail if request exceeds
 338	 * avilability.
 339	 */
 340#define SKL_CRTC_INDEX 31
 341	unsigned scaler_users;
 342
 343	/* scaler used by crtc for panel fitting purpose */
 344	int scaler_id;
 345};
 346
 347/* drm_mode->private_flags */
 348#define I915_MODE_FLAG_INHERITED 1
 349
 350struct intel_pipe_wm {
 351	struct intel_wm_level wm[5];
 
 352	uint32_t linetime;
 353	bool fbc_wm_enabled;
 354	bool pipe_enabled;
 355	bool sprites_enabled;
 356	bool sprites_scaled;
 357};
 358
 359struct skl_pipe_wm {
 360	struct skl_wm_level wm[8];
 361	struct skl_wm_level trans_wm;
 
 
 
 
 362	uint32_t linetime;
 363};
 364
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 365struct intel_crtc_state {
 366	struct drm_crtc_state base;
 367
 368	/**
 369	 * quirks - bitfield with hw state readout quirks
 370	 *
 371	 * For various reasons the hw state readout code might not be able to
 372	 * completely faithfully read out the current state. These cases are
 373	 * tracked with quirk flags so that fastboot and state checker can act
 374	 * accordingly.
 375	 */
 376#define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS	(1<<0) /* unreliable sync mode.flags */
 377	unsigned long quirks;
 378
 
 379	bool update_pipe; /* can a fast modeset be performed? */
 380	bool disable_cxsr;
 381	bool wm_changed; /* watermarks are updated */
 382	bool fb_changed; /* fb on any of the planes is changed */
 383
 384	/* Pipe source size (ie. panel fitter input size)
 385	 * All planes will be positioned inside this space,
 386	 * and get clipped at the edges. */
 387	int pipe_src_w, pipe_src_h;
 388
 389	/* Whether to set up the PCH/FDI. Note that we never allow sharing
 390	 * between pch encoders and cpu encoders. */
 391	bool has_pch_encoder;
 392
 393	/* Are we sending infoframes on the attached port */
 394	bool has_infoframe;
 395
 396	/* CPU Transcoder for the pipe. Currently this can only differ from the
 397	 * pipe on Haswell (where we have a special eDP transcoder). */
 
 398	enum transcoder cpu_transcoder;
 399
 400	/*
 401	 * Use reduced/limited/broadcast rbg range, compressing from the full
 402	 * range fed into the crtcs.
 403	 */
 404	bool limited_color_range;
 405
 406	/* DP has a bunch of special case unfortunately, so mark the pipe
 407	 * accordingly. */
 408	bool has_dp_encoder;
 409
 410	/* DSI has special cases */
 411	bool has_dsi_encoder;
 412
 413	/* Whether we should send NULL infoframes. Required for audio. */
 414	bool has_hdmi_sink;
 415
 416	/* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 417	 * has_dp_encoder is set. */
 418	bool has_audio;
 419
 420	/*
 421	 * Enable dithering, used when the selected pipe bpp doesn't match the
 422	 * plane bpp.
 423	 */
 424	bool dither;
 425
 426	/* Controls for the clock computation, to override various stages. */
 427	bool clock_set;
 428
 429	/* SDVO TV has a bunch of special case. To make multifunction encoders
 430	 * work correctly, we need to track this at runtime.*/
 431	bool sdvo_tv_clock;
 432
 433	/*
 434	 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 435	 * required. This is set in the 2nd loop of calling encoder's
 436	 * ->compute_config if the first pick doesn't work out.
 437	 */
 438	bool bw_constrained;
 439
 440	/* Settings for the intel dpll used on pretty much everything but
 441	 * haswell. */
 442	struct dpll dpll;
 443
 444	/* Selected dpll when shared or DPLL_ID_PRIVATE. */
 445	enum intel_dpll_id shared_dpll;
 446
 447	/*
 448	 * - PORT_CLK_SEL for DDI ports on HSW/BDW.
 449	 * - enum skl_dpll on SKL
 450	 */
 451	uint32_t ddi_pll_sel;
 452
 453	/* Actual register state of the dpll, for shared dpll cross-checking. */
 454	struct intel_dpll_hw_state dpll_hw_state;
 455
 
 
 
 
 
 456	int pipe_bpp;
 457	struct intel_link_m_n dp_m_n;
 458
 459	/* m2_n2 for eDP downclock */
 460	struct intel_link_m_n dp_m2_n2;
 461	bool has_drrs;
 462
 463	/*
 464	 * Frequence the dpll for the port should run at. Differs from the
 465	 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 466	 * already multiplied by pixel_multiplier.
 467	 */
 468	int port_clock;
 469
 470	/* Used by SDVO (and if we ever fix it, HDMI). */
 471	unsigned pixel_multiplier;
 472
 473	uint8_t lane_count;
 474
 
 
 
 
 
 
 475	/* Panel fitter controls for gen2-gen4 + VLV */
 476	struct {
 477		u32 control;
 478		u32 pgm_ratios;
 479		u32 lvds_border_bits;
 480	} gmch_pfit;
 481
 482	/* Panel fitter placement and size for Ironlake+ */
 483	struct {
 484		u32 pos;
 485		u32 size;
 486		bool enabled;
 487		bool force_thru;
 488	} pch_pfit;
 489
 490	/* FDI configuration, only valid if has_pch_encoder is set. */
 491	int fdi_lanes;
 492	struct intel_link_m_n fdi_m_n;
 493
 494	bool ips_enabled;
 495
 496	bool enable_fbc;
 497
 498	bool double_wide;
 499
 500	bool dp_encoder_is_mst;
 501	int pbn;
 502
 503	struct intel_crtc_scaler_state scaler_state;
 504
 505	/* w/a for waiting 2 vblanks during crtc enable */
 506	enum pipe hsw_workaround_pipe;
 507
 508	/* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
 509	bool disable_lp_wm;
 510
 511	struct {
 512		/*
 513		 * optimal watermarks, programmed post-vblank when this state
 514		 * is committed
 515		 */
 516		union {
 517			struct intel_pipe_wm ilk;
 518			struct skl_pipe_wm skl;
 519		} optimal;
 520	} wm;
 521};
 522
 523struct vlv_wm_state {
 524	struct vlv_pipe_wm wm[3];
 525	struct vlv_sr_wm sr[3];
 526	uint8_t num_active_planes;
 527	uint8_t num_levels;
 528	uint8_t level;
 529	bool cxsr;
 530};
 531
 532struct intel_mmio_flip {
 533	struct work_struct work;
 534	struct drm_i915_private *i915;
 535	struct drm_i915_gem_request *req;
 536	struct intel_crtc *crtc;
 537	unsigned int rotation;
 538};
 539
 540/*
 541 * Tracking of operations that need to be performed at the beginning/end of an
 542 * atomic commit, outside the atomic section where interrupts are disabled.
 543 * These are generally operations that grab mutexes or might otherwise sleep
 544 * and thus can't be run with interrupts disabled.
 545 */
 546struct intel_crtc_atomic_commit {
 547	/* Sleepable operations to perform before commit */
 548
 549	/* Sleepable operations to perform after commit */
 550	unsigned fb_bits;
 551	bool post_enable_primary;
 552
 553	/* Sleepable operations to perform before and after commit */
 554	bool update_fbc;
 555};
 556
 557struct intel_crtc {
 558	struct drm_crtc base;
 559	enum pipe pipe;
 560	enum plane plane;
 561	u8 lut_r[256], lut_g[256], lut_b[256];
 562	/*
 563	 * Whether the crtc and the connected output pipeline is active. Implies
 564	 * that crtc->enabled is set, i.e. the current mode configuration has
 565	 * some outputs connected to this crtc.
 566	 */
 567	bool active;
 568	unsigned long enabled_power_domains;
 569	bool lowfreq_avail;
 570	struct intel_overlay *overlay;
 571	struct intel_unpin_work *unpin_work;
 572
 573	atomic_t unpin_work_count;
 574
 575	/* Display surface base address adjustement for pageflips. Note that on
 576	 * gen4+ this only adjusts up to a tile, offsets within a tile are
 577	 * handled in the hw itself (with the TILEOFF register). */
 578	u32 dspaddr_offset;
 579	int adjusted_x;
 580	int adjusted_y;
 581
 582	uint32_t cursor_addr;
 583	uint32_t cursor_cntl;
 584	uint32_t cursor_size;
 585	uint32_t cursor_base;
 586
 587	struct intel_crtc_state *config;
 588
 589	/* reset counter value when the last flip was submitted */
 590	unsigned int reset_counter;
 591
 592	/* Access to these should be protected by dev_priv->irq_lock. */
 593	bool cpu_fifo_underrun_disabled;
 594	bool pch_fifo_underrun_disabled;
 595
 596	/* per-pipe watermark state */
 597	struct {
 598		/* watermarks currently being used  */
 599		union {
 600			struct intel_pipe_wm ilk;
 601			struct skl_pipe_wm skl;
 602		} active;
 
 603		/* allow CxSR on this pipe */
 604		bool cxsr_allowed;
 605	} wm;
 606
 607	int scanline_offset;
 608
 609	struct {
 610		unsigned start_vbl_count;
 611		ktime_t start_vbl_time;
 612		int min_vbl, max_vbl;
 613		int scanline_start;
 614	} debug;
 615
 616	struct intel_crtc_atomic_commit atomic;
 617
 618	/* scalers available on this crtc */
 619	int num_scalers;
 620
 621	struct vlv_wm_state wm_state;
 622};
 623
 624struct intel_plane_wm_parameters {
 625	uint32_t horiz_pixels;
 626	uint32_t vert_pixels;
 627	/*
 628	 *   For packed pixel formats:
 629	 *     bytes_per_pixel - holds bytes per pixel
 630	 *   For planar pixel formats:
 631	 *     bytes_per_pixel - holds bytes per pixel for uv-plane
 632	 *     y_bytes_per_pixel - holds bytes per pixel for y-plane
 633	 */
 634	uint8_t bytes_per_pixel;
 635	uint8_t y_bytes_per_pixel;
 636	bool enabled;
 637	bool scaled;
 638	u64 tiling;
 639	unsigned int rotation;
 640	uint16_t fifo_size;
 641};
 642
 643struct intel_plane {
 644	struct drm_plane base;
 645	int plane;
 646	enum pipe pipe;
 647	bool can_scale;
 648	int max_downscale;
 649	uint32_t frontbuffer_bit;
 650
 651	/* Since we need to change the watermarks before/after
 652	 * enabling/disabling the planes, we need to store the parameters here
 653	 * as the other pieces of the struct may not reflect the values we want
 654	 * for the watermark calculations. Currently only Haswell uses this.
 655	 */
 656	struct intel_plane_wm_parameters wm;
 657
 658	/*
 659	 * NOTE: Do not place new plane state fields here (e.g., when adding
 660	 * new plane properties).  New runtime state should now be placed in
 661	 * the intel_plane_state structure and accessed via plane_state.
 662	 */
 663
 664	void (*update_plane)(struct drm_plane *plane,
 665			     const struct intel_crtc_state *crtc_state,
 666			     const struct intel_plane_state *plane_state);
 667	void (*disable_plane)(struct drm_plane *plane,
 668			      struct drm_crtc *crtc);
 669	int (*check_plane)(struct drm_plane *plane,
 670			   struct intel_crtc_state *crtc_state,
 671			   struct intel_plane_state *state);
 672};
 673
 674struct intel_watermark_params {
 675	unsigned long fifo_size;
 676	unsigned long max_wm;
 677	unsigned long default_wm;
 678	unsigned long guard_size;
 679	unsigned long cacheline_size;
 680};
 681
 682struct cxsr_latency {
 683	int is_desktop;
 684	int is_ddr3;
 685	unsigned long fsb_freq;
 686	unsigned long mem_freq;
 687	unsigned long display_sr;
 688	unsigned long display_hpll_disable;
 689	unsigned long cursor_sr;
 690	unsigned long cursor_hpll_disable;
 691};
 692
 693#define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
 694#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 695#define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
 696#define to_intel_connector(x) container_of(x, struct intel_connector, base)
 697#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 698#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 699#define to_intel_plane(x) container_of(x, struct intel_plane, base)
 700#define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
 701#define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
 702
 703struct intel_hdmi {
 704	i915_reg_t hdmi_reg;
 705	int ddc_bus;
 
 
 
 
 706	bool limited_color_range;
 707	bool color_range_auto;
 708	bool has_hdmi_sink;
 709	bool has_audio;
 710	enum hdmi_force_audio force_audio;
 711	bool rgb_quant_range_selectable;
 712	enum hdmi_picture_aspect aspect_ratio;
 713	struct intel_connector *attached_connector;
 714	void (*write_infoframe)(struct drm_encoder *encoder,
 715				enum hdmi_infoframe_type type,
 716				const void *frame, ssize_t len);
 717	void (*set_infoframes)(struct drm_encoder *encoder,
 718			       bool enable,
 719			       const struct drm_display_mode *adjusted_mode);
 720	bool (*infoframe_enabled)(struct drm_encoder *encoder,
 721				  const struct intel_crtc_state *pipe_config);
 722};
 723
 724struct intel_dp_mst_encoder;
 725#define DP_MAX_DOWNSTREAM_PORTS		0x10
 726
 727/*
 728 * enum link_m_n_set:
 729 *	When platform provides two set of M_N registers for dp, we can
 730 *	program them and switch between them incase of DRRS.
 731 *	But When only one such register is provided, we have to program the
 732 *	required divider value on that registers itself based on the DRRS state.
 733 *
 734 * M1_N1	: Program dp_m_n on M1_N1 registers
 735 *			  dp_m2_n2 on M2_N2 registers (If supported)
 736 *
 737 * M2_N2	: Program dp_m2_n2 on M1_N1 registers
 738 *			  M2_N2 registers are not supported
 739 */
 740
 741enum link_m_n_set {
 742	/* Sets the m1_n1 and m2_n2 */
 743	M1_N1 = 0,
 744	M2_N2
 745};
 746
 
 
 
 
 
 
 
 
 747struct intel_dp {
 748	i915_reg_t output_reg;
 749	i915_reg_t aux_ch_ctl_reg;
 750	i915_reg_t aux_ch_data_reg[5];
 751	uint32_t DP;
 752	int link_rate;
 753	uint8_t lane_count;
 
 
 754	bool has_audio;
 
 
 755	enum hdmi_force_audio force_audio;
 756	bool limited_color_range;
 757	bool color_range_auto;
 758	uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 759	uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 760	uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 
 761	/* sink rates as reported by DP_SUPPORTED_LINK_RATES */
 762	uint8_t num_sink_rates;
 763	int sink_rates[DP_MAX_SUPPORTED_RATES];
 
 
 764	struct drm_dp_aux aux;
 765	uint8_t train_set[4];
 766	int panel_power_up_delay;
 767	int panel_power_down_delay;
 768	int panel_power_cycle_delay;
 769	int backlight_on_delay;
 770	int backlight_off_delay;
 771	struct delayed_work panel_vdd_work;
 772	bool want_panel_vdd;
 773	unsigned long last_power_on;
 774	unsigned long last_backlight_off;
 775	ktime_t panel_power_off_time;
 776
 777	struct notifier_block edp_notifier;
 778
 779	/*
 780	 * Pipe whose power sequencer is currently locked into
 781	 * this port. Only relevant on VLV/CHV.
 782	 */
 783	enum pipe pps_pipe;
 
 
 
 
 
 784	struct edp_power_seq pps_delays;
 785
 786	bool can_mst; /* this port supports mst */
 787	bool is_mst;
 788	int active_mst_links;
 789	/* connector directly attached - won't be use for modeset in mst world */
 790	struct intel_connector *attached_connector;
 791
 792	/* mst connector list */
 793	struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
 794	struct drm_dp_mst_topology_mgr mst_mgr;
 795
 796	uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
 797	/*
 798	 * This function returns the value we have to program the AUX_CTL
 799	 * register with to kick off an AUX transaction.
 800	 */
 801	uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
 802				     bool has_aux_irq,
 803				     int send_bytes,
 804				     uint32_t aux_clock_divider);
 805
 806	/* This is called before a link training is starterd */
 807	void (*prepare_link_retrain)(struct intel_dp *intel_dp);
 808
 809	bool train_set_valid;
 810
 811	/* Displayport compliance testing */
 812	unsigned long compliance_test_type;
 813	unsigned long compliance_test_data;
 814	bool compliance_test_active;
 815};
 816
 
 
 
 
 
 
 817struct intel_digital_port {
 818	struct intel_encoder base;
 819	enum port port;
 820	u32 saved_port_bits;
 821	struct intel_dp dp;
 822	struct intel_hdmi hdmi;
 
 823	enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
 824	bool release_cl2_override;
 825	uint8_t max_lanes;
 826	/* for communication with audio component; protected by av_mutex */
 827	const struct drm_connector *audio_connector;
 828};
 829
 830struct intel_dp_mst_encoder {
 831	struct intel_encoder base;
 832	enum pipe pipe;
 833	struct intel_digital_port *primary;
 834	void *port; /* store this opaque as its illegal to dereference it */
 835};
 836
 837static inline enum dpio_channel
 838vlv_dport_to_channel(struct intel_digital_port *dport)
 839{
 840	switch (dport->port) {
 841	case PORT_B:
 842	case PORT_D:
 843		return DPIO_CH0;
 844	case PORT_C:
 845		return DPIO_CH1;
 846	default:
 847		BUG();
 848	}
 849}
 850
 851static inline enum dpio_phy
 852vlv_dport_to_phy(struct intel_digital_port *dport)
 853{
 854	switch (dport->port) {
 855	case PORT_B:
 856	case PORT_C:
 857		return DPIO_PHY0;
 858	case PORT_D:
 859		return DPIO_PHY1;
 860	default:
 861		BUG();
 862	}
 863}
 864
 865static inline enum dpio_channel
 866vlv_pipe_to_channel(enum pipe pipe)
 867{
 868	switch (pipe) {
 869	case PIPE_A:
 870	case PIPE_C:
 871		return DPIO_CH0;
 872	case PIPE_B:
 873		return DPIO_CH1;
 874	default:
 875		BUG();
 876	}
 877}
 878
 879static inline struct drm_crtc *
 880intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
 881{
 882	struct drm_i915_private *dev_priv = dev->dev_private;
 883	return dev_priv->pipe_to_crtc_mapping[pipe];
 884}
 885
 886static inline struct drm_crtc *
 887intel_get_crtc_for_plane(struct drm_device *dev, int plane)
 888{
 889	struct drm_i915_private *dev_priv = dev->dev_private;
 890	return dev_priv->plane_to_crtc_mapping[plane];
 891}
 892
 893struct intel_unpin_work {
 894	struct work_struct work;
 
 
 895	struct drm_crtc *crtc;
 
 896	struct drm_framebuffer *old_fb;
 897	struct drm_i915_gem_object *pending_flip_obj;
 898	struct drm_pending_vblank_event *event;
 899	atomic_t pending;
 900#define INTEL_FLIP_INACTIVE	0
 901#define INTEL_FLIP_PENDING	1
 902#define INTEL_FLIP_COMPLETE	2
 903	u32 flip_count;
 904	u32 gtt_offset;
 905	struct drm_i915_gem_request *flip_queued_req;
 906	u32 flip_queued_vblank;
 907	u32 flip_ready_vblank;
 908	bool enable_stall_check;
 909};
 910
 911struct intel_load_detect_pipe {
 912	struct drm_atomic_state *restore_state;
 913};
 914
 915static inline struct intel_encoder *
 916intel_attached_encoder(struct drm_connector *connector)
 917{
 918	return to_intel_connector(connector)->encoder;
 919}
 920
 921static inline struct intel_digital_port *
 922enc_to_dig_port(struct drm_encoder *encoder)
 923{
 924	return container_of(encoder, struct intel_digital_port, base.base);
 925}
 926
 927static inline struct intel_dp_mst_encoder *
 928enc_to_mst(struct drm_encoder *encoder)
 929{
 930	return container_of(encoder, struct intel_dp_mst_encoder, base.base);
 931}
 932
 933static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
 934{
 935	return &enc_to_dig_port(encoder)->dp;
 936}
 937
 938static inline struct intel_digital_port *
 939dp_to_dig_port(struct intel_dp *intel_dp)
 940{
 941	return container_of(intel_dp, struct intel_digital_port, dp);
 942}
 943
 944static inline struct intel_digital_port *
 945hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
 946{
 947	return container_of(intel_hdmi, struct intel_digital_port, hdmi);
 948}
 949
 950/*
 951 * Returns the number of planes for this pipe, ie the number of sprites + 1
 952 * (primary plane). This doesn't count the cursor plane then.
 953 */
 954static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
 955{
 956	return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
 957}
 958
 959/* intel_fifo_underrun.c */
 960bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
 961					   enum pipe pipe, bool enable);
 962bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
 963					   enum transcoder pch_transcoder,
 964					   bool enable);
 965void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
 966					 enum pipe pipe);
 967void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
 968					 enum transcoder pch_transcoder);
 969void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
 970void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
 971
 972/* i915_irq.c */
 973void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 974void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 
 
 
 975void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 976void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 977void gen6_reset_rps_interrupts(struct drm_device *dev);
 978void gen6_enable_rps_interrupts(struct drm_device *dev);
 979void gen6_disable_rps_interrupts(struct drm_device *dev);
 980u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
 981void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
 982void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
 983static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
 984{
 985	/*
 986	 * We only use drm_irq_uninstall() at unload and VT switch, so
 987	 * this is the only thing we need to check.
 988	 */
 989	return dev_priv->pm.irqs_enabled;
 990}
 991
 992int intel_get_crtc_scanline(struct intel_crtc *crtc);
 993void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
 994				     unsigned int pipe_mask);
 995void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
 996				     unsigned int pipe_mask);
 
 
 
 997
 998/* intel_crt.c */
 999void intel_crt_init(struct drm_device *dev);
1000
1001
1002/* intel_ddi.c */
1003void intel_ddi_clk_select(struct intel_encoder *encoder,
1004			  const struct intel_crtc_state *pipe_config);
1005void intel_prepare_ddi_buffer(struct intel_encoder *encoder);
 
 
 
1006void hsw_fdi_link_train(struct drm_crtc *crtc);
1007void intel_ddi_init(struct drm_device *dev, enum port port);
1008enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
1009bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1010void intel_ddi_pll_init(struct drm_device *dev);
1011void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
1012void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1013				       enum transcoder cpu_transcoder);
1014void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
1015void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
1016bool intel_ddi_pll_select(struct intel_crtc *crtc,
1017			  struct intel_crtc_state *crtc_state);
1018void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
1019void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1020bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1021void intel_ddi_fdi_disable(struct drm_crtc *crtc);
1022void intel_ddi_get_config(struct intel_encoder *encoder,
1023			  struct intel_crtc_state *pipe_config);
1024struct intel_encoder *
1025intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1026
1027void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
1028void intel_ddi_clock_get(struct intel_encoder *encoder,
1029			 struct intel_crtc_state *pipe_config);
1030void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
1031uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1032
1033/* intel_frontbuffer.c */
1034void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
1035			     enum fb_op_origin origin);
1036void intel_frontbuffer_flip_prepare(struct drm_device *dev,
1037				    unsigned frontbuffer_bits);
1038void intel_frontbuffer_flip_complete(struct drm_device *dev,
1039				     unsigned frontbuffer_bits);
1040void intel_frontbuffer_flip(struct drm_device *dev,
1041			    unsigned frontbuffer_bits);
1042unsigned int intel_fb_align_height(struct drm_device *dev,
1043				   unsigned int height,
1044				   uint32_t pixel_format,
1045				   uint64_t fb_format_modifier);
1046void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire,
1047			enum fb_op_origin origin);
1048u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
1049			      uint64_t fb_modifier, uint32_t pixel_format);
1050
1051/* intel_audio.c */
1052void intel_init_audio(struct drm_device *dev);
1053void intel_audio_codec_enable(struct intel_encoder *encoder);
 
 
1054void intel_audio_codec_disable(struct intel_encoder *encoder);
1055void i915_audio_component_init(struct drm_i915_private *dev_priv);
1056void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1057
1058/* intel_display.c */
 
 
 
 
 
 
 
1059extern const struct drm_plane_funcs intel_plane_funcs;
 
 
 
 
 
 
 
1060bool intel_has_pending_fb_unpin(struct drm_device *dev);
1061int intel_pch_rawclk(struct drm_device *dev);
1062int intel_hrawclk(struct drm_device *dev);
1063void intel_mark_busy(struct drm_device *dev);
1064void intel_mark_idle(struct drm_device *dev);
1065void intel_crtc_restore_mode(struct drm_crtc *crtc);
1066int intel_display_suspend(struct drm_device *dev);
 
1067void intel_encoder_destroy(struct drm_encoder *encoder);
1068int intel_connector_init(struct intel_connector *);
1069struct intel_connector *intel_connector_alloc(void);
1070bool intel_connector_get_hw_state(struct intel_connector *connector);
1071void intel_connector_attach_encoder(struct intel_connector *connector,
1072				    struct intel_encoder *encoder);
1073struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
1074struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1075					     struct drm_crtc *crtc);
1076enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1077int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1078				struct drm_file *file_priv);
1079enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1080					     enum pipe pipe);
1081bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
 
 
 
 
 
 
 
 
 
 
 
 
 
1082static inline void
1083intel_wait_for_vblank(struct drm_device *dev, int pipe)
1084{
1085	drm_wait_one_vblank(dev, pipe);
1086}
1087static inline void
1088intel_wait_for_vblank_if_active(struct drm_device *dev, int pipe)
1089{
1090	const struct intel_crtc *crtc =
1091		to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
1092
1093	if (crtc->active)
1094		intel_wait_for_vblank(dev, pipe);
1095}
 
 
 
1096int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1097void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1098			 struct intel_digital_port *dport,
1099			 unsigned int expected_mask);
1100bool intel_get_load_detect_pipe(struct drm_connector *connector,
1101				struct drm_display_mode *mode,
1102				struct intel_load_detect_pipe *old,
1103				struct drm_modeset_acquire_ctx *ctx);
1104void intel_release_load_detect_pipe(struct drm_connector *connector,
1105				    struct intel_load_detect_pipe *old,
1106				    struct drm_modeset_acquire_ctx *ctx);
1107int intel_pin_and_fence_fb_obj(struct drm_plane *plane,
1108			       struct drm_framebuffer *fb,
1109			       const struct drm_plane_state *plane_state);
1110struct drm_framebuffer *
1111__intel_framebuffer_create(struct drm_device *dev,
1112			   struct drm_mode_fb_cmd2 *mode_cmd,
1113			   struct drm_i915_gem_object *obj);
1114void intel_prepare_page_flip(struct drm_device *dev, int plane);
1115void intel_finish_page_flip(struct drm_device *dev, int pipe);
1116void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
1117void intel_check_page_flip(struct drm_device *dev, int pipe);
1118int intel_prepare_plane_fb(struct drm_plane *plane,
1119			   const struct drm_plane_state *new_state);
1120void intel_cleanup_plane_fb(struct drm_plane *plane,
1121			    const struct drm_plane_state *old_state);
1122int intel_plane_atomic_get_property(struct drm_plane *plane,
1123				    const struct drm_plane_state *state,
1124				    struct drm_property *property,
1125				    uint64_t *val);
1126int intel_plane_atomic_set_property(struct drm_plane *plane,
1127				    struct drm_plane_state *state,
1128				    struct drm_property *property,
1129				    uint64_t val);
1130int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1131				    struct drm_plane_state *plane_state);
1132
1133unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
1134			       uint64_t fb_modifier, unsigned int cpp);
1135
1136static inline bool
1137intel_rotation_90_or_270(unsigned int rotation)
1138{
1139	return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270));
1140}
1141
1142void intel_create_rotation_property(struct drm_device *dev,
1143					struct intel_plane *plane);
1144
1145/* shared dpll functions */
1146struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
1147void assert_shared_dpll(struct drm_i915_private *dev_priv,
1148			struct intel_shared_dpll *pll,
1149			bool state);
1150#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
1151#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
1152struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
1153						struct intel_crtc_state *state);
1154
1155int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
1156		     const struct dpll *dpll);
1157void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
 
1158
1159/* modesetting asserts */
1160void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1161			   enum pipe pipe);
1162void assert_pll(struct drm_i915_private *dev_priv,
1163		enum pipe pipe, bool state);
1164#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1165#define assert_pll_disabled(d, p) assert_pll(d, p, false)
 
 
 
1166void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1167		       enum pipe pipe, bool state);
1168#define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1169#define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1170void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1171#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1172#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1173u32 intel_compute_tile_offset(struct drm_i915_private *dev_priv,
1174			      int *x, int *y,
1175			      uint64_t fb_modifier,
1176			      unsigned int cpp,
1177			      unsigned int pitch);
1178void intel_prepare_reset(struct drm_device *dev);
1179void intel_finish_reset(struct drm_device *dev);
1180void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1181void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1182void broxton_init_cdclk(struct drm_device *dev);
1183void broxton_uninit_cdclk(struct drm_device *dev);
1184void broxton_ddi_phy_init(struct drm_device *dev);
1185void broxton_ddi_phy_uninit(struct drm_device *dev);
1186void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1187void bxt_disable_dc9(struct drm_i915_private *dev_priv);
 
1188void skl_init_cdclk(struct drm_i915_private *dev_priv);
1189int skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
1190void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
 
1191void skl_enable_dc6(struct drm_i915_private *dev_priv);
1192void skl_disable_dc6(struct drm_i915_private *dev_priv);
1193void intel_dp_get_m_n(struct intel_crtc *crtc,
1194		      struct intel_crtc_state *pipe_config);
1195void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1196int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1197void
1198ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
1199				int dotclock);
1200bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1201			intel_clock_t *best_clock);
1202int chv_calc_dpll_params(int refclk, intel_clock_t *pll_clock);
1203
1204bool intel_crtc_active(struct drm_crtc *crtc);
1205void hsw_enable_ips(struct intel_crtc *crtc);
1206void hsw_disable_ips(struct intel_crtc *crtc);
1207enum intel_display_power_domain
1208intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1209enum intel_display_power_domain
1210intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder);
1211void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1212				 struct intel_crtc_state *pipe_config);
1213
1214int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1215int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1216
1217u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
1218			   struct drm_i915_gem_object *obj,
1219			   unsigned int plane);
 
1220
1221u32 skl_plane_ctl_format(uint32_t pixel_format);
1222u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1223u32 skl_plane_ctl_rotation(unsigned int rotation);
 
 
 
1224
1225/* intel_csr.c */
1226void intel_csr_ucode_init(struct drm_i915_private *);
1227bool intel_csr_load_program(struct drm_i915_private *);
1228void intel_csr_ucode_fini(struct drm_i915_private *);
 
 
1229
1230/* intel_dp.c */
1231void intel_dp_init(struct drm_device *dev, i915_reg_t output_reg, enum port port);
1232bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1233			     struct intel_connector *intel_connector);
1234void intel_dp_set_link_params(struct intel_dp *intel_dp,
1235			      const struct intel_crtc_state *pipe_config);
 
1236void intel_dp_start_link_train(struct intel_dp *intel_dp);
1237void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1238void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1239void intel_dp_encoder_reset(struct drm_encoder *encoder);
1240void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1241void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1242int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1243bool intel_dp_compute_config(struct intel_encoder *encoder,
1244			     struct intel_crtc_state *pipe_config);
1245bool intel_dp_is_edp(struct drm_device *dev, enum port port);
 
1246enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1247				  bool long_hpd);
1248void intel_edp_backlight_on(struct intel_dp *intel_dp);
1249void intel_edp_backlight_off(struct intel_dp *intel_dp);
1250void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1251void intel_edp_panel_on(struct intel_dp *intel_dp);
1252void intel_edp_panel_off(struct intel_dp *intel_dp);
1253void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1254void intel_dp_mst_suspend(struct drm_device *dev);
1255void intel_dp_mst_resume(struct drm_device *dev);
1256int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1257int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1258void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1259void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
1260uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1261void intel_plane_destroy(struct drm_plane *plane);
1262void intel_edp_drrs_enable(struct intel_dp *intel_dp);
1263void intel_edp_drrs_disable(struct intel_dp *intel_dp);
1264void intel_edp_drrs_invalidate(struct drm_device *dev,
1265		unsigned frontbuffer_bits);
1266void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
1267bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
1268					 struct intel_digital_port *port);
1269void hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config);
1270
1271void
1272intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1273				       uint8_t dp_train_pat);
1274void
1275intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1276void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1277uint8_t
1278intel_dp_voltage_max(struct intel_dp *intel_dp);
1279uint8_t
1280intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1281void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1282			   uint8_t *link_bw, uint8_t *rate_select);
1283bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1284bool
1285intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1286
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1287/* intel_dp_mst.c */
1288int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1289void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1290/* intel_dsi.c */
1291void intel_dsi_init(struct drm_device *dev);
1292
 
 
1293
1294/* intel_dvo.c */
1295void intel_dvo_init(struct drm_device *dev);
 
 
1296
1297
1298/* legacy fbdev emulation in intel_fbdev.c */
1299#ifdef CONFIG_DRM_FBDEV_EMULATION
1300extern int intel_fbdev_init(struct drm_device *dev);
1301extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1302extern void intel_fbdev_fini(struct drm_device *dev);
1303extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1304extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1305extern void intel_fbdev_restore_mode(struct drm_device *dev);
1306#else
1307static inline int intel_fbdev_init(struct drm_device *dev)
1308{
1309	return 0;
1310}
1311
1312static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1313{
1314}
1315
1316static inline void intel_fbdev_fini(struct drm_device *dev)
1317{
1318}
1319
1320static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1321{
1322}
1323
 
 
 
 
1324static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1325{
1326}
1327#endif
1328
1329/* intel_fbc.c */
1330void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1331			   struct drm_atomic_state *state);
1332bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1333void intel_fbc_pre_update(struct intel_crtc *crtc);
 
 
1334void intel_fbc_post_update(struct intel_crtc *crtc);
1335void intel_fbc_init(struct drm_i915_private *dev_priv);
1336void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1337void intel_fbc_enable(struct intel_crtc *crtc);
 
 
1338void intel_fbc_disable(struct intel_crtc *crtc);
1339void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1340void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1341			  unsigned int frontbuffer_bits,
1342			  enum fb_op_origin origin);
1343void intel_fbc_flush(struct drm_i915_private *dev_priv,
1344		     unsigned int frontbuffer_bits, enum fb_op_origin origin);
1345void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
 
1346
1347/* intel_hdmi.c */
1348void intel_hdmi_init(struct drm_device *dev, i915_reg_t hdmi_reg, enum port port);
1349void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1350			       struct intel_connector *intel_connector);
1351struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1352bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1353			       struct intel_crtc_state *pipe_config);
 
 
1354
1355
1356/* intel_lvds.c */
1357void intel_lvds_init(struct drm_device *dev);
 
1358bool intel_is_dual_link_lvds(struct drm_device *dev);
1359
1360
1361/* intel_modes.c */
1362int intel_connector_update_modes(struct drm_connector *connector,
1363				 struct edid *edid);
1364int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1365void intel_attach_force_audio_property(struct drm_connector *connector);
1366void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1367void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1368
1369
1370/* intel_overlay.c */
1371void intel_setup_overlay(struct drm_device *dev);
1372void intel_cleanup_overlay(struct drm_device *dev);
1373int intel_overlay_switch_off(struct intel_overlay *overlay);
1374int intel_overlay_put_image(struct drm_device *dev, void *data,
1375			    struct drm_file *file_priv);
1376int intel_overlay_attrs(struct drm_device *dev, void *data,
1377			struct drm_file *file_priv);
1378void intel_overlay_reset(struct drm_i915_private *dev_priv);
1379
1380
1381/* intel_panel.c */
1382int intel_panel_init(struct intel_panel *panel,
1383		     struct drm_display_mode *fixed_mode,
1384		     struct drm_display_mode *downclock_mode);
1385void intel_panel_fini(struct intel_panel *panel);
1386void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1387			    struct drm_display_mode *adjusted_mode);
1388void intel_pch_panel_fitting(struct intel_crtc *crtc,
1389			     struct intel_crtc_state *pipe_config,
1390			     int fitting_mode);
1391void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1392			      struct intel_crtc_state *pipe_config,
1393			      int fitting_mode);
1394void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1395				    u32 level, u32 max);
1396int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe);
 
1397void intel_panel_enable_backlight(struct intel_connector *connector);
1398void intel_panel_disable_backlight(struct intel_connector *connector);
1399void intel_panel_destroy_backlight(struct drm_connector *connector);
1400enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1401extern struct drm_display_mode *intel_find_panel_downclock(
1402				struct drm_device *dev,
1403				struct drm_display_mode *fixed_mode,
1404				struct drm_connector *connector);
1405void intel_backlight_register(struct drm_device *dev);
1406void intel_backlight_unregister(struct drm_device *dev);
 
 
 
 
 
 
 
 
 
 
 
1407
1408
1409/* intel_psr.c */
1410void intel_psr_enable(struct intel_dp *intel_dp);
1411void intel_psr_disable(struct intel_dp *intel_dp);
1412void intel_psr_invalidate(struct drm_device *dev,
1413			  unsigned frontbuffer_bits);
1414void intel_psr_flush(struct drm_device *dev,
1415		     unsigned frontbuffer_bits,
1416		     enum fb_op_origin origin);
1417void intel_psr_init(struct drm_device *dev);
1418void intel_psr_single_frame_update(struct drm_device *dev,
1419				   unsigned frontbuffer_bits);
1420
1421/* intel_runtime_pm.c */
1422int intel_power_domains_init(struct drm_i915_private *);
1423void intel_power_domains_fini(struct drm_i915_private *);
1424void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1425void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1426void skl_pw1_misc_io_init(struct drm_i915_private *dev_priv);
1427void skl_pw1_misc_io_fini(struct drm_i915_private *dev_priv);
1428void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1429const char *
1430intel_display_power_domain_str(enum intel_display_power_domain domain);
1431
1432bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1433				    enum intel_display_power_domain domain);
1434bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1435				      enum intel_display_power_domain domain);
1436void intel_display_power_get(struct drm_i915_private *dev_priv,
1437			     enum intel_display_power_domain domain);
1438bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1439					enum intel_display_power_domain domain);
1440void intel_display_power_put(struct drm_i915_private *dev_priv,
1441			     enum intel_display_power_domain domain);
1442
1443static inline void
1444assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1445{
1446	WARN_ONCE(dev_priv->pm.suspended,
1447		  "Device suspended during HW access\n");
1448}
1449
1450static inline void
1451assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1452{
1453	assert_rpm_device_not_suspended(dev_priv);
1454	/* FIXME: Needs to be converted back to WARN_ONCE, but currently causes
1455	 * too much noise. */
1456	if (!atomic_read(&dev_priv->pm.wakeref_count))
1457		DRM_DEBUG_DRIVER("RPM wakelock ref not held during HW access");
1458}
1459
1460static inline int
1461assert_rpm_atomic_begin(struct drm_i915_private *dev_priv)
1462{
1463	int seq = atomic_read(&dev_priv->pm.atomic_seq);
1464
1465	assert_rpm_wakelock_held(dev_priv);
1466
1467	return seq;
1468}
1469
1470static inline void
1471assert_rpm_atomic_end(struct drm_i915_private *dev_priv, int begin_seq)
1472{
1473	WARN_ONCE(atomic_read(&dev_priv->pm.atomic_seq) != begin_seq,
1474		  "HW access outside of RPM atomic section\n");
1475}
1476
1477/**
1478 * disable_rpm_wakeref_asserts - disable the RPM assert checks
1479 * @dev_priv: i915 device instance
1480 *
1481 * This function disable asserts that check if we hold an RPM wakelock
1482 * reference, while keeping the device-not-suspended checks still enabled.
1483 * It's meant to be used only in special circumstances where our rule about
1484 * the wakelock refcount wrt. the device power state doesn't hold. According
1485 * to this rule at any point where we access the HW or want to keep the HW in
1486 * an active state we must hold an RPM wakelock reference acquired via one of
1487 * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1488 * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1489 * forcewake release timer, and the GPU RPS and hangcheck works. All other
1490 * users should avoid using this function.
1491 *
1492 * Any calls to this function must have a symmetric call to
1493 * enable_rpm_wakeref_asserts().
1494 */
1495static inline void
1496disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1497{
1498	atomic_inc(&dev_priv->pm.wakeref_count);
1499}
1500
1501/**
1502 * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1503 * @dev_priv: i915 device instance
1504 *
1505 * This function re-enables the RPM assert checks after disabling them with
1506 * disable_rpm_wakeref_asserts. It's meant to be used only in special
1507 * circumstances otherwise its use should be avoided.
1508 *
1509 * Any calls to this function must have a symmetric call to
1510 * disable_rpm_wakeref_asserts().
1511 */
1512static inline void
1513enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1514{
1515	atomic_dec(&dev_priv->pm.wakeref_count);
1516}
1517
1518/* TODO: convert users of these to rely instead on proper RPM refcounting */
1519#define DISABLE_RPM_WAKEREF_ASSERTS(dev_priv)	\
1520	disable_rpm_wakeref_asserts(dev_priv)
1521
1522#define ENABLE_RPM_WAKEREF_ASSERTS(dev_priv)	\
1523	enable_rpm_wakeref_asserts(dev_priv)
1524
1525void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1526bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
1527void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1528void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1529
1530void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1531
1532void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1533			     bool override, unsigned int mask);
1534bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1535			  enum dpio_channel ch, bool override);
1536
1537
1538/* intel_pm.c */
1539void intel_init_clock_gating(struct drm_device *dev);
1540void intel_suspend_hw(struct drm_device *dev);
1541int ilk_wm_max_level(const struct drm_device *dev);
1542void intel_update_watermarks(struct drm_crtc *crtc);
1543void intel_init_pm(struct drm_device *dev);
 
1544void intel_pm_setup(struct drm_device *dev);
1545void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1546void intel_gpu_ips_teardown(void);
1547void intel_init_gt_powersave(struct drm_device *dev);
1548void intel_cleanup_gt_powersave(struct drm_device *dev);
1549void intel_enable_gt_powersave(struct drm_device *dev);
1550void intel_disable_gt_powersave(struct drm_device *dev);
1551void intel_suspend_gt_powersave(struct drm_device *dev);
1552void intel_reset_gt_powersave(struct drm_device *dev);
1553void gen6_update_ring_freq(struct drm_device *dev);
1554void gen6_rps_busy(struct drm_i915_private *dev_priv);
1555void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1556void gen6_rps_idle(struct drm_i915_private *dev_priv);
1557void gen6_rps_boost(struct drm_i915_private *dev_priv,
1558		    struct intel_rps_client *rps,
1559		    unsigned long submitted);
1560void intel_queue_rps_boost_for_request(struct drm_device *dev,
1561				       struct drm_i915_gem_request *req);
1562void vlv_wm_get_hw_state(struct drm_device *dev);
1563void ilk_wm_get_hw_state(struct drm_device *dev);
1564void skl_wm_get_hw_state(struct drm_device *dev);
1565void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1566			  struct skl_ddb_allocation *ddb /* out */);
 
 
 
 
 
 
 
 
 
 
1567uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
1568int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6);
 
 
 
 
 
1569
1570/* intel_sdvo.c */
1571bool intel_sdvo_init(struct drm_device *dev,
1572		     i915_reg_t reg, enum port port);
1573
1574
1575/* intel_sprite.c */
1576int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
 
 
 
1577int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1578			      struct drm_file *file_priv);
1579void intel_pipe_update_start(struct intel_crtc *crtc);
1580void intel_pipe_update_end(struct intel_crtc *crtc);
1581
1582/* intel_tv.c */
1583void intel_tv_init(struct drm_device *dev);
1584
1585/* intel_atomic.c */
1586int intel_connector_atomic_get_property(struct drm_connector *connector,
1587					const struct drm_connector_state *state,
1588					struct drm_property *property,
1589					uint64_t *val);
1590struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1591void intel_crtc_destroy_state(struct drm_crtc *crtc,
1592			       struct drm_crtc_state *state);
1593struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1594void intel_atomic_state_clear(struct drm_atomic_state *);
1595struct intel_shared_dpll_config *
1596intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s);
1597
1598static inline struct intel_crtc_state *
1599intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1600			    struct intel_crtc *crtc)
1601{
1602	struct drm_crtc_state *crtc_state;
1603	crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1604	if (IS_ERR(crtc_state))
1605		return ERR_CAST(crtc_state);
1606
1607	return to_intel_crtc_state(crtc_state);
1608}
 
 
 
 
 
 
 
 
 
 
 
 
1609int intel_atomic_setup_scalers(struct drm_device *dev,
1610	struct intel_crtc *intel_crtc,
1611	struct intel_crtc_state *crtc_state);
1612
1613/* intel_atomic_plane.c */
1614struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1615struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1616void intel_plane_destroy_state(struct drm_plane *plane,
1617			       struct drm_plane_state *state);
1618extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1619
 
 
 
 
 
 
 
 
 
1620#endif /* __INTEL_DRV_H__ */