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1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include <drm/drmP.h>
27#include <drm/radeon_drm.h>
28#include "radeon.h"
29
30static void radeon_lock_cursor(struct drm_crtc *crtc, bool lock)
31{
32 struct radeon_device *rdev = crtc->dev->dev_private;
33 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
34 uint32_t cur_lock;
35
36 if (ASIC_IS_DCE4(rdev)) {
37 cur_lock = RREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset);
38 if (lock)
39 cur_lock |= EVERGREEN_CURSOR_UPDATE_LOCK;
40 else
41 cur_lock &= ~EVERGREEN_CURSOR_UPDATE_LOCK;
42 WREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);
43 } else if (ASIC_IS_AVIVO(rdev)) {
44 cur_lock = RREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset);
45 if (lock)
46 cur_lock |= AVIVO_D1CURSOR_UPDATE_LOCK;
47 else
48 cur_lock &= ~AVIVO_D1CURSOR_UPDATE_LOCK;
49 WREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);
50 } else {
51 cur_lock = RREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset);
52 if (lock)
53 cur_lock |= RADEON_CUR_LOCK;
54 else
55 cur_lock &= ~RADEON_CUR_LOCK;
56 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, cur_lock);
57 }
58}
59
60static void radeon_hide_cursor(struct drm_crtc *crtc)
61{
62 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
63 struct radeon_device *rdev = crtc->dev->dev_private;
64
65 if (ASIC_IS_DCE4(rdev)) {
66 WREG32_IDX(EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset,
67 EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) |
68 EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2));
69 } else if (ASIC_IS_AVIVO(rdev)) {
70 WREG32_IDX(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset,
71 (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
72 } else {
73 u32 reg;
74 switch (radeon_crtc->crtc_id) {
75 case 0:
76 reg = RADEON_CRTC_GEN_CNTL;
77 break;
78 case 1:
79 reg = RADEON_CRTC2_GEN_CNTL;
80 break;
81 default:
82 return;
83 }
84 WREG32_IDX(reg, RREG32_IDX(reg) & ~RADEON_CRTC_CUR_EN);
85 }
86}
87
88static void radeon_show_cursor(struct drm_crtc *crtc)
89{
90 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
91 struct radeon_device *rdev = crtc->dev->dev_private;
92
93 if (ASIC_IS_DCE4(rdev)) {
94 WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
95 upper_32_bits(radeon_crtc->cursor_addr));
96 WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
97 lower_32_bits(radeon_crtc->cursor_addr));
98 WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset);
99 WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_EN |
100 EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) |
101 EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2));
102 } else if (ASIC_IS_AVIVO(rdev)) {
103 if (rdev->family >= CHIP_RV770) {
104 if (radeon_crtc->crtc_id)
105 WREG32(R700_D2CUR_SURFACE_ADDRESS_HIGH,
106 upper_32_bits(radeon_crtc->cursor_addr));
107 else
108 WREG32(R700_D1CUR_SURFACE_ADDRESS_HIGH,
109 upper_32_bits(radeon_crtc->cursor_addr));
110 }
111
112 WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
113 lower_32_bits(radeon_crtc->cursor_addr));
114 WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset);
115 WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN |
116 (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
117 } else {
118 /* offset is from DISP(2)_BASE_ADDRESS */
119 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset,
120 radeon_crtc->cursor_addr - radeon_crtc->legacy_display_base_addr);
121
122 switch (radeon_crtc->crtc_id) {
123 case 0:
124 WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL);
125 break;
126 case 1:
127 WREG32(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL);
128 break;
129 default:
130 return;
131 }
132
133 WREG32_P(RADEON_MM_DATA, (RADEON_CRTC_CUR_EN |
134 (RADEON_CRTC_CUR_MODE_24BPP << RADEON_CRTC_CUR_MODE_SHIFT)),
135 ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK));
136 }
137}
138
139static int radeon_cursor_move_locked(struct drm_crtc *crtc, int x, int y)
140{
141 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
142 struct radeon_device *rdev = crtc->dev->dev_private;
143 int xorigin = 0, yorigin = 0;
144 int w = radeon_crtc->cursor_width;
145
146 if (ASIC_IS_AVIVO(rdev)) {
147 /* avivo cursor are offset into the total surface */
148 x += crtc->x;
149 y += crtc->y;
150 }
151 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
152
153 if (x < 0) {
154 xorigin = min(-x, radeon_crtc->max_cursor_width - 1);
155 x = 0;
156 }
157 if (y < 0) {
158 yorigin = min(-y, radeon_crtc->max_cursor_height - 1);
159 y = 0;
160 }
161
162 /* fixed on DCE6 and newer */
163 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE6(rdev)) {
164 int i = 0;
165 struct drm_crtc *crtc_p;
166
167 /*
168 * avivo cursor image can't end on 128 pixel boundary or
169 * go past the end of the frame if both crtcs are enabled
170 *
171 * NOTE: It is safe to access crtc->enabled of other crtcs
172 * without holding either the mode_config lock or the other
173 * crtc's lock as long as write access to this flag _always_
174 * grabs all locks.
175 */
176 list_for_each_entry(crtc_p, &crtc->dev->mode_config.crtc_list, head) {
177 if (crtc_p->enabled)
178 i++;
179 }
180 if (i > 1) {
181 int cursor_end, frame_end;
182
183 cursor_end = x - xorigin + w;
184 frame_end = crtc->x + crtc->mode.crtc_hdisplay;
185 if (cursor_end >= frame_end) {
186 w = w - (cursor_end - frame_end);
187 if (!(frame_end & 0x7f))
188 w--;
189 } else {
190 if (!(cursor_end & 0x7f))
191 w--;
192 }
193 if (w <= 0) {
194 w = 1;
195 cursor_end = x - xorigin + w;
196 if (!(cursor_end & 0x7f)) {
197 x--;
198 WARN_ON_ONCE(x < 0);
199 }
200 }
201 }
202 }
203
204 if (ASIC_IS_DCE4(rdev)) {
205 WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);
206 WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
207 WREG32(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset,
208 ((w - 1) << 16) | (radeon_crtc->cursor_height - 1));
209 } else if (ASIC_IS_AVIVO(rdev)) {
210 WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);
211 WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
212 WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset,
213 ((w - 1) << 16) | (radeon_crtc->cursor_height - 1));
214 } else {
215 if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)
216 y *= 2;
217
218 WREG32(RADEON_CUR_HORZ_VERT_OFF + radeon_crtc->crtc_offset,
219 (RADEON_CUR_LOCK
220 | (xorigin << 16)
221 | yorigin));
222 WREG32(RADEON_CUR_HORZ_VERT_POSN + radeon_crtc->crtc_offset,
223 (RADEON_CUR_LOCK
224 | (x << 16)
225 | y));
226 /* offset is from DISP(2)_BASE_ADDRESS */
227 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset,
228 radeon_crtc->cursor_addr - radeon_crtc->legacy_display_base_addr +
229 yorigin * 256);
230 }
231
232 radeon_crtc->cursor_x = x;
233 radeon_crtc->cursor_y = y;
234
235 return 0;
236}
237
238int radeon_crtc_cursor_move(struct drm_crtc *crtc,
239 int x, int y)
240{
241 int ret;
242
243 radeon_lock_cursor(crtc, true);
244 ret = radeon_cursor_move_locked(crtc, x, y);
245 radeon_lock_cursor(crtc, false);
246
247 return ret;
248}
249
250int radeon_crtc_cursor_set2(struct drm_crtc *crtc,
251 struct drm_file *file_priv,
252 uint32_t handle,
253 uint32_t width,
254 uint32_t height,
255 int32_t hot_x,
256 int32_t hot_y)
257{
258 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
259 struct radeon_device *rdev = crtc->dev->dev_private;
260 struct drm_gem_object *obj;
261 struct radeon_bo *robj;
262 int ret;
263
264 if (!handle) {
265 /* turn off cursor */
266 radeon_hide_cursor(crtc);
267 obj = NULL;
268 goto unpin;
269 }
270
271 if ((width > radeon_crtc->max_cursor_width) ||
272 (height > radeon_crtc->max_cursor_height)) {
273 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
274 return -EINVAL;
275 }
276
277 obj = drm_gem_object_lookup(crtc->dev, file_priv, handle);
278 if (!obj) {
279 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, radeon_crtc->crtc_id);
280 return -ENOENT;
281 }
282
283 robj = gem_to_radeon_bo(obj);
284 ret = radeon_bo_reserve(robj, false);
285 if (ret != 0) {
286 drm_gem_object_unreference_unlocked(obj);
287 return ret;
288 }
289 /* Only 27 bit offset for legacy cursor */
290 ret = radeon_bo_pin_restricted(robj, RADEON_GEM_DOMAIN_VRAM,
291 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27,
292 &radeon_crtc->cursor_addr);
293 radeon_bo_unreserve(robj);
294 if (ret) {
295 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
296 drm_gem_object_unreference_unlocked(obj);
297 return ret;
298 }
299
300 radeon_crtc->cursor_width = width;
301 radeon_crtc->cursor_height = height;
302
303 radeon_lock_cursor(crtc, true);
304
305 if (hot_x != radeon_crtc->cursor_hot_x ||
306 hot_y != radeon_crtc->cursor_hot_y) {
307 int x, y;
308
309 x = radeon_crtc->cursor_x + radeon_crtc->cursor_hot_x - hot_x;
310 y = radeon_crtc->cursor_y + radeon_crtc->cursor_hot_y - hot_y;
311
312 radeon_cursor_move_locked(crtc, x, y);
313
314 radeon_crtc->cursor_hot_x = hot_x;
315 radeon_crtc->cursor_hot_y = hot_y;
316 }
317
318 radeon_show_cursor(crtc);
319
320 radeon_lock_cursor(crtc, false);
321
322unpin:
323 if (radeon_crtc->cursor_bo) {
324 struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo);
325 ret = radeon_bo_reserve(robj, false);
326 if (likely(ret == 0)) {
327 radeon_bo_unpin(robj);
328 radeon_bo_unreserve(robj);
329 }
330 drm_gem_object_unreference_unlocked(radeon_crtc->cursor_bo);
331 }
332
333 radeon_crtc->cursor_bo = obj;
334 return 0;
335}
336
337/**
338 * radeon_cursor_reset - Re-set the current cursor, if any.
339 *
340 * @crtc: drm crtc
341 *
342 * If the CRTC passed in currently has a cursor assigned, this function
343 * makes sure it's visible.
344 */
345void radeon_cursor_reset(struct drm_crtc *crtc)
346{
347 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
348
349 if (radeon_crtc->cursor_bo) {
350 radeon_lock_cursor(crtc, true);
351
352 radeon_cursor_move_locked(crtc, radeon_crtc->cursor_x,
353 radeon_crtc->cursor_y);
354
355 radeon_show_cursor(crtc);
356
357 radeon_lock_cursor(crtc, false);
358 }
359}
1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include "drmP.h"
27#include "radeon_drm.h"
28#include "radeon.h"
29
30#define CURSOR_WIDTH 64
31#define CURSOR_HEIGHT 64
32
33static void radeon_lock_cursor(struct drm_crtc *crtc, bool lock)
34{
35 struct radeon_device *rdev = crtc->dev->dev_private;
36 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
37 uint32_t cur_lock;
38
39 if (ASIC_IS_DCE4(rdev)) {
40 cur_lock = RREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset);
41 if (lock)
42 cur_lock |= EVERGREEN_CURSOR_UPDATE_LOCK;
43 else
44 cur_lock &= ~EVERGREEN_CURSOR_UPDATE_LOCK;
45 WREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);
46 } else if (ASIC_IS_AVIVO(rdev)) {
47 cur_lock = RREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset);
48 if (lock)
49 cur_lock |= AVIVO_D1CURSOR_UPDATE_LOCK;
50 else
51 cur_lock &= ~AVIVO_D1CURSOR_UPDATE_LOCK;
52 WREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);
53 } else {
54 cur_lock = RREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset);
55 if (lock)
56 cur_lock |= RADEON_CUR_LOCK;
57 else
58 cur_lock &= ~RADEON_CUR_LOCK;
59 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, cur_lock);
60 }
61}
62
63static void radeon_hide_cursor(struct drm_crtc *crtc)
64{
65 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
66 struct radeon_device *rdev = crtc->dev->dev_private;
67
68 if (ASIC_IS_DCE4(rdev)) {
69 WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset);
70 WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT));
71 } else if (ASIC_IS_AVIVO(rdev)) {
72 WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset);
73 WREG32(RADEON_MM_DATA, (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
74 } else {
75 switch (radeon_crtc->crtc_id) {
76 case 0:
77 WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL);
78 break;
79 case 1:
80 WREG32(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL);
81 break;
82 default:
83 return;
84 }
85 WREG32_P(RADEON_MM_DATA, 0, ~RADEON_CRTC_CUR_EN);
86 }
87}
88
89static void radeon_show_cursor(struct drm_crtc *crtc)
90{
91 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
92 struct radeon_device *rdev = crtc->dev->dev_private;
93
94 if (ASIC_IS_DCE4(rdev)) {
95 WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset);
96 WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_EN |
97 EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT));
98 } else if (ASIC_IS_AVIVO(rdev)) {
99 WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset);
100 WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN |
101 (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
102 } else {
103 switch (radeon_crtc->crtc_id) {
104 case 0:
105 WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL);
106 break;
107 case 1:
108 WREG32(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL);
109 break;
110 default:
111 return;
112 }
113
114 WREG32_P(RADEON_MM_DATA, (RADEON_CRTC_CUR_EN |
115 (RADEON_CRTC_CUR_MODE_24BPP << RADEON_CRTC_CUR_MODE_SHIFT)),
116 ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK));
117 }
118}
119
120static void radeon_set_cursor(struct drm_crtc *crtc, struct drm_gem_object *obj,
121 uint64_t gpu_addr)
122{
123 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
124 struct radeon_device *rdev = crtc->dev->dev_private;
125
126 if (ASIC_IS_DCE4(rdev)) {
127 WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
128 upper_32_bits(gpu_addr));
129 WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
130 gpu_addr & 0xffffffff);
131 } else if (ASIC_IS_AVIVO(rdev)) {
132 if (rdev->family >= CHIP_RV770) {
133 if (radeon_crtc->crtc_id)
134 WREG32(R700_D2CUR_SURFACE_ADDRESS_HIGH, upper_32_bits(gpu_addr));
135 else
136 WREG32(R700_D1CUR_SURFACE_ADDRESS_HIGH, upper_32_bits(gpu_addr));
137 }
138 WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
139 gpu_addr & 0xffffffff);
140 } else {
141 radeon_crtc->legacy_cursor_offset = gpu_addr - radeon_crtc->legacy_display_base_addr;
142 /* offset is from DISP(2)_BASE_ADDRESS */
143 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, radeon_crtc->legacy_cursor_offset);
144 }
145}
146
147int radeon_crtc_cursor_set(struct drm_crtc *crtc,
148 struct drm_file *file_priv,
149 uint32_t handle,
150 uint32_t width,
151 uint32_t height)
152{
153 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
154 struct radeon_device *rdev = crtc->dev->dev_private;
155 struct drm_gem_object *obj;
156 struct radeon_bo *robj;
157 uint64_t gpu_addr;
158 int ret;
159
160 if (!handle) {
161 /* turn off cursor */
162 radeon_hide_cursor(crtc);
163 obj = NULL;
164 goto unpin;
165 }
166
167 if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) {
168 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
169 return -EINVAL;
170 }
171
172 obj = drm_gem_object_lookup(crtc->dev, file_priv, handle);
173 if (!obj) {
174 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, radeon_crtc->crtc_id);
175 return -ENOENT;
176 }
177
178 robj = gem_to_radeon_bo(obj);
179 ret = radeon_bo_reserve(robj, false);
180 if (unlikely(ret != 0))
181 goto fail;
182 /* Only 27 bit offset for legacy cursor */
183 ret = radeon_bo_pin_restricted(robj, RADEON_GEM_DOMAIN_VRAM,
184 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27,
185 &gpu_addr);
186 radeon_bo_unreserve(robj);
187 if (ret)
188 goto fail;
189
190 radeon_crtc->cursor_width = width;
191 radeon_crtc->cursor_height = height;
192
193 radeon_lock_cursor(crtc, true);
194 radeon_set_cursor(crtc, obj, gpu_addr);
195 radeon_show_cursor(crtc);
196 radeon_lock_cursor(crtc, false);
197
198unpin:
199 if (radeon_crtc->cursor_bo) {
200 robj = gem_to_radeon_bo(radeon_crtc->cursor_bo);
201 ret = radeon_bo_reserve(robj, false);
202 if (likely(ret == 0)) {
203 radeon_bo_unpin(robj);
204 radeon_bo_unreserve(robj);
205 }
206 drm_gem_object_unreference_unlocked(radeon_crtc->cursor_bo);
207 }
208
209 radeon_crtc->cursor_bo = obj;
210 return 0;
211fail:
212 drm_gem_object_unreference_unlocked(obj);
213
214 return ret;
215}
216
217int radeon_crtc_cursor_move(struct drm_crtc *crtc,
218 int x, int y)
219{
220 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
221 struct radeon_device *rdev = crtc->dev->dev_private;
222 int xorigin = 0, yorigin = 0;
223 int w = radeon_crtc->cursor_width;
224
225 if (ASIC_IS_AVIVO(rdev)) {
226 /* avivo cursor are offset into the total surface */
227 x += crtc->x;
228 y += crtc->y;
229 }
230 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
231
232 if (x < 0) {
233 xorigin = min(-x, CURSOR_WIDTH - 1);
234 x = 0;
235 }
236 if (y < 0) {
237 yorigin = min(-y, CURSOR_HEIGHT - 1);
238 y = 0;
239 }
240
241 if (ASIC_IS_AVIVO(rdev)) {
242 int i = 0;
243 struct drm_crtc *crtc_p;
244
245 /* avivo cursor image can't end on 128 pixel boundary or
246 * go past the end of the frame if both crtcs are enabled
247 */
248 list_for_each_entry(crtc_p, &crtc->dev->mode_config.crtc_list, head) {
249 if (crtc_p->enabled)
250 i++;
251 }
252 if (i > 1) {
253 int cursor_end, frame_end;
254
255 cursor_end = x - xorigin + w;
256 frame_end = crtc->x + crtc->mode.crtc_hdisplay;
257 if (cursor_end >= frame_end) {
258 w = w - (cursor_end - frame_end);
259 if (!(frame_end & 0x7f))
260 w--;
261 } else {
262 if (!(cursor_end & 0x7f))
263 w--;
264 }
265 if (w <= 0) {
266 w = 1;
267 cursor_end = x - xorigin + w;
268 if (!(cursor_end & 0x7f)) {
269 x--;
270 WARN_ON_ONCE(x < 0);
271 }
272 }
273 }
274 }
275
276 radeon_lock_cursor(crtc, true);
277 if (ASIC_IS_DCE4(rdev)) {
278 WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);
279 WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
280 WREG32(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset,
281 ((w - 1) << 16) | (radeon_crtc->cursor_height - 1));
282 } else if (ASIC_IS_AVIVO(rdev)) {
283 WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);
284 WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
285 WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset,
286 ((w - 1) << 16) | (radeon_crtc->cursor_height - 1));
287 } else {
288 if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)
289 y *= 2;
290
291 WREG32(RADEON_CUR_HORZ_VERT_OFF + radeon_crtc->crtc_offset,
292 (RADEON_CUR_LOCK
293 | (xorigin << 16)
294 | yorigin));
295 WREG32(RADEON_CUR_HORZ_VERT_POSN + radeon_crtc->crtc_offset,
296 (RADEON_CUR_LOCK
297 | (x << 16)
298 | y));
299 /* offset is from DISP(2)_BASE_ADDRESS */
300 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, (radeon_crtc->legacy_cursor_offset +
301 (yorigin * 256)));
302 }
303 radeon_lock_cursor(crtc, false);
304
305 return 0;
306}