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1/*
2 * Tegra host1x driver
3 *
4 * Copyright (c) 2010-2013, NVIDIA Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#include <linux/module.h>
20#include <linux/list.h>
21#include <linux/slab.h>
22#include <linux/of.h>
23#include <linux/of_device.h>
24#include <linux/clk.h>
25#include <linux/io.h>
26#include <linux/dma-mapping.h>
27
28#define CREATE_TRACE_POINTS
29#include <trace/events/host1x.h>
30
31#include "bus.h"
32#include "dev.h"
33#include "intr.h"
34#include "channel.h"
35#include "debug.h"
36#include "hw/host1x01.h"
37#include "hw/host1x02.h"
38#include "hw/host1x04.h"
39#include "hw/host1x05.h"
40
41void host1x_sync_writel(struct host1x *host1x, u32 v, u32 r)
42{
43 void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset;
44
45 writel(v, sync_regs + r);
46}
47
48u32 host1x_sync_readl(struct host1x *host1x, u32 r)
49{
50 void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset;
51
52 return readl(sync_regs + r);
53}
54
55void host1x_ch_writel(struct host1x_channel *ch, u32 v, u32 r)
56{
57 writel(v, ch->regs + r);
58}
59
60u32 host1x_ch_readl(struct host1x_channel *ch, u32 r)
61{
62 return readl(ch->regs + r);
63}
64
65static const struct host1x_info host1x01_info = {
66 .nb_channels = 8,
67 .nb_pts = 32,
68 .nb_mlocks = 16,
69 .nb_bases = 8,
70 .init = host1x01_init,
71 .sync_offset = 0x3000,
72 .dma_mask = DMA_BIT_MASK(32),
73};
74
75static const struct host1x_info host1x02_info = {
76 .nb_channels = 9,
77 .nb_pts = 32,
78 .nb_mlocks = 16,
79 .nb_bases = 12,
80 .init = host1x02_init,
81 .sync_offset = 0x3000,
82 .dma_mask = DMA_BIT_MASK(32),
83};
84
85static const struct host1x_info host1x04_info = {
86 .nb_channels = 12,
87 .nb_pts = 192,
88 .nb_mlocks = 16,
89 .nb_bases = 64,
90 .init = host1x04_init,
91 .sync_offset = 0x2100,
92 .dma_mask = DMA_BIT_MASK(34),
93};
94
95static const struct host1x_info host1x05_info = {
96 .nb_channels = 14,
97 .nb_pts = 192,
98 .nb_mlocks = 16,
99 .nb_bases = 64,
100 .init = host1x05_init,
101 .sync_offset = 0x2100,
102 .dma_mask = DMA_BIT_MASK(34),
103};
104
105static struct of_device_id host1x_of_match[] = {
106 { .compatible = "nvidia,tegra210-host1x", .data = &host1x05_info, },
107 { .compatible = "nvidia,tegra124-host1x", .data = &host1x04_info, },
108 { .compatible = "nvidia,tegra114-host1x", .data = &host1x02_info, },
109 { .compatible = "nvidia,tegra30-host1x", .data = &host1x01_info, },
110 { .compatible = "nvidia,tegra20-host1x", .data = &host1x01_info, },
111 { },
112};
113MODULE_DEVICE_TABLE(of, host1x_of_match);
114
115static int host1x_probe(struct platform_device *pdev)
116{
117 const struct of_device_id *id;
118 struct host1x *host;
119 struct resource *regs;
120 int syncpt_irq;
121 int err;
122
123 id = of_match_device(host1x_of_match, &pdev->dev);
124 if (!id)
125 return -EINVAL;
126
127 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
128 if (!regs) {
129 dev_err(&pdev->dev, "failed to get registers\n");
130 return -ENXIO;
131 }
132
133 syncpt_irq = platform_get_irq(pdev, 0);
134 if (syncpt_irq < 0) {
135 dev_err(&pdev->dev, "failed to get IRQ\n");
136 return -ENXIO;
137 }
138
139 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
140 if (!host)
141 return -ENOMEM;
142
143 mutex_init(&host->devices_lock);
144 INIT_LIST_HEAD(&host->devices);
145 INIT_LIST_HEAD(&host->list);
146 host->dev = &pdev->dev;
147 host->info = id->data;
148
149 /* set common host1x device data */
150 platform_set_drvdata(pdev, host);
151
152 host->regs = devm_ioremap_resource(&pdev->dev, regs);
153 if (IS_ERR(host->regs))
154 return PTR_ERR(host->regs);
155
156 dma_set_mask_and_coherent(host->dev, host->info->dma_mask);
157
158 if (host->info->init) {
159 err = host->info->init(host);
160 if (err)
161 return err;
162 }
163
164 host->clk = devm_clk_get(&pdev->dev, NULL);
165 if (IS_ERR(host->clk)) {
166 dev_err(&pdev->dev, "failed to get clock\n");
167 err = PTR_ERR(host->clk);
168 return err;
169 }
170
171 err = host1x_channel_list_init(host);
172 if (err) {
173 dev_err(&pdev->dev, "failed to initialize channel list\n");
174 return err;
175 }
176
177 err = clk_prepare_enable(host->clk);
178 if (err < 0) {
179 dev_err(&pdev->dev, "failed to enable clock\n");
180 return err;
181 }
182
183 err = host1x_syncpt_init(host);
184 if (err) {
185 dev_err(&pdev->dev, "failed to initialize syncpts\n");
186 goto fail_unprepare_disable;
187 }
188
189 err = host1x_intr_init(host, syncpt_irq);
190 if (err) {
191 dev_err(&pdev->dev, "failed to initialize interrupts\n");
192 goto fail_deinit_syncpt;
193 }
194
195 host1x_debug_init(host);
196
197 err = host1x_register(host);
198 if (err < 0)
199 goto fail_deinit_intr;
200
201 return 0;
202
203fail_deinit_intr:
204 host1x_intr_deinit(host);
205fail_deinit_syncpt:
206 host1x_syncpt_deinit(host);
207fail_unprepare_disable:
208 clk_disable_unprepare(host->clk);
209 return err;
210}
211
212static int host1x_remove(struct platform_device *pdev)
213{
214 struct host1x *host = platform_get_drvdata(pdev);
215
216 host1x_unregister(host);
217 host1x_intr_deinit(host);
218 host1x_syncpt_deinit(host);
219 clk_disable_unprepare(host->clk);
220
221 return 0;
222}
223
224static struct platform_driver tegra_host1x_driver = {
225 .driver = {
226 .name = "tegra-host1x",
227 .of_match_table = host1x_of_match,
228 },
229 .probe = host1x_probe,
230 .remove = host1x_remove,
231};
232
233static struct platform_driver * const drivers[] = {
234 &tegra_host1x_driver,
235 &tegra_mipi_driver,
236};
237
238static int __init tegra_host1x_init(void)
239{
240 int err;
241
242 err = bus_register(&host1x_bus_type);
243 if (err < 0)
244 return err;
245
246 err = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
247 if (err < 0)
248 bus_unregister(&host1x_bus_type);
249
250 return err;
251}
252module_init(tegra_host1x_init);
253
254static void __exit tegra_host1x_exit(void)
255{
256 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
257 bus_unregister(&host1x_bus_type);
258}
259module_exit(tegra_host1x_exit);
260
261MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
262MODULE_AUTHOR("Terje Bergstrom <tbergstrom@nvidia.com>");
263MODULE_DESCRIPTION("Host1x driver for Tegra products");
264MODULE_LICENSE("GPL");
1/*
2 * Tegra host1x driver
3 *
4 * Copyright (c) 2010-2013, NVIDIA Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#include <linux/module.h>
20#include <linux/list.h>
21#include <linux/slab.h>
22#include <linux/of.h>
23#include <linux/of_device.h>
24#include <linux/clk.h>
25#include <linux/io.h>
26
27#define CREATE_TRACE_POINTS
28#include <trace/events/host1x.h>
29
30#include "bus.h"
31#include "dev.h"
32#include "intr.h"
33#include "channel.h"
34#include "debug.h"
35#include "hw/host1x01.h"
36#include "hw/host1x02.h"
37#include "hw/host1x04.h"
38
39void host1x_sync_writel(struct host1x *host1x, u32 v, u32 r)
40{
41 void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset;
42
43 writel(v, sync_regs + r);
44}
45
46u32 host1x_sync_readl(struct host1x *host1x, u32 r)
47{
48 void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset;
49
50 return readl(sync_regs + r);
51}
52
53void host1x_ch_writel(struct host1x_channel *ch, u32 v, u32 r)
54{
55 writel(v, ch->regs + r);
56}
57
58u32 host1x_ch_readl(struct host1x_channel *ch, u32 r)
59{
60 return readl(ch->regs + r);
61}
62
63static const struct host1x_info host1x01_info = {
64 .nb_channels = 8,
65 .nb_pts = 32,
66 .nb_mlocks = 16,
67 .nb_bases = 8,
68 .init = host1x01_init,
69 .sync_offset = 0x3000,
70};
71
72static const struct host1x_info host1x02_info = {
73 .nb_channels = 9,
74 .nb_pts = 32,
75 .nb_mlocks = 16,
76 .nb_bases = 12,
77 .init = host1x02_init,
78 .sync_offset = 0x3000,
79};
80
81static const struct host1x_info host1x04_info = {
82 .nb_channels = 12,
83 .nb_pts = 192,
84 .nb_mlocks = 16,
85 .nb_bases = 64,
86 .init = host1x04_init,
87 .sync_offset = 0x2100,
88};
89
90static struct of_device_id host1x_of_match[] = {
91 { .compatible = "nvidia,tegra124-host1x", .data = &host1x04_info, },
92 { .compatible = "nvidia,tegra114-host1x", .data = &host1x02_info, },
93 { .compatible = "nvidia,tegra30-host1x", .data = &host1x01_info, },
94 { .compatible = "nvidia,tegra20-host1x", .data = &host1x01_info, },
95 { },
96};
97MODULE_DEVICE_TABLE(of, host1x_of_match);
98
99static int host1x_probe(struct platform_device *pdev)
100{
101 const struct of_device_id *id;
102 struct host1x *host;
103 struct resource *regs;
104 int syncpt_irq;
105 int err;
106
107 id = of_match_device(host1x_of_match, &pdev->dev);
108 if (!id)
109 return -EINVAL;
110
111 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
112 if (!regs) {
113 dev_err(&pdev->dev, "failed to get registers\n");
114 return -ENXIO;
115 }
116
117 syncpt_irq = platform_get_irq(pdev, 0);
118 if (syncpt_irq < 0) {
119 dev_err(&pdev->dev, "failed to get IRQ\n");
120 return -ENXIO;
121 }
122
123 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
124 if (!host)
125 return -ENOMEM;
126
127 mutex_init(&host->devices_lock);
128 INIT_LIST_HEAD(&host->devices);
129 INIT_LIST_HEAD(&host->list);
130 host->dev = &pdev->dev;
131 host->info = id->data;
132
133 /* set common host1x device data */
134 platform_set_drvdata(pdev, host);
135
136 host->regs = devm_ioremap_resource(&pdev->dev, regs);
137 if (IS_ERR(host->regs))
138 return PTR_ERR(host->regs);
139
140 if (host->info->init) {
141 err = host->info->init(host);
142 if (err)
143 return err;
144 }
145
146 host->clk = devm_clk_get(&pdev->dev, NULL);
147 if (IS_ERR(host->clk)) {
148 dev_err(&pdev->dev, "failed to get clock\n");
149 err = PTR_ERR(host->clk);
150 return err;
151 }
152
153 err = host1x_channel_list_init(host);
154 if (err) {
155 dev_err(&pdev->dev, "failed to initialize channel list\n");
156 return err;
157 }
158
159 err = clk_prepare_enable(host->clk);
160 if (err < 0) {
161 dev_err(&pdev->dev, "failed to enable clock\n");
162 return err;
163 }
164
165 err = host1x_syncpt_init(host);
166 if (err) {
167 dev_err(&pdev->dev, "failed to initialize syncpts\n");
168 goto fail_unprepare_disable;
169 }
170
171 err = host1x_intr_init(host, syncpt_irq);
172 if (err) {
173 dev_err(&pdev->dev, "failed to initialize interrupts\n");
174 goto fail_deinit_syncpt;
175 }
176
177 host1x_debug_init(host);
178
179 err = host1x_register(host);
180 if (err < 0)
181 goto fail_deinit_intr;
182
183 return 0;
184
185fail_deinit_intr:
186 host1x_intr_deinit(host);
187fail_deinit_syncpt:
188 host1x_syncpt_deinit(host);
189fail_unprepare_disable:
190 clk_disable_unprepare(host->clk);
191 return err;
192}
193
194static int host1x_remove(struct platform_device *pdev)
195{
196 struct host1x *host = platform_get_drvdata(pdev);
197
198 host1x_unregister(host);
199 host1x_intr_deinit(host);
200 host1x_syncpt_deinit(host);
201 clk_disable_unprepare(host->clk);
202
203 return 0;
204}
205
206static struct platform_driver tegra_host1x_driver = {
207 .driver = {
208 .name = "tegra-host1x",
209 .of_match_table = host1x_of_match,
210 },
211 .probe = host1x_probe,
212 .remove = host1x_remove,
213};
214
215static int __init tegra_host1x_init(void)
216{
217 int err;
218
219 err = host1x_bus_init();
220 if (err < 0)
221 return err;
222
223 err = platform_driver_register(&tegra_host1x_driver);
224 if (err < 0)
225 goto unregister_bus;
226
227 err = platform_driver_register(&tegra_mipi_driver);
228 if (err < 0)
229 goto unregister_host1x;
230
231 return 0;
232
233unregister_host1x:
234 platform_driver_unregister(&tegra_host1x_driver);
235unregister_bus:
236 host1x_bus_exit();
237 return err;
238}
239module_init(tegra_host1x_init);
240
241static void __exit tegra_host1x_exit(void)
242{
243 platform_driver_unregister(&tegra_mipi_driver);
244 platform_driver_unregister(&tegra_host1x_driver);
245 host1x_bus_exit();
246}
247module_exit(tegra_host1x_exit);
248
249MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
250MODULE_AUTHOR("Terje Bergstrom <tbergstrom@nvidia.com>");
251MODULE_DESCRIPTION("Host1x driver for Tegra products");
252MODULE_LICENSE("GPL");