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1/*
2 * Tegra host1x driver
3 *
4 * Copyright (c) 2010-2013, NVIDIA Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#include <linux/module.h>
20#include <linux/list.h>
21#include <linux/slab.h>
22#include <linux/of.h>
23#include <linux/of_device.h>
24#include <linux/clk.h>
25#include <linux/io.h>
26#include <linux/dma-mapping.h>
27
28#define CREATE_TRACE_POINTS
29#include <trace/events/host1x.h>
30
31#include "bus.h"
32#include "dev.h"
33#include "intr.h"
34#include "channel.h"
35#include "debug.h"
36#include "hw/host1x01.h"
37#include "hw/host1x02.h"
38#include "hw/host1x04.h"
39#include "hw/host1x05.h"
40
41void host1x_sync_writel(struct host1x *host1x, u32 v, u32 r)
42{
43 void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset;
44
45 writel(v, sync_regs + r);
46}
47
48u32 host1x_sync_readl(struct host1x *host1x, u32 r)
49{
50 void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset;
51
52 return readl(sync_regs + r);
53}
54
55void host1x_ch_writel(struct host1x_channel *ch, u32 v, u32 r)
56{
57 writel(v, ch->regs + r);
58}
59
60u32 host1x_ch_readl(struct host1x_channel *ch, u32 r)
61{
62 return readl(ch->regs + r);
63}
64
65static const struct host1x_info host1x01_info = {
66 .nb_channels = 8,
67 .nb_pts = 32,
68 .nb_mlocks = 16,
69 .nb_bases = 8,
70 .init = host1x01_init,
71 .sync_offset = 0x3000,
72 .dma_mask = DMA_BIT_MASK(32),
73};
74
75static const struct host1x_info host1x02_info = {
76 .nb_channels = 9,
77 .nb_pts = 32,
78 .nb_mlocks = 16,
79 .nb_bases = 12,
80 .init = host1x02_init,
81 .sync_offset = 0x3000,
82 .dma_mask = DMA_BIT_MASK(32),
83};
84
85static const struct host1x_info host1x04_info = {
86 .nb_channels = 12,
87 .nb_pts = 192,
88 .nb_mlocks = 16,
89 .nb_bases = 64,
90 .init = host1x04_init,
91 .sync_offset = 0x2100,
92 .dma_mask = DMA_BIT_MASK(34),
93};
94
95static const struct host1x_info host1x05_info = {
96 .nb_channels = 14,
97 .nb_pts = 192,
98 .nb_mlocks = 16,
99 .nb_bases = 64,
100 .init = host1x05_init,
101 .sync_offset = 0x2100,
102 .dma_mask = DMA_BIT_MASK(34),
103};
104
105static struct of_device_id host1x_of_match[] = {
106 { .compatible = "nvidia,tegra210-host1x", .data = &host1x05_info, },
107 { .compatible = "nvidia,tegra124-host1x", .data = &host1x04_info, },
108 { .compatible = "nvidia,tegra114-host1x", .data = &host1x02_info, },
109 { .compatible = "nvidia,tegra30-host1x", .data = &host1x01_info, },
110 { .compatible = "nvidia,tegra20-host1x", .data = &host1x01_info, },
111 { },
112};
113MODULE_DEVICE_TABLE(of, host1x_of_match);
114
115static int host1x_probe(struct platform_device *pdev)
116{
117 const struct of_device_id *id;
118 struct host1x *host;
119 struct resource *regs;
120 int syncpt_irq;
121 int err;
122
123 id = of_match_device(host1x_of_match, &pdev->dev);
124 if (!id)
125 return -EINVAL;
126
127 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
128 if (!regs) {
129 dev_err(&pdev->dev, "failed to get registers\n");
130 return -ENXIO;
131 }
132
133 syncpt_irq = platform_get_irq(pdev, 0);
134 if (syncpt_irq < 0) {
135 dev_err(&pdev->dev, "failed to get IRQ\n");
136 return -ENXIO;
137 }
138
139 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
140 if (!host)
141 return -ENOMEM;
142
143 mutex_init(&host->devices_lock);
144 INIT_LIST_HEAD(&host->devices);
145 INIT_LIST_HEAD(&host->list);
146 host->dev = &pdev->dev;
147 host->info = id->data;
148
149 /* set common host1x device data */
150 platform_set_drvdata(pdev, host);
151
152 host->regs = devm_ioremap_resource(&pdev->dev, regs);
153 if (IS_ERR(host->regs))
154 return PTR_ERR(host->regs);
155
156 dma_set_mask_and_coherent(host->dev, host->info->dma_mask);
157
158 if (host->info->init) {
159 err = host->info->init(host);
160 if (err)
161 return err;
162 }
163
164 host->clk = devm_clk_get(&pdev->dev, NULL);
165 if (IS_ERR(host->clk)) {
166 dev_err(&pdev->dev, "failed to get clock\n");
167 err = PTR_ERR(host->clk);
168 return err;
169 }
170
171 err = host1x_channel_list_init(host);
172 if (err) {
173 dev_err(&pdev->dev, "failed to initialize channel list\n");
174 return err;
175 }
176
177 err = clk_prepare_enable(host->clk);
178 if (err < 0) {
179 dev_err(&pdev->dev, "failed to enable clock\n");
180 return err;
181 }
182
183 err = host1x_syncpt_init(host);
184 if (err) {
185 dev_err(&pdev->dev, "failed to initialize syncpts\n");
186 goto fail_unprepare_disable;
187 }
188
189 err = host1x_intr_init(host, syncpt_irq);
190 if (err) {
191 dev_err(&pdev->dev, "failed to initialize interrupts\n");
192 goto fail_deinit_syncpt;
193 }
194
195 host1x_debug_init(host);
196
197 err = host1x_register(host);
198 if (err < 0)
199 goto fail_deinit_intr;
200
201 return 0;
202
203fail_deinit_intr:
204 host1x_intr_deinit(host);
205fail_deinit_syncpt:
206 host1x_syncpt_deinit(host);
207fail_unprepare_disable:
208 clk_disable_unprepare(host->clk);
209 return err;
210}
211
212static int host1x_remove(struct platform_device *pdev)
213{
214 struct host1x *host = platform_get_drvdata(pdev);
215
216 host1x_unregister(host);
217 host1x_intr_deinit(host);
218 host1x_syncpt_deinit(host);
219 clk_disable_unprepare(host->clk);
220
221 return 0;
222}
223
224static struct platform_driver tegra_host1x_driver = {
225 .driver = {
226 .name = "tegra-host1x",
227 .of_match_table = host1x_of_match,
228 },
229 .probe = host1x_probe,
230 .remove = host1x_remove,
231};
232
233static struct platform_driver * const drivers[] = {
234 &tegra_host1x_driver,
235 &tegra_mipi_driver,
236};
237
238static int __init tegra_host1x_init(void)
239{
240 int err;
241
242 err = bus_register(&host1x_bus_type);
243 if (err < 0)
244 return err;
245
246 err = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
247 if (err < 0)
248 bus_unregister(&host1x_bus_type);
249
250 return err;
251}
252module_init(tegra_host1x_init);
253
254static void __exit tegra_host1x_exit(void)
255{
256 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
257 bus_unregister(&host1x_bus_type);
258}
259module_exit(tegra_host1x_exit);
260
261MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
262MODULE_AUTHOR("Terje Bergstrom <tbergstrom@nvidia.com>");
263MODULE_DESCRIPTION("Host1x driver for Tegra products");
264MODULE_LICENSE("GPL");
1/*
2 * Tegra host1x driver
3 *
4 * Copyright (c) 2010-2013, NVIDIA Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#include <linux/clk.h>
20#include <linux/dma-mapping.h>
21#include <linux/io.h>
22#include <linux/list.h>
23#include <linux/module.h>
24#include <linux/of_device.h>
25#include <linux/of.h>
26#include <linux/slab.h>
27
28#define CREATE_TRACE_POINTS
29#include <trace/events/host1x.h>
30#undef CREATE_TRACE_POINTS
31
32#include "bus.h"
33#include "channel.h"
34#include "debug.h"
35#include "dev.h"
36#include "intr.h"
37
38#include "hw/host1x01.h"
39#include "hw/host1x02.h"
40#include "hw/host1x04.h"
41#include "hw/host1x05.h"
42#include "hw/host1x06.h"
43
44void host1x_hypervisor_writel(struct host1x *host1x, u32 v, u32 r)
45{
46 writel(v, host1x->hv_regs + r);
47}
48
49u32 host1x_hypervisor_readl(struct host1x *host1x, u32 r)
50{
51 return readl(host1x->hv_regs + r);
52}
53
54void host1x_sync_writel(struct host1x *host1x, u32 v, u32 r)
55{
56 void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset;
57
58 writel(v, sync_regs + r);
59}
60
61u32 host1x_sync_readl(struct host1x *host1x, u32 r)
62{
63 void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset;
64
65 return readl(sync_regs + r);
66}
67
68void host1x_ch_writel(struct host1x_channel *ch, u32 v, u32 r)
69{
70 writel(v, ch->regs + r);
71}
72
73u32 host1x_ch_readl(struct host1x_channel *ch, u32 r)
74{
75 return readl(ch->regs + r);
76}
77
78static const struct host1x_info host1x01_info = {
79 .nb_channels = 8,
80 .nb_pts = 32,
81 .nb_mlocks = 16,
82 .nb_bases = 8,
83 .init = host1x01_init,
84 .sync_offset = 0x3000,
85 .dma_mask = DMA_BIT_MASK(32),
86};
87
88static const struct host1x_info host1x02_info = {
89 .nb_channels = 9,
90 .nb_pts = 32,
91 .nb_mlocks = 16,
92 .nb_bases = 12,
93 .init = host1x02_init,
94 .sync_offset = 0x3000,
95 .dma_mask = DMA_BIT_MASK(32),
96};
97
98static const struct host1x_info host1x04_info = {
99 .nb_channels = 12,
100 .nb_pts = 192,
101 .nb_mlocks = 16,
102 .nb_bases = 64,
103 .init = host1x04_init,
104 .sync_offset = 0x2100,
105 .dma_mask = DMA_BIT_MASK(34),
106};
107
108static const struct host1x_info host1x05_info = {
109 .nb_channels = 14,
110 .nb_pts = 192,
111 .nb_mlocks = 16,
112 .nb_bases = 64,
113 .init = host1x05_init,
114 .sync_offset = 0x2100,
115 .dma_mask = DMA_BIT_MASK(34),
116};
117
118static const struct host1x_info host1x06_info = {
119 .nb_channels = 63,
120 .nb_pts = 576,
121 .nb_mlocks = 24,
122 .nb_bases = 16,
123 .init = host1x06_init,
124 .sync_offset = 0x0,
125 .dma_mask = DMA_BIT_MASK(34),
126 .has_hypervisor = true,
127};
128
129static const struct of_device_id host1x_of_match[] = {
130 { .compatible = "nvidia,tegra186-host1x", .data = &host1x06_info, },
131 { .compatible = "nvidia,tegra210-host1x", .data = &host1x05_info, },
132 { .compatible = "nvidia,tegra124-host1x", .data = &host1x04_info, },
133 { .compatible = "nvidia,tegra114-host1x", .data = &host1x02_info, },
134 { .compatible = "nvidia,tegra30-host1x", .data = &host1x01_info, },
135 { .compatible = "nvidia,tegra20-host1x", .data = &host1x01_info, },
136 { },
137};
138MODULE_DEVICE_TABLE(of, host1x_of_match);
139
140static int host1x_probe(struct platform_device *pdev)
141{
142 struct host1x *host;
143 struct resource *regs, *hv_regs = NULL;
144 int syncpt_irq;
145 int err;
146
147 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
148 if (!host)
149 return -ENOMEM;
150
151 host->info = of_device_get_match_data(&pdev->dev);
152
153 if (host->info->has_hypervisor) {
154 regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vm");
155 if (!regs) {
156 dev_err(&pdev->dev, "failed to get vm registers\n");
157 return -ENXIO;
158 }
159
160 hv_regs = platform_get_resource_byname(pdev, IORESOURCE_MEM,
161 "hypervisor");
162 if (!hv_regs) {
163 dev_err(&pdev->dev,
164 "failed to get hypervisor registers\n");
165 return -ENXIO;
166 }
167 } else {
168 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
169 if (!regs) {
170 dev_err(&pdev->dev, "failed to get registers\n");
171 return -ENXIO;
172 }
173 }
174
175 syncpt_irq = platform_get_irq(pdev, 0);
176 if (syncpt_irq < 0) {
177 dev_err(&pdev->dev, "failed to get IRQ: %d\n", syncpt_irq);
178 return syncpt_irq;
179 }
180
181 mutex_init(&host->devices_lock);
182 INIT_LIST_HEAD(&host->devices);
183 INIT_LIST_HEAD(&host->list);
184 host->dev = &pdev->dev;
185
186 /* set common host1x device data */
187 platform_set_drvdata(pdev, host);
188
189 host->regs = devm_ioremap_resource(&pdev->dev, regs);
190 if (IS_ERR(host->regs))
191 return PTR_ERR(host->regs);
192
193 if (host->info->has_hypervisor) {
194 host->hv_regs = devm_ioremap_resource(&pdev->dev, hv_regs);
195 if (IS_ERR(host->hv_regs))
196 return PTR_ERR(host->hv_regs);
197 }
198
199 dma_set_mask_and_coherent(host->dev, host->info->dma_mask);
200
201 if (host->info->init) {
202 err = host->info->init(host);
203 if (err)
204 return err;
205 }
206
207 host->clk = devm_clk_get(&pdev->dev, NULL);
208 if (IS_ERR(host->clk)) {
209 dev_err(&pdev->dev, "failed to get clock\n");
210 err = PTR_ERR(host->clk);
211 return err;
212 }
213
214 host->rst = devm_reset_control_get(&pdev->dev, "host1x");
215 if (IS_ERR(host->rst)) {
216 err = PTR_ERR(host->rst);
217 dev_err(&pdev->dev, "failed to get reset: %d\n", err);
218 return err;
219 }
220
221 host->group = iommu_group_get(&pdev->dev);
222 if (host->group) {
223 struct iommu_domain_geometry *geometry;
224 unsigned long order;
225
226 host->domain = iommu_domain_alloc(&platform_bus_type);
227 if (!host->domain) {
228 err = -ENOMEM;
229 goto put_group;
230 }
231
232 err = iommu_attach_group(host->domain, host->group);
233 if (err) {
234 if (err == -ENODEV) {
235 iommu_domain_free(host->domain);
236 host->domain = NULL;
237 iommu_group_put(host->group);
238 host->group = NULL;
239 goto skip_iommu;
240 }
241
242 goto fail_free_domain;
243 }
244
245 geometry = &host->domain->geometry;
246
247 order = __ffs(host->domain->pgsize_bitmap);
248 init_iova_domain(&host->iova, 1UL << order,
249 geometry->aperture_start >> order);
250 host->iova_end = geometry->aperture_end;
251 }
252
253skip_iommu:
254 err = host1x_channel_list_init(&host->channel_list,
255 host->info->nb_channels);
256 if (err) {
257 dev_err(&pdev->dev, "failed to initialize channel list\n");
258 goto fail_detach_device;
259 }
260
261 err = clk_prepare_enable(host->clk);
262 if (err < 0) {
263 dev_err(&pdev->dev, "failed to enable clock\n");
264 goto fail_free_channels;
265 }
266
267 err = reset_control_deassert(host->rst);
268 if (err < 0) {
269 dev_err(&pdev->dev, "failed to deassert reset: %d\n", err);
270 goto fail_unprepare_disable;
271 }
272
273 err = host1x_syncpt_init(host);
274 if (err) {
275 dev_err(&pdev->dev, "failed to initialize syncpts\n");
276 goto fail_reset_assert;
277 }
278
279 err = host1x_intr_init(host, syncpt_irq);
280 if (err) {
281 dev_err(&pdev->dev, "failed to initialize interrupts\n");
282 goto fail_deinit_syncpt;
283 }
284
285 host1x_debug_init(host);
286
287 err = host1x_register(host);
288 if (err < 0)
289 goto fail_deinit_intr;
290
291 return 0;
292
293fail_deinit_intr:
294 host1x_intr_deinit(host);
295fail_deinit_syncpt:
296 host1x_syncpt_deinit(host);
297fail_reset_assert:
298 reset_control_assert(host->rst);
299fail_unprepare_disable:
300 clk_disable_unprepare(host->clk);
301fail_free_channels:
302 host1x_channel_list_free(&host->channel_list);
303fail_detach_device:
304 if (host->group && host->domain) {
305 put_iova_domain(&host->iova);
306 iommu_detach_group(host->domain, host->group);
307 }
308fail_free_domain:
309 if (host->domain)
310 iommu_domain_free(host->domain);
311put_group:
312 iommu_group_put(host->group);
313
314 return err;
315}
316
317static int host1x_remove(struct platform_device *pdev)
318{
319 struct host1x *host = platform_get_drvdata(pdev);
320
321 host1x_unregister(host);
322 host1x_intr_deinit(host);
323 host1x_syncpt_deinit(host);
324 reset_control_assert(host->rst);
325 clk_disable_unprepare(host->clk);
326
327 if (host->domain) {
328 put_iova_domain(&host->iova);
329 iommu_detach_group(host->domain, host->group);
330 iommu_domain_free(host->domain);
331 iommu_group_put(host->group);
332 }
333
334 return 0;
335}
336
337static struct platform_driver tegra_host1x_driver = {
338 .driver = {
339 .name = "tegra-host1x",
340 .of_match_table = host1x_of_match,
341 },
342 .probe = host1x_probe,
343 .remove = host1x_remove,
344};
345
346static struct platform_driver * const drivers[] = {
347 &tegra_host1x_driver,
348 &tegra_mipi_driver,
349};
350
351static int __init tegra_host1x_init(void)
352{
353 int err;
354
355 err = bus_register(&host1x_bus_type);
356 if (err < 0)
357 return err;
358
359 err = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
360 if (err < 0)
361 bus_unregister(&host1x_bus_type);
362
363 return err;
364}
365module_init(tegra_host1x_init);
366
367static void __exit tegra_host1x_exit(void)
368{
369 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
370 bus_unregister(&host1x_bus_type);
371}
372module_exit(tegra_host1x_exit);
373
374MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
375MODULE_AUTHOR("Terje Bergstrom <tbergstrom@nvidia.com>");
376MODULE_DESCRIPTION("Host1x driver for Tegra products");
377MODULE_LICENSE("GPL");