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1/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#ifndef EVERGREEND_H
25#define EVERGREEND_H
26
27#define EVERGREEN_MAX_SH_GPRS 256
28#define EVERGREEN_MAX_TEMP_GPRS 16
29#define EVERGREEN_MAX_SH_THREADS 256
30#define EVERGREEN_MAX_SH_STACK_ENTRIES 4096
31#define EVERGREEN_MAX_FRC_EOV_CNT 16384
32#define EVERGREEN_MAX_BACKENDS 8
33#define EVERGREEN_MAX_BACKENDS_MASK 0xFF
34#define EVERGREEN_MAX_SIMDS 16
35#define EVERGREEN_MAX_SIMDS_MASK 0xFFFF
36#define EVERGREEN_MAX_PIPES 8
37#define EVERGREEN_MAX_PIPES_MASK 0xFF
38#define EVERGREEN_MAX_LDS_NUM 0xFFFF
39
40#define CYPRESS_GB_ADDR_CONFIG_GOLDEN 0x02011003
41#define BARTS_GB_ADDR_CONFIG_GOLDEN 0x02011003
42#define CAYMAN_GB_ADDR_CONFIG_GOLDEN 0x02011003
43#define JUNIPER_GB_ADDR_CONFIG_GOLDEN 0x02010002
44#define REDWOOD_GB_ADDR_CONFIG_GOLDEN 0x02010002
45#define TURKS_GB_ADDR_CONFIG_GOLDEN 0x02010002
46#define CEDAR_GB_ADDR_CONFIG_GOLDEN 0x02010001
47#define CAICOS_GB_ADDR_CONFIG_GOLDEN 0x02010001
48#define SUMO_GB_ADDR_CONFIG_GOLDEN 0x02010002
49#define SUMO2_GB_ADDR_CONFIG_GOLDEN 0x02010002
50
51/* pm registers */
52#define SMC_MSG 0x20c
53#define HOST_SMC_MSG(x) ((x) << 0)
54#define HOST_SMC_MSG_MASK (0xff << 0)
55#define HOST_SMC_MSG_SHIFT 0
56#define HOST_SMC_RESP(x) ((x) << 8)
57#define HOST_SMC_RESP_MASK (0xff << 8)
58#define HOST_SMC_RESP_SHIFT 8
59#define SMC_HOST_MSG(x) ((x) << 16)
60#define SMC_HOST_MSG_MASK (0xff << 16)
61#define SMC_HOST_MSG_SHIFT 16
62#define SMC_HOST_RESP(x) ((x) << 24)
63#define SMC_HOST_RESP_MASK (0xff << 24)
64#define SMC_HOST_RESP_SHIFT 24
65
66#define DCCG_DISP_SLOW_SELECT_REG 0x4fc
67#define DCCG_DISP1_SLOW_SELECT(x) ((x) << 0)
68#define DCCG_DISP1_SLOW_SELECT_MASK (7 << 0)
69#define DCCG_DISP1_SLOW_SELECT_SHIFT 0
70#define DCCG_DISP2_SLOW_SELECT(x) ((x) << 4)
71#define DCCG_DISP2_SLOW_SELECT_MASK (7 << 4)
72#define DCCG_DISP2_SLOW_SELECT_SHIFT 4
73
74#define CG_SPLL_FUNC_CNTL 0x600
75#define SPLL_RESET (1 << 0)
76#define SPLL_SLEEP (1 << 1)
77#define SPLL_BYPASS_EN (1 << 3)
78#define SPLL_REF_DIV(x) ((x) << 4)
79#define SPLL_REF_DIV_MASK (0x3f << 4)
80#define SPLL_PDIV_A(x) ((x) << 20)
81#define SPLL_PDIV_A_MASK (0x7f << 20)
82#define CG_SPLL_FUNC_CNTL_2 0x604
83#define SCLK_MUX_SEL(x) ((x) << 0)
84#define SCLK_MUX_SEL_MASK (0x1ff << 0)
85#define SCLK_MUX_UPDATE (1 << 26)
86#define CG_SPLL_FUNC_CNTL_3 0x608
87#define SPLL_FB_DIV(x) ((x) << 0)
88#define SPLL_FB_DIV_MASK (0x3ffffff << 0)
89#define SPLL_DITHEN (1 << 28)
90#define CG_SPLL_STATUS 0x60c
91#define SPLL_CHG_STATUS (1 << 1)
92
93#define MPLL_CNTL_MODE 0x61c
94# define MPLL_MCLK_SEL (1 << 11)
95# define SS_SSEN (1 << 24)
96# define SS_DSMODE_EN (1 << 25)
97
98#define MPLL_AD_FUNC_CNTL 0x624
99#define CLKF(x) ((x) << 0)
100#define CLKF_MASK (0x7f << 0)
101#define CLKR(x) ((x) << 7)
102#define CLKR_MASK (0x1f << 7)
103#define CLKFRAC(x) ((x) << 12)
104#define CLKFRAC_MASK (0x1f << 12)
105#define YCLK_POST_DIV(x) ((x) << 17)
106#define YCLK_POST_DIV_MASK (3 << 17)
107#define IBIAS(x) ((x) << 20)
108#define IBIAS_MASK (0x3ff << 20)
109#define RESET (1 << 30)
110#define PDNB (1 << 31)
111#define MPLL_AD_FUNC_CNTL_2 0x628
112#define BYPASS (1 << 19)
113#define BIAS_GEN_PDNB (1 << 24)
114#define RESET_EN (1 << 25)
115#define VCO_MODE (1 << 29)
116#define MPLL_DQ_FUNC_CNTL 0x62c
117#define MPLL_DQ_FUNC_CNTL_2 0x630
118
119#define GENERAL_PWRMGT 0x63c
120# define GLOBAL_PWRMGT_EN (1 << 0)
121# define STATIC_PM_EN (1 << 1)
122# define THERMAL_PROTECTION_DIS (1 << 2)
123# define THERMAL_PROTECTION_TYPE (1 << 3)
124# define ENABLE_GEN2PCIE (1 << 4)
125# define ENABLE_GEN2XSP (1 << 5)
126# define SW_SMIO_INDEX(x) ((x) << 6)
127# define SW_SMIO_INDEX_MASK (3 << 6)
128# define SW_SMIO_INDEX_SHIFT 6
129# define LOW_VOLT_D2_ACPI (1 << 8)
130# define LOW_VOLT_D3_ACPI (1 << 9)
131# define VOLT_PWRMGT_EN (1 << 10)
132# define BACKBIAS_PAD_EN (1 << 18)
133# define BACKBIAS_VALUE (1 << 19)
134# define DYN_SPREAD_SPECTRUM_EN (1 << 23)
135# define AC_DC_SW (1 << 24)
136
137#define SCLK_PWRMGT_CNTL 0x644
138# define SCLK_PWRMGT_OFF (1 << 0)
139# define SCLK_LOW_D1 (1 << 1)
140# define FIR_RESET (1 << 4)
141# define FIR_FORCE_TREND_SEL (1 << 5)
142# define FIR_TREND_MODE (1 << 6)
143# define DYN_GFX_CLK_OFF_EN (1 << 7)
144# define GFX_CLK_FORCE_ON (1 << 8)
145# define GFX_CLK_REQUEST_OFF (1 << 9)
146# define GFX_CLK_FORCE_OFF (1 << 10)
147# define GFX_CLK_OFF_ACPI_D1 (1 << 11)
148# define GFX_CLK_OFF_ACPI_D2 (1 << 12)
149# define GFX_CLK_OFF_ACPI_D3 (1 << 13)
150# define DYN_LIGHT_SLEEP_EN (1 << 14)
151#define MCLK_PWRMGT_CNTL 0x648
152# define DLL_SPEED(x) ((x) << 0)
153# define DLL_SPEED_MASK (0x1f << 0)
154# define MPLL_PWRMGT_OFF (1 << 5)
155# define DLL_READY (1 << 6)
156# define MC_INT_CNTL (1 << 7)
157# define MRDCKA0_PDNB (1 << 8)
158# define MRDCKA1_PDNB (1 << 9)
159# define MRDCKB0_PDNB (1 << 10)
160# define MRDCKB1_PDNB (1 << 11)
161# define MRDCKC0_PDNB (1 << 12)
162# define MRDCKC1_PDNB (1 << 13)
163# define MRDCKD0_PDNB (1 << 14)
164# define MRDCKD1_PDNB (1 << 15)
165# define MRDCKA0_RESET (1 << 16)
166# define MRDCKA1_RESET (1 << 17)
167# define MRDCKB0_RESET (1 << 18)
168# define MRDCKB1_RESET (1 << 19)
169# define MRDCKC0_RESET (1 << 20)
170# define MRDCKC1_RESET (1 << 21)
171# define MRDCKD0_RESET (1 << 22)
172# define MRDCKD1_RESET (1 << 23)
173# define DLL_READY_READ (1 << 24)
174# define USE_DISPLAY_GAP (1 << 25)
175# define USE_DISPLAY_URGENT_NORMAL (1 << 26)
176# define MPLL_TURNOFF_D2 (1 << 28)
177#define DLL_CNTL 0x64c
178# define MRDCKA0_BYPASS (1 << 24)
179# define MRDCKA1_BYPASS (1 << 25)
180# define MRDCKB0_BYPASS (1 << 26)
181# define MRDCKB1_BYPASS (1 << 27)
182# define MRDCKC0_BYPASS (1 << 28)
183# define MRDCKC1_BYPASS (1 << 29)
184# define MRDCKD0_BYPASS (1 << 30)
185# define MRDCKD1_BYPASS (1 << 31)
186
187#define CG_AT 0x6d4
188# define CG_R(x) ((x) << 0)
189# define CG_R_MASK (0xffff << 0)
190# define CG_L(x) ((x) << 16)
191# define CG_L_MASK (0xffff << 16)
192
193#define CG_DISPLAY_GAP_CNTL 0x714
194# define DISP1_GAP(x) ((x) << 0)
195# define DISP1_GAP_MASK (3 << 0)
196# define DISP2_GAP(x) ((x) << 2)
197# define DISP2_GAP_MASK (3 << 2)
198# define VBI_TIMER_COUNT(x) ((x) << 4)
199# define VBI_TIMER_COUNT_MASK (0x3fff << 4)
200# define VBI_TIMER_UNIT(x) ((x) << 20)
201# define VBI_TIMER_UNIT_MASK (7 << 20)
202# define DISP1_GAP_MCHG(x) ((x) << 24)
203# define DISP1_GAP_MCHG_MASK (3 << 24)
204# define DISP2_GAP_MCHG(x) ((x) << 26)
205# define DISP2_GAP_MCHG_MASK (3 << 26)
206
207#define CG_BIF_REQ_AND_RSP 0x7f4
208#define CG_CLIENT_REQ(x) ((x) << 0)
209#define CG_CLIENT_REQ_MASK (0xff << 0)
210#define CG_CLIENT_REQ_SHIFT 0
211#define CG_CLIENT_RESP(x) ((x) << 8)
212#define CG_CLIENT_RESP_MASK (0xff << 8)
213#define CG_CLIENT_RESP_SHIFT 8
214#define CLIENT_CG_REQ(x) ((x) << 16)
215#define CLIENT_CG_REQ_MASK (0xff << 16)
216#define CLIENT_CG_REQ_SHIFT 16
217#define CLIENT_CG_RESP(x) ((x) << 24)
218#define CLIENT_CG_RESP_MASK (0xff << 24)
219#define CLIENT_CG_RESP_SHIFT 24
220
221#define CG_SPLL_SPREAD_SPECTRUM 0x790
222#define SSEN (1 << 0)
223#define CG_SPLL_SPREAD_SPECTRUM_2 0x794
224
225#define MPLL_SS1 0x85c
226#define CLKV(x) ((x) << 0)
227#define CLKV_MASK (0x3ffffff << 0)
228#define MPLL_SS2 0x860
229#define CLKS(x) ((x) << 0)
230#define CLKS_MASK (0xfff << 0)
231
232#define CG_IND_ADDR 0x8f8
233#define CG_IND_DATA 0x8fc
234/* CGIND regs */
235#define CG_CGTT_LOCAL_0 0x00
236#define CG_CGTT_LOCAL_1 0x01
237#define CG_CGTT_LOCAL_2 0x02
238#define CG_CGTT_LOCAL_3 0x03
239#define CG_CGLS_TILE_0 0x20
240#define CG_CGLS_TILE_1 0x21
241#define CG_CGLS_TILE_2 0x22
242#define CG_CGLS_TILE_3 0x23
243#define CG_CGLS_TILE_4 0x24
244#define CG_CGLS_TILE_5 0x25
245#define CG_CGLS_TILE_6 0x26
246#define CG_CGLS_TILE_7 0x27
247#define CG_CGLS_TILE_8 0x28
248#define CG_CGLS_TILE_9 0x29
249#define CG_CGLS_TILE_10 0x2a
250#define CG_CGLS_TILE_11 0x2b
251
252#define VM_L2_CG 0x15c0
253
254#define MC_CONFIG 0x2000
255
256#define MC_CONFIG_MCD 0x20a0
257#define MC_CG_CONFIG_MCD 0x20a4
258#define MC_RD_ENABLE_MCD(x) ((x) << 8)
259#define MC_RD_ENABLE_MCD_MASK (7 << 8)
260
261#define MC_HUB_MISC_HUB_CG 0x20b8
262#define MC_HUB_MISC_VM_CG 0x20bc
263#define MC_HUB_MISC_SIP_CG 0x20c0
264
265#define MC_XPB_CLK_GAT 0x2478
266
267#define MC_CG_CONFIG 0x25bc
268#define MC_RD_ENABLE(x) ((x) << 4)
269#define MC_RD_ENABLE_MASK (3 << 4)
270
271#define MC_CITF_MISC_RD_CG 0x2648
272#define MC_CITF_MISC_WR_CG 0x264c
273#define MC_CITF_MISC_VM_CG 0x2650
274# define MEM_LS_ENABLE (1 << 19)
275
276#define MC_ARB_BURST_TIME 0x2808
277#define STATE0(x) ((x) << 0)
278#define STATE0_MASK (0x1f << 0)
279#define STATE1(x) ((x) << 5)
280#define STATE1_MASK (0x1f << 5)
281#define STATE2(x) ((x) << 10)
282#define STATE2_MASK (0x1f << 10)
283#define STATE3(x) ((x) << 15)
284#define STATE3_MASK (0x1f << 15)
285
286#define MC_SEQ_RAS_TIMING 0x28a0
287#define MC_SEQ_CAS_TIMING 0x28a4
288#define MC_SEQ_MISC_TIMING 0x28a8
289#define MC_SEQ_MISC_TIMING2 0x28ac
290
291#define MC_SEQ_RD_CTL_D0 0x28b4
292#define MC_SEQ_RD_CTL_D1 0x28b8
293#define MC_SEQ_WR_CTL_D0 0x28bc
294#define MC_SEQ_WR_CTL_D1 0x28c0
295
296#define MC_SEQ_STATUS_M 0x29f4
297# define PMG_PWRSTATE (1 << 16)
298
299#define MC_SEQ_MISC1 0x2a04
300#define MC_SEQ_RESERVE_M 0x2a08
301#define MC_PMG_CMD_EMRS 0x2a0c
302
303#define MC_SEQ_MISC3 0x2a2c
304
305#define MC_SEQ_MISC5 0x2a54
306#define MC_SEQ_MISC6 0x2a58
307
308#define MC_SEQ_MISC7 0x2a64
309
310#define MC_SEQ_CG 0x2a68
311#define CG_SEQ_REQ(x) ((x) << 0)
312#define CG_SEQ_REQ_MASK (0xff << 0)
313#define CG_SEQ_REQ_SHIFT 0
314#define CG_SEQ_RESP(x) ((x) << 8)
315#define CG_SEQ_RESP_MASK (0xff << 8)
316#define CG_SEQ_RESP_SHIFT 8
317#define SEQ_CG_REQ(x) ((x) << 16)
318#define SEQ_CG_REQ_MASK (0xff << 16)
319#define SEQ_CG_REQ_SHIFT 16
320#define SEQ_CG_RESP(x) ((x) << 24)
321#define SEQ_CG_RESP_MASK (0xff << 24)
322#define SEQ_CG_RESP_SHIFT 24
323#define MC_SEQ_RAS_TIMING_LP 0x2a6c
324#define MC_SEQ_CAS_TIMING_LP 0x2a70
325#define MC_SEQ_MISC_TIMING_LP 0x2a74
326#define MC_SEQ_MISC_TIMING2_LP 0x2a78
327#define MC_SEQ_WR_CTL_D0_LP 0x2a7c
328#define MC_SEQ_WR_CTL_D1_LP 0x2a80
329#define MC_SEQ_PMG_CMD_EMRS_LP 0x2a84
330#define MC_SEQ_PMG_CMD_MRS_LP 0x2a88
331
332#define MC_PMG_CMD_MRS 0x2aac
333
334#define MC_SEQ_RD_CTL_D0_LP 0x2b1c
335#define MC_SEQ_RD_CTL_D1_LP 0x2b20
336
337#define MC_PMG_CMD_MRS1 0x2b44
338#define MC_SEQ_PMG_CMD_MRS1_LP 0x2b48
339
340#define CGTS_SM_CTRL_REG 0x9150
341
342/* Registers */
343
344#define RCU_IND_INDEX 0x100
345#define RCU_IND_DATA 0x104
346
347/* discrete uvd clocks */
348#define CG_UPLL_FUNC_CNTL 0x718
349# define UPLL_RESET_MASK 0x00000001
350# define UPLL_SLEEP_MASK 0x00000002
351# define UPLL_BYPASS_EN_MASK 0x00000004
352# define UPLL_CTLREQ_MASK 0x00000008
353# define UPLL_REF_DIV_MASK 0x003F0000
354# define UPLL_VCO_MODE_MASK 0x00000200
355# define UPLL_CTLACK_MASK 0x40000000
356# define UPLL_CTLACK2_MASK 0x80000000
357#define CG_UPLL_FUNC_CNTL_2 0x71c
358# define UPLL_PDIV_A(x) ((x) << 0)
359# define UPLL_PDIV_A_MASK 0x0000007F
360# define UPLL_PDIV_B(x) ((x) << 8)
361# define UPLL_PDIV_B_MASK 0x00007F00
362# define VCLK_SRC_SEL(x) ((x) << 20)
363# define VCLK_SRC_SEL_MASK 0x01F00000
364# define DCLK_SRC_SEL(x) ((x) << 25)
365# define DCLK_SRC_SEL_MASK 0x3E000000
366#define CG_UPLL_FUNC_CNTL_3 0x720
367# define UPLL_FB_DIV(x) ((x) << 0)
368# define UPLL_FB_DIV_MASK 0x01FFFFFF
369#define CG_UPLL_FUNC_CNTL_4 0x854
370# define UPLL_SPARE_ISPARE9 0x00020000
371#define CG_UPLL_SPREAD_SPECTRUM 0x79c
372# define SSEN_MASK 0x00000001
373
374/* fusion uvd clocks */
375#define CG_DCLK_CNTL 0x610
376# define DCLK_DIVIDER_MASK 0x7f
377# define DCLK_DIR_CNTL_EN (1 << 8)
378#define CG_DCLK_STATUS 0x614
379# define DCLK_STATUS (1 << 0)
380#define CG_VCLK_CNTL 0x618
381#define CG_VCLK_STATUS 0x61c
382#define CG_SCRATCH1 0x820
383
384#define RLC_CNTL 0x3f00
385# define RLC_ENABLE (1 << 0)
386# define GFX_POWER_GATING_ENABLE (1 << 7)
387# define GFX_POWER_GATING_SRC (1 << 8)
388# define DYN_PER_SIMD_PG_ENABLE (1 << 27)
389# define LB_CNT_SPIM_ACTIVE (1 << 30)
390# define LOAD_BALANCE_ENABLE (1 << 31)
391
392#define RLC_HB_BASE 0x3f10
393#define RLC_HB_CNTL 0x3f0c
394#define RLC_HB_RPTR 0x3f20
395#define RLC_HB_WPTR 0x3f1c
396#define RLC_HB_WPTR_LSB_ADDR 0x3f14
397#define RLC_HB_WPTR_MSB_ADDR 0x3f18
398#define RLC_MC_CNTL 0x3f44
399#define RLC_UCODE_CNTL 0x3f48
400#define RLC_UCODE_ADDR 0x3f2c
401#define RLC_UCODE_DATA 0x3f30
402
403/* new for TN */
404#define TN_RLC_SAVE_AND_RESTORE_BASE 0x3f10
405#define TN_RLC_LB_CNTR_MAX 0x3f14
406#define TN_RLC_LB_CNTR_INIT 0x3f18
407#define TN_RLC_CLEAR_STATE_RESTORE_BASE 0x3f20
408#define TN_RLC_LB_INIT_SIMD_MASK 0x3fe4
409#define TN_RLC_LB_ALWAYS_ACTIVE_SIMD_MASK 0x3fe8
410#define TN_RLC_LB_PARAMS 0x3fec
411
412#define GRBM_GFX_INDEX 0x802C
413#define INSTANCE_INDEX(x) ((x) << 0)
414#define SE_INDEX(x) ((x) << 16)
415#define INSTANCE_BROADCAST_WRITES (1 << 30)
416#define SE_BROADCAST_WRITES (1 << 31)
417#define RLC_GFX_INDEX 0x3fC4
418#define CC_GC_SHADER_PIPE_CONFIG 0x8950
419#define WRITE_DIS (1 << 0)
420#define CC_RB_BACKEND_DISABLE 0x98F4
421#define BACKEND_DISABLE(x) ((x) << 16)
422#define GB_ADDR_CONFIG 0x98F8
423#define NUM_PIPES(x) ((x) << 0)
424#define NUM_PIPES_MASK 0x0000000f
425#define PIPE_INTERLEAVE_SIZE(x) ((x) << 4)
426#define BANK_INTERLEAVE_SIZE(x) ((x) << 8)
427#define NUM_SHADER_ENGINES(x) ((x) << 12)
428#define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16)
429#define NUM_GPUS(x) ((x) << 20)
430#define MULTI_GPU_TILE_SIZE(x) ((x) << 24)
431#define ROW_SIZE(x) ((x) << 28)
432#define GB_BACKEND_MAP 0x98FC
433#define DMIF_ADDR_CONFIG 0xBD4
434#define HDP_ADDR_CONFIG 0x2F48
435#define HDP_MISC_CNTL 0x2F4C
436#define HDP_FLUSH_INVALIDATE_CACHE (1 << 0)
437
438#define CC_SYS_RB_BACKEND_DISABLE 0x3F88
439#define GC_USER_RB_BACKEND_DISABLE 0x9B7C
440
441#define CGTS_SYS_TCC_DISABLE 0x3F90
442#define CGTS_TCC_DISABLE 0x9148
443#define CGTS_USER_SYS_TCC_DISABLE 0x3F94
444#define CGTS_USER_TCC_DISABLE 0x914C
445
446#define CONFIG_MEMSIZE 0x5428
447
448#define BIF_FB_EN 0x5490
449#define FB_READ_EN (1 << 0)
450#define FB_WRITE_EN (1 << 1)
451
452#define CP_STRMOUT_CNTL 0x84FC
453
454#define CP_COHER_CNTL 0x85F0
455#define CP_COHER_SIZE 0x85F4
456#define CP_COHER_BASE 0x85F8
457#define CP_STALLED_STAT1 0x8674
458#define CP_STALLED_STAT2 0x8678
459#define CP_BUSY_STAT 0x867C
460#define CP_STAT 0x8680
461#define CP_ME_CNTL 0x86D8
462#define CP_ME_HALT (1 << 28)
463#define CP_PFP_HALT (1 << 26)
464#define CP_ME_RAM_DATA 0xC160
465#define CP_ME_RAM_RADDR 0xC158
466#define CP_ME_RAM_WADDR 0xC15C
467#define CP_MEQ_THRESHOLDS 0x8764
468#define STQ_SPLIT(x) ((x) << 0)
469#define CP_PERFMON_CNTL 0x87FC
470#define CP_PFP_UCODE_ADDR 0xC150
471#define CP_PFP_UCODE_DATA 0xC154
472#define CP_QUEUE_THRESHOLDS 0x8760
473#define ROQ_IB1_START(x) ((x) << 0)
474#define ROQ_IB2_START(x) ((x) << 8)
475#define CP_RB_BASE 0xC100
476#define CP_RB_CNTL 0xC104
477#define RB_BUFSZ(x) ((x) << 0)
478#define RB_BLKSZ(x) ((x) << 8)
479#define RB_NO_UPDATE (1 << 27)
480#define RB_RPTR_WR_ENA (1 << 31)
481#define BUF_SWAP_32BIT (2 << 16)
482#define CP_RB_RPTR 0x8700
483#define CP_RB_RPTR_ADDR 0xC10C
484#define RB_RPTR_SWAP(x) ((x) << 0)
485#define CP_RB_RPTR_ADDR_HI 0xC110
486#define CP_RB_RPTR_WR 0xC108
487#define CP_RB_WPTR 0xC114
488#define CP_RB_WPTR_ADDR 0xC118
489#define CP_RB_WPTR_ADDR_HI 0xC11C
490#define CP_RB_WPTR_DELAY 0x8704
491#define CP_SEM_WAIT_TIMER 0x85BC
492#define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8
493#define CP_DEBUG 0xC1FC
494
495/* Audio clocks */
496#define DCCG_AUDIO_DTO_SOURCE 0x05ac
497# define DCCG_AUDIO_DTO0_SOURCE_SEL(x) ((x) << 0) /* crtc0 - crtc5 */
498# define DCCG_AUDIO_DTO_SEL (1 << 4) /* 0=dto0 1=dto1 */
499
500#define DCCG_AUDIO_DTO0_PHASE 0x05b0
501#define DCCG_AUDIO_DTO0_MODULE 0x05b4
502#define DCCG_AUDIO_DTO0_LOAD 0x05b8
503#define DCCG_AUDIO_DTO0_CNTL 0x05bc
504# define DCCG_AUDIO_DTO_WALLCLOCK_RATIO(x) (((x) & 7) << 0)
505# define DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK 7
506# define DCCG_AUDIO_DTO_WALLCLOCK_RATIO_SHIFT 0
507
508#define DCCG_AUDIO_DTO1_PHASE 0x05c0
509#define DCCG_AUDIO_DTO1_MODULE 0x05c4
510#define DCCG_AUDIO_DTO1_LOAD 0x05c8
511#define DCCG_AUDIO_DTO1_CNTL 0x05cc
512# define DCCG_AUDIO_DTO1_USE_512FBR_DTO (1 << 3)
513
514#define DCE41_DENTIST_DISPCLK_CNTL 0x049c
515# define DENTIST_DPREFCLK_WDIVIDER(x) (((x) & 0x7f) << 24)
516# define DENTIST_DPREFCLK_WDIVIDER_MASK (0x7f << 24)
517# define DENTIST_DPREFCLK_WDIVIDER_SHIFT 24
518
519/* DCE 4.0 AFMT */
520#define HDMI_CONTROL 0x7030
521# define HDMI_KEEPOUT_MODE (1 << 0)
522# define HDMI_PACKET_GEN_VERSION (1 << 4) /* 0 = r6xx compat */
523# define HDMI_ERROR_ACK (1 << 8)
524# define HDMI_ERROR_MASK (1 << 9)
525# define HDMI_DEEP_COLOR_ENABLE (1 << 24)
526# define HDMI_DEEP_COLOR_DEPTH(x) (((x) & 3) << 28)
527# define HDMI_24BIT_DEEP_COLOR 0
528# define HDMI_30BIT_DEEP_COLOR 1
529# define HDMI_36BIT_DEEP_COLOR 2
530# define HDMI_DEEP_COLOR_DEPTH_MASK (3 << 28)
531#define HDMI_STATUS 0x7034
532# define HDMI_ACTIVE_AVMUTE (1 << 0)
533# define HDMI_AUDIO_PACKET_ERROR (1 << 16)
534# define HDMI_VBI_PACKET_ERROR (1 << 20)
535#define HDMI_AUDIO_PACKET_CONTROL 0x7038
536# define HDMI_AUDIO_DELAY_EN(x) (((x) & 3) << 4)
537# define HDMI_AUDIO_PACKETS_PER_LINE(x) (((x) & 0x1f) << 16)
538#define HDMI_ACR_PACKET_CONTROL 0x703c
539# define HDMI_ACR_SEND (1 << 0)
540# define HDMI_ACR_CONT (1 << 1)
541# define HDMI_ACR_SELECT(x) (((x) & 3) << 4)
542# define HDMI_ACR_HW 0
543# define HDMI_ACR_32 1
544# define HDMI_ACR_44 2
545# define HDMI_ACR_48 3
546# define HDMI_ACR_SOURCE (1 << 8) /* 0 - hw; 1 - cts value */
547# define HDMI_ACR_AUTO_SEND (1 << 12)
548# define HDMI_ACR_N_MULTIPLE(x) (((x) & 7) << 16)
549# define HDMI_ACR_X1 1
550# define HDMI_ACR_X2 2
551# define HDMI_ACR_X4 4
552# define HDMI_ACR_AUDIO_PRIORITY (1 << 31)
553#define HDMI_VBI_PACKET_CONTROL 0x7040
554# define HDMI_NULL_SEND (1 << 0)
555# define HDMI_GC_SEND (1 << 4)
556# define HDMI_GC_CONT (1 << 5) /* 0 - once; 1 - every frame */
557#define HDMI_INFOFRAME_CONTROL0 0x7044
558# define HDMI_AVI_INFO_SEND (1 << 0)
559# define HDMI_AVI_INFO_CONT (1 << 1)
560# define HDMI_AUDIO_INFO_SEND (1 << 4)
561# define HDMI_AUDIO_INFO_CONT (1 << 5)
562# define HDMI_MPEG_INFO_SEND (1 << 8)
563# define HDMI_MPEG_INFO_CONT (1 << 9)
564#define HDMI_INFOFRAME_CONTROL1 0x7048
565# define HDMI_AVI_INFO_LINE(x) (((x) & 0x3f) << 0)
566# define HDMI_AVI_INFO_LINE_MASK (0x3f << 0)
567# define HDMI_AUDIO_INFO_LINE(x) (((x) & 0x3f) << 8)
568# define HDMI_MPEG_INFO_LINE(x) (((x) & 0x3f) << 16)
569#define HDMI_GENERIC_PACKET_CONTROL 0x704c
570# define HDMI_GENERIC0_SEND (1 << 0)
571# define HDMI_GENERIC0_CONT (1 << 1)
572# define HDMI_GENERIC1_SEND (1 << 4)
573# define HDMI_GENERIC1_CONT (1 << 5)
574# define HDMI_GENERIC0_LINE(x) (((x) & 0x3f) << 16)
575# define HDMI_GENERIC1_LINE(x) (((x) & 0x3f) << 24)
576#define HDMI_GC 0x7058
577# define HDMI_GC_AVMUTE (1 << 0)
578# define HDMI_GC_AVMUTE_CONT (1 << 2)
579#define AFMT_AUDIO_PACKET_CONTROL2 0x705c
580# define AFMT_AUDIO_LAYOUT_OVRD (1 << 0)
581# define AFMT_AUDIO_LAYOUT_SELECT (1 << 1)
582# define AFMT_60958_CS_SOURCE (1 << 4)
583# define AFMT_AUDIO_CHANNEL_ENABLE(x) (((x) & 0xff) << 8)
584# define AFMT_DP_AUDIO_STREAM_ID(x) (((x) & 0xff) << 16)
585#define AFMT_AVI_INFO0 0x7084
586# define AFMT_AVI_INFO_CHECKSUM(x) (((x) & 0xff) << 0)
587# define AFMT_AVI_INFO_S(x) (((x) & 3) << 8)
588# define AFMT_AVI_INFO_B(x) (((x) & 3) << 10)
589# define AFMT_AVI_INFO_A(x) (((x) & 1) << 12)
590# define AFMT_AVI_INFO_Y(x) (((x) & 3) << 13)
591# define AFMT_AVI_INFO_Y_RGB 0
592# define AFMT_AVI_INFO_Y_YCBCR422 1
593# define AFMT_AVI_INFO_Y_YCBCR444 2
594# define AFMT_AVI_INFO_Y_A_B_S(x) (((x) & 0xff) << 8)
595# define AFMT_AVI_INFO_R(x) (((x) & 0xf) << 16)
596# define AFMT_AVI_INFO_M(x) (((x) & 0x3) << 20)
597# define AFMT_AVI_INFO_C(x) (((x) & 0x3) << 22)
598# define AFMT_AVI_INFO_C_M_R(x) (((x) & 0xff) << 16)
599# define AFMT_AVI_INFO_SC(x) (((x) & 0x3) << 24)
600# define AFMT_AVI_INFO_Q(x) (((x) & 0x3) << 26)
601# define AFMT_AVI_INFO_EC(x) (((x) & 0x3) << 28)
602# define AFMT_AVI_INFO_ITC(x) (((x) & 0x1) << 31)
603# define AFMT_AVI_INFO_ITC_EC_Q_SC(x) (((x) & 0xff) << 24)
604#define AFMT_AVI_INFO1 0x7088
605# define AFMT_AVI_INFO_VIC(x) (((x) & 0x7f) << 0) /* don't use avi infoframe v1 */
606# define AFMT_AVI_INFO_PR(x) (((x) & 0xf) << 8) /* don't use avi infoframe v1 */
607# define AFMT_AVI_INFO_CN(x) (((x) & 0x3) << 12)
608# define AFMT_AVI_INFO_YQ(x) (((x) & 0x3) << 14)
609# define AFMT_AVI_INFO_TOP(x) (((x) & 0xffff) << 16)
610#define AFMT_AVI_INFO2 0x708c
611# define AFMT_AVI_INFO_BOTTOM(x) (((x) & 0xffff) << 0)
612# define AFMT_AVI_INFO_LEFT(x) (((x) & 0xffff) << 16)
613#define AFMT_AVI_INFO3 0x7090
614# define AFMT_AVI_INFO_RIGHT(x) (((x) & 0xffff) << 0)
615# define AFMT_AVI_INFO_VERSION(x) (((x) & 3) << 24)
616#define AFMT_MPEG_INFO0 0x7094
617# define AFMT_MPEG_INFO_CHECKSUM(x) (((x) & 0xff) << 0)
618# define AFMT_MPEG_INFO_MB0(x) (((x) & 0xff) << 8)
619# define AFMT_MPEG_INFO_MB1(x) (((x) & 0xff) << 16)
620# define AFMT_MPEG_INFO_MB2(x) (((x) & 0xff) << 24)
621#define AFMT_MPEG_INFO1 0x7098
622# define AFMT_MPEG_INFO_MB3(x) (((x) & 0xff) << 0)
623# define AFMT_MPEG_INFO_MF(x) (((x) & 3) << 8)
624# define AFMT_MPEG_INFO_FR(x) (((x) & 1) << 12)
625#define AFMT_GENERIC0_HDR 0x709c
626#define AFMT_GENERIC0_0 0x70a0
627#define AFMT_GENERIC0_1 0x70a4
628#define AFMT_GENERIC0_2 0x70a8
629#define AFMT_GENERIC0_3 0x70ac
630#define AFMT_GENERIC0_4 0x70b0
631#define AFMT_GENERIC0_5 0x70b4
632#define AFMT_GENERIC0_6 0x70b8
633#define AFMT_GENERIC1_HDR 0x70bc
634#define AFMT_GENERIC1_0 0x70c0
635#define AFMT_GENERIC1_1 0x70c4
636#define AFMT_GENERIC1_2 0x70c8
637#define AFMT_GENERIC1_3 0x70cc
638#define AFMT_GENERIC1_4 0x70d0
639#define AFMT_GENERIC1_5 0x70d4
640#define AFMT_GENERIC1_6 0x70d8
641#define HDMI_ACR_32_0 0x70dc
642# define HDMI_ACR_CTS_32(x) (((x) & 0xfffff) << 12)
643#define HDMI_ACR_32_1 0x70e0
644# define HDMI_ACR_N_32(x) (((x) & 0xfffff) << 0)
645#define HDMI_ACR_44_0 0x70e4
646# define HDMI_ACR_CTS_44(x) (((x) & 0xfffff) << 12)
647#define HDMI_ACR_44_1 0x70e8
648# define HDMI_ACR_N_44(x) (((x) & 0xfffff) << 0)
649#define HDMI_ACR_48_0 0x70ec
650# define HDMI_ACR_CTS_48(x) (((x) & 0xfffff) << 12)
651#define HDMI_ACR_48_1 0x70f0
652# define HDMI_ACR_N_48(x) (((x) & 0xfffff) << 0)
653#define HDMI_ACR_STATUS_0 0x70f4
654#define HDMI_ACR_STATUS_1 0x70f8
655#define AFMT_AUDIO_INFO0 0x70fc
656# define AFMT_AUDIO_INFO_CHECKSUM(x) (((x) & 0xff) << 0)
657# define AFMT_AUDIO_INFO_CC(x) (((x) & 7) << 8)
658# define AFMT_AUDIO_INFO_CT(x) (((x) & 0xf) << 11)
659# define AFMT_AUDIO_INFO_CHECKSUM_OFFSET(x) (((x) & 0xff) << 16)
660# define AFMT_AUDIO_INFO_CXT(x) (((x) & 0x1f) << 24)
661#define AFMT_AUDIO_INFO1 0x7100
662# define AFMT_AUDIO_INFO_CA(x) (((x) & 0xff) << 0)
663# define AFMT_AUDIO_INFO_LSV(x) (((x) & 0xf) << 11)
664# define AFMT_AUDIO_INFO_DM_INH(x) (((x) & 1) << 15)
665# define AFMT_AUDIO_INFO_DM_INH_LSV(x) (((x) & 0xff) << 8)
666# define AFMT_AUDIO_INFO_LFEBPL(x) (((x) & 3) << 16)
667#define AFMT_60958_0 0x7104
668# define AFMT_60958_CS_A(x) (((x) & 1) << 0)
669# define AFMT_60958_CS_B(x) (((x) & 1) << 1)
670# define AFMT_60958_CS_C(x) (((x) & 1) << 2)
671# define AFMT_60958_CS_D(x) (((x) & 3) << 3)
672# define AFMT_60958_CS_MODE(x) (((x) & 3) << 6)
673# define AFMT_60958_CS_CATEGORY_CODE(x) (((x) & 0xff) << 8)
674# define AFMT_60958_CS_SOURCE_NUMBER(x) (((x) & 0xf) << 16)
675# define AFMT_60958_CS_CHANNEL_NUMBER_L(x) (((x) & 0xf) << 20)
676# define AFMT_60958_CS_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 24)
677# define AFMT_60958_CS_CLOCK_ACCURACY(x) (((x) & 3) << 28)
678#define AFMT_60958_1 0x7108
679# define AFMT_60958_CS_WORD_LENGTH(x) (((x) & 0xf) << 0)
680# define AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 4)
681# define AFMT_60958_CS_VALID_L(x) (((x) & 1) << 16)
682# define AFMT_60958_CS_VALID_R(x) (((x) & 1) << 18)
683# define AFMT_60958_CS_CHANNEL_NUMBER_R(x) (((x) & 0xf) << 20)
684#define AFMT_AUDIO_CRC_CONTROL 0x710c
685# define AFMT_AUDIO_CRC_EN (1 << 0)
686#define AFMT_RAMP_CONTROL0 0x7110
687# define AFMT_RAMP_MAX_COUNT(x) (((x) & 0xffffff) << 0)
688# define AFMT_RAMP_DATA_SIGN (1 << 31)
689#define AFMT_RAMP_CONTROL1 0x7114
690# define AFMT_RAMP_MIN_COUNT(x) (((x) & 0xffffff) << 0)
691# define AFMT_AUDIO_TEST_CH_DISABLE(x) (((x) & 0xff) << 24)
692#define AFMT_RAMP_CONTROL2 0x7118
693# define AFMT_RAMP_INC_COUNT(x) (((x) & 0xffffff) << 0)
694#define AFMT_RAMP_CONTROL3 0x711c
695# define AFMT_RAMP_DEC_COUNT(x) (((x) & 0xffffff) << 0)
696#define AFMT_60958_2 0x7120
697# define AFMT_60958_CS_CHANNEL_NUMBER_2(x) (((x) & 0xf) << 0)
698# define AFMT_60958_CS_CHANNEL_NUMBER_3(x) (((x) & 0xf) << 4)
699# define AFMT_60958_CS_CHANNEL_NUMBER_4(x) (((x) & 0xf) << 8)
700# define AFMT_60958_CS_CHANNEL_NUMBER_5(x) (((x) & 0xf) << 12)
701# define AFMT_60958_CS_CHANNEL_NUMBER_6(x) (((x) & 0xf) << 16)
702# define AFMT_60958_CS_CHANNEL_NUMBER_7(x) (((x) & 0xf) << 20)
703#define AFMT_STATUS 0x7128
704# define AFMT_AUDIO_ENABLE (1 << 4)
705# define AFMT_AUDIO_HBR_ENABLE (1 << 8)
706# define AFMT_AZ_FORMAT_WTRIG (1 << 28)
707# define AFMT_AZ_FORMAT_WTRIG_INT (1 << 29)
708# define AFMT_AZ_AUDIO_ENABLE_CHG (1 << 30)
709#define AFMT_AUDIO_PACKET_CONTROL 0x712c
710# define AFMT_AUDIO_SAMPLE_SEND (1 << 0)
711# define AFMT_RESET_FIFO_WHEN_AUDIO_DIS (1 << 11) /* set to 1 */
712# define AFMT_AUDIO_TEST_EN (1 << 12)
713# define AFMT_AUDIO_CHANNEL_SWAP (1 << 24)
714# define AFMT_60958_CS_UPDATE (1 << 26)
715# define AFMT_AZ_AUDIO_ENABLE_CHG_MASK (1 << 27)
716# define AFMT_AZ_FORMAT_WTRIG_MASK (1 << 28)
717# define AFMT_AZ_FORMAT_WTRIG_ACK (1 << 29)
718# define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30)
719#define AFMT_VBI_PACKET_CONTROL 0x7130
720# define AFMT_GENERIC0_UPDATE (1 << 2)
721#define AFMT_INFOFRAME_CONTROL0 0x7134
722# define AFMT_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - afmt regs */
723# define AFMT_AUDIO_INFO_UPDATE (1 << 7)
724# define AFMT_MPEG_INFO_UPDATE (1 << 10)
725#define AFMT_GENERIC0_7 0x7138
726
727/* DCE4/5 ELD audio interface */
728#define AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER 0x5f78
729#define SPEAKER_ALLOCATION(x) (((x) & 0x7f) << 0)
730#define SPEAKER_ALLOCATION_MASK (0x7f << 0)
731#define SPEAKER_ALLOCATION_SHIFT 0
732#define HDMI_CONNECTION (1 << 16)
733#define DP_CONNECTION (1 << 17)
734
735#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0 0x5f84 /* LPCM */
736#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1 0x5f88 /* AC3 */
737#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2 0x5f8c /* MPEG1 */
738#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3 0x5f90 /* MP3 */
739#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4 0x5f94 /* MPEG2 */
740#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5 0x5f98 /* AAC */
741#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6 0x5f9c /* DTS */
742#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7 0x5fa0 /* ATRAC */
743#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR8 0x5fa4 /* one bit audio - leave at 0 (default) */
744#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9 0x5fa8 /* Dolby Digital */
745#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10 0x5fac /* DTS-HD */
746#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11 0x5fb0 /* MAT-MLP */
747#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR12 0x5fb4 /* DTS */
748#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13 0x5fb8 /* WMA Pro */
749# define MAX_CHANNELS(x) (((x) & 0x7) << 0)
750/* max channels minus one. 7 = 8 channels */
751# define SUPPORTED_FREQUENCIES(x) (((x) & 0xff) << 8)
752# define DESCRIPTOR_BYTE_2(x) (((x) & 0xff) << 16)
753# define SUPPORTED_FREQUENCIES_STEREO(x) (((x) & 0xff) << 24) /* LPCM only */
754/* SUPPORTED_FREQUENCIES, SUPPORTED_FREQUENCIES_STEREO
755 * bit0 = 32 kHz
756 * bit1 = 44.1 kHz
757 * bit2 = 48 kHz
758 * bit3 = 88.2 kHz
759 * bit4 = 96 kHz
760 * bit5 = 176.4 kHz
761 * bit6 = 192 kHz
762 */
763
764#define AZ_CHANNEL_COUNT_CONTROL 0x5fe4
765# define HBR_CHANNEL_COUNT(x) (((x) & 0x7) << 0)
766# define COMPRESSED_CHANNEL_COUNT(x) (((x) & 0x7) << 4)
767/* HBR_CHANNEL_COUNT, COMPRESSED_CHANNEL_COUNT
768 * 0 = use stream header
769 * 1-7 = channel count - 1
770 */
771#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC 0x5fe8
772# define VIDEO_LIPSYNC(x) (((x) & 0xff) << 0)
773# define AUDIO_LIPSYNC(x) (((x) & 0xff) << 8)
774/* VIDEO_LIPSYNC, AUDIO_LIPSYNC
775 * 0 = invalid
776 * x = legal delay value
777 * 255 = sync not supported
778 */
779#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_HBR 0x5fec
780# define HBR_CAPABLE (1 << 0) /* enabled by default */
781
782#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION0 0x5ff4
783# define DISPLAY0_TYPE(x) (((x) & 0x3) << 0)
784# define DISPLAY_TYPE_NONE 0
785# define DISPLAY_TYPE_HDMI 1
786# define DISPLAY_TYPE_DP 2
787# define DISPLAY0_ID(x) (((x) & 0x3f) << 2)
788# define DISPLAY1_TYPE(x) (((x) & 0x3) << 8)
789# define DISPLAY1_ID(x) (((x) & 0x3f) << 10)
790# define DISPLAY2_TYPE(x) (((x) & 0x3) << 16)
791# define DISPLAY2_ID(x) (((x) & 0x3f) << 18)
792# define DISPLAY3_TYPE(x) (((x) & 0x3) << 24)
793# define DISPLAY3_ID(x) (((x) & 0x3f) << 26)
794#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION1 0x5ff8
795# define DISPLAY4_TYPE(x) (((x) & 0x3) << 0)
796# define DISPLAY4_ID(x) (((x) & 0x3f) << 2)
797# define DISPLAY5_TYPE(x) (((x) & 0x3) << 8)
798# define DISPLAY5_ID(x) (((x) & 0x3f) << 10)
799#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_NUMBER 0x5ffc
800# define NUMBER_OF_DISPLAY_ID(x) (((x) & 0x7) << 0)
801
802#define AZ_HOT_PLUG_CONTROL 0x5e78
803# define AZ_FORCE_CODEC_WAKE (1 << 0)
804# define PIN0_JACK_DETECTION_ENABLE (1 << 4)
805# define PIN1_JACK_DETECTION_ENABLE (1 << 5)
806# define PIN2_JACK_DETECTION_ENABLE (1 << 6)
807# define PIN3_JACK_DETECTION_ENABLE (1 << 7)
808# define PIN0_UNSOLICITED_RESPONSE_ENABLE (1 << 8)
809# define PIN1_UNSOLICITED_RESPONSE_ENABLE (1 << 9)
810# define PIN2_UNSOLICITED_RESPONSE_ENABLE (1 << 10)
811# define PIN3_UNSOLICITED_RESPONSE_ENABLE (1 << 11)
812# define CODEC_HOT_PLUG_ENABLE (1 << 12)
813# define PIN0_AUDIO_ENABLED (1 << 24)
814# define PIN1_AUDIO_ENABLED (1 << 25)
815# define PIN2_AUDIO_ENABLED (1 << 26)
816# define PIN3_AUDIO_ENABLED (1 << 27)
817# define AUDIO_ENABLED (1 << 31)
818
819
820#define GC_USER_SHADER_PIPE_CONFIG 0x8954
821#define INACTIVE_QD_PIPES(x) ((x) << 8)
822#define INACTIVE_QD_PIPES_MASK 0x0000FF00
823#define INACTIVE_SIMDS(x) ((x) << 16)
824#define INACTIVE_SIMDS_MASK 0x00FF0000
825
826#define GRBM_CNTL 0x8000
827#define GRBM_READ_TIMEOUT(x) ((x) << 0)
828#define GRBM_SOFT_RESET 0x8020
829#define SOFT_RESET_CP (1 << 0)
830#define SOFT_RESET_CB (1 << 1)
831#define SOFT_RESET_DB (1 << 3)
832#define SOFT_RESET_PA (1 << 5)
833#define SOFT_RESET_SC (1 << 6)
834#define SOFT_RESET_SPI (1 << 8)
835#define SOFT_RESET_SH (1 << 9)
836#define SOFT_RESET_SX (1 << 10)
837#define SOFT_RESET_TC (1 << 11)
838#define SOFT_RESET_TA (1 << 12)
839#define SOFT_RESET_VC (1 << 13)
840#define SOFT_RESET_VGT (1 << 14)
841
842#define GRBM_STATUS 0x8010
843#define CMDFIFO_AVAIL_MASK 0x0000000F
844#define SRBM_RQ_PENDING (1 << 5)
845#define CF_RQ_PENDING (1 << 7)
846#define PF_RQ_PENDING (1 << 8)
847#define GRBM_EE_BUSY (1 << 10)
848#define SX_CLEAN (1 << 11)
849#define DB_CLEAN (1 << 12)
850#define CB_CLEAN (1 << 13)
851#define TA_BUSY (1 << 14)
852#define VGT_BUSY_NO_DMA (1 << 16)
853#define VGT_BUSY (1 << 17)
854#define SX_BUSY (1 << 20)
855#define SH_BUSY (1 << 21)
856#define SPI_BUSY (1 << 22)
857#define SC_BUSY (1 << 24)
858#define PA_BUSY (1 << 25)
859#define DB_BUSY (1 << 26)
860#define CP_COHERENCY_BUSY (1 << 28)
861#define CP_BUSY (1 << 29)
862#define CB_BUSY (1 << 30)
863#define GUI_ACTIVE (1 << 31)
864#define GRBM_STATUS_SE0 0x8014
865#define GRBM_STATUS_SE1 0x8018
866#define SE_SX_CLEAN (1 << 0)
867#define SE_DB_CLEAN (1 << 1)
868#define SE_CB_CLEAN (1 << 2)
869#define SE_TA_BUSY (1 << 25)
870#define SE_SX_BUSY (1 << 26)
871#define SE_SPI_BUSY (1 << 27)
872#define SE_SH_BUSY (1 << 28)
873#define SE_SC_BUSY (1 << 29)
874#define SE_DB_BUSY (1 << 30)
875#define SE_CB_BUSY (1 << 31)
876/* evergreen */
877#define CG_THERMAL_CTRL 0x72c
878#define TOFFSET_MASK 0x00003FE0
879#define TOFFSET_SHIFT 5
880#define DIG_THERM_DPM(x) ((x) << 14)
881#define DIG_THERM_DPM_MASK 0x003FC000
882#define DIG_THERM_DPM_SHIFT 14
883
884#define CG_THERMAL_INT 0x734
885#define DIG_THERM_INTH(x) ((x) << 8)
886#define DIG_THERM_INTH_MASK 0x0000FF00
887#define DIG_THERM_INTH_SHIFT 8
888#define DIG_THERM_INTL(x) ((x) << 16)
889#define DIG_THERM_INTL_MASK 0x00FF0000
890#define DIG_THERM_INTL_SHIFT 16
891#define THERM_INT_MASK_HIGH (1 << 24)
892#define THERM_INT_MASK_LOW (1 << 25)
893
894#define TN_CG_THERMAL_INT_CTRL 0x738
895#define TN_DIG_THERM_INTH(x) ((x) << 0)
896#define TN_DIG_THERM_INTH_MASK 0x000000FF
897#define TN_DIG_THERM_INTH_SHIFT 0
898#define TN_DIG_THERM_INTL(x) ((x) << 8)
899#define TN_DIG_THERM_INTL_MASK 0x0000FF00
900#define TN_DIG_THERM_INTL_SHIFT 8
901#define TN_THERM_INT_MASK_HIGH (1 << 24)
902#define TN_THERM_INT_MASK_LOW (1 << 25)
903
904#define CG_MULT_THERMAL_STATUS 0x740
905#define ASIC_T(x) ((x) << 16)
906#define ASIC_T_MASK 0x07FF0000
907#define ASIC_T_SHIFT 16
908#define CG_TS0_STATUS 0x760
909#define TS0_ADC_DOUT_MASK 0x000003FF
910#define TS0_ADC_DOUT_SHIFT 0
911
912/* APU */
913#define CG_THERMAL_STATUS 0x678
914
915#define HDP_HOST_PATH_CNTL 0x2C00
916#define HDP_NONSURFACE_BASE 0x2C04
917#define HDP_NONSURFACE_INFO 0x2C08
918#define HDP_NONSURFACE_SIZE 0x2C0C
919#define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480
920#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
921#define HDP_TILING_CONFIG 0x2F3C
922
923#define MC_SHARED_CHMAP 0x2004
924#define NOOFCHAN_SHIFT 12
925#define NOOFCHAN_MASK 0x00003000
926#define MC_SHARED_CHREMAP 0x2008
927
928#define MC_SHARED_BLACKOUT_CNTL 0x20ac
929#define BLACKOUT_MODE_MASK 0x00000007
930
931#define MC_ARB_RAMCFG 0x2760
932#define NOOFBANK_SHIFT 0
933#define NOOFBANK_MASK 0x00000003
934#define NOOFRANK_SHIFT 2
935#define NOOFRANK_MASK 0x00000004
936#define NOOFROWS_SHIFT 3
937#define NOOFROWS_MASK 0x00000038
938#define NOOFCOLS_SHIFT 6
939#define NOOFCOLS_MASK 0x000000C0
940#define CHANSIZE_SHIFT 8
941#define CHANSIZE_MASK 0x00000100
942#define BURSTLENGTH_SHIFT 9
943#define BURSTLENGTH_MASK 0x00000200
944#define CHANSIZE_OVERRIDE (1 << 11)
945#define FUS_MC_ARB_RAMCFG 0x2768
946#define MC_VM_AGP_TOP 0x2028
947#define MC_VM_AGP_BOT 0x202C
948#define MC_VM_AGP_BASE 0x2030
949#define MC_VM_FB_LOCATION 0x2024
950#define MC_FUS_VM_FB_OFFSET 0x2898
951#define MC_VM_MB_L1_TLB0_CNTL 0x2234
952#define MC_VM_MB_L1_TLB1_CNTL 0x2238
953#define MC_VM_MB_L1_TLB2_CNTL 0x223C
954#define MC_VM_MB_L1_TLB3_CNTL 0x2240
955#define ENABLE_L1_TLB (1 << 0)
956#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
957#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)
958#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
959#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
960#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)
961#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
962#define EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15)
963#define EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18)
964#define MC_VM_MD_L1_TLB0_CNTL 0x2654
965#define MC_VM_MD_L1_TLB1_CNTL 0x2658
966#define MC_VM_MD_L1_TLB2_CNTL 0x265C
967#define MC_VM_MD_L1_TLB3_CNTL 0x2698
968
969#define FUS_MC_VM_MD_L1_TLB0_CNTL 0x265C
970#define FUS_MC_VM_MD_L1_TLB1_CNTL 0x2660
971#define FUS_MC_VM_MD_L1_TLB2_CNTL 0x2664
972
973#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C
974#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
975#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
976
977#define PA_CL_ENHANCE 0x8A14
978#define CLIP_VTX_REORDER_ENA (1 << 0)
979#define NUM_CLIP_SEQ(x) ((x) << 1)
980#define PA_SC_ENHANCE 0x8BF0
981#define PA_SC_AA_CONFIG 0x28C04
982#define MSAA_NUM_SAMPLES_SHIFT 0
983#define MSAA_NUM_SAMPLES_MASK 0x3
984#define PA_SC_CLIPRECT_RULE 0x2820C
985#define PA_SC_EDGERULE 0x28230
986#define PA_SC_FIFO_SIZE 0x8BCC
987#define SC_PRIM_FIFO_SIZE(x) ((x) << 0)
988#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12)
989#define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20)
990#define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24
991#define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
992#define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)
993#define PA_SC_LINE_STIPPLE 0x28A0C
994#define PA_SU_LINE_STIPPLE_VALUE 0x8A60
995#define PA_SC_LINE_STIPPLE_STATE 0x8B10
996
997#define SCRATCH_REG0 0x8500
998#define SCRATCH_REG1 0x8504
999#define SCRATCH_REG2 0x8508
1000#define SCRATCH_REG3 0x850C
1001#define SCRATCH_REG4 0x8510
1002#define SCRATCH_REG5 0x8514
1003#define SCRATCH_REG6 0x8518
1004#define SCRATCH_REG7 0x851C
1005#define SCRATCH_UMSK 0x8540
1006#define SCRATCH_ADDR 0x8544
1007
1008#define SMX_SAR_CTL0 0xA008
1009#define SMX_DC_CTL0 0xA020
1010#define USE_HASH_FUNCTION (1 << 0)
1011#define NUMBER_OF_SETS(x) ((x) << 1)
1012#define FLUSH_ALL_ON_EVENT (1 << 10)
1013#define STALL_ON_EVENT (1 << 11)
1014#define SMX_EVENT_CTL 0xA02C
1015#define ES_FLUSH_CTL(x) ((x) << 0)
1016#define GS_FLUSH_CTL(x) ((x) << 3)
1017#define ACK_FLUSH_CTL(x) ((x) << 6)
1018#define SYNC_FLUSH_CTL (1 << 8)
1019
1020#define SPI_CONFIG_CNTL 0x9100
1021#define GPR_WRITE_PRIORITY(x) ((x) << 0)
1022#define SPI_CONFIG_CNTL_1 0x913C
1023#define VTX_DONE_DELAY(x) ((x) << 0)
1024#define INTERP_ONE_PRIM_PER_ROW (1 << 4)
1025#define SPI_INPUT_Z 0x286D8
1026#define SPI_PS_IN_CONTROL_0 0x286CC
1027#define NUM_INTERP(x) ((x)<<0)
1028#define POSITION_ENA (1<<8)
1029#define POSITION_CENTROID (1<<9)
1030#define POSITION_ADDR(x) ((x)<<10)
1031#define PARAM_GEN(x) ((x)<<15)
1032#define PARAM_GEN_ADDR(x) ((x)<<19)
1033#define BARYC_SAMPLE_CNTL(x) ((x)<<26)
1034#define PERSP_GRADIENT_ENA (1<<28)
1035#define LINEAR_GRADIENT_ENA (1<<29)
1036#define POSITION_SAMPLE (1<<30)
1037#define BARYC_AT_SAMPLE_ENA (1<<31)
1038
1039#define SQ_CONFIG 0x8C00
1040#define VC_ENABLE (1 << 0)
1041#define EXPORT_SRC_C (1 << 1)
1042#define CS_PRIO(x) ((x) << 18)
1043#define LS_PRIO(x) ((x) << 20)
1044#define HS_PRIO(x) ((x) << 22)
1045#define PS_PRIO(x) ((x) << 24)
1046#define VS_PRIO(x) ((x) << 26)
1047#define GS_PRIO(x) ((x) << 28)
1048#define ES_PRIO(x) ((x) << 30)
1049#define SQ_GPR_RESOURCE_MGMT_1 0x8C04
1050#define NUM_PS_GPRS(x) ((x) << 0)
1051#define NUM_VS_GPRS(x) ((x) << 16)
1052#define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28)
1053#define SQ_GPR_RESOURCE_MGMT_2 0x8C08
1054#define NUM_GS_GPRS(x) ((x) << 0)
1055#define NUM_ES_GPRS(x) ((x) << 16)
1056#define SQ_GPR_RESOURCE_MGMT_3 0x8C0C
1057#define NUM_HS_GPRS(x) ((x) << 0)
1058#define NUM_LS_GPRS(x) ((x) << 16)
1059#define SQ_GLOBAL_GPR_RESOURCE_MGMT_1 0x8C10
1060#define SQ_GLOBAL_GPR_RESOURCE_MGMT_2 0x8C14
1061#define SQ_THREAD_RESOURCE_MGMT 0x8C18
1062#define NUM_PS_THREADS(x) ((x) << 0)
1063#define NUM_VS_THREADS(x) ((x) << 8)
1064#define NUM_GS_THREADS(x) ((x) << 16)
1065#define NUM_ES_THREADS(x) ((x) << 24)
1066#define SQ_THREAD_RESOURCE_MGMT_2 0x8C1C
1067#define NUM_HS_THREADS(x) ((x) << 0)
1068#define NUM_LS_THREADS(x) ((x) << 8)
1069#define SQ_STACK_RESOURCE_MGMT_1 0x8C20
1070#define NUM_PS_STACK_ENTRIES(x) ((x) << 0)
1071#define NUM_VS_STACK_ENTRIES(x) ((x) << 16)
1072#define SQ_STACK_RESOURCE_MGMT_2 0x8C24
1073#define NUM_GS_STACK_ENTRIES(x) ((x) << 0)
1074#define NUM_ES_STACK_ENTRIES(x) ((x) << 16)
1075#define SQ_STACK_RESOURCE_MGMT_3 0x8C28
1076#define NUM_HS_STACK_ENTRIES(x) ((x) << 0)
1077#define NUM_LS_STACK_ENTRIES(x) ((x) << 16)
1078#define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C
1079#define SQ_DYN_GPR_SIMD_LOCK_EN 0x8D94
1080#define SQ_STATIC_THREAD_MGMT_1 0x8E20
1081#define SQ_STATIC_THREAD_MGMT_2 0x8E24
1082#define SQ_STATIC_THREAD_MGMT_3 0x8E28
1083#define SQ_LDS_RESOURCE_MGMT 0x8E2C
1084
1085#define SQ_MS_FIFO_SIZES 0x8CF0
1086#define CACHE_FIFO_SIZE(x) ((x) << 0)
1087#define FETCH_FIFO_HIWATER(x) ((x) << 8)
1088#define DONE_FIFO_HIWATER(x) ((x) << 16)
1089#define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24)
1090
1091#define SX_DEBUG_1 0x9058
1092#define ENABLE_NEW_SMX_ADDRESS (1 << 16)
1093#define SX_EXPORT_BUFFER_SIZES 0x900C
1094#define COLOR_BUFFER_SIZE(x) ((x) << 0)
1095#define POSITION_BUFFER_SIZE(x) ((x) << 8)
1096#define SMX_BUFFER_SIZE(x) ((x) << 16)
1097#define SX_MEMORY_EXPORT_BASE 0x9010
1098#define SX_MISC 0x28350
1099
1100#define CB_PERF_CTR0_SEL_0 0x9A20
1101#define CB_PERF_CTR0_SEL_1 0x9A24
1102#define CB_PERF_CTR1_SEL_0 0x9A28
1103#define CB_PERF_CTR1_SEL_1 0x9A2C
1104#define CB_PERF_CTR2_SEL_0 0x9A30
1105#define CB_PERF_CTR2_SEL_1 0x9A34
1106#define CB_PERF_CTR3_SEL_0 0x9A38
1107#define CB_PERF_CTR3_SEL_1 0x9A3C
1108
1109#define TA_CNTL_AUX 0x9508
1110#define DISABLE_CUBE_WRAP (1 << 0)
1111#define DISABLE_CUBE_ANISO (1 << 1)
1112#define SYNC_GRADIENT (1 << 24)
1113#define SYNC_WALKER (1 << 25)
1114#define SYNC_ALIGNER (1 << 26)
1115
1116#define TCP_CHAN_STEER_LO 0x960c
1117#define TCP_CHAN_STEER_HI 0x9610
1118
1119#define VGT_CACHE_INVALIDATION 0x88C4
1120#define CACHE_INVALIDATION(x) ((x) << 0)
1121#define VC_ONLY 0
1122#define TC_ONLY 1
1123#define VC_AND_TC 2
1124#define AUTO_INVLD_EN(x) ((x) << 6)
1125#define NO_AUTO 0
1126#define ES_AUTO 1
1127#define GS_AUTO 2
1128#define ES_AND_GS_AUTO 3
1129#define VGT_GS_VERTEX_REUSE 0x88D4
1130#define VGT_NUM_INSTANCES 0x8974
1131#define VGT_OUT_DEALLOC_CNTL 0x28C5C
1132#define DEALLOC_DIST_MASK 0x0000007F
1133#define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58
1134#define VTX_REUSE_DEPTH_MASK 0x000000FF
1135
1136#define VM_CONTEXT0_CNTL 0x1410
1137#define ENABLE_CONTEXT (1 << 0)
1138#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
1139#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
1140#define VM_CONTEXT1_CNTL 0x1414
1141#define VM_CONTEXT1_CNTL2 0x1434
1142#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C
1143#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C
1144#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C
1145#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518
1146#define VM_CONTEXT0_REQUEST_RESPONSE 0x1470
1147#define REQUEST_TYPE(x) (((x) & 0xf) << 0)
1148#define RESPONSE_TYPE_MASK 0x000000F0
1149#define RESPONSE_TYPE_SHIFT 4
1150#define VM_L2_CNTL 0x1400
1151#define ENABLE_L2_CACHE (1 << 0)
1152#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
1153#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
1154#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14)
1155#define VM_L2_CNTL2 0x1404
1156#define INVALIDATE_ALL_L1_TLBS (1 << 0)
1157#define INVALIDATE_L2_CACHE (1 << 1)
1158#define VM_L2_CNTL3 0x1408
1159#define BANK_SELECT(x) ((x) << 0)
1160#define CACHE_UPDATE_MODE(x) ((x) << 6)
1161#define VM_L2_STATUS 0x140C
1162#define L2_BUSY (1 << 0)
1163#define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC
1164#define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC
1165
1166#define WAIT_UNTIL 0x8040
1167
1168#define SRBM_STATUS 0x0E50
1169#define RLC_RQ_PENDING (1 << 3)
1170#define GRBM_RQ_PENDING (1 << 5)
1171#define VMC_BUSY (1 << 8)
1172#define MCB_BUSY (1 << 9)
1173#define MCB_NON_DISPLAY_BUSY (1 << 10)
1174#define MCC_BUSY (1 << 11)
1175#define MCD_BUSY (1 << 12)
1176#define SEM_BUSY (1 << 14)
1177#define RLC_BUSY (1 << 15)
1178#define IH_BUSY (1 << 17)
1179#define SRBM_STATUS2 0x0EC4
1180#define DMA_BUSY (1 << 5)
1181#define SRBM_SOFT_RESET 0x0E60
1182#define SRBM_SOFT_RESET_ALL_MASK 0x00FEEFA6
1183#define SOFT_RESET_BIF (1 << 1)
1184#define SOFT_RESET_CG (1 << 2)
1185#define SOFT_RESET_DC (1 << 5)
1186#define SOFT_RESET_GRBM (1 << 8)
1187#define SOFT_RESET_HDP (1 << 9)
1188#define SOFT_RESET_IH (1 << 10)
1189#define SOFT_RESET_MC (1 << 11)
1190#define SOFT_RESET_RLC (1 << 13)
1191#define SOFT_RESET_ROM (1 << 14)
1192#define SOFT_RESET_SEM (1 << 15)
1193#define SOFT_RESET_VMC (1 << 17)
1194#define SOFT_RESET_DMA (1 << 20)
1195#define SOFT_RESET_TST (1 << 21)
1196#define SOFT_RESET_REGBB (1 << 22)
1197#define SOFT_RESET_ORB (1 << 23)
1198
1199#define SRBM_READ_ERROR 0xE98
1200#define SRBM_INT_CNTL 0xEA0
1201#define SRBM_INT_ACK 0xEA8
1202
1203/* display watermarks */
1204#define DC_LB_MEMORY_SPLIT 0x6b0c
1205#define PRIORITY_A_CNT 0x6b18
1206#define PRIORITY_MARK_MASK 0x7fff
1207#define PRIORITY_OFF (1 << 16)
1208#define PRIORITY_ALWAYS_ON (1 << 20)
1209#define PRIORITY_B_CNT 0x6b1c
1210#define PIPE0_ARBITRATION_CONTROL3 0x0bf0
1211# define LATENCY_WATERMARK_MASK(x) ((x) << 16)
1212#define PIPE0_LATENCY_CONTROL 0x0bf4
1213# define LATENCY_LOW_WATERMARK(x) ((x) << 0)
1214# define LATENCY_HIGH_WATERMARK(x) ((x) << 16)
1215
1216#define PIPE0_DMIF_BUFFER_CONTROL 0x0ca0
1217# define DMIF_BUFFERS_ALLOCATED(x) ((x) << 0)
1218# define DMIF_BUFFERS_ALLOCATED_COMPLETED (1 << 4)
1219
1220#define IH_RB_CNTL 0x3e00
1221# define IH_RB_ENABLE (1 << 0)
1222# define IH_IB_SIZE(x) ((x) << 1) /* log2 */
1223# define IH_RB_FULL_DRAIN_ENABLE (1 << 6)
1224# define IH_WPTR_WRITEBACK_ENABLE (1 << 8)
1225# define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */
1226# define IH_WPTR_OVERFLOW_ENABLE (1 << 16)
1227# define IH_WPTR_OVERFLOW_CLEAR (1 << 31)
1228#define IH_RB_BASE 0x3e04
1229#define IH_RB_RPTR 0x3e08
1230#define IH_RB_WPTR 0x3e0c
1231# define RB_OVERFLOW (1 << 0)
1232# define WPTR_OFFSET_MASK 0x3fffc
1233#define IH_RB_WPTR_ADDR_HI 0x3e10
1234#define IH_RB_WPTR_ADDR_LO 0x3e14
1235#define IH_CNTL 0x3e18
1236# define ENABLE_INTR (1 << 0)
1237# define IH_MC_SWAP(x) ((x) << 1)
1238# define IH_MC_SWAP_NONE 0
1239# define IH_MC_SWAP_16BIT 1
1240# define IH_MC_SWAP_32BIT 2
1241# define IH_MC_SWAP_64BIT 3
1242# define RPTR_REARM (1 << 4)
1243# define MC_WRREQ_CREDIT(x) ((x) << 15)
1244# define MC_WR_CLEAN_CNT(x) ((x) << 20)
1245
1246#define CP_INT_CNTL 0xc124
1247# define CNTX_BUSY_INT_ENABLE (1 << 19)
1248# define CNTX_EMPTY_INT_ENABLE (1 << 20)
1249# define SCRATCH_INT_ENABLE (1 << 25)
1250# define TIME_STAMP_INT_ENABLE (1 << 26)
1251# define IB2_INT_ENABLE (1 << 29)
1252# define IB1_INT_ENABLE (1 << 30)
1253# define RB_INT_ENABLE (1 << 31)
1254#define CP_INT_STATUS 0xc128
1255# define SCRATCH_INT_STAT (1 << 25)
1256# define TIME_STAMP_INT_STAT (1 << 26)
1257# define IB2_INT_STAT (1 << 29)
1258# define IB1_INT_STAT (1 << 30)
1259# define RB_INT_STAT (1 << 31)
1260
1261#define GRBM_INT_CNTL 0x8060
1262# define RDERR_INT_ENABLE (1 << 0)
1263# define GUI_IDLE_INT_ENABLE (1 << 19)
1264
1265/* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */
1266#define CRTC_STATUS_FRAME_COUNT 0x6e98
1267
1268/* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */
1269#define VLINE_STATUS 0x6bb8
1270# define VLINE_OCCURRED (1 << 0)
1271# define VLINE_ACK (1 << 4)
1272# define VLINE_STAT (1 << 12)
1273# define VLINE_INTERRUPT (1 << 16)
1274# define VLINE_INTERRUPT_TYPE (1 << 17)
1275/* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */
1276#define VBLANK_STATUS 0x6bbc
1277# define VBLANK_OCCURRED (1 << 0)
1278# define VBLANK_ACK (1 << 4)
1279# define VBLANK_STAT (1 << 12)
1280# define VBLANK_INTERRUPT (1 << 16)
1281# define VBLANK_INTERRUPT_TYPE (1 << 17)
1282
1283/* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */
1284#define INT_MASK 0x6b40
1285# define VBLANK_INT_MASK (1 << 0)
1286# define VLINE_INT_MASK (1 << 4)
1287
1288#define DISP_INTERRUPT_STATUS 0x60f4
1289# define LB_D1_VLINE_INTERRUPT (1 << 2)
1290# define LB_D1_VBLANK_INTERRUPT (1 << 3)
1291# define DC_HPD1_INTERRUPT (1 << 17)
1292# define DC_HPD1_RX_INTERRUPT (1 << 18)
1293# define DACA_AUTODETECT_INTERRUPT (1 << 22)
1294# define DACB_AUTODETECT_INTERRUPT (1 << 23)
1295# define DC_I2C_SW_DONE_INTERRUPT (1 << 24)
1296# define DC_I2C_HW_DONE_INTERRUPT (1 << 25)
1297#define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8
1298# define LB_D2_VLINE_INTERRUPT (1 << 2)
1299# define LB_D2_VBLANK_INTERRUPT (1 << 3)
1300# define DC_HPD2_INTERRUPT (1 << 17)
1301# define DC_HPD2_RX_INTERRUPT (1 << 18)
1302# define DISP_TIMER_INTERRUPT (1 << 24)
1303#define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc
1304# define LB_D3_VLINE_INTERRUPT (1 << 2)
1305# define LB_D3_VBLANK_INTERRUPT (1 << 3)
1306# define DC_HPD3_INTERRUPT (1 << 17)
1307# define DC_HPD3_RX_INTERRUPT (1 << 18)
1308#define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100
1309# define LB_D4_VLINE_INTERRUPT (1 << 2)
1310# define LB_D4_VBLANK_INTERRUPT (1 << 3)
1311# define DC_HPD4_INTERRUPT (1 << 17)
1312# define DC_HPD4_RX_INTERRUPT (1 << 18)
1313#define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c
1314# define LB_D5_VLINE_INTERRUPT (1 << 2)
1315# define LB_D5_VBLANK_INTERRUPT (1 << 3)
1316# define DC_HPD5_INTERRUPT (1 << 17)
1317# define DC_HPD5_RX_INTERRUPT (1 << 18)
1318#define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150
1319# define LB_D6_VLINE_INTERRUPT (1 << 2)
1320# define LB_D6_VBLANK_INTERRUPT (1 << 3)
1321# define DC_HPD6_INTERRUPT (1 << 17)
1322# define DC_HPD6_RX_INTERRUPT (1 << 18)
1323
1324/* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */
1325#define GRPH_INT_STATUS 0x6858
1326# define GRPH_PFLIP_INT_OCCURRED (1 << 0)
1327# define GRPH_PFLIP_INT_CLEAR (1 << 8)
1328/* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */
1329#define GRPH_INT_CONTROL 0x685c
1330# define GRPH_PFLIP_INT_MASK (1 << 0)
1331# define GRPH_PFLIP_INT_TYPE (1 << 8)
1332
1333#define DACA_AUTODETECT_INT_CONTROL 0x66c8
1334#define DACB_AUTODETECT_INT_CONTROL 0x67c8
1335
1336#define DC_HPD1_INT_STATUS 0x601c
1337#define DC_HPD2_INT_STATUS 0x6028
1338#define DC_HPD3_INT_STATUS 0x6034
1339#define DC_HPD4_INT_STATUS 0x6040
1340#define DC_HPD5_INT_STATUS 0x604c
1341#define DC_HPD6_INT_STATUS 0x6058
1342# define DC_HPDx_INT_STATUS (1 << 0)
1343# define DC_HPDx_SENSE (1 << 1)
1344# define DC_HPDx_RX_INT_STATUS (1 << 8)
1345
1346#define DC_HPD1_INT_CONTROL 0x6020
1347#define DC_HPD2_INT_CONTROL 0x602c
1348#define DC_HPD3_INT_CONTROL 0x6038
1349#define DC_HPD4_INT_CONTROL 0x6044
1350#define DC_HPD5_INT_CONTROL 0x6050
1351#define DC_HPD6_INT_CONTROL 0x605c
1352# define DC_HPDx_INT_ACK (1 << 0)
1353# define DC_HPDx_INT_POLARITY (1 << 8)
1354# define DC_HPDx_INT_EN (1 << 16)
1355# define DC_HPDx_RX_INT_ACK (1 << 20)
1356# define DC_HPDx_RX_INT_EN (1 << 24)
1357
1358#define DC_HPD1_CONTROL 0x6024
1359#define DC_HPD2_CONTROL 0x6030
1360#define DC_HPD3_CONTROL 0x603c
1361#define DC_HPD4_CONTROL 0x6048
1362#define DC_HPD5_CONTROL 0x6054
1363#define DC_HPD6_CONTROL 0x6060
1364# define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0)
1365# define DC_HPDx_RX_INT_TIMER(x) ((x) << 16)
1366# define DC_HPDx_EN (1 << 28)
1367
1368/* DCE4/5/6 FMT blocks */
1369#define FMT_DYNAMIC_EXP_CNTL 0x6fb4
1370# define FMT_DYNAMIC_EXP_EN (1 << 0)
1371# define FMT_DYNAMIC_EXP_MODE (1 << 4)
1372 /* 0 = 10bit -> 12bit, 1 = 8bit -> 12bit */
1373#define FMT_CONTROL 0x6fb8
1374# define FMT_PIXEL_ENCODING (1 << 16)
1375 /* 0 = RGB 4:4:4 or YCbCr 4:4:4, 1 = YCbCr 4:2:2 */
1376#define FMT_BIT_DEPTH_CONTROL 0x6fc8
1377# define FMT_TRUNCATE_EN (1 << 0)
1378# define FMT_TRUNCATE_DEPTH (1 << 4)
1379# define FMT_SPATIAL_DITHER_EN (1 << 8)
1380# define FMT_SPATIAL_DITHER_MODE(x) ((x) << 9)
1381# define FMT_SPATIAL_DITHER_DEPTH (1 << 12)
1382# define FMT_FRAME_RANDOM_ENABLE (1 << 13)
1383# define FMT_RGB_RANDOM_ENABLE (1 << 14)
1384# define FMT_HIGHPASS_RANDOM_ENABLE (1 << 15)
1385# define FMT_TEMPORAL_DITHER_EN (1 << 16)
1386# define FMT_TEMPORAL_DITHER_DEPTH (1 << 20)
1387# define FMT_TEMPORAL_DITHER_OFFSET(x) ((x) << 21)
1388# define FMT_TEMPORAL_LEVEL (1 << 24)
1389# define FMT_TEMPORAL_DITHER_RESET (1 << 25)
1390# define FMT_25FRC_SEL(x) ((x) << 26)
1391# define FMT_50FRC_SEL(x) ((x) << 28)
1392# define FMT_75FRC_SEL(x) ((x) << 30)
1393#define FMT_CLAMP_CONTROL 0x6fe4
1394# define FMT_CLAMP_DATA_EN (1 << 0)
1395# define FMT_CLAMP_COLOR_FORMAT(x) ((x) << 16)
1396# define FMT_CLAMP_6BPC 0
1397# define FMT_CLAMP_8BPC 1
1398# define FMT_CLAMP_10BPC 2
1399
1400/* ASYNC DMA */
1401#define DMA_RB_RPTR 0xd008
1402#define DMA_RB_WPTR 0xd00c
1403
1404#define DMA_CNTL 0xd02c
1405# define TRAP_ENABLE (1 << 0)
1406# define SEM_INCOMPLETE_INT_ENABLE (1 << 1)
1407# define SEM_WAIT_INT_ENABLE (1 << 2)
1408# define DATA_SWAP_ENABLE (1 << 3)
1409# define FENCE_SWAP_ENABLE (1 << 4)
1410# define CTXEMPTY_INT_ENABLE (1 << 28)
1411#define DMA_TILING_CONFIG 0xD0B8
1412
1413#define CAYMAN_DMA1_CNTL 0xd82c
1414
1415/* async DMA packets */
1416#define DMA_PACKET(cmd, sub_cmd, n) ((((cmd) & 0xF) << 28) | \
1417 (((sub_cmd) & 0xFF) << 20) |\
1418 (((n) & 0xFFFFF) << 0))
1419#define GET_DMA_CMD(h) (((h) & 0xf0000000) >> 28)
1420#define GET_DMA_COUNT(h) ((h) & 0x000fffff)
1421#define GET_DMA_SUB_CMD(h) (((h) & 0x0ff00000) >> 20)
1422
1423/* async DMA Packet types */
1424#define DMA_PACKET_WRITE 0x2
1425#define DMA_PACKET_COPY 0x3
1426#define DMA_PACKET_INDIRECT_BUFFER 0x4
1427#define DMA_PACKET_SEMAPHORE 0x5
1428#define DMA_PACKET_FENCE 0x6
1429#define DMA_PACKET_TRAP 0x7
1430#define DMA_PACKET_SRBM_WRITE 0x9
1431#define DMA_PACKET_CONSTANT_FILL 0xd
1432#define DMA_PACKET_NOP 0xf
1433
1434/* PIF PHY0 indirect regs */
1435#define PB0_PIF_CNTL 0x10
1436# define LS2_EXIT_TIME(x) ((x) << 17)
1437# define LS2_EXIT_TIME_MASK (0x7 << 17)
1438# define LS2_EXIT_TIME_SHIFT 17
1439#define PB0_PIF_PAIRING 0x11
1440# define MULTI_PIF (1 << 25)
1441#define PB0_PIF_PWRDOWN_0 0x12
1442# define PLL_POWER_STATE_IN_TXS2_0(x) ((x) << 7)
1443# define PLL_POWER_STATE_IN_TXS2_0_MASK (0x7 << 7)
1444# define PLL_POWER_STATE_IN_TXS2_0_SHIFT 7
1445# define PLL_POWER_STATE_IN_OFF_0(x) ((x) << 10)
1446# define PLL_POWER_STATE_IN_OFF_0_MASK (0x7 << 10)
1447# define PLL_POWER_STATE_IN_OFF_0_SHIFT 10
1448# define PLL_RAMP_UP_TIME_0(x) ((x) << 24)
1449# define PLL_RAMP_UP_TIME_0_MASK (0x7 << 24)
1450# define PLL_RAMP_UP_TIME_0_SHIFT 24
1451#define PB0_PIF_PWRDOWN_1 0x13
1452# define PLL_POWER_STATE_IN_TXS2_1(x) ((x) << 7)
1453# define PLL_POWER_STATE_IN_TXS2_1_MASK (0x7 << 7)
1454# define PLL_POWER_STATE_IN_TXS2_1_SHIFT 7
1455# define PLL_POWER_STATE_IN_OFF_1(x) ((x) << 10)
1456# define PLL_POWER_STATE_IN_OFF_1_MASK (0x7 << 10)
1457# define PLL_POWER_STATE_IN_OFF_1_SHIFT 10
1458# define PLL_RAMP_UP_TIME_1(x) ((x) << 24)
1459# define PLL_RAMP_UP_TIME_1_MASK (0x7 << 24)
1460# define PLL_RAMP_UP_TIME_1_SHIFT 24
1461/* PIF PHY1 indirect regs */
1462#define PB1_PIF_CNTL 0x10
1463#define PB1_PIF_PAIRING 0x11
1464#define PB1_PIF_PWRDOWN_0 0x12
1465#define PB1_PIF_PWRDOWN_1 0x13
1466/* PCIE PORT indirect regs */
1467#define PCIE_LC_CNTL 0xa0
1468# define LC_L0S_INACTIVITY(x) ((x) << 8)
1469# define LC_L0S_INACTIVITY_MASK (0xf << 8)
1470# define LC_L0S_INACTIVITY_SHIFT 8
1471# define LC_L1_INACTIVITY(x) ((x) << 12)
1472# define LC_L1_INACTIVITY_MASK (0xf << 12)
1473# define LC_L1_INACTIVITY_SHIFT 12
1474# define LC_PMI_TO_L1_DIS (1 << 16)
1475# define LC_ASPM_TO_L1_DIS (1 << 24)
1476#define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */
1477#define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */
1478# define LC_LINK_WIDTH_SHIFT 0
1479# define LC_LINK_WIDTH_MASK 0x7
1480# define LC_LINK_WIDTH_X0 0
1481# define LC_LINK_WIDTH_X1 1
1482# define LC_LINK_WIDTH_X2 2
1483# define LC_LINK_WIDTH_X4 3
1484# define LC_LINK_WIDTH_X8 4
1485# define LC_LINK_WIDTH_X16 6
1486# define LC_LINK_WIDTH_RD_SHIFT 4
1487# define LC_LINK_WIDTH_RD_MASK 0x70
1488# define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
1489# define LC_RECONFIG_NOW (1 << 8)
1490# define LC_RENEGOTIATION_SUPPORT (1 << 9)
1491# define LC_RENEGOTIATE_EN (1 << 10)
1492# define LC_SHORT_RECONFIG_EN (1 << 11)
1493# define LC_UPCONFIGURE_SUPPORT (1 << 12)
1494# define LC_UPCONFIGURE_DIS (1 << 13)
1495# define LC_DYN_LANES_PWR_STATE(x) ((x) << 21)
1496# define LC_DYN_LANES_PWR_STATE_MASK (0x3 << 21)
1497# define LC_DYN_LANES_PWR_STATE_SHIFT 21
1498#define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */
1499# define LC_GEN2_EN_STRAP (1 << 0)
1500# define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1)
1501# define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5)
1502# define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6)
1503# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8)
1504# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3
1505# define LC_CURRENT_DATA_RATE (1 << 11)
1506# define LC_HW_VOLTAGE_IF_CONTROL(x) ((x) << 12)
1507# define LC_HW_VOLTAGE_IF_CONTROL_MASK (3 << 12)
1508# define LC_HW_VOLTAGE_IF_CONTROL_SHIFT 12
1509# define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14)
1510# define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21)
1511# define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23)
1512# define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24)
1513#define MM_CFGREGS_CNTL 0x544c
1514# define MM_WR_TO_CFG_EN (1 << 3)
1515#define LINK_CNTL2 0x88 /* F0 */
1516# define TARGET_LINK_SPEED_MASK (0xf << 0)
1517# define SELECTABLE_DEEMPHASIS (1 << 6)
1518
1519
1520/*
1521 * UVD
1522 */
1523#define UVD_UDEC_ADDR_CONFIG 0xef4c
1524#define UVD_UDEC_DB_ADDR_CONFIG 0xef50
1525#define UVD_UDEC_DBW_ADDR_CONFIG 0xef54
1526#define UVD_RBC_RB_RPTR 0xf690
1527#define UVD_RBC_RB_WPTR 0xf694
1528#define UVD_STATUS 0xf6bc
1529
1530/*
1531 * PM4
1532 */
1533#define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \
1534 (((reg) >> 2) & 0xFFFF) | \
1535 ((n) & 0x3FFF) << 16)
1536#define CP_PACKET2 0x80000000
1537#define PACKET2_PAD_SHIFT 0
1538#define PACKET2_PAD_MASK (0x3fffffff << 0)
1539
1540#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
1541
1542#define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \
1543 (((op) & 0xFF) << 8) | \
1544 ((n) & 0x3FFF) << 16)
1545
1546/* Packet 3 types */
1547#define PACKET3_NOP 0x10
1548#define PACKET3_SET_BASE 0x11
1549#define PACKET3_CLEAR_STATE 0x12
1550#define PACKET3_INDEX_BUFFER_SIZE 0x13
1551#define PACKET3_DISPATCH_DIRECT 0x15
1552#define PACKET3_DISPATCH_INDIRECT 0x16
1553#define PACKET3_INDIRECT_BUFFER_END 0x17
1554#define PACKET3_MODE_CONTROL 0x18
1555#define PACKET3_SET_PREDICATION 0x20
1556#define PACKET3_REG_RMW 0x21
1557#define PACKET3_COND_EXEC 0x22
1558#define PACKET3_PRED_EXEC 0x23
1559#define PACKET3_DRAW_INDIRECT 0x24
1560#define PACKET3_DRAW_INDEX_INDIRECT 0x25
1561#define PACKET3_INDEX_BASE 0x26
1562#define PACKET3_DRAW_INDEX_2 0x27
1563#define PACKET3_CONTEXT_CONTROL 0x28
1564#define PACKET3_DRAW_INDEX_OFFSET 0x29
1565#define PACKET3_INDEX_TYPE 0x2A
1566#define PACKET3_DRAW_INDEX 0x2B
1567#define PACKET3_DRAW_INDEX_AUTO 0x2D
1568#define PACKET3_DRAW_INDEX_IMMD 0x2E
1569#define PACKET3_NUM_INSTANCES 0x2F
1570#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
1571#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
1572#define PACKET3_DRAW_INDEX_OFFSET_2 0x35
1573#define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36
1574#define PACKET3_MEM_SEMAPHORE 0x39
1575#define PACKET3_MPEG_INDEX 0x3A
1576#define PACKET3_COPY_DW 0x3B
1577#define PACKET3_WAIT_REG_MEM 0x3C
1578#define PACKET3_MEM_WRITE 0x3D
1579#define PACKET3_INDIRECT_BUFFER 0x32
1580#define PACKET3_CP_DMA 0x41
1581/* 1. header
1582 * 2. SRC_ADDR_LO or DATA [31:0]
1583 * 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] |
1584 * SRC_ADDR_HI [7:0]
1585 * 4. DST_ADDR_LO [31:0]
1586 * 5. DST_ADDR_HI [7:0]
1587 * 6. COMMAND [29:22] | BYTE_COUNT [20:0]
1588 */
1589# define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20)
1590 /* 0 - DST_ADDR
1591 * 1 - GDS
1592 */
1593# define PACKET3_CP_DMA_ENGINE(x) ((x) << 27)
1594 /* 0 - ME
1595 * 1 - PFP
1596 */
1597# define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29)
1598 /* 0 - SRC_ADDR
1599 * 1 - GDS
1600 * 2 - DATA
1601 */
1602# define PACKET3_CP_DMA_CP_SYNC (1 << 31)
1603/* COMMAND */
1604# define PACKET3_CP_DMA_DIS_WC (1 << 21)
1605# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22)
1606 /* 0 - none
1607 * 1 - 8 in 16
1608 * 2 - 8 in 32
1609 * 3 - 8 in 64
1610 */
1611# define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24)
1612 /* 0 - none
1613 * 1 - 8 in 16
1614 * 2 - 8 in 32
1615 * 3 - 8 in 64
1616 */
1617# define PACKET3_CP_DMA_CMD_SAS (1 << 26)
1618 /* 0 - memory
1619 * 1 - register
1620 */
1621# define PACKET3_CP_DMA_CMD_DAS (1 << 27)
1622 /* 0 - memory
1623 * 1 - register
1624 */
1625# define PACKET3_CP_DMA_CMD_SAIC (1 << 28)
1626# define PACKET3_CP_DMA_CMD_DAIC (1 << 29)
1627#define PACKET3_SURFACE_SYNC 0x43
1628# define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
1629# define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
1630# define PACKET3_CB2_DEST_BASE_ENA (1 << 8)
1631# define PACKET3_CB3_DEST_BASE_ENA (1 << 9)
1632# define PACKET3_CB4_DEST_BASE_ENA (1 << 10)
1633# define PACKET3_CB5_DEST_BASE_ENA (1 << 11)
1634# define PACKET3_CB6_DEST_BASE_ENA (1 << 12)
1635# define PACKET3_CB7_DEST_BASE_ENA (1 << 13)
1636# define PACKET3_DB_DEST_BASE_ENA (1 << 14)
1637# define PACKET3_CB8_DEST_BASE_ENA (1 << 15)
1638# define PACKET3_CB9_DEST_BASE_ENA (1 << 16)
1639# define PACKET3_CB10_DEST_BASE_ENA (1 << 17)
1640# define PACKET3_CB11_DEST_BASE_ENA (1 << 18)
1641# define PACKET3_FULL_CACHE_ENA (1 << 20)
1642# define PACKET3_TC_ACTION_ENA (1 << 23)
1643# define PACKET3_VC_ACTION_ENA (1 << 24)
1644# define PACKET3_CB_ACTION_ENA (1 << 25)
1645# define PACKET3_DB_ACTION_ENA (1 << 26)
1646# define PACKET3_SH_ACTION_ENA (1 << 27)
1647# define PACKET3_SX_ACTION_ENA (1 << 28)
1648#define PACKET3_ME_INITIALIZE 0x44
1649#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
1650#define PACKET3_COND_WRITE 0x45
1651#define PACKET3_EVENT_WRITE 0x46
1652#define PACKET3_EVENT_WRITE_EOP 0x47
1653#define PACKET3_EVENT_WRITE_EOS 0x48
1654#define PACKET3_PREAMBLE_CNTL 0x4A
1655# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
1656# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
1657#define PACKET3_RB_OFFSET 0x4B
1658#define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C
1659#define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D
1660#define PACKET3_ALU_PS_CONST_UPDATE 0x4E
1661#define PACKET3_ALU_VS_CONST_UPDATE 0x4F
1662#define PACKET3_ONE_REG_WRITE 0x57
1663#define PACKET3_SET_CONFIG_REG 0x68
1664#define PACKET3_SET_CONFIG_REG_START 0x00008000
1665#define PACKET3_SET_CONFIG_REG_END 0x0000ac00
1666#define PACKET3_SET_CONTEXT_REG 0x69
1667#define PACKET3_SET_CONTEXT_REG_START 0x00028000
1668#define PACKET3_SET_CONTEXT_REG_END 0x00029000
1669#define PACKET3_SET_ALU_CONST 0x6A
1670/* alu const buffers only; no reg file */
1671#define PACKET3_SET_BOOL_CONST 0x6B
1672#define PACKET3_SET_BOOL_CONST_START 0x0003a500
1673#define PACKET3_SET_BOOL_CONST_END 0x0003a518
1674#define PACKET3_SET_LOOP_CONST 0x6C
1675#define PACKET3_SET_LOOP_CONST_START 0x0003a200
1676#define PACKET3_SET_LOOP_CONST_END 0x0003a500
1677#define PACKET3_SET_RESOURCE 0x6D
1678#define PACKET3_SET_RESOURCE_START 0x00030000
1679#define PACKET3_SET_RESOURCE_END 0x00038000
1680#define PACKET3_SET_SAMPLER 0x6E
1681#define PACKET3_SET_SAMPLER_START 0x0003c000
1682#define PACKET3_SET_SAMPLER_END 0x0003c600
1683#define PACKET3_SET_CTL_CONST 0x6F
1684#define PACKET3_SET_CTL_CONST_START 0x0003cff0
1685#define PACKET3_SET_CTL_CONST_END 0x0003ff0c
1686#define PACKET3_SET_RESOURCE_OFFSET 0x70
1687#define PACKET3_SET_ALU_CONST_VS 0x71
1688#define PACKET3_SET_ALU_CONST_DI 0x72
1689#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
1690#define PACKET3_SET_RESOURCE_INDIRECT 0x74
1691#define PACKET3_SET_APPEND_CNT 0x75
1692
1693#define SQ_RESOURCE_CONSTANT_WORD7_0 0x3001c
1694#define S__SQ_CONSTANT_TYPE(x) (((x) & 3) << 30)
1695#define G__SQ_CONSTANT_TYPE(x) (((x) >> 30) & 3)
1696#define SQ_TEX_VTX_INVALID_TEXTURE 0x0
1697#define SQ_TEX_VTX_INVALID_BUFFER 0x1
1698#define SQ_TEX_VTX_VALID_TEXTURE 0x2
1699#define SQ_TEX_VTX_VALID_BUFFER 0x3
1700
1701#define VGT_VTX_VECT_EJECT_REG 0x88b0
1702
1703#define SQ_CONST_MEM_BASE 0x8df8
1704
1705#define SQ_ESGS_RING_BASE 0x8c40
1706#define SQ_ESGS_RING_SIZE 0x8c44
1707#define SQ_GSVS_RING_BASE 0x8c48
1708#define SQ_GSVS_RING_SIZE 0x8c4c
1709#define SQ_ESTMP_RING_BASE 0x8c50
1710#define SQ_ESTMP_RING_SIZE 0x8c54
1711#define SQ_GSTMP_RING_BASE 0x8c58
1712#define SQ_GSTMP_RING_SIZE 0x8c5c
1713#define SQ_VSTMP_RING_BASE 0x8c60
1714#define SQ_VSTMP_RING_SIZE 0x8c64
1715#define SQ_PSTMP_RING_BASE 0x8c68
1716#define SQ_PSTMP_RING_SIZE 0x8c6c
1717#define SQ_LSTMP_RING_BASE 0x8e10
1718#define SQ_LSTMP_RING_SIZE 0x8e14
1719#define SQ_HSTMP_RING_BASE 0x8e18
1720#define SQ_HSTMP_RING_SIZE 0x8e1c
1721#define VGT_TF_RING_SIZE 0x8988
1722
1723#define SQ_ESGS_RING_ITEMSIZE 0x28900
1724#define SQ_GSVS_RING_ITEMSIZE 0x28904
1725#define SQ_ESTMP_RING_ITEMSIZE 0x28908
1726#define SQ_GSTMP_RING_ITEMSIZE 0x2890c
1727#define SQ_VSTMP_RING_ITEMSIZE 0x28910
1728#define SQ_PSTMP_RING_ITEMSIZE 0x28914
1729#define SQ_LSTMP_RING_ITEMSIZE 0x28830
1730#define SQ_HSTMP_RING_ITEMSIZE 0x28834
1731
1732#define SQ_GS_VERT_ITEMSIZE 0x2891c
1733#define SQ_GS_VERT_ITEMSIZE_1 0x28920
1734#define SQ_GS_VERT_ITEMSIZE_2 0x28924
1735#define SQ_GS_VERT_ITEMSIZE_3 0x28928
1736#define SQ_GSVS_RING_OFFSET_1 0x2892c
1737#define SQ_GSVS_RING_OFFSET_2 0x28930
1738#define SQ_GSVS_RING_OFFSET_3 0x28934
1739
1740#define SQ_ALU_CONST_BUFFER_SIZE_PS_0 0x28140
1741#define SQ_ALU_CONST_BUFFER_SIZE_HS_0 0x28f80
1742
1743#define SQ_ALU_CONST_CACHE_PS_0 0x28940
1744#define SQ_ALU_CONST_CACHE_PS_1 0x28944
1745#define SQ_ALU_CONST_CACHE_PS_2 0x28948
1746#define SQ_ALU_CONST_CACHE_PS_3 0x2894c
1747#define SQ_ALU_CONST_CACHE_PS_4 0x28950
1748#define SQ_ALU_CONST_CACHE_PS_5 0x28954
1749#define SQ_ALU_CONST_CACHE_PS_6 0x28958
1750#define SQ_ALU_CONST_CACHE_PS_7 0x2895c
1751#define SQ_ALU_CONST_CACHE_PS_8 0x28960
1752#define SQ_ALU_CONST_CACHE_PS_9 0x28964
1753#define SQ_ALU_CONST_CACHE_PS_10 0x28968
1754#define SQ_ALU_CONST_CACHE_PS_11 0x2896c
1755#define SQ_ALU_CONST_CACHE_PS_12 0x28970
1756#define SQ_ALU_CONST_CACHE_PS_13 0x28974
1757#define SQ_ALU_CONST_CACHE_PS_14 0x28978
1758#define SQ_ALU_CONST_CACHE_PS_15 0x2897c
1759#define SQ_ALU_CONST_CACHE_VS_0 0x28980
1760#define SQ_ALU_CONST_CACHE_VS_1 0x28984
1761#define SQ_ALU_CONST_CACHE_VS_2 0x28988
1762#define SQ_ALU_CONST_CACHE_VS_3 0x2898c
1763#define SQ_ALU_CONST_CACHE_VS_4 0x28990
1764#define SQ_ALU_CONST_CACHE_VS_5 0x28994
1765#define SQ_ALU_CONST_CACHE_VS_6 0x28998
1766#define SQ_ALU_CONST_CACHE_VS_7 0x2899c
1767#define SQ_ALU_CONST_CACHE_VS_8 0x289a0
1768#define SQ_ALU_CONST_CACHE_VS_9 0x289a4
1769#define SQ_ALU_CONST_CACHE_VS_10 0x289a8
1770#define SQ_ALU_CONST_CACHE_VS_11 0x289ac
1771#define SQ_ALU_CONST_CACHE_VS_12 0x289b0
1772#define SQ_ALU_CONST_CACHE_VS_13 0x289b4
1773#define SQ_ALU_CONST_CACHE_VS_14 0x289b8
1774#define SQ_ALU_CONST_CACHE_VS_15 0x289bc
1775#define SQ_ALU_CONST_CACHE_GS_0 0x289c0
1776#define SQ_ALU_CONST_CACHE_GS_1 0x289c4
1777#define SQ_ALU_CONST_CACHE_GS_2 0x289c8
1778#define SQ_ALU_CONST_CACHE_GS_3 0x289cc
1779#define SQ_ALU_CONST_CACHE_GS_4 0x289d0
1780#define SQ_ALU_CONST_CACHE_GS_5 0x289d4
1781#define SQ_ALU_CONST_CACHE_GS_6 0x289d8
1782#define SQ_ALU_CONST_CACHE_GS_7 0x289dc
1783#define SQ_ALU_CONST_CACHE_GS_8 0x289e0
1784#define SQ_ALU_CONST_CACHE_GS_9 0x289e4
1785#define SQ_ALU_CONST_CACHE_GS_10 0x289e8
1786#define SQ_ALU_CONST_CACHE_GS_11 0x289ec
1787#define SQ_ALU_CONST_CACHE_GS_12 0x289f0
1788#define SQ_ALU_CONST_CACHE_GS_13 0x289f4
1789#define SQ_ALU_CONST_CACHE_GS_14 0x289f8
1790#define SQ_ALU_CONST_CACHE_GS_15 0x289fc
1791#define SQ_ALU_CONST_CACHE_HS_0 0x28f00
1792#define SQ_ALU_CONST_CACHE_HS_1 0x28f04
1793#define SQ_ALU_CONST_CACHE_HS_2 0x28f08
1794#define SQ_ALU_CONST_CACHE_HS_3 0x28f0c
1795#define SQ_ALU_CONST_CACHE_HS_4 0x28f10
1796#define SQ_ALU_CONST_CACHE_HS_5 0x28f14
1797#define SQ_ALU_CONST_CACHE_HS_6 0x28f18
1798#define SQ_ALU_CONST_CACHE_HS_7 0x28f1c
1799#define SQ_ALU_CONST_CACHE_HS_8 0x28f20
1800#define SQ_ALU_CONST_CACHE_HS_9 0x28f24
1801#define SQ_ALU_CONST_CACHE_HS_10 0x28f28
1802#define SQ_ALU_CONST_CACHE_HS_11 0x28f2c
1803#define SQ_ALU_CONST_CACHE_HS_12 0x28f30
1804#define SQ_ALU_CONST_CACHE_HS_13 0x28f34
1805#define SQ_ALU_CONST_CACHE_HS_14 0x28f38
1806#define SQ_ALU_CONST_CACHE_HS_15 0x28f3c
1807#define SQ_ALU_CONST_CACHE_LS_0 0x28f40
1808#define SQ_ALU_CONST_CACHE_LS_1 0x28f44
1809#define SQ_ALU_CONST_CACHE_LS_2 0x28f48
1810#define SQ_ALU_CONST_CACHE_LS_3 0x28f4c
1811#define SQ_ALU_CONST_CACHE_LS_4 0x28f50
1812#define SQ_ALU_CONST_CACHE_LS_5 0x28f54
1813#define SQ_ALU_CONST_CACHE_LS_6 0x28f58
1814#define SQ_ALU_CONST_CACHE_LS_7 0x28f5c
1815#define SQ_ALU_CONST_CACHE_LS_8 0x28f60
1816#define SQ_ALU_CONST_CACHE_LS_9 0x28f64
1817#define SQ_ALU_CONST_CACHE_LS_10 0x28f68
1818#define SQ_ALU_CONST_CACHE_LS_11 0x28f6c
1819#define SQ_ALU_CONST_CACHE_LS_12 0x28f70
1820#define SQ_ALU_CONST_CACHE_LS_13 0x28f74
1821#define SQ_ALU_CONST_CACHE_LS_14 0x28f78
1822#define SQ_ALU_CONST_CACHE_LS_15 0x28f7c
1823
1824#define PA_SC_SCREEN_SCISSOR_TL 0x28030
1825#define PA_SC_GENERIC_SCISSOR_TL 0x28240
1826#define PA_SC_WINDOW_SCISSOR_TL 0x28204
1827
1828#define VGT_PRIMITIVE_TYPE 0x8958
1829#define VGT_INDEX_TYPE 0x895C
1830
1831#define VGT_NUM_INDICES 0x8970
1832
1833#define VGT_COMPUTE_DIM_X 0x8990
1834#define VGT_COMPUTE_DIM_Y 0x8994
1835#define VGT_COMPUTE_DIM_Z 0x8998
1836#define VGT_COMPUTE_START_X 0x899C
1837#define VGT_COMPUTE_START_Y 0x89A0
1838#define VGT_COMPUTE_START_Z 0x89A4
1839#define VGT_COMPUTE_INDEX 0x89A8
1840#define VGT_COMPUTE_THREAD_GROUP_SIZE 0x89AC
1841#define VGT_HS_OFFCHIP_PARAM 0x89B0
1842
1843#define DB_DEBUG 0x9830
1844#define DB_DEBUG2 0x9834
1845#define DB_DEBUG3 0x9838
1846#define DB_DEBUG4 0x983C
1847#define DB_WATERMARKS 0x9854
1848#define DB_DEPTH_CONTROL 0x28800
1849#define R_028800_DB_DEPTH_CONTROL 0x028800
1850#define S_028800_STENCIL_ENABLE(x) (((x) & 0x1) << 0)
1851#define G_028800_STENCIL_ENABLE(x) (((x) >> 0) & 0x1)
1852#define C_028800_STENCIL_ENABLE 0xFFFFFFFE
1853#define S_028800_Z_ENABLE(x) (((x) & 0x1) << 1)
1854#define G_028800_Z_ENABLE(x) (((x) >> 1) & 0x1)
1855#define C_028800_Z_ENABLE 0xFFFFFFFD
1856#define S_028800_Z_WRITE_ENABLE(x) (((x) & 0x1) << 2)
1857#define G_028800_Z_WRITE_ENABLE(x) (((x) >> 2) & 0x1)
1858#define C_028800_Z_WRITE_ENABLE 0xFFFFFFFB
1859#define S_028800_ZFUNC(x) (((x) & 0x7) << 4)
1860#define G_028800_ZFUNC(x) (((x) >> 4) & 0x7)
1861#define C_028800_ZFUNC 0xFFFFFF8F
1862#define S_028800_BACKFACE_ENABLE(x) (((x) & 0x1) << 7)
1863#define G_028800_BACKFACE_ENABLE(x) (((x) >> 7) & 0x1)
1864#define C_028800_BACKFACE_ENABLE 0xFFFFFF7F
1865#define S_028800_STENCILFUNC(x) (((x) & 0x7) << 8)
1866#define G_028800_STENCILFUNC(x) (((x) >> 8) & 0x7)
1867#define C_028800_STENCILFUNC 0xFFFFF8FF
1868#define V_028800_STENCILFUNC_NEVER 0x00000000
1869#define V_028800_STENCILFUNC_LESS 0x00000001
1870#define V_028800_STENCILFUNC_EQUAL 0x00000002
1871#define V_028800_STENCILFUNC_LEQUAL 0x00000003
1872#define V_028800_STENCILFUNC_GREATER 0x00000004
1873#define V_028800_STENCILFUNC_NOTEQUAL 0x00000005
1874#define V_028800_STENCILFUNC_GEQUAL 0x00000006
1875#define V_028800_STENCILFUNC_ALWAYS 0x00000007
1876#define S_028800_STENCILFAIL(x) (((x) & 0x7) << 11)
1877#define G_028800_STENCILFAIL(x) (((x) >> 11) & 0x7)
1878#define C_028800_STENCILFAIL 0xFFFFC7FF
1879#define V_028800_STENCIL_KEEP 0x00000000
1880#define V_028800_STENCIL_ZERO 0x00000001
1881#define V_028800_STENCIL_REPLACE 0x00000002
1882#define V_028800_STENCIL_INCR 0x00000003
1883#define V_028800_STENCIL_DECR 0x00000004
1884#define V_028800_STENCIL_INVERT 0x00000005
1885#define V_028800_STENCIL_INCR_WRAP 0x00000006
1886#define V_028800_STENCIL_DECR_WRAP 0x00000007
1887#define S_028800_STENCILZPASS(x) (((x) & 0x7) << 14)
1888#define G_028800_STENCILZPASS(x) (((x) >> 14) & 0x7)
1889#define C_028800_STENCILZPASS 0xFFFE3FFF
1890#define S_028800_STENCILZFAIL(x) (((x) & 0x7) << 17)
1891#define G_028800_STENCILZFAIL(x) (((x) >> 17) & 0x7)
1892#define C_028800_STENCILZFAIL 0xFFF1FFFF
1893#define S_028800_STENCILFUNC_BF(x) (((x) & 0x7) << 20)
1894#define G_028800_STENCILFUNC_BF(x) (((x) >> 20) & 0x7)
1895#define C_028800_STENCILFUNC_BF 0xFF8FFFFF
1896#define S_028800_STENCILFAIL_BF(x) (((x) & 0x7) << 23)
1897#define G_028800_STENCILFAIL_BF(x) (((x) >> 23) & 0x7)
1898#define C_028800_STENCILFAIL_BF 0xFC7FFFFF
1899#define S_028800_STENCILZPASS_BF(x) (((x) & 0x7) << 26)
1900#define G_028800_STENCILZPASS_BF(x) (((x) >> 26) & 0x7)
1901#define C_028800_STENCILZPASS_BF 0xE3FFFFFF
1902#define S_028800_STENCILZFAIL_BF(x) (((x) & 0x7) << 29)
1903#define G_028800_STENCILZFAIL_BF(x) (((x) >> 29) & 0x7)
1904#define C_028800_STENCILZFAIL_BF 0x1FFFFFFF
1905#define DB_DEPTH_VIEW 0x28008
1906#define R_028008_DB_DEPTH_VIEW 0x00028008
1907#define S_028008_SLICE_START(x) (((x) & 0x7FF) << 0)
1908#define G_028008_SLICE_START(x) (((x) >> 0) & 0x7FF)
1909#define C_028008_SLICE_START 0xFFFFF800
1910#define S_028008_SLICE_MAX(x) (((x) & 0x7FF) << 13)
1911#define G_028008_SLICE_MAX(x) (((x) >> 13) & 0x7FF)
1912#define C_028008_SLICE_MAX 0xFF001FFF
1913#define DB_HTILE_DATA_BASE 0x28014
1914#define DB_HTILE_SURFACE 0x28abc
1915#define S_028ABC_HTILE_WIDTH(x) (((x) & 0x1) << 0)
1916#define G_028ABC_HTILE_WIDTH(x) (((x) >> 0) & 0x1)
1917#define C_028ABC_HTILE_WIDTH 0xFFFFFFFE
1918#define S_028ABC_HTILE_HEIGHT(x) (((x) & 0x1) << 1)
1919#define G_028ABC_HTILE_HEIGHT(x) (((x) >> 1) & 0x1)
1920#define C_028ABC_HTILE_HEIGHT 0xFFFFFFFD
1921#define G_028ABC_LINEAR(x) (((x) >> 2) & 0x1)
1922#define DB_Z_INFO 0x28040
1923# define Z_ARRAY_MODE(x) ((x) << 4)
1924# define DB_TILE_SPLIT(x) (((x) & 0x7) << 8)
1925# define DB_NUM_BANKS(x) (((x) & 0x3) << 12)
1926# define DB_BANK_WIDTH(x) (((x) & 0x3) << 16)
1927# define DB_BANK_HEIGHT(x) (((x) & 0x3) << 20)
1928# define DB_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 24)
1929#define R_028040_DB_Z_INFO 0x028040
1930#define S_028040_FORMAT(x) (((x) & 0x3) << 0)
1931#define G_028040_FORMAT(x) (((x) >> 0) & 0x3)
1932#define C_028040_FORMAT 0xFFFFFFFC
1933#define V_028040_Z_INVALID 0x00000000
1934#define V_028040_Z_16 0x00000001
1935#define V_028040_Z_24 0x00000002
1936#define V_028040_Z_32_FLOAT 0x00000003
1937#define S_028040_ARRAY_MODE(x) (((x) & 0xF) << 4)
1938#define G_028040_ARRAY_MODE(x) (((x) >> 4) & 0xF)
1939#define C_028040_ARRAY_MODE 0xFFFFFF0F
1940#define S_028040_READ_SIZE(x) (((x) & 0x1) << 28)
1941#define G_028040_READ_SIZE(x) (((x) >> 28) & 0x1)
1942#define C_028040_READ_SIZE 0xEFFFFFFF
1943#define S_028040_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 29)
1944#define G_028040_TILE_SURFACE_ENABLE(x) (((x) >> 29) & 0x1)
1945#define C_028040_TILE_SURFACE_ENABLE 0xDFFFFFFF
1946#define S_028040_ZRANGE_PRECISION(x) (((x) & 0x1) << 31)
1947#define G_028040_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1)
1948#define C_028040_ZRANGE_PRECISION 0x7FFFFFFF
1949#define S_028040_TILE_SPLIT(x) (((x) & 0x7) << 8)
1950#define G_028040_TILE_SPLIT(x) (((x) >> 8) & 0x7)
1951#define S_028040_NUM_BANKS(x) (((x) & 0x3) << 12)
1952#define G_028040_NUM_BANKS(x) (((x) >> 12) & 0x3)
1953#define S_028040_BANK_WIDTH(x) (((x) & 0x3) << 16)
1954#define G_028040_BANK_WIDTH(x) (((x) >> 16) & 0x3)
1955#define S_028040_BANK_HEIGHT(x) (((x) & 0x3) << 20)
1956#define G_028040_BANK_HEIGHT(x) (((x) >> 20) & 0x3)
1957#define S_028040_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 24)
1958#define G_028040_MACRO_TILE_ASPECT(x) (((x) >> 24) & 0x3)
1959#define DB_STENCIL_INFO 0x28044
1960#define R_028044_DB_STENCIL_INFO 0x028044
1961#define S_028044_FORMAT(x) (((x) & 0x1) << 0)
1962#define G_028044_FORMAT(x) (((x) >> 0) & 0x1)
1963#define C_028044_FORMAT 0xFFFFFFFE
1964#define V_028044_STENCIL_INVALID 0
1965#define V_028044_STENCIL_8 1
1966#define G_028044_TILE_SPLIT(x) (((x) >> 8) & 0x7)
1967#define DB_Z_READ_BASE 0x28048
1968#define DB_STENCIL_READ_BASE 0x2804c
1969#define DB_Z_WRITE_BASE 0x28050
1970#define DB_STENCIL_WRITE_BASE 0x28054
1971#define DB_DEPTH_SIZE 0x28058
1972#define R_028058_DB_DEPTH_SIZE 0x028058
1973#define S_028058_PITCH_TILE_MAX(x) (((x) & 0x7FF) << 0)
1974#define G_028058_PITCH_TILE_MAX(x) (((x) >> 0) & 0x7FF)
1975#define C_028058_PITCH_TILE_MAX 0xFFFFF800
1976#define S_028058_HEIGHT_TILE_MAX(x) (((x) & 0x7FF) << 11)
1977#define G_028058_HEIGHT_TILE_MAX(x) (((x) >> 11) & 0x7FF)
1978#define C_028058_HEIGHT_TILE_MAX 0xFFC007FF
1979#define R_02805C_DB_DEPTH_SLICE 0x02805C
1980#define S_02805C_SLICE_TILE_MAX(x) (((x) & 0x3FFFFF) << 0)
1981#define G_02805C_SLICE_TILE_MAX(x) (((x) >> 0) & 0x3FFFFF)
1982#define C_02805C_SLICE_TILE_MAX 0xFFC00000
1983
1984#define SQ_PGM_START_PS 0x28840
1985#define SQ_PGM_START_VS 0x2885c
1986#define SQ_PGM_START_GS 0x28874
1987#define SQ_PGM_START_ES 0x2888c
1988#define SQ_PGM_START_FS 0x288a4
1989#define SQ_PGM_START_HS 0x288b8
1990#define SQ_PGM_START_LS 0x288d0
1991
1992#define VGT_STRMOUT_BUFFER_BASE_0 0x28AD8
1993#define VGT_STRMOUT_BUFFER_BASE_1 0x28AE8
1994#define VGT_STRMOUT_BUFFER_BASE_2 0x28AF8
1995#define VGT_STRMOUT_BUFFER_BASE_3 0x28B08
1996#define VGT_STRMOUT_BUFFER_SIZE_0 0x28AD0
1997#define VGT_STRMOUT_BUFFER_SIZE_1 0x28AE0
1998#define VGT_STRMOUT_BUFFER_SIZE_2 0x28AF0
1999#define VGT_STRMOUT_BUFFER_SIZE_3 0x28B00
2000#define VGT_STRMOUT_CONFIG 0x28b94
2001#define VGT_STRMOUT_BUFFER_CONFIG 0x28b98
2002
2003#define CB_TARGET_MASK 0x28238
2004#define CB_SHADER_MASK 0x2823c
2005
2006#define GDS_ADDR_BASE 0x28720
2007
2008#define CB_IMMED0_BASE 0x28b9c
2009#define CB_IMMED1_BASE 0x28ba0
2010#define CB_IMMED2_BASE 0x28ba4
2011#define CB_IMMED3_BASE 0x28ba8
2012#define CB_IMMED4_BASE 0x28bac
2013#define CB_IMMED5_BASE 0x28bb0
2014#define CB_IMMED6_BASE 0x28bb4
2015#define CB_IMMED7_BASE 0x28bb8
2016#define CB_IMMED8_BASE 0x28bbc
2017#define CB_IMMED9_BASE 0x28bc0
2018#define CB_IMMED10_BASE 0x28bc4
2019#define CB_IMMED11_BASE 0x28bc8
2020
2021/* all 12 CB blocks have these regs */
2022#define CB_COLOR0_BASE 0x28c60
2023#define CB_COLOR0_PITCH 0x28c64
2024#define CB_COLOR0_SLICE 0x28c68
2025#define CB_COLOR0_VIEW 0x28c6c
2026#define R_028C6C_CB_COLOR0_VIEW 0x00028C6C
2027#define S_028C6C_SLICE_START(x) (((x) & 0x7FF) << 0)
2028#define G_028C6C_SLICE_START(x) (((x) >> 0) & 0x7FF)
2029#define C_028C6C_SLICE_START 0xFFFFF800
2030#define S_028C6C_SLICE_MAX(x) (((x) & 0x7FF) << 13)
2031#define G_028C6C_SLICE_MAX(x) (((x) >> 13) & 0x7FF)
2032#define C_028C6C_SLICE_MAX 0xFF001FFF
2033#define R_028C70_CB_COLOR0_INFO 0x028C70
2034#define S_028C70_ENDIAN(x) (((x) & 0x3) << 0)
2035#define G_028C70_ENDIAN(x) (((x) >> 0) & 0x3)
2036#define C_028C70_ENDIAN 0xFFFFFFFC
2037#define S_028C70_FORMAT(x) (((x) & 0x3F) << 2)
2038#define G_028C70_FORMAT(x) (((x) >> 2) & 0x3F)
2039#define C_028C70_FORMAT 0xFFFFFF03
2040#define V_028C70_COLOR_INVALID 0x00000000
2041#define V_028C70_COLOR_8 0x00000001
2042#define V_028C70_COLOR_4_4 0x00000002
2043#define V_028C70_COLOR_3_3_2 0x00000003
2044#define V_028C70_COLOR_16 0x00000005
2045#define V_028C70_COLOR_16_FLOAT 0x00000006
2046#define V_028C70_COLOR_8_8 0x00000007
2047#define V_028C70_COLOR_5_6_5 0x00000008
2048#define V_028C70_COLOR_6_5_5 0x00000009
2049#define V_028C70_COLOR_1_5_5_5 0x0000000A
2050#define V_028C70_COLOR_4_4_4_4 0x0000000B
2051#define V_028C70_COLOR_5_5_5_1 0x0000000C
2052#define V_028C70_COLOR_32 0x0000000D
2053#define V_028C70_COLOR_32_FLOAT 0x0000000E
2054#define V_028C70_COLOR_16_16 0x0000000F
2055#define V_028C70_COLOR_16_16_FLOAT 0x00000010
2056#define V_028C70_COLOR_8_24 0x00000011
2057#define V_028C70_COLOR_8_24_FLOAT 0x00000012
2058#define V_028C70_COLOR_24_8 0x00000013
2059#define V_028C70_COLOR_24_8_FLOAT 0x00000014
2060#define V_028C70_COLOR_10_11_11 0x00000015
2061#define V_028C70_COLOR_10_11_11_FLOAT 0x00000016
2062#define V_028C70_COLOR_11_11_10 0x00000017
2063#define V_028C70_COLOR_11_11_10_FLOAT 0x00000018
2064#define V_028C70_COLOR_2_10_10_10 0x00000019
2065#define V_028C70_COLOR_8_8_8_8 0x0000001A
2066#define V_028C70_COLOR_10_10_10_2 0x0000001B
2067#define V_028C70_COLOR_X24_8_32_FLOAT 0x0000001C
2068#define V_028C70_COLOR_32_32 0x0000001D
2069#define V_028C70_COLOR_32_32_FLOAT 0x0000001E
2070#define V_028C70_COLOR_16_16_16_16 0x0000001F
2071#define V_028C70_COLOR_16_16_16_16_FLOAT 0x00000020
2072#define V_028C70_COLOR_32_32_32_32 0x00000022
2073#define V_028C70_COLOR_32_32_32_32_FLOAT 0x00000023
2074#define V_028C70_COLOR_32_32_32_FLOAT 0x00000030
2075#define S_028C70_ARRAY_MODE(x) (((x) & 0xF) << 8)
2076#define G_028C70_ARRAY_MODE(x) (((x) >> 8) & 0xF)
2077#define C_028C70_ARRAY_MODE 0xFFFFF0FF
2078#define V_028C70_ARRAY_LINEAR_GENERAL 0x00000000
2079#define V_028C70_ARRAY_LINEAR_ALIGNED 0x00000001
2080#define V_028C70_ARRAY_1D_TILED_THIN1 0x00000002
2081#define V_028C70_ARRAY_2D_TILED_THIN1 0x00000004
2082#define S_028C70_NUMBER_TYPE(x) (((x) & 0x7) << 12)
2083#define G_028C70_NUMBER_TYPE(x) (((x) >> 12) & 0x7)
2084#define C_028C70_NUMBER_TYPE 0xFFFF8FFF
2085#define V_028C70_NUMBER_UNORM 0x00000000
2086#define V_028C70_NUMBER_SNORM 0x00000001
2087#define V_028C70_NUMBER_USCALED 0x00000002
2088#define V_028C70_NUMBER_SSCALED 0x00000003
2089#define V_028C70_NUMBER_UINT 0x00000004
2090#define V_028C70_NUMBER_SINT 0x00000005
2091#define V_028C70_NUMBER_SRGB 0x00000006
2092#define V_028C70_NUMBER_FLOAT 0x00000007
2093#define S_028C70_COMP_SWAP(x) (((x) & 0x3) << 15)
2094#define G_028C70_COMP_SWAP(x) (((x) >> 15) & 0x3)
2095#define C_028C70_COMP_SWAP 0xFFFE7FFF
2096#define V_028C70_SWAP_STD 0x00000000
2097#define V_028C70_SWAP_ALT 0x00000001
2098#define V_028C70_SWAP_STD_REV 0x00000002
2099#define V_028C70_SWAP_ALT_REV 0x00000003
2100#define S_028C70_FAST_CLEAR(x) (((x) & 0x1) << 17)
2101#define G_028C70_FAST_CLEAR(x) (((x) >> 17) & 0x1)
2102#define C_028C70_FAST_CLEAR 0xFFFDFFFF
2103#define S_028C70_COMPRESSION(x) (((x) & 0x3) << 18)
2104#define G_028C70_COMPRESSION(x) (((x) >> 18) & 0x3)
2105#define C_028C70_COMPRESSION 0xFFF3FFFF
2106#define S_028C70_BLEND_CLAMP(x) (((x) & 0x1) << 19)
2107#define G_028C70_BLEND_CLAMP(x) (((x) >> 19) & 0x1)
2108#define C_028C70_BLEND_CLAMP 0xFFF7FFFF
2109#define S_028C70_BLEND_BYPASS(x) (((x) & 0x1) << 20)
2110#define G_028C70_BLEND_BYPASS(x) (((x) >> 20) & 0x1)
2111#define C_028C70_BLEND_BYPASS 0xFFEFFFFF
2112#define S_028C70_SIMPLE_FLOAT(x) (((x) & 0x1) << 21)
2113#define G_028C70_SIMPLE_FLOAT(x) (((x) >> 21) & 0x1)
2114#define C_028C70_SIMPLE_FLOAT 0xFFDFFFFF
2115#define S_028C70_ROUND_MODE(x) (((x) & 0x1) << 22)
2116#define G_028C70_ROUND_MODE(x) (((x) >> 22) & 0x1)
2117#define C_028C70_ROUND_MODE 0xFFBFFFFF
2118#define S_028C70_TILE_COMPACT(x) (((x) & 0x1) << 23)
2119#define G_028C70_TILE_COMPACT(x) (((x) >> 23) & 0x1)
2120#define C_028C70_TILE_COMPACT 0xFF7FFFFF
2121#define S_028C70_SOURCE_FORMAT(x) (((x) & 0x3) << 24)
2122#define G_028C70_SOURCE_FORMAT(x) (((x) >> 24) & 0x3)
2123#define C_028C70_SOURCE_FORMAT 0xFCFFFFFF
2124#define V_028C70_EXPORT_4C_32BPC 0x0
2125#define V_028C70_EXPORT_4C_16BPC 0x1
2126#define V_028C70_EXPORT_2C_32BPC 0x2 /* Do not use */
2127#define S_028C70_RAT(x) (((x) & 0x1) << 26)
2128#define G_028C70_RAT(x) (((x) >> 26) & 0x1)
2129#define C_028C70_RAT 0xFBFFFFFF
2130#define S_028C70_RESOURCE_TYPE(x) (((x) & 0x7) << 27)
2131#define G_028C70_RESOURCE_TYPE(x) (((x) >> 27) & 0x7)
2132#define C_028C70_RESOURCE_TYPE 0xC7FFFFFF
2133
2134#define CB_COLOR0_INFO 0x28c70
2135# define CB_FORMAT(x) ((x) << 2)
2136# define CB_ARRAY_MODE(x) ((x) << 8)
2137# define ARRAY_LINEAR_GENERAL 0
2138# define ARRAY_LINEAR_ALIGNED 1
2139# define ARRAY_1D_TILED_THIN1 2
2140# define ARRAY_2D_TILED_THIN1 4
2141# define CB_SOURCE_FORMAT(x) ((x) << 24)
2142# define CB_SF_EXPORT_FULL 0
2143# define CB_SF_EXPORT_NORM 1
2144#define R_028C74_CB_COLOR0_ATTRIB 0x028C74
2145#define S_028C74_NON_DISP_TILING_ORDER(x) (((x) & 0x1) << 4)
2146#define G_028C74_NON_DISP_TILING_ORDER(x) (((x) >> 4) & 0x1)
2147#define C_028C74_NON_DISP_TILING_ORDER 0xFFFFFFEF
2148#define S_028C74_TILE_SPLIT(x) (((x) & 0xf) << 5)
2149#define G_028C74_TILE_SPLIT(x) (((x) >> 5) & 0xf)
2150#define S_028C74_NUM_BANKS(x) (((x) & 0x3) << 10)
2151#define G_028C74_NUM_BANKS(x) (((x) >> 10) & 0x3)
2152#define S_028C74_BANK_WIDTH(x) (((x) & 0x3) << 13)
2153#define G_028C74_BANK_WIDTH(x) (((x) >> 13) & 0x3)
2154#define S_028C74_BANK_HEIGHT(x) (((x) & 0x3) << 16)
2155#define G_028C74_BANK_HEIGHT(x) (((x) >> 16) & 0x3)
2156#define S_028C74_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 19)
2157#define G_028C74_MACRO_TILE_ASPECT(x) (((x) >> 19) & 0x3)
2158#define CB_COLOR0_ATTRIB 0x28c74
2159# define CB_TILE_SPLIT(x) (((x) & 0x7) << 5)
2160# define ADDR_SURF_TILE_SPLIT_64B 0
2161# define ADDR_SURF_TILE_SPLIT_128B 1
2162# define ADDR_SURF_TILE_SPLIT_256B 2
2163# define ADDR_SURF_TILE_SPLIT_512B 3
2164# define ADDR_SURF_TILE_SPLIT_1KB 4
2165# define ADDR_SURF_TILE_SPLIT_2KB 5
2166# define ADDR_SURF_TILE_SPLIT_4KB 6
2167# define CB_NUM_BANKS(x) (((x) & 0x3) << 10)
2168# define ADDR_SURF_2_BANK 0
2169# define ADDR_SURF_4_BANK 1
2170# define ADDR_SURF_8_BANK 2
2171# define ADDR_SURF_16_BANK 3
2172# define CB_BANK_WIDTH(x) (((x) & 0x3) << 13)
2173# define ADDR_SURF_BANK_WIDTH_1 0
2174# define ADDR_SURF_BANK_WIDTH_2 1
2175# define ADDR_SURF_BANK_WIDTH_4 2
2176# define ADDR_SURF_BANK_WIDTH_8 3
2177# define CB_BANK_HEIGHT(x) (((x) & 0x3) << 16)
2178# define ADDR_SURF_BANK_HEIGHT_1 0
2179# define ADDR_SURF_BANK_HEIGHT_2 1
2180# define ADDR_SURF_BANK_HEIGHT_4 2
2181# define ADDR_SURF_BANK_HEIGHT_8 3
2182# define CB_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 19)
2183#define CB_COLOR0_DIM 0x28c78
2184/* only CB0-7 blocks have these regs */
2185#define CB_COLOR0_CMASK 0x28c7c
2186#define CB_COLOR0_CMASK_SLICE 0x28c80
2187#define CB_COLOR0_FMASK 0x28c84
2188#define CB_COLOR0_FMASK_SLICE 0x28c88
2189#define CB_COLOR0_CLEAR_WORD0 0x28c8c
2190#define CB_COLOR0_CLEAR_WORD1 0x28c90
2191#define CB_COLOR0_CLEAR_WORD2 0x28c94
2192#define CB_COLOR0_CLEAR_WORD3 0x28c98
2193
2194#define CB_COLOR1_BASE 0x28c9c
2195#define CB_COLOR2_BASE 0x28cd8
2196#define CB_COLOR3_BASE 0x28d14
2197#define CB_COLOR4_BASE 0x28d50
2198#define CB_COLOR5_BASE 0x28d8c
2199#define CB_COLOR6_BASE 0x28dc8
2200#define CB_COLOR7_BASE 0x28e04
2201#define CB_COLOR8_BASE 0x28e40
2202#define CB_COLOR9_BASE 0x28e5c
2203#define CB_COLOR10_BASE 0x28e78
2204#define CB_COLOR11_BASE 0x28e94
2205
2206#define CB_COLOR1_PITCH 0x28ca0
2207#define CB_COLOR2_PITCH 0x28cdc
2208#define CB_COLOR3_PITCH 0x28d18
2209#define CB_COLOR4_PITCH 0x28d54
2210#define CB_COLOR5_PITCH 0x28d90
2211#define CB_COLOR6_PITCH 0x28dcc
2212#define CB_COLOR7_PITCH 0x28e08
2213#define CB_COLOR8_PITCH 0x28e44
2214#define CB_COLOR9_PITCH 0x28e60
2215#define CB_COLOR10_PITCH 0x28e7c
2216#define CB_COLOR11_PITCH 0x28e98
2217
2218#define CB_COLOR1_SLICE 0x28ca4
2219#define CB_COLOR2_SLICE 0x28ce0
2220#define CB_COLOR3_SLICE 0x28d1c
2221#define CB_COLOR4_SLICE 0x28d58
2222#define CB_COLOR5_SLICE 0x28d94
2223#define CB_COLOR6_SLICE 0x28dd0
2224#define CB_COLOR7_SLICE 0x28e0c
2225#define CB_COLOR8_SLICE 0x28e48
2226#define CB_COLOR9_SLICE 0x28e64
2227#define CB_COLOR10_SLICE 0x28e80
2228#define CB_COLOR11_SLICE 0x28e9c
2229
2230#define CB_COLOR1_VIEW 0x28ca8
2231#define CB_COLOR2_VIEW 0x28ce4
2232#define CB_COLOR3_VIEW 0x28d20
2233#define CB_COLOR4_VIEW 0x28d5c
2234#define CB_COLOR5_VIEW 0x28d98
2235#define CB_COLOR6_VIEW 0x28dd4
2236#define CB_COLOR7_VIEW 0x28e10
2237#define CB_COLOR8_VIEW 0x28e4c
2238#define CB_COLOR9_VIEW 0x28e68
2239#define CB_COLOR10_VIEW 0x28e84
2240#define CB_COLOR11_VIEW 0x28ea0
2241
2242#define CB_COLOR1_INFO 0x28cac
2243#define CB_COLOR2_INFO 0x28ce8
2244#define CB_COLOR3_INFO 0x28d24
2245#define CB_COLOR4_INFO 0x28d60
2246#define CB_COLOR5_INFO 0x28d9c
2247#define CB_COLOR6_INFO 0x28dd8
2248#define CB_COLOR7_INFO 0x28e14
2249#define CB_COLOR8_INFO 0x28e50
2250#define CB_COLOR9_INFO 0x28e6c
2251#define CB_COLOR10_INFO 0x28e88
2252#define CB_COLOR11_INFO 0x28ea4
2253
2254#define CB_COLOR1_ATTRIB 0x28cb0
2255#define CB_COLOR2_ATTRIB 0x28cec
2256#define CB_COLOR3_ATTRIB 0x28d28
2257#define CB_COLOR4_ATTRIB 0x28d64
2258#define CB_COLOR5_ATTRIB 0x28da0
2259#define CB_COLOR6_ATTRIB 0x28ddc
2260#define CB_COLOR7_ATTRIB 0x28e18
2261#define CB_COLOR8_ATTRIB 0x28e54
2262#define CB_COLOR9_ATTRIB 0x28e70
2263#define CB_COLOR10_ATTRIB 0x28e8c
2264#define CB_COLOR11_ATTRIB 0x28ea8
2265
2266#define CB_COLOR1_DIM 0x28cb4
2267#define CB_COLOR2_DIM 0x28cf0
2268#define CB_COLOR3_DIM 0x28d2c
2269#define CB_COLOR4_DIM 0x28d68
2270#define CB_COLOR5_DIM 0x28da4
2271#define CB_COLOR6_DIM 0x28de0
2272#define CB_COLOR7_DIM 0x28e1c
2273#define CB_COLOR8_DIM 0x28e58
2274#define CB_COLOR9_DIM 0x28e74
2275#define CB_COLOR10_DIM 0x28e90
2276#define CB_COLOR11_DIM 0x28eac
2277
2278#define CB_COLOR1_CMASK 0x28cb8
2279#define CB_COLOR2_CMASK 0x28cf4
2280#define CB_COLOR3_CMASK 0x28d30
2281#define CB_COLOR4_CMASK 0x28d6c
2282#define CB_COLOR5_CMASK 0x28da8
2283#define CB_COLOR6_CMASK 0x28de4
2284#define CB_COLOR7_CMASK 0x28e20
2285
2286#define CB_COLOR1_CMASK_SLICE 0x28cbc
2287#define CB_COLOR2_CMASK_SLICE 0x28cf8
2288#define CB_COLOR3_CMASK_SLICE 0x28d34
2289#define CB_COLOR4_CMASK_SLICE 0x28d70
2290#define CB_COLOR5_CMASK_SLICE 0x28dac
2291#define CB_COLOR6_CMASK_SLICE 0x28de8
2292#define CB_COLOR7_CMASK_SLICE 0x28e24
2293
2294#define CB_COLOR1_FMASK 0x28cc0
2295#define CB_COLOR2_FMASK 0x28cfc
2296#define CB_COLOR3_FMASK 0x28d38
2297#define CB_COLOR4_FMASK 0x28d74
2298#define CB_COLOR5_FMASK 0x28db0
2299#define CB_COLOR6_FMASK 0x28dec
2300#define CB_COLOR7_FMASK 0x28e28
2301
2302#define CB_COLOR1_FMASK_SLICE 0x28cc4
2303#define CB_COLOR2_FMASK_SLICE 0x28d00
2304#define CB_COLOR3_FMASK_SLICE 0x28d3c
2305#define CB_COLOR4_FMASK_SLICE 0x28d78
2306#define CB_COLOR5_FMASK_SLICE 0x28db4
2307#define CB_COLOR6_FMASK_SLICE 0x28df0
2308#define CB_COLOR7_FMASK_SLICE 0x28e2c
2309
2310#define CB_COLOR1_CLEAR_WORD0 0x28cc8
2311#define CB_COLOR2_CLEAR_WORD0 0x28d04
2312#define CB_COLOR3_CLEAR_WORD0 0x28d40
2313#define CB_COLOR4_CLEAR_WORD0 0x28d7c
2314#define CB_COLOR5_CLEAR_WORD0 0x28db8
2315#define CB_COLOR6_CLEAR_WORD0 0x28df4
2316#define CB_COLOR7_CLEAR_WORD0 0x28e30
2317
2318#define CB_COLOR1_CLEAR_WORD1 0x28ccc
2319#define CB_COLOR2_CLEAR_WORD1 0x28d08
2320#define CB_COLOR3_CLEAR_WORD1 0x28d44
2321#define CB_COLOR4_CLEAR_WORD1 0x28d80
2322#define CB_COLOR5_CLEAR_WORD1 0x28dbc
2323#define CB_COLOR6_CLEAR_WORD1 0x28df8
2324#define CB_COLOR7_CLEAR_WORD1 0x28e34
2325
2326#define CB_COLOR1_CLEAR_WORD2 0x28cd0
2327#define CB_COLOR2_CLEAR_WORD2 0x28d0c
2328#define CB_COLOR3_CLEAR_WORD2 0x28d48
2329#define CB_COLOR4_CLEAR_WORD2 0x28d84
2330#define CB_COLOR5_CLEAR_WORD2 0x28dc0
2331#define CB_COLOR6_CLEAR_WORD2 0x28dfc
2332#define CB_COLOR7_CLEAR_WORD2 0x28e38
2333
2334#define CB_COLOR1_CLEAR_WORD3 0x28cd4
2335#define CB_COLOR2_CLEAR_WORD3 0x28d10
2336#define CB_COLOR3_CLEAR_WORD3 0x28d4c
2337#define CB_COLOR4_CLEAR_WORD3 0x28d88
2338#define CB_COLOR5_CLEAR_WORD3 0x28dc4
2339#define CB_COLOR6_CLEAR_WORD3 0x28e00
2340#define CB_COLOR7_CLEAR_WORD3 0x28e3c
2341
2342#define SQ_TEX_RESOURCE_WORD0_0 0x30000
2343# define TEX_DIM(x) ((x) << 0)
2344# define SQ_TEX_DIM_1D 0
2345# define SQ_TEX_DIM_2D 1
2346# define SQ_TEX_DIM_3D 2
2347# define SQ_TEX_DIM_CUBEMAP 3
2348# define SQ_TEX_DIM_1D_ARRAY 4
2349# define SQ_TEX_DIM_2D_ARRAY 5
2350# define SQ_TEX_DIM_2D_MSAA 6
2351# define SQ_TEX_DIM_2D_ARRAY_MSAA 7
2352#define SQ_TEX_RESOURCE_WORD1_0 0x30004
2353# define TEX_ARRAY_MODE(x) ((x) << 28)
2354#define SQ_TEX_RESOURCE_WORD2_0 0x30008
2355#define SQ_TEX_RESOURCE_WORD3_0 0x3000C
2356#define SQ_TEX_RESOURCE_WORD4_0 0x30010
2357# define TEX_DST_SEL_X(x) ((x) << 16)
2358# define TEX_DST_SEL_Y(x) ((x) << 19)
2359# define TEX_DST_SEL_Z(x) ((x) << 22)
2360# define TEX_DST_SEL_W(x) ((x) << 25)
2361# define SQ_SEL_X 0
2362# define SQ_SEL_Y 1
2363# define SQ_SEL_Z 2
2364# define SQ_SEL_W 3
2365# define SQ_SEL_0 4
2366# define SQ_SEL_1 5
2367#define SQ_TEX_RESOURCE_WORD5_0 0x30014
2368#define SQ_TEX_RESOURCE_WORD6_0 0x30018
2369# define TEX_TILE_SPLIT(x) (((x) & 0x7) << 29)
2370#define SQ_TEX_RESOURCE_WORD7_0 0x3001c
2371# define MACRO_TILE_ASPECT(x) (((x) & 0x3) << 6)
2372# define TEX_BANK_WIDTH(x) (((x) & 0x3) << 8)
2373# define TEX_BANK_HEIGHT(x) (((x) & 0x3) << 10)
2374# define TEX_NUM_BANKS(x) (((x) & 0x3) << 16)
2375#define R_030000_SQ_TEX_RESOURCE_WORD0_0 0x030000
2376#define S_030000_DIM(x) (((x) & 0x7) << 0)
2377#define G_030000_DIM(x) (((x) >> 0) & 0x7)
2378#define C_030000_DIM 0xFFFFFFF8
2379#define V_030000_SQ_TEX_DIM_1D 0x00000000
2380#define V_030000_SQ_TEX_DIM_2D 0x00000001
2381#define V_030000_SQ_TEX_DIM_3D 0x00000002
2382#define V_030000_SQ_TEX_DIM_CUBEMAP 0x00000003
2383#define V_030000_SQ_TEX_DIM_1D_ARRAY 0x00000004
2384#define V_030000_SQ_TEX_DIM_2D_ARRAY 0x00000005
2385#define V_030000_SQ_TEX_DIM_2D_MSAA 0x00000006
2386#define V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA 0x00000007
2387#define S_030000_NON_DISP_TILING_ORDER(x) (((x) & 0x1) << 5)
2388#define G_030000_NON_DISP_TILING_ORDER(x) (((x) >> 5) & 0x1)
2389#define C_030000_NON_DISP_TILING_ORDER 0xFFFFFFDF
2390#define S_030000_PITCH(x) (((x) & 0xFFF) << 6)
2391#define G_030000_PITCH(x) (((x) >> 6) & 0xFFF)
2392#define C_030000_PITCH 0xFFFC003F
2393#define S_030000_TEX_WIDTH(x) (((x) & 0x3FFF) << 18)
2394#define G_030000_TEX_WIDTH(x) (((x) >> 18) & 0x3FFF)
2395#define C_030000_TEX_WIDTH 0x0003FFFF
2396#define R_030004_SQ_TEX_RESOURCE_WORD1_0 0x030004
2397#define S_030004_TEX_HEIGHT(x) (((x) & 0x3FFF) << 0)
2398#define G_030004_TEX_HEIGHT(x) (((x) >> 0) & 0x3FFF)
2399#define C_030004_TEX_HEIGHT 0xFFFFC000
2400#define S_030004_TEX_DEPTH(x) (((x) & 0x1FFF) << 14)
2401#define G_030004_TEX_DEPTH(x) (((x) >> 14) & 0x1FFF)
2402#define C_030004_TEX_DEPTH 0xF8003FFF
2403#define S_030004_ARRAY_MODE(x) (((x) & 0xF) << 28)
2404#define G_030004_ARRAY_MODE(x) (((x) >> 28) & 0xF)
2405#define C_030004_ARRAY_MODE 0x0FFFFFFF
2406#define R_030008_SQ_TEX_RESOURCE_WORD2_0 0x030008
2407#define S_030008_BASE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0)
2408#define G_030008_BASE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF)
2409#define C_030008_BASE_ADDRESS 0x00000000
2410#define R_03000C_SQ_TEX_RESOURCE_WORD3_0 0x03000C
2411#define S_03000C_MIP_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0)
2412#define G_03000C_MIP_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF)
2413#define C_03000C_MIP_ADDRESS 0x00000000
2414#define R_030010_SQ_TEX_RESOURCE_WORD4_0 0x030010
2415#define S_030010_FORMAT_COMP_X(x) (((x) & 0x3) << 0)
2416#define G_030010_FORMAT_COMP_X(x) (((x) >> 0) & 0x3)
2417#define C_030010_FORMAT_COMP_X 0xFFFFFFFC
2418#define V_030010_SQ_FORMAT_COMP_UNSIGNED 0x00000000
2419#define V_030010_SQ_FORMAT_COMP_SIGNED 0x00000001
2420#define V_030010_SQ_FORMAT_COMP_UNSIGNED_BIASED 0x00000002
2421#define S_030010_FORMAT_COMP_Y(x) (((x) & 0x3) << 2)
2422#define G_030010_FORMAT_COMP_Y(x) (((x) >> 2) & 0x3)
2423#define C_030010_FORMAT_COMP_Y 0xFFFFFFF3
2424#define S_030010_FORMAT_COMP_Z(x) (((x) & 0x3) << 4)
2425#define G_030010_FORMAT_COMP_Z(x) (((x) >> 4) & 0x3)
2426#define C_030010_FORMAT_COMP_Z 0xFFFFFFCF
2427#define S_030010_FORMAT_COMP_W(x) (((x) & 0x3) << 6)
2428#define G_030010_FORMAT_COMP_W(x) (((x) >> 6) & 0x3)
2429#define C_030010_FORMAT_COMP_W 0xFFFFFF3F
2430#define S_030010_NUM_FORMAT_ALL(x) (((x) & 0x3) << 8)
2431#define G_030010_NUM_FORMAT_ALL(x) (((x) >> 8) & 0x3)
2432#define C_030010_NUM_FORMAT_ALL 0xFFFFFCFF
2433#define V_030010_SQ_NUM_FORMAT_NORM 0x00000000
2434#define V_030010_SQ_NUM_FORMAT_INT 0x00000001
2435#define V_030010_SQ_NUM_FORMAT_SCALED 0x00000002
2436#define S_030010_SRF_MODE_ALL(x) (((x) & 0x1) << 10)
2437#define G_030010_SRF_MODE_ALL(x) (((x) >> 10) & 0x1)
2438#define C_030010_SRF_MODE_ALL 0xFFFFFBFF
2439#define V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE 0x00000000
2440#define V_030010_SRF_MODE_NO_ZERO 0x00000001
2441#define S_030010_FORCE_DEGAMMA(x) (((x) & 0x1) << 11)
2442#define G_030010_FORCE_DEGAMMA(x) (((x) >> 11) & 0x1)
2443#define C_030010_FORCE_DEGAMMA 0xFFFFF7FF
2444#define S_030010_ENDIAN_SWAP(x) (((x) & 0x3) << 12)
2445#define G_030010_ENDIAN_SWAP(x) (((x) >> 12) & 0x3)
2446#define C_030010_ENDIAN_SWAP 0xFFFFCFFF
2447#define S_030010_DST_SEL_X(x) (((x) & 0x7) << 16)
2448#define G_030010_DST_SEL_X(x) (((x) >> 16) & 0x7)
2449#define C_030010_DST_SEL_X 0xFFF8FFFF
2450#define V_030010_SQ_SEL_X 0x00000000
2451#define V_030010_SQ_SEL_Y 0x00000001
2452#define V_030010_SQ_SEL_Z 0x00000002
2453#define V_030010_SQ_SEL_W 0x00000003
2454#define V_030010_SQ_SEL_0 0x00000004
2455#define V_030010_SQ_SEL_1 0x00000005
2456#define S_030010_DST_SEL_Y(x) (((x) & 0x7) << 19)
2457#define G_030010_DST_SEL_Y(x) (((x) >> 19) & 0x7)
2458#define C_030010_DST_SEL_Y 0xFFC7FFFF
2459#define S_030010_DST_SEL_Z(x) (((x) & 0x7) << 22)
2460#define G_030010_DST_SEL_Z(x) (((x) >> 22) & 0x7)
2461#define C_030010_DST_SEL_Z 0xFE3FFFFF
2462#define S_030010_DST_SEL_W(x) (((x) & 0x7) << 25)
2463#define G_030010_DST_SEL_W(x) (((x) >> 25) & 0x7)
2464#define C_030010_DST_SEL_W 0xF1FFFFFF
2465#define S_030010_BASE_LEVEL(x) (((x) & 0xF) << 28)
2466#define G_030010_BASE_LEVEL(x) (((x) >> 28) & 0xF)
2467#define C_030010_BASE_LEVEL 0x0FFFFFFF
2468#define R_030014_SQ_TEX_RESOURCE_WORD5_0 0x030014
2469#define S_030014_LAST_LEVEL(x) (((x) & 0xF) << 0)
2470#define G_030014_LAST_LEVEL(x) (((x) >> 0) & 0xF)
2471#define C_030014_LAST_LEVEL 0xFFFFFFF0
2472#define S_030014_BASE_ARRAY(x) (((x) & 0x1FFF) << 4)
2473#define G_030014_BASE_ARRAY(x) (((x) >> 4) & 0x1FFF)
2474#define C_030014_BASE_ARRAY 0xFFFE000F
2475#define S_030014_LAST_ARRAY(x) (((x) & 0x1FFF) << 17)
2476#define G_030014_LAST_ARRAY(x) (((x) >> 17) & 0x1FFF)
2477#define C_030014_LAST_ARRAY 0xC001FFFF
2478#define R_030018_SQ_TEX_RESOURCE_WORD6_0 0x030018
2479#define S_030018_MAX_ANISO(x) (((x) & 0x7) << 0)
2480#define G_030018_MAX_ANISO(x) (((x) >> 0) & 0x7)
2481#define C_030018_MAX_ANISO 0xFFFFFFF8
2482#define S_030018_PERF_MODULATION(x) (((x) & 0x7) << 3)
2483#define G_030018_PERF_MODULATION(x) (((x) >> 3) & 0x7)
2484#define C_030018_PERF_MODULATION 0xFFFFFFC7
2485#define S_030018_INTERLACED(x) (((x) & 0x1) << 6)
2486#define G_030018_INTERLACED(x) (((x) >> 6) & 0x1)
2487#define C_030018_INTERLACED 0xFFFFFFBF
2488#define S_030018_TILE_SPLIT(x) (((x) & 0x7) << 29)
2489#define G_030018_TILE_SPLIT(x) (((x) >> 29) & 0x7)
2490#define R_03001C_SQ_TEX_RESOURCE_WORD7_0 0x03001C
2491#define S_03001C_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 6)
2492#define G_03001C_MACRO_TILE_ASPECT(x) (((x) >> 6) & 0x3)
2493#define S_03001C_BANK_WIDTH(x) (((x) & 0x3) << 8)
2494#define G_03001C_BANK_WIDTH(x) (((x) >> 8) & 0x3)
2495#define S_03001C_BANK_HEIGHT(x) (((x) & 0x3) << 10)
2496#define G_03001C_BANK_HEIGHT(x) (((x) >> 10) & 0x3)
2497#define S_03001C_NUM_BANKS(x) (((x) & 0x3) << 16)
2498#define G_03001C_NUM_BANKS(x) (((x) >> 16) & 0x3)
2499#define S_03001C_TYPE(x) (((x) & 0x3) << 30)
2500#define G_03001C_TYPE(x) (((x) >> 30) & 0x3)
2501#define C_03001C_TYPE 0x3FFFFFFF
2502#define V_03001C_SQ_TEX_VTX_INVALID_TEXTURE 0x00000000
2503#define V_03001C_SQ_TEX_VTX_INVALID_BUFFER 0x00000001
2504#define V_03001C_SQ_TEX_VTX_VALID_TEXTURE 0x00000002
2505#define V_03001C_SQ_TEX_VTX_VALID_BUFFER 0x00000003
2506#define S_03001C_DATA_FORMAT(x) (((x) & 0x3F) << 0)
2507#define G_03001C_DATA_FORMAT(x) (((x) >> 0) & 0x3F)
2508#define C_03001C_DATA_FORMAT 0xFFFFFFC0
2509
2510#define SQ_VTX_CONSTANT_WORD0_0 0x30000
2511#define SQ_VTX_CONSTANT_WORD1_0 0x30004
2512#define SQ_VTX_CONSTANT_WORD2_0 0x30008
2513# define SQ_VTXC_BASE_ADDR_HI(x) ((x) << 0)
2514# define SQ_VTXC_STRIDE(x) ((x) << 8)
2515# define SQ_VTXC_ENDIAN_SWAP(x) ((x) << 30)
2516# define SQ_ENDIAN_NONE 0
2517# define SQ_ENDIAN_8IN16 1
2518# define SQ_ENDIAN_8IN32 2
2519#define SQ_VTX_CONSTANT_WORD3_0 0x3000C
2520# define SQ_VTCX_SEL_X(x) ((x) << 3)
2521# define SQ_VTCX_SEL_Y(x) ((x) << 6)
2522# define SQ_VTCX_SEL_Z(x) ((x) << 9)
2523# define SQ_VTCX_SEL_W(x) ((x) << 12)
2524#define SQ_VTX_CONSTANT_WORD4_0 0x30010
2525#define SQ_VTX_CONSTANT_WORD5_0 0x30014
2526#define SQ_VTX_CONSTANT_WORD6_0 0x30018
2527#define SQ_VTX_CONSTANT_WORD7_0 0x3001c
2528
2529#define TD_PS_BORDER_COLOR_INDEX 0xA400
2530#define TD_PS_BORDER_COLOR_RED 0xA404
2531#define TD_PS_BORDER_COLOR_GREEN 0xA408
2532#define TD_PS_BORDER_COLOR_BLUE 0xA40C
2533#define TD_PS_BORDER_COLOR_ALPHA 0xA410
2534#define TD_VS_BORDER_COLOR_INDEX 0xA414
2535#define TD_VS_BORDER_COLOR_RED 0xA418
2536#define TD_VS_BORDER_COLOR_GREEN 0xA41C
2537#define TD_VS_BORDER_COLOR_BLUE 0xA420
2538#define TD_VS_BORDER_COLOR_ALPHA 0xA424
2539#define TD_GS_BORDER_COLOR_INDEX 0xA428
2540#define TD_GS_BORDER_COLOR_RED 0xA42C
2541#define TD_GS_BORDER_COLOR_GREEN 0xA430
2542#define TD_GS_BORDER_COLOR_BLUE 0xA434
2543#define TD_GS_BORDER_COLOR_ALPHA 0xA438
2544#define TD_HS_BORDER_COLOR_INDEX 0xA43C
2545#define TD_HS_BORDER_COLOR_RED 0xA440
2546#define TD_HS_BORDER_COLOR_GREEN 0xA444
2547#define TD_HS_BORDER_COLOR_BLUE 0xA448
2548#define TD_HS_BORDER_COLOR_ALPHA 0xA44C
2549#define TD_LS_BORDER_COLOR_INDEX 0xA450
2550#define TD_LS_BORDER_COLOR_RED 0xA454
2551#define TD_LS_BORDER_COLOR_GREEN 0xA458
2552#define TD_LS_BORDER_COLOR_BLUE 0xA45C
2553#define TD_LS_BORDER_COLOR_ALPHA 0xA460
2554#define TD_CS_BORDER_COLOR_INDEX 0xA464
2555#define TD_CS_BORDER_COLOR_RED 0xA468
2556#define TD_CS_BORDER_COLOR_GREEN 0xA46C
2557#define TD_CS_BORDER_COLOR_BLUE 0xA470
2558#define TD_CS_BORDER_COLOR_ALPHA 0xA474
2559
2560/* cayman 3D regs */
2561#define CAYMAN_VGT_OFFCHIP_LDS_BASE 0x89B4
2562#define CAYMAN_SQ_EX_ALLOC_TABLE_SLOTS 0x8E48
2563#define CAYMAN_DB_EQAA 0x28804
2564#define CAYMAN_DB_DEPTH_INFO 0x2803C
2565#define CAYMAN_PA_SC_AA_CONFIG 0x28BE0
2566#define CAYMAN_MSAA_NUM_SAMPLES_SHIFT 0
2567#define CAYMAN_MSAA_NUM_SAMPLES_MASK 0x7
2568#define CAYMAN_SX_SCATTER_EXPORT_BASE 0x28358
2569/* cayman packet3 addition */
2570#define CAYMAN_PACKET3_DEALLOC_STATE 0x14
2571
2572/* DMA regs common on r6xx/r7xx/evergreen/ni */
2573#define DMA_RB_CNTL 0xd000
2574# define DMA_RB_ENABLE (1 << 0)
2575# define DMA_RB_SIZE(x) ((x) << 1) /* log2 */
2576# define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */
2577# define DMA_RPTR_WRITEBACK_ENABLE (1 << 12)
2578# define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */
2579# define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */
2580#define DMA_STATUS_REG 0xd034
2581# define DMA_IDLE (1 << 0)
2582
2583#endif
1/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#ifndef EVERGREEND_H
25#define EVERGREEND_H
26
27#define EVERGREEN_MAX_SH_GPRS 256
28#define EVERGREEN_MAX_TEMP_GPRS 16
29#define EVERGREEN_MAX_SH_THREADS 256
30#define EVERGREEN_MAX_SH_STACK_ENTRIES 4096
31#define EVERGREEN_MAX_FRC_EOV_CNT 16384
32#define EVERGREEN_MAX_BACKENDS 8
33#define EVERGREEN_MAX_BACKENDS_MASK 0xFF
34#define EVERGREEN_MAX_SIMDS 16
35#define EVERGREEN_MAX_SIMDS_MASK 0xFFFF
36#define EVERGREEN_MAX_PIPES 8
37#define EVERGREEN_MAX_PIPES_MASK 0xFF
38#define EVERGREEN_MAX_LDS_NUM 0xFFFF
39
40#define CYPRESS_GB_ADDR_CONFIG_GOLDEN 0x02011003
41#define BARTS_GB_ADDR_CONFIG_GOLDEN 0x02011003
42#define CAYMAN_GB_ADDR_CONFIG_GOLDEN 0x02011003
43#define JUNIPER_GB_ADDR_CONFIG_GOLDEN 0x02010002
44#define REDWOOD_GB_ADDR_CONFIG_GOLDEN 0x02010002
45#define TURKS_GB_ADDR_CONFIG_GOLDEN 0x02010002
46#define CEDAR_GB_ADDR_CONFIG_GOLDEN 0x02010001
47#define CAICOS_GB_ADDR_CONFIG_GOLDEN 0x02010001
48#define SUMO_GB_ADDR_CONFIG_GOLDEN 0x02010002
49#define SUMO2_GB_ADDR_CONFIG_GOLDEN 0x02010002
50
51/* pm registers */
52#define SMC_MSG 0x20c
53#define HOST_SMC_MSG(x) ((x) << 0)
54#define HOST_SMC_MSG_MASK (0xff << 0)
55#define HOST_SMC_MSG_SHIFT 0
56#define HOST_SMC_RESP(x) ((x) << 8)
57#define HOST_SMC_RESP_MASK (0xff << 8)
58#define HOST_SMC_RESP_SHIFT 8
59#define SMC_HOST_MSG(x) ((x) << 16)
60#define SMC_HOST_MSG_MASK (0xff << 16)
61#define SMC_HOST_MSG_SHIFT 16
62#define SMC_HOST_RESP(x) ((x) << 24)
63#define SMC_HOST_RESP_MASK (0xff << 24)
64#define SMC_HOST_RESP_SHIFT 24
65
66#define DCCG_DISP_SLOW_SELECT_REG 0x4fc
67#define DCCG_DISP1_SLOW_SELECT(x) ((x) << 0)
68#define DCCG_DISP1_SLOW_SELECT_MASK (7 << 0)
69#define DCCG_DISP1_SLOW_SELECT_SHIFT 0
70#define DCCG_DISP2_SLOW_SELECT(x) ((x) << 4)
71#define DCCG_DISP2_SLOW_SELECT_MASK (7 << 4)
72#define DCCG_DISP2_SLOW_SELECT_SHIFT 4
73
74#define CG_SPLL_FUNC_CNTL 0x600
75#define SPLL_RESET (1 << 0)
76#define SPLL_SLEEP (1 << 1)
77#define SPLL_BYPASS_EN (1 << 3)
78#define SPLL_REF_DIV(x) ((x) << 4)
79#define SPLL_REF_DIV_MASK (0x3f << 4)
80#define SPLL_PDIV_A(x) ((x) << 20)
81#define SPLL_PDIV_A_MASK (0x7f << 20)
82#define CG_SPLL_FUNC_CNTL_2 0x604
83#define SCLK_MUX_SEL(x) ((x) << 0)
84#define SCLK_MUX_SEL_MASK (0x1ff << 0)
85#define SCLK_MUX_UPDATE (1 << 26)
86#define CG_SPLL_FUNC_CNTL_3 0x608
87#define SPLL_FB_DIV(x) ((x) << 0)
88#define SPLL_FB_DIV_MASK (0x3ffffff << 0)
89#define SPLL_DITHEN (1 << 28)
90#define CG_SPLL_STATUS 0x60c
91#define SPLL_CHG_STATUS (1 << 1)
92
93#define MPLL_CNTL_MODE 0x61c
94# define MPLL_MCLK_SEL (1 << 11)
95# define SS_SSEN (1 << 24)
96# define SS_DSMODE_EN (1 << 25)
97
98#define MPLL_AD_FUNC_CNTL 0x624
99#define CLKF(x) ((x) << 0)
100#define CLKF_MASK (0x7f << 0)
101#define CLKR(x) ((x) << 7)
102#define CLKR_MASK (0x1f << 7)
103#define CLKFRAC(x) ((x) << 12)
104#define CLKFRAC_MASK (0x1f << 12)
105#define YCLK_POST_DIV(x) ((x) << 17)
106#define YCLK_POST_DIV_MASK (3 << 17)
107#define IBIAS(x) ((x) << 20)
108#define IBIAS_MASK (0x3ff << 20)
109#define RESET (1 << 30)
110#define PDNB (1 << 31)
111#define MPLL_AD_FUNC_CNTL_2 0x628
112#define BYPASS (1 << 19)
113#define BIAS_GEN_PDNB (1 << 24)
114#define RESET_EN (1 << 25)
115#define VCO_MODE (1 << 29)
116#define MPLL_DQ_FUNC_CNTL 0x62c
117#define MPLL_DQ_FUNC_CNTL_2 0x630
118
119#define GENERAL_PWRMGT 0x63c
120# define GLOBAL_PWRMGT_EN (1 << 0)
121# define STATIC_PM_EN (1 << 1)
122# define THERMAL_PROTECTION_DIS (1 << 2)
123# define THERMAL_PROTECTION_TYPE (1 << 3)
124# define ENABLE_GEN2PCIE (1 << 4)
125# define ENABLE_GEN2XSP (1 << 5)
126# define SW_SMIO_INDEX(x) ((x) << 6)
127# define SW_SMIO_INDEX_MASK (3 << 6)
128# define SW_SMIO_INDEX_SHIFT 6
129# define LOW_VOLT_D2_ACPI (1 << 8)
130# define LOW_VOLT_D3_ACPI (1 << 9)
131# define VOLT_PWRMGT_EN (1 << 10)
132# define BACKBIAS_PAD_EN (1 << 18)
133# define BACKBIAS_VALUE (1 << 19)
134# define DYN_SPREAD_SPECTRUM_EN (1 << 23)
135# define AC_DC_SW (1 << 24)
136
137#define SCLK_PWRMGT_CNTL 0x644
138# define SCLK_PWRMGT_OFF (1 << 0)
139# define SCLK_LOW_D1 (1 << 1)
140# define FIR_RESET (1 << 4)
141# define FIR_FORCE_TREND_SEL (1 << 5)
142# define FIR_TREND_MODE (1 << 6)
143# define DYN_GFX_CLK_OFF_EN (1 << 7)
144# define GFX_CLK_FORCE_ON (1 << 8)
145# define GFX_CLK_REQUEST_OFF (1 << 9)
146# define GFX_CLK_FORCE_OFF (1 << 10)
147# define GFX_CLK_OFF_ACPI_D1 (1 << 11)
148# define GFX_CLK_OFF_ACPI_D2 (1 << 12)
149# define GFX_CLK_OFF_ACPI_D3 (1 << 13)
150# define DYN_LIGHT_SLEEP_EN (1 << 14)
151#define MCLK_PWRMGT_CNTL 0x648
152# define DLL_SPEED(x) ((x) << 0)
153# define DLL_SPEED_MASK (0x1f << 0)
154# define MPLL_PWRMGT_OFF (1 << 5)
155# define DLL_READY (1 << 6)
156# define MC_INT_CNTL (1 << 7)
157# define MRDCKA0_PDNB (1 << 8)
158# define MRDCKA1_PDNB (1 << 9)
159# define MRDCKB0_PDNB (1 << 10)
160# define MRDCKB1_PDNB (1 << 11)
161# define MRDCKC0_PDNB (1 << 12)
162# define MRDCKC1_PDNB (1 << 13)
163# define MRDCKD0_PDNB (1 << 14)
164# define MRDCKD1_PDNB (1 << 15)
165# define MRDCKA0_RESET (1 << 16)
166# define MRDCKA1_RESET (1 << 17)
167# define MRDCKB0_RESET (1 << 18)
168# define MRDCKB1_RESET (1 << 19)
169# define MRDCKC0_RESET (1 << 20)
170# define MRDCKC1_RESET (1 << 21)
171# define MRDCKD0_RESET (1 << 22)
172# define MRDCKD1_RESET (1 << 23)
173# define DLL_READY_READ (1 << 24)
174# define USE_DISPLAY_GAP (1 << 25)
175# define USE_DISPLAY_URGENT_NORMAL (1 << 26)
176# define MPLL_TURNOFF_D2 (1 << 28)
177#define DLL_CNTL 0x64c
178# define MRDCKA0_BYPASS (1 << 24)
179# define MRDCKA1_BYPASS (1 << 25)
180# define MRDCKB0_BYPASS (1 << 26)
181# define MRDCKB1_BYPASS (1 << 27)
182# define MRDCKC0_BYPASS (1 << 28)
183# define MRDCKC1_BYPASS (1 << 29)
184# define MRDCKD0_BYPASS (1 << 30)
185# define MRDCKD1_BYPASS (1 << 31)
186
187#define CG_AT 0x6d4
188# define CG_R(x) ((x) << 0)
189# define CG_R_MASK (0xffff << 0)
190# define CG_L(x) ((x) << 16)
191# define CG_L_MASK (0xffff << 16)
192
193#define CG_DISPLAY_GAP_CNTL 0x714
194# define DISP1_GAP(x) ((x) << 0)
195# define DISP1_GAP_MASK (3 << 0)
196# define DISP2_GAP(x) ((x) << 2)
197# define DISP2_GAP_MASK (3 << 2)
198# define VBI_TIMER_COUNT(x) ((x) << 4)
199# define VBI_TIMER_COUNT_MASK (0x3fff << 4)
200# define VBI_TIMER_UNIT(x) ((x) << 20)
201# define VBI_TIMER_UNIT_MASK (7 << 20)
202# define DISP1_GAP_MCHG(x) ((x) << 24)
203# define DISP1_GAP_MCHG_MASK (3 << 24)
204# define DISP2_GAP_MCHG(x) ((x) << 26)
205# define DISP2_GAP_MCHG_MASK (3 << 26)
206
207#define CG_BIF_REQ_AND_RSP 0x7f4
208#define CG_CLIENT_REQ(x) ((x) << 0)
209#define CG_CLIENT_REQ_MASK (0xff << 0)
210#define CG_CLIENT_REQ_SHIFT 0
211#define CG_CLIENT_RESP(x) ((x) << 8)
212#define CG_CLIENT_RESP_MASK (0xff << 8)
213#define CG_CLIENT_RESP_SHIFT 8
214#define CLIENT_CG_REQ(x) ((x) << 16)
215#define CLIENT_CG_REQ_MASK (0xff << 16)
216#define CLIENT_CG_REQ_SHIFT 16
217#define CLIENT_CG_RESP(x) ((x) << 24)
218#define CLIENT_CG_RESP_MASK (0xff << 24)
219#define CLIENT_CG_RESP_SHIFT 24
220
221#define CG_SPLL_SPREAD_SPECTRUM 0x790
222#define SSEN (1 << 0)
223#define CG_SPLL_SPREAD_SPECTRUM_2 0x794
224
225#define MPLL_SS1 0x85c
226#define CLKV(x) ((x) << 0)
227#define CLKV_MASK (0x3ffffff << 0)
228#define MPLL_SS2 0x860
229#define CLKS(x) ((x) << 0)
230#define CLKS_MASK (0xfff << 0)
231
232#define CG_IND_ADDR 0x8f8
233#define CG_IND_DATA 0x8fc
234/* CGIND regs */
235#define CG_CGTT_LOCAL_0 0x00
236#define CG_CGTT_LOCAL_1 0x01
237#define CG_CGTT_LOCAL_2 0x02
238#define CG_CGTT_LOCAL_3 0x03
239#define CG_CGLS_TILE_0 0x20
240#define CG_CGLS_TILE_1 0x21
241#define CG_CGLS_TILE_2 0x22
242#define CG_CGLS_TILE_3 0x23
243#define CG_CGLS_TILE_4 0x24
244#define CG_CGLS_TILE_5 0x25
245#define CG_CGLS_TILE_6 0x26
246#define CG_CGLS_TILE_7 0x27
247#define CG_CGLS_TILE_8 0x28
248#define CG_CGLS_TILE_9 0x29
249#define CG_CGLS_TILE_10 0x2a
250#define CG_CGLS_TILE_11 0x2b
251
252#define VM_L2_CG 0x15c0
253
254#define MC_CONFIG 0x2000
255
256#define MC_CONFIG_MCD 0x20a0
257#define MC_CG_CONFIG_MCD 0x20a4
258#define MC_RD_ENABLE_MCD(x) ((x) << 8)
259#define MC_RD_ENABLE_MCD_MASK (7 << 8)
260
261#define MC_HUB_MISC_HUB_CG 0x20b8
262#define MC_HUB_MISC_VM_CG 0x20bc
263#define MC_HUB_MISC_SIP_CG 0x20c0
264
265#define MC_XPB_CLK_GAT 0x2478
266
267#define MC_CG_CONFIG 0x25bc
268#define MC_RD_ENABLE(x) ((x) << 4)
269#define MC_RD_ENABLE_MASK (3 << 4)
270
271#define MC_CITF_MISC_RD_CG 0x2648
272#define MC_CITF_MISC_WR_CG 0x264c
273#define MC_CITF_MISC_VM_CG 0x2650
274# define MEM_LS_ENABLE (1 << 19)
275
276#define MC_ARB_BURST_TIME 0x2808
277#define STATE0(x) ((x) << 0)
278#define STATE0_MASK (0x1f << 0)
279#define STATE1(x) ((x) << 5)
280#define STATE1_MASK (0x1f << 5)
281#define STATE2(x) ((x) << 10)
282#define STATE2_MASK (0x1f << 10)
283#define STATE3(x) ((x) << 15)
284#define STATE3_MASK (0x1f << 15)
285
286#define MC_SEQ_RAS_TIMING 0x28a0
287#define MC_SEQ_CAS_TIMING 0x28a4
288#define MC_SEQ_MISC_TIMING 0x28a8
289#define MC_SEQ_MISC_TIMING2 0x28ac
290
291#define MC_SEQ_RD_CTL_D0 0x28b4
292#define MC_SEQ_RD_CTL_D1 0x28b8
293#define MC_SEQ_WR_CTL_D0 0x28bc
294#define MC_SEQ_WR_CTL_D1 0x28c0
295
296#define MC_SEQ_STATUS_M 0x29f4
297# define PMG_PWRSTATE (1 << 16)
298
299#define MC_SEQ_MISC1 0x2a04
300#define MC_SEQ_RESERVE_M 0x2a08
301#define MC_PMG_CMD_EMRS 0x2a0c
302
303#define MC_SEQ_MISC3 0x2a2c
304
305#define MC_SEQ_MISC5 0x2a54
306#define MC_SEQ_MISC6 0x2a58
307
308#define MC_SEQ_MISC7 0x2a64
309
310#define MC_SEQ_CG 0x2a68
311#define CG_SEQ_REQ(x) ((x) << 0)
312#define CG_SEQ_REQ_MASK (0xff << 0)
313#define CG_SEQ_REQ_SHIFT 0
314#define CG_SEQ_RESP(x) ((x) << 8)
315#define CG_SEQ_RESP_MASK (0xff << 8)
316#define CG_SEQ_RESP_SHIFT 8
317#define SEQ_CG_REQ(x) ((x) << 16)
318#define SEQ_CG_REQ_MASK (0xff << 16)
319#define SEQ_CG_REQ_SHIFT 16
320#define SEQ_CG_RESP(x) ((x) << 24)
321#define SEQ_CG_RESP_MASK (0xff << 24)
322#define SEQ_CG_RESP_SHIFT 24
323#define MC_SEQ_RAS_TIMING_LP 0x2a6c
324#define MC_SEQ_CAS_TIMING_LP 0x2a70
325#define MC_SEQ_MISC_TIMING_LP 0x2a74
326#define MC_SEQ_MISC_TIMING2_LP 0x2a78
327#define MC_SEQ_WR_CTL_D0_LP 0x2a7c
328#define MC_SEQ_WR_CTL_D1_LP 0x2a80
329#define MC_SEQ_PMG_CMD_EMRS_LP 0x2a84
330#define MC_SEQ_PMG_CMD_MRS_LP 0x2a88
331
332#define MC_PMG_CMD_MRS 0x2aac
333
334#define MC_SEQ_RD_CTL_D0_LP 0x2b1c
335#define MC_SEQ_RD_CTL_D1_LP 0x2b20
336
337#define MC_PMG_CMD_MRS1 0x2b44
338#define MC_SEQ_PMG_CMD_MRS1_LP 0x2b48
339
340#define CGTS_SM_CTRL_REG 0x9150
341
342/* Registers */
343
344#define RCU_IND_INDEX 0x100
345#define RCU_IND_DATA 0x104
346
347/* discrete uvd clocks */
348#define CG_UPLL_FUNC_CNTL 0x718
349# define UPLL_RESET_MASK 0x00000001
350# define UPLL_SLEEP_MASK 0x00000002
351# define UPLL_BYPASS_EN_MASK 0x00000004
352# define UPLL_CTLREQ_MASK 0x00000008
353# define UPLL_REF_DIV_MASK 0x003F0000
354# define UPLL_VCO_MODE_MASK 0x00000200
355# define UPLL_CTLACK_MASK 0x40000000
356# define UPLL_CTLACK2_MASK 0x80000000
357#define CG_UPLL_FUNC_CNTL_2 0x71c
358# define UPLL_PDIV_A(x) ((x) << 0)
359# define UPLL_PDIV_A_MASK 0x0000007F
360# define UPLL_PDIV_B(x) ((x) << 8)
361# define UPLL_PDIV_B_MASK 0x00007F00
362# define VCLK_SRC_SEL(x) ((x) << 20)
363# define VCLK_SRC_SEL_MASK 0x01F00000
364# define DCLK_SRC_SEL(x) ((x) << 25)
365# define DCLK_SRC_SEL_MASK 0x3E000000
366#define CG_UPLL_FUNC_CNTL_3 0x720
367# define UPLL_FB_DIV(x) ((x) << 0)
368# define UPLL_FB_DIV_MASK 0x01FFFFFF
369#define CG_UPLL_FUNC_CNTL_4 0x854
370# define UPLL_SPARE_ISPARE9 0x00020000
371#define CG_UPLL_SPREAD_SPECTRUM 0x79c
372# define SSEN_MASK 0x00000001
373
374/* fusion uvd clocks */
375#define CG_DCLK_CNTL 0x610
376# define DCLK_DIVIDER_MASK 0x7f
377# define DCLK_DIR_CNTL_EN (1 << 8)
378#define CG_DCLK_STATUS 0x614
379# define DCLK_STATUS (1 << 0)
380#define CG_VCLK_CNTL 0x618
381#define CG_VCLK_STATUS 0x61c
382#define CG_SCRATCH1 0x820
383
384#define RLC_CNTL 0x3f00
385# define RLC_ENABLE (1 << 0)
386# define GFX_POWER_GATING_ENABLE (1 << 7)
387# define GFX_POWER_GATING_SRC (1 << 8)
388# define DYN_PER_SIMD_PG_ENABLE (1 << 27)
389# define LB_CNT_SPIM_ACTIVE (1 << 30)
390# define LOAD_BALANCE_ENABLE (1 << 31)
391
392#define RLC_HB_BASE 0x3f10
393#define RLC_HB_CNTL 0x3f0c
394#define RLC_HB_RPTR 0x3f20
395#define RLC_HB_WPTR 0x3f1c
396#define RLC_HB_WPTR_LSB_ADDR 0x3f14
397#define RLC_HB_WPTR_MSB_ADDR 0x3f18
398#define RLC_MC_CNTL 0x3f44
399#define RLC_UCODE_CNTL 0x3f48
400#define RLC_UCODE_ADDR 0x3f2c
401#define RLC_UCODE_DATA 0x3f30
402
403/* new for TN */
404#define TN_RLC_SAVE_AND_RESTORE_BASE 0x3f10
405#define TN_RLC_LB_CNTR_MAX 0x3f14
406#define TN_RLC_LB_CNTR_INIT 0x3f18
407#define TN_RLC_CLEAR_STATE_RESTORE_BASE 0x3f20
408#define TN_RLC_LB_INIT_SIMD_MASK 0x3fe4
409#define TN_RLC_LB_ALWAYS_ACTIVE_SIMD_MASK 0x3fe8
410#define TN_RLC_LB_PARAMS 0x3fec
411
412#define GRBM_GFX_INDEX 0x802C
413#define INSTANCE_INDEX(x) ((x) << 0)
414#define SE_INDEX(x) ((x) << 16)
415#define INSTANCE_BROADCAST_WRITES (1 << 30)
416#define SE_BROADCAST_WRITES (1 << 31)
417#define RLC_GFX_INDEX 0x3fC4
418#define CC_GC_SHADER_PIPE_CONFIG 0x8950
419#define WRITE_DIS (1 << 0)
420#define CC_RB_BACKEND_DISABLE 0x98F4
421#define BACKEND_DISABLE(x) ((x) << 16)
422#define GB_ADDR_CONFIG 0x98F8
423#define NUM_PIPES(x) ((x) << 0)
424#define NUM_PIPES_MASK 0x0000000f
425#define PIPE_INTERLEAVE_SIZE(x) ((x) << 4)
426#define BANK_INTERLEAVE_SIZE(x) ((x) << 8)
427#define NUM_SHADER_ENGINES(x) ((x) << 12)
428#define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16)
429#define NUM_GPUS(x) ((x) << 20)
430#define MULTI_GPU_TILE_SIZE(x) ((x) << 24)
431#define ROW_SIZE(x) ((x) << 28)
432#define GB_BACKEND_MAP 0x98FC
433#define DMIF_ADDR_CONFIG 0xBD4
434#define HDP_ADDR_CONFIG 0x2F48
435#define HDP_MISC_CNTL 0x2F4C
436#define HDP_FLUSH_INVALIDATE_CACHE (1 << 0)
437
438#define CC_SYS_RB_BACKEND_DISABLE 0x3F88
439#define GC_USER_RB_BACKEND_DISABLE 0x9B7C
440
441#define CGTS_SYS_TCC_DISABLE 0x3F90
442#define CGTS_TCC_DISABLE 0x9148
443#define CGTS_USER_SYS_TCC_DISABLE 0x3F94
444#define CGTS_USER_TCC_DISABLE 0x914C
445
446#define CONFIG_MEMSIZE 0x5428
447
448#define BIF_FB_EN 0x5490
449#define FB_READ_EN (1 << 0)
450#define FB_WRITE_EN (1 << 1)
451
452#define CP_STRMOUT_CNTL 0x84FC
453
454#define CP_COHER_CNTL 0x85F0
455#define CP_COHER_SIZE 0x85F4
456#define CP_COHER_BASE 0x85F8
457#define CP_STALLED_STAT1 0x8674
458#define CP_STALLED_STAT2 0x8678
459#define CP_BUSY_STAT 0x867C
460#define CP_STAT 0x8680
461#define CP_ME_CNTL 0x86D8
462#define CP_ME_HALT (1 << 28)
463#define CP_PFP_HALT (1 << 26)
464#define CP_ME_RAM_DATA 0xC160
465#define CP_ME_RAM_RADDR 0xC158
466#define CP_ME_RAM_WADDR 0xC15C
467#define CP_MEQ_THRESHOLDS 0x8764
468#define STQ_SPLIT(x) ((x) << 0)
469#define CP_PERFMON_CNTL 0x87FC
470#define CP_PFP_UCODE_ADDR 0xC150
471#define CP_PFP_UCODE_DATA 0xC154
472#define CP_QUEUE_THRESHOLDS 0x8760
473#define ROQ_IB1_START(x) ((x) << 0)
474#define ROQ_IB2_START(x) ((x) << 8)
475#define CP_RB_BASE 0xC100
476#define CP_RB_CNTL 0xC104
477#define RB_BUFSZ(x) ((x) << 0)
478#define RB_BLKSZ(x) ((x) << 8)
479#define RB_NO_UPDATE (1 << 27)
480#define RB_RPTR_WR_ENA (1 << 31)
481#define BUF_SWAP_32BIT (2 << 16)
482#define CP_RB_RPTR 0x8700
483#define CP_RB_RPTR_ADDR 0xC10C
484#define RB_RPTR_SWAP(x) ((x) << 0)
485#define CP_RB_RPTR_ADDR_HI 0xC110
486#define CP_RB_RPTR_WR 0xC108
487#define CP_RB_WPTR 0xC114
488#define CP_RB_WPTR_ADDR 0xC118
489#define CP_RB_WPTR_ADDR_HI 0xC11C
490#define CP_RB_WPTR_DELAY 0x8704
491#define CP_SEM_WAIT_TIMER 0x85BC
492#define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8
493#define CP_DEBUG 0xC1FC
494
495/* Audio clocks */
496#define DCCG_AUDIO_DTO_SOURCE 0x05ac
497# define DCCG_AUDIO_DTO0_SOURCE_SEL(x) ((x) << 0) /* crtc0 - crtc5 */
498# define DCCG_AUDIO_DTO_SEL (1 << 4) /* 0=dto0 1=dto1 */
499
500#define DCCG_AUDIO_DTO0_PHASE 0x05b0
501#define DCCG_AUDIO_DTO0_MODULE 0x05b4
502#define DCCG_AUDIO_DTO0_LOAD 0x05b8
503#define DCCG_AUDIO_DTO0_CNTL 0x05bc
504# define DCCG_AUDIO_DTO_WALLCLOCK_RATIO(x) (((x) & 7) << 0)
505# define DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK 7
506# define DCCG_AUDIO_DTO_WALLCLOCK_RATIO_SHIFT 0
507
508#define DCCG_AUDIO_DTO1_PHASE 0x05c0
509#define DCCG_AUDIO_DTO1_MODULE 0x05c4
510#define DCCG_AUDIO_DTO1_LOAD 0x05c8
511#define DCCG_AUDIO_DTO1_CNTL 0x05cc
512
513/* DCE 4.0 AFMT */
514#define HDMI_CONTROL 0x7030
515# define HDMI_KEEPOUT_MODE (1 << 0)
516# define HDMI_PACKET_GEN_VERSION (1 << 4) /* 0 = r6xx compat */
517# define HDMI_ERROR_ACK (1 << 8)
518# define HDMI_ERROR_MASK (1 << 9)
519# define HDMI_DEEP_COLOR_ENABLE (1 << 24)
520# define HDMI_DEEP_COLOR_DEPTH (((x) & 3) << 28)
521# define HDMI_24BIT_DEEP_COLOR 0
522# define HDMI_30BIT_DEEP_COLOR 1
523# define HDMI_36BIT_DEEP_COLOR 2
524#define HDMI_STATUS 0x7034
525# define HDMI_ACTIVE_AVMUTE (1 << 0)
526# define HDMI_AUDIO_PACKET_ERROR (1 << 16)
527# define HDMI_VBI_PACKET_ERROR (1 << 20)
528#define HDMI_AUDIO_PACKET_CONTROL 0x7038
529# define HDMI_AUDIO_DELAY_EN(x) (((x) & 3) << 4)
530# define HDMI_AUDIO_PACKETS_PER_LINE(x) (((x) & 0x1f) << 16)
531#define HDMI_ACR_PACKET_CONTROL 0x703c
532# define HDMI_ACR_SEND (1 << 0)
533# define HDMI_ACR_CONT (1 << 1)
534# define HDMI_ACR_SELECT(x) (((x) & 3) << 4)
535# define HDMI_ACR_HW 0
536# define HDMI_ACR_32 1
537# define HDMI_ACR_44 2
538# define HDMI_ACR_48 3
539# define HDMI_ACR_SOURCE (1 << 8) /* 0 - hw; 1 - cts value */
540# define HDMI_ACR_AUTO_SEND (1 << 12)
541# define HDMI_ACR_N_MULTIPLE(x) (((x) & 7) << 16)
542# define HDMI_ACR_X1 1
543# define HDMI_ACR_X2 2
544# define HDMI_ACR_X4 4
545# define HDMI_ACR_AUDIO_PRIORITY (1 << 31)
546#define HDMI_VBI_PACKET_CONTROL 0x7040
547# define HDMI_NULL_SEND (1 << 0)
548# define HDMI_GC_SEND (1 << 4)
549# define HDMI_GC_CONT (1 << 5) /* 0 - once; 1 - every frame */
550#define HDMI_INFOFRAME_CONTROL0 0x7044
551# define HDMI_AVI_INFO_SEND (1 << 0)
552# define HDMI_AVI_INFO_CONT (1 << 1)
553# define HDMI_AUDIO_INFO_SEND (1 << 4)
554# define HDMI_AUDIO_INFO_CONT (1 << 5)
555# define HDMI_MPEG_INFO_SEND (1 << 8)
556# define HDMI_MPEG_INFO_CONT (1 << 9)
557#define HDMI_INFOFRAME_CONTROL1 0x7048
558# define HDMI_AVI_INFO_LINE(x) (((x) & 0x3f) << 0)
559# define HDMI_AVI_INFO_LINE_MASK (0x3f << 0)
560# define HDMI_AUDIO_INFO_LINE(x) (((x) & 0x3f) << 8)
561# define HDMI_MPEG_INFO_LINE(x) (((x) & 0x3f) << 16)
562#define HDMI_GENERIC_PACKET_CONTROL 0x704c
563# define HDMI_GENERIC0_SEND (1 << 0)
564# define HDMI_GENERIC0_CONT (1 << 1)
565# define HDMI_GENERIC1_SEND (1 << 4)
566# define HDMI_GENERIC1_CONT (1 << 5)
567# define HDMI_GENERIC0_LINE(x) (((x) & 0x3f) << 16)
568# define HDMI_GENERIC1_LINE(x) (((x) & 0x3f) << 24)
569#define HDMI_GC 0x7058
570# define HDMI_GC_AVMUTE (1 << 0)
571# define HDMI_GC_AVMUTE_CONT (1 << 2)
572#define AFMT_AUDIO_PACKET_CONTROL2 0x705c
573# define AFMT_AUDIO_LAYOUT_OVRD (1 << 0)
574# define AFMT_AUDIO_LAYOUT_SELECT (1 << 1)
575# define AFMT_60958_CS_SOURCE (1 << 4)
576# define AFMT_AUDIO_CHANNEL_ENABLE(x) (((x) & 0xff) << 8)
577# define AFMT_DP_AUDIO_STREAM_ID(x) (((x) & 0xff) << 16)
578#define AFMT_AVI_INFO0 0x7084
579# define AFMT_AVI_INFO_CHECKSUM(x) (((x) & 0xff) << 0)
580# define AFMT_AVI_INFO_S(x) (((x) & 3) << 8)
581# define AFMT_AVI_INFO_B(x) (((x) & 3) << 10)
582# define AFMT_AVI_INFO_A(x) (((x) & 1) << 12)
583# define AFMT_AVI_INFO_Y(x) (((x) & 3) << 13)
584# define AFMT_AVI_INFO_Y_RGB 0
585# define AFMT_AVI_INFO_Y_YCBCR422 1
586# define AFMT_AVI_INFO_Y_YCBCR444 2
587# define AFMT_AVI_INFO_Y_A_B_S(x) (((x) & 0xff) << 8)
588# define AFMT_AVI_INFO_R(x) (((x) & 0xf) << 16)
589# define AFMT_AVI_INFO_M(x) (((x) & 0x3) << 20)
590# define AFMT_AVI_INFO_C(x) (((x) & 0x3) << 22)
591# define AFMT_AVI_INFO_C_M_R(x) (((x) & 0xff) << 16)
592# define AFMT_AVI_INFO_SC(x) (((x) & 0x3) << 24)
593# define AFMT_AVI_INFO_Q(x) (((x) & 0x3) << 26)
594# define AFMT_AVI_INFO_EC(x) (((x) & 0x3) << 28)
595# define AFMT_AVI_INFO_ITC(x) (((x) & 0x1) << 31)
596# define AFMT_AVI_INFO_ITC_EC_Q_SC(x) (((x) & 0xff) << 24)
597#define AFMT_AVI_INFO1 0x7088
598# define AFMT_AVI_INFO_VIC(x) (((x) & 0x7f) << 0) /* don't use avi infoframe v1 */
599# define AFMT_AVI_INFO_PR(x) (((x) & 0xf) << 8) /* don't use avi infoframe v1 */
600# define AFMT_AVI_INFO_CN(x) (((x) & 0x3) << 12)
601# define AFMT_AVI_INFO_YQ(x) (((x) & 0x3) << 14)
602# define AFMT_AVI_INFO_TOP(x) (((x) & 0xffff) << 16)
603#define AFMT_AVI_INFO2 0x708c
604# define AFMT_AVI_INFO_BOTTOM(x) (((x) & 0xffff) << 0)
605# define AFMT_AVI_INFO_LEFT(x) (((x) & 0xffff) << 16)
606#define AFMT_AVI_INFO3 0x7090
607# define AFMT_AVI_INFO_RIGHT(x) (((x) & 0xffff) << 0)
608# define AFMT_AVI_INFO_VERSION(x) (((x) & 3) << 24)
609#define AFMT_MPEG_INFO0 0x7094
610# define AFMT_MPEG_INFO_CHECKSUM(x) (((x) & 0xff) << 0)
611# define AFMT_MPEG_INFO_MB0(x) (((x) & 0xff) << 8)
612# define AFMT_MPEG_INFO_MB1(x) (((x) & 0xff) << 16)
613# define AFMT_MPEG_INFO_MB2(x) (((x) & 0xff) << 24)
614#define AFMT_MPEG_INFO1 0x7098
615# define AFMT_MPEG_INFO_MB3(x) (((x) & 0xff) << 0)
616# define AFMT_MPEG_INFO_MF(x) (((x) & 3) << 8)
617# define AFMT_MPEG_INFO_FR(x) (((x) & 1) << 12)
618#define AFMT_GENERIC0_HDR 0x709c
619#define AFMT_GENERIC0_0 0x70a0
620#define AFMT_GENERIC0_1 0x70a4
621#define AFMT_GENERIC0_2 0x70a8
622#define AFMT_GENERIC0_3 0x70ac
623#define AFMT_GENERIC0_4 0x70b0
624#define AFMT_GENERIC0_5 0x70b4
625#define AFMT_GENERIC0_6 0x70b8
626#define AFMT_GENERIC1_HDR 0x70bc
627#define AFMT_GENERIC1_0 0x70c0
628#define AFMT_GENERIC1_1 0x70c4
629#define AFMT_GENERIC1_2 0x70c8
630#define AFMT_GENERIC1_3 0x70cc
631#define AFMT_GENERIC1_4 0x70d0
632#define AFMT_GENERIC1_5 0x70d4
633#define AFMT_GENERIC1_6 0x70d8
634#define HDMI_ACR_32_0 0x70dc
635# define HDMI_ACR_CTS_32(x) (((x) & 0xfffff) << 12)
636#define HDMI_ACR_32_1 0x70e0
637# define HDMI_ACR_N_32(x) (((x) & 0xfffff) << 0)
638#define HDMI_ACR_44_0 0x70e4
639# define HDMI_ACR_CTS_44(x) (((x) & 0xfffff) << 12)
640#define HDMI_ACR_44_1 0x70e8
641# define HDMI_ACR_N_44(x) (((x) & 0xfffff) << 0)
642#define HDMI_ACR_48_0 0x70ec
643# define HDMI_ACR_CTS_48(x) (((x) & 0xfffff) << 12)
644#define HDMI_ACR_48_1 0x70f0
645# define HDMI_ACR_N_48(x) (((x) & 0xfffff) << 0)
646#define HDMI_ACR_STATUS_0 0x70f4
647#define HDMI_ACR_STATUS_1 0x70f8
648#define AFMT_AUDIO_INFO0 0x70fc
649# define AFMT_AUDIO_INFO_CHECKSUM(x) (((x) & 0xff) << 0)
650# define AFMT_AUDIO_INFO_CC(x) (((x) & 7) << 8)
651# define AFMT_AUDIO_INFO_CT(x) (((x) & 0xf) << 11)
652# define AFMT_AUDIO_INFO_CHECKSUM_OFFSET(x) (((x) & 0xff) << 16)
653# define AFMT_AUDIO_INFO_CXT(x) (((x) & 0x1f) << 24)
654#define AFMT_AUDIO_INFO1 0x7100
655# define AFMT_AUDIO_INFO_CA(x) (((x) & 0xff) << 0)
656# define AFMT_AUDIO_INFO_LSV(x) (((x) & 0xf) << 11)
657# define AFMT_AUDIO_INFO_DM_INH(x) (((x) & 1) << 15)
658# define AFMT_AUDIO_INFO_DM_INH_LSV(x) (((x) & 0xff) << 8)
659# define AFMT_AUDIO_INFO_LFEBPL(x) (((x) & 3) << 16)
660#define AFMT_60958_0 0x7104
661# define AFMT_60958_CS_A(x) (((x) & 1) << 0)
662# define AFMT_60958_CS_B(x) (((x) & 1) << 1)
663# define AFMT_60958_CS_C(x) (((x) & 1) << 2)
664# define AFMT_60958_CS_D(x) (((x) & 3) << 3)
665# define AFMT_60958_CS_MODE(x) (((x) & 3) << 6)
666# define AFMT_60958_CS_CATEGORY_CODE(x) (((x) & 0xff) << 8)
667# define AFMT_60958_CS_SOURCE_NUMBER(x) (((x) & 0xf) << 16)
668# define AFMT_60958_CS_CHANNEL_NUMBER_L(x) (((x) & 0xf) << 20)
669# define AFMT_60958_CS_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 24)
670# define AFMT_60958_CS_CLOCK_ACCURACY(x) (((x) & 3) << 28)
671#define AFMT_60958_1 0x7108
672# define AFMT_60958_CS_WORD_LENGTH(x) (((x) & 0xf) << 0)
673# define AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 4)
674# define AFMT_60958_CS_VALID_L(x) (((x) & 1) << 16)
675# define AFMT_60958_CS_VALID_R(x) (((x) & 1) << 18)
676# define AFMT_60958_CS_CHANNEL_NUMBER_R(x) (((x) & 0xf) << 20)
677#define AFMT_AUDIO_CRC_CONTROL 0x710c
678# define AFMT_AUDIO_CRC_EN (1 << 0)
679#define AFMT_RAMP_CONTROL0 0x7110
680# define AFMT_RAMP_MAX_COUNT(x) (((x) & 0xffffff) << 0)
681# define AFMT_RAMP_DATA_SIGN (1 << 31)
682#define AFMT_RAMP_CONTROL1 0x7114
683# define AFMT_RAMP_MIN_COUNT(x) (((x) & 0xffffff) << 0)
684# define AFMT_AUDIO_TEST_CH_DISABLE(x) (((x) & 0xff) << 24)
685#define AFMT_RAMP_CONTROL2 0x7118
686# define AFMT_RAMP_INC_COUNT(x) (((x) & 0xffffff) << 0)
687#define AFMT_RAMP_CONTROL3 0x711c
688# define AFMT_RAMP_DEC_COUNT(x) (((x) & 0xffffff) << 0)
689#define AFMT_60958_2 0x7120
690# define AFMT_60958_CS_CHANNEL_NUMBER_2(x) (((x) & 0xf) << 0)
691# define AFMT_60958_CS_CHANNEL_NUMBER_3(x) (((x) & 0xf) << 4)
692# define AFMT_60958_CS_CHANNEL_NUMBER_4(x) (((x) & 0xf) << 8)
693# define AFMT_60958_CS_CHANNEL_NUMBER_5(x) (((x) & 0xf) << 12)
694# define AFMT_60958_CS_CHANNEL_NUMBER_6(x) (((x) & 0xf) << 16)
695# define AFMT_60958_CS_CHANNEL_NUMBER_7(x) (((x) & 0xf) << 20)
696#define AFMT_STATUS 0x7128
697# define AFMT_AUDIO_ENABLE (1 << 4)
698# define AFMT_AUDIO_HBR_ENABLE (1 << 8)
699# define AFMT_AZ_FORMAT_WTRIG (1 << 28)
700# define AFMT_AZ_FORMAT_WTRIG_INT (1 << 29)
701# define AFMT_AZ_AUDIO_ENABLE_CHG (1 << 30)
702#define AFMT_AUDIO_PACKET_CONTROL 0x712c
703# define AFMT_AUDIO_SAMPLE_SEND (1 << 0)
704# define AFMT_RESET_FIFO_WHEN_AUDIO_DIS (1 << 11) /* set to 1 */
705# define AFMT_AUDIO_TEST_EN (1 << 12)
706# define AFMT_AUDIO_CHANNEL_SWAP (1 << 24)
707# define AFMT_60958_CS_UPDATE (1 << 26)
708# define AFMT_AZ_AUDIO_ENABLE_CHG_MASK (1 << 27)
709# define AFMT_AZ_FORMAT_WTRIG_MASK (1 << 28)
710# define AFMT_AZ_FORMAT_WTRIG_ACK (1 << 29)
711# define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30)
712#define AFMT_VBI_PACKET_CONTROL 0x7130
713# define AFMT_GENERIC0_UPDATE (1 << 2)
714#define AFMT_INFOFRAME_CONTROL0 0x7134
715# define AFMT_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - afmt regs */
716# define AFMT_AUDIO_INFO_UPDATE (1 << 7)
717# define AFMT_MPEG_INFO_UPDATE (1 << 10)
718#define AFMT_GENERIC0_7 0x7138
719
720/* DCE4/5 ELD audio interface */
721#define AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER 0x5f78
722#define SPEAKER_ALLOCATION(x) (((x) & 0x7f) << 0)
723#define SPEAKER_ALLOCATION_MASK (0x7f << 0)
724#define SPEAKER_ALLOCATION_SHIFT 0
725#define HDMI_CONNECTION (1 << 16)
726#define DP_CONNECTION (1 << 17)
727
728#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0 0x5f84 /* LPCM */
729#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1 0x5f88 /* AC3 */
730#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2 0x5f8c /* MPEG1 */
731#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3 0x5f90 /* MP3 */
732#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4 0x5f94 /* MPEG2 */
733#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5 0x5f98 /* AAC */
734#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6 0x5f9c /* DTS */
735#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7 0x5fa0 /* ATRAC */
736#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR8 0x5fa4 /* one bit audio - leave at 0 (default) */
737#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9 0x5fa8 /* Dolby Digital */
738#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10 0x5fac /* DTS-HD */
739#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11 0x5fb0 /* MAT-MLP */
740#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR12 0x5fb4 /* DTS */
741#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13 0x5fb8 /* WMA Pro */
742# define MAX_CHANNELS(x) (((x) & 0x7) << 0)
743/* max channels minus one. 7 = 8 channels */
744# define SUPPORTED_FREQUENCIES(x) (((x) & 0xff) << 8)
745# define DESCRIPTOR_BYTE_2(x) (((x) & 0xff) << 16)
746# define SUPPORTED_FREQUENCIES_STEREO(x) (((x) & 0xff) << 24) /* LPCM only */
747/* SUPPORTED_FREQUENCIES, SUPPORTED_FREQUENCIES_STEREO
748 * bit0 = 32 kHz
749 * bit1 = 44.1 kHz
750 * bit2 = 48 kHz
751 * bit3 = 88.2 kHz
752 * bit4 = 96 kHz
753 * bit5 = 176.4 kHz
754 * bit6 = 192 kHz
755 */
756
757#define AZ_CHANNEL_COUNT_CONTROL 0x5fe4
758# define HBR_CHANNEL_COUNT(x) (((x) & 0x7) << 0)
759# define COMPRESSED_CHANNEL_COUNT(x) (((x) & 0x7) << 4)
760/* HBR_CHANNEL_COUNT, COMPRESSED_CHANNEL_COUNT
761 * 0 = use stream header
762 * 1-7 = channel count - 1
763 */
764#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC 0x5fe8
765# define VIDEO_LIPSYNC(x) (((x) & 0xff) << 0)
766# define AUDIO_LIPSYNC(x) (((x) & 0xff) << 8)
767/* VIDEO_LIPSYNC, AUDIO_LIPSYNC
768 * 0 = invalid
769 * x = legal delay value
770 * 255 = sync not supported
771 */
772#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_HBR 0x5fec
773# define HBR_CAPABLE (1 << 0) /* enabled by default */
774
775#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION0 0x5ff4
776# define DISPLAY0_TYPE(x) (((x) & 0x3) << 0)
777# define DISPLAY_TYPE_NONE 0
778# define DISPLAY_TYPE_HDMI 1
779# define DISPLAY_TYPE_DP 2
780# define DISPLAY0_ID(x) (((x) & 0x3f) << 2)
781# define DISPLAY1_TYPE(x) (((x) & 0x3) << 8)
782# define DISPLAY1_ID(x) (((x) & 0x3f) << 10)
783# define DISPLAY2_TYPE(x) (((x) & 0x3) << 16)
784# define DISPLAY2_ID(x) (((x) & 0x3f) << 18)
785# define DISPLAY3_TYPE(x) (((x) & 0x3) << 24)
786# define DISPLAY3_ID(x) (((x) & 0x3f) << 26)
787#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION1 0x5ff8
788# define DISPLAY4_TYPE(x) (((x) & 0x3) << 0)
789# define DISPLAY4_ID(x) (((x) & 0x3f) << 2)
790# define DISPLAY5_TYPE(x) (((x) & 0x3) << 8)
791# define DISPLAY5_ID(x) (((x) & 0x3f) << 10)
792#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_NUMBER 0x5ffc
793# define NUMBER_OF_DISPLAY_ID(x) (((x) & 0x7) << 0)
794
795#define AZ_HOT_PLUG_CONTROL 0x5e78
796# define AZ_FORCE_CODEC_WAKE (1 << 0)
797# define PIN0_JACK_DETECTION_ENABLE (1 << 4)
798# define PIN1_JACK_DETECTION_ENABLE (1 << 5)
799# define PIN2_JACK_DETECTION_ENABLE (1 << 6)
800# define PIN3_JACK_DETECTION_ENABLE (1 << 7)
801# define PIN0_UNSOLICITED_RESPONSE_ENABLE (1 << 8)
802# define PIN1_UNSOLICITED_RESPONSE_ENABLE (1 << 9)
803# define PIN2_UNSOLICITED_RESPONSE_ENABLE (1 << 10)
804# define PIN3_UNSOLICITED_RESPONSE_ENABLE (1 << 11)
805# define CODEC_HOT_PLUG_ENABLE (1 << 12)
806# define PIN0_AUDIO_ENABLED (1 << 24)
807# define PIN1_AUDIO_ENABLED (1 << 25)
808# define PIN2_AUDIO_ENABLED (1 << 26)
809# define PIN3_AUDIO_ENABLED (1 << 27)
810# define AUDIO_ENABLED (1 << 31)
811
812
813#define GC_USER_SHADER_PIPE_CONFIG 0x8954
814#define INACTIVE_QD_PIPES(x) ((x) << 8)
815#define INACTIVE_QD_PIPES_MASK 0x0000FF00
816#define INACTIVE_SIMDS(x) ((x) << 16)
817#define INACTIVE_SIMDS_MASK 0x00FF0000
818
819#define GRBM_CNTL 0x8000
820#define GRBM_READ_TIMEOUT(x) ((x) << 0)
821#define GRBM_SOFT_RESET 0x8020
822#define SOFT_RESET_CP (1 << 0)
823#define SOFT_RESET_CB (1 << 1)
824#define SOFT_RESET_DB (1 << 3)
825#define SOFT_RESET_PA (1 << 5)
826#define SOFT_RESET_SC (1 << 6)
827#define SOFT_RESET_SPI (1 << 8)
828#define SOFT_RESET_SH (1 << 9)
829#define SOFT_RESET_SX (1 << 10)
830#define SOFT_RESET_TC (1 << 11)
831#define SOFT_RESET_TA (1 << 12)
832#define SOFT_RESET_VC (1 << 13)
833#define SOFT_RESET_VGT (1 << 14)
834
835#define GRBM_STATUS 0x8010
836#define CMDFIFO_AVAIL_MASK 0x0000000F
837#define SRBM_RQ_PENDING (1 << 5)
838#define CF_RQ_PENDING (1 << 7)
839#define PF_RQ_PENDING (1 << 8)
840#define GRBM_EE_BUSY (1 << 10)
841#define SX_CLEAN (1 << 11)
842#define DB_CLEAN (1 << 12)
843#define CB_CLEAN (1 << 13)
844#define TA_BUSY (1 << 14)
845#define VGT_BUSY_NO_DMA (1 << 16)
846#define VGT_BUSY (1 << 17)
847#define SX_BUSY (1 << 20)
848#define SH_BUSY (1 << 21)
849#define SPI_BUSY (1 << 22)
850#define SC_BUSY (1 << 24)
851#define PA_BUSY (1 << 25)
852#define DB_BUSY (1 << 26)
853#define CP_COHERENCY_BUSY (1 << 28)
854#define CP_BUSY (1 << 29)
855#define CB_BUSY (1 << 30)
856#define GUI_ACTIVE (1 << 31)
857#define GRBM_STATUS_SE0 0x8014
858#define GRBM_STATUS_SE1 0x8018
859#define SE_SX_CLEAN (1 << 0)
860#define SE_DB_CLEAN (1 << 1)
861#define SE_CB_CLEAN (1 << 2)
862#define SE_TA_BUSY (1 << 25)
863#define SE_SX_BUSY (1 << 26)
864#define SE_SPI_BUSY (1 << 27)
865#define SE_SH_BUSY (1 << 28)
866#define SE_SC_BUSY (1 << 29)
867#define SE_DB_BUSY (1 << 30)
868#define SE_CB_BUSY (1 << 31)
869/* evergreen */
870#define CG_THERMAL_CTRL 0x72c
871#define TOFFSET_MASK 0x00003FE0
872#define TOFFSET_SHIFT 5
873#define DIG_THERM_DPM(x) ((x) << 14)
874#define DIG_THERM_DPM_MASK 0x003FC000
875#define DIG_THERM_DPM_SHIFT 14
876
877#define CG_THERMAL_INT 0x734
878#define DIG_THERM_INTH(x) ((x) << 8)
879#define DIG_THERM_INTH_MASK 0x0000FF00
880#define DIG_THERM_INTH_SHIFT 8
881#define DIG_THERM_INTL(x) ((x) << 16)
882#define DIG_THERM_INTL_MASK 0x00FF0000
883#define DIG_THERM_INTL_SHIFT 16
884#define THERM_INT_MASK_HIGH (1 << 24)
885#define THERM_INT_MASK_LOW (1 << 25)
886
887#define TN_CG_THERMAL_INT_CTRL 0x738
888#define TN_DIG_THERM_INTH(x) ((x) << 0)
889#define TN_DIG_THERM_INTH_MASK 0x000000FF
890#define TN_DIG_THERM_INTH_SHIFT 0
891#define TN_DIG_THERM_INTL(x) ((x) << 8)
892#define TN_DIG_THERM_INTL_MASK 0x0000FF00
893#define TN_DIG_THERM_INTL_SHIFT 8
894#define TN_THERM_INT_MASK_HIGH (1 << 24)
895#define TN_THERM_INT_MASK_LOW (1 << 25)
896
897#define CG_MULT_THERMAL_STATUS 0x740
898#define ASIC_T(x) ((x) << 16)
899#define ASIC_T_MASK 0x07FF0000
900#define ASIC_T_SHIFT 16
901#define CG_TS0_STATUS 0x760
902#define TS0_ADC_DOUT_MASK 0x000003FF
903#define TS0_ADC_DOUT_SHIFT 0
904
905/* APU */
906#define CG_THERMAL_STATUS 0x678
907
908#define HDP_HOST_PATH_CNTL 0x2C00
909#define HDP_NONSURFACE_BASE 0x2C04
910#define HDP_NONSURFACE_INFO 0x2C08
911#define HDP_NONSURFACE_SIZE 0x2C0C
912#define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480
913#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
914#define HDP_TILING_CONFIG 0x2F3C
915
916#define MC_SHARED_CHMAP 0x2004
917#define NOOFCHAN_SHIFT 12
918#define NOOFCHAN_MASK 0x00003000
919#define MC_SHARED_CHREMAP 0x2008
920
921#define MC_SHARED_BLACKOUT_CNTL 0x20ac
922#define BLACKOUT_MODE_MASK 0x00000007
923
924#define MC_ARB_RAMCFG 0x2760
925#define NOOFBANK_SHIFT 0
926#define NOOFBANK_MASK 0x00000003
927#define NOOFRANK_SHIFT 2
928#define NOOFRANK_MASK 0x00000004
929#define NOOFROWS_SHIFT 3
930#define NOOFROWS_MASK 0x00000038
931#define NOOFCOLS_SHIFT 6
932#define NOOFCOLS_MASK 0x000000C0
933#define CHANSIZE_SHIFT 8
934#define CHANSIZE_MASK 0x00000100
935#define BURSTLENGTH_SHIFT 9
936#define BURSTLENGTH_MASK 0x00000200
937#define CHANSIZE_OVERRIDE (1 << 11)
938#define FUS_MC_ARB_RAMCFG 0x2768
939#define MC_VM_AGP_TOP 0x2028
940#define MC_VM_AGP_BOT 0x202C
941#define MC_VM_AGP_BASE 0x2030
942#define MC_VM_FB_LOCATION 0x2024
943#define MC_FUS_VM_FB_OFFSET 0x2898
944#define MC_VM_MB_L1_TLB0_CNTL 0x2234
945#define MC_VM_MB_L1_TLB1_CNTL 0x2238
946#define MC_VM_MB_L1_TLB2_CNTL 0x223C
947#define MC_VM_MB_L1_TLB3_CNTL 0x2240
948#define ENABLE_L1_TLB (1 << 0)
949#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
950#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)
951#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
952#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
953#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)
954#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
955#define EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15)
956#define EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18)
957#define MC_VM_MD_L1_TLB0_CNTL 0x2654
958#define MC_VM_MD_L1_TLB1_CNTL 0x2658
959#define MC_VM_MD_L1_TLB2_CNTL 0x265C
960#define MC_VM_MD_L1_TLB3_CNTL 0x2698
961
962#define FUS_MC_VM_MD_L1_TLB0_CNTL 0x265C
963#define FUS_MC_VM_MD_L1_TLB1_CNTL 0x2660
964#define FUS_MC_VM_MD_L1_TLB2_CNTL 0x2664
965
966#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C
967#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
968#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
969
970#define PA_CL_ENHANCE 0x8A14
971#define CLIP_VTX_REORDER_ENA (1 << 0)
972#define NUM_CLIP_SEQ(x) ((x) << 1)
973#define PA_SC_ENHANCE 0x8BF0
974#define PA_SC_AA_CONFIG 0x28C04
975#define MSAA_NUM_SAMPLES_SHIFT 0
976#define MSAA_NUM_SAMPLES_MASK 0x3
977#define PA_SC_CLIPRECT_RULE 0x2820C
978#define PA_SC_EDGERULE 0x28230
979#define PA_SC_FIFO_SIZE 0x8BCC
980#define SC_PRIM_FIFO_SIZE(x) ((x) << 0)
981#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12)
982#define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20)
983#define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24
984#define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
985#define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)
986#define PA_SC_LINE_STIPPLE 0x28A0C
987#define PA_SU_LINE_STIPPLE_VALUE 0x8A60
988#define PA_SC_LINE_STIPPLE_STATE 0x8B10
989
990#define SCRATCH_REG0 0x8500
991#define SCRATCH_REG1 0x8504
992#define SCRATCH_REG2 0x8508
993#define SCRATCH_REG3 0x850C
994#define SCRATCH_REG4 0x8510
995#define SCRATCH_REG5 0x8514
996#define SCRATCH_REG6 0x8518
997#define SCRATCH_REG7 0x851C
998#define SCRATCH_UMSK 0x8540
999#define SCRATCH_ADDR 0x8544
1000
1001#define SMX_SAR_CTL0 0xA008
1002#define SMX_DC_CTL0 0xA020
1003#define USE_HASH_FUNCTION (1 << 0)
1004#define NUMBER_OF_SETS(x) ((x) << 1)
1005#define FLUSH_ALL_ON_EVENT (1 << 10)
1006#define STALL_ON_EVENT (1 << 11)
1007#define SMX_EVENT_CTL 0xA02C
1008#define ES_FLUSH_CTL(x) ((x) << 0)
1009#define GS_FLUSH_CTL(x) ((x) << 3)
1010#define ACK_FLUSH_CTL(x) ((x) << 6)
1011#define SYNC_FLUSH_CTL (1 << 8)
1012
1013#define SPI_CONFIG_CNTL 0x9100
1014#define GPR_WRITE_PRIORITY(x) ((x) << 0)
1015#define SPI_CONFIG_CNTL_1 0x913C
1016#define VTX_DONE_DELAY(x) ((x) << 0)
1017#define INTERP_ONE_PRIM_PER_ROW (1 << 4)
1018#define SPI_INPUT_Z 0x286D8
1019#define SPI_PS_IN_CONTROL_0 0x286CC
1020#define NUM_INTERP(x) ((x)<<0)
1021#define POSITION_ENA (1<<8)
1022#define POSITION_CENTROID (1<<9)
1023#define POSITION_ADDR(x) ((x)<<10)
1024#define PARAM_GEN(x) ((x)<<15)
1025#define PARAM_GEN_ADDR(x) ((x)<<19)
1026#define BARYC_SAMPLE_CNTL(x) ((x)<<26)
1027#define PERSP_GRADIENT_ENA (1<<28)
1028#define LINEAR_GRADIENT_ENA (1<<29)
1029#define POSITION_SAMPLE (1<<30)
1030#define BARYC_AT_SAMPLE_ENA (1<<31)
1031
1032#define SQ_CONFIG 0x8C00
1033#define VC_ENABLE (1 << 0)
1034#define EXPORT_SRC_C (1 << 1)
1035#define CS_PRIO(x) ((x) << 18)
1036#define LS_PRIO(x) ((x) << 20)
1037#define HS_PRIO(x) ((x) << 22)
1038#define PS_PRIO(x) ((x) << 24)
1039#define VS_PRIO(x) ((x) << 26)
1040#define GS_PRIO(x) ((x) << 28)
1041#define ES_PRIO(x) ((x) << 30)
1042#define SQ_GPR_RESOURCE_MGMT_1 0x8C04
1043#define NUM_PS_GPRS(x) ((x) << 0)
1044#define NUM_VS_GPRS(x) ((x) << 16)
1045#define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28)
1046#define SQ_GPR_RESOURCE_MGMT_2 0x8C08
1047#define NUM_GS_GPRS(x) ((x) << 0)
1048#define NUM_ES_GPRS(x) ((x) << 16)
1049#define SQ_GPR_RESOURCE_MGMT_3 0x8C0C
1050#define NUM_HS_GPRS(x) ((x) << 0)
1051#define NUM_LS_GPRS(x) ((x) << 16)
1052#define SQ_GLOBAL_GPR_RESOURCE_MGMT_1 0x8C10
1053#define SQ_GLOBAL_GPR_RESOURCE_MGMT_2 0x8C14
1054#define SQ_THREAD_RESOURCE_MGMT 0x8C18
1055#define NUM_PS_THREADS(x) ((x) << 0)
1056#define NUM_VS_THREADS(x) ((x) << 8)
1057#define NUM_GS_THREADS(x) ((x) << 16)
1058#define NUM_ES_THREADS(x) ((x) << 24)
1059#define SQ_THREAD_RESOURCE_MGMT_2 0x8C1C
1060#define NUM_HS_THREADS(x) ((x) << 0)
1061#define NUM_LS_THREADS(x) ((x) << 8)
1062#define SQ_STACK_RESOURCE_MGMT_1 0x8C20
1063#define NUM_PS_STACK_ENTRIES(x) ((x) << 0)
1064#define NUM_VS_STACK_ENTRIES(x) ((x) << 16)
1065#define SQ_STACK_RESOURCE_MGMT_2 0x8C24
1066#define NUM_GS_STACK_ENTRIES(x) ((x) << 0)
1067#define NUM_ES_STACK_ENTRIES(x) ((x) << 16)
1068#define SQ_STACK_RESOURCE_MGMT_3 0x8C28
1069#define NUM_HS_STACK_ENTRIES(x) ((x) << 0)
1070#define NUM_LS_STACK_ENTRIES(x) ((x) << 16)
1071#define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C
1072#define SQ_DYN_GPR_SIMD_LOCK_EN 0x8D94
1073#define SQ_STATIC_THREAD_MGMT_1 0x8E20
1074#define SQ_STATIC_THREAD_MGMT_2 0x8E24
1075#define SQ_STATIC_THREAD_MGMT_3 0x8E28
1076#define SQ_LDS_RESOURCE_MGMT 0x8E2C
1077
1078#define SQ_MS_FIFO_SIZES 0x8CF0
1079#define CACHE_FIFO_SIZE(x) ((x) << 0)
1080#define FETCH_FIFO_HIWATER(x) ((x) << 8)
1081#define DONE_FIFO_HIWATER(x) ((x) << 16)
1082#define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24)
1083
1084#define SX_DEBUG_1 0x9058
1085#define ENABLE_NEW_SMX_ADDRESS (1 << 16)
1086#define SX_EXPORT_BUFFER_SIZES 0x900C
1087#define COLOR_BUFFER_SIZE(x) ((x) << 0)
1088#define POSITION_BUFFER_SIZE(x) ((x) << 8)
1089#define SMX_BUFFER_SIZE(x) ((x) << 16)
1090#define SX_MEMORY_EXPORT_BASE 0x9010
1091#define SX_MISC 0x28350
1092
1093#define CB_PERF_CTR0_SEL_0 0x9A20
1094#define CB_PERF_CTR0_SEL_1 0x9A24
1095#define CB_PERF_CTR1_SEL_0 0x9A28
1096#define CB_PERF_CTR1_SEL_1 0x9A2C
1097#define CB_PERF_CTR2_SEL_0 0x9A30
1098#define CB_PERF_CTR2_SEL_1 0x9A34
1099#define CB_PERF_CTR3_SEL_0 0x9A38
1100#define CB_PERF_CTR3_SEL_1 0x9A3C
1101
1102#define TA_CNTL_AUX 0x9508
1103#define DISABLE_CUBE_WRAP (1 << 0)
1104#define DISABLE_CUBE_ANISO (1 << 1)
1105#define SYNC_GRADIENT (1 << 24)
1106#define SYNC_WALKER (1 << 25)
1107#define SYNC_ALIGNER (1 << 26)
1108
1109#define TCP_CHAN_STEER_LO 0x960c
1110#define TCP_CHAN_STEER_HI 0x9610
1111
1112#define VGT_CACHE_INVALIDATION 0x88C4
1113#define CACHE_INVALIDATION(x) ((x) << 0)
1114#define VC_ONLY 0
1115#define TC_ONLY 1
1116#define VC_AND_TC 2
1117#define AUTO_INVLD_EN(x) ((x) << 6)
1118#define NO_AUTO 0
1119#define ES_AUTO 1
1120#define GS_AUTO 2
1121#define ES_AND_GS_AUTO 3
1122#define VGT_GS_VERTEX_REUSE 0x88D4
1123#define VGT_NUM_INSTANCES 0x8974
1124#define VGT_OUT_DEALLOC_CNTL 0x28C5C
1125#define DEALLOC_DIST_MASK 0x0000007F
1126#define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58
1127#define VTX_REUSE_DEPTH_MASK 0x000000FF
1128
1129#define VM_CONTEXT0_CNTL 0x1410
1130#define ENABLE_CONTEXT (1 << 0)
1131#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
1132#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
1133#define VM_CONTEXT1_CNTL 0x1414
1134#define VM_CONTEXT1_CNTL2 0x1434
1135#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C
1136#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C
1137#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C
1138#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518
1139#define VM_CONTEXT0_REQUEST_RESPONSE 0x1470
1140#define REQUEST_TYPE(x) (((x) & 0xf) << 0)
1141#define RESPONSE_TYPE_MASK 0x000000F0
1142#define RESPONSE_TYPE_SHIFT 4
1143#define VM_L2_CNTL 0x1400
1144#define ENABLE_L2_CACHE (1 << 0)
1145#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
1146#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
1147#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14)
1148#define VM_L2_CNTL2 0x1404
1149#define INVALIDATE_ALL_L1_TLBS (1 << 0)
1150#define INVALIDATE_L2_CACHE (1 << 1)
1151#define VM_L2_CNTL3 0x1408
1152#define BANK_SELECT(x) ((x) << 0)
1153#define CACHE_UPDATE_MODE(x) ((x) << 6)
1154#define VM_L2_STATUS 0x140C
1155#define L2_BUSY (1 << 0)
1156#define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC
1157#define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC
1158
1159#define WAIT_UNTIL 0x8040
1160
1161#define SRBM_STATUS 0x0E50
1162#define RLC_RQ_PENDING (1 << 3)
1163#define GRBM_RQ_PENDING (1 << 5)
1164#define VMC_BUSY (1 << 8)
1165#define MCB_BUSY (1 << 9)
1166#define MCB_NON_DISPLAY_BUSY (1 << 10)
1167#define MCC_BUSY (1 << 11)
1168#define MCD_BUSY (1 << 12)
1169#define SEM_BUSY (1 << 14)
1170#define RLC_BUSY (1 << 15)
1171#define IH_BUSY (1 << 17)
1172#define SRBM_STATUS2 0x0EC4
1173#define DMA_BUSY (1 << 5)
1174#define SRBM_SOFT_RESET 0x0E60
1175#define SRBM_SOFT_RESET_ALL_MASK 0x00FEEFA6
1176#define SOFT_RESET_BIF (1 << 1)
1177#define SOFT_RESET_CG (1 << 2)
1178#define SOFT_RESET_DC (1 << 5)
1179#define SOFT_RESET_GRBM (1 << 8)
1180#define SOFT_RESET_HDP (1 << 9)
1181#define SOFT_RESET_IH (1 << 10)
1182#define SOFT_RESET_MC (1 << 11)
1183#define SOFT_RESET_RLC (1 << 13)
1184#define SOFT_RESET_ROM (1 << 14)
1185#define SOFT_RESET_SEM (1 << 15)
1186#define SOFT_RESET_VMC (1 << 17)
1187#define SOFT_RESET_DMA (1 << 20)
1188#define SOFT_RESET_TST (1 << 21)
1189#define SOFT_RESET_REGBB (1 << 22)
1190#define SOFT_RESET_ORB (1 << 23)
1191
1192/* display watermarks */
1193#define DC_LB_MEMORY_SPLIT 0x6b0c
1194#define PRIORITY_A_CNT 0x6b18
1195#define PRIORITY_MARK_MASK 0x7fff
1196#define PRIORITY_OFF (1 << 16)
1197#define PRIORITY_ALWAYS_ON (1 << 20)
1198#define PRIORITY_B_CNT 0x6b1c
1199#define PIPE0_ARBITRATION_CONTROL3 0x0bf0
1200# define LATENCY_WATERMARK_MASK(x) ((x) << 16)
1201#define PIPE0_LATENCY_CONTROL 0x0bf4
1202# define LATENCY_LOW_WATERMARK(x) ((x) << 0)
1203# define LATENCY_HIGH_WATERMARK(x) ((x) << 16)
1204
1205#define PIPE0_DMIF_BUFFER_CONTROL 0x0ca0
1206# define DMIF_BUFFERS_ALLOCATED(x) ((x) << 0)
1207# define DMIF_BUFFERS_ALLOCATED_COMPLETED (1 << 4)
1208
1209#define IH_RB_CNTL 0x3e00
1210# define IH_RB_ENABLE (1 << 0)
1211# define IH_IB_SIZE(x) ((x) << 1) /* log2 */
1212# define IH_RB_FULL_DRAIN_ENABLE (1 << 6)
1213# define IH_WPTR_WRITEBACK_ENABLE (1 << 8)
1214# define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */
1215# define IH_WPTR_OVERFLOW_ENABLE (1 << 16)
1216# define IH_WPTR_OVERFLOW_CLEAR (1 << 31)
1217#define IH_RB_BASE 0x3e04
1218#define IH_RB_RPTR 0x3e08
1219#define IH_RB_WPTR 0x3e0c
1220# define RB_OVERFLOW (1 << 0)
1221# define WPTR_OFFSET_MASK 0x3fffc
1222#define IH_RB_WPTR_ADDR_HI 0x3e10
1223#define IH_RB_WPTR_ADDR_LO 0x3e14
1224#define IH_CNTL 0x3e18
1225# define ENABLE_INTR (1 << 0)
1226# define IH_MC_SWAP(x) ((x) << 1)
1227# define IH_MC_SWAP_NONE 0
1228# define IH_MC_SWAP_16BIT 1
1229# define IH_MC_SWAP_32BIT 2
1230# define IH_MC_SWAP_64BIT 3
1231# define RPTR_REARM (1 << 4)
1232# define MC_WRREQ_CREDIT(x) ((x) << 15)
1233# define MC_WR_CLEAN_CNT(x) ((x) << 20)
1234
1235#define CP_INT_CNTL 0xc124
1236# define CNTX_BUSY_INT_ENABLE (1 << 19)
1237# define CNTX_EMPTY_INT_ENABLE (1 << 20)
1238# define SCRATCH_INT_ENABLE (1 << 25)
1239# define TIME_STAMP_INT_ENABLE (1 << 26)
1240# define IB2_INT_ENABLE (1 << 29)
1241# define IB1_INT_ENABLE (1 << 30)
1242# define RB_INT_ENABLE (1 << 31)
1243#define CP_INT_STATUS 0xc128
1244# define SCRATCH_INT_STAT (1 << 25)
1245# define TIME_STAMP_INT_STAT (1 << 26)
1246# define IB2_INT_STAT (1 << 29)
1247# define IB1_INT_STAT (1 << 30)
1248# define RB_INT_STAT (1 << 31)
1249
1250#define GRBM_INT_CNTL 0x8060
1251# define RDERR_INT_ENABLE (1 << 0)
1252# define GUI_IDLE_INT_ENABLE (1 << 19)
1253
1254/* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */
1255#define CRTC_STATUS_FRAME_COUNT 0x6e98
1256
1257/* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */
1258#define VLINE_STATUS 0x6bb8
1259# define VLINE_OCCURRED (1 << 0)
1260# define VLINE_ACK (1 << 4)
1261# define VLINE_STAT (1 << 12)
1262# define VLINE_INTERRUPT (1 << 16)
1263# define VLINE_INTERRUPT_TYPE (1 << 17)
1264/* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */
1265#define VBLANK_STATUS 0x6bbc
1266# define VBLANK_OCCURRED (1 << 0)
1267# define VBLANK_ACK (1 << 4)
1268# define VBLANK_STAT (1 << 12)
1269# define VBLANK_INTERRUPT (1 << 16)
1270# define VBLANK_INTERRUPT_TYPE (1 << 17)
1271
1272/* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */
1273#define INT_MASK 0x6b40
1274# define VBLANK_INT_MASK (1 << 0)
1275# define VLINE_INT_MASK (1 << 4)
1276
1277#define DISP_INTERRUPT_STATUS 0x60f4
1278# define LB_D1_VLINE_INTERRUPT (1 << 2)
1279# define LB_D1_VBLANK_INTERRUPT (1 << 3)
1280# define DC_HPD1_INTERRUPT (1 << 17)
1281# define DC_HPD1_RX_INTERRUPT (1 << 18)
1282# define DACA_AUTODETECT_INTERRUPT (1 << 22)
1283# define DACB_AUTODETECT_INTERRUPT (1 << 23)
1284# define DC_I2C_SW_DONE_INTERRUPT (1 << 24)
1285# define DC_I2C_HW_DONE_INTERRUPT (1 << 25)
1286#define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8
1287# define LB_D2_VLINE_INTERRUPT (1 << 2)
1288# define LB_D2_VBLANK_INTERRUPT (1 << 3)
1289# define DC_HPD2_INTERRUPT (1 << 17)
1290# define DC_HPD2_RX_INTERRUPT (1 << 18)
1291# define DISP_TIMER_INTERRUPT (1 << 24)
1292#define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc
1293# define LB_D3_VLINE_INTERRUPT (1 << 2)
1294# define LB_D3_VBLANK_INTERRUPT (1 << 3)
1295# define DC_HPD3_INTERRUPT (1 << 17)
1296# define DC_HPD3_RX_INTERRUPT (1 << 18)
1297#define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100
1298# define LB_D4_VLINE_INTERRUPT (1 << 2)
1299# define LB_D4_VBLANK_INTERRUPT (1 << 3)
1300# define DC_HPD4_INTERRUPT (1 << 17)
1301# define DC_HPD4_RX_INTERRUPT (1 << 18)
1302#define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c
1303# define LB_D5_VLINE_INTERRUPT (1 << 2)
1304# define LB_D5_VBLANK_INTERRUPT (1 << 3)
1305# define DC_HPD5_INTERRUPT (1 << 17)
1306# define DC_HPD5_RX_INTERRUPT (1 << 18)
1307#define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150
1308# define LB_D6_VLINE_INTERRUPT (1 << 2)
1309# define LB_D6_VBLANK_INTERRUPT (1 << 3)
1310# define DC_HPD6_INTERRUPT (1 << 17)
1311# define DC_HPD6_RX_INTERRUPT (1 << 18)
1312
1313/* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */
1314#define GRPH_INT_STATUS 0x6858
1315# define GRPH_PFLIP_INT_OCCURRED (1 << 0)
1316# define GRPH_PFLIP_INT_CLEAR (1 << 8)
1317/* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */
1318#define GRPH_INT_CONTROL 0x685c
1319# define GRPH_PFLIP_INT_MASK (1 << 0)
1320# define GRPH_PFLIP_INT_TYPE (1 << 8)
1321
1322#define DACA_AUTODETECT_INT_CONTROL 0x66c8
1323#define DACB_AUTODETECT_INT_CONTROL 0x67c8
1324
1325#define DC_HPD1_INT_STATUS 0x601c
1326#define DC_HPD2_INT_STATUS 0x6028
1327#define DC_HPD3_INT_STATUS 0x6034
1328#define DC_HPD4_INT_STATUS 0x6040
1329#define DC_HPD5_INT_STATUS 0x604c
1330#define DC_HPD6_INT_STATUS 0x6058
1331# define DC_HPDx_INT_STATUS (1 << 0)
1332# define DC_HPDx_SENSE (1 << 1)
1333# define DC_HPDx_RX_INT_STATUS (1 << 8)
1334
1335#define DC_HPD1_INT_CONTROL 0x6020
1336#define DC_HPD2_INT_CONTROL 0x602c
1337#define DC_HPD3_INT_CONTROL 0x6038
1338#define DC_HPD4_INT_CONTROL 0x6044
1339#define DC_HPD5_INT_CONTROL 0x6050
1340#define DC_HPD6_INT_CONTROL 0x605c
1341# define DC_HPDx_INT_ACK (1 << 0)
1342# define DC_HPDx_INT_POLARITY (1 << 8)
1343# define DC_HPDx_INT_EN (1 << 16)
1344# define DC_HPDx_RX_INT_ACK (1 << 20)
1345# define DC_HPDx_RX_INT_EN (1 << 24)
1346
1347#define DC_HPD1_CONTROL 0x6024
1348#define DC_HPD2_CONTROL 0x6030
1349#define DC_HPD3_CONTROL 0x603c
1350#define DC_HPD4_CONTROL 0x6048
1351#define DC_HPD5_CONTROL 0x6054
1352#define DC_HPD6_CONTROL 0x6060
1353# define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0)
1354# define DC_HPDx_RX_INT_TIMER(x) ((x) << 16)
1355# define DC_HPDx_EN (1 << 28)
1356
1357/* DCE4/5/6 FMT blocks */
1358#define FMT_DYNAMIC_EXP_CNTL 0x6fb4
1359# define FMT_DYNAMIC_EXP_EN (1 << 0)
1360# define FMT_DYNAMIC_EXP_MODE (1 << 4)
1361 /* 0 = 10bit -> 12bit, 1 = 8bit -> 12bit */
1362#define FMT_CONTROL 0x6fb8
1363# define FMT_PIXEL_ENCODING (1 << 16)
1364 /* 0 = RGB 4:4:4 or YCbCr 4:4:4, 1 = YCbCr 4:2:2 */
1365#define FMT_BIT_DEPTH_CONTROL 0x6fc8
1366# define FMT_TRUNCATE_EN (1 << 0)
1367# define FMT_TRUNCATE_DEPTH (1 << 4)
1368# define FMT_SPATIAL_DITHER_EN (1 << 8)
1369# define FMT_SPATIAL_DITHER_MODE(x) ((x) << 9)
1370# define FMT_SPATIAL_DITHER_DEPTH (1 << 12)
1371# define FMT_FRAME_RANDOM_ENABLE (1 << 13)
1372# define FMT_RGB_RANDOM_ENABLE (1 << 14)
1373# define FMT_HIGHPASS_RANDOM_ENABLE (1 << 15)
1374# define FMT_TEMPORAL_DITHER_EN (1 << 16)
1375# define FMT_TEMPORAL_DITHER_DEPTH (1 << 20)
1376# define FMT_TEMPORAL_DITHER_OFFSET(x) ((x) << 21)
1377# define FMT_TEMPORAL_LEVEL (1 << 24)
1378# define FMT_TEMPORAL_DITHER_RESET (1 << 25)
1379# define FMT_25FRC_SEL(x) ((x) << 26)
1380# define FMT_50FRC_SEL(x) ((x) << 28)
1381# define FMT_75FRC_SEL(x) ((x) << 30)
1382#define FMT_CLAMP_CONTROL 0x6fe4
1383# define FMT_CLAMP_DATA_EN (1 << 0)
1384# define FMT_CLAMP_COLOR_FORMAT(x) ((x) << 16)
1385# define FMT_CLAMP_6BPC 0
1386# define FMT_CLAMP_8BPC 1
1387# define FMT_CLAMP_10BPC 2
1388
1389/* ASYNC DMA */
1390#define DMA_RB_RPTR 0xd008
1391#define DMA_RB_WPTR 0xd00c
1392
1393#define DMA_CNTL 0xd02c
1394# define TRAP_ENABLE (1 << 0)
1395# define SEM_INCOMPLETE_INT_ENABLE (1 << 1)
1396# define SEM_WAIT_INT_ENABLE (1 << 2)
1397# define DATA_SWAP_ENABLE (1 << 3)
1398# define FENCE_SWAP_ENABLE (1 << 4)
1399# define CTXEMPTY_INT_ENABLE (1 << 28)
1400#define DMA_TILING_CONFIG 0xD0B8
1401
1402#define CAYMAN_DMA1_CNTL 0xd82c
1403
1404/* async DMA packets */
1405#define DMA_PACKET(cmd, sub_cmd, n) ((((cmd) & 0xF) << 28) | \
1406 (((sub_cmd) & 0xFF) << 20) |\
1407 (((n) & 0xFFFFF) << 0))
1408#define GET_DMA_CMD(h) (((h) & 0xf0000000) >> 28)
1409#define GET_DMA_COUNT(h) ((h) & 0x000fffff)
1410#define GET_DMA_SUB_CMD(h) (((h) & 0x0ff00000) >> 20)
1411
1412/* async DMA Packet types */
1413#define DMA_PACKET_WRITE 0x2
1414#define DMA_PACKET_COPY 0x3
1415#define DMA_PACKET_INDIRECT_BUFFER 0x4
1416#define DMA_PACKET_SEMAPHORE 0x5
1417#define DMA_PACKET_FENCE 0x6
1418#define DMA_PACKET_TRAP 0x7
1419#define DMA_PACKET_SRBM_WRITE 0x9
1420#define DMA_PACKET_CONSTANT_FILL 0xd
1421#define DMA_PACKET_NOP 0xf
1422
1423/* PIF PHY0 indirect regs */
1424#define PB0_PIF_CNTL 0x10
1425# define LS2_EXIT_TIME(x) ((x) << 17)
1426# define LS2_EXIT_TIME_MASK (0x7 << 17)
1427# define LS2_EXIT_TIME_SHIFT 17
1428#define PB0_PIF_PAIRING 0x11
1429# define MULTI_PIF (1 << 25)
1430#define PB0_PIF_PWRDOWN_0 0x12
1431# define PLL_POWER_STATE_IN_TXS2_0(x) ((x) << 7)
1432# define PLL_POWER_STATE_IN_TXS2_0_MASK (0x7 << 7)
1433# define PLL_POWER_STATE_IN_TXS2_0_SHIFT 7
1434# define PLL_POWER_STATE_IN_OFF_0(x) ((x) << 10)
1435# define PLL_POWER_STATE_IN_OFF_0_MASK (0x7 << 10)
1436# define PLL_POWER_STATE_IN_OFF_0_SHIFT 10
1437# define PLL_RAMP_UP_TIME_0(x) ((x) << 24)
1438# define PLL_RAMP_UP_TIME_0_MASK (0x7 << 24)
1439# define PLL_RAMP_UP_TIME_0_SHIFT 24
1440#define PB0_PIF_PWRDOWN_1 0x13
1441# define PLL_POWER_STATE_IN_TXS2_1(x) ((x) << 7)
1442# define PLL_POWER_STATE_IN_TXS2_1_MASK (0x7 << 7)
1443# define PLL_POWER_STATE_IN_TXS2_1_SHIFT 7
1444# define PLL_POWER_STATE_IN_OFF_1(x) ((x) << 10)
1445# define PLL_POWER_STATE_IN_OFF_1_MASK (0x7 << 10)
1446# define PLL_POWER_STATE_IN_OFF_1_SHIFT 10
1447# define PLL_RAMP_UP_TIME_1(x) ((x) << 24)
1448# define PLL_RAMP_UP_TIME_1_MASK (0x7 << 24)
1449# define PLL_RAMP_UP_TIME_1_SHIFT 24
1450/* PIF PHY1 indirect regs */
1451#define PB1_PIF_CNTL 0x10
1452#define PB1_PIF_PAIRING 0x11
1453#define PB1_PIF_PWRDOWN_0 0x12
1454#define PB1_PIF_PWRDOWN_1 0x13
1455/* PCIE PORT indirect regs */
1456#define PCIE_LC_CNTL 0xa0
1457# define LC_L0S_INACTIVITY(x) ((x) << 8)
1458# define LC_L0S_INACTIVITY_MASK (0xf << 8)
1459# define LC_L0S_INACTIVITY_SHIFT 8
1460# define LC_L1_INACTIVITY(x) ((x) << 12)
1461# define LC_L1_INACTIVITY_MASK (0xf << 12)
1462# define LC_L1_INACTIVITY_SHIFT 12
1463# define LC_PMI_TO_L1_DIS (1 << 16)
1464# define LC_ASPM_TO_L1_DIS (1 << 24)
1465#define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */
1466#define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */
1467# define LC_LINK_WIDTH_SHIFT 0
1468# define LC_LINK_WIDTH_MASK 0x7
1469# define LC_LINK_WIDTH_X0 0
1470# define LC_LINK_WIDTH_X1 1
1471# define LC_LINK_WIDTH_X2 2
1472# define LC_LINK_WIDTH_X4 3
1473# define LC_LINK_WIDTH_X8 4
1474# define LC_LINK_WIDTH_X16 6
1475# define LC_LINK_WIDTH_RD_SHIFT 4
1476# define LC_LINK_WIDTH_RD_MASK 0x70
1477# define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
1478# define LC_RECONFIG_NOW (1 << 8)
1479# define LC_RENEGOTIATION_SUPPORT (1 << 9)
1480# define LC_RENEGOTIATE_EN (1 << 10)
1481# define LC_SHORT_RECONFIG_EN (1 << 11)
1482# define LC_UPCONFIGURE_SUPPORT (1 << 12)
1483# define LC_UPCONFIGURE_DIS (1 << 13)
1484# define LC_DYN_LANES_PWR_STATE(x) ((x) << 21)
1485# define LC_DYN_LANES_PWR_STATE_MASK (0x3 << 21)
1486# define LC_DYN_LANES_PWR_STATE_SHIFT 21
1487#define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */
1488# define LC_GEN2_EN_STRAP (1 << 0)
1489# define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1)
1490# define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5)
1491# define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6)
1492# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8)
1493# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3
1494# define LC_CURRENT_DATA_RATE (1 << 11)
1495# define LC_HW_VOLTAGE_IF_CONTROL(x) ((x) << 12)
1496# define LC_HW_VOLTAGE_IF_CONTROL_MASK (3 << 12)
1497# define LC_HW_VOLTAGE_IF_CONTROL_SHIFT 12
1498# define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14)
1499# define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21)
1500# define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23)
1501# define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24)
1502#define MM_CFGREGS_CNTL 0x544c
1503# define MM_WR_TO_CFG_EN (1 << 3)
1504#define LINK_CNTL2 0x88 /* F0 */
1505# define TARGET_LINK_SPEED_MASK (0xf << 0)
1506# define SELECTABLE_DEEMPHASIS (1 << 6)
1507
1508
1509/*
1510 * UVD
1511 */
1512#define UVD_UDEC_ADDR_CONFIG 0xef4c
1513#define UVD_UDEC_DB_ADDR_CONFIG 0xef50
1514#define UVD_UDEC_DBW_ADDR_CONFIG 0xef54
1515#define UVD_RBC_RB_RPTR 0xf690
1516#define UVD_RBC_RB_WPTR 0xf694
1517
1518/*
1519 * PM4
1520 */
1521#define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \
1522 (((reg) >> 2) & 0xFFFF) | \
1523 ((n) & 0x3FFF) << 16)
1524#define CP_PACKET2 0x80000000
1525#define PACKET2_PAD_SHIFT 0
1526#define PACKET2_PAD_MASK (0x3fffffff << 0)
1527
1528#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
1529
1530#define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \
1531 (((op) & 0xFF) << 8) | \
1532 ((n) & 0x3FFF) << 16)
1533
1534/* Packet 3 types */
1535#define PACKET3_NOP 0x10
1536#define PACKET3_SET_BASE 0x11
1537#define PACKET3_CLEAR_STATE 0x12
1538#define PACKET3_INDEX_BUFFER_SIZE 0x13
1539#define PACKET3_DISPATCH_DIRECT 0x15
1540#define PACKET3_DISPATCH_INDIRECT 0x16
1541#define PACKET3_INDIRECT_BUFFER_END 0x17
1542#define PACKET3_MODE_CONTROL 0x18
1543#define PACKET3_SET_PREDICATION 0x20
1544#define PACKET3_REG_RMW 0x21
1545#define PACKET3_COND_EXEC 0x22
1546#define PACKET3_PRED_EXEC 0x23
1547#define PACKET3_DRAW_INDIRECT 0x24
1548#define PACKET3_DRAW_INDEX_INDIRECT 0x25
1549#define PACKET3_INDEX_BASE 0x26
1550#define PACKET3_DRAW_INDEX_2 0x27
1551#define PACKET3_CONTEXT_CONTROL 0x28
1552#define PACKET3_DRAW_INDEX_OFFSET 0x29
1553#define PACKET3_INDEX_TYPE 0x2A
1554#define PACKET3_DRAW_INDEX 0x2B
1555#define PACKET3_DRAW_INDEX_AUTO 0x2D
1556#define PACKET3_DRAW_INDEX_IMMD 0x2E
1557#define PACKET3_NUM_INSTANCES 0x2F
1558#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
1559#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
1560#define PACKET3_DRAW_INDEX_OFFSET_2 0x35
1561#define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36
1562#define PACKET3_MEM_SEMAPHORE 0x39
1563#define PACKET3_MPEG_INDEX 0x3A
1564#define PACKET3_COPY_DW 0x3B
1565#define PACKET3_WAIT_REG_MEM 0x3C
1566#define PACKET3_MEM_WRITE 0x3D
1567#define PACKET3_INDIRECT_BUFFER 0x32
1568#define PACKET3_CP_DMA 0x41
1569/* 1. header
1570 * 2. SRC_ADDR_LO or DATA [31:0]
1571 * 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] |
1572 * SRC_ADDR_HI [7:0]
1573 * 4. DST_ADDR_LO [31:0]
1574 * 5. DST_ADDR_HI [7:0]
1575 * 6. COMMAND [29:22] | BYTE_COUNT [20:0]
1576 */
1577# define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20)
1578 /* 0 - DST_ADDR
1579 * 1 - GDS
1580 */
1581# define PACKET3_CP_DMA_ENGINE(x) ((x) << 27)
1582 /* 0 - ME
1583 * 1 - PFP
1584 */
1585# define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29)
1586 /* 0 - SRC_ADDR
1587 * 1 - GDS
1588 * 2 - DATA
1589 */
1590# define PACKET3_CP_DMA_CP_SYNC (1 << 31)
1591/* COMMAND */
1592# define PACKET3_CP_DMA_DIS_WC (1 << 21)
1593# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22)
1594 /* 0 - none
1595 * 1 - 8 in 16
1596 * 2 - 8 in 32
1597 * 3 - 8 in 64
1598 */
1599# define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24)
1600 /* 0 - none
1601 * 1 - 8 in 16
1602 * 2 - 8 in 32
1603 * 3 - 8 in 64
1604 */
1605# define PACKET3_CP_DMA_CMD_SAS (1 << 26)
1606 /* 0 - memory
1607 * 1 - register
1608 */
1609# define PACKET3_CP_DMA_CMD_DAS (1 << 27)
1610 /* 0 - memory
1611 * 1 - register
1612 */
1613# define PACKET3_CP_DMA_CMD_SAIC (1 << 28)
1614# define PACKET3_CP_DMA_CMD_DAIC (1 << 29)
1615#define PACKET3_SURFACE_SYNC 0x43
1616# define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
1617# define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
1618# define PACKET3_CB2_DEST_BASE_ENA (1 << 8)
1619# define PACKET3_CB3_DEST_BASE_ENA (1 << 9)
1620# define PACKET3_CB4_DEST_BASE_ENA (1 << 10)
1621# define PACKET3_CB5_DEST_BASE_ENA (1 << 11)
1622# define PACKET3_CB6_DEST_BASE_ENA (1 << 12)
1623# define PACKET3_CB7_DEST_BASE_ENA (1 << 13)
1624# define PACKET3_DB_DEST_BASE_ENA (1 << 14)
1625# define PACKET3_CB8_DEST_BASE_ENA (1 << 15)
1626# define PACKET3_CB9_DEST_BASE_ENA (1 << 16)
1627# define PACKET3_CB10_DEST_BASE_ENA (1 << 17)
1628# define PACKET3_CB11_DEST_BASE_ENA (1 << 18)
1629# define PACKET3_FULL_CACHE_ENA (1 << 20)
1630# define PACKET3_TC_ACTION_ENA (1 << 23)
1631# define PACKET3_VC_ACTION_ENA (1 << 24)
1632# define PACKET3_CB_ACTION_ENA (1 << 25)
1633# define PACKET3_DB_ACTION_ENA (1 << 26)
1634# define PACKET3_SH_ACTION_ENA (1 << 27)
1635# define PACKET3_SX_ACTION_ENA (1 << 28)
1636#define PACKET3_ME_INITIALIZE 0x44
1637#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
1638#define PACKET3_COND_WRITE 0x45
1639#define PACKET3_EVENT_WRITE 0x46
1640#define PACKET3_EVENT_WRITE_EOP 0x47
1641#define PACKET3_EVENT_WRITE_EOS 0x48
1642#define PACKET3_PREAMBLE_CNTL 0x4A
1643# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
1644# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
1645#define PACKET3_RB_OFFSET 0x4B
1646#define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C
1647#define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D
1648#define PACKET3_ALU_PS_CONST_UPDATE 0x4E
1649#define PACKET3_ALU_VS_CONST_UPDATE 0x4F
1650#define PACKET3_ONE_REG_WRITE 0x57
1651#define PACKET3_SET_CONFIG_REG 0x68
1652#define PACKET3_SET_CONFIG_REG_START 0x00008000
1653#define PACKET3_SET_CONFIG_REG_END 0x0000ac00
1654#define PACKET3_SET_CONTEXT_REG 0x69
1655#define PACKET3_SET_CONTEXT_REG_START 0x00028000
1656#define PACKET3_SET_CONTEXT_REG_END 0x00029000
1657#define PACKET3_SET_ALU_CONST 0x6A
1658/* alu const buffers only; no reg file */
1659#define PACKET3_SET_BOOL_CONST 0x6B
1660#define PACKET3_SET_BOOL_CONST_START 0x0003a500
1661#define PACKET3_SET_BOOL_CONST_END 0x0003a518
1662#define PACKET3_SET_LOOP_CONST 0x6C
1663#define PACKET3_SET_LOOP_CONST_START 0x0003a200
1664#define PACKET3_SET_LOOP_CONST_END 0x0003a500
1665#define PACKET3_SET_RESOURCE 0x6D
1666#define PACKET3_SET_RESOURCE_START 0x00030000
1667#define PACKET3_SET_RESOURCE_END 0x00038000
1668#define PACKET3_SET_SAMPLER 0x6E
1669#define PACKET3_SET_SAMPLER_START 0x0003c000
1670#define PACKET3_SET_SAMPLER_END 0x0003c600
1671#define PACKET3_SET_CTL_CONST 0x6F
1672#define PACKET3_SET_CTL_CONST_START 0x0003cff0
1673#define PACKET3_SET_CTL_CONST_END 0x0003ff0c
1674#define PACKET3_SET_RESOURCE_OFFSET 0x70
1675#define PACKET3_SET_ALU_CONST_VS 0x71
1676#define PACKET3_SET_ALU_CONST_DI 0x72
1677#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
1678#define PACKET3_SET_RESOURCE_INDIRECT 0x74
1679#define PACKET3_SET_APPEND_CNT 0x75
1680
1681#define SQ_RESOURCE_CONSTANT_WORD7_0 0x3001c
1682#define S__SQ_CONSTANT_TYPE(x) (((x) & 3) << 30)
1683#define G__SQ_CONSTANT_TYPE(x) (((x) >> 30) & 3)
1684#define SQ_TEX_VTX_INVALID_TEXTURE 0x0
1685#define SQ_TEX_VTX_INVALID_BUFFER 0x1
1686#define SQ_TEX_VTX_VALID_TEXTURE 0x2
1687#define SQ_TEX_VTX_VALID_BUFFER 0x3
1688
1689#define VGT_VTX_VECT_EJECT_REG 0x88b0
1690
1691#define SQ_CONST_MEM_BASE 0x8df8
1692
1693#define SQ_ESGS_RING_BASE 0x8c40
1694#define SQ_ESGS_RING_SIZE 0x8c44
1695#define SQ_GSVS_RING_BASE 0x8c48
1696#define SQ_GSVS_RING_SIZE 0x8c4c
1697#define SQ_ESTMP_RING_BASE 0x8c50
1698#define SQ_ESTMP_RING_SIZE 0x8c54
1699#define SQ_GSTMP_RING_BASE 0x8c58
1700#define SQ_GSTMP_RING_SIZE 0x8c5c
1701#define SQ_VSTMP_RING_BASE 0x8c60
1702#define SQ_VSTMP_RING_SIZE 0x8c64
1703#define SQ_PSTMP_RING_BASE 0x8c68
1704#define SQ_PSTMP_RING_SIZE 0x8c6c
1705#define SQ_LSTMP_RING_BASE 0x8e10
1706#define SQ_LSTMP_RING_SIZE 0x8e14
1707#define SQ_HSTMP_RING_BASE 0x8e18
1708#define SQ_HSTMP_RING_SIZE 0x8e1c
1709#define VGT_TF_RING_SIZE 0x8988
1710
1711#define SQ_ESGS_RING_ITEMSIZE 0x28900
1712#define SQ_GSVS_RING_ITEMSIZE 0x28904
1713#define SQ_ESTMP_RING_ITEMSIZE 0x28908
1714#define SQ_GSTMP_RING_ITEMSIZE 0x2890c
1715#define SQ_VSTMP_RING_ITEMSIZE 0x28910
1716#define SQ_PSTMP_RING_ITEMSIZE 0x28914
1717#define SQ_LSTMP_RING_ITEMSIZE 0x28830
1718#define SQ_HSTMP_RING_ITEMSIZE 0x28834
1719
1720#define SQ_GS_VERT_ITEMSIZE 0x2891c
1721#define SQ_GS_VERT_ITEMSIZE_1 0x28920
1722#define SQ_GS_VERT_ITEMSIZE_2 0x28924
1723#define SQ_GS_VERT_ITEMSIZE_3 0x28928
1724#define SQ_GSVS_RING_OFFSET_1 0x2892c
1725#define SQ_GSVS_RING_OFFSET_2 0x28930
1726#define SQ_GSVS_RING_OFFSET_3 0x28934
1727
1728#define SQ_ALU_CONST_BUFFER_SIZE_PS_0 0x28140
1729#define SQ_ALU_CONST_BUFFER_SIZE_HS_0 0x28f80
1730
1731#define SQ_ALU_CONST_CACHE_PS_0 0x28940
1732#define SQ_ALU_CONST_CACHE_PS_1 0x28944
1733#define SQ_ALU_CONST_CACHE_PS_2 0x28948
1734#define SQ_ALU_CONST_CACHE_PS_3 0x2894c
1735#define SQ_ALU_CONST_CACHE_PS_4 0x28950
1736#define SQ_ALU_CONST_CACHE_PS_5 0x28954
1737#define SQ_ALU_CONST_CACHE_PS_6 0x28958
1738#define SQ_ALU_CONST_CACHE_PS_7 0x2895c
1739#define SQ_ALU_CONST_CACHE_PS_8 0x28960
1740#define SQ_ALU_CONST_CACHE_PS_9 0x28964
1741#define SQ_ALU_CONST_CACHE_PS_10 0x28968
1742#define SQ_ALU_CONST_CACHE_PS_11 0x2896c
1743#define SQ_ALU_CONST_CACHE_PS_12 0x28970
1744#define SQ_ALU_CONST_CACHE_PS_13 0x28974
1745#define SQ_ALU_CONST_CACHE_PS_14 0x28978
1746#define SQ_ALU_CONST_CACHE_PS_15 0x2897c
1747#define SQ_ALU_CONST_CACHE_VS_0 0x28980
1748#define SQ_ALU_CONST_CACHE_VS_1 0x28984
1749#define SQ_ALU_CONST_CACHE_VS_2 0x28988
1750#define SQ_ALU_CONST_CACHE_VS_3 0x2898c
1751#define SQ_ALU_CONST_CACHE_VS_4 0x28990
1752#define SQ_ALU_CONST_CACHE_VS_5 0x28994
1753#define SQ_ALU_CONST_CACHE_VS_6 0x28998
1754#define SQ_ALU_CONST_CACHE_VS_7 0x2899c
1755#define SQ_ALU_CONST_CACHE_VS_8 0x289a0
1756#define SQ_ALU_CONST_CACHE_VS_9 0x289a4
1757#define SQ_ALU_CONST_CACHE_VS_10 0x289a8
1758#define SQ_ALU_CONST_CACHE_VS_11 0x289ac
1759#define SQ_ALU_CONST_CACHE_VS_12 0x289b0
1760#define SQ_ALU_CONST_CACHE_VS_13 0x289b4
1761#define SQ_ALU_CONST_CACHE_VS_14 0x289b8
1762#define SQ_ALU_CONST_CACHE_VS_15 0x289bc
1763#define SQ_ALU_CONST_CACHE_GS_0 0x289c0
1764#define SQ_ALU_CONST_CACHE_GS_1 0x289c4
1765#define SQ_ALU_CONST_CACHE_GS_2 0x289c8
1766#define SQ_ALU_CONST_CACHE_GS_3 0x289cc
1767#define SQ_ALU_CONST_CACHE_GS_4 0x289d0
1768#define SQ_ALU_CONST_CACHE_GS_5 0x289d4
1769#define SQ_ALU_CONST_CACHE_GS_6 0x289d8
1770#define SQ_ALU_CONST_CACHE_GS_7 0x289dc
1771#define SQ_ALU_CONST_CACHE_GS_8 0x289e0
1772#define SQ_ALU_CONST_CACHE_GS_9 0x289e4
1773#define SQ_ALU_CONST_CACHE_GS_10 0x289e8
1774#define SQ_ALU_CONST_CACHE_GS_11 0x289ec
1775#define SQ_ALU_CONST_CACHE_GS_12 0x289f0
1776#define SQ_ALU_CONST_CACHE_GS_13 0x289f4
1777#define SQ_ALU_CONST_CACHE_GS_14 0x289f8
1778#define SQ_ALU_CONST_CACHE_GS_15 0x289fc
1779#define SQ_ALU_CONST_CACHE_HS_0 0x28f00
1780#define SQ_ALU_CONST_CACHE_HS_1 0x28f04
1781#define SQ_ALU_CONST_CACHE_HS_2 0x28f08
1782#define SQ_ALU_CONST_CACHE_HS_3 0x28f0c
1783#define SQ_ALU_CONST_CACHE_HS_4 0x28f10
1784#define SQ_ALU_CONST_CACHE_HS_5 0x28f14
1785#define SQ_ALU_CONST_CACHE_HS_6 0x28f18
1786#define SQ_ALU_CONST_CACHE_HS_7 0x28f1c
1787#define SQ_ALU_CONST_CACHE_HS_8 0x28f20
1788#define SQ_ALU_CONST_CACHE_HS_9 0x28f24
1789#define SQ_ALU_CONST_CACHE_HS_10 0x28f28
1790#define SQ_ALU_CONST_CACHE_HS_11 0x28f2c
1791#define SQ_ALU_CONST_CACHE_HS_12 0x28f30
1792#define SQ_ALU_CONST_CACHE_HS_13 0x28f34
1793#define SQ_ALU_CONST_CACHE_HS_14 0x28f38
1794#define SQ_ALU_CONST_CACHE_HS_15 0x28f3c
1795#define SQ_ALU_CONST_CACHE_LS_0 0x28f40
1796#define SQ_ALU_CONST_CACHE_LS_1 0x28f44
1797#define SQ_ALU_CONST_CACHE_LS_2 0x28f48
1798#define SQ_ALU_CONST_CACHE_LS_3 0x28f4c
1799#define SQ_ALU_CONST_CACHE_LS_4 0x28f50
1800#define SQ_ALU_CONST_CACHE_LS_5 0x28f54
1801#define SQ_ALU_CONST_CACHE_LS_6 0x28f58
1802#define SQ_ALU_CONST_CACHE_LS_7 0x28f5c
1803#define SQ_ALU_CONST_CACHE_LS_8 0x28f60
1804#define SQ_ALU_CONST_CACHE_LS_9 0x28f64
1805#define SQ_ALU_CONST_CACHE_LS_10 0x28f68
1806#define SQ_ALU_CONST_CACHE_LS_11 0x28f6c
1807#define SQ_ALU_CONST_CACHE_LS_12 0x28f70
1808#define SQ_ALU_CONST_CACHE_LS_13 0x28f74
1809#define SQ_ALU_CONST_CACHE_LS_14 0x28f78
1810#define SQ_ALU_CONST_CACHE_LS_15 0x28f7c
1811
1812#define PA_SC_SCREEN_SCISSOR_TL 0x28030
1813#define PA_SC_GENERIC_SCISSOR_TL 0x28240
1814#define PA_SC_WINDOW_SCISSOR_TL 0x28204
1815
1816#define VGT_PRIMITIVE_TYPE 0x8958
1817#define VGT_INDEX_TYPE 0x895C
1818
1819#define VGT_NUM_INDICES 0x8970
1820
1821#define VGT_COMPUTE_DIM_X 0x8990
1822#define VGT_COMPUTE_DIM_Y 0x8994
1823#define VGT_COMPUTE_DIM_Z 0x8998
1824#define VGT_COMPUTE_START_X 0x899C
1825#define VGT_COMPUTE_START_Y 0x89A0
1826#define VGT_COMPUTE_START_Z 0x89A4
1827#define VGT_COMPUTE_INDEX 0x89A8
1828#define VGT_COMPUTE_THREAD_GROUP_SIZE 0x89AC
1829#define VGT_HS_OFFCHIP_PARAM 0x89B0
1830
1831#define DB_DEBUG 0x9830
1832#define DB_DEBUG2 0x9834
1833#define DB_DEBUG3 0x9838
1834#define DB_DEBUG4 0x983C
1835#define DB_WATERMARKS 0x9854
1836#define DB_DEPTH_CONTROL 0x28800
1837#define R_028800_DB_DEPTH_CONTROL 0x028800
1838#define S_028800_STENCIL_ENABLE(x) (((x) & 0x1) << 0)
1839#define G_028800_STENCIL_ENABLE(x) (((x) >> 0) & 0x1)
1840#define C_028800_STENCIL_ENABLE 0xFFFFFFFE
1841#define S_028800_Z_ENABLE(x) (((x) & 0x1) << 1)
1842#define G_028800_Z_ENABLE(x) (((x) >> 1) & 0x1)
1843#define C_028800_Z_ENABLE 0xFFFFFFFD
1844#define S_028800_Z_WRITE_ENABLE(x) (((x) & 0x1) << 2)
1845#define G_028800_Z_WRITE_ENABLE(x) (((x) >> 2) & 0x1)
1846#define C_028800_Z_WRITE_ENABLE 0xFFFFFFFB
1847#define S_028800_ZFUNC(x) (((x) & 0x7) << 4)
1848#define G_028800_ZFUNC(x) (((x) >> 4) & 0x7)
1849#define C_028800_ZFUNC 0xFFFFFF8F
1850#define S_028800_BACKFACE_ENABLE(x) (((x) & 0x1) << 7)
1851#define G_028800_BACKFACE_ENABLE(x) (((x) >> 7) & 0x1)
1852#define C_028800_BACKFACE_ENABLE 0xFFFFFF7F
1853#define S_028800_STENCILFUNC(x) (((x) & 0x7) << 8)
1854#define G_028800_STENCILFUNC(x) (((x) >> 8) & 0x7)
1855#define C_028800_STENCILFUNC 0xFFFFF8FF
1856#define V_028800_STENCILFUNC_NEVER 0x00000000
1857#define V_028800_STENCILFUNC_LESS 0x00000001
1858#define V_028800_STENCILFUNC_EQUAL 0x00000002
1859#define V_028800_STENCILFUNC_LEQUAL 0x00000003
1860#define V_028800_STENCILFUNC_GREATER 0x00000004
1861#define V_028800_STENCILFUNC_NOTEQUAL 0x00000005
1862#define V_028800_STENCILFUNC_GEQUAL 0x00000006
1863#define V_028800_STENCILFUNC_ALWAYS 0x00000007
1864#define S_028800_STENCILFAIL(x) (((x) & 0x7) << 11)
1865#define G_028800_STENCILFAIL(x) (((x) >> 11) & 0x7)
1866#define C_028800_STENCILFAIL 0xFFFFC7FF
1867#define V_028800_STENCIL_KEEP 0x00000000
1868#define V_028800_STENCIL_ZERO 0x00000001
1869#define V_028800_STENCIL_REPLACE 0x00000002
1870#define V_028800_STENCIL_INCR 0x00000003
1871#define V_028800_STENCIL_DECR 0x00000004
1872#define V_028800_STENCIL_INVERT 0x00000005
1873#define V_028800_STENCIL_INCR_WRAP 0x00000006
1874#define V_028800_STENCIL_DECR_WRAP 0x00000007
1875#define S_028800_STENCILZPASS(x) (((x) & 0x7) << 14)
1876#define G_028800_STENCILZPASS(x) (((x) >> 14) & 0x7)
1877#define C_028800_STENCILZPASS 0xFFFE3FFF
1878#define S_028800_STENCILZFAIL(x) (((x) & 0x7) << 17)
1879#define G_028800_STENCILZFAIL(x) (((x) >> 17) & 0x7)
1880#define C_028800_STENCILZFAIL 0xFFF1FFFF
1881#define S_028800_STENCILFUNC_BF(x) (((x) & 0x7) << 20)
1882#define G_028800_STENCILFUNC_BF(x) (((x) >> 20) & 0x7)
1883#define C_028800_STENCILFUNC_BF 0xFF8FFFFF
1884#define S_028800_STENCILFAIL_BF(x) (((x) & 0x7) << 23)
1885#define G_028800_STENCILFAIL_BF(x) (((x) >> 23) & 0x7)
1886#define C_028800_STENCILFAIL_BF 0xFC7FFFFF
1887#define S_028800_STENCILZPASS_BF(x) (((x) & 0x7) << 26)
1888#define G_028800_STENCILZPASS_BF(x) (((x) >> 26) & 0x7)
1889#define C_028800_STENCILZPASS_BF 0xE3FFFFFF
1890#define S_028800_STENCILZFAIL_BF(x) (((x) & 0x7) << 29)
1891#define G_028800_STENCILZFAIL_BF(x) (((x) >> 29) & 0x7)
1892#define C_028800_STENCILZFAIL_BF 0x1FFFFFFF
1893#define DB_DEPTH_VIEW 0x28008
1894#define R_028008_DB_DEPTH_VIEW 0x00028008
1895#define S_028008_SLICE_START(x) (((x) & 0x7FF) << 0)
1896#define G_028008_SLICE_START(x) (((x) >> 0) & 0x7FF)
1897#define C_028008_SLICE_START 0xFFFFF800
1898#define S_028008_SLICE_MAX(x) (((x) & 0x7FF) << 13)
1899#define G_028008_SLICE_MAX(x) (((x) >> 13) & 0x7FF)
1900#define C_028008_SLICE_MAX 0xFF001FFF
1901#define DB_HTILE_DATA_BASE 0x28014
1902#define DB_HTILE_SURFACE 0x28abc
1903#define S_028ABC_HTILE_WIDTH(x) (((x) & 0x1) << 0)
1904#define G_028ABC_HTILE_WIDTH(x) (((x) >> 0) & 0x1)
1905#define C_028ABC_HTILE_WIDTH 0xFFFFFFFE
1906#define S_028ABC_HTILE_HEIGHT(x) (((x) & 0x1) << 1)
1907#define G_028ABC_HTILE_HEIGHT(x) (((x) >> 1) & 0x1)
1908#define C_028ABC_HTILE_HEIGHT 0xFFFFFFFD
1909#define G_028ABC_LINEAR(x) (((x) >> 2) & 0x1)
1910#define DB_Z_INFO 0x28040
1911# define Z_ARRAY_MODE(x) ((x) << 4)
1912# define DB_TILE_SPLIT(x) (((x) & 0x7) << 8)
1913# define DB_NUM_BANKS(x) (((x) & 0x3) << 12)
1914# define DB_BANK_WIDTH(x) (((x) & 0x3) << 16)
1915# define DB_BANK_HEIGHT(x) (((x) & 0x3) << 20)
1916# define DB_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 24)
1917#define R_028040_DB_Z_INFO 0x028040
1918#define S_028040_FORMAT(x) (((x) & 0x3) << 0)
1919#define G_028040_FORMAT(x) (((x) >> 0) & 0x3)
1920#define C_028040_FORMAT 0xFFFFFFFC
1921#define V_028040_Z_INVALID 0x00000000
1922#define V_028040_Z_16 0x00000001
1923#define V_028040_Z_24 0x00000002
1924#define V_028040_Z_32_FLOAT 0x00000003
1925#define S_028040_ARRAY_MODE(x) (((x) & 0xF) << 4)
1926#define G_028040_ARRAY_MODE(x) (((x) >> 4) & 0xF)
1927#define C_028040_ARRAY_MODE 0xFFFFFF0F
1928#define S_028040_READ_SIZE(x) (((x) & 0x1) << 28)
1929#define G_028040_READ_SIZE(x) (((x) >> 28) & 0x1)
1930#define C_028040_READ_SIZE 0xEFFFFFFF
1931#define S_028040_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 29)
1932#define G_028040_TILE_SURFACE_ENABLE(x) (((x) >> 29) & 0x1)
1933#define C_028040_TILE_SURFACE_ENABLE 0xDFFFFFFF
1934#define S_028040_ZRANGE_PRECISION(x) (((x) & 0x1) << 31)
1935#define G_028040_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1)
1936#define C_028040_ZRANGE_PRECISION 0x7FFFFFFF
1937#define S_028040_TILE_SPLIT(x) (((x) & 0x7) << 8)
1938#define G_028040_TILE_SPLIT(x) (((x) >> 8) & 0x7)
1939#define S_028040_NUM_BANKS(x) (((x) & 0x3) << 12)
1940#define G_028040_NUM_BANKS(x) (((x) >> 12) & 0x3)
1941#define S_028040_BANK_WIDTH(x) (((x) & 0x3) << 16)
1942#define G_028040_BANK_WIDTH(x) (((x) >> 16) & 0x3)
1943#define S_028040_BANK_HEIGHT(x) (((x) & 0x3) << 20)
1944#define G_028040_BANK_HEIGHT(x) (((x) >> 20) & 0x3)
1945#define S_028040_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 24)
1946#define G_028040_MACRO_TILE_ASPECT(x) (((x) >> 24) & 0x3)
1947#define DB_STENCIL_INFO 0x28044
1948#define R_028044_DB_STENCIL_INFO 0x028044
1949#define S_028044_FORMAT(x) (((x) & 0x1) << 0)
1950#define G_028044_FORMAT(x) (((x) >> 0) & 0x1)
1951#define C_028044_FORMAT 0xFFFFFFFE
1952#define V_028044_STENCIL_INVALID 0
1953#define V_028044_STENCIL_8 1
1954#define G_028044_TILE_SPLIT(x) (((x) >> 8) & 0x7)
1955#define DB_Z_READ_BASE 0x28048
1956#define DB_STENCIL_READ_BASE 0x2804c
1957#define DB_Z_WRITE_BASE 0x28050
1958#define DB_STENCIL_WRITE_BASE 0x28054
1959#define DB_DEPTH_SIZE 0x28058
1960#define R_028058_DB_DEPTH_SIZE 0x028058
1961#define S_028058_PITCH_TILE_MAX(x) (((x) & 0x7FF) << 0)
1962#define G_028058_PITCH_TILE_MAX(x) (((x) >> 0) & 0x7FF)
1963#define C_028058_PITCH_TILE_MAX 0xFFFFF800
1964#define S_028058_HEIGHT_TILE_MAX(x) (((x) & 0x7FF) << 11)
1965#define G_028058_HEIGHT_TILE_MAX(x) (((x) >> 11) & 0x7FF)
1966#define C_028058_HEIGHT_TILE_MAX 0xFFC007FF
1967#define R_02805C_DB_DEPTH_SLICE 0x02805C
1968#define S_02805C_SLICE_TILE_MAX(x) (((x) & 0x3FFFFF) << 0)
1969#define G_02805C_SLICE_TILE_MAX(x) (((x) >> 0) & 0x3FFFFF)
1970#define C_02805C_SLICE_TILE_MAX 0xFFC00000
1971
1972#define SQ_PGM_START_PS 0x28840
1973#define SQ_PGM_START_VS 0x2885c
1974#define SQ_PGM_START_GS 0x28874
1975#define SQ_PGM_START_ES 0x2888c
1976#define SQ_PGM_START_FS 0x288a4
1977#define SQ_PGM_START_HS 0x288b8
1978#define SQ_PGM_START_LS 0x288d0
1979
1980#define VGT_STRMOUT_BUFFER_BASE_0 0x28AD8
1981#define VGT_STRMOUT_BUFFER_BASE_1 0x28AE8
1982#define VGT_STRMOUT_BUFFER_BASE_2 0x28AF8
1983#define VGT_STRMOUT_BUFFER_BASE_3 0x28B08
1984#define VGT_STRMOUT_BUFFER_SIZE_0 0x28AD0
1985#define VGT_STRMOUT_BUFFER_SIZE_1 0x28AE0
1986#define VGT_STRMOUT_BUFFER_SIZE_2 0x28AF0
1987#define VGT_STRMOUT_BUFFER_SIZE_3 0x28B00
1988#define VGT_STRMOUT_CONFIG 0x28b94
1989#define VGT_STRMOUT_BUFFER_CONFIG 0x28b98
1990
1991#define CB_TARGET_MASK 0x28238
1992#define CB_SHADER_MASK 0x2823c
1993
1994#define GDS_ADDR_BASE 0x28720
1995
1996#define CB_IMMED0_BASE 0x28b9c
1997#define CB_IMMED1_BASE 0x28ba0
1998#define CB_IMMED2_BASE 0x28ba4
1999#define CB_IMMED3_BASE 0x28ba8
2000#define CB_IMMED4_BASE 0x28bac
2001#define CB_IMMED5_BASE 0x28bb0
2002#define CB_IMMED6_BASE 0x28bb4
2003#define CB_IMMED7_BASE 0x28bb8
2004#define CB_IMMED8_BASE 0x28bbc
2005#define CB_IMMED9_BASE 0x28bc0
2006#define CB_IMMED10_BASE 0x28bc4
2007#define CB_IMMED11_BASE 0x28bc8
2008
2009/* all 12 CB blocks have these regs */
2010#define CB_COLOR0_BASE 0x28c60
2011#define CB_COLOR0_PITCH 0x28c64
2012#define CB_COLOR0_SLICE 0x28c68
2013#define CB_COLOR0_VIEW 0x28c6c
2014#define R_028C6C_CB_COLOR0_VIEW 0x00028C6C
2015#define S_028C6C_SLICE_START(x) (((x) & 0x7FF) << 0)
2016#define G_028C6C_SLICE_START(x) (((x) >> 0) & 0x7FF)
2017#define C_028C6C_SLICE_START 0xFFFFF800
2018#define S_028C6C_SLICE_MAX(x) (((x) & 0x7FF) << 13)
2019#define G_028C6C_SLICE_MAX(x) (((x) >> 13) & 0x7FF)
2020#define C_028C6C_SLICE_MAX 0xFF001FFF
2021#define R_028C70_CB_COLOR0_INFO 0x028C70
2022#define S_028C70_ENDIAN(x) (((x) & 0x3) << 0)
2023#define G_028C70_ENDIAN(x) (((x) >> 0) & 0x3)
2024#define C_028C70_ENDIAN 0xFFFFFFFC
2025#define S_028C70_FORMAT(x) (((x) & 0x3F) << 2)
2026#define G_028C70_FORMAT(x) (((x) >> 2) & 0x3F)
2027#define C_028C70_FORMAT 0xFFFFFF03
2028#define V_028C70_COLOR_INVALID 0x00000000
2029#define V_028C70_COLOR_8 0x00000001
2030#define V_028C70_COLOR_4_4 0x00000002
2031#define V_028C70_COLOR_3_3_2 0x00000003
2032#define V_028C70_COLOR_16 0x00000005
2033#define V_028C70_COLOR_16_FLOAT 0x00000006
2034#define V_028C70_COLOR_8_8 0x00000007
2035#define V_028C70_COLOR_5_6_5 0x00000008
2036#define V_028C70_COLOR_6_5_5 0x00000009
2037#define V_028C70_COLOR_1_5_5_5 0x0000000A
2038#define V_028C70_COLOR_4_4_4_4 0x0000000B
2039#define V_028C70_COLOR_5_5_5_1 0x0000000C
2040#define V_028C70_COLOR_32 0x0000000D
2041#define V_028C70_COLOR_32_FLOAT 0x0000000E
2042#define V_028C70_COLOR_16_16 0x0000000F
2043#define V_028C70_COLOR_16_16_FLOAT 0x00000010
2044#define V_028C70_COLOR_8_24 0x00000011
2045#define V_028C70_COLOR_8_24_FLOAT 0x00000012
2046#define V_028C70_COLOR_24_8 0x00000013
2047#define V_028C70_COLOR_24_8_FLOAT 0x00000014
2048#define V_028C70_COLOR_10_11_11 0x00000015
2049#define V_028C70_COLOR_10_11_11_FLOAT 0x00000016
2050#define V_028C70_COLOR_11_11_10 0x00000017
2051#define V_028C70_COLOR_11_11_10_FLOAT 0x00000018
2052#define V_028C70_COLOR_2_10_10_10 0x00000019
2053#define V_028C70_COLOR_8_8_8_8 0x0000001A
2054#define V_028C70_COLOR_10_10_10_2 0x0000001B
2055#define V_028C70_COLOR_X24_8_32_FLOAT 0x0000001C
2056#define V_028C70_COLOR_32_32 0x0000001D
2057#define V_028C70_COLOR_32_32_FLOAT 0x0000001E
2058#define V_028C70_COLOR_16_16_16_16 0x0000001F
2059#define V_028C70_COLOR_16_16_16_16_FLOAT 0x00000020
2060#define V_028C70_COLOR_32_32_32_32 0x00000022
2061#define V_028C70_COLOR_32_32_32_32_FLOAT 0x00000023
2062#define V_028C70_COLOR_32_32_32_FLOAT 0x00000030
2063#define S_028C70_ARRAY_MODE(x) (((x) & 0xF) << 8)
2064#define G_028C70_ARRAY_MODE(x) (((x) >> 8) & 0xF)
2065#define C_028C70_ARRAY_MODE 0xFFFFF0FF
2066#define V_028C70_ARRAY_LINEAR_GENERAL 0x00000000
2067#define V_028C70_ARRAY_LINEAR_ALIGNED 0x00000001
2068#define V_028C70_ARRAY_1D_TILED_THIN1 0x00000002
2069#define V_028C70_ARRAY_2D_TILED_THIN1 0x00000004
2070#define S_028C70_NUMBER_TYPE(x) (((x) & 0x7) << 12)
2071#define G_028C70_NUMBER_TYPE(x) (((x) >> 12) & 0x7)
2072#define C_028C70_NUMBER_TYPE 0xFFFF8FFF
2073#define V_028C70_NUMBER_UNORM 0x00000000
2074#define V_028C70_NUMBER_SNORM 0x00000001
2075#define V_028C70_NUMBER_USCALED 0x00000002
2076#define V_028C70_NUMBER_SSCALED 0x00000003
2077#define V_028C70_NUMBER_UINT 0x00000004
2078#define V_028C70_NUMBER_SINT 0x00000005
2079#define V_028C70_NUMBER_SRGB 0x00000006
2080#define V_028C70_NUMBER_FLOAT 0x00000007
2081#define S_028C70_COMP_SWAP(x) (((x) & 0x3) << 15)
2082#define G_028C70_COMP_SWAP(x) (((x) >> 15) & 0x3)
2083#define C_028C70_COMP_SWAP 0xFFFE7FFF
2084#define V_028C70_SWAP_STD 0x00000000
2085#define V_028C70_SWAP_ALT 0x00000001
2086#define V_028C70_SWAP_STD_REV 0x00000002
2087#define V_028C70_SWAP_ALT_REV 0x00000003
2088#define S_028C70_FAST_CLEAR(x) (((x) & 0x1) << 17)
2089#define G_028C70_FAST_CLEAR(x) (((x) >> 17) & 0x1)
2090#define C_028C70_FAST_CLEAR 0xFFFDFFFF
2091#define S_028C70_COMPRESSION(x) (((x) & 0x3) << 18)
2092#define G_028C70_COMPRESSION(x) (((x) >> 18) & 0x3)
2093#define C_028C70_COMPRESSION 0xFFF3FFFF
2094#define S_028C70_BLEND_CLAMP(x) (((x) & 0x1) << 19)
2095#define G_028C70_BLEND_CLAMP(x) (((x) >> 19) & 0x1)
2096#define C_028C70_BLEND_CLAMP 0xFFF7FFFF
2097#define S_028C70_BLEND_BYPASS(x) (((x) & 0x1) << 20)
2098#define G_028C70_BLEND_BYPASS(x) (((x) >> 20) & 0x1)
2099#define C_028C70_BLEND_BYPASS 0xFFEFFFFF
2100#define S_028C70_SIMPLE_FLOAT(x) (((x) & 0x1) << 21)
2101#define G_028C70_SIMPLE_FLOAT(x) (((x) >> 21) & 0x1)
2102#define C_028C70_SIMPLE_FLOAT 0xFFDFFFFF
2103#define S_028C70_ROUND_MODE(x) (((x) & 0x1) << 22)
2104#define G_028C70_ROUND_MODE(x) (((x) >> 22) & 0x1)
2105#define C_028C70_ROUND_MODE 0xFFBFFFFF
2106#define S_028C70_TILE_COMPACT(x) (((x) & 0x1) << 23)
2107#define G_028C70_TILE_COMPACT(x) (((x) >> 23) & 0x1)
2108#define C_028C70_TILE_COMPACT 0xFF7FFFFF
2109#define S_028C70_SOURCE_FORMAT(x) (((x) & 0x3) << 24)
2110#define G_028C70_SOURCE_FORMAT(x) (((x) >> 24) & 0x3)
2111#define C_028C70_SOURCE_FORMAT 0xFCFFFFFF
2112#define V_028C70_EXPORT_4C_32BPC 0x0
2113#define V_028C70_EXPORT_4C_16BPC 0x1
2114#define V_028C70_EXPORT_2C_32BPC 0x2 /* Do not use */
2115#define S_028C70_RAT(x) (((x) & 0x1) << 26)
2116#define G_028C70_RAT(x) (((x) >> 26) & 0x1)
2117#define C_028C70_RAT 0xFBFFFFFF
2118#define S_028C70_RESOURCE_TYPE(x) (((x) & 0x7) << 27)
2119#define G_028C70_RESOURCE_TYPE(x) (((x) >> 27) & 0x7)
2120#define C_028C70_RESOURCE_TYPE 0xC7FFFFFF
2121
2122#define CB_COLOR0_INFO 0x28c70
2123# define CB_FORMAT(x) ((x) << 2)
2124# define CB_ARRAY_MODE(x) ((x) << 8)
2125# define ARRAY_LINEAR_GENERAL 0
2126# define ARRAY_LINEAR_ALIGNED 1
2127# define ARRAY_1D_TILED_THIN1 2
2128# define ARRAY_2D_TILED_THIN1 4
2129# define CB_SOURCE_FORMAT(x) ((x) << 24)
2130# define CB_SF_EXPORT_FULL 0
2131# define CB_SF_EXPORT_NORM 1
2132#define R_028C74_CB_COLOR0_ATTRIB 0x028C74
2133#define S_028C74_NON_DISP_TILING_ORDER(x) (((x) & 0x1) << 4)
2134#define G_028C74_NON_DISP_TILING_ORDER(x) (((x) >> 4) & 0x1)
2135#define C_028C74_NON_DISP_TILING_ORDER 0xFFFFFFEF
2136#define S_028C74_TILE_SPLIT(x) (((x) & 0xf) << 5)
2137#define G_028C74_TILE_SPLIT(x) (((x) >> 5) & 0xf)
2138#define S_028C74_NUM_BANKS(x) (((x) & 0x3) << 10)
2139#define G_028C74_NUM_BANKS(x) (((x) >> 10) & 0x3)
2140#define S_028C74_BANK_WIDTH(x) (((x) & 0x3) << 13)
2141#define G_028C74_BANK_WIDTH(x) (((x) >> 13) & 0x3)
2142#define S_028C74_BANK_HEIGHT(x) (((x) & 0x3) << 16)
2143#define G_028C74_BANK_HEIGHT(x) (((x) >> 16) & 0x3)
2144#define S_028C74_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 19)
2145#define G_028C74_MACRO_TILE_ASPECT(x) (((x) >> 19) & 0x3)
2146#define CB_COLOR0_ATTRIB 0x28c74
2147# define CB_TILE_SPLIT(x) (((x) & 0x7) << 5)
2148# define ADDR_SURF_TILE_SPLIT_64B 0
2149# define ADDR_SURF_TILE_SPLIT_128B 1
2150# define ADDR_SURF_TILE_SPLIT_256B 2
2151# define ADDR_SURF_TILE_SPLIT_512B 3
2152# define ADDR_SURF_TILE_SPLIT_1KB 4
2153# define ADDR_SURF_TILE_SPLIT_2KB 5
2154# define ADDR_SURF_TILE_SPLIT_4KB 6
2155# define CB_NUM_BANKS(x) (((x) & 0x3) << 10)
2156# define ADDR_SURF_2_BANK 0
2157# define ADDR_SURF_4_BANK 1
2158# define ADDR_SURF_8_BANK 2
2159# define ADDR_SURF_16_BANK 3
2160# define CB_BANK_WIDTH(x) (((x) & 0x3) << 13)
2161# define ADDR_SURF_BANK_WIDTH_1 0
2162# define ADDR_SURF_BANK_WIDTH_2 1
2163# define ADDR_SURF_BANK_WIDTH_4 2
2164# define ADDR_SURF_BANK_WIDTH_8 3
2165# define CB_BANK_HEIGHT(x) (((x) & 0x3) << 16)
2166# define ADDR_SURF_BANK_HEIGHT_1 0
2167# define ADDR_SURF_BANK_HEIGHT_2 1
2168# define ADDR_SURF_BANK_HEIGHT_4 2
2169# define ADDR_SURF_BANK_HEIGHT_8 3
2170# define CB_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 19)
2171#define CB_COLOR0_DIM 0x28c78
2172/* only CB0-7 blocks have these regs */
2173#define CB_COLOR0_CMASK 0x28c7c
2174#define CB_COLOR0_CMASK_SLICE 0x28c80
2175#define CB_COLOR0_FMASK 0x28c84
2176#define CB_COLOR0_FMASK_SLICE 0x28c88
2177#define CB_COLOR0_CLEAR_WORD0 0x28c8c
2178#define CB_COLOR0_CLEAR_WORD1 0x28c90
2179#define CB_COLOR0_CLEAR_WORD2 0x28c94
2180#define CB_COLOR0_CLEAR_WORD3 0x28c98
2181
2182#define CB_COLOR1_BASE 0x28c9c
2183#define CB_COLOR2_BASE 0x28cd8
2184#define CB_COLOR3_BASE 0x28d14
2185#define CB_COLOR4_BASE 0x28d50
2186#define CB_COLOR5_BASE 0x28d8c
2187#define CB_COLOR6_BASE 0x28dc8
2188#define CB_COLOR7_BASE 0x28e04
2189#define CB_COLOR8_BASE 0x28e40
2190#define CB_COLOR9_BASE 0x28e5c
2191#define CB_COLOR10_BASE 0x28e78
2192#define CB_COLOR11_BASE 0x28e94
2193
2194#define CB_COLOR1_PITCH 0x28ca0
2195#define CB_COLOR2_PITCH 0x28cdc
2196#define CB_COLOR3_PITCH 0x28d18
2197#define CB_COLOR4_PITCH 0x28d54
2198#define CB_COLOR5_PITCH 0x28d90
2199#define CB_COLOR6_PITCH 0x28dcc
2200#define CB_COLOR7_PITCH 0x28e08
2201#define CB_COLOR8_PITCH 0x28e44
2202#define CB_COLOR9_PITCH 0x28e60
2203#define CB_COLOR10_PITCH 0x28e7c
2204#define CB_COLOR11_PITCH 0x28e98
2205
2206#define CB_COLOR1_SLICE 0x28ca4
2207#define CB_COLOR2_SLICE 0x28ce0
2208#define CB_COLOR3_SLICE 0x28d1c
2209#define CB_COLOR4_SLICE 0x28d58
2210#define CB_COLOR5_SLICE 0x28d94
2211#define CB_COLOR6_SLICE 0x28dd0
2212#define CB_COLOR7_SLICE 0x28e0c
2213#define CB_COLOR8_SLICE 0x28e48
2214#define CB_COLOR9_SLICE 0x28e64
2215#define CB_COLOR10_SLICE 0x28e80
2216#define CB_COLOR11_SLICE 0x28e9c
2217
2218#define CB_COLOR1_VIEW 0x28ca8
2219#define CB_COLOR2_VIEW 0x28ce4
2220#define CB_COLOR3_VIEW 0x28d20
2221#define CB_COLOR4_VIEW 0x28d5c
2222#define CB_COLOR5_VIEW 0x28d98
2223#define CB_COLOR6_VIEW 0x28dd4
2224#define CB_COLOR7_VIEW 0x28e10
2225#define CB_COLOR8_VIEW 0x28e4c
2226#define CB_COLOR9_VIEW 0x28e68
2227#define CB_COLOR10_VIEW 0x28e84
2228#define CB_COLOR11_VIEW 0x28ea0
2229
2230#define CB_COLOR1_INFO 0x28cac
2231#define CB_COLOR2_INFO 0x28ce8
2232#define CB_COLOR3_INFO 0x28d24
2233#define CB_COLOR4_INFO 0x28d60
2234#define CB_COLOR5_INFO 0x28d9c
2235#define CB_COLOR6_INFO 0x28dd8
2236#define CB_COLOR7_INFO 0x28e14
2237#define CB_COLOR8_INFO 0x28e50
2238#define CB_COLOR9_INFO 0x28e6c
2239#define CB_COLOR10_INFO 0x28e88
2240#define CB_COLOR11_INFO 0x28ea4
2241
2242#define CB_COLOR1_ATTRIB 0x28cb0
2243#define CB_COLOR2_ATTRIB 0x28cec
2244#define CB_COLOR3_ATTRIB 0x28d28
2245#define CB_COLOR4_ATTRIB 0x28d64
2246#define CB_COLOR5_ATTRIB 0x28da0
2247#define CB_COLOR6_ATTRIB 0x28ddc
2248#define CB_COLOR7_ATTRIB 0x28e18
2249#define CB_COLOR8_ATTRIB 0x28e54
2250#define CB_COLOR9_ATTRIB 0x28e70
2251#define CB_COLOR10_ATTRIB 0x28e8c
2252#define CB_COLOR11_ATTRIB 0x28ea8
2253
2254#define CB_COLOR1_DIM 0x28cb4
2255#define CB_COLOR2_DIM 0x28cf0
2256#define CB_COLOR3_DIM 0x28d2c
2257#define CB_COLOR4_DIM 0x28d68
2258#define CB_COLOR5_DIM 0x28da4
2259#define CB_COLOR6_DIM 0x28de0
2260#define CB_COLOR7_DIM 0x28e1c
2261#define CB_COLOR8_DIM 0x28e58
2262#define CB_COLOR9_DIM 0x28e74
2263#define CB_COLOR10_DIM 0x28e90
2264#define CB_COLOR11_DIM 0x28eac
2265
2266#define CB_COLOR1_CMASK 0x28cb8
2267#define CB_COLOR2_CMASK 0x28cf4
2268#define CB_COLOR3_CMASK 0x28d30
2269#define CB_COLOR4_CMASK 0x28d6c
2270#define CB_COLOR5_CMASK 0x28da8
2271#define CB_COLOR6_CMASK 0x28de4
2272#define CB_COLOR7_CMASK 0x28e20
2273
2274#define CB_COLOR1_CMASK_SLICE 0x28cbc
2275#define CB_COLOR2_CMASK_SLICE 0x28cf8
2276#define CB_COLOR3_CMASK_SLICE 0x28d34
2277#define CB_COLOR4_CMASK_SLICE 0x28d70
2278#define CB_COLOR5_CMASK_SLICE 0x28dac
2279#define CB_COLOR6_CMASK_SLICE 0x28de8
2280#define CB_COLOR7_CMASK_SLICE 0x28e24
2281
2282#define CB_COLOR1_FMASK 0x28cc0
2283#define CB_COLOR2_FMASK 0x28cfc
2284#define CB_COLOR3_FMASK 0x28d38
2285#define CB_COLOR4_FMASK 0x28d74
2286#define CB_COLOR5_FMASK 0x28db0
2287#define CB_COLOR6_FMASK 0x28dec
2288#define CB_COLOR7_FMASK 0x28e28
2289
2290#define CB_COLOR1_FMASK_SLICE 0x28cc4
2291#define CB_COLOR2_FMASK_SLICE 0x28d00
2292#define CB_COLOR3_FMASK_SLICE 0x28d3c
2293#define CB_COLOR4_FMASK_SLICE 0x28d78
2294#define CB_COLOR5_FMASK_SLICE 0x28db4
2295#define CB_COLOR6_FMASK_SLICE 0x28df0
2296#define CB_COLOR7_FMASK_SLICE 0x28e2c
2297
2298#define CB_COLOR1_CLEAR_WORD0 0x28cc8
2299#define CB_COLOR2_CLEAR_WORD0 0x28d04
2300#define CB_COLOR3_CLEAR_WORD0 0x28d40
2301#define CB_COLOR4_CLEAR_WORD0 0x28d7c
2302#define CB_COLOR5_CLEAR_WORD0 0x28db8
2303#define CB_COLOR6_CLEAR_WORD0 0x28df4
2304#define CB_COLOR7_CLEAR_WORD0 0x28e30
2305
2306#define CB_COLOR1_CLEAR_WORD1 0x28ccc
2307#define CB_COLOR2_CLEAR_WORD1 0x28d08
2308#define CB_COLOR3_CLEAR_WORD1 0x28d44
2309#define CB_COLOR4_CLEAR_WORD1 0x28d80
2310#define CB_COLOR5_CLEAR_WORD1 0x28dbc
2311#define CB_COLOR6_CLEAR_WORD1 0x28df8
2312#define CB_COLOR7_CLEAR_WORD1 0x28e34
2313
2314#define CB_COLOR1_CLEAR_WORD2 0x28cd0
2315#define CB_COLOR2_CLEAR_WORD2 0x28d0c
2316#define CB_COLOR3_CLEAR_WORD2 0x28d48
2317#define CB_COLOR4_CLEAR_WORD2 0x28d84
2318#define CB_COLOR5_CLEAR_WORD2 0x28dc0
2319#define CB_COLOR6_CLEAR_WORD2 0x28dfc
2320#define CB_COLOR7_CLEAR_WORD2 0x28e38
2321
2322#define CB_COLOR1_CLEAR_WORD3 0x28cd4
2323#define CB_COLOR2_CLEAR_WORD3 0x28d10
2324#define CB_COLOR3_CLEAR_WORD3 0x28d4c
2325#define CB_COLOR4_CLEAR_WORD3 0x28d88
2326#define CB_COLOR5_CLEAR_WORD3 0x28dc4
2327#define CB_COLOR6_CLEAR_WORD3 0x28e00
2328#define CB_COLOR7_CLEAR_WORD3 0x28e3c
2329
2330#define SQ_TEX_RESOURCE_WORD0_0 0x30000
2331# define TEX_DIM(x) ((x) << 0)
2332# define SQ_TEX_DIM_1D 0
2333# define SQ_TEX_DIM_2D 1
2334# define SQ_TEX_DIM_3D 2
2335# define SQ_TEX_DIM_CUBEMAP 3
2336# define SQ_TEX_DIM_1D_ARRAY 4
2337# define SQ_TEX_DIM_2D_ARRAY 5
2338# define SQ_TEX_DIM_2D_MSAA 6
2339# define SQ_TEX_DIM_2D_ARRAY_MSAA 7
2340#define SQ_TEX_RESOURCE_WORD1_0 0x30004
2341# define TEX_ARRAY_MODE(x) ((x) << 28)
2342#define SQ_TEX_RESOURCE_WORD2_0 0x30008
2343#define SQ_TEX_RESOURCE_WORD3_0 0x3000C
2344#define SQ_TEX_RESOURCE_WORD4_0 0x30010
2345# define TEX_DST_SEL_X(x) ((x) << 16)
2346# define TEX_DST_SEL_Y(x) ((x) << 19)
2347# define TEX_DST_SEL_Z(x) ((x) << 22)
2348# define TEX_DST_SEL_W(x) ((x) << 25)
2349# define SQ_SEL_X 0
2350# define SQ_SEL_Y 1
2351# define SQ_SEL_Z 2
2352# define SQ_SEL_W 3
2353# define SQ_SEL_0 4
2354# define SQ_SEL_1 5
2355#define SQ_TEX_RESOURCE_WORD5_0 0x30014
2356#define SQ_TEX_RESOURCE_WORD6_0 0x30018
2357# define TEX_TILE_SPLIT(x) (((x) & 0x7) << 29)
2358#define SQ_TEX_RESOURCE_WORD7_0 0x3001c
2359# define MACRO_TILE_ASPECT(x) (((x) & 0x3) << 6)
2360# define TEX_BANK_WIDTH(x) (((x) & 0x3) << 8)
2361# define TEX_BANK_HEIGHT(x) (((x) & 0x3) << 10)
2362# define TEX_NUM_BANKS(x) (((x) & 0x3) << 16)
2363#define R_030000_SQ_TEX_RESOURCE_WORD0_0 0x030000
2364#define S_030000_DIM(x) (((x) & 0x7) << 0)
2365#define G_030000_DIM(x) (((x) >> 0) & 0x7)
2366#define C_030000_DIM 0xFFFFFFF8
2367#define V_030000_SQ_TEX_DIM_1D 0x00000000
2368#define V_030000_SQ_TEX_DIM_2D 0x00000001
2369#define V_030000_SQ_TEX_DIM_3D 0x00000002
2370#define V_030000_SQ_TEX_DIM_CUBEMAP 0x00000003
2371#define V_030000_SQ_TEX_DIM_1D_ARRAY 0x00000004
2372#define V_030000_SQ_TEX_DIM_2D_ARRAY 0x00000005
2373#define V_030000_SQ_TEX_DIM_2D_MSAA 0x00000006
2374#define V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA 0x00000007
2375#define S_030000_NON_DISP_TILING_ORDER(x) (((x) & 0x1) << 5)
2376#define G_030000_NON_DISP_TILING_ORDER(x) (((x) >> 5) & 0x1)
2377#define C_030000_NON_DISP_TILING_ORDER 0xFFFFFFDF
2378#define S_030000_PITCH(x) (((x) & 0xFFF) << 6)
2379#define G_030000_PITCH(x) (((x) >> 6) & 0xFFF)
2380#define C_030000_PITCH 0xFFFC003F
2381#define S_030000_TEX_WIDTH(x) (((x) & 0x3FFF) << 18)
2382#define G_030000_TEX_WIDTH(x) (((x) >> 18) & 0x3FFF)
2383#define C_030000_TEX_WIDTH 0x0003FFFF
2384#define R_030004_SQ_TEX_RESOURCE_WORD1_0 0x030004
2385#define S_030004_TEX_HEIGHT(x) (((x) & 0x3FFF) << 0)
2386#define G_030004_TEX_HEIGHT(x) (((x) >> 0) & 0x3FFF)
2387#define C_030004_TEX_HEIGHT 0xFFFFC000
2388#define S_030004_TEX_DEPTH(x) (((x) & 0x1FFF) << 14)
2389#define G_030004_TEX_DEPTH(x) (((x) >> 14) & 0x1FFF)
2390#define C_030004_TEX_DEPTH 0xF8003FFF
2391#define S_030004_ARRAY_MODE(x) (((x) & 0xF) << 28)
2392#define G_030004_ARRAY_MODE(x) (((x) >> 28) & 0xF)
2393#define C_030004_ARRAY_MODE 0x0FFFFFFF
2394#define R_030008_SQ_TEX_RESOURCE_WORD2_0 0x030008
2395#define S_030008_BASE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0)
2396#define G_030008_BASE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF)
2397#define C_030008_BASE_ADDRESS 0x00000000
2398#define R_03000C_SQ_TEX_RESOURCE_WORD3_0 0x03000C
2399#define S_03000C_MIP_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0)
2400#define G_03000C_MIP_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF)
2401#define C_03000C_MIP_ADDRESS 0x00000000
2402#define R_030010_SQ_TEX_RESOURCE_WORD4_0 0x030010
2403#define S_030010_FORMAT_COMP_X(x) (((x) & 0x3) << 0)
2404#define G_030010_FORMAT_COMP_X(x) (((x) >> 0) & 0x3)
2405#define C_030010_FORMAT_COMP_X 0xFFFFFFFC
2406#define V_030010_SQ_FORMAT_COMP_UNSIGNED 0x00000000
2407#define V_030010_SQ_FORMAT_COMP_SIGNED 0x00000001
2408#define V_030010_SQ_FORMAT_COMP_UNSIGNED_BIASED 0x00000002
2409#define S_030010_FORMAT_COMP_Y(x) (((x) & 0x3) << 2)
2410#define G_030010_FORMAT_COMP_Y(x) (((x) >> 2) & 0x3)
2411#define C_030010_FORMAT_COMP_Y 0xFFFFFFF3
2412#define S_030010_FORMAT_COMP_Z(x) (((x) & 0x3) << 4)
2413#define G_030010_FORMAT_COMP_Z(x) (((x) >> 4) & 0x3)
2414#define C_030010_FORMAT_COMP_Z 0xFFFFFFCF
2415#define S_030010_FORMAT_COMP_W(x) (((x) & 0x3) << 6)
2416#define G_030010_FORMAT_COMP_W(x) (((x) >> 6) & 0x3)
2417#define C_030010_FORMAT_COMP_W 0xFFFFFF3F
2418#define S_030010_NUM_FORMAT_ALL(x) (((x) & 0x3) << 8)
2419#define G_030010_NUM_FORMAT_ALL(x) (((x) >> 8) & 0x3)
2420#define C_030010_NUM_FORMAT_ALL 0xFFFFFCFF
2421#define V_030010_SQ_NUM_FORMAT_NORM 0x00000000
2422#define V_030010_SQ_NUM_FORMAT_INT 0x00000001
2423#define V_030010_SQ_NUM_FORMAT_SCALED 0x00000002
2424#define S_030010_SRF_MODE_ALL(x) (((x) & 0x1) << 10)
2425#define G_030010_SRF_MODE_ALL(x) (((x) >> 10) & 0x1)
2426#define C_030010_SRF_MODE_ALL 0xFFFFFBFF
2427#define V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE 0x00000000
2428#define V_030010_SRF_MODE_NO_ZERO 0x00000001
2429#define S_030010_FORCE_DEGAMMA(x) (((x) & 0x1) << 11)
2430#define G_030010_FORCE_DEGAMMA(x) (((x) >> 11) & 0x1)
2431#define C_030010_FORCE_DEGAMMA 0xFFFFF7FF
2432#define S_030010_ENDIAN_SWAP(x) (((x) & 0x3) << 12)
2433#define G_030010_ENDIAN_SWAP(x) (((x) >> 12) & 0x3)
2434#define C_030010_ENDIAN_SWAP 0xFFFFCFFF
2435#define S_030010_DST_SEL_X(x) (((x) & 0x7) << 16)
2436#define G_030010_DST_SEL_X(x) (((x) >> 16) & 0x7)
2437#define C_030010_DST_SEL_X 0xFFF8FFFF
2438#define V_030010_SQ_SEL_X 0x00000000
2439#define V_030010_SQ_SEL_Y 0x00000001
2440#define V_030010_SQ_SEL_Z 0x00000002
2441#define V_030010_SQ_SEL_W 0x00000003
2442#define V_030010_SQ_SEL_0 0x00000004
2443#define V_030010_SQ_SEL_1 0x00000005
2444#define S_030010_DST_SEL_Y(x) (((x) & 0x7) << 19)
2445#define G_030010_DST_SEL_Y(x) (((x) >> 19) & 0x7)
2446#define C_030010_DST_SEL_Y 0xFFC7FFFF
2447#define S_030010_DST_SEL_Z(x) (((x) & 0x7) << 22)
2448#define G_030010_DST_SEL_Z(x) (((x) >> 22) & 0x7)
2449#define C_030010_DST_SEL_Z 0xFE3FFFFF
2450#define S_030010_DST_SEL_W(x) (((x) & 0x7) << 25)
2451#define G_030010_DST_SEL_W(x) (((x) >> 25) & 0x7)
2452#define C_030010_DST_SEL_W 0xF1FFFFFF
2453#define S_030010_BASE_LEVEL(x) (((x) & 0xF) << 28)
2454#define G_030010_BASE_LEVEL(x) (((x) >> 28) & 0xF)
2455#define C_030010_BASE_LEVEL 0x0FFFFFFF
2456#define R_030014_SQ_TEX_RESOURCE_WORD5_0 0x030014
2457#define S_030014_LAST_LEVEL(x) (((x) & 0xF) << 0)
2458#define G_030014_LAST_LEVEL(x) (((x) >> 0) & 0xF)
2459#define C_030014_LAST_LEVEL 0xFFFFFFF0
2460#define S_030014_BASE_ARRAY(x) (((x) & 0x1FFF) << 4)
2461#define G_030014_BASE_ARRAY(x) (((x) >> 4) & 0x1FFF)
2462#define C_030014_BASE_ARRAY 0xFFFE000F
2463#define S_030014_LAST_ARRAY(x) (((x) & 0x1FFF) << 17)
2464#define G_030014_LAST_ARRAY(x) (((x) >> 17) & 0x1FFF)
2465#define C_030014_LAST_ARRAY 0xC001FFFF
2466#define R_030018_SQ_TEX_RESOURCE_WORD6_0 0x030018
2467#define S_030018_MAX_ANISO(x) (((x) & 0x7) << 0)
2468#define G_030018_MAX_ANISO(x) (((x) >> 0) & 0x7)
2469#define C_030018_MAX_ANISO 0xFFFFFFF8
2470#define S_030018_PERF_MODULATION(x) (((x) & 0x7) << 3)
2471#define G_030018_PERF_MODULATION(x) (((x) >> 3) & 0x7)
2472#define C_030018_PERF_MODULATION 0xFFFFFFC7
2473#define S_030018_INTERLACED(x) (((x) & 0x1) << 6)
2474#define G_030018_INTERLACED(x) (((x) >> 6) & 0x1)
2475#define C_030018_INTERLACED 0xFFFFFFBF
2476#define S_030018_TILE_SPLIT(x) (((x) & 0x7) << 29)
2477#define G_030018_TILE_SPLIT(x) (((x) >> 29) & 0x7)
2478#define R_03001C_SQ_TEX_RESOURCE_WORD7_0 0x03001C
2479#define S_03001C_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 6)
2480#define G_03001C_MACRO_TILE_ASPECT(x) (((x) >> 6) & 0x3)
2481#define S_03001C_BANK_WIDTH(x) (((x) & 0x3) << 8)
2482#define G_03001C_BANK_WIDTH(x) (((x) >> 8) & 0x3)
2483#define S_03001C_BANK_HEIGHT(x) (((x) & 0x3) << 10)
2484#define G_03001C_BANK_HEIGHT(x) (((x) >> 10) & 0x3)
2485#define S_03001C_NUM_BANKS(x) (((x) & 0x3) << 16)
2486#define G_03001C_NUM_BANKS(x) (((x) >> 16) & 0x3)
2487#define S_03001C_TYPE(x) (((x) & 0x3) << 30)
2488#define G_03001C_TYPE(x) (((x) >> 30) & 0x3)
2489#define C_03001C_TYPE 0x3FFFFFFF
2490#define V_03001C_SQ_TEX_VTX_INVALID_TEXTURE 0x00000000
2491#define V_03001C_SQ_TEX_VTX_INVALID_BUFFER 0x00000001
2492#define V_03001C_SQ_TEX_VTX_VALID_TEXTURE 0x00000002
2493#define V_03001C_SQ_TEX_VTX_VALID_BUFFER 0x00000003
2494#define S_03001C_DATA_FORMAT(x) (((x) & 0x3F) << 0)
2495#define G_03001C_DATA_FORMAT(x) (((x) >> 0) & 0x3F)
2496#define C_03001C_DATA_FORMAT 0xFFFFFFC0
2497
2498#define SQ_VTX_CONSTANT_WORD0_0 0x30000
2499#define SQ_VTX_CONSTANT_WORD1_0 0x30004
2500#define SQ_VTX_CONSTANT_WORD2_0 0x30008
2501# define SQ_VTXC_BASE_ADDR_HI(x) ((x) << 0)
2502# define SQ_VTXC_STRIDE(x) ((x) << 8)
2503# define SQ_VTXC_ENDIAN_SWAP(x) ((x) << 30)
2504# define SQ_ENDIAN_NONE 0
2505# define SQ_ENDIAN_8IN16 1
2506# define SQ_ENDIAN_8IN32 2
2507#define SQ_VTX_CONSTANT_WORD3_0 0x3000C
2508# define SQ_VTCX_SEL_X(x) ((x) << 3)
2509# define SQ_VTCX_SEL_Y(x) ((x) << 6)
2510# define SQ_VTCX_SEL_Z(x) ((x) << 9)
2511# define SQ_VTCX_SEL_W(x) ((x) << 12)
2512#define SQ_VTX_CONSTANT_WORD4_0 0x30010
2513#define SQ_VTX_CONSTANT_WORD5_0 0x30014
2514#define SQ_VTX_CONSTANT_WORD6_0 0x30018
2515#define SQ_VTX_CONSTANT_WORD7_0 0x3001c
2516
2517#define TD_PS_BORDER_COLOR_INDEX 0xA400
2518#define TD_PS_BORDER_COLOR_RED 0xA404
2519#define TD_PS_BORDER_COLOR_GREEN 0xA408
2520#define TD_PS_BORDER_COLOR_BLUE 0xA40C
2521#define TD_PS_BORDER_COLOR_ALPHA 0xA410
2522#define TD_VS_BORDER_COLOR_INDEX 0xA414
2523#define TD_VS_BORDER_COLOR_RED 0xA418
2524#define TD_VS_BORDER_COLOR_GREEN 0xA41C
2525#define TD_VS_BORDER_COLOR_BLUE 0xA420
2526#define TD_VS_BORDER_COLOR_ALPHA 0xA424
2527#define TD_GS_BORDER_COLOR_INDEX 0xA428
2528#define TD_GS_BORDER_COLOR_RED 0xA42C
2529#define TD_GS_BORDER_COLOR_GREEN 0xA430
2530#define TD_GS_BORDER_COLOR_BLUE 0xA434
2531#define TD_GS_BORDER_COLOR_ALPHA 0xA438
2532#define TD_HS_BORDER_COLOR_INDEX 0xA43C
2533#define TD_HS_BORDER_COLOR_RED 0xA440
2534#define TD_HS_BORDER_COLOR_GREEN 0xA444
2535#define TD_HS_BORDER_COLOR_BLUE 0xA448
2536#define TD_HS_BORDER_COLOR_ALPHA 0xA44C
2537#define TD_LS_BORDER_COLOR_INDEX 0xA450
2538#define TD_LS_BORDER_COLOR_RED 0xA454
2539#define TD_LS_BORDER_COLOR_GREEN 0xA458
2540#define TD_LS_BORDER_COLOR_BLUE 0xA45C
2541#define TD_LS_BORDER_COLOR_ALPHA 0xA460
2542#define TD_CS_BORDER_COLOR_INDEX 0xA464
2543#define TD_CS_BORDER_COLOR_RED 0xA468
2544#define TD_CS_BORDER_COLOR_GREEN 0xA46C
2545#define TD_CS_BORDER_COLOR_BLUE 0xA470
2546#define TD_CS_BORDER_COLOR_ALPHA 0xA474
2547
2548/* cayman 3D regs */
2549#define CAYMAN_VGT_OFFCHIP_LDS_BASE 0x89B4
2550#define CAYMAN_SQ_EX_ALLOC_TABLE_SLOTS 0x8E48
2551#define CAYMAN_DB_EQAA 0x28804
2552#define CAYMAN_DB_DEPTH_INFO 0x2803C
2553#define CAYMAN_PA_SC_AA_CONFIG 0x28BE0
2554#define CAYMAN_MSAA_NUM_SAMPLES_SHIFT 0
2555#define CAYMAN_MSAA_NUM_SAMPLES_MASK 0x7
2556#define CAYMAN_SX_SCATTER_EXPORT_BASE 0x28358
2557/* cayman packet3 addition */
2558#define CAYMAN_PACKET3_DEALLOC_STATE 0x14
2559
2560/* DMA regs common on r6xx/r7xx/evergreen/ni */
2561#define DMA_RB_CNTL 0xd000
2562# define DMA_RB_ENABLE (1 << 0)
2563# define DMA_RB_SIZE(x) ((x) << 1) /* log2 */
2564# define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */
2565# define DMA_RPTR_WRITEBACK_ENABLE (1 << 12)
2566# define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */
2567# define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */
2568#define DMA_STATUS_REG 0xd034
2569# define DMA_IDLE (1 << 0)
2570
2571#endif