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1/*
2 * Copyright © 2011 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Jesse Barnes <jbarnes@virtuousgeek.org>
25 *
26 * New plane/sprite handling.
27 *
28 * The older chips had a separate interface for programming plane related
29 * registers; newer ones are much simpler and we can use the new DRM plane
30 * support.
31 */
32#include <drm/drmP.h>
33#include <drm/drm_crtc.h>
34#include <drm/drm_fourcc.h>
35#include <drm/drm_rect.h>
36#include <drm/drm_atomic.h>
37#include <drm/drm_plane_helper.h>
38#include "intel_drv.h"
39#include <drm/i915_drm.h>
40#include "i915_drv.h"
41
42static bool
43format_is_yuv(uint32_t format)
44{
45 switch (format) {
46 case DRM_FORMAT_YUYV:
47 case DRM_FORMAT_UYVY:
48 case DRM_FORMAT_VYUY:
49 case DRM_FORMAT_YVYU:
50 return true;
51 default:
52 return false;
53 }
54}
55
56static int usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
57 int usecs)
58{
59 /* paranoia */
60 if (!adjusted_mode->crtc_htotal)
61 return 1;
62
63 return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock,
64 1000 * adjusted_mode->crtc_htotal);
65}
66
67/**
68 * intel_pipe_update_start() - start update of a set of display registers
69 * @crtc: the crtc of which the registers are going to be updated
70 * @start_vbl_count: vblank counter return pointer used for error checking
71 *
72 * Mark the start of an update to pipe registers that should be updated
73 * atomically regarding vblank. If the next vblank will happens within
74 * the next 100 us, this function waits until the vblank passes.
75 *
76 * After a successful call to this function, interrupts will be disabled
77 * until a subsequent call to intel_pipe_update_end(). That is done to
78 * avoid random delays. The value written to @start_vbl_count should be
79 * supplied to intel_pipe_update_end() for error checking.
80 */
81void intel_pipe_update_start(struct intel_crtc *crtc)
82{
83 struct drm_device *dev = crtc->base.dev;
84 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
85 enum pipe pipe = crtc->pipe;
86 long timeout = msecs_to_jiffies_timeout(1);
87 int scanline, min, max, vblank_start;
88 wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
89 DEFINE_WAIT(wait);
90
91 vblank_start = adjusted_mode->crtc_vblank_start;
92 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
93 vblank_start = DIV_ROUND_UP(vblank_start, 2);
94
95 /* FIXME needs to be calibrated sensibly */
96 min = vblank_start - usecs_to_scanlines(adjusted_mode, 100);
97 max = vblank_start - 1;
98
99 local_irq_disable();
100
101 if (min <= 0 || max <= 0)
102 return;
103
104 if (WARN_ON(drm_crtc_vblank_get(&crtc->base)))
105 return;
106
107 crtc->debug.min_vbl = min;
108 crtc->debug.max_vbl = max;
109 trace_i915_pipe_update_start(crtc);
110
111 for (;;) {
112 /*
113 * prepare_to_wait() has a memory barrier, which guarantees
114 * other CPUs can see the task state update by the time we
115 * read the scanline.
116 */
117 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
118
119 scanline = intel_get_crtc_scanline(crtc);
120 if (scanline < min || scanline > max)
121 break;
122
123 if (timeout <= 0) {
124 DRM_ERROR("Potential atomic update failure on pipe %c\n",
125 pipe_name(crtc->pipe));
126 break;
127 }
128
129 local_irq_enable();
130
131 timeout = schedule_timeout(timeout);
132
133 local_irq_disable();
134 }
135
136 finish_wait(wq, &wait);
137
138 drm_crtc_vblank_put(&crtc->base);
139
140 crtc->debug.scanline_start = scanline;
141 crtc->debug.start_vbl_time = ktime_get();
142 crtc->debug.start_vbl_count =
143 dev->driver->get_vblank_counter(dev, pipe);
144
145 trace_i915_pipe_update_vblank_evaded(crtc);
146}
147
148/**
149 * intel_pipe_update_end() - end update of a set of display registers
150 * @crtc: the crtc of which the registers were updated
151 * @start_vbl_count: start vblank counter (used for error checking)
152 *
153 * Mark the end of an update started with intel_pipe_update_start(). This
154 * re-enables interrupts and verifies the update was actually completed
155 * before a vblank using the value of @start_vbl_count.
156 */
157void intel_pipe_update_end(struct intel_crtc *crtc)
158{
159 struct drm_device *dev = crtc->base.dev;
160 enum pipe pipe = crtc->pipe;
161 int scanline_end = intel_get_crtc_scanline(crtc);
162 u32 end_vbl_count = dev->driver->get_vblank_counter(dev, pipe);
163 ktime_t end_vbl_time = ktime_get();
164
165 trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end);
166
167 local_irq_enable();
168
169 if (crtc->debug.start_vbl_count &&
170 crtc->debug.start_vbl_count != end_vbl_count) {
171 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n",
172 pipe_name(pipe), crtc->debug.start_vbl_count,
173 end_vbl_count,
174 ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
175 crtc->debug.min_vbl, crtc->debug.max_vbl,
176 crtc->debug.scanline_start, scanline_end);
177 }
178}
179
180static void
181skl_update_plane(struct drm_plane *drm_plane,
182 const struct intel_crtc_state *crtc_state,
183 const struct intel_plane_state *plane_state)
184{
185 struct drm_device *dev = drm_plane->dev;
186 struct drm_i915_private *dev_priv = dev->dev_private;
187 struct intel_plane *intel_plane = to_intel_plane(drm_plane);
188 struct drm_framebuffer *fb = plane_state->base.fb;
189 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
190 const int pipe = intel_plane->pipe;
191 const int plane = intel_plane->plane + 1;
192 u32 plane_ctl, stride_div, stride;
193 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
194 u32 surf_addr;
195 u32 tile_height, plane_offset, plane_size;
196 unsigned int rotation;
197 int x_offset, y_offset;
198 int crtc_x = plane_state->dst.x1;
199 int crtc_y = plane_state->dst.y1;
200 uint32_t crtc_w = drm_rect_width(&plane_state->dst);
201 uint32_t crtc_h = drm_rect_height(&plane_state->dst);
202 uint32_t x = plane_state->src.x1 >> 16;
203 uint32_t y = plane_state->src.y1 >> 16;
204 uint32_t src_w = drm_rect_width(&plane_state->src) >> 16;
205 uint32_t src_h = drm_rect_height(&plane_state->src) >> 16;
206 const struct intel_scaler *scaler =
207 &crtc_state->scaler_state.scalers[plane_state->scaler_id];
208
209 plane_ctl = PLANE_CTL_ENABLE |
210 PLANE_CTL_PIPE_GAMMA_ENABLE |
211 PLANE_CTL_PIPE_CSC_ENABLE;
212
213 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
214 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
215
216 rotation = plane_state->base.rotation;
217 plane_ctl |= skl_plane_ctl_rotation(rotation);
218
219 stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
220 fb->pixel_format);
221
222 /* Sizes are 0 based */
223 src_w--;
224 src_h--;
225 crtc_w--;
226 crtc_h--;
227
228 if (key->flags) {
229 I915_WRITE(PLANE_KEYVAL(pipe, plane), key->min_value);
230 I915_WRITE(PLANE_KEYMAX(pipe, plane), key->max_value);
231 I915_WRITE(PLANE_KEYMSK(pipe, plane), key->channel_mask);
232 }
233
234 if (key->flags & I915_SET_COLORKEY_DESTINATION)
235 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
236 else if (key->flags & I915_SET_COLORKEY_SOURCE)
237 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
238
239 surf_addr = intel_plane_obj_offset(intel_plane, obj, 0);
240
241 if (intel_rotation_90_or_270(rotation)) {
242 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
243
244 /* stride: Surface height in tiles */
245 tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp);
246 stride = DIV_ROUND_UP(fb->height, tile_height);
247 plane_size = (src_w << 16) | src_h;
248 x_offset = stride * tile_height - y - (src_h + 1);
249 y_offset = x;
250 } else {
251 stride = fb->pitches[0] / stride_div;
252 plane_size = (src_h << 16) | src_w;
253 x_offset = x;
254 y_offset = y;
255 }
256 plane_offset = y_offset << 16 | x_offset;
257
258 I915_WRITE(PLANE_OFFSET(pipe, plane), plane_offset);
259 I915_WRITE(PLANE_STRIDE(pipe, plane), stride);
260 I915_WRITE(PLANE_SIZE(pipe, plane), plane_size);
261
262 /* program plane scaler */
263 if (plane_state->scaler_id >= 0) {
264 uint32_t ps_ctrl = 0;
265 int scaler_id = plane_state->scaler_id;
266
267 DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) = 0x%x\n", plane,
268 PS_PLANE_SEL(plane));
269 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane) | scaler->mode;
270 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
271 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
272 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
273 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id),
274 ((crtc_w + 1) << 16)|(crtc_h + 1));
275
276 I915_WRITE(PLANE_POS(pipe, plane), 0);
277 } else {
278 I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x);
279 }
280
281 I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl);
282 I915_WRITE(PLANE_SURF(pipe, plane), surf_addr);
283 POSTING_READ(PLANE_SURF(pipe, plane));
284}
285
286static void
287skl_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
288{
289 struct drm_device *dev = dplane->dev;
290 struct drm_i915_private *dev_priv = dev->dev_private;
291 struct intel_plane *intel_plane = to_intel_plane(dplane);
292 const int pipe = intel_plane->pipe;
293 const int plane = intel_plane->plane + 1;
294
295 I915_WRITE(PLANE_CTL(pipe, plane), 0);
296
297 I915_WRITE(PLANE_SURF(pipe, plane), 0);
298 POSTING_READ(PLANE_SURF(pipe, plane));
299}
300
301static void
302chv_update_csc(struct intel_plane *intel_plane, uint32_t format)
303{
304 struct drm_i915_private *dev_priv = intel_plane->base.dev->dev_private;
305 int plane = intel_plane->plane;
306
307 /* Seems RGB data bypasses the CSC always */
308 if (!format_is_yuv(format))
309 return;
310
311 /*
312 * BT.601 limited range YCbCr -> full range RGB
313 *
314 * |r| | 6537 4769 0| |cr |
315 * |g| = |-3330 4769 -1605| x |y-64|
316 * |b| | 0 4769 8263| |cb |
317 *
318 * Cb and Cr apparently come in as signed already, so no
319 * need for any offset. For Y we need to remove the offset.
320 */
321 I915_WRITE(SPCSCYGOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(-64));
322 I915_WRITE(SPCSCCBOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0));
323 I915_WRITE(SPCSCCROFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0));
324
325 I915_WRITE(SPCSCC01(plane), SPCSC_C1(4769) | SPCSC_C0(6537));
326 I915_WRITE(SPCSCC23(plane), SPCSC_C1(-3330) | SPCSC_C0(0));
327 I915_WRITE(SPCSCC45(plane), SPCSC_C1(-1605) | SPCSC_C0(4769));
328 I915_WRITE(SPCSCC67(plane), SPCSC_C1(4769) | SPCSC_C0(0));
329 I915_WRITE(SPCSCC8(plane), SPCSC_C0(8263));
330
331 I915_WRITE(SPCSCYGICLAMP(plane), SPCSC_IMAX(940) | SPCSC_IMIN(64));
332 I915_WRITE(SPCSCCBICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
333 I915_WRITE(SPCSCCRICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
334
335 I915_WRITE(SPCSCYGOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
336 I915_WRITE(SPCSCCBOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
337 I915_WRITE(SPCSCCROCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
338}
339
340static void
341vlv_update_plane(struct drm_plane *dplane,
342 const struct intel_crtc_state *crtc_state,
343 const struct intel_plane_state *plane_state)
344{
345 struct drm_device *dev = dplane->dev;
346 struct drm_i915_private *dev_priv = dev->dev_private;
347 struct intel_plane *intel_plane = to_intel_plane(dplane);
348 struct drm_framebuffer *fb = plane_state->base.fb;
349 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
350 int pipe = intel_plane->pipe;
351 int plane = intel_plane->plane;
352 u32 sprctl;
353 u32 sprsurf_offset, linear_offset;
354 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
355 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
356 int crtc_x = plane_state->dst.x1;
357 int crtc_y = plane_state->dst.y1;
358 uint32_t crtc_w = drm_rect_width(&plane_state->dst);
359 uint32_t crtc_h = drm_rect_height(&plane_state->dst);
360 uint32_t x = plane_state->src.x1 >> 16;
361 uint32_t y = plane_state->src.y1 >> 16;
362 uint32_t src_w = drm_rect_width(&plane_state->src) >> 16;
363 uint32_t src_h = drm_rect_height(&plane_state->src) >> 16;
364
365 sprctl = SP_ENABLE;
366
367 switch (fb->pixel_format) {
368 case DRM_FORMAT_YUYV:
369 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
370 break;
371 case DRM_FORMAT_YVYU:
372 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
373 break;
374 case DRM_FORMAT_UYVY:
375 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
376 break;
377 case DRM_FORMAT_VYUY:
378 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
379 break;
380 case DRM_FORMAT_RGB565:
381 sprctl |= SP_FORMAT_BGR565;
382 break;
383 case DRM_FORMAT_XRGB8888:
384 sprctl |= SP_FORMAT_BGRX8888;
385 break;
386 case DRM_FORMAT_ARGB8888:
387 sprctl |= SP_FORMAT_BGRA8888;
388 break;
389 case DRM_FORMAT_XBGR2101010:
390 sprctl |= SP_FORMAT_RGBX1010102;
391 break;
392 case DRM_FORMAT_ABGR2101010:
393 sprctl |= SP_FORMAT_RGBA1010102;
394 break;
395 case DRM_FORMAT_XBGR8888:
396 sprctl |= SP_FORMAT_RGBX8888;
397 break;
398 case DRM_FORMAT_ABGR8888:
399 sprctl |= SP_FORMAT_RGBA8888;
400 break;
401 default:
402 /*
403 * If we get here one of the upper layers failed to filter
404 * out the unsupported plane formats
405 */
406 BUG();
407 break;
408 }
409
410 /*
411 * Enable gamma to match primary/cursor plane behaviour.
412 * FIXME should be user controllable via propertiesa.
413 */
414 sprctl |= SP_GAMMA_ENABLE;
415
416 if (obj->tiling_mode != I915_TILING_NONE)
417 sprctl |= SP_TILED;
418
419 /* Sizes are 0 based */
420 src_w--;
421 src_h--;
422 crtc_w--;
423 crtc_h--;
424
425 linear_offset = y * fb->pitches[0] + x * cpp;
426 sprsurf_offset = intel_compute_tile_offset(dev_priv, &x, &y,
427 fb->modifier[0], cpp,
428 fb->pitches[0]);
429 linear_offset -= sprsurf_offset;
430
431 if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
432 sprctl |= SP_ROTATE_180;
433
434 x += src_w;
435 y += src_h;
436 linear_offset += src_h * fb->pitches[0] + src_w * cpp;
437 }
438
439 if (key->flags) {
440 I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value);
441 I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value);
442 I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask);
443 }
444
445 if (key->flags & I915_SET_COLORKEY_SOURCE)
446 sprctl |= SP_SOURCE_KEY;
447
448 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B)
449 chv_update_csc(intel_plane, fb->pixel_format);
450
451 I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
452 I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
453
454 if (obj->tiling_mode != I915_TILING_NONE)
455 I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x);
456 else
457 I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
458
459 I915_WRITE(SPCONSTALPHA(pipe, plane), 0);
460
461 I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
462 I915_WRITE(SPCNTR(pipe, plane), sprctl);
463 I915_WRITE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) +
464 sprsurf_offset);
465 POSTING_READ(SPSURF(pipe, plane));
466}
467
468static void
469vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
470{
471 struct drm_device *dev = dplane->dev;
472 struct drm_i915_private *dev_priv = dev->dev_private;
473 struct intel_plane *intel_plane = to_intel_plane(dplane);
474 int pipe = intel_plane->pipe;
475 int plane = intel_plane->plane;
476
477 I915_WRITE(SPCNTR(pipe, plane), 0);
478
479 I915_WRITE(SPSURF(pipe, plane), 0);
480 POSTING_READ(SPSURF(pipe, plane));
481}
482
483static void
484ivb_update_plane(struct drm_plane *plane,
485 const struct intel_crtc_state *crtc_state,
486 const struct intel_plane_state *plane_state)
487{
488 struct drm_device *dev = plane->dev;
489 struct drm_i915_private *dev_priv = dev->dev_private;
490 struct intel_plane *intel_plane = to_intel_plane(plane);
491 struct drm_framebuffer *fb = plane_state->base.fb;
492 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
493 enum pipe pipe = intel_plane->pipe;
494 u32 sprctl, sprscale = 0;
495 u32 sprsurf_offset, linear_offset;
496 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
497 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
498 int crtc_x = plane_state->dst.x1;
499 int crtc_y = plane_state->dst.y1;
500 uint32_t crtc_w = drm_rect_width(&plane_state->dst);
501 uint32_t crtc_h = drm_rect_height(&plane_state->dst);
502 uint32_t x = plane_state->src.x1 >> 16;
503 uint32_t y = plane_state->src.y1 >> 16;
504 uint32_t src_w = drm_rect_width(&plane_state->src) >> 16;
505 uint32_t src_h = drm_rect_height(&plane_state->src) >> 16;
506
507 sprctl = SPRITE_ENABLE;
508
509 switch (fb->pixel_format) {
510 case DRM_FORMAT_XBGR8888:
511 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
512 break;
513 case DRM_FORMAT_XRGB8888:
514 sprctl |= SPRITE_FORMAT_RGBX888;
515 break;
516 case DRM_FORMAT_YUYV:
517 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
518 break;
519 case DRM_FORMAT_YVYU:
520 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
521 break;
522 case DRM_FORMAT_UYVY:
523 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
524 break;
525 case DRM_FORMAT_VYUY:
526 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
527 break;
528 default:
529 BUG();
530 }
531
532 /*
533 * Enable gamma to match primary/cursor plane behaviour.
534 * FIXME should be user controllable via propertiesa.
535 */
536 sprctl |= SPRITE_GAMMA_ENABLE;
537
538 if (obj->tiling_mode != I915_TILING_NONE)
539 sprctl |= SPRITE_TILED;
540
541 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
542 sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE;
543 else
544 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
545
546 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
547 sprctl |= SPRITE_PIPE_CSC_ENABLE;
548
549 /* Sizes are 0 based */
550 src_w--;
551 src_h--;
552 crtc_w--;
553 crtc_h--;
554
555 if (crtc_w != src_w || crtc_h != src_h)
556 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
557
558 linear_offset = y * fb->pitches[0] + x * cpp;
559 sprsurf_offset = intel_compute_tile_offset(dev_priv, &x, &y,
560 fb->modifier[0], cpp,
561 fb->pitches[0]);
562 linear_offset -= sprsurf_offset;
563
564 if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
565 sprctl |= SPRITE_ROTATE_180;
566
567 /* HSW and BDW does this automagically in hardware */
568 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
569 x += src_w;
570 y += src_h;
571 linear_offset += src_h * fb->pitches[0] + src_w * cpp;
572 }
573 }
574
575 if (key->flags) {
576 I915_WRITE(SPRKEYVAL(pipe), key->min_value);
577 I915_WRITE(SPRKEYMAX(pipe), key->max_value);
578 I915_WRITE(SPRKEYMSK(pipe), key->channel_mask);
579 }
580
581 if (key->flags & I915_SET_COLORKEY_DESTINATION)
582 sprctl |= SPRITE_DEST_KEY;
583 else if (key->flags & I915_SET_COLORKEY_SOURCE)
584 sprctl |= SPRITE_SOURCE_KEY;
585
586 I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);
587 I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
588
589 /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
590 * register */
591 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
592 I915_WRITE(SPROFFSET(pipe), (y << 16) | x);
593 else if (obj->tiling_mode != I915_TILING_NONE)
594 I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
595 else
596 I915_WRITE(SPRLINOFF(pipe), linear_offset);
597
598 I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
599 if (intel_plane->can_scale)
600 I915_WRITE(SPRSCALE(pipe), sprscale);
601 I915_WRITE(SPRCTL(pipe), sprctl);
602 I915_WRITE(SPRSURF(pipe),
603 i915_gem_obj_ggtt_offset(obj) + sprsurf_offset);
604 POSTING_READ(SPRSURF(pipe));
605}
606
607static void
608ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
609{
610 struct drm_device *dev = plane->dev;
611 struct drm_i915_private *dev_priv = dev->dev_private;
612 struct intel_plane *intel_plane = to_intel_plane(plane);
613 int pipe = intel_plane->pipe;
614
615 I915_WRITE(SPRCTL(pipe), 0);
616 /* Can't leave the scaler enabled... */
617 if (intel_plane->can_scale)
618 I915_WRITE(SPRSCALE(pipe), 0);
619
620 I915_WRITE(SPRSURF(pipe), 0);
621 POSTING_READ(SPRSURF(pipe));
622}
623
624static void
625ilk_update_plane(struct drm_plane *plane,
626 const struct intel_crtc_state *crtc_state,
627 const struct intel_plane_state *plane_state)
628{
629 struct drm_device *dev = plane->dev;
630 struct drm_i915_private *dev_priv = dev->dev_private;
631 struct intel_plane *intel_plane = to_intel_plane(plane);
632 struct drm_framebuffer *fb = plane_state->base.fb;
633 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
634 int pipe = intel_plane->pipe;
635 u32 dvscntr, dvsscale;
636 u32 dvssurf_offset, linear_offset;
637 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
638 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
639 int crtc_x = plane_state->dst.x1;
640 int crtc_y = plane_state->dst.y1;
641 uint32_t crtc_w = drm_rect_width(&plane_state->dst);
642 uint32_t crtc_h = drm_rect_height(&plane_state->dst);
643 uint32_t x = plane_state->src.x1 >> 16;
644 uint32_t y = plane_state->src.y1 >> 16;
645 uint32_t src_w = drm_rect_width(&plane_state->src) >> 16;
646 uint32_t src_h = drm_rect_height(&plane_state->src) >> 16;
647
648 dvscntr = DVS_ENABLE;
649
650 switch (fb->pixel_format) {
651 case DRM_FORMAT_XBGR8888:
652 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
653 break;
654 case DRM_FORMAT_XRGB8888:
655 dvscntr |= DVS_FORMAT_RGBX888;
656 break;
657 case DRM_FORMAT_YUYV:
658 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
659 break;
660 case DRM_FORMAT_YVYU:
661 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
662 break;
663 case DRM_FORMAT_UYVY:
664 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
665 break;
666 case DRM_FORMAT_VYUY:
667 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
668 break;
669 default:
670 BUG();
671 }
672
673 /*
674 * Enable gamma to match primary/cursor plane behaviour.
675 * FIXME should be user controllable via propertiesa.
676 */
677 dvscntr |= DVS_GAMMA_ENABLE;
678
679 if (obj->tiling_mode != I915_TILING_NONE)
680 dvscntr |= DVS_TILED;
681
682 if (IS_GEN6(dev))
683 dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */
684
685 /* Sizes are 0 based */
686 src_w--;
687 src_h--;
688 crtc_w--;
689 crtc_h--;
690
691 dvsscale = 0;
692 if (crtc_w != src_w || crtc_h != src_h)
693 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
694
695 linear_offset = y * fb->pitches[0] + x * cpp;
696 dvssurf_offset = intel_compute_tile_offset(dev_priv, &x, &y,
697 fb->modifier[0], cpp,
698 fb->pitches[0]);
699 linear_offset -= dvssurf_offset;
700
701 if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
702 dvscntr |= DVS_ROTATE_180;
703
704 x += src_w;
705 y += src_h;
706 linear_offset += src_h * fb->pitches[0] + src_w * cpp;
707 }
708
709 if (key->flags) {
710 I915_WRITE(DVSKEYVAL(pipe), key->min_value);
711 I915_WRITE(DVSKEYMAX(pipe), key->max_value);
712 I915_WRITE(DVSKEYMSK(pipe), key->channel_mask);
713 }
714
715 if (key->flags & I915_SET_COLORKEY_DESTINATION)
716 dvscntr |= DVS_DEST_KEY;
717 else if (key->flags & I915_SET_COLORKEY_SOURCE)
718 dvscntr |= DVS_SOURCE_KEY;
719
720 I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
721 I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
722
723 if (obj->tiling_mode != I915_TILING_NONE)
724 I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);
725 else
726 I915_WRITE(DVSLINOFF(pipe), linear_offset);
727
728 I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
729 I915_WRITE(DVSSCALE(pipe), dvsscale);
730 I915_WRITE(DVSCNTR(pipe), dvscntr);
731 I915_WRITE(DVSSURF(pipe),
732 i915_gem_obj_ggtt_offset(obj) + dvssurf_offset);
733 POSTING_READ(DVSSURF(pipe));
734}
735
736static void
737ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
738{
739 struct drm_device *dev = plane->dev;
740 struct drm_i915_private *dev_priv = dev->dev_private;
741 struct intel_plane *intel_plane = to_intel_plane(plane);
742 int pipe = intel_plane->pipe;
743
744 I915_WRITE(DVSCNTR(pipe), 0);
745 /* Disable the scaler */
746 I915_WRITE(DVSSCALE(pipe), 0);
747
748 I915_WRITE(DVSSURF(pipe), 0);
749 POSTING_READ(DVSSURF(pipe));
750}
751
752static int
753intel_check_sprite_plane(struct drm_plane *plane,
754 struct intel_crtc_state *crtc_state,
755 struct intel_plane_state *state)
756{
757 struct drm_device *dev = plane->dev;
758 struct drm_crtc *crtc = state->base.crtc;
759 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
760 struct intel_plane *intel_plane = to_intel_plane(plane);
761 struct drm_framebuffer *fb = state->base.fb;
762 int crtc_x, crtc_y;
763 unsigned int crtc_w, crtc_h;
764 uint32_t src_x, src_y, src_w, src_h;
765 struct drm_rect *src = &state->src;
766 struct drm_rect *dst = &state->dst;
767 const struct drm_rect *clip = &state->clip;
768 int hscale, vscale;
769 int max_scale, min_scale;
770 bool can_scale;
771
772 if (!fb) {
773 state->visible = false;
774 return 0;
775 }
776
777 /* Don't modify another pipe's plane */
778 if (intel_plane->pipe != intel_crtc->pipe) {
779 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
780 return -EINVAL;
781 }
782
783 /* FIXME check all gen limits */
784 if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) {
785 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
786 return -EINVAL;
787 }
788
789 /* setup can_scale, min_scale, max_scale */
790 if (INTEL_INFO(dev)->gen >= 9) {
791 /* use scaler when colorkey is not required */
792 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
793 can_scale = 1;
794 min_scale = 1;
795 max_scale = skl_max_scale(intel_crtc, crtc_state);
796 } else {
797 can_scale = 0;
798 min_scale = DRM_PLANE_HELPER_NO_SCALING;
799 max_scale = DRM_PLANE_HELPER_NO_SCALING;
800 }
801 } else {
802 can_scale = intel_plane->can_scale;
803 max_scale = intel_plane->max_downscale << 16;
804 min_scale = intel_plane->can_scale ? 1 : (1 << 16);
805 }
806
807 /*
808 * FIXME the following code does a bunch of fuzzy adjustments to the
809 * coordinates and sizes. We probably need some way to decide whether
810 * more strict checking should be done instead.
811 */
812 drm_rect_rotate(src, fb->width << 16, fb->height << 16,
813 state->base.rotation);
814
815 hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale);
816 BUG_ON(hscale < 0);
817
818 vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale);
819 BUG_ON(vscale < 0);
820
821 state->visible = drm_rect_clip_scaled(src, dst, clip, hscale, vscale);
822
823 crtc_x = dst->x1;
824 crtc_y = dst->y1;
825 crtc_w = drm_rect_width(dst);
826 crtc_h = drm_rect_height(dst);
827
828 if (state->visible) {
829 /* check again in case clipping clamped the results */
830 hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
831 if (hscale < 0) {
832 DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
833 drm_rect_debug_print("src: ", src, true);
834 drm_rect_debug_print("dst: ", dst, false);
835
836 return hscale;
837 }
838
839 vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
840 if (vscale < 0) {
841 DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
842 drm_rect_debug_print("src: ", src, true);
843 drm_rect_debug_print("dst: ", dst, false);
844
845 return vscale;
846 }
847
848 /* Make the source viewport size an exact multiple of the scaling factors. */
849 drm_rect_adjust_size(src,
850 drm_rect_width(dst) * hscale - drm_rect_width(src),
851 drm_rect_height(dst) * vscale - drm_rect_height(src));
852
853 drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16,
854 state->base.rotation);
855
856 /* sanity check to make sure the src viewport wasn't enlarged */
857 WARN_ON(src->x1 < (int) state->base.src_x ||
858 src->y1 < (int) state->base.src_y ||
859 src->x2 > (int) state->base.src_x + state->base.src_w ||
860 src->y2 > (int) state->base.src_y + state->base.src_h);
861
862 /*
863 * Hardware doesn't handle subpixel coordinates.
864 * Adjust to (macro)pixel boundary, but be careful not to
865 * increase the source viewport size, because that could
866 * push the downscaling factor out of bounds.
867 */
868 src_x = src->x1 >> 16;
869 src_w = drm_rect_width(src) >> 16;
870 src_y = src->y1 >> 16;
871 src_h = drm_rect_height(src) >> 16;
872
873 if (format_is_yuv(fb->pixel_format)) {
874 src_x &= ~1;
875 src_w &= ~1;
876
877 /*
878 * Must keep src and dst the
879 * same if we can't scale.
880 */
881 if (!can_scale)
882 crtc_w &= ~1;
883
884 if (crtc_w == 0)
885 state->visible = false;
886 }
887 }
888
889 /* Check size restrictions when scaling */
890 if (state->visible && (src_w != crtc_w || src_h != crtc_h)) {
891 unsigned int width_bytes;
892 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
893
894 WARN_ON(!can_scale);
895
896 /* FIXME interlacing min height is 6 */
897
898 if (crtc_w < 3 || crtc_h < 3)
899 state->visible = false;
900
901 if (src_w < 3 || src_h < 3)
902 state->visible = false;
903
904 width_bytes = ((src_x * cpp) & 63) + src_w * cpp;
905
906 if (INTEL_INFO(dev)->gen < 9 && (src_w > 2048 || src_h > 2048 ||
907 width_bytes > 4096 || fb->pitches[0] > 4096)) {
908 DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
909 return -EINVAL;
910 }
911 }
912
913 if (state->visible) {
914 src->x1 = src_x << 16;
915 src->x2 = (src_x + src_w) << 16;
916 src->y1 = src_y << 16;
917 src->y2 = (src_y + src_h) << 16;
918 }
919
920 dst->x1 = crtc_x;
921 dst->x2 = crtc_x + crtc_w;
922 dst->y1 = crtc_y;
923 dst->y2 = crtc_y + crtc_h;
924
925 return 0;
926}
927
928int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
929 struct drm_file *file_priv)
930{
931 struct drm_intel_sprite_colorkey *set = data;
932 struct drm_plane *plane;
933 struct drm_plane_state *plane_state;
934 struct drm_atomic_state *state;
935 struct drm_modeset_acquire_ctx ctx;
936 int ret = 0;
937
938 /* Make sure we don't try to enable both src & dest simultaneously */
939 if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
940 return -EINVAL;
941
942 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
943 set->flags & I915_SET_COLORKEY_DESTINATION)
944 return -EINVAL;
945
946 plane = drm_plane_find(dev, set->plane_id);
947 if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY)
948 return -ENOENT;
949
950 drm_modeset_acquire_init(&ctx, 0);
951
952 state = drm_atomic_state_alloc(plane->dev);
953 if (!state) {
954 ret = -ENOMEM;
955 goto out;
956 }
957 state->acquire_ctx = &ctx;
958
959 while (1) {
960 plane_state = drm_atomic_get_plane_state(state, plane);
961 ret = PTR_ERR_OR_ZERO(plane_state);
962 if (!ret) {
963 to_intel_plane_state(plane_state)->ckey = *set;
964 ret = drm_atomic_commit(state);
965 }
966
967 if (ret != -EDEADLK)
968 break;
969
970 drm_atomic_state_clear(state);
971 drm_modeset_backoff(&ctx);
972 }
973
974 if (ret)
975 drm_atomic_state_free(state);
976
977out:
978 drm_modeset_drop_locks(&ctx);
979 drm_modeset_acquire_fini(&ctx);
980 return ret;
981}
982
983static const uint32_t ilk_plane_formats[] = {
984 DRM_FORMAT_XRGB8888,
985 DRM_FORMAT_YUYV,
986 DRM_FORMAT_YVYU,
987 DRM_FORMAT_UYVY,
988 DRM_FORMAT_VYUY,
989};
990
991static const uint32_t snb_plane_formats[] = {
992 DRM_FORMAT_XBGR8888,
993 DRM_FORMAT_XRGB8888,
994 DRM_FORMAT_YUYV,
995 DRM_FORMAT_YVYU,
996 DRM_FORMAT_UYVY,
997 DRM_FORMAT_VYUY,
998};
999
1000static const uint32_t vlv_plane_formats[] = {
1001 DRM_FORMAT_RGB565,
1002 DRM_FORMAT_ABGR8888,
1003 DRM_FORMAT_ARGB8888,
1004 DRM_FORMAT_XBGR8888,
1005 DRM_FORMAT_XRGB8888,
1006 DRM_FORMAT_XBGR2101010,
1007 DRM_FORMAT_ABGR2101010,
1008 DRM_FORMAT_YUYV,
1009 DRM_FORMAT_YVYU,
1010 DRM_FORMAT_UYVY,
1011 DRM_FORMAT_VYUY,
1012};
1013
1014static uint32_t skl_plane_formats[] = {
1015 DRM_FORMAT_RGB565,
1016 DRM_FORMAT_ABGR8888,
1017 DRM_FORMAT_ARGB8888,
1018 DRM_FORMAT_XBGR8888,
1019 DRM_FORMAT_XRGB8888,
1020 DRM_FORMAT_YUYV,
1021 DRM_FORMAT_YVYU,
1022 DRM_FORMAT_UYVY,
1023 DRM_FORMAT_VYUY,
1024};
1025
1026int
1027intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
1028{
1029 struct intel_plane *intel_plane;
1030 struct intel_plane_state *state;
1031 unsigned long possible_crtcs;
1032 const uint32_t *plane_formats;
1033 int num_plane_formats;
1034 int ret;
1035
1036 if (INTEL_INFO(dev)->gen < 5)
1037 return -ENODEV;
1038
1039 intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL);
1040 if (!intel_plane)
1041 return -ENOMEM;
1042
1043 state = intel_create_plane_state(&intel_plane->base);
1044 if (!state) {
1045 kfree(intel_plane);
1046 return -ENOMEM;
1047 }
1048 intel_plane->base.state = &state->base;
1049
1050 switch (INTEL_INFO(dev)->gen) {
1051 case 5:
1052 case 6:
1053 intel_plane->can_scale = true;
1054 intel_plane->max_downscale = 16;
1055 intel_plane->update_plane = ilk_update_plane;
1056 intel_plane->disable_plane = ilk_disable_plane;
1057
1058 if (IS_GEN6(dev)) {
1059 plane_formats = snb_plane_formats;
1060 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1061 } else {
1062 plane_formats = ilk_plane_formats;
1063 num_plane_formats = ARRAY_SIZE(ilk_plane_formats);
1064 }
1065 break;
1066
1067 case 7:
1068 case 8:
1069 if (IS_IVYBRIDGE(dev)) {
1070 intel_plane->can_scale = true;
1071 intel_plane->max_downscale = 2;
1072 } else {
1073 intel_plane->can_scale = false;
1074 intel_plane->max_downscale = 1;
1075 }
1076
1077 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1078 intel_plane->update_plane = vlv_update_plane;
1079 intel_plane->disable_plane = vlv_disable_plane;
1080
1081 plane_formats = vlv_plane_formats;
1082 num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
1083 } else {
1084 intel_plane->update_plane = ivb_update_plane;
1085 intel_plane->disable_plane = ivb_disable_plane;
1086
1087 plane_formats = snb_plane_formats;
1088 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1089 }
1090 break;
1091 case 9:
1092 intel_plane->can_scale = true;
1093 intel_plane->update_plane = skl_update_plane;
1094 intel_plane->disable_plane = skl_disable_plane;
1095 state->scaler_id = -1;
1096
1097 plane_formats = skl_plane_formats;
1098 num_plane_formats = ARRAY_SIZE(skl_plane_formats);
1099 break;
1100 default:
1101 kfree(intel_plane);
1102 return -ENODEV;
1103 }
1104
1105 intel_plane->pipe = pipe;
1106 intel_plane->plane = plane;
1107 intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER_SPRITE(pipe, plane);
1108 intel_plane->check_plane = intel_check_sprite_plane;
1109 possible_crtcs = (1 << pipe);
1110 ret = drm_universal_plane_init(dev, &intel_plane->base, possible_crtcs,
1111 &intel_plane_funcs,
1112 plane_formats, num_plane_formats,
1113 DRM_PLANE_TYPE_OVERLAY, NULL);
1114 if (ret) {
1115 kfree(intel_plane);
1116 goto out;
1117 }
1118
1119 intel_create_rotation_property(dev, intel_plane);
1120
1121 drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs);
1122
1123out:
1124 return ret;
1125}
1/*
2 * Copyright © 2011 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Jesse Barnes <jbarnes@virtuousgeek.org>
25 *
26 * New plane/sprite handling.
27 *
28 * The older chips had a separate interface for programming plane related
29 * registers; newer ones are much simpler and we can use the new DRM plane
30 * support.
31 */
32#include <drm/drmP.h>
33#include <drm/drm_crtc.h>
34#include <drm/drm_fourcc.h>
35#include <drm/drm_rect.h>
36#include "intel_drv.h"
37#include <drm/i915_drm.h>
38#include "i915_drv.h"
39
40static void
41vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
42 struct drm_framebuffer *fb,
43 struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
44 unsigned int crtc_w, unsigned int crtc_h,
45 uint32_t x, uint32_t y,
46 uint32_t src_w, uint32_t src_h)
47{
48 struct drm_device *dev = dplane->dev;
49 struct drm_i915_private *dev_priv = dev->dev_private;
50 struct intel_plane *intel_plane = to_intel_plane(dplane);
51 int pipe = intel_plane->pipe;
52 int plane = intel_plane->plane;
53 u32 sprctl;
54 unsigned long sprsurf_offset, linear_offset;
55 int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
56
57 sprctl = I915_READ(SPCNTR(pipe, plane));
58
59 /* Mask out pixel format bits in case we change it */
60 sprctl &= ~SP_PIXFORMAT_MASK;
61 sprctl &= ~SP_YUV_BYTE_ORDER_MASK;
62 sprctl &= ~SP_TILED;
63
64 switch (fb->pixel_format) {
65 case DRM_FORMAT_YUYV:
66 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
67 break;
68 case DRM_FORMAT_YVYU:
69 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
70 break;
71 case DRM_FORMAT_UYVY:
72 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
73 break;
74 case DRM_FORMAT_VYUY:
75 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
76 break;
77 case DRM_FORMAT_RGB565:
78 sprctl |= SP_FORMAT_BGR565;
79 break;
80 case DRM_FORMAT_XRGB8888:
81 sprctl |= SP_FORMAT_BGRX8888;
82 break;
83 case DRM_FORMAT_ARGB8888:
84 sprctl |= SP_FORMAT_BGRA8888;
85 break;
86 case DRM_FORMAT_XBGR2101010:
87 sprctl |= SP_FORMAT_RGBX1010102;
88 break;
89 case DRM_FORMAT_ABGR2101010:
90 sprctl |= SP_FORMAT_RGBA1010102;
91 break;
92 case DRM_FORMAT_XBGR8888:
93 sprctl |= SP_FORMAT_RGBX8888;
94 break;
95 case DRM_FORMAT_ABGR8888:
96 sprctl |= SP_FORMAT_RGBA8888;
97 break;
98 default:
99 /*
100 * If we get here one of the upper layers failed to filter
101 * out the unsupported plane formats
102 */
103 BUG();
104 break;
105 }
106
107 /*
108 * Enable gamma to match primary/cursor plane behaviour.
109 * FIXME should be user controllable via propertiesa.
110 */
111 sprctl |= SP_GAMMA_ENABLE;
112
113 if (obj->tiling_mode != I915_TILING_NONE)
114 sprctl |= SP_TILED;
115
116 sprctl |= SP_ENABLE;
117
118 intel_update_sprite_watermarks(dplane, crtc, src_w, pixel_size, true,
119 src_w != crtc_w || src_h != crtc_h);
120
121 /* Sizes are 0 based */
122 src_w--;
123 src_h--;
124 crtc_w--;
125 crtc_h--;
126
127 linear_offset = y * fb->pitches[0] + x * pixel_size;
128 sprsurf_offset = intel_gen4_compute_page_offset(&x, &y,
129 obj->tiling_mode,
130 pixel_size,
131 fb->pitches[0]);
132 linear_offset -= sprsurf_offset;
133
134 I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
135 I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
136
137 if (obj->tiling_mode != I915_TILING_NONE)
138 I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x);
139 else
140 I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
141
142 I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
143 I915_WRITE(SPCNTR(pipe, plane), sprctl);
144 I915_WRITE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) +
145 sprsurf_offset);
146 POSTING_READ(SPSURF(pipe, plane));
147}
148
149static void
150vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
151{
152 struct drm_device *dev = dplane->dev;
153 struct drm_i915_private *dev_priv = dev->dev_private;
154 struct intel_plane *intel_plane = to_intel_plane(dplane);
155 int pipe = intel_plane->pipe;
156 int plane = intel_plane->plane;
157
158 I915_WRITE(SPCNTR(pipe, plane), I915_READ(SPCNTR(pipe, plane)) &
159 ~SP_ENABLE);
160 /* Activate double buffered register update */
161 I915_WRITE(SPSURF(pipe, plane), 0);
162 POSTING_READ(SPSURF(pipe, plane));
163
164 intel_update_sprite_watermarks(dplane, crtc, 0, 0, false, false);
165}
166
167static int
168vlv_update_colorkey(struct drm_plane *dplane,
169 struct drm_intel_sprite_colorkey *key)
170{
171 struct drm_device *dev = dplane->dev;
172 struct drm_i915_private *dev_priv = dev->dev_private;
173 struct intel_plane *intel_plane = to_intel_plane(dplane);
174 int pipe = intel_plane->pipe;
175 int plane = intel_plane->plane;
176 u32 sprctl;
177
178 if (key->flags & I915_SET_COLORKEY_DESTINATION)
179 return -EINVAL;
180
181 I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value);
182 I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value);
183 I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask);
184
185 sprctl = I915_READ(SPCNTR(pipe, plane));
186 sprctl &= ~SP_SOURCE_KEY;
187 if (key->flags & I915_SET_COLORKEY_SOURCE)
188 sprctl |= SP_SOURCE_KEY;
189 I915_WRITE(SPCNTR(pipe, plane), sprctl);
190
191 POSTING_READ(SPKEYMSK(pipe, plane));
192
193 return 0;
194}
195
196static void
197vlv_get_colorkey(struct drm_plane *dplane,
198 struct drm_intel_sprite_colorkey *key)
199{
200 struct drm_device *dev = dplane->dev;
201 struct drm_i915_private *dev_priv = dev->dev_private;
202 struct intel_plane *intel_plane = to_intel_plane(dplane);
203 int pipe = intel_plane->pipe;
204 int plane = intel_plane->plane;
205 u32 sprctl;
206
207 key->min_value = I915_READ(SPKEYMINVAL(pipe, plane));
208 key->max_value = I915_READ(SPKEYMAXVAL(pipe, plane));
209 key->channel_mask = I915_READ(SPKEYMSK(pipe, plane));
210
211 sprctl = I915_READ(SPCNTR(pipe, plane));
212 if (sprctl & SP_SOURCE_KEY)
213 key->flags = I915_SET_COLORKEY_SOURCE;
214 else
215 key->flags = I915_SET_COLORKEY_NONE;
216}
217
218static void
219ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
220 struct drm_framebuffer *fb,
221 struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
222 unsigned int crtc_w, unsigned int crtc_h,
223 uint32_t x, uint32_t y,
224 uint32_t src_w, uint32_t src_h)
225{
226 struct drm_device *dev = plane->dev;
227 struct drm_i915_private *dev_priv = dev->dev_private;
228 struct intel_plane *intel_plane = to_intel_plane(plane);
229 int pipe = intel_plane->pipe;
230 u32 sprctl, sprscale = 0;
231 unsigned long sprsurf_offset, linear_offset;
232 int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
233
234 sprctl = I915_READ(SPRCTL(pipe));
235
236 /* Mask out pixel format bits in case we change it */
237 sprctl &= ~SPRITE_PIXFORMAT_MASK;
238 sprctl &= ~SPRITE_RGB_ORDER_RGBX;
239 sprctl &= ~SPRITE_YUV_BYTE_ORDER_MASK;
240 sprctl &= ~SPRITE_TILED;
241
242 switch (fb->pixel_format) {
243 case DRM_FORMAT_XBGR8888:
244 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
245 break;
246 case DRM_FORMAT_XRGB8888:
247 sprctl |= SPRITE_FORMAT_RGBX888;
248 break;
249 case DRM_FORMAT_YUYV:
250 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
251 break;
252 case DRM_FORMAT_YVYU:
253 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
254 break;
255 case DRM_FORMAT_UYVY:
256 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
257 break;
258 case DRM_FORMAT_VYUY:
259 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
260 break;
261 default:
262 BUG();
263 }
264
265 /*
266 * Enable gamma to match primary/cursor plane behaviour.
267 * FIXME should be user controllable via propertiesa.
268 */
269 sprctl |= SPRITE_GAMMA_ENABLE;
270
271 if (obj->tiling_mode != I915_TILING_NONE)
272 sprctl |= SPRITE_TILED;
273
274 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
275 sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE;
276 else
277 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
278
279 sprctl |= SPRITE_ENABLE;
280
281 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
282 sprctl |= SPRITE_PIPE_CSC_ENABLE;
283
284 intel_update_sprite_watermarks(plane, crtc, src_w, pixel_size, true,
285 src_w != crtc_w || src_h != crtc_h);
286
287 /* Sizes are 0 based */
288 src_w--;
289 src_h--;
290 crtc_w--;
291 crtc_h--;
292
293 if (crtc_w != src_w || crtc_h != src_h)
294 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
295
296 linear_offset = y * fb->pitches[0] + x * pixel_size;
297 sprsurf_offset =
298 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
299 pixel_size, fb->pitches[0]);
300 linear_offset -= sprsurf_offset;
301
302 I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);
303 I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
304
305 /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
306 * register */
307 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
308 I915_WRITE(SPROFFSET(pipe), (y << 16) | x);
309 else if (obj->tiling_mode != I915_TILING_NONE)
310 I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
311 else
312 I915_WRITE(SPRLINOFF(pipe), linear_offset);
313
314 I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
315 if (intel_plane->can_scale)
316 I915_WRITE(SPRSCALE(pipe), sprscale);
317 I915_WRITE(SPRCTL(pipe), sprctl);
318 I915_WRITE(SPRSURF(pipe),
319 i915_gem_obj_ggtt_offset(obj) + sprsurf_offset);
320 POSTING_READ(SPRSURF(pipe));
321}
322
323static void
324ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
325{
326 struct drm_device *dev = plane->dev;
327 struct drm_i915_private *dev_priv = dev->dev_private;
328 struct intel_plane *intel_plane = to_intel_plane(plane);
329 int pipe = intel_plane->pipe;
330
331 I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE);
332 /* Can't leave the scaler enabled... */
333 if (intel_plane->can_scale)
334 I915_WRITE(SPRSCALE(pipe), 0);
335 /* Activate double buffered register update */
336 I915_WRITE(SPRSURF(pipe), 0);
337 POSTING_READ(SPRSURF(pipe));
338
339 /*
340 * Avoid underruns when disabling the sprite.
341 * FIXME remove once watermark updates are done properly.
342 */
343 intel_wait_for_vblank(dev, pipe);
344
345 intel_update_sprite_watermarks(plane, crtc, 0, 0, false, false);
346}
347
348static int
349ivb_update_colorkey(struct drm_plane *plane,
350 struct drm_intel_sprite_colorkey *key)
351{
352 struct drm_device *dev = plane->dev;
353 struct drm_i915_private *dev_priv = dev->dev_private;
354 struct intel_plane *intel_plane;
355 u32 sprctl;
356 int ret = 0;
357
358 intel_plane = to_intel_plane(plane);
359
360 I915_WRITE(SPRKEYVAL(intel_plane->pipe), key->min_value);
361 I915_WRITE(SPRKEYMAX(intel_plane->pipe), key->max_value);
362 I915_WRITE(SPRKEYMSK(intel_plane->pipe), key->channel_mask);
363
364 sprctl = I915_READ(SPRCTL(intel_plane->pipe));
365 sprctl &= ~(SPRITE_SOURCE_KEY | SPRITE_DEST_KEY);
366 if (key->flags & I915_SET_COLORKEY_DESTINATION)
367 sprctl |= SPRITE_DEST_KEY;
368 else if (key->flags & I915_SET_COLORKEY_SOURCE)
369 sprctl |= SPRITE_SOURCE_KEY;
370 I915_WRITE(SPRCTL(intel_plane->pipe), sprctl);
371
372 POSTING_READ(SPRKEYMSK(intel_plane->pipe));
373
374 return ret;
375}
376
377static void
378ivb_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key)
379{
380 struct drm_device *dev = plane->dev;
381 struct drm_i915_private *dev_priv = dev->dev_private;
382 struct intel_plane *intel_plane;
383 u32 sprctl;
384
385 intel_plane = to_intel_plane(plane);
386
387 key->min_value = I915_READ(SPRKEYVAL(intel_plane->pipe));
388 key->max_value = I915_READ(SPRKEYMAX(intel_plane->pipe));
389 key->channel_mask = I915_READ(SPRKEYMSK(intel_plane->pipe));
390 key->flags = 0;
391
392 sprctl = I915_READ(SPRCTL(intel_plane->pipe));
393
394 if (sprctl & SPRITE_DEST_KEY)
395 key->flags = I915_SET_COLORKEY_DESTINATION;
396 else if (sprctl & SPRITE_SOURCE_KEY)
397 key->flags = I915_SET_COLORKEY_SOURCE;
398 else
399 key->flags = I915_SET_COLORKEY_NONE;
400}
401
402static void
403ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
404 struct drm_framebuffer *fb,
405 struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
406 unsigned int crtc_w, unsigned int crtc_h,
407 uint32_t x, uint32_t y,
408 uint32_t src_w, uint32_t src_h)
409{
410 struct drm_device *dev = plane->dev;
411 struct drm_i915_private *dev_priv = dev->dev_private;
412 struct intel_plane *intel_plane = to_intel_plane(plane);
413 int pipe = intel_plane->pipe;
414 unsigned long dvssurf_offset, linear_offset;
415 u32 dvscntr, dvsscale;
416 int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
417
418 dvscntr = I915_READ(DVSCNTR(pipe));
419
420 /* Mask out pixel format bits in case we change it */
421 dvscntr &= ~DVS_PIXFORMAT_MASK;
422 dvscntr &= ~DVS_RGB_ORDER_XBGR;
423 dvscntr &= ~DVS_YUV_BYTE_ORDER_MASK;
424 dvscntr &= ~DVS_TILED;
425
426 switch (fb->pixel_format) {
427 case DRM_FORMAT_XBGR8888:
428 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
429 break;
430 case DRM_FORMAT_XRGB8888:
431 dvscntr |= DVS_FORMAT_RGBX888;
432 break;
433 case DRM_FORMAT_YUYV:
434 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
435 break;
436 case DRM_FORMAT_YVYU:
437 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
438 break;
439 case DRM_FORMAT_UYVY:
440 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
441 break;
442 case DRM_FORMAT_VYUY:
443 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
444 break;
445 default:
446 BUG();
447 }
448
449 /*
450 * Enable gamma to match primary/cursor plane behaviour.
451 * FIXME should be user controllable via propertiesa.
452 */
453 dvscntr |= DVS_GAMMA_ENABLE;
454
455 if (obj->tiling_mode != I915_TILING_NONE)
456 dvscntr |= DVS_TILED;
457
458 if (IS_GEN6(dev))
459 dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */
460 dvscntr |= DVS_ENABLE;
461
462 intel_update_sprite_watermarks(plane, crtc, src_w, pixel_size, true,
463 src_w != crtc_w || src_h != crtc_h);
464
465 /* Sizes are 0 based */
466 src_w--;
467 src_h--;
468 crtc_w--;
469 crtc_h--;
470
471 dvsscale = 0;
472 if (crtc_w != src_w || crtc_h != src_h)
473 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
474
475 linear_offset = y * fb->pitches[0] + x * pixel_size;
476 dvssurf_offset =
477 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
478 pixel_size, fb->pitches[0]);
479 linear_offset -= dvssurf_offset;
480
481 I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
482 I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
483
484 if (obj->tiling_mode != I915_TILING_NONE)
485 I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);
486 else
487 I915_WRITE(DVSLINOFF(pipe), linear_offset);
488
489 I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
490 I915_WRITE(DVSSCALE(pipe), dvsscale);
491 I915_WRITE(DVSCNTR(pipe), dvscntr);
492 I915_WRITE(DVSSURF(pipe),
493 i915_gem_obj_ggtt_offset(obj) + dvssurf_offset);
494 POSTING_READ(DVSSURF(pipe));
495}
496
497static void
498ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
499{
500 struct drm_device *dev = plane->dev;
501 struct drm_i915_private *dev_priv = dev->dev_private;
502 struct intel_plane *intel_plane = to_intel_plane(plane);
503 int pipe = intel_plane->pipe;
504
505 I915_WRITE(DVSCNTR(pipe), I915_READ(DVSCNTR(pipe)) & ~DVS_ENABLE);
506 /* Disable the scaler */
507 I915_WRITE(DVSSCALE(pipe), 0);
508 /* Flush double buffered register updates */
509 I915_WRITE(DVSSURF(pipe), 0);
510 POSTING_READ(DVSSURF(pipe));
511
512 /*
513 * Avoid underruns when disabling the sprite.
514 * FIXME remove once watermark updates are done properly.
515 */
516 intel_wait_for_vblank(dev, pipe);
517
518 intel_update_sprite_watermarks(plane, crtc, 0, 0, false, false);
519}
520
521static void
522intel_enable_primary(struct drm_crtc *crtc)
523{
524 struct drm_device *dev = crtc->dev;
525 struct drm_i915_private *dev_priv = dev->dev_private;
526 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
527 int reg = DSPCNTR(intel_crtc->plane);
528
529 if (intel_crtc->primary_enabled)
530 return;
531
532 intel_crtc->primary_enabled = true;
533
534 I915_WRITE(reg, I915_READ(reg) | DISPLAY_PLANE_ENABLE);
535 intel_flush_primary_plane(dev_priv, intel_crtc->plane);
536
537 /*
538 * FIXME IPS should be fine as long as one plane is
539 * enabled, but in practice it seems to have problems
540 * when going from primary only to sprite only and vice
541 * versa.
542 */
543 if (intel_crtc->config.ips_enabled) {
544 intel_wait_for_vblank(dev, intel_crtc->pipe);
545 hsw_enable_ips(intel_crtc);
546 }
547
548 mutex_lock(&dev->struct_mutex);
549 intel_update_fbc(dev);
550 mutex_unlock(&dev->struct_mutex);
551}
552
553static void
554intel_disable_primary(struct drm_crtc *crtc)
555{
556 struct drm_device *dev = crtc->dev;
557 struct drm_i915_private *dev_priv = dev->dev_private;
558 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
559 int reg = DSPCNTR(intel_crtc->plane);
560
561 if (!intel_crtc->primary_enabled)
562 return;
563
564 intel_crtc->primary_enabled = false;
565
566 mutex_lock(&dev->struct_mutex);
567 if (dev_priv->fbc.plane == intel_crtc->plane)
568 intel_disable_fbc(dev);
569 mutex_unlock(&dev->struct_mutex);
570
571 /*
572 * FIXME IPS should be fine as long as one plane is
573 * enabled, but in practice it seems to have problems
574 * when going from primary only to sprite only and vice
575 * versa.
576 */
577 hsw_disable_ips(intel_crtc);
578
579 I915_WRITE(reg, I915_READ(reg) & ~DISPLAY_PLANE_ENABLE);
580 intel_flush_primary_plane(dev_priv, intel_crtc->plane);
581}
582
583static int
584ilk_update_colorkey(struct drm_plane *plane,
585 struct drm_intel_sprite_colorkey *key)
586{
587 struct drm_device *dev = plane->dev;
588 struct drm_i915_private *dev_priv = dev->dev_private;
589 struct intel_plane *intel_plane;
590 u32 dvscntr;
591 int ret = 0;
592
593 intel_plane = to_intel_plane(plane);
594
595 I915_WRITE(DVSKEYVAL(intel_plane->pipe), key->min_value);
596 I915_WRITE(DVSKEYMAX(intel_plane->pipe), key->max_value);
597 I915_WRITE(DVSKEYMSK(intel_plane->pipe), key->channel_mask);
598
599 dvscntr = I915_READ(DVSCNTR(intel_plane->pipe));
600 dvscntr &= ~(DVS_SOURCE_KEY | DVS_DEST_KEY);
601 if (key->flags & I915_SET_COLORKEY_DESTINATION)
602 dvscntr |= DVS_DEST_KEY;
603 else if (key->flags & I915_SET_COLORKEY_SOURCE)
604 dvscntr |= DVS_SOURCE_KEY;
605 I915_WRITE(DVSCNTR(intel_plane->pipe), dvscntr);
606
607 POSTING_READ(DVSKEYMSK(intel_plane->pipe));
608
609 return ret;
610}
611
612static void
613ilk_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key)
614{
615 struct drm_device *dev = plane->dev;
616 struct drm_i915_private *dev_priv = dev->dev_private;
617 struct intel_plane *intel_plane;
618 u32 dvscntr;
619
620 intel_plane = to_intel_plane(plane);
621
622 key->min_value = I915_READ(DVSKEYVAL(intel_plane->pipe));
623 key->max_value = I915_READ(DVSKEYMAX(intel_plane->pipe));
624 key->channel_mask = I915_READ(DVSKEYMSK(intel_plane->pipe));
625 key->flags = 0;
626
627 dvscntr = I915_READ(DVSCNTR(intel_plane->pipe));
628
629 if (dvscntr & DVS_DEST_KEY)
630 key->flags = I915_SET_COLORKEY_DESTINATION;
631 else if (dvscntr & DVS_SOURCE_KEY)
632 key->flags = I915_SET_COLORKEY_SOURCE;
633 else
634 key->flags = I915_SET_COLORKEY_NONE;
635}
636
637static bool
638format_is_yuv(uint32_t format)
639{
640 switch (format) {
641 case DRM_FORMAT_YUYV:
642 case DRM_FORMAT_UYVY:
643 case DRM_FORMAT_VYUY:
644 case DRM_FORMAT_YVYU:
645 return true;
646 default:
647 return false;
648 }
649}
650
651static bool colorkey_enabled(struct intel_plane *intel_plane)
652{
653 struct drm_intel_sprite_colorkey key;
654
655 intel_plane->get_colorkey(&intel_plane->base, &key);
656
657 return key.flags != I915_SET_COLORKEY_NONE;
658}
659
660static int
661intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
662 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
663 unsigned int crtc_w, unsigned int crtc_h,
664 uint32_t src_x, uint32_t src_y,
665 uint32_t src_w, uint32_t src_h)
666{
667 struct drm_device *dev = plane->dev;
668 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
669 struct intel_plane *intel_plane = to_intel_plane(plane);
670 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
671 struct drm_i915_gem_object *obj = intel_fb->obj;
672 struct drm_i915_gem_object *old_obj = intel_plane->obj;
673 int ret;
674 bool disable_primary = false;
675 bool visible;
676 int hscale, vscale;
677 int max_scale, min_scale;
678 int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
679 struct drm_rect src = {
680 /* sample coordinates in 16.16 fixed point */
681 .x1 = src_x,
682 .x2 = src_x + src_w,
683 .y1 = src_y,
684 .y2 = src_y + src_h,
685 };
686 struct drm_rect dst = {
687 /* integer pixels */
688 .x1 = crtc_x,
689 .x2 = crtc_x + crtc_w,
690 .y1 = crtc_y,
691 .y2 = crtc_y + crtc_h,
692 };
693 const struct drm_rect clip = {
694 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
695 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
696 };
697 const struct {
698 int crtc_x, crtc_y;
699 unsigned int crtc_w, crtc_h;
700 uint32_t src_x, src_y, src_w, src_h;
701 } orig = {
702 .crtc_x = crtc_x,
703 .crtc_y = crtc_y,
704 .crtc_w = crtc_w,
705 .crtc_h = crtc_h,
706 .src_x = src_x,
707 .src_y = src_y,
708 .src_w = src_w,
709 .src_h = src_h,
710 };
711
712 /* Don't modify another pipe's plane */
713 if (intel_plane->pipe != intel_crtc->pipe) {
714 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
715 return -EINVAL;
716 }
717
718 /* FIXME check all gen limits */
719 if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) {
720 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
721 return -EINVAL;
722 }
723
724 /* Sprite planes can be linear or x-tiled surfaces */
725 switch (obj->tiling_mode) {
726 case I915_TILING_NONE:
727 case I915_TILING_X:
728 break;
729 default:
730 DRM_DEBUG_KMS("Unsupported tiling mode\n");
731 return -EINVAL;
732 }
733
734 /*
735 * FIXME the following code does a bunch of fuzzy adjustments to the
736 * coordinates and sizes. We probably need some way to decide whether
737 * more strict checking should be done instead.
738 */
739 max_scale = intel_plane->max_downscale << 16;
740 min_scale = intel_plane->can_scale ? 1 : (1 << 16);
741
742 hscale = drm_rect_calc_hscale_relaxed(&src, &dst, min_scale, max_scale);
743 BUG_ON(hscale < 0);
744
745 vscale = drm_rect_calc_vscale_relaxed(&src, &dst, min_scale, max_scale);
746 BUG_ON(vscale < 0);
747
748 visible = drm_rect_clip_scaled(&src, &dst, &clip, hscale, vscale);
749
750 crtc_x = dst.x1;
751 crtc_y = dst.y1;
752 crtc_w = drm_rect_width(&dst);
753 crtc_h = drm_rect_height(&dst);
754
755 if (visible) {
756 /* check again in case clipping clamped the results */
757 hscale = drm_rect_calc_hscale(&src, &dst, min_scale, max_scale);
758 if (hscale < 0) {
759 DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
760 drm_rect_debug_print(&src, true);
761 drm_rect_debug_print(&dst, false);
762
763 return hscale;
764 }
765
766 vscale = drm_rect_calc_vscale(&src, &dst, min_scale, max_scale);
767 if (vscale < 0) {
768 DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
769 drm_rect_debug_print(&src, true);
770 drm_rect_debug_print(&dst, false);
771
772 return vscale;
773 }
774
775 /* Make the source viewport size an exact multiple of the scaling factors. */
776 drm_rect_adjust_size(&src,
777 drm_rect_width(&dst) * hscale - drm_rect_width(&src),
778 drm_rect_height(&dst) * vscale - drm_rect_height(&src));
779
780 /* sanity check to make sure the src viewport wasn't enlarged */
781 WARN_ON(src.x1 < (int) src_x ||
782 src.y1 < (int) src_y ||
783 src.x2 > (int) (src_x + src_w) ||
784 src.y2 > (int) (src_y + src_h));
785
786 /*
787 * Hardware doesn't handle subpixel coordinates.
788 * Adjust to (macro)pixel boundary, but be careful not to
789 * increase the source viewport size, because that could
790 * push the downscaling factor out of bounds.
791 */
792 src_x = src.x1 >> 16;
793 src_w = drm_rect_width(&src) >> 16;
794 src_y = src.y1 >> 16;
795 src_h = drm_rect_height(&src) >> 16;
796
797 if (format_is_yuv(fb->pixel_format)) {
798 src_x &= ~1;
799 src_w &= ~1;
800
801 /*
802 * Must keep src and dst the
803 * same if we can't scale.
804 */
805 if (!intel_plane->can_scale)
806 crtc_w &= ~1;
807
808 if (crtc_w == 0)
809 visible = false;
810 }
811 }
812
813 /* Check size restrictions when scaling */
814 if (visible && (src_w != crtc_w || src_h != crtc_h)) {
815 unsigned int width_bytes;
816
817 WARN_ON(!intel_plane->can_scale);
818
819 /* FIXME interlacing min height is 6 */
820
821 if (crtc_w < 3 || crtc_h < 3)
822 visible = false;
823
824 if (src_w < 3 || src_h < 3)
825 visible = false;
826
827 width_bytes = ((src_x * pixel_size) & 63) + src_w * pixel_size;
828
829 if (src_w > 2048 || src_h > 2048 ||
830 width_bytes > 4096 || fb->pitches[0] > 4096) {
831 DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
832 return -EINVAL;
833 }
834 }
835
836 dst.x1 = crtc_x;
837 dst.x2 = crtc_x + crtc_w;
838 dst.y1 = crtc_y;
839 dst.y2 = crtc_y + crtc_h;
840
841 /*
842 * If the sprite is completely covering the primary plane,
843 * we can disable the primary and save power.
844 */
845 disable_primary = drm_rect_equals(&dst, &clip) && !colorkey_enabled(intel_plane);
846 WARN_ON(disable_primary && !visible && intel_crtc->active);
847
848 mutex_lock(&dev->struct_mutex);
849
850 /* Note that this will apply the VT-d workaround for scanouts,
851 * which is more restrictive than required for sprites. (The
852 * primary plane requires 256KiB alignment with 64 PTE padding,
853 * the sprite planes only require 128KiB alignment and 32 PTE padding.
854 */
855 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
856
857 mutex_unlock(&dev->struct_mutex);
858
859 if (ret)
860 return ret;
861
862 intel_plane->crtc_x = orig.crtc_x;
863 intel_plane->crtc_y = orig.crtc_y;
864 intel_plane->crtc_w = orig.crtc_w;
865 intel_plane->crtc_h = orig.crtc_h;
866 intel_plane->src_x = orig.src_x;
867 intel_plane->src_y = orig.src_y;
868 intel_plane->src_w = orig.src_w;
869 intel_plane->src_h = orig.src_h;
870 intel_plane->obj = obj;
871
872 if (intel_crtc->active) {
873 /*
874 * Be sure to re-enable the primary before the sprite is no longer
875 * covering it fully.
876 */
877 if (!disable_primary)
878 intel_enable_primary(crtc);
879
880 if (visible)
881 intel_plane->update_plane(plane, crtc, fb, obj,
882 crtc_x, crtc_y, crtc_w, crtc_h,
883 src_x, src_y, src_w, src_h);
884 else
885 intel_plane->disable_plane(plane, crtc);
886
887 if (disable_primary)
888 intel_disable_primary(crtc);
889 }
890
891 /* Unpin old obj after new one is active to avoid ugliness */
892 if (old_obj) {
893 /*
894 * It's fairly common to simply update the position of
895 * an existing object. In that case, we don't need to
896 * wait for vblank to avoid ugliness, we only need to
897 * do the pin & ref bookkeeping.
898 */
899 if (old_obj != obj && intel_crtc->active)
900 intel_wait_for_vblank(dev, intel_crtc->pipe);
901
902 mutex_lock(&dev->struct_mutex);
903 intel_unpin_fb_obj(old_obj);
904 mutex_unlock(&dev->struct_mutex);
905 }
906
907 return 0;
908}
909
910static int
911intel_disable_plane(struct drm_plane *plane)
912{
913 struct drm_device *dev = plane->dev;
914 struct intel_plane *intel_plane = to_intel_plane(plane);
915 struct intel_crtc *intel_crtc;
916
917 if (!plane->fb)
918 return 0;
919
920 if (WARN_ON(!plane->crtc))
921 return -EINVAL;
922
923 intel_crtc = to_intel_crtc(plane->crtc);
924
925 if (intel_crtc->active) {
926 intel_enable_primary(plane->crtc);
927 intel_plane->disable_plane(plane, plane->crtc);
928 }
929
930 if (intel_plane->obj) {
931 if (intel_crtc->active)
932 intel_wait_for_vblank(dev, intel_plane->pipe);
933
934 mutex_lock(&dev->struct_mutex);
935 intel_unpin_fb_obj(intel_plane->obj);
936 mutex_unlock(&dev->struct_mutex);
937
938 intel_plane->obj = NULL;
939 }
940
941 return 0;
942}
943
944static void intel_destroy_plane(struct drm_plane *plane)
945{
946 struct intel_plane *intel_plane = to_intel_plane(plane);
947 intel_disable_plane(plane);
948 drm_plane_cleanup(plane);
949 kfree(intel_plane);
950}
951
952int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
953 struct drm_file *file_priv)
954{
955 struct drm_intel_sprite_colorkey *set = data;
956 struct drm_mode_object *obj;
957 struct drm_plane *plane;
958 struct intel_plane *intel_plane;
959 int ret = 0;
960
961 if (!drm_core_check_feature(dev, DRIVER_MODESET))
962 return -ENODEV;
963
964 /* Make sure we don't try to enable both src & dest simultaneously */
965 if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
966 return -EINVAL;
967
968 drm_modeset_lock_all(dev);
969
970 obj = drm_mode_object_find(dev, set->plane_id, DRM_MODE_OBJECT_PLANE);
971 if (!obj) {
972 ret = -ENOENT;
973 goto out_unlock;
974 }
975
976 plane = obj_to_plane(obj);
977 intel_plane = to_intel_plane(plane);
978 ret = intel_plane->update_colorkey(plane, set);
979
980out_unlock:
981 drm_modeset_unlock_all(dev);
982 return ret;
983}
984
985int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
986 struct drm_file *file_priv)
987{
988 struct drm_intel_sprite_colorkey *get = data;
989 struct drm_mode_object *obj;
990 struct drm_plane *plane;
991 struct intel_plane *intel_plane;
992 int ret = 0;
993
994 if (!drm_core_check_feature(dev, DRIVER_MODESET))
995 return -ENODEV;
996
997 drm_modeset_lock_all(dev);
998
999 obj = drm_mode_object_find(dev, get->plane_id, DRM_MODE_OBJECT_PLANE);
1000 if (!obj) {
1001 ret = -ENOENT;
1002 goto out_unlock;
1003 }
1004
1005 plane = obj_to_plane(obj);
1006 intel_plane = to_intel_plane(plane);
1007 intel_plane->get_colorkey(plane, get);
1008
1009out_unlock:
1010 drm_modeset_unlock_all(dev);
1011 return ret;
1012}
1013
1014void intel_plane_restore(struct drm_plane *plane)
1015{
1016 struct intel_plane *intel_plane = to_intel_plane(plane);
1017
1018 if (!plane->crtc || !plane->fb)
1019 return;
1020
1021 intel_update_plane(plane, plane->crtc, plane->fb,
1022 intel_plane->crtc_x, intel_plane->crtc_y,
1023 intel_plane->crtc_w, intel_plane->crtc_h,
1024 intel_plane->src_x, intel_plane->src_y,
1025 intel_plane->src_w, intel_plane->src_h);
1026}
1027
1028void intel_plane_disable(struct drm_plane *plane)
1029{
1030 if (!plane->crtc || !plane->fb)
1031 return;
1032
1033 intel_disable_plane(plane);
1034}
1035
1036static const struct drm_plane_funcs intel_plane_funcs = {
1037 .update_plane = intel_update_plane,
1038 .disable_plane = intel_disable_plane,
1039 .destroy = intel_destroy_plane,
1040};
1041
1042static uint32_t ilk_plane_formats[] = {
1043 DRM_FORMAT_XRGB8888,
1044 DRM_FORMAT_YUYV,
1045 DRM_FORMAT_YVYU,
1046 DRM_FORMAT_UYVY,
1047 DRM_FORMAT_VYUY,
1048};
1049
1050static uint32_t snb_plane_formats[] = {
1051 DRM_FORMAT_XBGR8888,
1052 DRM_FORMAT_XRGB8888,
1053 DRM_FORMAT_YUYV,
1054 DRM_FORMAT_YVYU,
1055 DRM_FORMAT_UYVY,
1056 DRM_FORMAT_VYUY,
1057};
1058
1059static uint32_t vlv_plane_formats[] = {
1060 DRM_FORMAT_RGB565,
1061 DRM_FORMAT_ABGR8888,
1062 DRM_FORMAT_ARGB8888,
1063 DRM_FORMAT_XBGR8888,
1064 DRM_FORMAT_XRGB8888,
1065 DRM_FORMAT_XBGR2101010,
1066 DRM_FORMAT_ABGR2101010,
1067 DRM_FORMAT_YUYV,
1068 DRM_FORMAT_YVYU,
1069 DRM_FORMAT_UYVY,
1070 DRM_FORMAT_VYUY,
1071};
1072
1073int
1074intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
1075{
1076 struct intel_plane *intel_plane;
1077 unsigned long possible_crtcs;
1078 const uint32_t *plane_formats;
1079 int num_plane_formats;
1080 int ret;
1081
1082 if (INTEL_INFO(dev)->gen < 5)
1083 return -ENODEV;
1084
1085 intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL);
1086 if (!intel_plane)
1087 return -ENOMEM;
1088
1089 switch (INTEL_INFO(dev)->gen) {
1090 case 5:
1091 case 6:
1092 intel_plane->can_scale = true;
1093 intel_plane->max_downscale = 16;
1094 intel_plane->update_plane = ilk_update_plane;
1095 intel_plane->disable_plane = ilk_disable_plane;
1096 intel_plane->update_colorkey = ilk_update_colorkey;
1097 intel_plane->get_colorkey = ilk_get_colorkey;
1098
1099 if (IS_GEN6(dev)) {
1100 plane_formats = snb_plane_formats;
1101 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1102 } else {
1103 plane_formats = ilk_plane_formats;
1104 num_plane_formats = ARRAY_SIZE(ilk_plane_formats);
1105 }
1106 break;
1107
1108 case 7:
1109 case 8:
1110 if (IS_IVYBRIDGE(dev)) {
1111 intel_plane->can_scale = true;
1112 intel_plane->max_downscale = 2;
1113 } else {
1114 intel_plane->can_scale = false;
1115 intel_plane->max_downscale = 1;
1116 }
1117
1118 if (IS_VALLEYVIEW(dev)) {
1119 intel_plane->update_plane = vlv_update_plane;
1120 intel_plane->disable_plane = vlv_disable_plane;
1121 intel_plane->update_colorkey = vlv_update_colorkey;
1122 intel_plane->get_colorkey = vlv_get_colorkey;
1123
1124 plane_formats = vlv_plane_formats;
1125 num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
1126 } else {
1127 intel_plane->update_plane = ivb_update_plane;
1128 intel_plane->disable_plane = ivb_disable_plane;
1129 intel_plane->update_colorkey = ivb_update_colorkey;
1130 intel_plane->get_colorkey = ivb_get_colorkey;
1131
1132 plane_formats = snb_plane_formats;
1133 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1134 }
1135 break;
1136
1137 default:
1138 kfree(intel_plane);
1139 return -ENODEV;
1140 }
1141
1142 intel_plane->pipe = pipe;
1143 intel_plane->plane = plane;
1144 possible_crtcs = (1 << pipe);
1145 ret = drm_plane_init(dev, &intel_plane->base, possible_crtcs,
1146 &intel_plane_funcs,
1147 plane_formats, num_plane_formats,
1148 false);
1149 if (ret)
1150 kfree(intel_plane);
1151
1152 return ret;
1153}