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1/*
2 * Copyright © 2011 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Jesse Barnes <jbarnes@virtuousgeek.org>
25 *
26 * New plane/sprite handling.
27 *
28 * The older chips had a separate interface for programming plane related
29 * registers; newer ones are much simpler and we can use the new DRM plane
30 * support.
31 */
32#include <drm/drmP.h>
33#include <drm/drm_crtc.h>
34#include <drm/drm_fourcc.h>
35#include <drm/drm_rect.h>
36#include <drm/drm_atomic.h>
37#include <drm/drm_plane_helper.h>
38#include "intel_drv.h"
39#include <drm/i915_drm.h>
40#include "i915_drv.h"
41
42static bool
43format_is_yuv(uint32_t format)
44{
45 switch (format) {
46 case DRM_FORMAT_YUYV:
47 case DRM_FORMAT_UYVY:
48 case DRM_FORMAT_VYUY:
49 case DRM_FORMAT_YVYU:
50 return true;
51 default:
52 return false;
53 }
54}
55
56static int usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
57 int usecs)
58{
59 /* paranoia */
60 if (!adjusted_mode->crtc_htotal)
61 return 1;
62
63 return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock,
64 1000 * adjusted_mode->crtc_htotal);
65}
66
67/**
68 * intel_pipe_update_start() - start update of a set of display registers
69 * @crtc: the crtc of which the registers are going to be updated
70 * @start_vbl_count: vblank counter return pointer used for error checking
71 *
72 * Mark the start of an update to pipe registers that should be updated
73 * atomically regarding vblank. If the next vblank will happens within
74 * the next 100 us, this function waits until the vblank passes.
75 *
76 * After a successful call to this function, interrupts will be disabled
77 * until a subsequent call to intel_pipe_update_end(). That is done to
78 * avoid random delays. The value written to @start_vbl_count should be
79 * supplied to intel_pipe_update_end() for error checking.
80 */
81void intel_pipe_update_start(struct intel_crtc *crtc)
82{
83 struct drm_device *dev = crtc->base.dev;
84 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
85 enum pipe pipe = crtc->pipe;
86 long timeout = msecs_to_jiffies_timeout(1);
87 int scanline, min, max, vblank_start;
88 wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
89 DEFINE_WAIT(wait);
90
91 vblank_start = adjusted_mode->crtc_vblank_start;
92 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
93 vblank_start = DIV_ROUND_UP(vblank_start, 2);
94
95 /* FIXME needs to be calibrated sensibly */
96 min = vblank_start - usecs_to_scanlines(adjusted_mode, 100);
97 max = vblank_start - 1;
98
99 local_irq_disable();
100
101 if (min <= 0 || max <= 0)
102 return;
103
104 if (WARN_ON(drm_crtc_vblank_get(&crtc->base)))
105 return;
106
107 crtc->debug.min_vbl = min;
108 crtc->debug.max_vbl = max;
109 trace_i915_pipe_update_start(crtc);
110
111 for (;;) {
112 /*
113 * prepare_to_wait() has a memory barrier, which guarantees
114 * other CPUs can see the task state update by the time we
115 * read the scanline.
116 */
117 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
118
119 scanline = intel_get_crtc_scanline(crtc);
120 if (scanline < min || scanline > max)
121 break;
122
123 if (timeout <= 0) {
124 DRM_ERROR("Potential atomic update failure on pipe %c\n",
125 pipe_name(crtc->pipe));
126 break;
127 }
128
129 local_irq_enable();
130
131 timeout = schedule_timeout(timeout);
132
133 local_irq_disable();
134 }
135
136 finish_wait(wq, &wait);
137
138 drm_crtc_vblank_put(&crtc->base);
139
140 crtc->debug.scanline_start = scanline;
141 crtc->debug.start_vbl_time = ktime_get();
142 crtc->debug.start_vbl_count =
143 dev->driver->get_vblank_counter(dev, pipe);
144
145 trace_i915_pipe_update_vblank_evaded(crtc);
146}
147
148/**
149 * intel_pipe_update_end() - end update of a set of display registers
150 * @crtc: the crtc of which the registers were updated
151 * @start_vbl_count: start vblank counter (used for error checking)
152 *
153 * Mark the end of an update started with intel_pipe_update_start(). This
154 * re-enables interrupts and verifies the update was actually completed
155 * before a vblank using the value of @start_vbl_count.
156 */
157void intel_pipe_update_end(struct intel_crtc *crtc)
158{
159 struct drm_device *dev = crtc->base.dev;
160 enum pipe pipe = crtc->pipe;
161 int scanline_end = intel_get_crtc_scanline(crtc);
162 u32 end_vbl_count = dev->driver->get_vblank_counter(dev, pipe);
163 ktime_t end_vbl_time = ktime_get();
164
165 trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end);
166
167 local_irq_enable();
168
169 if (crtc->debug.start_vbl_count &&
170 crtc->debug.start_vbl_count != end_vbl_count) {
171 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n",
172 pipe_name(pipe), crtc->debug.start_vbl_count,
173 end_vbl_count,
174 ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
175 crtc->debug.min_vbl, crtc->debug.max_vbl,
176 crtc->debug.scanline_start, scanline_end);
177 }
178}
179
180static void
181skl_update_plane(struct drm_plane *drm_plane,
182 const struct intel_crtc_state *crtc_state,
183 const struct intel_plane_state *plane_state)
184{
185 struct drm_device *dev = drm_plane->dev;
186 struct drm_i915_private *dev_priv = dev->dev_private;
187 struct intel_plane *intel_plane = to_intel_plane(drm_plane);
188 struct drm_framebuffer *fb = plane_state->base.fb;
189 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
190 const int pipe = intel_plane->pipe;
191 const int plane = intel_plane->plane + 1;
192 u32 plane_ctl, stride_div, stride;
193 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
194 u32 surf_addr;
195 u32 tile_height, plane_offset, plane_size;
196 unsigned int rotation;
197 int x_offset, y_offset;
198 int crtc_x = plane_state->dst.x1;
199 int crtc_y = plane_state->dst.y1;
200 uint32_t crtc_w = drm_rect_width(&plane_state->dst);
201 uint32_t crtc_h = drm_rect_height(&plane_state->dst);
202 uint32_t x = plane_state->src.x1 >> 16;
203 uint32_t y = plane_state->src.y1 >> 16;
204 uint32_t src_w = drm_rect_width(&plane_state->src) >> 16;
205 uint32_t src_h = drm_rect_height(&plane_state->src) >> 16;
206 const struct intel_scaler *scaler =
207 &crtc_state->scaler_state.scalers[plane_state->scaler_id];
208
209 plane_ctl = PLANE_CTL_ENABLE |
210 PLANE_CTL_PIPE_GAMMA_ENABLE |
211 PLANE_CTL_PIPE_CSC_ENABLE;
212
213 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
214 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
215
216 rotation = plane_state->base.rotation;
217 plane_ctl |= skl_plane_ctl_rotation(rotation);
218
219 stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
220 fb->pixel_format);
221
222 /* Sizes are 0 based */
223 src_w--;
224 src_h--;
225 crtc_w--;
226 crtc_h--;
227
228 if (key->flags) {
229 I915_WRITE(PLANE_KEYVAL(pipe, plane), key->min_value);
230 I915_WRITE(PLANE_KEYMAX(pipe, plane), key->max_value);
231 I915_WRITE(PLANE_KEYMSK(pipe, plane), key->channel_mask);
232 }
233
234 if (key->flags & I915_SET_COLORKEY_DESTINATION)
235 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
236 else if (key->flags & I915_SET_COLORKEY_SOURCE)
237 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
238
239 surf_addr = intel_plane_obj_offset(intel_plane, obj, 0);
240
241 if (intel_rotation_90_or_270(rotation)) {
242 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
243
244 /* stride: Surface height in tiles */
245 tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp);
246 stride = DIV_ROUND_UP(fb->height, tile_height);
247 plane_size = (src_w << 16) | src_h;
248 x_offset = stride * tile_height - y - (src_h + 1);
249 y_offset = x;
250 } else {
251 stride = fb->pitches[0] / stride_div;
252 plane_size = (src_h << 16) | src_w;
253 x_offset = x;
254 y_offset = y;
255 }
256 plane_offset = y_offset << 16 | x_offset;
257
258 I915_WRITE(PLANE_OFFSET(pipe, plane), plane_offset);
259 I915_WRITE(PLANE_STRIDE(pipe, plane), stride);
260 I915_WRITE(PLANE_SIZE(pipe, plane), plane_size);
261
262 /* program plane scaler */
263 if (plane_state->scaler_id >= 0) {
264 uint32_t ps_ctrl = 0;
265 int scaler_id = plane_state->scaler_id;
266
267 DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) = 0x%x\n", plane,
268 PS_PLANE_SEL(plane));
269 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane) | scaler->mode;
270 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
271 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
272 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
273 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id),
274 ((crtc_w + 1) << 16)|(crtc_h + 1));
275
276 I915_WRITE(PLANE_POS(pipe, plane), 0);
277 } else {
278 I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x);
279 }
280
281 I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl);
282 I915_WRITE(PLANE_SURF(pipe, plane), surf_addr);
283 POSTING_READ(PLANE_SURF(pipe, plane));
284}
285
286static void
287skl_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
288{
289 struct drm_device *dev = dplane->dev;
290 struct drm_i915_private *dev_priv = dev->dev_private;
291 struct intel_plane *intel_plane = to_intel_plane(dplane);
292 const int pipe = intel_plane->pipe;
293 const int plane = intel_plane->plane + 1;
294
295 I915_WRITE(PLANE_CTL(pipe, plane), 0);
296
297 I915_WRITE(PLANE_SURF(pipe, plane), 0);
298 POSTING_READ(PLANE_SURF(pipe, plane));
299}
300
301static void
302chv_update_csc(struct intel_plane *intel_plane, uint32_t format)
303{
304 struct drm_i915_private *dev_priv = intel_plane->base.dev->dev_private;
305 int plane = intel_plane->plane;
306
307 /* Seems RGB data bypasses the CSC always */
308 if (!format_is_yuv(format))
309 return;
310
311 /*
312 * BT.601 limited range YCbCr -> full range RGB
313 *
314 * |r| | 6537 4769 0| |cr |
315 * |g| = |-3330 4769 -1605| x |y-64|
316 * |b| | 0 4769 8263| |cb |
317 *
318 * Cb and Cr apparently come in as signed already, so no
319 * need for any offset. For Y we need to remove the offset.
320 */
321 I915_WRITE(SPCSCYGOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(-64));
322 I915_WRITE(SPCSCCBOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0));
323 I915_WRITE(SPCSCCROFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0));
324
325 I915_WRITE(SPCSCC01(plane), SPCSC_C1(4769) | SPCSC_C0(6537));
326 I915_WRITE(SPCSCC23(plane), SPCSC_C1(-3330) | SPCSC_C0(0));
327 I915_WRITE(SPCSCC45(plane), SPCSC_C1(-1605) | SPCSC_C0(4769));
328 I915_WRITE(SPCSCC67(plane), SPCSC_C1(4769) | SPCSC_C0(0));
329 I915_WRITE(SPCSCC8(plane), SPCSC_C0(8263));
330
331 I915_WRITE(SPCSCYGICLAMP(plane), SPCSC_IMAX(940) | SPCSC_IMIN(64));
332 I915_WRITE(SPCSCCBICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
333 I915_WRITE(SPCSCCRICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
334
335 I915_WRITE(SPCSCYGOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
336 I915_WRITE(SPCSCCBOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
337 I915_WRITE(SPCSCCROCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
338}
339
340static void
341vlv_update_plane(struct drm_plane *dplane,
342 const struct intel_crtc_state *crtc_state,
343 const struct intel_plane_state *plane_state)
344{
345 struct drm_device *dev = dplane->dev;
346 struct drm_i915_private *dev_priv = dev->dev_private;
347 struct intel_plane *intel_plane = to_intel_plane(dplane);
348 struct drm_framebuffer *fb = plane_state->base.fb;
349 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
350 int pipe = intel_plane->pipe;
351 int plane = intel_plane->plane;
352 u32 sprctl;
353 u32 sprsurf_offset, linear_offset;
354 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
355 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
356 int crtc_x = plane_state->dst.x1;
357 int crtc_y = plane_state->dst.y1;
358 uint32_t crtc_w = drm_rect_width(&plane_state->dst);
359 uint32_t crtc_h = drm_rect_height(&plane_state->dst);
360 uint32_t x = plane_state->src.x1 >> 16;
361 uint32_t y = plane_state->src.y1 >> 16;
362 uint32_t src_w = drm_rect_width(&plane_state->src) >> 16;
363 uint32_t src_h = drm_rect_height(&plane_state->src) >> 16;
364
365 sprctl = SP_ENABLE;
366
367 switch (fb->pixel_format) {
368 case DRM_FORMAT_YUYV:
369 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
370 break;
371 case DRM_FORMAT_YVYU:
372 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
373 break;
374 case DRM_FORMAT_UYVY:
375 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
376 break;
377 case DRM_FORMAT_VYUY:
378 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
379 break;
380 case DRM_FORMAT_RGB565:
381 sprctl |= SP_FORMAT_BGR565;
382 break;
383 case DRM_FORMAT_XRGB8888:
384 sprctl |= SP_FORMAT_BGRX8888;
385 break;
386 case DRM_FORMAT_ARGB8888:
387 sprctl |= SP_FORMAT_BGRA8888;
388 break;
389 case DRM_FORMAT_XBGR2101010:
390 sprctl |= SP_FORMAT_RGBX1010102;
391 break;
392 case DRM_FORMAT_ABGR2101010:
393 sprctl |= SP_FORMAT_RGBA1010102;
394 break;
395 case DRM_FORMAT_XBGR8888:
396 sprctl |= SP_FORMAT_RGBX8888;
397 break;
398 case DRM_FORMAT_ABGR8888:
399 sprctl |= SP_FORMAT_RGBA8888;
400 break;
401 default:
402 /*
403 * If we get here one of the upper layers failed to filter
404 * out the unsupported plane formats
405 */
406 BUG();
407 break;
408 }
409
410 /*
411 * Enable gamma to match primary/cursor plane behaviour.
412 * FIXME should be user controllable via propertiesa.
413 */
414 sprctl |= SP_GAMMA_ENABLE;
415
416 if (obj->tiling_mode != I915_TILING_NONE)
417 sprctl |= SP_TILED;
418
419 /* Sizes are 0 based */
420 src_w--;
421 src_h--;
422 crtc_w--;
423 crtc_h--;
424
425 linear_offset = y * fb->pitches[0] + x * cpp;
426 sprsurf_offset = intel_compute_tile_offset(dev_priv, &x, &y,
427 fb->modifier[0], cpp,
428 fb->pitches[0]);
429 linear_offset -= sprsurf_offset;
430
431 if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
432 sprctl |= SP_ROTATE_180;
433
434 x += src_w;
435 y += src_h;
436 linear_offset += src_h * fb->pitches[0] + src_w * cpp;
437 }
438
439 if (key->flags) {
440 I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value);
441 I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value);
442 I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask);
443 }
444
445 if (key->flags & I915_SET_COLORKEY_SOURCE)
446 sprctl |= SP_SOURCE_KEY;
447
448 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B)
449 chv_update_csc(intel_plane, fb->pixel_format);
450
451 I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
452 I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
453
454 if (obj->tiling_mode != I915_TILING_NONE)
455 I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x);
456 else
457 I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
458
459 I915_WRITE(SPCONSTALPHA(pipe, plane), 0);
460
461 I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
462 I915_WRITE(SPCNTR(pipe, plane), sprctl);
463 I915_WRITE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) +
464 sprsurf_offset);
465 POSTING_READ(SPSURF(pipe, plane));
466}
467
468static void
469vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
470{
471 struct drm_device *dev = dplane->dev;
472 struct drm_i915_private *dev_priv = dev->dev_private;
473 struct intel_plane *intel_plane = to_intel_plane(dplane);
474 int pipe = intel_plane->pipe;
475 int plane = intel_plane->plane;
476
477 I915_WRITE(SPCNTR(pipe, plane), 0);
478
479 I915_WRITE(SPSURF(pipe, plane), 0);
480 POSTING_READ(SPSURF(pipe, plane));
481}
482
483static void
484ivb_update_plane(struct drm_plane *plane,
485 const struct intel_crtc_state *crtc_state,
486 const struct intel_plane_state *plane_state)
487{
488 struct drm_device *dev = plane->dev;
489 struct drm_i915_private *dev_priv = dev->dev_private;
490 struct intel_plane *intel_plane = to_intel_plane(plane);
491 struct drm_framebuffer *fb = plane_state->base.fb;
492 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
493 enum pipe pipe = intel_plane->pipe;
494 u32 sprctl, sprscale = 0;
495 u32 sprsurf_offset, linear_offset;
496 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
497 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
498 int crtc_x = plane_state->dst.x1;
499 int crtc_y = plane_state->dst.y1;
500 uint32_t crtc_w = drm_rect_width(&plane_state->dst);
501 uint32_t crtc_h = drm_rect_height(&plane_state->dst);
502 uint32_t x = plane_state->src.x1 >> 16;
503 uint32_t y = plane_state->src.y1 >> 16;
504 uint32_t src_w = drm_rect_width(&plane_state->src) >> 16;
505 uint32_t src_h = drm_rect_height(&plane_state->src) >> 16;
506
507 sprctl = SPRITE_ENABLE;
508
509 switch (fb->pixel_format) {
510 case DRM_FORMAT_XBGR8888:
511 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
512 break;
513 case DRM_FORMAT_XRGB8888:
514 sprctl |= SPRITE_FORMAT_RGBX888;
515 break;
516 case DRM_FORMAT_YUYV:
517 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
518 break;
519 case DRM_FORMAT_YVYU:
520 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
521 break;
522 case DRM_FORMAT_UYVY:
523 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
524 break;
525 case DRM_FORMAT_VYUY:
526 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
527 break;
528 default:
529 BUG();
530 }
531
532 /*
533 * Enable gamma to match primary/cursor plane behaviour.
534 * FIXME should be user controllable via propertiesa.
535 */
536 sprctl |= SPRITE_GAMMA_ENABLE;
537
538 if (obj->tiling_mode != I915_TILING_NONE)
539 sprctl |= SPRITE_TILED;
540
541 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
542 sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE;
543 else
544 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
545
546 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
547 sprctl |= SPRITE_PIPE_CSC_ENABLE;
548
549 /* Sizes are 0 based */
550 src_w--;
551 src_h--;
552 crtc_w--;
553 crtc_h--;
554
555 if (crtc_w != src_w || crtc_h != src_h)
556 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
557
558 linear_offset = y * fb->pitches[0] + x * cpp;
559 sprsurf_offset = intel_compute_tile_offset(dev_priv, &x, &y,
560 fb->modifier[0], cpp,
561 fb->pitches[0]);
562 linear_offset -= sprsurf_offset;
563
564 if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
565 sprctl |= SPRITE_ROTATE_180;
566
567 /* HSW and BDW does this automagically in hardware */
568 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
569 x += src_w;
570 y += src_h;
571 linear_offset += src_h * fb->pitches[0] + src_w * cpp;
572 }
573 }
574
575 if (key->flags) {
576 I915_WRITE(SPRKEYVAL(pipe), key->min_value);
577 I915_WRITE(SPRKEYMAX(pipe), key->max_value);
578 I915_WRITE(SPRKEYMSK(pipe), key->channel_mask);
579 }
580
581 if (key->flags & I915_SET_COLORKEY_DESTINATION)
582 sprctl |= SPRITE_DEST_KEY;
583 else if (key->flags & I915_SET_COLORKEY_SOURCE)
584 sprctl |= SPRITE_SOURCE_KEY;
585
586 I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);
587 I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
588
589 /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
590 * register */
591 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
592 I915_WRITE(SPROFFSET(pipe), (y << 16) | x);
593 else if (obj->tiling_mode != I915_TILING_NONE)
594 I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
595 else
596 I915_WRITE(SPRLINOFF(pipe), linear_offset);
597
598 I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
599 if (intel_plane->can_scale)
600 I915_WRITE(SPRSCALE(pipe), sprscale);
601 I915_WRITE(SPRCTL(pipe), sprctl);
602 I915_WRITE(SPRSURF(pipe),
603 i915_gem_obj_ggtt_offset(obj) + sprsurf_offset);
604 POSTING_READ(SPRSURF(pipe));
605}
606
607static void
608ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
609{
610 struct drm_device *dev = plane->dev;
611 struct drm_i915_private *dev_priv = dev->dev_private;
612 struct intel_plane *intel_plane = to_intel_plane(plane);
613 int pipe = intel_plane->pipe;
614
615 I915_WRITE(SPRCTL(pipe), 0);
616 /* Can't leave the scaler enabled... */
617 if (intel_plane->can_scale)
618 I915_WRITE(SPRSCALE(pipe), 0);
619
620 I915_WRITE(SPRSURF(pipe), 0);
621 POSTING_READ(SPRSURF(pipe));
622}
623
624static void
625ilk_update_plane(struct drm_plane *plane,
626 const struct intel_crtc_state *crtc_state,
627 const struct intel_plane_state *plane_state)
628{
629 struct drm_device *dev = plane->dev;
630 struct drm_i915_private *dev_priv = dev->dev_private;
631 struct intel_plane *intel_plane = to_intel_plane(plane);
632 struct drm_framebuffer *fb = plane_state->base.fb;
633 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
634 int pipe = intel_plane->pipe;
635 u32 dvscntr, dvsscale;
636 u32 dvssurf_offset, linear_offset;
637 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
638 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
639 int crtc_x = plane_state->dst.x1;
640 int crtc_y = plane_state->dst.y1;
641 uint32_t crtc_w = drm_rect_width(&plane_state->dst);
642 uint32_t crtc_h = drm_rect_height(&plane_state->dst);
643 uint32_t x = plane_state->src.x1 >> 16;
644 uint32_t y = plane_state->src.y1 >> 16;
645 uint32_t src_w = drm_rect_width(&plane_state->src) >> 16;
646 uint32_t src_h = drm_rect_height(&plane_state->src) >> 16;
647
648 dvscntr = DVS_ENABLE;
649
650 switch (fb->pixel_format) {
651 case DRM_FORMAT_XBGR8888:
652 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
653 break;
654 case DRM_FORMAT_XRGB8888:
655 dvscntr |= DVS_FORMAT_RGBX888;
656 break;
657 case DRM_FORMAT_YUYV:
658 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
659 break;
660 case DRM_FORMAT_YVYU:
661 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
662 break;
663 case DRM_FORMAT_UYVY:
664 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
665 break;
666 case DRM_FORMAT_VYUY:
667 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
668 break;
669 default:
670 BUG();
671 }
672
673 /*
674 * Enable gamma to match primary/cursor plane behaviour.
675 * FIXME should be user controllable via propertiesa.
676 */
677 dvscntr |= DVS_GAMMA_ENABLE;
678
679 if (obj->tiling_mode != I915_TILING_NONE)
680 dvscntr |= DVS_TILED;
681
682 if (IS_GEN6(dev))
683 dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */
684
685 /* Sizes are 0 based */
686 src_w--;
687 src_h--;
688 crtc_w--;
689 crtc_h--;
690
691 dvsscale = 0;
692 if (crtc_w != src_w || crtc_h != src_h)
693 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
694
695 linear_offset = y * fb->pitches[0] + x * cpp;
696 dvssurf_offset = intel_compute_tile_offset(dev_priv, &x, &y,
697 fb->modifier[0], cpp,
698 fb->pitches[0]);
699 linear_offset -= dvssurf_offset;
700
701 if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
702 dvscntr |= DVS_ROTATE_180;
703
704 x += src_w;
705 y += src_h;
706 linear_offset += src_h * fb->pitches[0] + src_w * cpp;
707 }
708
709 if (key->flags) {
710 I915_WRITE(DVSKEYVAL(pipe), key->min_value);
711 I915_WRITE(DVSKEYMAX(pipe), key->max_value);
712 I915_WRITE(DVSKEYMSK(pipe), key->channel_mask);
713 }
714
715 if (key->flags & I915_SET_COLORKEY_DESTINATION)
716 dvscntr |= DVS_DEST_KEY;
717 else if (key->flags & I915_SET_COLORKEY_SOURCE)
718 dvscntr |= DVS_SOURCE_KEY;
719
720 I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
721 I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
722
723 if (obj->tiling_mode != I915_TILING_NONE)
724 I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);
725 else
726 I915_WRITE(DVSLINOFF(pipe), linear_offset);
727
728 I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
729 I915_WRITE(DVSSCALE(pipe), dvsscale);
730 I915_WRITE(DVSCNTR(pipe), dvscntr);
731 I915_WRITE(DVSSURF(pipe),
732 i915_gem_obj_ggtt_offset(obj) + dvssurf_offset);
733 POSTING_READ(DVSSURF(pipe));
734}
735
736static void
737ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
738{
739 struct drm_device *dev = plane->dev;
740 struct drm_i915_private *dev_priv = dev->dev_private;
741 struct intel_plane *intel_plane = to_intel_plane(plane);
742 int pipe = intel_plane->pipe;
743
744 I915_WRITE(DVSCNTR(pipe), 0);
745 /* Disable the scaler */
746 I915_WRITE(DVSSCALE(pipe), 0);
747
748 I915_WRITE(DVSSURF(pipe), 0);
749 POSTING_READ(DVSSURF(pipe));
750}
751
752static int
753intel_check_sprite_plane(struct drm_plane *plane,
754 struct intel_crtc_state *crtc_state,
755 struct intel_plane_state *state)
756{
757 struct drm_device *dev = plane->dev;
758 struct drm_crtc *crtc = state->base.crtc;
759 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
760 struct intel_plane *intel_plane = to_intel_plane(plane);
761 struct drm_framebuffer *fb = state->base.fb;
762 int crtc_x, crtc_y;
763 unsigned int crtc_w, crtc_h;
764 uint32_t src_x, src_y, src_w, src_h;
765 struct drm_rect *src = &state->src;
766 struct drm_rect *dst = &state->dst;
767 const struct drm_rect *clip = &state->clip;
768 int hscale, vscale;
769 int max_scale, min_scale;
770 bool can_scale;
771
772 if (!fb) {
773 state->visible = false;
774 return 0;
775 }
776
777 /* Don't modify another pipe's plane */
778 if (intel_plane->pipe != intel_crtc->pipe) {
779 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
780 return -EINVAL;
781 }
782
783 /* FIXME check all gen limits */
784 if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) {
785 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
786 return -EINVAL;
787 }
788
789 /* setup can_scale, min_scale, max_scale */
790 if (INTEL_INFO(dev)->gen >= 9) {
791 /* use scaler when colorkey is not required */
792 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
793 can_scale = 1;
794 min_scale = 1;
795 max_scale = skl_max_scale(intel_crtc, crtc_state);
796 } else {
797 can_scale = 0;
798 min_scale = DRM_PLANE_HELPER_NO_SCALING;
799 max_scale = DRM_PLANE_HELPER_NO_SCALING;
800 }
801 } else {
802 can_scale = intel_plane->can_scale;
803 max_scale = intel_plane->max_downscale << 16;
804 min_scale = intel_plane->can_scale ? 1 : (1 << 16);
805 }
806
807 /*
808 * FIXME the following code does a bunch of fuzzy adjustments to the
809 * coordinates and sizes. We probably need some way to decide whether
810 * more strict checking should be done instead.
811 */
812 drm_rect_rotate(src, fb->width << 16, fb->height << 16,
813 state->base.rotation);
814
815 hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale);
816 BUG_ON(hscale < 0);
817
818 vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale);
819 BUG_ON(vscale < 0);
820
821 state->visible = drm_rect_clip_scaled(src, dst, clip, hscale, vscale);
822
823 crtc_x = dst->x1;
824 crtc_y = dst->y1;
825 crtc_w = drm_rect_width(dst);
826 crtc_h = drm_rect_height(dst);
827
828 if (state->visible) {
829 /* check again in case clipping clamped the results */
830 hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
831 if (hscale < 0) {
832 DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
833 drm_rect_debug_print("src: ", src, true);
834 drm_rect_debug_print("dst: ", dst, false);
835
836 return hscale;
837 }
838
839 vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
840 if (vscale < 0) {
841 DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
842 drm_rect_debug_print("src: ", src, true);
843 drm_rect_debug_print("dst: ", dst, false);
844
845 return vscale;
846 }
847
848 /* Make the source viewport size an exact multiple of the scaling factors. */
849 drm_rect_adjust_size(src,
850 drm_rect_width(dst) * hscale - drm_rect_width(src),
851 drm_rect_height(dst) * vscale - drm_rect_height(src));
852
853 drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16,
854 state->base.rotation);
855
856 /* sanity check to make sure the src viewport wasn't enlarged */
857 WARN_ON(src->x1 < (int) state->base.src_x ||
858 src->y1 < (int) state->base.src_y ||
859 src->x2 > (int) state->base.src_x + state->base.src_w ||
860 src->y2 > (int) state->base.src_y + state->base.src_h);
861
862 /*
863 * Hardware doesn't handle subpixel coordinates.
864 * Adjust to (macro)pixel boundary, but be careful not to
865 * increase the source viewport size, because that could
866 * push the downscaling factor out of bounds.
867 */
868 src_x = src->x1 >> 16;
869 src_w = drm_rect_width(src) >> 16;
870 src_y = src->y1 >> 16;
871 src_h = drm_rect_height(src) >> 16;
872
873 if (format_is_yuv(fb->pixel_format)) {
874 src_x &= ~1;
875 src_w &= ~1;
876
877 /*
878 * Must keep src and dst the
879 * same if we can't scale.
880 */
881 if (!can_scale)
882 crtc_w &= ~1;
883
884 if (crtc_w == 0)
885 state->visible = false;
886 }
887 }
888
889 /* Check size restrictions when scaling */
890 if (state->visible && (src_w != crtc_w || src_h != crtc_h)) {
891 unsigned int width_bytes;
892 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
893
894 WARN_ON(!can_scale);
895
896 /* FIXME interlacing min height is 6 */
897
898 if (crtc_w < 3 || crtc_h < 3)
899 state->visible = false;
900
901 if (src_w < 3 || src_h < 3)
902 state->visible = false;
903
904 width_bytes = ((src_x * cpp) & 63) + src_w * cpp;
905
906 if (INTEL_INFO(dev)->gen < 9 && (src_w > 2048 || src_h > 2048 ||
907 width_bytes > 4096 || fb->pitches[0] > 4096)) {
908 DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
909 return -EINVAL;
910 }
911 }
912
913 if (state->visible) {
914 src->x1 = src_x << 16;
915 src->x2 = (src_x + src_w) << 16;
916 src->y1 = src_y << 16;
917 src->y2 = (src_y + src_h) << 16;
918 }
919
920 dst->x1 = crtc_x;
921 dst->x2 = crtc_x + crtc_w;
922 dst->y1 = crtc_y;
923 dst->y2 = crtc_y + crtc_h;
924
925 return 0;
926}
927
928int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
929 struct drm_file *file_priv)
930{
931 struct drm_intel_sprite_colorkey *set = data;
932 struct drm_plane *plane;
933 struct drm_plane_state *plane_state;
934 struct drm_atomic_state *state;
935 struct drm_modeset_acquire_ctx ctx;
936 int ret = 0;
937
938 /* Make sure we don't try to enable both src & dest simultaneously */
939 if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
940 return -EINVAL;
941
942 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
943 set->flags & I915_SET_COLORKEY_DESTINATION)
944 return -EINVAL;
945
946 plane = drm_plane_find(dev, set->plane_id);
947 if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY)
948 return -ENOENT;
949
950 drm_modeset_acquire_init(&ctx, 0);
951
952 state = drm_atomic_state_alloc(plane->dev);
953 if (!state) {
954 ret = -ENOMEM;
955 goto out;
956 }
957 state->acquire_ctx = &ctx;
958
959 while (1) {
960 plane_state = drm_atomic_get_plane_state(state, plane);
961 ret = PTR_ERR_OR_ZERO(plane_state);
962 if (!ret) {
963 to_intel_plane_state(plane_state)->ckey = *set;
964 ret = drm_atomic_commit(state);
965 }
966
967 if (ret != -EDEADLK)
968 break;
969
970 drm_atomic_state_clear(state);
971 drm_modeset_backoff(&ctx);
972 }
973
974 if (ret)
975 drm_atomic_state_free(state);
976
977out:
978 drm_modeset_drop_locks(&ctx);
979 drm_modeset_acquire_fini(&ctx);
980 return ret;
981}
982
983static const uint32_t ilk_plane_formats[] = {
984 DRM_FORMAT_XRGB8888,
985 DRM_FORMAT_YUYV,
986 DRM_FORMAT_YVYU,
987 DRM_FORMAT_UYVY,
988 DRM_FORMAT_VYUY,
989};
990
991static const uint32_t snb_plane_formats[] = {
992 DRM_FORMAT_XBGR8888,
993 DRM_FORMAT_XRGB8888,
994 DRM_FORMAT_YUYV,
995 DRM_FORMAT_YVYU,
996 DRM_FORMAT_UYVY,
997 DRM_FORMAT_VYUY,
998};
999
1000static const uint32_t vlv_plane_formats[] = {
1001 DRM_FORMAT_RGB565,
1002 DRM_FORMAT_ABGR8888,
1003 DRM_FORMAT_ARGB8888,
1004 DRM_FORMAT_XBGR8888,
1005 DRM_FORMAT_XRGB8888,
1006 DRM_FORMAT_XBGR2101010,
1007 DRM_FORMAT_ABGR2101010,
1008 DRM_FORMAT_YUYV,
1009 DRM_FORMAT_YVYU,
1010 DRM_FORMAT_UYVY,
1011 DRM_FORMAT_VYUY,
1012};
1013
1014static uint32_t skl_plane_formats[] = {
1015 DRM_FORMAT_RGB565,
1016 DRM_FORMAT_ABGR8888,
1017 DRM_FORMAT_ARGB8888,
1018 DRM_FORMAT_XBGR8888,
1019 DRM_FORMAT_XRGB8888,
1020 DRM_FORMAT_YUYV,
1021 DRM_FORMAT_YVYU,
1022 DRM_FORMAT_UYVY,
1023 DRM_FORMAT_VYUY,
1024};
1025
1026int
1027intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
1028{
1029 struct intel_plane *intel_plane;
1030 struct intel_plane_state *state;
1031 unsigned long possible_crtcs;
1032 const uint32_t *plane_formats;
1033 int num_plane_formats;
1034 int ret;
1035
1036 if (INTEL_INFO(dev)->gen < 5)
1037 return -ENODEV;
1038
1039 intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL);
1040 if (!intel_plane)
1041 return -ENOMEM;
1042
1043 state = intel_create_plane_state(&intel_plane->base);
1044 if (!state) {
1045 kfree(intel_plane);
1046 return -ENOMEM;
1047 }
1048 intel_plane->base.state = &state->base;
1049
1050 switch (INTEL_INFO(dev)->gen) {
1051 case 5:
1052 case 6:
1053 intel_plane->can_scale = true;
1054 intel_plane->max_downscale = 16;
1055 intel_plane->update_plane = ilk_update_plane;
1056 intel_plane->disable_plane = ilk_disable_plane;
1057
1058 if (IS_GEN6(dev)) {
1059 plane_formats = snb_plane_formats;
1060 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1061 } else {
1062 plane_formats = ilk_plane_formats;
1063 num_plane_formats = ARRAY_SIZE(ilk_plane_formats);
1064 }
1065 break;
1066
1067 case 7:
1068 case 8:
1069 if (IS_IVYBRIDGE(dev)) {
1070 intel_plane->can_scale = true;
1071 intel_plane->max_downscale = 2;
1072 } else {
1073 intel_plane->can_scale = false;
1074 intel_plane->max_downscale = 1;
1075 }
1076
1077 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1078 intel_plane->update_plane = vlv_update_plane;
1079 intel_plane->disable_plane = vlv_disable_plane;
1080
1081 plane_formats = vlv_plane_formats;
1082 num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
1083 } else {
1084 intel_plane->update_plane = ivb_update_plane;
1085 intel_plane->disable_plane = ivb_disable_plane;
1086
1087 plane_formats = snb_plane_formats;
1088 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1089 }
1090 break;
1091 case 9:
1092 intel_plane->can_scale = true;
1093 intel_plane->update_plane = skl_update_plane;
1094 intel_plane->disable_plane = skl_disable_plane;
1095 state->scaler_id = -1;
1096
1097 plane_formats = skl_plane_formats;
1098 num_plane_formats = ARRAY_SIZE(skl_plane_formats);
1099 break;
1100 default:
1101 kfree(intel_plane);
1102 return -ENODEV;
1103 }
1104
1105 intel_plane->pipe = pipe;
1106 intel_plane->plane = plane;
1107 intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER_SPRITE(pipe, plane);
1108 intel_plane->check_plane = intel_check_sprite_plane;
1109 possible_crtcs = (1 << pipe);
1110 ret = drm_universal_plane_init(dev, &intel_plane->base, possible_crtcs,
1111 &intel_plane_funcs,
1112 plane_formats, num_plane_formats,
1113 DRM_PLANE_TYPE_OVERLAY, NULL);
1114 if (ret) {
1115 kfree(intel_plane);
1116 goto out;
1117 }
1118
1119 intel_create_rotation_property(dev, intel_plane);
1120
1121 drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs);
1122
1123out:
1124 return ret;
1125}
1/*
2 * Copyright © 2011 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Jesse Barnes <jbarnes@virtuousgeek.org>
25 *
26 * New plane/sprite handling.
27 *
28 * The older chips had a separate interface for programming plane related
29 * registers; newer ones are much simpler and we can use the new DRM plane
30 * support.
31 */
32#include "drmP.h"
33#include "drm_crtc.h"
34#include "drm_fourcc.h"
35#include "intel_drv.h"
36#include "i915_drm.h"
37#include "i915_drv.h"
38
39static void
40ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
41 struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
42 unsigned int crtc_w, unsigned int crtc_h,
43 uint32_t x, uint32_t y,
44 uint32_t src_w, uint32_t src_h)
45{
46 struct drm_device *dev = plane->dev;
47 struct drm_i915_private *dev_priv = dev->dev_private;
48 struct intel_plane *intel_plane = to_intel_plane(plane);
49 int pipe = intel_plane->pipe;
50 u32 sprctl, sprscale = 0;
51 int pixel_size;
52
53 sprctl = I915_READ(SPRCTL(pipe));
54
55 /* Mask out pixel format bits in case we change it */
56 sprctl &= ~SPRITE_PIXFORMAT_MASK;
57 sprctl &= ~SPRITE_RGB_ORDER_RGBX;
58 sprctl &= ~SPRITE_YUV_BYTE_ORDER_MASK;
59
60 switch (fb->pixel_format) {
61 case DRM_FORMAT_XBGR8888:
62 sprctl |= SPRITE_FORMAT_RGBX888;
63 pixel_size = 4;
64 break;
65 case DRM_FORMAT_XRGB8888:
66 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
67 pixel_size = 4;
68 break;
69 case DRM_FORMAT_YUYV:
70 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
71 pixel_size = 2;
72 break;
73 case DRM_FORMAT_YVYU:
74 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
75 pixel_size = 2;
76 break;
77 case DRM_FORMAT_UYVY:
78 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
79 pixel_size = 2;
80 break;
81 case DRM_FORMAT_VYUY:
82 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
83 pixel_size = 2;
84 break;
85 default:
86 DRM_DEBUG_DRIVER("bad pixel format, assuming RGBX888\n");
87 sprctl |= DVS_FORMAT_RGBX888;
88 pixel_size = 4;
89 break;
90 }
91
92 if (obj->tiling_mode != I915_TILING_NONE)
93 sprctl |= SPRITE_TILED;
94
95 /* must disable */
96 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
97 sprctl |= SPRITE_ENABLE;
98
99 /* Sizes are 0 based */
100 src_w--;
101 src_h--;
102 crtc_w--;
103 crtc_h--;
104
105 intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size);
106
107 /*
108 * IVB workaround: must disable low power watermarks for at least
109 * one frame before enabling scaling. LP watermarks can be re-enabled
110 * when scaling is disabled.
111 */
112 if (crtc_w != src_w || crtc_h != src_h) {
113 if (!dev_priv->sprite_scaling_enabled) {
114 dev_priv->sprite_scaling_enabled = true;
115 intel_update_watermarks(dev);
116 intel_wait_for_vblank(dev, pipe);
117 }
118 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
119 } else {
120 if (dev_priv->sprite_scaling_enabled) {
121 dev_priv->sprite_scaling_enabled = false;
122 /* potentially re-enable LP watermarks */
123 intel_update_watermarks(dev);
124 }
125 }
126
127 I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);
128 I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
129 if (obj->tiling_mode != I915_TILING_NONE) {
130 I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
131 } else {
132 unsigned long offset;
133
134 offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
135 I915_WRITE(SPRLINOFF(pipe), offset);
136 }
137 I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
138 I915_WRITE(SPRSCALE(pipe), sprscale);
139 I915_WRITE(SPRCTL(pipe), sprctl);
140 I915_MODIFY_DISPBASE(SPRSURF(pipe), obj->gtt_offset);
141 POSTING_READ(SPRSURF(pipe));
142}
143
144static void
145ivb_disable_plane(struct drm_plane *plane)
146{
147 struct drm_device *dev = plane->dev;
148 struct drm_i915_private *dev_priv = dev->dev_private;
149 struct intel_plane *intel_plane = to_intel_plane(plane);
150 int pipe = intel_plane->pipe;
151
152 I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE);
153 /* Can't leave the scaler enabled... */
154 I915_WRITE(SPRSCALE(pipe), 0);
155 /* Activate double buffered register update */
156 I915_MODIFY_DISPBASE(SPRSURF(pipe), 0);
157 POSTING_READ(SPRSURF(pipe));
158
159 dev_priv->sprite_scaling_enabled = false;
160 intel_update_watermarks(dev);
161}
162
163static int
164ivb_update_colorkey(struct drm_plane *plane,
165 struct drm_intel_sprite_colorkey *key)
166{
167 struct drm_device *dev = plane->dev;
168 struct drm_i915_private *dev_priv = dev->dev_private;
169 struct intel_plane *intel_plane;
170 u32 sprctl;
171 int ret = 0;
172
173 intel_plane = to_intel_plane(plane);
174
175 I915_WRITE(SPRKEYVAL(intel_plane->pipe), key->min_value);
176 I915_WRITE(SPRKEYMAX(intel_plane->pipe), key->max_value);
177 I915_WRITE(SPRKEYMSK(intel_plane->pipe), key->channel_mask);
178
179 sprctl = I915_READ(SPRCTL(intel_plane->pipe));
180 sprctl &= ~(SPRITE_SOURCE_KEY | SPRITE_DEST_KEY);
181 if (key->flags & I915_SET_COLORKEY_DESTINATION)
182 sprctl |= SPRITE_DEST_KEY;
183 else if (key->flags & I915_SET_COLORKEY_SOURCE)
184 sprctl |= SPRITE_SOURCE_KEY;
185 I915_WRITE(SPRCTL(intel_plane->pipe), sprctl);
186
187 POSTING_READ(SPRKEYMSK(intel_plane->pipe));
188
189 return ret;
190}
191
192static void
193ivb_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key)
194{
195 struct drm_device *dev = plane->dev;
196 struct drm_i915_private *dev_priv = dev->dev_private;
197 struct intel_plane *intel_plane;
198 u32 sprctl;
199
200 intel_plane = to_intel_plane(plane);
201
202 key->min_value = I915_READ(SPRKEYVAL(intel_plane->pipe));
203 key->max_value = I915_READ(SPRKEYMAX(intel_plane->pipe));
204 key->channel_mask = I915_READ(SPRKEYMSK(intel_plane->pipe));
205 key->flags = 0;
206
207 sprctl = I915_READ(SPRCTL(intel_plane->pipe));
208
209 if (sprctl & SPRITE_DEST_KEY)
210 key->flags = I915_SET_COLORKEY_DESTINATION;
211 else if (sprctl & SPRITE_SOURCE_KEY)
212 key->flags = I915_SET_COLORKEY_SOURCE;
213 else
214 key->flags = I915_SET_COLORKEY_NONE;
215}
216
217static void
218ilk_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
219 struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
220 unsigned int crtc_w, unsigned int crtc_h,
221 uint32_t x, uint32_t y,
222 uint32_t src_w, uint32_t src_h)
223{
224 struct drm_device *dev = plane->dev;
225 struct drm_i915_private *dev_priv = dev->dev_private;
226 struct intel_plane *intel_plane = to_intel_plane(plane);
227 int pipe = intel_plane->pipe, pixel_size;
228 u32 dvscntr, dvsscale;
229
230 dvscntr = I915_READ(DVSCNTR(pipe));
231
232 /* Mask out pixel format bits in case we change it */
233 dvscntr &= ~DVS_PIXFORMAT_MASK;
234 dvscntr &= ~DVS_RGB_ORDER_XBGR;
235 dvscntr &= ~DVS_YUV_BYTE_ORDER_MASK;
236
237 switch (fb->pixel_format) {
238 case DRM_FORMAT_XBGR8888:
239 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
240 pixel_size = 4;
241 break;
242 case DRM_FORMAT_XRGB8888:
243 dvscntr |= DVS_FORMAT_RGBX888;
244 pixel_size = 4;
245 break;
246 case DRM_FORMAT_YUYV:
247 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
248 pixel_size = 2;
249 break;
250 case DRM_FORMAT_YVYU:
251 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
252 pixel_size = 2;
253 break;
254 case DRM_FORMAT_UYVY:
255 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
256 pixel_size = 2;
257 break;
258 case DRM_FORMAT_VYUY:
259 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
260 pixel_size = 2;
261 break;
262 default:
263 DRM_DEBUG_DRIVER("bad pixel format, assuming RGBX888\n");
264 dvscntr |= DVS_FORMAT_RGBX888;
265 pixel_size = 4;
266 break;
267 }
268
269 if (obj->tiling_mode != I915_TILING_NONE)
270 dvscntr |= DVS_TILED;
271
272 if (IS_GEN6(dev))
273 dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */
274 dvscntr |= DVS_ENABLE;
275
276 /* Sizes are 0 based */
277 src_w--;
278 src_h--;
279 crtc_w--;
280 crtc_h--;
281
282 intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size);
283
284 dvsscale = 0;
285 if (IS_GEN5(dev) || crtc_w != src_w || crtc_h != src_h)
286 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
287
288 I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
289 I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
290 if (obj->tiling_mode != I915_TILING_NONE) {
291 I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);
292 } else {
293 unsigned long offset;
294
295 offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
296 I915_WRITE(DVSLINOFF(pipe), offset);
297 }
298 I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
299 I915_WRITE(DVSSCALE(pipe), dvsscale);
300 I915_WRITE(DVSCNTR(pipe), dvscntr);
301 I915_MODIFY_DISPBASE(DVSSURF(pipe), obj->gtt_offset);
302 POSTING_READ(DVSSURF(pipe));
303}
304
305static void
306ilk_disable_plane(struct drm_plane *plane)
307{
308 struct drm_device *dev = plane->dev;
309 struct drm_i915_private *dev_priv = dev->dev_private;
310 struct intel_plane *intel_plane = to_intel_plane(plane);
311 int pipe = intel_plane->pipe;
312
313 I915_WRITE(DVSCNTR(pipe), I915_READ(DVSCNTR(pipe)) & ~DVS_ENABLE);
314 /* Disable the scaler */
315 I915_WRITE(DVSSCALE(pipe), 0);
316 /* Flush double buffered register updates */
317 I915_MODIFY_DISPBASE(DVSSURF(pipe), 0);
318 POSTING_READ(DVSSURF(pipe));
319}
320
321static void
322intel_enable_primary(struct drm_crtc *crtc)
323{
324 struct drm_device *dev = crtc->dev;
325 struct drm_i915_private *dev_priv = dev->dev_private;
326 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
327 int reg = DSPCNTR(intel_crtc->plane);
328
329 I915_WRITE(reg, I915_READ(reg) | DISPLAY_PLANE_ENABLE);
330}
331
332static void
333intel_disable_primary(struct drm_crtc *crtc)
334{
335 struct drm_device *dev = crtc->dev;
336 struct drm_i915_private *dev_priv = dev->dev_private;
337 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
338 int reg = DSPCNTR(intel_crtc->plane);
339
340 I915_WRITE(reg, I915_READ(reg) & ~DISPLAY_PLANE_ENABLE);
341}
342
343static int
344ilk_update_colorkey(struct drm_plane *plane,
345 struct drm_intel_sprite_colorkey *key)
346{
347 struct drm_device *dev = plane->dev;
348 struct drm_i915_private *dev_priv = dev->dev_private;
349 struct intel_plane *intel_plane;
350 u32 dvscntr;
351 int ret = 0;
352
353 intel_plane = to_intel_plane(plane);
354
355 I915_WRITE(DVSKEYVAL(intel_plane->pipe), key->min_value);
356 I915_WRITE(DVSKEYMAX(intel_plane->pipe), key->max_value);
357 I915_WRITE(DVSKEYMSK(intel_plane->pipe), key->channel_mask);
358
359 dvscntr = I915_READ(DVSCNTR(intel_plane->pipe));
360 dvscntr &= ~(DVS_SOURCE_KEY | DVS_DEST_KEY);
361 if (key->flags & I915_SET_COLORKEY_DESTINATION)
362 dvscntr |= DVS_DEST_KEY;
363 else if (key->flags & I915_SET_COLORKEY_SOURCE)
364 dvscntr |= DVS_SOURCE_KEY;
365 I915_WRITE(DVSCNTR(intel_plane->pipe), dvscntr);
366
367 POSTING_READ(DVSKEYMSK(intel_plane->pipe));
368
369 return ret;
370}
371
372static void
373ilk_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key)
374{
375 struct drm_device *dev = plane->dev;
376 struct drm_i915_private *dev_priv = dev->dev_private;
377 struct intel_plane *intel_plane;
378 u32 dvscntr;
379
380 intel_plane = to_intel_plane(plane);
381
382 key->min_value = I915_READ(DVSKEYVAL(intel_plane->pipe));
383 key->max_value = I915_READ(DVSKEYMAX(intel_plane->pipe));
384 key->channel_mask = I915_READ(DVSKEYMSK(intel_plane->pipe));
385 key->flags = 0;
386
387 dvscntr = I915_READ(DVSCNTR(intel_plane->pipe));
388
389 if (dvscntr & DVS_DEST_KEY)
390 key->flags = I915_SET_COLORKEY_DESTINATION;
391 else if (dvscntr & DVS_SOURCE_KEY)
392 key->flags = I915_SET_COLORKEY_SOURCE;
393 else
394 key->flags = I915_SET_COLORKEY_NONE;
395}
396
397static int
398intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
399 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
400 unsigned int crtc_w, unsigned int crtc_h,
401 uint32_t src_x, uint32_t src_y,
402 uint32_t src_w, uint32_t src_h)
403{
404 struct drm_device *dev = plane->dev;
405 struct drm_i915_private *dev_priv = dev->dev_private;
406 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
407 struct intel_plane *intel_plane = to_intel_plane(plane);
408 struct intel_framebuffer *intel_fb;
409 struct drm_i915_gem_object *obj, *old_obj;
410 int pipe = intel_plane->pipe;
411 int ret = 0;
412 int x = src_x >> 16, y = src_y >> 16;
413 int primary_w = crtc->mode.hdisplay, primary_h = crtc->mode.vdisplay;
414 bool disable_primary = false;
415
416 intel_fb = to_intel_framebuffer(fb);
417 obj = intel_fb->obj;
418
419 old_obj = intel_plane->obj;
420
421 src_w = src_w >> 16;
422 src_h = src_h >> 16;
423
424 /* Pipe must be running... */
425 if (!(I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE))
426 return -EINVAL;
427
428 if (crtc_x >= primary_w || crtc_y >= primary_h)
429 return -EINVAL;
430
431 /* Don't modify another pipe's plane */
432 if (intel_plane->pipe != intel_crtc->pipe)
433 return -EINVAL;
434
435 /*
436 * Clamp the width & height into the visible area. Note we don't
437 * try to scale the source if part of the visible region is offscreen.
438 * The caller must handle that by adjusting source offset and size.
439 */
440 if ((crtc_x < 0) && ((crtc_x + crtc_w) > 0)) {
441 crtc_w += crtc_x;
442 crtc_x = 0;
443 }
444 if ((crtc_x + crtc_w) <= 0) /* Nothing to display */
445 goto out;
446 if ((crtc_x + crtc_w) > primary_w)
447 crtc_w = primary_w - crtc_x;
448
449 if ((crtc_y < 0) && ((crtc_y + crtc_h) > 0)) {
450 crtc_h += crtc_y;
451 crtc_y = 0;
452 }
453 if ((crtc_y + crtc_h) <= 0) /* Nothing to display */
454 goto out;
455 if (crtc_y + crtc_h > primary_h)
456 crtc_h = primary_h - crtc_y;
457
458 if (!crtc_w || !crtc_h) /* Again, nothing to display */
459 goto out;
460
461 /*
462 * We can take a larger source and scale it down, but
463 * only so much... 16x is the max on SNB.
464 */
465 if (((src_w * src_h) / (crtc_w * crtc_h)) > intel_plane->max_downscale)
466 return -EINVAL;
467
468 /*
469 * If the sprite is completely covering the primary plane,
470 * we can disable the primary and save power.
471 */
472 if ((crtc_x == 0) && (crtc_y == 0) &&
473 (crtc_w == primary_w) && (crtc_h == primary_h))
474 disable_primary = true;
475
476 mutex_lock(&dev->struct_mutex);
477
478 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
479 if (ret)
480 goto out_unlock;
481
482 intel_plane->obj = obj;
483
484 /*
485 * Be sure to re-enable the primary before the sprite is no longer
486 * covering it fully.
487 */
488 if (!disable_primary && intel_plane->primary_disabled) {
489 intel_enable_primary(crtc);
490 intel_plane->primary_disabled = false;
491 }
492
493 intel_plane->update_plane(plane, fb, obj, crtc_x, crtc_y,
494 crtc_w, crtc_h, x, y, src_w, src_h);
495
496 if (disable_primary) {
497 intel_disable_primary(crtc);
498 intel_plane->primary_disabled = true;
499 }
500
501 /* Unpin old obj after new one is active to avoid ugliness */
502 if (old_obj) {
503 /*
504 * It's fairly common to simply update the position of
505 * an existing object. In that case, we don't need to
506 * wait for vblank to avoid ugliness, we only need to
507 * do the pin & ref bookkeeping.
508 */
509 if (old_obj != obj) {
510 mutex_unlock(&dev->struct_mutex);
511 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
512 mutex_lock(&dev->struct_mutex);
513 }
514 intel_unpin_fb_obj(old_obj);
515 }
516
517out_unlock:
518 mutex_unlock(&dev->struct_mutex);
519out:
520 return ret;
521}
522
523static int
524intel_disable_plane(struct drm_plane *plane)
525{
526 struct drm_device *dev = plane->dev;
527 struct intel_plane *intel_plane = to_intel_plane(plane);
528 int ret = 0;
529
530 if (intel_plane->primary_disabled) {
531 intel_enable_primary(plane->crtc);
532 intel_plane->primary_disabled = false;
533 }
534
535 intel_plane->disable_plane(plane);
536
537 if (!intel_plane->obj)
538 goto out;
539
540 mutex_lock(&dev->struct_mutex);
541 intel_unpin_fb_obj(intel_plane->obj);
542 intel_plane->obj = NULL;
543 mutex_unlock(&dev->struct_mutex);
544out:
545
546 return ret;
547}
548
549static void intel_destroy_plane(struct drm_plane *plane)
550{
551 struct intel_plane *intel_plane = to_intel_plane(plane);
552 intel_disable_plane(plane);
553 drm_plane_cleanup(plane);
554 kfree(intel_plane);
555}
556
557int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
558 struct drm_file *file_priv)
559{
560 struct drm_intel_sprite_colorkey *set = data;
561 struct drm_mode_object *obj;
562 struct drm_plane *plane;
563 struct intel_plane *intel_plane;
564 int ret = 0;
565
566 if (!drm_core_check_feature(dev, DRIVER_MODESET))
567 return -ENODEV;
568
569 /* Make sure we don't try to enable both src & dest simultaneously */
570 if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
571 return -EINVAL;
572
573 mutex_lock(&dev->mode_config.mutex);
574
575 obj = drm_mode_object_find(dev, set->plane_id, DRM_MODE_OBJECT_PLANE);
576 if (!obj) {
577 ret = -EINVAL;
578 goto out_unlock;
579 }
580
581 plane = obj_to_plane(obj);
582 intel_plane = to_intel_plane(plane);
583 ret = intel_plane->update_colorkey(plane, set);
584
585out_unlock:
586 mutex_unlock(&dev->mode_config.mutex);
587 return ret;
588}
589
590int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
591 struct drm_file *file_priv)
592{
593 struct drm_intel_sprite_colorkey *get = data;
594 struct drm_mode_object *obj;
595 struct drm_plane *plane;
596 struct intel_plane *intel_plane;
597 int ret = 0;
598
599 if (!drm_core_check_feature(dev, DRIVER_MODESET))
600 return -ENODEV;
601
602 mutex_lock(&dev->mode_config.mutex);
603
604 obj = drm_mode_object_find(dev, get->plane_id, DRM_MODE_OBJECT_PLANE);
605 if (!obj) {
606 ret = -EINVAL;
607 goto out_unlock;
608 }
609
610 plane = obj_to_plane(obj);
611 intel_plane = to_intel_plane(plane);
612 intel_plane->get_colorkey(plane, get);
613
614out_unlock:
615 mutex_unlock(&dev->mode_config.mutex);
616 return ret;
617}
618
619static const struct drm_plane_funcs intel_plane_funcs = {
620 .update_plane = intel_update_plane,
621 .disable_plane = intel_disable_plane,
622 .destroy = intel_destroy_plane,
623};
624
625static uint32_t ilk_plane_formats[] = {
626 DRM_FORMAT_XRGB8888,
627 DRM_FORMAT_YUYV,
628 DRM_FORMAT_YVYU,
629 DRM_FORMAT_UYVY,
630 DRM_FORMAT_VYUY,
631};
632
633static uint32_t snb_plane_formats[] = {
634 DRM_FORMAT_XBGR8888,
635 DRM_FORMAT_XRGB8888,
636 DRM_FORMAT_YUYV,
637 DRM_FORMAT_YVYU,
638 DRM_FORMAT_UYVY,
639 DRM_FORMAT_VYUY,
640};
641
642int
643intel_plane_init(struct drm_device *dev, enum pipe pipe)
644{
645 struct intel_plane *intel_plane;
646 unsigned long possible_crtcs;
647 const uint32_t *plane_formats;
648 int num_plane_formats;
649 int ret;
650
651 if (INTEL_INFO(dev)->gen < 5)
652 return -ENODEV;
653
654 intel_plane = kzalloc(sizeof(struct intel_plane), GFP_KERNEL);
655 if (!intel_plane)
656 return -ENOMEM;
657
658 switch (INTEL_INFO(dev)->gen) {
659 case 5:
660 case 6:
661 intel_plane->max_downscale = 16;
662 intel_plane->update_plane = ilk_update_plane;
663 intel_plane->disable_plane = ilk_disable_plane;
664 intel_plane->update_colorkey = ilk_update_colorkey;
665 intel_plane->get_colorkey = ilk_get_colorkey;
666
667 if (IS_GEN6(dev)) {
668 plane_formats = snb_plane_formats;
669 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
670 } else {
671 plane_formats = ilk_plane_formats;
672 num_plane_formats = ARRAY_SIZE(ilk_plane_formats);
673 }
674 break;
675
676 case 7:
677 intel_plane->max_downscale = 2;
678 intel_plane->update_plane = ivb_update_plane;
679 intel_plane->disable_plane = ivb_disable_plane;
680 intel_plane->update_colorkey = ivb_update_colorkey;
681 intel_plane->get_colorkey = ivb_get_colorkey;
682
683 plane_formats = snb_plane_formats;
684 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
685 break;
686
687 default:
688 return -ENODEV;
689 }
690
691 intel_plane->pipe = pipe;
692 possible_crtcs = (1 << pipe);
693 ret = drm_plane_init(dev, &intel_plane->base, possible_crtcs,
694 &intel_plane_funcs,
695 plane_formats, num_plane_formats,
696 false);
697 if (ret)
698 kfree(intel_plane);
699
700 return ret;
701}
702