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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
31/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63#include <linux/atomic.h>
64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
67#include <linux/interval_tree.h>
68#include <linux/hashtable.h>
69#include <linux/fence.h>
70
71#include <ttm/ttm_bo_api.h>
72#include <ttm/ttm_bo_driver.h>
73#include <ttm/ttm_placement.h>
74#include <ttm/ttm_module.h>
75#include <ttm/ttm_execbuf_util.h>
76
77#include <drm/drm_gem.h>
78
79#include "radeon_family.h"
80#include "radeon_mode.h"
81#include "radeon_reg.h"
82
83/*
84 * Modules parameters.
85 */
86extern int radeon_no_wb;
87extern int radeon_modeset;
88extern int radeon_dynclks;
89extern int radeon_r4xx_atom;
90extern int radeon_agpmode;
91extern int radeon_vram_limit;
92extern int radeon_gart_size;
93extern int radeon_benchmarking;
94extern int radeon_testing;
95extern int radeon_connector_table;
96extern int radeon_tv;
97extern int radeon_audio;
98extern int radeon_disp_priority;
99extern int radeon_hw_i2c;
100extern int radeon_pcie_gen2;
101extern int radeon_msi;
102extern int radeon_lockup_timeout;
103extern int radeon_fastfb;
104extern int radeon_dpm;
105extern int radeon_aspm;
106extern int radeon_runtime_pm;
107extern int radeon_hard_reset;
108extern int radeon_vm_size;
109extern int radeon_vm_block_size;
110extern int radeon_deep_color;
111extern int radeon_use_pflipirq;
112extern int radeon_bapm;
113extern int radeon_backlight;
114extern int radeon_auxch;
115extern int radeon_mst;
116
117/*
118 * Copy from radeon_drv.h so we don't have to include both and have conflicting
119 * symbol;
120 */
121#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
122#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
123#define RADEON_USEC_IB_TEST_TIMEOUT 1000000 /* 1s */
124/* RADEON_IB_POOL_SIZE must be a power of 2 */
125#define RADEON_IB_POOL_SIZE 16
126#define RADEON_DEBUGFS_MAX_COMPONENTS 32
127#define RADEONFB_CONN_LIMIT 4
128#define RADEON_BIOS_NUM_SCRATCH 8
129
130/* internal ring indices */
131/* r1xx+ has gfx CP ring */
132#define RADEON_RING_TYPE_GFX_INDEX 0
133
134/* cayman has 2 compute CP rings */
135#define CAYMAN_RING_TYPE_CP1_INDEX 1
136#define CAYMAN_RING_TYPE_CP2_INDEX 2
137
138/* R600+ has an async dma ring */
139#define R600_RING_TYPE_DMA_INDEX 3
140/* cayman add a second async dma ring */
141#define CAYMAN_RING_TYPE_DMA1_INDEX 4
142
143/* R600+ */
144#define R600_RING_TYPE_UVD_INDEX 5
145
146/* TN+ */
147#define TN_RING_TYPE_VCE1_INDEX 6
148#define TN_RING_TYPE_VCE2_INDEX 7
149
150/* max number of rings */
151#define RADEON_NUM_RINGS 8
152
153/* number of hw syncs before falling back on blocking */
154#define RADEON_NUM_SYNCS 4
155
156/* hardcode those limit for now */
157#define RADEON_VA_IB_OFFSET (1 << 20)
158#define RADEON_VA_RESERVED_SIZE (8 << 20)
159#define RADEON_IB_VM_MAX_SIZE (64 << 10)
160
161/* hard reset data */
162#define RADEON_ASIC_RESET_DATA 0x39d5e86b
163
164/* reset flags */
165#define RADEON_RESET_GFX (1 << 0)
166#define RADEON_RESET_COMPUTE (1 << 1)
167#define RADEON_RESET_DMA (1 << 2)
168#define RADEON_RESET_CP (1 << 3)
169#define RADEON_RESET_GRBM (1 << 4)
170#define RADEON_RESET_DMA1 (1 << 5)
171#define RADEON_RESET_RLC (1 << 6)
172#define RADEON_RESET_SEM (1 << 7)
173#define RADEON_RESET_IH (1 << 8)
174#define RADEON_RESET_VMC (1 << 9)
175#define RADEON_RESET_MC (1 << 10)
176#define RADEON_RESET_DISPLAY (1 << 11)
177
178/* CG block flags */
179#define RADEON_CG_BLOCK_GFX (1 << 0)
180#define RADEON_CG_BLOCK_MC (1 << 1)
181#define RADEON_CG_BLOCK_SDMA (1 << 2)
182#define RADEON_CG_BLOCK_UVD (1 << 3)
183#define RADEON_CG_BLOCK_VCE (1 << 4)
184#define RADEON_CG_BLOCK_HDP (1 << 5)
185#define RADEON_CG_BLOCK_BIF (1 << 6)
186
187/* CG flags */
188#define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
189#define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
190#define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
191#define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
192#define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
193#define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
194#define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
195#define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
196#define RADEON_CG_SUPPORT_MC_LS (1 << 8)
197#define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
198#define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
199#define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
200#define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
201#define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
202#define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
203#define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
204#define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
205
206/* PG flags */
207#define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
208#define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
209#define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
210#define RADEON_PG_SUPPORT_UVD (1 << 3)
211#define RADEON_PG_SUPPORT_VCE (1 << 4)
212#define RADEON_PG_SUPPORT_CP (1 << 5)
213#define RADEON_PG_SUPPORT_GDS (1 << 6)
214#define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
215#define RADEON_PG_SUPPORT_SDMA (1 << 8)
216#define RADEON_PG_SUPPORT_ACP (1 << 9)
217#define RADEON_PG_SUPPORT_SAMU (1 << 10)
218
219/* max cursor sizes (in pixels) */
220#define CURSOR_WIDTH 64
221#define CURSOR_HEIGHT 64
222
223#define CIK_CURSOR_WIDTH 128
224#define CIK_CURSOR_HEIGHT 128
225
226/*
227 * Errata workarounds.
228 */
229enum radeon_pll_errata {
230 CHIP_ERRATA_R300_CG = 0x00000001,
231 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
232 CHIP_ERRATA_PLL_DELAY = 0x00000004
233};
234
235
236struct radeon_device;
237
238
239/*
240 * BIOS.
241 */
242bool radeon_get_bios(struct radeon_device *rdev);
243
244/*
245 * Dummy page
246 */
247struct radeon_dummy_page {
248 uint64_t entry;
249 struct page *page;
250 dma_addr_t addr;
251};
252int radeon_dummy_page_init(struct radeon_device *rdev);
253void radeon_dummy_page_fini(struct radeon_device *rdev);
254
255
256/*
257 * Clocks
258 */
259struct radeon_clock {
260 struct radeon_pll p1pll;
261 struct radeon_pll p2pll;
262 struct radeon_pll dcpll;
263 struct radeon_pll spll;
264 struct radeon_pll mpll;
265 /* 10 Khz units */
266 uint32_t default_mclk;
267 uint32_t default_sclk;
268 uint32_t default_dispclk;
269 uint32_t current_dispclk;
270 uint32_t dp_extclk;
271 uint32_t max_pixel_clock;
272 uint32_t vco_freq;
273};
274
275/*
276 * Power management
277 */
278int radeon_pm_init(struct radeon_device *rdev);
279int radeon_pm_late_init(struct radeon_device *rdev);
280void radeon_pm_fini(struct radeon_device *rdev);
281void radeon_pm_compute_clocks(struct radeon_device *rdev);
282void radeon_pm_suspend(struct radeon_device *rdev);
283void radeon_pm_resume(struct radeon_device *rdev);
284void radeon_combios_get_power_modes(struct radeon_device *rdev);
285void radeon_atombios_get_power_modes(struct radeon_device *rdev);
286int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
287 u8 clock_type,
288 u32 clock,
289 bool strobe_mode,
290 struct atom_clock_dividers *dividers);
291int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
292 u32 clock,
293 bool strobe_mode,
294 struct atom_mpll_param *mpll_param);
295void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
296int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
297 u16 voltage_level, u8 voltage_type,
298 u32 *gpio_value, u32 *gpio_mask);
299void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
300 u32 eng_clock, u32 mem_clock);
301int radeon_atom_get_voltage_step(struct radeon_device *rdev,
302 u8 voltage_type, u16 *voltage_step);
303int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
304 u16 voltage_id, u16 *voltage);
305int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
306 u16 *voltage,
307 u16 leakage_idx);
308int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
309 u16 *leakage_id);
310int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
311 u16 *vddc, u16 *vddci,
312 u16 virtual_voltage_id,
313 u16 vbios_voltage_id);
314int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
315 u16 virtual_voltage_id,
316 u16 *voltage);
317int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
318 u8 voltage_type,
319 u16 nominal_voltage,
320 u16 *true_voltage);
321int radeon_atom_get_min_voltage(struct radeon_device *rdev,
322 u8 voltage_type, u16 *min_voltage);
323int radeon_atom_get_max_voltage(struct radeon_device *rdev,
324 u8 voltage_type, u16 *max_voltage);
325int radeon_atom_get_voltage_table(struct radeon_device *rdev,
326 u8 voltage_type, u8 voltage_mode,
327 struct atom_voltage_table *voltage_table);
328bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
329 u8 voltage_type, u8 voltage_mode);
330int radeon_atom_get_svi2_info(struct radeon_device *rdev,
331 u8 voltage_type,
332 u8 *svd_gpio_id, u8 *svc_gpio_id);
333void radeon_atom_update_memory_dll(struct radeon_device *rdev,
334 u32 mem_clock);
335void radeon_atom_set_ac_timing(struct radeon_device *rdev,
336 u32 mem_clock);
337int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
338 u8 module_index,
339 struct atom_mc_reg_table *reg_table);
340int radeon_atom_get_memory_info(struct radeon_device *rdev,
341 u8 module_index, struct atom_memory_info *mem_info);
342int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
343 bool gddr5, u8 module_index,
344 struct atom_memory_clock_range_table *mclk_range_table);
345int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
346 u16 voltage_id, u16 *voltage);
347void rs690_pm_info(struct radeon_device *rdev);
348extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
349 unsigned *bankh, unsigned *mtaspect,
350 unsigned *tile_split);
351
352/*
353 * Fences.
354 */
355struct radeon_fence_driver {
356 struct radeon_device *rdev;
357 uint32_t scratch_reg;
358 uint64_t gpu_addr;
359 volatile uint32_t *cpu_addr;
360 /* sync_seq is protected by ring emission lock */
361 uint64_t sync_seq[RADEON_NUM_RINGS];
362 atomic64_t last_seq;
363 bool initialized, delayed_irq;
364 struct delayed_work lockup_work;
365};
366
367struct radeon_fence {
368 struct fence base;
369
370 struct radeon_device *rdev;
371 uint64_t seq;
372 /* RB, DMA, etc. */
373 unsigned ring;
374 bool is_vm_update;
375
376 wait_queue_t fence_wake;
377};
378
379int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
380int radeon_fence_driver_init(struct radeon_device *rdev);
381void radeon_fence_driver_fini(struct radeon_device *rdev);
382void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring);
383int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
384void radeon_fence_process(struct radeon_device *rdev, int ring);
385bool radeon_fence_signaled(struct radeon_fence *fence);
386long radeon_fence_wait_timeout(struct radeon_fence *fence, bool interruptible, long timeout);
387int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
388int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
389int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
390int radeon_fence_wait_any(struct radeon_device *rdev,
391 struct radeon_fence **fences,
392 bool intr);
393struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
394void radeon_fence_unref(struct radeon_fence **fence);
395unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
396bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
397void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
398static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
399 struct radeon_fence *b)
400{
401 if (!a) {
402 return b;
403 }
404
405 if (!b) {
406 return a;
407 }
408
409 BUG_ON(a->ring != b->ring);
410
411 if (a->seq > b->seq) {
412 return a;
413 } else {
414 return b;
415 }
416}
417
418static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
419 struct radeon_fence *b)
420{
421 if (!a) {
422 return false;
423 }
424
425 if (!b) {
426 return true;
427 }
428
429 BUG_ON(a->ring != b->ring);
430
431 return a->seq < b->seq;
432}
433
434/*
435 * Tiling registers
436 */
437struct radeon_surface_reg {
438 struct radeon_bo *bo;
439};
440
441#define RADEON_GEM_MAX_SURFACES 8
442
443/*
444 * TTM.
445 */
446struct radeon_mman {
447 struct ttm_bo_global_ref bo_global_ref;
448 struct drm_global_reference mem_global_ref;
449 struct ttm_bo_device bdev;
450 bool mem_global_referenced;
451 bool initialized;
452
453#if defined(CONFIG_DEBUG_FS)
454 struct dentry *vram;
455 struct dentry *gtt;
456#endif
457};
458
459struct radeon_bo_list {
460 struct radeon_bo *robj;
461 struct ttm_validate_buffer tv;
462 uint64_t gpu_offset;
463 unsigned prefered_domains;
464 unsigned allowed_domains;
465 uint32_t tiling_flags;
466};
467
468/* bo virtual address in a specific vm */
469struct radeon_bo_va {
470 /* protected by bo being reserved */
471 struct list_head bo_list;
472 uint32_t flags;
473 struct radeon_fence *last_pt_update;
474 unsigned ref_count;
475
476 /* protected by vm mutex */
477 struct interval_tree_node it;
478 struct list_head vm_status;
479
480 /* constant after initialization */
481 struct radeon_vm *vm;
482 struct radeon_bo *bo;
483};
484
485struct radeon_bo {
486 /* Protected by gem.mutex */
487 struct list_head list;
488 /* Protected by tbo.reserved */
489 u32 initial_domain;
490 struct ttm_place placements[4];
491 struct ttm_placement placement;
492 struct ttm_buffer_object tbo;
493 struct ttm_bo_kmap_obj kmap;
494 u32 flags;
495 unsigned pin_count;
496 void *kptr;
497 u32 tiling_flags;
498 u32 pitch;
499 int surface_reg;
500 /* list of all virtual address to which this bo
501 * is associated to
502 */
503 struct list_head va;
504 /* Constant after initialization */
505 struct radeon_device *rdev;
506 struct drm_gem_object gem_base;
507
508 struct ttm_bo_kmap_obj dma_buf_vmap;
509 pid_t pid;
510
511 struct radeon_mn *mn;
512 struct list_head mn_list;
513};
514#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
515
516int radeon_gem_debugfs_init(struct radeon_device *rdev);
517
518/* sub-allocation manager, it has to be protected by another lock.
519 * By conception this is an helper for other part of the driver
520 * like the indirect buffer or semaphore, which both have their
521 * locking.
522 *
523 * Principe is simple, we keep a list of sub allocation in offset
524 * order (first entry has offset == 0, last entry has the highest
525 * offset).
526 *
527 * When allocating new object we first check if there is room at
528 * the end total_size - (last_object_offset + last_object_size) >=
529 * alloc_size. If so we allocate new object there.
530 *
531 * When there is not enough room at the end, we start waiting for
532 * each sub object until we reach object_offset+object_size >=
533 * alloc_size, this object then become the sub object we return.
534 *
535 * Alignment can't be bigger than page size.
536 *
537 * Hole are not considered for allocation to keep things simple.
538 * Assumption is that there won't be hole (all object on same
539 * alignment).
540 */
541struct radeon_sa_manager {
542 wait_queue_head_t wq;
543 struct radeon_bo *bo;
544 struct list_head *hole;
545 struct list_head flist[RADEON_NUM_RINGS];
546 struct list_head olist;
547 unsigned size;
548 uint64_t gpu_addr;
549 void *cpu_ptr;
550 uint32_t domain;
551 uint32_t align;
552};
553
554struct radeon_sa_bo;
555
556/* sub-allocation buffer */
557struct radeon_sa_bo {
558 struct list_head olist;
559 struct list_head flist;
560 struct radeon_sa_manager *manager;
561 unsigned soffset;
562 unsigned eoffset;
563 struct radeon_fence *fence;
564};
565
566/*
567 * GEM objects.
568 */
569struct radeon_gem {
570 struct mutex mutex;
571 struct list_head objects;
572};
573
574int radeon_gem_init(struct radeon_device *rdev);
575void radeon_gem_fini(struct radeon_device *rdev);
576int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size,
577 int alignment, int initial_domain,
578 u32 flags, bool kernel,
579 struct drm_gem_object **obj);
580
581int radeon_mode_dumb_create(struct drm_file *file_priv,
582 struct drm_device *dev,
583 struct drm_mode_create_dumb *args);
584int radeon_mode_dumb_mmap(struct drm_file *filp,
585 struct drm_device *dev,
586 uint32_t handle, uint64_t *offset_p);
587
588/*
589 * Semaphores.
590 */
591struct radeon_semaphore {
592 struct radeon_sa_bo *sa_bo;
593 signed waiters;
594 uint64_t gpu_addr;
595};
596
597int radeon_semaphore_create(struct radeon_device *rdev,
598 struct radeon_semaphore **semaphore);
599bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
600 struct radeon_semaphore *semaphore);
601bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
602 struct radeon_semaphore *semaphore);
603void radeon_semaphore_free(struct radeon_device *rdev,
604 struct radeon_semaphore **semaphore,
605 struct radeon_fence *fence);
606
607/*
608 * Synchronization
609 */
610struct radeon_sync {
611 struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS];
612 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
613 struct radeon_fence *last_vm_update;
614};
615
616void radeon_sync_create(struct radeon_sync *sync);
617void radeon_sync_fence(struct radeon_sync *sync,
618 struct radeon_fence *fence);
619int radeon_sync_resv(struct radeon_device *rdev,
620 struct radeon_sync *sync,
621 struct reservation_object *resv,
622 bool shared);
623int radeon_sync_rings(struct radeon_device *rdev,
624 struct radeon_sync *sync,
625 int waiting_ring);
626void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync,
627 struct radeon_fence *fence);
628
629/*
630 * GART structures, functions & helpers
631 */
632struct radeon_mc;
633
634#define RADEON_GPU_PAGE_SIZE 4096
635#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
636#define RADEON_GPU_PAGE_SHIFT 12
637#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
638
639#define RADEON_GART_PAGE_DUMMY 0
640#define RADEON_GART_PAGE_VALID (1 << 0)
641#define RADEON_GART_PAGE_READ (1 << 1)
642#define RADEON_GART_PAGE_WRITE (1 << 2)
643#define RADEON_GART_PAGE_SNOOP (1 << 3)
644
645struct radeon_gart {
646 dma_addr_t table_addr;
647 struct radeon_bo *robj;
648 void *ptr;
649 unsigned num_gpu_pages;
650 unsigned num_cpu_pages;
651 unsigned table_size;
652 struct page **pages;
653 uint64_t *pages_entry;
654 bool ready;
655};
656
657int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
658void radeon_gart_table_ram_free(struct radeon_device *rdev);
659int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
660void radeon_gart_table_vram_free(struct radeon_device *rdev);
661int radeon_gart_table_vram_pin(struct radeon_device *rdev);
662void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
663int radeon_gart_init(struct radeon_device *rdev);
664void radeon_gart_fini(struct radeon_device *rdev);
665void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
666 int pages);
667int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
668 int pages, struct page **pagelist,
669 dma_addr_t *dma_addr, uint32_t flags);
670
671
672/*
673 * GPU MC structures, functions & helpers
674 */
675struct radeon_mc {
676 resource_size_t aper_size;
677 resource_size_t aper_base;
678 resource_size_t agp_base;
679 /* for some chips with <= 32MB we need to lie
680 * about vram size near mc fb location */
681 u64 mc_vram_size;
682 u64 visible_vram_size;
683 u64 gtt_size;
684 u64 gtt_start;
685 u64 gtt_end;
686 u64 vram_start;
687 u64 vram_end;
688 unsigned vram_width;
689 u64 real_vram_size;
690 int vram_mtrr;
691 bool vram_is_ddr;
692 bool igp_sideport_enabled;
693 u64 gtt_base_align;
694 u64 mc_mask;
695};
696
697bool radeon_combios_sideport_present(struct radeon_device *rdev);
698bool radeon_atombios_sideport_present(struct radeon_device *rdev);
699
700/*
701 * GPU scratch registers structures, functions & helpers
702 */
703struct radeon_scratch {
704 unsigned num_reg;
705 uint32_t reg_base;
706 bool free[32];
707 uint32_t reg[32];
708};
709
710int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
711void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
712
713/*
714 * GPU doorbell structures, functions & helpers
715 */
716#define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
717
718struct radeon_doorbell {
719 /* doorbell mmio */
720 resource_size_t base;
721 resource_size_t size;
722 u32 __iomem *ptr;
723 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
724 DECLARE_BITMAP(used, RADEON_MAX_DOORBELLS);
725};
726
727int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
728void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
729void radeon_doorbell_get_kfd_info(struct radeon_device *rdev,
730 phys_addr_t *aperture_base,
731 size_t *aperture_size,
732 size_t *start_offset);
733
734/*
735 * IRQS.
736 */
737
738struct radeon_flip_work {
739 struct work_struct flip_work;
740 struct work_struct unpin_work;
741 struct radeon_device *rdev;
742 int crtc_id;
743 uint64_t base;
744 struct drm_pending_vblank_event *event;
745 struct radeon_bo *old_rbo;
746 struct fence *fence;
747};
748
749struct r500_irq_stat_regs {
750 u32 disp_int;
751 u32 hdmi0_status;
752};
753
754struct r600_irq_stat_regs {
755 u32 disp_int;
756 u32 disp_int_cont;
757 u32 disp_int_cont2;
758 u32 d1grph_int;
759 u32 d2grph_int;
760 u32 hdmi0_status;
761 u32 hdmi1_status;
762};
763
764struct evergreen_irq_stat_regs {
765 u32 disp_int;
766 u32 disp_int_cont;
767 u32 disp_int_cont2;
768 u32 disp_int_cont3;
769 u32 disp_int_cont4;
770 u32 disp_int_cont5;
771 u32 d1grph_int;
772 u32 d2grph_int;
773 u32 d3grph_int;
774 u32 d4grph_int;
775 u32 d5grph_int;
776 u32 d6grph_int;
777 u32 afmt_status1;
778 u32 afmt_status2;
779 u32 afmt_status3;
780 u32 afmt_status4;
781 u32 afmt_status5;
782 u32 afmt_status6;
783};
784
785struct cik_irq_stat_regs {
786 u32 disp_int;
787 u32 disp_int_cont;
788 u32 disp_int_cont2;
789 u32 disp_int_cont3;
790 u32 disp_int_cont4;
791 u32 disp_int_cont5;
792 u32 disp_int_cont6;
793 u32 d1grph_int;
794 u32 d2grph_int;
795 u32 d3grph_int;
796 u32 d4grph_int;
797 u32 d5grph_int;
798 u32 d6grph_int;
799};
800
801union radeon_irq_stat_regs {
802 struct r500_irq_stat_regs r500;
803 struct r600_irq_stat_regs r600;
804 struct evergreen_irq_stat_regs evergreen;
805 struct cik_irq_stat_regs cik;
806};
807
808struct radeon_irq {
809 bool installed;
810 spinlock_t lock;
811 atomic_t ring_int[RADEON_NUM_RINGS];
812 bool crtc_vblank_int[RADEON_MAX_CRTCS];
813 atomic_t pflip[RADEON_MAX_CRTCS];
814 wait_queue_head_t vblank_queue;
815 bool hpd[RADEON_MAX_HPD_PINS];
816 bool afmt[RADEON_MAX_AFMT_BLOCKS];
817 union radeon_irq_stat_regs stat_regs;
818 bool dpm_thermal;
819};
820
821int radeon_irq_kms_init(struct radeon_device *rdev);
822void radeon_irq_kms_fini(struct radeon_device *rdev);
823void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
824bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring);
825void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
826void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
827void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
828void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
829void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
830void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
831void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
832
833/*
834 * CP & rings.
835 */
836
837struct radeon_ib {
838 struct radeon_sa_bo *sa_bo;
839 uint32_t length_dw;
840 uint64_t gpu_addr;
841 uint32_t *ptr;
842 int ring;
843 struct radeon_fence *fence;
844 struct radeon_vm *vm;
845 bool is_const_ib;
846 struct radeon_sync sync;
847};
848
849struct radeon_ring {
850 struct radeon_bo *ring_obj;
851 volatile uint32_t *ring;
852 unsigned rptr_offs;
853 unsigned rptr_save_reg;
854 u64 next_rptr_gpu_addr;
855 volatile u32 *next_rptr_cpu_addr;
856 unsigned wptr;
857 unsigned wptr_old;
858 unsigned ring_size;
859 unsigned ring_free_dw;
860 int count_dw;
861 atomic_t last_rptr;
862 atomic64_t last_activity;
863 uint64_t gpu_addr;
864 uint32_t align_mask;
865 uint32_t ptr_mask;
866 bool ready;
867 u32 nop;
868 u32 idx;
869 u64 last_semaphore_signal_addr;
870 u64 last_semaphore_wait_addr;
871 /* for CIK queues */
872 u32 me;
873 u32 pipe;
874 u32 queue;
875 struct radeon_bo *mqd_obj;
876 u32 doorbell_index;
877 unsigned wptr_offs;
878};
879
880struct radeon_mec {
881 struct radeon_bo *hpd_eop_obj;
882 u64 hpd_eop_gpu_addr;
883 u32 num_pipe;
884 u32 num_mec;
885 u32 num_queue;
886};
887
888/*
889 * VM
890 */
891
892/* maximum number of VMIDs */
893#define RADEON_NUM_VM 16
894
895/* number of entries in page table */
896#define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
897
898/* PTBs (Page Table Blocks) need to be aligned to 32K */
899#define RADEON_VM_PTB_ALIGN_SIZE 32768
900#define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
901#define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
902
903#define R600_PTE_VALID (1 << 0)
904#define R600_PTE_SYSTEM (1 << 1)
905#define R600_PTE_SNOOPED (1 << 2)
906#define R600_PTE_READABLE (1 << 5)
907#define R600_PTE_WRITEABLE (1 << 6)
908
909/* PTE (Page Table Entry) fragment field for different page sizes */
910#define R600_PTE_FRAG_4KB (0 << 7)
911#define R600_PTE_FRAG_64KB (4 << 7)
912#define R600_PTE_FRAG_256KB (6 << 7)
913
914/* flags needed to be set so we can copy directly from the GART table */
915#define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \
916 R600_PTE_SYSTEM | R600_PTE_VALID )
917
918struct radeon_vm_pt {
919 struct radeon_bo *bo;
920 uint64_t addr;
921};
922
923struct radeon_vm_id {
924 unsigned id;
925 uint64_t pd_gpu_addr;
926 /* last flushed PD/PT update */
927 struct radeon_fence *flushed_updates;
928 /* last use of vmid */
929 struct radeon_fence *last_id_use;
930};
931
932struct radeon_vm {
933 struct mutex mutex;
934
935 struct rb_root va;
936
937 /* protecting invalidated and freed */
938 spinlock_t status_lock;
939
940 /* BOs moved, but not yet updated in the PT */
941 struct list_head invalidated;
942
943 /* BOs freed, but not yet updated in the PT */
944 struct list_head freed;
945
946 /* BOs cleared in the PT */
947 struct list_head cleared;
948
949 /* contains the page directory */
950 struct radeon_bo *page_directory;
951 unsigned max_pde_used;
952
953 /* array of page tables, one for each page directory entry */
954 struct radeon_vm_pt *page_tables;
955
956 struct radeon_bo_va *ib_bo_va;
957
958 /* for id and flush management per ring */
959 struct radeon_vm_id ids[RADEON_NUM_RINGS];
960};
961
962struct radeon_vm_manager {
963 struct radeon_fence *active[RADEON_NUM_VM];
964 uint32_t max_pfn;
965 /* number of VMIDs */
966 unsigned nvm;
967 /* vram base address for page table entry */
968 u64 vram_base_offset;
969 /* is vm enabled? */
970 bool enabled;
971 /* for hw to save the PD addr on suspend/resume */
972 uint32_t saved_table_addr[RADEON_NUM_VM];
973};
974
975/*
976 * file private structure
977 */
978struct radeon_fpriv {
979 struct radeon_vm vm;
980};
981
982/*
983 * R6xx+ IH ring
984 */
985struct r600_ih {
986 struct radeon_bo *ring_obj;
987 volatile uint32_t *ring;
988 unsigned rptr;
989 unsigned ring_size;
990 uint64_t gpu_addr;
991 uint32_t ptr_mask;
992 atomic_t lock;
993 bool enabled;
994};
995
996/*
997 * RLC stuff
998 */
999#include "clearstate_defs.h"
1000
1001struct radeon_rlc {
1002 /* for power gating */
1003 struct radeon_bo *save_restore_obj;
1004 uint64_t save_restore_gpu_addr;
1005 volatile uint32_t *sr_ptr;
1006 const u32 *reg_list;
1007 u32 reg_list_size;
1008 /* for clear state */
1009 struct radeon_bo *clear_state_obj;
1010 uint64_t clear_state_gpu_addr;
1011 volatile uint32_t *cs_ptr;
1012 const struct cs_section_def *cs_data;
1013 u32 clear_state_size;
1014 /* for cp tables */
1015 struct radeon_bo *cp_table_obj;
1016 uint64_t cp_table_gpu_addr;
1017 volatile uint32_t *cp_table_ptr;
1018 u32 cp_table_size;
1019};
1020
1021int radeon_ib_get(struct radeon_device *rdev, int ring,
1022 struct radeon_ib *ib, struct radeon_vm *vm,
1023 unsigned size);
1024void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
1025int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
1026 struct radeon_ib *const_ib, bool hdp_flush);
1027int radeon_ib_pool_init(struct radeon_device *rdev);
1028void radeon_ib_pool_fini(struct radeon_device *rdev);
1029int radeon_ib_ring_tests(struct radeon_device *rdev);
1030/* Ring access between begin & end cannot sleep */
1031bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
1032 struct radeon_ring *ring);
1033void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
1034int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1035int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1036void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1037 bool hdp_flush);
1038void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1039 bool hdp_flush);
1040void radeon_ring_undo(struct radeon_ring *ring);
1041void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
1042int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
1043void radeon_ring_lockup_update(struct radeon_device *rdev,
1044 struct radeon_ring *ring);
1045bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
1046unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
1047 uint32_t **data);
1048int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
1049 unsigned size, uint32_t *data);
1050int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
1051 unsigned rptr_offs, u32 nop);
1052void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
1053
1054
1055/* r600 async dma */
1056void r600_dma_stop(struct radeon_device *rdev);
1057int r600_dma_resume(struct radeon_device *rdev);
1058void r600_dma_fini(struct radeon_device *rdev);
1059
1060void cayman_dma_stop(struct radeon_device *rdev);
1061int cayman_dma_resume(struct radeon_device *rdev);
1062void cayman_dma_fini(struct radeon_device *rdev);
1063
1064/*
1065 * CS.
1066 */
1067struct radeon_cs_chunk {
1068 uint32_t length_dw;
1069 uint32_t *kdata;
1070 void __user *user_ptr;
1071};
1072
1073struct radeon_cs_parser {
1074 struct device *dev;
1075 struct radeon_device *rdev;
1076 struct drm_file *filp;
1077 /* chunks */
1078 unsigned nchunks;
1079 struct radeon_cs_chunk *chunks;
1080 uint64_t *chunks_array;
1081 /* IB */
1082 unsigned idx;
1083 /* relocations */
1084 unsigned nrelocs;
1085 struct radeon_bo_list *relocs;
1086 struct radeon_bo_list *vm_bos;
1087 struct list_head validated;
1088 unsigned dma_reloc_idx;
1089 /* indices of various chunks */
1090 struct radeon_cs_chunk *chunk_ib;
1091 struct radeon_cs_chunk *chunk_relocs;
1092 struct radeon_cs_chunk *chunk_flags;
1093 struct radeon_cs_chunk *chunk_const_ib;
1094 struct radeon_ib ib;
1095 struct radeon_ib const_ib;
1096 void *track;
1097 unsigned family;
1098 int parser_error;
1099 u32 cs_flags;
1100 u32 ring;
1101 s32 priority;
1102 struct ww_acquire_ctx ticket;
1103};
1104
1105static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1106{
1107 struct radeon_cs_chunk *ibc = p->chunk_ib;
1108
1109 if (ibc->kdata)
1110 return ibc->kdata[idx];
1111 return p->ib.ptr[idx];
1112}
1113
1114
1115struct radeon_cs_packet {
1116 unsigned idx;
1117 unsigned type;
1118 unsigned reg;
1119 unsigned opcode;
1120 int count;
1121 unsigned one_reg_wr;
1122};
1123
1124typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1125 struct radeon_cs_packet *pkt,
1126 unsigned idx, unsigned reg);
1127typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1128 struct radeon_cs_packet *pkt);
1129
1130
1131/*
1132 * AGP
1133 */
1134int radeon_agp_init(struct radeon_device *rdev);
1135void radeon_agp_resume(struct radeon_device *rdev);
1136void radeon_agp_suspend(struct radeon_device *rdev);
1137void radeon_agp_fini(struct radeon_device *rdev);
1138
1139
1140/*
1141 * Writeback
1142 */
1143struct radeon_wb {
1144 struct radeon_bo *wb_obj;
1145 volatile uint32_t *wb;
1146 uint64_t gpu_addr;
1147 bool enabled;
1148 bool use_event;
1149};
1150
1151#define RADEON_WB_SCRATCH_OFFSET 0
1152#define RADEON_WB_RING0_NEXT_RPTR 256
1153#define RADEON_WB_CP_RPTR_OFFSET 1024
1154#define RADEON_WB_CP1_RPTR_OFFSET 1280
1155#define RADEON_WB_CP2_RPTR_OFFSET 1536
1156#define R600_WB_DMA_RPTR_OFFSET 1792
1157#define R600_WB_IH_WPTR_OFFSET 2048
1158#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
1159#define R600_WB_EVENT_OFFSET 3072
1160#define CIK_WB_CP1_WPTR_OFFSET 3328
1161#define CIK_WB_CP2_WPTR_OFFSET 3584
1162#define R600_WB_DMA_RING_TEST_OFFSET 3588
1163#define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592
1164
1165/**
1166 * struct radeon_pm - power management datas
1167 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1168 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1169 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1170 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1171 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1172 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1173 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1174 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1175 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
1176 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
1177 * @needed_bandwidth: current bandwidth needs
1178 *
1179 * It keeps track of various data needed to take powermanagement decision.
1180 * Bandwidth need is used to determine minimun clock of the GPU and memory.
1181 * Equation between gpu/memory clock and available bandwidth is hw dependent
1182 * (type of memory, bus size, efficiency, ...)
1183 */
1184
1185enum radeon_pm_method {
1186 PM_METHOD_PROFILE,
1187 PM_METHOD_DYNPM,
1188 PM_METHOD_DPM,
1189};
1190
1191enum radeon_dynpm_state {
1192 DYNPM_STATE_DISABLED,
1193 DYNPM_STATE_MINIMUM,
1194 DYNPM_STATE_PAUSED,
1195 DYNPM_STATE_ACTIVE,
1196 DYNPM_STATE_SUSPENDED,
1197};
1198enum radeon_dynpm_action {
1199 DYNPM_ACTION_NONE,
1200 DYNPM_ACTION_MINIMUM,
1201 DYNPM_ACTION_DOWNCLOCK,
1202 DYNPM_ACTION_UPCLOCK,
1203 DYNPM_ACTION_DEFAULT
1204};
1205
1206enum radeon_voltage_type {
1207 VOLTAGE_NONE = 0,
1208 VOLTAGE_GPIO,
1209 VOLTAGE_VDDC,
1210 VOLTAGE_SW
1211};
1212
1213enum radeon_pm_state_type {
1214 /* not used for dpm */
1215 POWER_STATE_TYPE_DEFAULT,
1216 POWER_STATE_TYPE_POWERSAVE,
1217 /* user selectable states */
1218 POWER_STATE_TYPE_BATTERY,
1219 POWER_STATE_TYPE_BALANCED,
1220 POWER_STATE_TYPE_PERFORMANCE,
1221 /* internal states */
1222 POWER_STATE_TYPE_INTERNAL_UVD,
1223 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1224 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1225 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1226 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1227 POWER_STATE_TYPE_INTERNAL_BOOT,
1228 POWER_STATE_TYPE_INTERNAL_THERMAL,
1229 POWER_STATE_TYPE_INTERNAL_ACPI,
1230 POWER_STATE_TYPE_INTERNAL_ULV,
1231 POWER_STATE_TYPE_INTERNAL_3DPERF,
1232};
1233
1234enum radeon_pm_profile_type {
1235 PM_PROFILE_DEFAULT,
1236 PM_PROFILE_AUTO,
1237 PM_PROFILE_LOW,
1238 PM_PROFILE_MID,
1239 PM_PROFILE_HIGH,
1240};
1241
1242#define PM_PROFILE_DEFAULT_IDX 0
1243#define PM_PROFILE_LOW_SH_IDX 1
1244#define PM_PROFILE_MID_SH_IDX 2
1245#define PM_PROFILE_HIGH_SH_IDX 3
1246#define PM_PROFILE_LOW_MH_IDX 4
1247#define PM_PROFILE_MID_MH_IDX 5
1248#define PM_PROFILE_HIGH_MH_IDX 6
1249#define PM_PROFILE_MAX 7
1250
1251struct radeon_pm_profile {
1252 int dpms_off_ps_idx;
1253 int dpms_on_ps_idx;
1254 int dpms_off_cm_idx;
1255 int dpms_on_cm_idx;
1256};
1257
1258enum radeon_int_thermal_type {
1259 THERMAL_TYPE_NONE,
1260 THERMAL_TYPE_EXTERNAL,
1261 THERMAL_TYPE_EXTERNAL_GPIO,
1262 THERMAL_TYPE_RV6XX,
1263 THERMAL_TYPE_RV770,
1264 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1265 THERMAL_TYPE_EVERGREEN,
1266 THERMAL_TYPE_SUMO,
1267 THERMAL_TYPE_NI,
1268 THERMAL_TYPE_SI,
1269 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1270 THERMAL_TYPE_CI,
1271 THERMAL_TYPE_KV,
1272};
1273
1274struct radeon_voltage {
1275 enum radeon_voltage_type type;
1276 /* gpio voltage */
1277 struct radeon_gpio_rec gpio;
1278 u32 delay; /* delay in usec from voltage drop to sclk change */
1279 bool active_high; /* voltage drop is active when bit is high */
1280 /* VDDC voltage */
1281 u8 vddc_id; /* index into vddc voltage table */
1282 u8 vddci_id; /* index into vddci voltage table */
1283 bool vddci_enabled;
1284 /* r6xx+ sw */
1285 u16 voltage;
1286 /* evergreen+ vddci */
1287 u16 vddci;
1288};
1289
1290/* clock mode flags */
1291#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1292
1293struct radeon_pm_clock_info {
1294 /* memory clock */
1295 u32 mclk;
1296 /* engine clock */
1297 u32 sclk;
1298 /* voltage info */
1299 struct radeon_voltage voltage;
1300 /* standardized clock flags */
1301 u32 flags;
1302};
1303
1304/* state flags */
1305#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1306
1307struct radeon_power_state {
1308 enum radeon_pm_state_type type;
1309 struct radeon_pm_clock_info *clock_info;
1310 /* number of valid clock modes in this power state */
1311 int num_clock_modes;
1312 struct radeon_pm_clock_info *default_clock_mode;
1313 /* standardized state flags */
1314 u32 flags;
1315 u32 misc; /* vbios specific flags */
1316 u32 misc2; /* vbios specific flags */
1317 int pcie_lanes; /* pcie lanes */
1318};
1319
1320/*
1321 * Some modes are overclocked by very low value, accept them
1322 */
1323#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1324
1325enum radeon_dpm_auto_throttle_src {
1326 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1327 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1328};
1329
1330enum radeon_dpm_event_src {
1331 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1332 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1333 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1334 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1335 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1336};
1337
1338#define RADEON_MAX_VCE_LEVELS 6
1339
1340enum radeon_vce_level {
1341 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1342 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1343 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1344 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1345 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1346 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1347};
1348
1349struct radeon_ps {
1350 u32 caps; /* vbios flags */
1351 u32 class; /* vbios flags */
1352 u32 class2; /* vbios flags */
1353 /* UVD clocks */
1354 u32 vclk;
1355 u32 dclk;
1356 /* VCE clocks */
1357 u32 evclk;
1358 u32 ecclk;
1359 bool vce_active;
1360 enum radeon_vce_level vce_level;
1361 /* asic priv */
1362 void *ps_priv;
1363};
1364
1365struct radeon_dpm_thermal {
1366 /* thermal interrupt work */
1367 struct work_struct work;
1368 /* low temperature threshold */
1369 int min_temp;
1370 /* high temperature threshold */
1371 int max_temp;
1372 /* was interrupt low to high or high to low */
1373 bool high_to_low;
1374};
1375
1376enum radeon_clk_action
1377{
1378 RADEON_SCLK_UP = 1,
1379 RADEON_SCLK_DOWN
1380};
1381
1382struct radeon_blacklist_clocks
1383{
1384 u32 sclk;
1385 u32 mclk;
1386 enum radeon_clk_action action;
1387};
1388
1389struct radeon_clock_and_voltage_limits {
1390 u32 sclk;
1391 u32 mclk;
1392 u16 vddc;
1393 u16 vddci;
1394};
1395
1396struct radeon_clock_array {
1397 u32 count;
1398 u32 *values;
1399};
1400
1401struct radeon_clock_voltage_dependency_entry {
1402 u32 clk;
1403 u16 v;
1404};
1405
1406struct radeon_clock_voltage_dependency_table {
1407 u32 count;
1408 struct radeon_clock_voltage_dependency_entry *entries;
1409};
1410
1411union radeon_cac_leakage_entry {
1412 struct {
1413 u16 vddc;
1414 u32 leakage;
1415 };
1416 struct {
1417 u16 vddc1;
1418 u16 vddc2;
1419 u16 vddc3;
1420 };
1421};
1422
1423struct radeon_cac_leakage_table {
1424 u32 count;
1425 union radeon_cac_leakage_entry *entries;
1426};
1427
1428struct radeon_phase_shedding_limits_entry {
1429 u16 voltage;
1430 u32 sclk;
1431 u32 mclk;
1432};
1433
1434struct radeon_phase_shedding_limits_table {
1435 u32 count;
1436 struct radeon_phase_shedding_limits_entry *entries;
1437};
1438
1439struct radeon_uvd_clock_voltage_dependency_entry {
1440 u32 vclk;
1441 u32 dclk;
1442 u16 v;
1443};
1444
1445struct radeon_uvd_clock_voltage_dependency_table {
1446 u8 count;
1447 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1448};
1449
1450struct radeon_vce_clock_voltage_dependency_entry {
1451 u32 ecclk;
1452 u32 evclk;
1453 u16 v;
1454};
1455
1456struct radeon_vce_clock_voltage_dependency_table {
1457 u8 count;
1458 struct radeon_vce_clock_voltage_dependency_entry *entries;
1459};
1460
1461struct radeon_ppm_table {
1462 u8 ppm_design;
1463 u16 cpu_core_number;
1464 u32 platform_tdp;
1465 u32 small_ac_platform_tdp;
1466 u32 platform_tdc;
1467 u32 small_ac_platform_tdc;
1468 u32 apu_tdp;
1469 u32 dgpu_tdp;
1470 u32 dgpu_ulv_power;
1471 u32 tj_max;
1472};
1473
1474struct radeon_cac_tdp_table {
1475 u16 tdp;
1476 u16 configurable_tdp;
1477 u16 tdc;
1478 u16 battery_power_limit;
1479 u16 small_power_limit;
1480 u16 low_cac_leakage;
1481 u16 high_cac_leakage;
1482 u16 maximum_power_delivery_limit;
1483};
1484
1485struct radeon_dpm_dynamic_state {
1486 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1487 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1488 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
1489 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1490 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1491 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1492 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1493 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1494 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1495 struct radeon_clock_array valid_sclk_values;
1496 struct radeon_clock_array valid_mclk_values;
1497 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1498 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1499 u32 mclk_sclk_ratio;
1500 u32 sclk_mclk_delta;
1501 u16 vddc_vddci_delta;
1502 u16 min_vddc_for_pcie_gen2;
1503 struct radeon_cac_leakage_table cac_leakage_table;
1504 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
1505 struct radeon_ppm_table *ppm_table;
1506 struct radeon_cac_tdp_table *cac_tdp_table;
1507};
1508
1509struct radeon_dpm_fan {
1510 u16 t_min;
1511 u16 t_med;
1512 u16 t_high;
1513 u16 pwm_min;
1514 u16 pwm_med;
1515 u16 pwm_high;
1516 u8 t_hyst;
1517 u32 cycle_delay;
1518 u16 t_max;
1519 u8 control_mode;
1520 u16 default_max_fan_pwm;
1521 u16 default_fan_output_sensitivity;
1522 u16 fan_output_sensitivity;
1523 bool ucode_fan_control;
1524};
1525
1526enum radeon_pcie_gen {
1527 RADEON_PCIE_GEN1 = 0,
1528 RADEON_PCIE_GEN2 = 1,
1529 RADEON_PCIE_GEN3 = 2,
1530 RADEON_PCIE_GEN_INVALID = 0xffff
1531};
1532
1533enum radeon_dpm_forced_level {
1534 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1535 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1536 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1537};
1538
1539struct radeon_vce_state {
1540 /* vce clocks */
1541 u32 evclk;
1542 u32 ecclk;
1543 /* gpu clocks */
1544 u32 sclk;
1545 u32 mclk;
1546 u8 clk_idx;
1547 u8 pstate;
1548};
1549
1550struct radeon_dpm {
1551 struct radeon_ps *ps;
1552 /* number of valid power states */
1553 int num_ps;
1554 /* current power state that is active */
1555 struct radeon_ps *current_ps;
1556 /* requested power state */
1557 struct radeon_ps *requested_ps;
1558 /* boot up power state */
1559 struct radeon_ps *boot_ps;
1560 /* default uvd power state */
1561 struct radeon_ps *uvd_ps;
1562 /* vce requirements */
1563 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1564 enum radeon_vce_level vce_level;
1565 enum radeon_pm_state_type state;
1566 enum radeon_pm_state_type user_state;
1567 u32 platform_caps;
1568 u32 voltage_response_time;
1569 u32 backbias_response_time;
1570 void *priv;
1571 u32 new_active_crtcs;
1572 int new_active_crtc_count;
1573 u32 current_active_crtcs;
1574 int current_active_crtc_count;
1575 bool single_display;
1576 struct radeon_dpm_dynamic_state dyn_state;
1577 struct radeon_dpm_fan fan;
1578 u32 tdp_limit;
1579 u32 near_tdp_limit;
1580 u32 near_tdp_limit_adjusted;
1581 u32 sq_ramping_threshold;
1582 u32 cac_leakage;
1583 u16 tdp_od_limit;
1584 u32 tdp_adjustment;
1585 u16 load_line_slope;
1586 bool power_control;
1587 bool ac_power;
1588 /* special states active */
1589 bool thermal_active;
1590 bool uvd_active;
1591 bool vce_active;
1592 /* thermal handling */
1593 struct radeon_dpm_thermal thermal;
1594 /* forced levels */
1595 enum radeon_dpm_forced_level forced_level;
1596 /* track UVD streams */
1597 unsigned sd;
1598 unsigned hd;
1599};
1600
1601void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
1602void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
1603
1604struct radeon_pm {
1605 struct mutex mutex;
1606 /* write locked while reprogramming mclk */
1607 struct rw_semaphore mclk_lock;
1608 u32 active_crtcs;
1609 int active_crtc_count;
1610 int req_vblank;
1611 bool vblank_sync;
1612 fixed20_12 max_bandwidth;
1613 fixed20_12 igp_sideport_mclk;
1614 fixed20_12 igp_system_mclk;
1615 fixed20_12 igp_ht_link_clk;
1616 fixed20_12 igp_ht_link_width;
1617 fixed20_12 k8_bandwidth;
1618 fixed20_12 sideport_bandwidth;
1619 fixed20_12 ht_bandwidth;
1620 fixed20_12 core_bandwidth;
1621 fixed20_12 sclk;
1622 fixed20_12 mclk;
1623 fixed20_12 needed_bandwidth;
1624 struct radeon_power_state *power_state;
1625 /* number of valid power states */
1626 int num_power_states;
1627 int current_power_state_index;
1628 int current_clock_mode_index;
1629 int requested_power_state_index;
1630 int requested_clock_mode_index;
1631 int default_power_state_index;
1632 u32 current_sclk;
1633 u32 current_mclk;
1634 u16 current_vddc;
1635 u16 current_vddci;
1636 u32 default_sclk;
1637 u32 default_mclk;
1638 u16 default_vddc;
1639 u16 default_vddci;
1640 struct radeon_i2c_chan *i2c_bus;
1641 /* selected pm method */
1642 enum radeon_pm_method pm_method;
1643 /* dynpm power management */
1644 struct delayed_work dynpm_idle_work;
1645 enum radeon_dynpm_state dynpm_state;
1646 enum radeon_dynpm_action dynpm_planned_action;
1647 unsigned long dynpm_action_timeout;
1648 bool dynpm_can_upclock;
1649 bool dynpm_can_downclock;
1650 /* profile-based power management */
1651 enum radeon_pm_profile_type profile;
1652 int profile_index;
1653 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1654 /* internal thermal controller on rv6xx+ */
1655 enum radeon_int_thermal_type int_thermal_type;
1656 struct device *int_hwmon_dev;
1657 /* fan control parameters */
1658 bool no_fan;
1659 u8 fan_pulses_per_revolution;
1660 u8 fan_min_rpm;
1661 u8 fan_max_rpm;
1662 /* dpm */
1663 bool dpm_enabled;
1664 bool sysfs_initialized;
1665 struct radeon_dpm dpm;
1666};
1667
1668int radeon_pm_get_type_index(struct radeon_device *rdev,
1669 enum radeon_pm_state_type ps_type,
1670 int instance);
1671/*
1672 * UVD
1673 */
1674#define RADEON_MAX_UVD_HANDLES 10
1675#define RADEON_UVD_STACK_SIZE (1024*1024)
1676#define RADEON_UVD_HEAP_SIZE (1024*1024)
1677
1678struct radeon_uvd {
1679 struct radeon_bo *vcpu_bo;
1680 void *cpu_addr;
1681 uint64_t gpu_addr;
1682 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1683 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
1684 unsigned img_size[RADEON_MAX_UVD_HANDLES];
1685 struct delayed_work idle_work;
1686};
1687
1688int radeon_uvd_init(struct radeon_device *rdev);
1689void radeon_uvd_fini(struct radeon_device *rdev);
1690int radeon_uvd_suspend(struct radeon_device *rdev);
1691int radeon_uvd_resume(struct radeon_device *rdev);
1692int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1693 uint32_t handle, struct radeon_fence **fence);
1694int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1695 uint32_t handle, struct radeon_fence **fence);
1696void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo,
1697 uint32_t allowed_domains);
1698void radeon_uvd_free_handles(struct radeon_device *rdev,
1699 struct drm_file *filp);
1700int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1701void radeon_uvd_note_usage(struct radeon_device *rdev);
1702int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1703 unsigned vclk, unsigned dclk,
1704 unsigned vco_min, unsigned vco_max,
1705 unsigned fb_factor, unsigned fb_mask,
1706 unsigned pd_min, unsigned pd_max,
1707 unsigned pd_even,
1708 unsigned *optimal_fb_div,
1709 unsigned *optimal_vclk_div,
1710 unsigned *optimal_dclk_div);
1711int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1712 unsigned cg_upll_func_cntl);
1713
1714/*
1715 * VCE
1716 */
1717#define RADEON_MAX_VCE_HANDLES 16
1718
1719struct radeon_vce {
1720 struct radeon_bo *vcpu_bo;
1721 uint64_t gpu_addr;
1722 unsigned fw_version;
1723 unsigned fb_version;
1724 atomic_t handles[RADEON_MAX_VCE_HANDLES];
1725 struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
1726 unsigned img_size[RADEON_MAX_VCE_HANDLES];
1727 struct delayed_work idle_work;
1728 uint32_t keyselect;
1729};
1730
1731int radeon_vce_init(struct radeon_device *rdev);
1732void radeon_vce_fini(struct radeon_device *rdev);
1733int radeon_vce_suspend(struct radeon_device *rdev);
1734int radeon_vce_resume(struct radeon_device *rdev);
1735int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1736 uint32_t handle, struct radeon_fence **fence);
1737int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1738 uint32_t handle, struct radeon_fence **fence);
1739void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
1740void radeon_vce_note_usage(struct radeon_device *rdev);
1741int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
1742int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1743bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1744 struct radeon_ring *ring,
1745 struct radeon_semaphore *semaphore,
1746 bool emit_wait);
1747void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1748void radeon_vce_fence_emit(struct radeon_device *rdev,
1749 struct radeon_fence *fence);
1750int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1751int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1752
1753struct r600_audio_pin {
1754 int channels;
1755 int rate;
1756 int bits_per_sample;
1757 u8 status_bits;
1758 u8 category_code;
1759 u32 offset;
1760 bool connected;
1761 u32 id;
1762};
1763
1764struct r600_audio {
1765 bool enabled;
1766 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1767 int num_pins;
1768 struct radeon_audio_funcs *hdmi_funcs;
1769 struct radeon_audio_funcs *dp_funcs;
1770 struct radeon_audio_basic_funcs *funcs;
1771};
1772
1773/*
1774 * Benchmarking
1775 */
1776void radeon_benchmark(struct radeon_device *rdev, int test_number);
1777
1778
1779/*
1780 * Testing
1781 */
1782void radeon_test_moves(struct radeon_device *rdev);
1783void radeon_test_ring_sync(struct radeon_device *rdev,
1784 struct radeon_ring *cpA,
1785 struct radeon_ring *cpB);
1786void radeon_test_syncing(struct radeon_device *rdev);
1787
1788/*
1789 * MMU Notifier
1790 */
1791#if defined(CONFIG_MMU_NOTIFIER)
1792int radeon_mn_register(struct radeon_bo *bo, unsigned long addr);
1793void radeon_mn_unregister(struct radeon_bo *bo);
1794#else
1795static inline int radeon_mn_register(struct radeon_bo *bo, unsigned long addr)
1796{
1797 return -ENODEV;
1798}
1799static inline void radeon_mn_unregister(struct radeon_bo *bo) {}
1800#endif
1801
1802/*
1803 * Debugfs
1804 */
1805struct radeon_debugfs {
1806 struct drm_info_list *files;
1807 unsigned num_files;
1808};
1809
1810int radeon_debugfs_add_files(struct radeon_device *rdev,
1811 struct drm_info_list *files,
1812 unsigned nfiles);
1813int radeon_debugfs_fence_init(struct radeon_device *rdev);
1814
1815/*
1816 * ASIC ring specific functions.
1817 */
1818struct radeon_asic_ring {
1819 /* ring read/write ptr handling */
1820 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1821 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1822 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1823
1824 /* validating and patching of IBs */
1825 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1826 int (*cs_parse)(struct radeon_cs_parser *p);
1827
1828 /* command emmit functions */
1829 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1830 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1831 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring);
1832 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1833 struct radeon_semaphore *semaphore, bool emit_wait);
1834 void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring,
1835 unsigned vm_id, uint64_t pd_addr);
1836
1837 /* testing functions */
1838 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1839 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1840 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1841
1842 /* deprecated */
1843 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1844};
1845
1846/*
1847 * ASIC specific functions.
1848 */
1849struct radeon_asic {
1850 int (*init)(struct radeon_device *rdev);
1851 void (*fini)(struct radeon_device *rdev);
1852 int (*resume)(struct radeon_device *rdev);
1853 int (*suspend)(struct radeon_device *rdev);
1854 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1855 int (*asic_reset)(struct radeon_device *rdev);
1856 /* Flush the HDP cache via MMIO */
1857 void (*mmio_hdp_flush)(struct radeon_device *rdev);
1858 /* check if 3D engine is idle */
1859 bool (*gui_idle)(struct radeon_device *rdev);
1860 /* wait for mc_idle */
1861 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1862 /* get the reference clock */
1863 u32 (*get_xclk)(struct radeon_device *rdev);
1864 /* get the gpu clock counter */
1865 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1866 /* get register for info ioctl */
1867 int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val);
1868 /* gart */
1869 struct {
1870 void (*tlb_flush)(struct radeon_device *rdev);
1871 uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags);
1872 void (*set_page)(struct radeon_device *rdev, unsigned i,
1873 uint64_t entry);
1874 } gart;
1875 struct {
1876 int (*init)(struct radeon_device *rdev);
1877 void (*fini)(struct radeon_device *rdev);
1878 void (*copy_pages)(struct radeon_device *rdev,
1879 struct radeon_ib *ib,
1880 uint64_t pe, uint64_t src,
1881 unsigned count);
1882 void (*write_pages)(struct radeon_device *rdev,
1883 struct radeon_ib *ib,
1884 uint64_t pe,
1885 uint64_t addr, unsigned count,
1886 uint32_t incr, uint32_t flags);
1887 void (*set_pages)(struct radeon_device *rdev,
1888 struct radeon_ib *ib,
1889 uint64_t pe,
1890 uint64_t addr, unsigned count,
1891 uint32_t incr, uint32_t flags);
1892 void (*pad_ib)(struct radeon_ib *ib);
1893 } vm;
1894 /* ring specific callbacks */
1895 const struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
1896 /* irqs */
1897 struct {
1898 int (*set)(struct radeon_device *rdev);
1899 int (*process)(struct radeon_device *rdev);
1900 } irq;
1901 /* displays */
1902 struct {
1903 /* display watermarks */
1904 void (*bandwidth_update)(struct radeon_device *rdev);
1905 /* get frame count */
1906 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1907 /* wait for vblank */
1908 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1909 /* set backlight level */
1910 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1911 /* get backlight level */
1912 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1913 /* audio callbacks */
1914 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1915 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1916 } display;
1917 /* copy functions for bo handling */
1918 struct {
1919 struct radeon_fence *(*blit)(struct radeon_device *rdev,
1920 uint64_t src_offset,
1921 uint64_t dst_offset,
1922 unsigned num_gpu_pages,
1923 struct reservation_object *resv);
1924 u32 blit_ring_index;
1925 struct radeon_fence *(*dma)(struct radeon_device *rdev,
1926 uint64_t src_offset,
1927 uint64_t dst_offset,
1928 unsigned num_gpu_pages,
1929 struct reservation_object *resv);
1930 u32 dma_ring_index;
1931 /* method used for bo copy */
1932 struct radeon_fence *(*copy)(struct radeon_device *rdev,
1933 uint64_t src_offset,
1934 uint64_t dst_offset,
1935 unsigned num_gpu_pages,
1936 struct reservation_object *resv);
1937 /* ring used for bo copies */
1938 u32 copy_ring_index;
1939 } copy;
1940 /* surfaces */
1941 struct {
1942 int (*set_reg)(struct radeon_device *rdev, int reg,
1943 uint32_t tiling_flags, uint32_t pitch,
1944 uint32_t offset, uint32_t obj_size);
1945 void (*clear_reg)(struct radeon_device *rdev, int reg);
1946 } surface;
1947 /* hotplug detect */
1948 struct {
1949 void (*init)(struct radeon_device *rdev);
1950 void (*fini)(struct radeon_device *rdev);
1951 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1952 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1953 } hpd;
1954 /* static power management */
1955 struct {
1956 void (*misc)(struct radeon_device *rdev);
1957 void (*prepare)(struct radeon_device *rdev);
1958 void (*finish)(struct radeon_device *rdev);
1959 void (*init_profile)(struct radeon_device *rdev);
1960 void (*get_dynpm_state)(struct radeon_device *rdev);
1961 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1962 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1963 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1964 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1965 int (*get_pcie_lanes)(struct radeon_device *rdev);
1966 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1967 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1968 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1969 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
1970 int (*get_temperature)(struct radeon_device *rdev);
1971 } pm;
1972 /* dynamic power management */
1973 struct {
1974 int (*init)(struct radeon_device *rdev);
1975 void (*setup_asic)(struct radeon_device *rdev);
1976 int (*enable)(struct radeon_device *rdev);
1977 int (*late_enable)(struct radeon_device *rdev);
1978 void (*disable)(struct radeon_device *rdev);
1979 int (*pre_set_power_state)(struct radeon_device *rdev);
1980 int (*set_power_state)(struct radeon_device *rdev);
1981 void (*post_set_power_state)(struct radeon_device *rdev);
1982 void (*display_configuration_changed)(struct radeon_device *rdev);
1983 void (*fini)(struct radeon_device *rdev);
1984 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1985 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1986 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1987 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
1988 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
1989 bool (*vblank_too_short)(struct radeon_device *rdev);
1990 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1991 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
1992 void (*fan_ctrl_set_mode)(struct radeon_device *rdev, u32 mode);
1993 u32 (*fan_ctrl_get_mode)(struct radeon_device *rdev);
1994 int (*set_fan_speed_percent)(struct radeon_device *rdev, u32 speed);
1995 int (*get_fan_speed_percent)(struct radeon_device *rdev, u32 *speed);
1996 u32 (*get_current_sclk)(struct radeon_device *rdev);
1997 u32 (*get_current_mclk)(struct radeon_device *rdev);
1998 } dpm;
1999 /* pageflipping */
2000 struct {
2001 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
2002 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);
2003 } pflip;
2004};
2005
2006/*
2007 * Asic structures
2008 */
2009struct r100_asic {
2010 const unsigned *reg_safe_bm;
2011 unsigned reg_safe_bm_size;
2012 u32 hdp_cntl;
2013};
2014
2015struct r300_asic {
2016 const unsigned *reg_safe_bm;
2017 unsigned reg_safe_bm_size;
2018 u32 resync_scratch;
2019 u32 hdp_cntl;
2020};
2021
2022struct r600_asic {
2023 unsigned max_pipes;
2024 unsigned max_tile_pipes;
2025 unsigned max_simds;
2026 unsigned max_backends;
2027 unsigned max_gprs;
2028 unsigned max_threads;
2029 unsigned max_stack_entries;
2030 unsigned max_hw_contexts;
2031 unsigned max_gs_threads;
2032 unsigned sx_max_export_size;
2033 unsigned sx_max_export_pos_size;
2034 unsigned sx_max_export_smx_size;
2035 unsigned sq_num_cf_insts;
2036 unsigned tiling_nbanks;
2037 unsigned tiling_npipes;
2038 unsigned tiling_group_size;
2039 unsigned tile_config;
2040 unsigned backend_map;
2041 unsigned active_simds;
2042};
2043
2044struct rv770_asic {
2045 unsigned max_pipes;
2046 unsigned max_tile_pipes;
2047 unsigned max_simds;
2048 unsigned max_backends;
2049 unsigned max_gprs;
2050 unsigned max_threads;
2051 unsigned max_stack_entries;
2052 unsigned max_hw_contexts;
2053 unsigned max_gs_threads;
2054 unsigned sx_max_export_size;
2055 unsigned sx_max_export_pos_size;
2056 unsigned sx_max_export_smx_size;
2057 unsigned sq_num_cf_insts;
2058 unsigned sx_num_of_sets;
2059 unsigned sc_prim_fifo_size;
2060 unsigned sc_hiz_tile_fifo_size;
2061 unsigned sc_earlyz_tile_fifo_fize;
2062 unsigned tiling_nbanks;
2063 unsigned tiling_npipes;
2064 unsigned tiling_group_size;
2065 unsigned tile_config;
2066 unsigned backend_map;
2067 unsigned active_simds;
2068};
2069
2070struct evergreen_asic {
2071 unsigned num_ses;
2072 unsigned max_pipes;
2073 unsigned max_tile_pipes;
2074 unsigned max_simds;
2075 unsigned max_backends;
2076 unsigned max_gprs;
2077 unsigned max_threads;
2078 unsigned max_stack_entries;
2079 unsigned max_hw_contexts;
2080 unsigned max_gs_threads;
2081 unsigned sx_max_export_size;
2082 unsigned sx_max_export_pos_size;
2083 unsigned sx_max_export_smx_size;
2084 unsigned sq_num_cf_insts;
2085 unsigned sx_num_of_sets;
2086 unsigned sc_prim_fifo_size;
2087 unsigned sc_hiz_tile_fifo_size;
2088 unsigned sc_earlyz_tile_fifo_size;
2089 unsigned tiling_nbanks;
2090 unsigned tiling_npipes;
2091 unsigned tiling_group_size;
2092 unsigned tile_config;
2093 unsigned backend_map;
2094 unsigned active_simds;
2095};
2096
2097struct cayman_asic {
2098 unsigned max_shader_engines;
2099 unsigned max_pipes_per_simd;
2100 unsigned max_tile_pipes;
2101 unsigned max_simds_per_se;
2102 unsigned max_backends_per_se;
2103 unsigned max_texture_channel_caches;
2104 unsigned max_gprs;
2105 unsigned max_threads;
2106 unsigned max_gs_threads;
2107 unsigned max_stack_entries;
2108 unsigned sx_num_of_sets;
2109 unsigned sx_max_export_size;
2110 unsigned sx_max_export_pos_size;
2111 unsigned sx_max_export_smx_size;
2112 unsigned max_hw_contexts;
2113 unsigned sq_num_cf_insts;
2114 unsigned sc_prim_fifo_size;
2115 unsigned sc_hiz_tile_fifo_size;
2116 unsigned sc_earlyz_tile_fifo_size;
2117
2118 unsigned num_shader_engines;
2119 unsigned num_shader_pipes_per_simd;
2120 unsigned num_tile_pipes;
2121 unsigned num_simds_per_se;
2122 unsigned num_backends_per_se;
2123 unsigned backend_disable_mask_per_asic;
2124 unsigned backend_map;
2125 unsigned num_texture_channel_caches;
2126 unsigned mem_max_burst_length_bytes;
2127 unsigned mem_row_size_in_kb;
2128 unsigned shader_engine_tile_size;
2129 unsigned num_gpus;
2130 unsigned multi_gpu_tile_size;
2131
2132 unsigned tile_config;
2133 unsigned active_simds;
2134};
2135
2136struct si_asic {
2137 unsigned max_shader_engines;
2138 unsigned max_tile_pipes;
2139 unsigned max_cu_per_sh;
2140 unsigned max_sh_per_se;
2141 unsigned max_backends_per_se;
2142 unsigned max_texture_channel_caches;
2143 unsigned max_gprs;
2144 unsigned max_gs_threads;
2145 unsigned max_hw_contexts;
2146 unsigned sc_prim_fifo_size_frontend;
2147 unsigned sc_prim_fifo_size_backend;
2148 unsigned sc_hiz_tile_fifo_size;
2149 unsigned sc_earlyz_tile_fifo_size;
2150
2151 unsigned num_tile_pipes;
2152 unsigned backend_enable_mask;
2153 unsigned backend_disable_mask_per_asic;
2154 unsigned backend_map;
2155 unsigned num_texture_channel_caches;
2156 unsigned mem_max_burst_length_bytes;
2157 unsigned mem_row_size_in_kb;
2158 unsigned shader_engine_tile_size;
2159 unsigned num_gpus;
2160 unsigned multi_gpu_tile_size;
2161
2162 unsigned tile_config;
2163 uint32_t tile_mode_array[32];
2164 uint32_t active_cus;
2165};
2166
2167struct cik_asic {
2168 unsigned max_shader_engines;
2169 unsigned max_tile_pipes;
2170 unsigned max_cu_per_sh;
2171 unsigned max_sh_per_se;
2172 unsigned max_backends_per_se;
2173 unsigned max_texture_channel_caches;
2174 unsigned max_gprs;
2175 unsigned max_gs_threads;
2176 unsigned max_hw_contexts;
2177 unsigned sc_prim_fifo_size_frontend;
2178 unsigned sc_prim_fifo_size_backend;
2179 unsigned sc_hiz_tile_fifo_size;
2180 unsigned sc_earlyz_tile_fifo_size;
2181
2182 unsigned num_tile_pipes;
2183 unsigned backend_enable_mask;
2184 unsigned backend_disable_mask_per_asic;
2185 unsigned backend_map;
2186 unsigned num_texture_channel_caches;
2187 unsigned mem_max_burst_length_bytes;
2188 unsigned mem_row_size_in_kb;
2189 unsigned shader_engine_tile_size;
2190 unsigned num_gpus;
2191 unsigned multi_gpu_tile_size;
2192
2193 unsigned tile_config;
2194 uint32_t tile_mode_array[32];
2195 uint32_t macrotile_mode_array[16];
2196 uint32_t active_cus;
2197};
2198
2199union radeon_asic_config {
2200 struct r300_asic r300;
2201 struct r100_asic r100;
2202 struct r600_asic r600;
2203 struct rv770_asic rv770;
2204 struct evergreen_asic evergreen;
2205 struct cayman_asic cayman;
2206 struct si_asic si;
2207 struct cik_asic cik;
2208};
2209
2210/*
2211 * asic initizalization from radeon_asic.c
2212 */
2213void radeon_agp_disable(struct radeon_device *rdev);
2214int radeon_asic_init(struct radeon_device *rdev);
2215
2216
2217/*
2218 * IOCTL.
2219 */
2220int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2221 struct drm_file *filp);
2222int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2223 struct drm_file *filp);
2224int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data,
2225 struct drm_file *filp);
2226int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2227 struct drm_file *file_priv);
2228int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2229 struct drm_file *file_priv);
2230int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2231 struct drm_file *file_priv);
2232int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2233 struct drm_file *file_priv);
2234int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2235 struct drm_file *filp);
2236int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2237 struct drm_file *filp);
2238int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2239 struct drm_file *filp);
2240int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2241 struct drm_file *filp);
2242int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2243 struct drm_file *filp);
2244int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2245 struct drm_file *filp);
2246int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
2247int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2248 struct drm_file *filp);
2249int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2250 struct drm_file *filp);
2251
2252/* VRAM scratch page for HDP bug, default vram page */
2253struct r600_vram_scratch {
2254 struct radeon_bo *robj;
2255 volatile uint32_t *ptr;
2256 u64 gpu_addr;
2257};
2258
2259/*
2260 * ACPI
2261 */
2262struct radeon_atif_notification_cfg {
2263 bool enabled;
2264 int command_code;
2265};
2266
2267struct radeon_atif_notifications {
2268 bool display_switch;
2269 bool expansion_mode_change;
2270 bool thermal_state;
2271 bool forced_power_state;
2272 bool system_power_state;
2273 bool display_conf_change;
2274 bool px_gfx_switch;
2275 bool brightness_change;
2276 bool dgpu_display_event;
2277};
2278
2279struct radeon_atif_functions {
2280 bool system_params;
2281 bool sbios_requests;
2282 bool select_active_disp;
2283 bool lid_state;
2284 bool get_tv_standard;
2285 bool set_tv_standard;
2286 bool get_panel_expansion_mode;
2287 bool set_panel_expansion_mode;
2288 bool temperature_change;
2289 bool graphics_device_types;
2290};
2291
2292struct radeon_atif {
2293 struct radeon_atif_notifications notifications;
2294 struct radeon_atif_functions functions;
2295 struct radeon_atif_notification_cfg notification_cfg;
2296 struct radeon_encoder *encoder_for_bl;
2297};
2298
2299struct radeon_atcs_functions {
2300 bool get_ext_state;
2301 bool pcie_perf_req;
2302 bool pcie_dev_rdy;
2303 bool pcie_bus_width;
2304};
2305
2306struct radeon_atcs {
2307 struct radeon_atcs_functions functions;
2308};
2309
2310/*
2311 * Core structure, functions and helpers.
2312 */
2313typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2314typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2315
2316struct radeon_device {
2317 struct device *dev;
2318 struct drm_device *ddev;
2319 struct pci_dev *pdev;
2320 struct rw_semaphore exclusive_lock;
2321 /* ASIC */
2322 union radeon_asic_config config;
2323 enum radeon_family family;
2324 unsigned long flags;
2325 int usec_timeout;
2326 enum radeon_pll_errata pll_errata;
2327 int num_gb_pipes;
2328 int num_z_pipes;
2329 int disp_priority;
2330 /* BIOS */
2331 uint8_t *bios;
2332 bool is_atom_bios;
2333 uint16_t bios_header_start;
2334 struct radeon_bo *stollen_vga_memory;
2335 /* Register mmio */
2336 resource_size_t rmmio_base;
2337 resource_size_t rmmio_size;
2338 /* protects concurrent MM_INDEX/DATA based register access */
2339 spinlock_t mmio_idx_lock;
2340 /* protects concurrent SMC based register access */
2341 spinlock_t smc_idx_lock;
2342 /* protects concurrent PLL register access */
2343 spinlock_t pll_idx_lock;
2344 /* protects concurrent MC register access */
2345 spinlock_t mc_idx_lock;
2346 /* protects concurrent PCIE register access */
2347 spinlock_t pcie_idx_lock;
2348 /* protects concurrent PCIE_PORT register access */
2349 spinlock_t pciep_idx_lock;
2350 /* protects concurrent PIF register access */
2351 spinlock_t pif_idx_lock;
2352 /* protects concurrent CG register access */
2353 spinlock_t cg_idx_lock;
2354 /* protects concurrent UVD register access */
2355 spinlock_t uvd_idx_lock;
2356 /* protects concurrent RCU register access */
2357 spinlock_t rcu_idx_lock;
2358 /* protects concurrent DIDT register access */
2359 spinlock_t didt_idx_lock;
2360 /* protects concurrent ENDPOINT (audio) register access */
2361 spinlock_t end_idx_lock;
2362 void __iomem *rmmio;
2363 radeon_rreg_t mc_rreg;
2364 radeon_wreg_t mc_wreg;
2365 radeon_rreg_t pll_rreg;
2366 radeon_wreg_t pll_wreg;
2367 uint32_t pcie_reg_mask;
2368 radeon_rreg_t pciep_rreg;
2369 radeon_wreg_t pciep_wreg;
2370 /* io port */
2371 void __iomem *rio_mem;
2372 resource_size_t rio_mem_size;
2373 struct radeon_clock clock;
2374 struct radeon_mc mc;
2375 struct radeon_gart gart;
2376 struct radeon_mode_info mode_info;
2377 struct radeon_scratch scratch;
2378 struct radeon_doorbell doorbell;
2379 struct radeon_mman mman;
2380 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
2381 wait_queue_head_t fence_queue;
2382 unsigned fence_context;
2383 struct mutex ring_lock;
2384 struct radeon_ring ring[RADEON_NUM_RINGS];
2385 bool ib_pool_ready;
2386 struct radeon_sa_manager ring_tmp_bo;
2387 struct radeon_irq irq;
2388 struct radeon_asic *asic;
2389 struct radeon_gem gem;
2390 struct radeon_pm pm;
2391 struct radeon_uvd uvd;
2392 struct radeon_vce vce;
2393 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
2394 struct radeon_wb wb;
2395 struct radeon_dummy_page dummy_page;
2396 bool shutdown;
2397 bool suspend;
2398 bool need_dma32;
2399 bool accel_working;
2400 bool fastfb_working; /* IGP feature*/
2401 bool needs_reset, in_reset;
2402 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
2403 const struct firmware *me_fw; /* all family ME firmware */
2404 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
2405 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
2406 const struct firmware *mc_fw; /* NI MC firmware */
2407 const struct firmware *ce_fw; /* SI CE firmware */
2408 const struct firmware *mec_fw; /* CIK MEC firmware */
2409 const struct firmware *mec2_fw; /* KV MEC2 firmware */
2410 const struct firmware *sdma_fw; /* CIK SDMA firmware */
2411 const struct firmware *smc_fw; /* SMC firmware */
2412 const struct firmware *uvd_fw; /* UVD firmware */
2413 const struct firmware *vce_fw; /* VCE firmware */
2414 bool new_fw;
2415 struct r600_vram_scratch vram_scratch;
2416 int msi_enabled; /* msi enabled */
2417 struct r600_ih ih; /* r6/700 interrupt ring */
2418 struct radeon_rlc rlc;
2419 struct radeon_mec mec;
2420 struct delayed_work hotplug_work;
2421 struct work_struct dp_work;
2422 struct work_struct audio_work;
2423 int num_crtc; /* number of crtcs */
2424 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
2425 bool has_uvd;
2426 struct r600_audio audio; /* audio stuff */
2427 struct notifier_block acpi_nb;
2428 /* only one userspace can use Hyperz features or CMASK at a time */
2429 struct drm_file *hyperz_filp;
2430 struct drm_file *cmask_filp;
2431 /* i2c buses */
2432 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
2433 /* debugfs */
2434 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2435 unsigned debugfs_count;
2436 /* virtual memory */
2437 struct radeon_vm_manager vm_manager;
2438 struct mutex gpu_clock_mutex;
2439 /* memory stats */
2440 atomic64_t vram_usage;
2441 atomic64_t gtt_usage;
2442 atomic64_t num_bytes_moved;
2443 atomic_t gpu_reset_counter;
2444 /* ACPI interface */
2445 struct radeon_atif atif;
2446 struct radeon_atcs atcs;
2447 /* srbm instance registers */
2448 struct mutex srbm_mutex;
2449 /* GRBM index mutex. Protects concurrents access to GRBM index */
2450 struct mutex grbm_idx_mutex;
2451 /* clock, powergating flags */
2452 u32 cg_flags;
2453 u32 pg_flags;
2454
2455 struct dev_pm_domain vga_pm_domain;
2456 bool have_disp_power_ref;
2457 u32 px_quirk_flags;
2458
2459 /* tracking pinned memory */
2460 u64 vram_pin_size;
2461 u64 gart_pin_size;
2462
2463 /* amdkfd interface */
2464 struct kfd_dev *kfd;
2465
2466 struct mutex mn_lock;
2467 DECLARE_HASHTABLE(mn_hash, 7);
2468};
2469
2470bool radeon_is_px(struct drm_device *dev);
2471int radeon_device_init(struct radeon_device *rdev,
2472 struct drm_device *ddev,
2473 struct pci_dev *pdev,
2474 uint32_t flags);
2475void radeon_device_fini(struct radeon_device *rdev);
2476int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2477
2478#define RADEON_MIN_MMIO_SIZE 0x10000
2479
2480uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg);
2481void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v);
2482static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2483 bool always_indirect)
2484{
2485 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */
2486 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2487 return readl(((void __iomem *)rdev->rmmio) + reg);
2488 else
2489 return r100_mm_rreg_slow(rdev, reg);
2490}
2491static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2492 bool always_indirect)
2493{
2494 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2495 writel(v, ((void __iomem *)rdev->rmmio) + reg);
2496 else
2497 r100_mm_wreg_slow(rdev, reg, v);
2498}
2499
2500u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2501void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2502
2503u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2504void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
2505
2506/*
2507 * Cast helper
2508 */
2509extern const struct fence_ops radeon_fence_ops;
2510
2511static inline struct radeon_fence *to_radeon_fence(struct fence *f)
2512{
2513 struct radeon_fence *__f = container_of(f, struct radeon_fence, base);
2514
2515 if (__f->base.ops == &radeon_fence_ops)
2516 return __f;
2517
2518 return NULL;
2519}
2520
2521/*
2522 * Registers read & write functions.
2523 */
2524#define RREG8(reg) readb((rdev->rmmio) + (reg))
2525#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2526#define RREG16(reg) readw((rdev->rmmio) + (reg))
2527#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2528#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2529#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2530#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2531#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2532#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
2533#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2534#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2535#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2536#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2537#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2538#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
2539#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2540#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
2541#define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2542#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
2543#define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2544#define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
2545#define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2546#define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
2547#define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2548#define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
2549#define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2550#define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2551#define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2552#define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
2553#define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2554#define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
2555#define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2556#define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
2557#define WREG32_P(reg, val, mask) \
2558 do { \
2559 uint32_t tmp_ = RREG32(reg); \
2560 tmp_ &= (mask); \
2561 tmp_ |= ((val) & ~(mask)); \
2562 WREG32(reg, tmp_); \
2563 } while (0)
2564#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2565#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2566#define WREG32_PLL_P(reg, val, mask) \
2567 do { \
2568 uint32_t tmp_ = RREG32_PLL(reg); \
2569 tmp_ &= (mask); \
2570 tmp_ |= ((val) & ~(mask)); \
2571 WREG32_PLL(reg, tmp_); \
2572 } while (0)
2573#define WREG32_SMC_P(reg, val, mask) \
2574 do { \
2575 uint32_t tmp_ = RREG32_SMC(reg); \
2576 tmp_ &= (mask); \
2577 tmp_ |= ((val) & ~(mask)); \
2578 WREG32_SMC(reg, tmp_); \
2579 } while (0)
2580#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
2581#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2582#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
2583
2584#define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2585#define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
2586
2587/*
2588 * Indirect registers accessors.
2589 * They used to be inlined, but this increases code size by ~65 kbytes.
2590 * Since each performs a pair of MMIO ops
2591 * within a spin_lock_irqsave/spin_unlock_irqrestore region,
2592 * the cost of call+ret is almost negligible. MMIO and locking
2593 * costs several dozens of cycles each at best, call+ret is ~5 cycles.
2594 */
2595uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
2596void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
2597u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg);
2598void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2599u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg);
2600void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2601u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg);
2602void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2603u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg);
2604void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2605u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg);
2606void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2607u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg);
2608void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2609u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg);
2610void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2611
2612void r100_pll_errata_after_index(struct radeon_device *rdev);
2613
2614
2615/*
2616 * ASICs helpers.
2617 */
2618#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2619 (rdev->pdev->device == 0x5969))
2620#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2621 (rdev->family == CHIP_RV200) || \
2622 (rdev->family == CHIP_RS100) || \
2623 (rdev->family == CHIP_RS200) || \
2624 (rdev->family == CHIP_RV250) || \
2625 (rdev->family == CHIP_RV280) || \
2626 (rdev->family == CHIP_RS300))
2627#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2628 (rdev->family == CHIP_RV350) || \
2629 (rdev->family == CHIP_R350) || \
2630 (rdev->family == CHIP_RV380) || \
2631 (rdev->family == CHIP_R420) || \
2632 (rdev->family == CHIP_R423) || \
2633 (rdev->family == CHIP_RV410) || \
2634 (rdev->family == CHIP_RS400) || \
2635 (rdev->family == CHIP_RS480))
2636#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2637 (rdev->ddev->pdev->device == 0x9443) || \
2638 (rdev->ddev->pdev->device == 0x944B) || \
2639 (rdev->ddev->pdev->device == 0x9506) || \
2640 (rdev->ddev->pdev->device == 0x9509) || \
2641 (rdev->ddev->pdev->device == 0x950F) || \
2642 (rdev->ddev->pdev->device == 0x689C) || \
2643 (rdev->ddev->pdev->device == 0x689D))
2644#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
2645#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2646 (rdev->family == CHIP_RS690) || \
2647 (rdev->family == CHIP_RS740) || \
2648 (rdev->family >= CHIP_R600))
2649#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2650#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
2651#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
2652#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2653 (rdev->flags & RADEON_IS_IGP))
2654#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2655#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2656#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2657 (rdev->flags & RADEON_IS_IGP))
2658#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
2659#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
2660#define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
2661#define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2662#define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
2663#define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2664 (rdev->family == CHIP_MULLINS))
2665
2666#define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2667 (rdev->ddev->pdev->device == 0x6850) || \
2668 (rdev->ddev->pdev->device == 0x6858) || \
2669 (rdev->ddev->pdev->device == 0x6859) || \
2670 (rdev->ddev->pdev->device == 0x6840) || \
2671 (rdev->ddev->pdev->device == 0x6841) || \
2672 (rdev->ddev->pdev->device == 0x6842) || \
2673 (rdev->ddev->pdev->device == 0x6843))
2674
2675/*
2676 * BIOS helpers.
2677 */
2678#define RBIOS8(i) (rdev->bios[i])
2679#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2680#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2681
2682int radeon_combios_init(struct radeon_device *rdev);
2683void radeon_combios_fini(struct radeon_device *rdev);
2684int radeon_atombios_init(struct radeon_device *rdev);
2685void radeon_atombios_fini(struct radeon_device *rdev);
2686
2687
2688/*
2689 * RING helpers.
2690 */
2691
2692/**
2693 * radeon_ring_write - write a value to the ring
2694 *
2695 * @ring: radeon_ring structure holding ring information
2696 * @v: dword (dw) value to write
2697 *
2698 * Write a value to the requested ring buffer (all asics).
2699 */
2700static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2701{
2702 if (ring->count_dw <= 0)
2703 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
2704
2705 ring->ring[ring->wptr++] = v;
2706 ring->wptr &= ring->ptr_mask;
2707 ring->count_dw--;
2708 ring->ring_free_dw--;
2709}
2710
2711/*
2712 * ASICs macro.
2713 */
2714#define radeon_init(rdev) (rdev)->asic->init((rdev))
2715#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2716#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2717#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2718#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
2719#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2720#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
2721#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2722#define radeon_gart_get_page_entry(a, f) (rdev)->asic->gart.get_page_entry((a), (f))
2723#define radeon_gart_set_page(rdev, i, e) (rdev)->asic->gart.set_page((rdev), (i), (e))
2724#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2725#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2726#define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count)))
2727#define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2728#define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2729#define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib)))
2730#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2731#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2732#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2733#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2734#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2735#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2736#define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr))
2737#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2738#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2739#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
2740#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2741#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2742#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2743#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2744#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2745#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2746#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2747#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2748#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2749#define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv))
2750#define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv))
2751#define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv))
2752#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2753#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2754#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2755#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2756#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2757#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2758#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2759#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2760#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2761#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2762#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2763#define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
2764#define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2765#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2766#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2767#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
2768#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2769#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2770#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2771#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
2772#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2773#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2774#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2775#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2776#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2777#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
2778#define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2779#define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
2780#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2781#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
2782#define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
2783#define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
2784#define radeon_get_allowed_info_register(rdev, r, v) (rdev)->asic->get_allowed_info_register((rdev), (r), (v))
2785#define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2786#define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2787#define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2788#define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
2789#define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2790#define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2791#define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2792#define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
2793#define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2794#define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2795#define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2796#define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2797#define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
2798#define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
2799#define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
2800#define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
2801#define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
2802#define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
2803#define radeon_dpm_get_current_sclk(rdev) rdev->asic->dpm.get_current_sclk((rdev))
2804#define radeon_dpm_get_current_mclk(rdev) rdev->asic->dpm.get_current_mclk((rdev))
2805
2806/* Common functions */
2807/* AGP */
2808extern int radeon_gpu_reset(struct radeon_device *rdev);
2809extern void radeon_pci_config_reset(struct radeon_device *rdev);
2810extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
2811extern void radeon_agp_disable(struct radeon_device *rdev);
2812extern int radeon_modeset_init(struct radeon_device *rdev);
2813extern void radeon_modeset_fini(struct radeon_device *rdev);
2814extern bool radeon_card_posted(struct radeon_device *rdev);
2815extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
2816extern void radeon_update_display_priority(struct radeon_device *rdev);
2817extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
2818extern void radeon_scratch_init(struct radeon_device *rdev);
2819extern void radeon_wb_fini(struct radeon_device *rdev);
2820extern int radeon_wb_init(struct radeon_device *rdev);
2821extern void radeon_wb_disable(struct radeon_device *rdev);
2822extern void radeon_surface_init(struct radeon_device *rdev);
2823extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2824extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2825extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2826extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2827extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2828extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2829 uint32_t flags);
2830extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm);
2831extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm);
2832extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2833extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2834extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2835extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2836extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2837extern void radeon_program_register_sequence(struct radeon_device *rdev,
2838 const u32 *registers,
2839 const u32 array_size);
2840
2841/*
2842 * vm
2843 */
2844int radeon_vm_manager_init(struct radeon_device *rdev);
2845void radeon_vm_manager_fini(struct radeon_device *rdev);
2846int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
2847void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
2848struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev,
2849 struct radeon_vm *vm,
2850 struct list_head *head);
2851struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2852 struct radeon_vm *vm, int ring);
2853void radeon_vm_flush(struct radeon_device *rdev,
2854 struct radeon_vm *vm,
2855 int ring, struct radeon_fence *fence);
2856void radeon_vm_fence(struct radeon_device *rdev,
2857 struct radeon_vm *vm,
2858 struct radeon_fence *fence);
2859uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2860int radeon_vm_update_page_directory(struct radeon_device *rdev,
2861 struct radeon_vm *vm);
2862int radeon_vm_clear_freed(struct radeon_device *rdev,
2863 struct radeon_vm *vm);
2864int radeon_vm_clear_invalids(struct radeon_device *rdev,
2865 struct radeon_vm *vm);
2866int radeon_vm_bo_update(struct radeon_device *rdev,
2867 struct radeon_bo_va *bo_va,
2868 struct ttm_mem_reg *mem);
2869void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2870 struct radeon_bo *bo);
2871struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2872 struct radeon_bo *bo);
2873struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2874 struct radeon_vm *vm,
2875 struct radeon_bo *bo);
2876int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2877 struct radeon_bo_va *bo_va,
2878 uint64_t offset,
2879 uint32_t flags);
2880void radeon_vm_bo_rmv(struct radeon_device *rdev,
2881 struct radeon_bo_va *bo_va);
2882
2883/* audio */
2884void r600_audio_update_hdmi(struct work_struct *work);
2885struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2886struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
2887void r600_audio_enable(struct radeon_device *rdev,
2888 struct r600_audio_pin *pin,
2889 u8 enable_mask);
2890void dce6_audio_enable(struct radeon_device *rdev,
2891 struct r600_audio_pin *pin,
2892 u8 enable_mask);
2893
2894/*
2895 * R600 vram scratch functions
2896 */
2897int r600_vram_scratch_init(struct radeon_device *rdev);
2898void r600_vram_scratch_fini(struct radeon_device *rdev);
2899
2900/*
2901 * r600 cs checking helper
2902 */
2903unsigned r600_mip_minify(unsigned size, unsigned level);
2904bool r600_fmt_is_valid_color(u32 format);
2905bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2906int r600_fmt_get_blocksize(u32 format);
2907int r600_fmt_get_nblocksx(u32 format, u32 w);
2908int r600_fmt_get_nblocksy(u32 format, u32 h);
2909
2910/*
2911 * r600 functions used by radeon_encoder.c
2912 */
2913struct radeon_hdmi_acr {
2914 u32 clock;
2915
2916 int n_32khz;
2917 int cts_32khz;
2918
2919 int n_44_1khz;
2920 int cts_44_1khz;
2921
2922 int n_48khz;
2923 int cts_48khz;
2924
2925};
2926
2927extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2928
2929extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2930 u32 tiling_pipe_num,
2931 u32 max_rb_num,
2932 u32 total_max_rb_num,
2933 u32 enabled_rb_mask);
2934
2935/*
2936 * evergreen functions used by radeon_encoder.c
2937 */
2938
2939extern int ni_init_microcode(struct radeon_device *rdev);
2940extern int ni_mc_load_microcode(struct radeon_device *rdev);
2941
2942/* radeon_acpi.c */
2943#if defined(CONFIG_ACPI)
2944extern int radeon_acpi_init(struct radeon_device *rdev);
2945extern void radeon_acpi_fini(struct radeon_device *rdev);
2946extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2947extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
2948 u8 perf_req, bool advertise);
2949extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
2950#else
2951static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2952static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2953#endif
2954
2955int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2956 struct radeon_cs_packet *pkt,
2957 unsigned idx);
2958bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
2959void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2960 struct radeon_cs_packet *pkt);
2961int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2962 struct radeon_bo_list **cs_reloc,
2963 int nomm);
2964int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2965 uint32_t *vline_start_end,
2966 uint32_t *vline_status);
2967
2968#include "radeon_object.h"
2969
2970#endif
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
31/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63#include <linux/atomic.h>
64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
67
68#include <ttm/ttm_bo_api.h>
69#include <ttm/ttm_bo_driver.h>
70#include <ttm/ttm_placement.h>
71#include <ttm/ttm_module.h>
72#include <ttm/ttm_execbuf_util.h>
73
74#include "radeon_family.h"
75#include "radeon_mode.h"
76#include "radeon_reg.h"
77
78/*
79 * Modules parameters.
80 */
81extern int radeon_no_wb;
82extern int radeon_modeset;
83extern int radeon_dynclks;
84extern int radeon_r4xx_atom;
85extern int radeon_agpmode;
86extern int radeon_vram_limit;
87extern int radeon_gart_size;
88extern int radeon_benchmarking;
89extern int radeon_testing;
90extern int radeon_connector_table;
91extern int radeon_tv;
92extern int radeon_audio;
93extern int radeon_disp_priority;
94extern int radeon_hw_i2c;
95extern int radeon_pcie_gen2;
96extern int radeon_msi;
97extern int radeon_lockup_timeout;
98extern int radeon_fastfb;
99extern int radeon_dpm;
100extern int radeon_aspm;
101extern int radeon_runtime_pm;
102extern int radeon_hard_reset;
103
104/*
105 * Copy from radeon_drv.h so we don't have to include both and have conflicting
106 * symbol;
107 */
108#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
109#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
110/* RADEON_IB_POOL_SIZE must be a power of 2 */
111#define RADEON_IB_POOL_SIZE 16
112#define RADEON_DEBUGFS_MAX_COMPONENTS 32
113#define RADEONFB_CONN_LIMIT 4
114#define RADEON_BIOS_NUM_SCRATCH 8
115
116/* fence seq are set to this number when signaled */
117#define RADEON_FENCE_SIGNALED_SEQ 0LL
118
119/* internal ring indices */
120/* r1xx+ has gfx CP ring */
121#define RADEON_RING_TYPE_GFX_INDEX 0
122
123/* cayman has 2 compute CP rings */
124#define CAYMAN_RING_TYPE_CP1_INDEX 1
125#define CAYMAN_RING_TYPE_CP2_INDEX 2
126
127/* R600+ has an async dma ring */
128#define R600_RING_TYPE_DMA_INDEX 3
129/* cayman add a second async dma ring */
130#define CAYMAN_RING_TYPE_DMA1_INDEX 4
131
132/* R600+ */
133#define R600_RING_TYPE_UVD_INDEX 5
134
135/* TN+ */
136#define TN_RING_TYPE_VCE1_INDEX 6
137#define TN_RING_TYPE_VCE2_INDEX 7
138
139/* max number of rings */
140#define RADEON_NUM_RINGS 8
141
142/* number of hw syncs before falling back on blocking */
143#define RADEON_NUM_SYNCS 4
144
145/* number of hw syncs before falling back on blocking */
146#define RADEON_NUM_SYNCS 4
147
148/* hardcode those limit for now */
149#define RADEON_VA_IB_OFFSET (1 << 20)
150#define RADEON_VA_RESERVED_SIZE (8 << 20)
151#define RADEON_IB_VM_MAX_SIZE (64 << 10)
152
153/* hard reset data */
154#define RADEON_ASIC_RESET_DATA 0x39d5e86b
155
156/* reset flags */
157#define RADEON_RESET_GFX (1 << 0)
158#define RADEON_RESET_COMPUTE (1 << 1)
159#define RADEON_RESET_DMA (1 << 2)
160#define RADEON_RESET_CP (1 << 3)
161#define RADEON_RESET_GRBM (1 << 4)
162#define RADEON_RESET_DMA1 (1 << 5)
163#define RADEON_RESET_RLC (1 << 6)
164#define RADEON_RESET_SEM (1 << 7)
165#define RADEON_RESET_IH (1 << 8)
166#define RADEON_RESET_VMC (1 << 9)
167#define RADEON_RESET_MC (1 << 10)
168#define RADEON_RESET_DISPLAY (1 << 11)
169
170/* CG block flags */
171#define RADEON_CG_BLOCK_GFX (1 << 0)
172#define RADEON_CG_BLOCK_MC (1 << 1)
173#define RADEON_CG_BLOCK_SDMA (1 << 2)
174#define RADEON_CG_BLOCK_UVD (1 << 3)
175#define RADEON_CG_BLOCK_VCE (1 << 4)
176#define RADEON_CG_BLOCK_HDP (1 << 5)
177#define RADEON_CG_BLOCK_BIF (1 << 6)
178
179/* CG flags */
180#define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
181#define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
182#define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
183#define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
184#define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
185#define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
186#define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
187#define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
188#define RADEON_CG_SUPPORT_MC_LS (1 << 8)
189#define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
190#define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
191#define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
192#define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
193#define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
194#define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
195#define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
196#define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
197
198/* PG flags */
199#define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
200#define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
201#define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
202#define RADEON_PG_SUPPORT_UVD (1 << 3)
203#define RADEON_PG_SUPPORT_VCE (1 << 4)
204#define RADEON_PG_SUPPORT_CP (1 << 5)
205#define RADEON_PG_SUPPORT_GDS (1 << 6)
206#define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
207#define RADEON_PG_SUPPORT_SDMA (1 << 8)
208#define RADEON_PG_SUPPORT_ACP (1 << 9)
209#define RADEON_PG_SUPPORT_SAMU (1 << 10)
210
211/* max cursor sizes (in pixels) */
212#define CURSOR_WIDTH 64
213#define CURSOR_HEIGHT 64
214
215#define CIK_CURSOR_WIDTH 128
216#define CIK_CURSOR_HEIGHT 128
217
218/*
219 * Errata workarounds.
220 */
221enum radeon_pll_errata {
222 CHIP_ERRATA_R300_CG = 0x00000001,
223 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
224 CHIP_ERRATA_PLL_DELAY = 0x00000004
225};
226
227
228struct radeon_device;
229
230
231/*
232 * BIOS.
233 */
234bool radeon_get_bios(struct radeon_device *rdev);
235
236/*
237 * Dummy page
238 */
239struct radeon_dummy_page {
240 struct page *page;
241 dma_addr_t addr;
242};
243int radeon_dummy_page_init(struct radeon_device *rdev);
244void radeon_dummy_page_fini(struct radeon_device *rdev);
245
246
247/*
248 * Clocks
249 */
250struct radeon_clock {
251 struct radeon_pll p1pll;
252 struct radeon_pll p2pll;
253 struct radeon_pll dcpll;
254 struct radeon_pll spll;
255 struct radeon_pll mpll;
256 /* 10 Khz units */
257 uint32_t default_mclk;
258 uint32_t default_sclk;
259 uint32_t default_dispclk;
260 uint32_t current_dispclk;
261 uint32_t dp_extclk;
262 uint32_t max_pixel_clock;
263};
264
265/*
266 * Power management
267 */
268int radeon_pm_init(struct radeon_device *rdev);
269int radeon_pm_late_init(struct radeon_device *rdev);
270void radeon_pm_fini(struct radeon_device *rdev);
271void radeon_pm_compute_clocks(struct radeon_device *rdev);
272void radeon_pm_suspend(struct radeon_device *rdev);
273void radeon_pm_resume(struct radeon_device *rdev);
274void radeon_combios_get_power_modes(struct radeon_device *rdev);
275void radeon_atombios_get_power_modes(struct radeon_device *rdev);
276int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
277 u8 clock_type,
278 u32 clock,
279 bool strobe_mode,
280 struct atom_clock_dividers *dividers);
281int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
282 u32 clock,
283 bool strobe_mode,
284 struct atom_mpll_param *mpll_param);
285void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
286int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
287 u16 voltage_level, u8 voltage_type,
288 u32 *gpio_value, u32 *gpio_mask);
289void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
290 u32 eng_clock, u32 mem_clock);
291int radeon_atom_get_voltage_step(struct radeon_device *rdev,
292 u8 voltage_type, u16 *voltage_step);
293int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
294 u16 voltage_id, u16 *voltage);
295int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
296 u16 *voltage,
297 u16 leakage_idx);
298int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
299 u16 *leakage_id);
300int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
301 u16 *vddc, u16 *vddci,
302 u16 virtual_voltage_id,
303 u16 vbios_voltage_id);
304int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
305 u8 voltage_type,
306 u16 nominal_voltage,
307 u16 *true_voltage);
308int radeon_atom_get_min_voltage(struct radeon_device *rdev,
309 u8 voltage_type, u16 *min_voltage);
310int radeon_atom_get_max_voltage(struct radeon_device *rdev,
311 u8 voltage_type, u16 *max_voltage);
312int radeon_atom_get_voltage_table(struct radeon_device *rdev,
313 u8 voltage_type, u8 voltage_mode,
314 struct atom_voltage_table *voltage_table);
315bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
316 u8 voltage_type, u8 voltage_mode);
317void radeon_atom_update_memory_dll(struct radeon_device *rdev,
318 u32 mem_clock);
319void radeon_atom_set_ac_timing(struct radeon_device *rdev,
320 u32 mem_clock);
321int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
322 u8 module_index,
323 struct atom_mc_reg_table *reg_table);
324int radeon_atom_get_memory_info(struct radeon_device *rdev,
325 u8 module_index, struct atom_memory_info *mem_info);
326int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
327 bool gddr5, u8 module_index,
328 struct atom_memory_clock_range_table *mclk_range_table);
329int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
330 u16 voltage_id, u16 *voltage);
331void rs690_pm_info(struct radeon_device *rdev);
332extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
333 unsigned *bankh, unsigned *mtaspect,
334 unsigned *tile_split);
335
336/*
337 * Fences.
338 */
339struct radeon_fence_driver {
340 uint32_t scratch_reg;
341 uint64_t gpu_addr;
342 volatile uint32_t *cpu_addr;
343 /* sync_seq is protected by ring emission lock */
344 uint64_t sync_seq[RADEON_NUM_RINGS];
345 atomic64_t last_seq;
346 bool initialized;
347};
348
349struct radeon_fence {
350 struct radeon_device *rdev;
351 struct kref kref;
352 /* protected by radeon_fence.lock */
353 uint64_t seq;
354 /* RB, DMA, etc. */
355 unsigned ring;
356};
357
358int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
359int radeon_fence_driver_init(struct radeon_device *rdev);
360void radeon_fence_driver_fini(struct radeon_device *rdev);
361void radeon_fence_driver_force_completion(struct radeon_device *rdev);
362int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
363void radeon_fence_process(struct radeon_device *rdev, int ring);
364bool radeon_fence_signaled(struct radeon_fence *fence);
365int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
366int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
367int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
368int radeon_fence_wait_any(struct radeon_device *rdev,
369 struct radeon_fence **fences,
370 bool intr);
371struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
372void radeon_fence_unref(struct radeon_fence **fence);
373unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
374bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
375void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
376static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
377 struct radeon_fence *b)
378{
379 if (!a) {
380 return b;
381 }
382
383 if (!b) {
384 return a;
385 }
386
387 BUG_ON(a->ring != b->ring);
388
389 if (a->seq > b->seq) {
390 return a;
391 } else {
392 return b;
393 }
394}
395
396static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
397 struct radeon_fence *b)
398{
399 if (!a) {
400 return false;
401 }
402
403 if (!b) {
404 return true;
405 }
406
407 BUG_ON(a->ring != b->ring);
408
409 return a->seq < b->seq;
410}
411
412/*
413 * Tiling registers
414 */
415struct radeon_surface_reg {
416 struct radeon_bo *bo;
417};
418
419#define RADEON_GEM_MAX_SURFACES 8
420
421/*
422 * TTM.
423 */
424struct radeon_mman {
425 struct ttm_bo_global_ref bo_global_ref;
426 struct drm_global_reference mem_global_ref;
427 struct ttm_bo_device bdev;
428 bool mem_global_referenced;
429 bool initialized;
430
431#if defined(CONFIG_DEBUG_FS)
432 struct dentry *vram;
433 struct dentry *gtt;
434#endif
435};
436
437/* bo virtual address in a specific vm */
438struct radeon_bo_va {
439 /* protected by bo being reserved */
440 struct list_head bo_list;
441 uint64_t soffset;
442 uint64_t eoffset;
443 uint32_t flags;
444 bool valid;
445 unsigned ref_count;
446
447 /* protected by vm mutex */
448 struct list_head vm_list;
449
450 /* constant after initialization */
451 struct radeon_vm *vm;
452 struct radeon_bo *bo;
453};
454
455struct radeon_bo {
456 /* Protected by gem.mutex */
457 struct list_head list;
458 /* Protected by tbo.reserved */
459 u32 initial_domain;
460 u32 placements[3];
461 struct ttm_placement placement;
462 struct ttm_buffer_object tbo;
463 struct ttm_bo_kmap_obj kmap;
464 unsigned pin_count;
465 void *kptr;
466 u32 tiling_flags;
467 u32 pitch;
468 int surface_reg;
469 /* list of all virtual address to which this bo
470 * is associated to
471 */
472 struct list_head va;
473 /* Constant after initialization */
474 struct radeon_device *rdev;
475 struct drm_gem_object gem_base;
476
477 struct ttm_bo_kmap_obj dma_buf_vmap;
478 pid_t pid;
479};
480#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
481
482int radeon_gem_debugfs_init(struct radeon_device *rdev);
483
484/* sub-allocation manager, it has to be protected by another lock.
485 * By conception this is an helper for other part of the driver
486 * like the indirect buffer or semaphore, which both have their
487 * locking.
488 *
489 * Principe is simple, we keep a list of sub allocation in offset
490 * order (first entry has offset == 0, last entry has the highest
491 * offset).
492 *
493 * When allocating new object we first check if there is room at
494 * the end total_size - (last_object_offset + last_object_size) >=
495 * alloc_size. If so we allocate new object there.
496 *
497 * When there is not enough room at the end, we start waiting for
498 * each sub object until we reach object_offset+object_size >=
499 * alloc_size, this object then become the sub object we return.
500 *
501 * Alignment can't be bigger than page size.
502 *
503 * Hole are not considered for allocation to keep things simple.
504 * Assumption is that there won't be hole (all object on same
505 * alignment).
506 */
507struct radeon_sa_manager {
508 wait_queue_head_t wq;
509 struct radeon_bo *bo;
510 struct list_head *hole;
511 struct list_head flist[RADEON_NUM_RINGS];
512 struct list_head olist;
513 unsigned size;
514 uint64_t gpu_addr;
515 void *cpu_ptr;
516 uint32_t domain;
517 uint32_t align;
518};
519
520struct radeon_sa_bo;
521
522/* sub-allocation buffer */
523struct radeon_sa_bo {
524 struct list_head olist;
525 struct list_head flist;
526 struct radeon_sa_manager *manager;
527 unsigned soffset;
528 unsigned eoffset;
529 struct radeon_fence *fence;
530};
531
532/*
533 * GEM objects.
534 */
535struct radeon_gem {
536 struct mutex mutex;
537 struct list_head objects;
538};
539
540int radeon_gem_init(struct radeon_device *rdev);
541void radeon_gem_fini(struct radeon_device *rdev);
542int radeon_gem_object_create(struct radeon_device *rdev, int size,
543 int alignment, int initial_domain,
544 bool discardable, bool kernel,
545 struct drm_gem_object **obj);
546
547int radeon_mode_dumb_create(struct drm_file *file_priv,
548 struct drm_device *dev,
549 struct drm_mode_create_dumb *args);
550int radeon_mode_dumb_mmap(struct drm_file *filp,
551 struct drm_device *dev,
552 uint32_t handle, uint64_t *offset_p);
553
554/*
555 * Semaphores.
556 */
557struct radeon_semaphore {
558 struct radeon_sa_bo *sa_bo;
559 signed waiters;
560 uint64_t gpu_addr;
561 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
562};
563
564int radeon_semaphore_create(struct radeon_device *rdev,
565 struct radeon_semaphore **semaphore);
566bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
567 struct radeon_semaphore *semaphore);
568bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
569 struct radeon_semaphore *semaphore);
570void radeon_semaphore_sync_to(struct radeon_semaphore *semaphore,
571 struct radeon_fence *fence);
572int radeon_semaphore_sync_rings(struct radeon_device *rdev,
573 struct radeon_semaphore *semaphore,
574 int waiting_ring);
575void radeon_semaphore_free(struct radeon_device *rdev,
576 struct radeon_semaphore **semaphore,
577 struct radeon_fence *fence);
578
579/*
580 * GART structures, functions & helpers
581 */
582struct radeon_mc;
583
584#define RADEON_GPU_PAGE_SIZE 4096
585#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
586#define RADEON_GPU_PAGE_SHIFT 12
587#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
588
589struct radeon_gart {
590 dma_addr_t table_addr;
591 struct radeon_bo *robj;
592 void *ptr;
593 unsigned num_gpu_pages;
594 unsigned num_cpu_pages;
595 unsigned table_size;
596 struct page **pages;
597 dma_addr_t *pages_addr;
598 bool ready;
599};
600
601int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
602void radeon_gart_table_ram_free(struct radeon_device *rdev);
603int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
604void radeon_gart_table_vram_free(struct radeon_device *rdev);
605int radeon_gart_table_vram_pin(struct radeon_device *rdev);
606void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
607int radeon_gart_init(struct radeon_device *rdev);
608void radeon_gart_fini(struct radeon_device *rdev);
609void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
610 int pages);
611int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
612 int pages, struct page **pagelist,
613 dma_addr_t *dma_addr);
614void radeon_gart_restore(struct radeon_device *rdev);
615
616
617/*
618 * GPU MC structures, functions & helpers
619 */
620struct radeon_mc {
621 resource_size_t aper_size;
622 resource_size_t aper_base;
623 resource_size_t agp_base;
624 /* for some chips with <= 32MB we need to lie
625 * about vram size near mc fb location */
626 u64 mc_vram_size;
627 u64 visible_vram_size;
628 u64 gtt_size;
629 u64 gtt_start;
630 u64 gtt_end;
631 u64 vram_start;
632 u64 vram_end;
633 unsigned vram_width;
634 u64 real_vram_size;
635 int vram_mtrr;
636 bool vram_is_ddr;
637 bool igp_sideport_enabled;
638 u64 gtt_base_align;
639 u64 mc_mask;
640};
641
642bool radeon_combios_sideport_present(struct radeon_device *rdev);
643bool radeon_atombios_sideport_present(struct radeon_device *rdev);
644
645/*
646 * GPU scratch registers structures, functions & helpers
647 */
648struct radeon_scratch {
649 unsigned num_reg;
650 uint32_t reg_base;
651 bool free[32];
652 uint32_t reg[32];
653};
654
655int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
656void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
657
658/*
659 * GPU doorbell structures, functions & helpers
660 */
661#define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
662
663struct radeon_doorbell {
664 /* doorbell mmio */
665 resource_size_t base;
666 resource_size_t size;
667 u32 __iomem *ptr;
668 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
669 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)];
670};
671
672int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
673void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
674
675/*
676 * IRQS.
677 */
678
679struct radeon_unpin_work {
680 struct work_struct work;
681 struct radeon_device *rdev;
682 int crtc_id;
683 struct radeon_fence *fence;
684 struct drm_pending_vblank_event *event;
685 struct radeon_bo *old_rbo;
686 u64 new_crtc_base;
687};
688
689struct r500_irq_stat_regs {
690 u32 disp_int;
691 u32 hdmi0_status;
692};
693
694struct r600_irq_stat_regs {
695 u32 disp_int;
696 u32 disp_int_cont;
697 u32 disp_int_cont2;
698 u32 d1grph_int;
699 u32 d2grph_int;
700 u32 hdmi0_status;
701 u32 hdmi1_status;
702};
703
704struct evergreen_irq_stat_regs {
705 u32 disp_int;
706 u32 disp_int_cont;
707 u32 disp_int_cont2;
708 u32 disp_int_cont3;
709 u32 disp_int_cont4;
710 u32 disp_int_cont5;
711 u32 d1grph_int;
712 u32 d2grph_int;
713 u32 d3grph_int;
714 u32 d4grph_int;
715 u32 d5grph_int;
716 u32 d6grph_int;
717 u32 afmt_status1;
718 u32 afmt_status2;
719 u32 afmt_status3;
720 u32 afmt_status4;
721 u32 afmt_status5;
722 u32 afmt_status6;
723};
724
725struct cik_irq_stat_regs {
726 u32 disp_int;
727 u32 disp_int_cont;
728 u32 disp_int_cont2;
729 u32 disp_int_cont3;
730 u32 disp_int_cont4;
731 u32 disp_int_cont5;
732 u32 disp_int_cont6;
733 u32 d1grph_int;
734 u32 d2grph_int;
735 u32 d3grph_int;
736 u32 d4grph_int;
737 u32 d5grph_int;
738 u32 d6grph_int;
739};
740
741union radeon_irq_stat_regs {
742 struct r500_irq_stat_regs r500;
743 struct r600_irq_stat_regs r600;
744 struct evergreen_irq_stat_regs evergreen;
745 struct cik_irq_stat_regs cik;
746};
747
748#define RADEON_MAX_HPD_PINS 7
749#define RADEON_MAX_CRTCS 6
750#define RADEON_MAX_AFMT_BLOCKS 7
751
752struct radeon_irq {
753 bool installed;
754 spinlock_t lock;
755 atomic_t ring_int[RADEON_NUM_RINGS];
756 bool crtc_vblank_int[RADEON_MAX_CRTCS];
757 atomic_t pflip[RADEON_MAX_CRTCS];
758 wait_queue_head_t vblank_queue;
759 bool hpd[RADEON_MAX_HPD_PINS];
760 bool afmt[RADEON_MAX_AFMT_BLOCKS];
761 union radeon_irq_stat_regs stat_regs;
762 bool dpm_thermal;
763};
764
765int radeon_irq_kms_init(struct radeon_device *rdev);
766void radeon_irq_kms_fini(struct radeon_device *rdev);
767void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
768void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
769void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
770void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
771void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
772void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
773void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
774void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
775
776/*
777 * CP & rings.
778 */
779
780struct radeon_ib {
781 struct radeon_sa_bo *sa_bo;
782 uint32_t length_dw;
783 uint64_t gpu_addr;
784 uint32_t *ptr;
785 int ring;
786 struct radeon_fence *fence;
787 struct radeon_vm *vm;
788 bool is_const_ib;
789 struct radeon_semaphore *semaphore;
790};
791
792struct radeon_ring {
793 struct radeon_bo *ring_obj;
794 volatile uint32_t *ring;
795 unsigned rptr_offs;
796 unsigned rptr_save_reg;
797 u64 next_rptr_gpu_addr;
798 volatile u32 *next_rptr_cpu_addr;
799 unsigned wptr;
800 unsigned wptr_old;
801 unsigned ring_size;
802 unsigned ring_free_dw;
803 int count_dw;
804 atomic_t last_rptr;
805 atomic64_t last_activity;
806 uint64_t gpu_addr;
807 uint32_t align_mask;
808 uint32_t ptr_mask;
809 bool ready;
810 u32 nop;
811 u32 idx;
812 u64 last_semaphore_signal_addr;
813 u64 last_semaphore_wait_addr;
814 /* for CIK queues */
815 u32 me;
816 u32 pipe;
817 u32 queue;
818 struct radeon_bo *mqd_obj;
819 u32 doorbell_index;
820 unsigned wptr_offs;
821};
822
823struct radeon_mec {
824 struct radeon_bo *hpd_eop_obj;
825 u64 hpd_eop_gpu_addr;
826 u32 num_pipe;
827 u32 num_mec;
828 u32 num_queue;
829};
830
831/*
832 * VM
833 */
834
835/* maximum number of VMIDs */
836#define RADEON_NUM_VM 16
837
838/* defines number of bits in page table versus page directory,
839 * a page is 4KB so we have 12 bits offset, 9 bits in the page
840 * table and the remaining 19 bits are in the page directory */
841#define RADEON_VM_BLOCK_SIZE 9
842
843/* number of entries in page table */
844#define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE)
845
846/* PTBs (Page Table Blocks) need to be aligned to 32K */
847#define RADEON_VM_PTB_ALIGN_SIZE 32768
848#define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
849#define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
850
851#define R600_PTE_VALID (1 << 0)
852#define R600_PTE_SYSTEM (1 << 1)
853#define R600_PTE_SNOOPED (1 << 2)
854#define R600_PTE_READABLE (1 << 5)
855#define R600_PTE_WRITEABLE (1 << 6)
856
857struct radeon_vm_pt {
858 struct radeon_bo *bo;
859 uint64_t addr;
860};
861
862struct radeon_vm {
863 struct list_head va;
864 unsigned id;
865
866 /* contains the page directory */
867 struct radeon_bo *page_directory;
868 uint64_t pd_gpu_addr;
869 unsigned max_pde_used;
870
871 /* array of page tables, one for each page directory entry */
872 struct radeon_vm_pt *page_tables;
873
874 struct mutex mutex;
875 /* last fence for cs using this vm */
876 struct radeon_fence *fence;
877 /* last flush or NULL if we still need to flush */
878 struct radeon_fence *last_flush;
879 /* last use of vmid */
880 struct radeon_fence *last_id_use;
881};
882
883struct radeon_vm_manager {
884 struct radeon_fence *active[RADEON_NUM_VM];
885 uint32_t max_pfn;
886 /* number of VMIDs */
887 unsigned nvm;
888 /* vram base address for page table entry */
889 u64 vram_base_offset;
890 /* is vm enabled? */
891 bool enabled;
892};
893
894/*
895 * file private structure
896 */
897struct radeon_fpriv {
898 struct radeon_vm vm;
899};
900
901/*
902 * R6xx+ IH ring
903 */
904struct r600_ih {
905 struct radeon_bo *ring_obj;
906 volatile uint32_t *ring;
907 unsigned rptr;
908 unsigned ring_size;
909 uint64_t gpu_addr;
910 uint32_t ptr_mask;
911 atomic_t lock;
912 bool enabled;
913};
914
915/*
916 * RLC stuff
917 */
918#include "clearstate_defs.h"
919
920struct radeon_rlc {
921 /* for power gating */
922 struct radeon_bo *save_restore_obj;
923 uint64_t save_restore_gpu_addr;
924 volatile uint32_t *sr_ptr;
925 const u32 *reg_list;
926 u32 reg_list_size;
927 /* for clear state */
928 struct radeon_bo *clear_state_obj;
929 uint64_t clear_state_gpu_addr;
930 volatile uint32_t *cs_ptr;
931 const struct cs_section_def *cs_data;
932 u32 clear_state_size;
933 /* for cp tables */
934 struct radeon_bo *cp_table_obj;
935 uint64_t cp_table_gpu_addr;
936 volatile uint32_t *cp_table_ptr;
937 u32 cp_table_size;
938};
939
940int radeon_ib_get(struct radeon_device *rdev, int ring,
941 struct radeon_ib *ib, struct radeon_vm *vm,
942 unsigned size);
943void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
944int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
945 struct radeon_ib *const_ib);
946int radeon_ib_pool_init(struct radeon_device *rdev);
947void radeon_ib_pool_fini(struct radeon_device *rdev);
948int radeon_ib_ring_tests(struct radeon_device *rdev);
949/* Ring access between begin & end cannot sleep */
950bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
951 struct radeon_ring *ring);
952void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
953int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
954int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
955void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
956void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
957void radeon_ring_undo(struct radeon_ring *ring);
958void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
959int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
960void radeon_ring_lockup_update(struct radeon_device *rdev,
961 struct radeon_ring *ring);
962bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
963unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
964 uint32_t **data);
965int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
966 unsigned size, uint32_t *data);
967int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
968 unsigned rptr_offs, u32 nop);
969void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
970
971
972/* r600 async dma */
973void r600_dma_stop(struct radeon_device *rdev);
974int r600_dma_resume(struct radeon_device *rdev);
975void r600_dma_fini(struct radeon_device *rdev);
976
977void cayman_dma_stop(struct radeon_device *rdev);
978int cayman_dma_resume(struct radeon_device *rdev);
979void cayman_dma_fini(struct radeon_device *rdev);
980
981/*
982 * CS.
983 */
984struct radeon_cs_reloc {
985 struct drm_gem_object *gobj;
986 struct radeon_bo *robj;
987 struct ttm_validate_buffer tv;
988 uint64_t gpu_offset;
989 unsigned domain;
990 unsigned alt_domain;
991 uint32_t tiling_flags;
992 uint32_t handle;
993};
994
995struct radeon_cs_chunk {
996 uint32_t chunk_id;
997 uint32_t length_dw;
998 uint32_t *kdata;
999 void __user *user_ptr;
1000};
1001
1002struct radeon_cs_parser {
1003 struct device *dev;
1004 struct radeon_device *rdev;
1005 struct drm_file *filp;
1006 /* chunks */
1007 unsigned nchunks;
1008 struct radeon_cs_chunk *chunks;
1009 uint64_t *chunks_array;
1010 /* IB */
1011 unsigned idx;
1012 /* relocations */
1013 unsigned nrelocs;
1014 struct radeon_cs_reloc *relocs;
1015 struct radeon_cs_reloc **relocs_ptr;
1016 struct radeon_cs_reloc *vm_bos;
1017 struct list_head validated;
1018 unsigned dma_reloc_idx;
1019 /* indices of various chunks */
1020 int chunk_ib_idx;
1021 int chunk_relocs_idx;
1022 int chunk_flags_idx;
1023 int chunk_const_ib_idx;
1024 struct radeon_ib ib;
1025 struct radeon_ib const_ib;
1026 void *track;
1027 unsigned family;
1028 int parser_error;
1029 u32 cs_flags;
1030 u32 ring;
1031 s32 priority;
1032 struct ww_acquire_ctx ticket;
1033};
1034
1035static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1036{
1037 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
1038
1039 if (ibc->kdata)
1040 return ibc->kdata[idx];
1041 return p->ib.ptr[idx];
1042}
1043
1044
1045struct radeon_cs_packet {
1046 unsigned idx;
1047 unsigned type;
1048 unsigned reg;
1049 unsigned opcode;
1050 int count;
1051 unsigned one_reg_wr;
1052};
1053
1054typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1055 struct radeon_cs_packet *pkt,
1056 unsigned idx, unsigned reg);
1057typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1058 struct radeon_cs_packet *pkt);
1059
1060
1061/*
1062 * AGP
1063 */
1064int radeon_agp_init(struct radeon_device *rdev);
1065void radeon_agp_resume(struct radeon_device *rdev);
1066void radeon_agp_suspend(struct radeon_device *rdev);
1067void radeon_agp_fini(struct radeon_device *rdev);
1068
1069
1070/*
1071 * Writeback
1072 */
1073struct radeon_wb {
1074 struct radeon_bo *wb_obj;
1075 volatile uint32_t *wb;
1076 uint64_t gpu_addr;
1077 bool enabled;
1078 bool use_event;
1079};
1080
1081#define RADEON_WB_SCRATCH_OFFSET 0
1082#define RADEON_WB_RING0_NEXT_RPTR 256
1083#define RADEON_WB_CP_RPTR_OFFSET 1024
1084#define RADEON_WB_CP1_RPTR_OFFSET 1280
1085#define RADEON_WB_CP2_RPTR_OFFSET 1536
1086#define R600_WB_DMA_RPTR_OFFSET 1792
1087#define R600_WB_IH_WPTR_OFFSET 2048
1088#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
1089#define R600_WB_EVENT_OFFSET 3072
1090#define CIK_WB_CP1_WPTR_OFFSET 3328
1091#define CIK_WB_CP2_WPTR_OFFSET 3584
1092
1093/**
1094 * struct radeon_pm - power management datas
1095 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1096 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1097 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1098 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1099 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1100 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1101 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1102 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1103 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
1104 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
1105 * @needed_bandwidth: current bandwidth needs
1106 *
1107 * It keeps track of various data needed to take powermanagement decision.
1108 * Bandwidth need is used to determine minimun clock of the GPU and memory.
1109 * Equation between gpu/memory clock and available bandwidth is hw dependent
1110 * (type of memory, bus size, efficiency, ...)
1111 */
1112
1113enum radeon_pm_method {
1114 PM_METHOD_PROFILE,
1115 PM_METHOD_DYNPM,
1116 PM_METHOD_DPM,
1117};
1118
1119enum radeon_dynpm_state {
1120 DYNPM_STATE_DISABLED,
1121 DYNPM_STATE_MINIMUM,
1122 DYNPM_STATE_PAUSED,
1123 DYNPM_STATE_ACTIVE,
1124 DYNPM_STATE_SUSPENDED,
1125};
1126enum radeon_dynpm_action {
1127 DYNPM_ACTION_NONE,
1128 DYNPM_ACTION_MINIMUM,
1129 DYNPM_ACTION_DOWNCLOCK,
1130 DYNPM_ACTION_UPCLOCK,
1131 DYNPM_ACTION_DEFAULT
1132};
1133
1134enum radeon_voltage_type {
1135 VOLTAGE_NONE = 0,
1136 VOLTAGE_GPIO,
1137 VOLTAGE_VDDC,
1138 VOLTAGE_SW
1139};
1140
1141enum radeon_pm_state_type {
1142 /* not used for dpm */
1143 POWER_STATE_TYPE_DEFAULT,
1144 POWER_STATE_TYPE_POWERSAVE,
1145 /* user selectable states */
1146 POWER_STATE_TYPE_BATTERY,
1147 POWER_STATE_TYPE_BALANCED,
1148 POWER_STATE_TYPE_PERFORMANCE,
1149 /* internal states */
1150 POWER_STATE_TYPE_INTERNAL_UVD,
1151 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1152 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1153 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1154 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1155 POWER_STATE_TYPE_INTERNAL_BOOT,
1156 POWER_STATE_TYPE_INTERNAL_THERMAL,
1157 POWER_STATE_TYPE_INTERNAL_ACPI,
1158 POWER_STATE_TYPE_INTERNAL_ULV,
1159 POWER_STATE_TYPE_INTERNAL_3DPERF,
1160};
1161
1162enum radeon_pm_profile_type {
1163 PM_PROFILE_DEFAULT,
1164 PM_PROFILE_AUTO,
1165 PM_PROFILE_LOW,
1166 PM_PROFILE_MID,
1167 PM_PROFILE_HIGH,
1168};
1169
1170#define PM_PROFILE_DEFAULT_IDX 0
1171#define PM_PROFILE_LOW_SH_IDX 1
1172#define PM_PROFILE_MID_SH_IDX 2
1173#define PM_PROFILE_HIGH_SH_IDX 3
1174#define PM_PROFILE_LOW_MH_IDX 4
1175#define PM_PROFILE_MID_MH_IDX 5
1176#define PM_PROFILE_HIGH_MH_IDX 6
1177#define PM_PROFILE_MAX 7
1178
1179struct radeon_pm_profile {
1180 int dpms_off_ps_idx;
1181 int dpms_on_ps_idx;
1182 int dpms_off_cm_idx;
1183 int dpms_on_cm_idx;
1184};
1185
1186enum radeon_int_thermal_type {
1187 THERMAL_TYPE_NONE,
1188 THERMAL_TYPE_EXTERNAL,
1189 THERMAL_TYPE_EXTERNAL_GPIO,
1190 THERMAL_TYPE_RV6XX,
1191 THERMAL_TYPE_RV770,
1192 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1193 THERMAL_TYPE_EVERGREEN,
1194 THERMAL_TYPE_SUMO,
1195 THERMAL_TYPE_NI,
1196 THERMAL_TYPE_SI,
1197 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1198 THERMAL_TYPE_CI,
1199 THERMAL_TYPE_KV,
1200};
1201
1202struct radeon_voltage {
1203 enum radeon_voltage_type type;
1204 /* gpio voltage */
1205 struct radeon_gpio_rec gpio;
1206 u32 delay; /* delay in usec from voltage drop to sclk change */
1207 bool active_high; /* voltage drop is active when bit is high */
1208 /* VDDC voltage */
1209 u8 vddc_id; /* index into vddc voltage table */
1210 u8 vddci_id; /* index into vddci voltage table */
1211 bool vddci_enabled;
1212 /* r6xx+ sw */
1213 u16 voltage;
1214 /* evergreen+ vddci */
1215 u16 vddci;
1216};
1217
1218/* clock mode flags */
1219#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1220
1221struct radeon_pm_clock_info {
1222 /* memory clock */
1223 u32 mclk;
1224 /* engine clock */
1225 u32 sclk;
1226 /* voltage info */
1227 struct radeon_voltage voltage;
1228 /* standardized clock flags */
1229 u32 flags;
1230};
1231
1232/* state flags */
1233#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1234
1235struct radeon_power_state {
1236 enum radeon_pm_state_type type;
1237 struct radeon_pm_clock_info *clock_info;
1238 /* number of valid clock modes in this power state */
1239 int num_clock_modes;
1240 struct radeon_pm_clock_info *default_clock_mode;
1241 /* standardized state flags */
1242 u32 flags;
1243 u32 misc; /* vbios specific flags */
1244 u32 misc2; /* vbios specific flags */
1245 int pcie_lanes; /* pcie lanes */
1246};
1247
1248/*
1249 * Some modes are overclocked by very low value, accept them
1250 */
1251#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1252
1253enum radeon_dpm_auto_throttle_src {
1254 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1255 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1256};
1257
1258enum radeon_dpm_event_src {
1259 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1260 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1261 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1262 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1263 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1264};
1265
1266#define RADEON_MAX_VCE_LEVELS 6
1267
1268enum radeon_vce_level {
1269 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1270 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1271 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1272 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1273 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1274 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1275};
1276
1277struct radeon_ps {
1278 u32 caps; /* vbios flags */
1279 u32 class; /* vbios flags */
1280 u32 class2; /* vbios flags */
1281 /* UVD clocks */
1282 u32 vclk;
1283 u32 dclk;
1284 /* VCE clocks */
1285 u32 evclk;
1286 u32 ecclk;
1287 bool vce_active;
1288 enum radeon_vce_level vce_level;
1289 /* asic priv */
1290 void *ps_priv;
1291};
1292
1293struct radeon_dpm_thermal {
1294 /* thermal interrupt work */
1295 struct work_struct work;
1296 /* low temperature threshold */
1297 int min_temp;
1298 /* high temperature threshold */
1299 int max_temp;
1300 /* was interrupt low to high or high to low */
1301 bool high_to_low;
1302};
1303
1304enum radeon_clk_action
1305{
1306 RADEON_SCLK_UP = 1,
1307 RADEON_SCLK_DOWN
1308};
1309
1310struct radeon_blacklist_clocks
1311{
1312 u32 sclk;
1313 u32 mclk;
1314 enum radeon_clk_action action;
1315};
1316
1317struct radeon_clock_and_voltage_limits {
1318 u32 sclk;
1319 u32 mclk;
1320 u16 vddc;
1321 u16 vddci;
1322};
1323
1324struct radeon_clock_array {
1325 u32 count;
1326 u32 *values;
1327};
1328
1329struct radeon_clock_voltage_dependency_entry {
1330 u32 clk;
1331 u16 v;
1332};
1333
1334struct radeon_clock_voltage_dependency_table {
1335 u32 count;
1336 struct radeon_clock_voltage_dependency_entry *entries;
1337};
1338
1339union radeon_cac_leakage_entry {
1340 struct {
1341 u16 vddc;
1342 u32 leakage;
1343 };
1344 struct {
1345 u16 vddc1;
1346 u16 vddc2;
1347 u16 vddc3;
1348 };
1349};
1350
1351struct radeon_cac_leakage_table {
1352 u32 count;
1353 union radeon_cac_leakage_entry *entries;
1354};
1355
1356struct radeon_phase_shedding_limits_entry {
1357 u16 voltage;
1358 u32 sclk;
1359 u32 mclk;
1360};
1361
1362struct radeon_phase_shedding_limits_table {
1363 u32 count;
1364 struct radeon_phase_shedding_limits_entry *entries;
1365};
1366
1367struct radeon_uvd_clock_voltage_dependency_entry {
1368 u32 vclk;
1369 u32 dclk;
1370 u16 v;
1371};
1372
1373struct radeon_uvd_clock_voltage_dependency_table {
1374 u8 count;
1375 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1376};
1377
1378struct radeon_vce_clock_voltage_dependency_entry {
1379 u32 ecclk;
1380 u32 evclk;
1381 u16 v;
1382};
1383
1384struct radeon_vce_clock_voltage_dependency_table {
1385 u8 count;
1386 struct radeon_vce_clock_voltage_dependency_entry *entries;
1387};
1388
1389struct radeon_ppm_table {
1390 u8 ppm_design;
1391 u16 cpu_core_number;
1392 u32 platform_tdp;
1393 u32 small_ac_platform_tdp;
1394 u32 platform_tdc;
1395 u32 small_ac_platform_tdc;
1396 u32 apu_tdp;
1397 u32 dgpu_tdp;
1398 u32 dgpu_ulv_power;
1399 u32 tj_max;
1400};
1401
1402struct radeon_cac_tdp_table {
1403 u16 tdp;
1404 u16 configurable_tdp;
1405 u16 tdc;
1406 u16 battery_power_limit;
1407 u16 small_power_limit;
1408 u16 low_cac_leakage;
1409 u16 high_cac_leakage;
1410 u16 maximum_power_delivery_limit;
1411};
1412
1413struct radeon_dpm_dynamic_state {
1414 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1415 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1416 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
1417 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1418 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1419 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1420 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1421 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1422 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1423 struct radeon_clock_array valid_sclk_values;
1424 struct radeon_clock_array valid_mclk_values;
1425 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1426 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1427 u32 mclk_sclk_ratio;
1428 u32 sclk_mclk_delta;
1429 u16 vddc_vddci_delta;
1430 u16 min_vddc_for_pcie_gen2;
1431 struct radeon_cac_leakage_table cac_leakage_table;
1432 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
1433 struct radeon_ppm_table *ppm_table;
1434 struct radeon_cac_tdp_table *cac_tdp_table;
1435};
1436
1437struct radeon_dpm_fan {
1438 u16 t_min;
1439 u16 t_med;
1440 u16 t_high;
1441 u16 pwm_min;
1442 u16 pwm_med;
1443 u16 pwm_high;
1444 u8 t_hyst;
1445 u32 cycle_delay;
1446 u16 t_max;
1447 bool ucode_fan_control;
1448};
1449
1450enum radeon_pcie_gen {
1451 RADEON_PCIE_GEN1 = 0,
1452 RADEON_PCIE_GEN2 = 1,
1453 RADEON_PCIE_GEN3 = 2,
1454 RADEON_PCIE_GEN_INVALID = 0xffff
1455};
1456
1457enum radeon_dpm_forced_level {
1458 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1459 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1460 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1461};
1462
1463struct radeon_vce_state {
1464 /* vce clocks */
1465 u32 evclk;
1466 u32 ecclk;
1467 /* gpu clocks */
1468 u32 sclk;
1469 u32 mclk;
1470 u8 clk_idx;
1471 u8 pstate;
1472};
1473
1474struct radeon_dpm {
1475 struct radeon_ps *ps;
1476 /* number of valid power states */
1477 int num_ps;
1478 /* current power state that is active */
1479 struct radeon_ps *current_ps;
1480 /* requested power state */
1481 struct radeon_ps *requested_ps;
1482 /* boot up power state */
1483 struct radeon_ps *boot_ps;
1484 /* default uvd power state */
1485 struct radeon_ps *uvd_ps;
1486 /* vce requirements */
1487 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1488 enum radeon_vce_level vce_level;
1489 enum radeon_pm_state_type state;
1490 enum radeon_pm_state_type user_state;
1491 u32 platform_caps;
1492 u32 voltage_response_time;
1493 u32 backbias_response_time;
1494 void *priv;
1495 u32 new_active_crtcs;
1496 int new_active_crtc_count;
1497 u32 current_active_crtcs;
1498 int current_active_crtc_count;
1499 struct radeon_dpm_dynamic_state dyn_state;
1500 struct radeon_dpm_fan fan;
1501 u32 tdp_limit;
1502 u32 near_tdp_limit;
1503 u32 near_tdp_limit_adjusted;
1504 u32 sq_ramping_threshold;
1505 u32 cac_leakage;
1506 u16 tdp_od_limit;
1507 u32 tdp_adjustment;
1508 u16 load_line_slope;
1509 bool power_control;
1510 bool ac_power;
1511 /* special states active */
1512 bool thermal_active;
1513 bool uvd_active;
1514 bool vce_active;
1515 /* thermal handling */
1516 struct radeon_dpm_thermal thermal;
1517 /* forced levels */
1518 enum radeon_dpm_forced_level forced_level;
1519 /* track UVD streams */
1520 unsigned sd;
1521 unsigned hd;
1522};
1523
1524void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
1525void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
1526
1527struct radeon_pm {
1528 struct mutex mutex;
1529 /* write locked while reprogramming mclk */
1530 struct rw_semaphore mclk_lock;
1531 u32 active_crtcs;
1532 int active_crtc_count;
1533 int req_vblank;
1534 bool vblank_sync;
1535 fixed20_12 max_bandwidth;
1536 fixed20_12 igp_sideport_mclk;
1537 fixed20_12 igp_system_mclk;
1538 fixed20_12 igp_ht_link_clk;
1539 fixed20_12 igp_ht_link_width;
1540 fixed20_12 k8_bandwidth;
1541 fixed20_12 sideport_bandwidth;
1542 fixed20_12 ht_bandwidth;
1543 fixed20_12 core_bandwidth;
1544 fixed20_12 sclk;
1545 fixed20_12 mclk;
1546 fixed20_12 needed_bandwidth;
1547 struct radeon_power_state *power_state;
1548 /* number of valid power states */
1549 int num_power_states;
1550 int current_power_state_index;
1551 int current_clock_mode_index;
1552 int requested_power_state_index;
1553 int requested_clock_mode_index;
1554 int default_power_state_index;
1555 u32 current_sclk;
1556 u32 current_mclk;
1557 u16 current_vddc;
1558 u16 current_vddci;
1559 u32 default_sclk;
1560 u32 default_mclk;
1561 u16 default_vddc;
1562 u16 default_vddci;
1563 struct radeon_i2c_chan *i2c_bus;
1564 /* selected pm method */
1565 enum radeon_pm_method pm_method;
1566 /* dynpm power management */
1567 struct delayed_work dynpm_idle_work;
1568 enum radeon_dynpm_state dynpm_state;
1569 enum radeon_dynpm_action dynpm_planned_action;
1570 unsigned long dynpm_action_timeout;
1571 bool dynpm_can_upclock;
1572 bool dynpm_can_downclock;
1573 /* profile-based power management */
1574 enum radeon_pm_profile_type profile;
1575 int profile_index;
1576 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1577 /* internal thermal controller on rv6xx+ */
1578 enum radeon_int_thermal_type int_thermal_type;
1579 struct device *int_hwmon_dev;
1580 /* dpm */
1581 bool dpm_enabled;
1582 struct radeon_dpm dpm;
1583};
1584
1585int radeon_pm_get_type_index(struct radeon_device *rdev,
1586 enum radeon_pm_state_type ps_type,
1587 int instance);
1588/*
1589 * UVD
1590 */
1591#define RADEON_MAX_UVD_HANDLES 10
1592#define RADEON_UVD_STACK_SIZE (1024*1024)
1593#define RADEON_UVD_HEAP_SIZE (1024*1024)
1594
1595struct radeon_uvd {
1596 struct radeon_bo *vcpu_bo;
1597 void *cpu_addr;
1598 uint64_t gpu_addr;
1599 void *saved_bo;
1600 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1601 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
1602 unsigned img_size[RADEON_MAX_UVD_HANDLES];
1603 struct delayed_work idle_work;
1604};
1605
1606int radeon_uvd_init(struct radeon_device *rdev);
1607void radeon_uvd_fini(struct radeon_device *rdev);
1608int radeon_uvd_suspend(struct radeon_device *rdev);
1609int radeon_uvd_resume(struct radeon_device *rdev);
1610int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1611 uint32_t handle, struct radeon_fence **fence);
1612int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1613 uint32_t handle, struct radeon_fence **fence);
1614void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1615void radeon_uvd_free_handles(struct radeon_device *rdev,
1616 struct drm_file *filp);
1617int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1618void radeon_uvd_note_usage(struct radeon_device *rdev);
1619int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1620 unsigned vclk, unsigned dclk,
1621 unsigned vco_min, unsigned vco_max,
1622 unsigned fb_factor, unsigned fb_mask,
1623 unsigned pd_min, unsigned pd_max,
1624 unsigned pd_even,
1625 unsigned *optimal_fb_div,
1626 unsigned *optimal_vclk_div,
1627 unsigned *optimal_dclk_div);
1628int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1629 unsigned cg_upll_func_cntl);
1630
1631/*
1632 * VCE
1633 */
1634#define RADEON_MAX_VCE_HANDLES 16
1635#define RADEON_VCE_STACK_SIZE (1024*1024)
1636#define RADEON_VCE_HEAP_SIZE (4*1024*1024)
1637
1638struct radeon_vce {
1639 struct radeon_bo *vcpu_bo;
1640 uint64_t gpu_addr;
1641 unsigned fw_version;
1642 unsigned fb_version;
1643 atomic_t handles[RADEON_MAX_VCE_HANDLES];
1644 struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
1645 unsigned img_size[RADEON_MAX_VCE_HANDLES];
1646 struct delayed_work idle_work;
1647};
1648
1649int radeon_vce_init(struct radeon_device *rdev);
1650void radeon_vce_fini(struct radeon_device *rdev);
1651int radeon_vce_suspend(struct radeon_device *rdev);
1652int radeon_vce_resume(struct radeon_device *rdev);
1653int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1654 uint32_t handle, struct radeon_fence **fence);
1655int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1656 uint32_t handle, struct radeon_fence **fence);
1657void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
1658void radeon_vce_note_usage(struct radeon_device *rdev);
1659int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
1660int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1661bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1662 struct radeon_ring *ring,
1663 struct radeon_semaphore *semaphore,
1664 bool emit_wait);
1665void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1666void radeon_vce_fence_emit(struct radeon_device *rdev,
1667 struct radeon_fence *fence);
1668int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1669int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1670
1671struct r600_audio_pin {
1672 int channels;
1673 int rate;
1674 int bits_per_sample;
1675 u8 status_bits;
1676 u8 category_code;
1677 u32 offset;
1678 bool connected;
1679 u32 id;
1680};
1681
1682struct r600_audio {
1683 bool enabled;
1684 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1685 int num_pins;
1686};
1687
1688/*
1689 * Benchmarking
1690 */
1691void radeon_benchmark(struct radeon_device *rdev, int test_number);
1692
1693
1694/*
1695 * Testing
1696 */
1697void radeon_test_moves(struct radeon_device *rdev);
1698void radeon_test_ring_sync(struct radeon_device *rdev,
1699 struct radeon_ring *cpA,
1700 struct radeon_ring *cpB);
1701void radeon_test_syncing(struct radeon_device *rdev);
1702
1703
1704/*
1705 * Debugfs
1706 */
1707struct radeon_debugfs {
1708 struct drm_info_list *files;
1709 unsigned num_files;
1710};
1711
1712int radeon_debugfs_add_files(struct radeon_device *rdev,
1713 struct drm_info_list *files,
1714 unsigned nfiles);
1715int radeon_debugfs_fence_init(struct radeon_device *rdev);
1716
1717/*
1718 * ASIC ring specific functions.
1719 */
1720struct radeon_asic_ring {
1721 /* ring read/write ptr handling */
1722 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1723 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1724 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1725
1726 /* validating and patching of IBs */
1727 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1728 int (*cs_parse)(struct radeon_cs_parser *p);
1729
1730 /* command emmit functions */
1731 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1732 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1733 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1734 struct radeon_semaphore *semaphore, bool emit_wait);
1735 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1736
1737 /* testing functions */
1738 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1739 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1740 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1741
1742 /* deprecated */
1743 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1744};
1745
1746/*
1747 * ASIC specific functions.
1748 */
1749struct radeon_asic {
1750 int (*init)(struct radeon_device *rdev);
1751 void (*fini)(struct radeon_device *rdev);
1752 int (*resume)(struct radeon_device *rdev);
1753 int (*suspend)(struct radeon_device *rdev);
1754 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1755 int (*asic_reset)(struct radeon_device *rdev);
1756 /* ioctl hw specific callback. Some hw might want to perform special
1757 * operation on specific ioctl. For instance on wait idle some hw
1758 * might want to perform and HDP flush through MMIO as it seems that
1759 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1760 * through ring.
1761 */
1762 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1763 /* check if 3D engine is idle */
1764 bool (*gui_idle)(struct radeon_device *rdev);
1765 /* wait for mc_idle */
1766 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1767 /* get the reference clock */
1768 u32 (*get_xclk)(struct radeon_device *rdev);
1769 /* get the gpu clock counter */
1770 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1771 /* gart */
1772 struct {
1773 void (*tlb_flush)(struct radeon_device *rdev);
1774 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1775 } gart;
1776 struct {
1777 int (*init)(struct radeon_device *rdev);
1778 void (*fini)(struct radeon_device *rdev);
1779 void (*set_page)(struct radeon_device *rdev,
1780 struct radeon_ib *ib,
1781 uint64_t pe,
1782 uint64_t addr, unsigned count,
1783 uint32_t incr, uint32_t flags);
1784 } vm;
1785 /* ring specific callbacks */
1786 struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
1787 /* irqs */
1788 struct {
1789 int (*set)(struct radeon_device *rdev);
1790 int (*process)(struct radeon_device *rdev);
1791 } irq;
1792 /* displays */
1793 struct {
1794 /* display watermarks */
1795 void (*bandwidth_update)(struct radeon_device *rdev);
1796 /* get frame count */
1797 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1798 /* wait for vblank */
1799 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1800 /* set backlight level */
1801 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1802 /* get backlight level */
1803 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1804 /* audio callbacks */
1805 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1806 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1807 } display;
1808 /* copy functions for bo handling */
1809 struct {
1810 int (*blit)(struct radeon_device *rdev,
1811 uint64_t src_offset,
1812 uint64_t dst_offset,
1813 unsigned num_gpu_pages,
1814 struct radeon_fence **fence);
1815 u32 blit_ring_index;
1816 int (*dma)(struct radeon_device *rdev,
1817 uint64_t src_offset,
1818 uint64_t dst_offset,
1819 unsigned num_gpu_pages,
1820 struct radeon_fence **fence);
1821 u32 dma_ring_index;
1822 /* method used for bo copy */
1823 int (*copy)(struct radeon_device *rdev,
1824 uint64_t src_offset,
1825 uint64_t dst_offset,
1826 unsigned num_gpu_pages,
1827 struct radeon_fence **fence);
1828 /* ring used for bo copies */
1829 u32 copy_ring_index;
1830 } copy;
1831 /* surfaces */
1832 struct {
1833 int (*set_reg)(struct radeon_device *rdev, int reg,
1834 uint32_t tiling_flags, uint32_t pitch,
1835 uint32_t offset, uint32_t obj_size);
1836 void (*clear_reg)(struct radeon_device *rdev, int reg);
1837 } surface;
1838 /* hotplug detect */
1839 struct {
1840 void (*init)(struct radeon_device *rdev);
1841 void (*fini)(struct radeon_device *rdev);
1842 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1843 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1844 } hpd;
1845 /* static power management */
1846 struct {
1847 void (*misc)(struct radeon_device *rdev);
1848 void (*prepare)(struct radeon_device *rdev);
1849 void (*finish)(struct radeon_device *rdev);
1850 void (*init_profile)(struct radeon_device *rdev);
1851 void (*get_dynpm_state)(struct radeon_device *rdev);
1852 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1853 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1854 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1855 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1856 int (*get_pcie_lanes)(struct radeon_device *rdev);
1857 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1858 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1859 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1860 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
1861 int (*get_temperature)(struct radeon_device *rdev);
1862 } pm;
1863 /* dynamic power management */
1864 struct {
1865 int (*init)(struct radeon_device *rdev);
1866 void (*setup_asic)(struct radeon_device *rdev);
1867 int (*enable)(struct radeon_device *rdev);
1868 int (*late_enable)(struct radeon_device *rdev);
1869 void (*disable)(struct radeon_device *rdev);
1870 int (*pre_set_power_state)(struct radeon_device *rdev);
1871 int (*set_power_state)(struct radeon_device *rdev);
1872 void (*post_set_power_state)(struct radeon_device *rdev);
1873 void (*display_configuration_changed)(struct radeon_device *rdev);
1874 void (*fini)(struct radeon_device *rdev);
1875 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1876 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1877 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1878 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
1879 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
1880 bool (*vblank_too_short)(struct radeon_device *rdev);
1881 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1882 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
1883 } dpm;
1884 /* pageflipping */
1885 struct {
1886 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1887 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1888 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1889 } pflip;
1890};
1891
1892/*
1893 * Asic structures
1894 */
1895struct r100_asic {
1896 const unsigned *reg_safe_bm;
1897 unsigned reg_safe_bm_size;
1898 u32 hdp_cntl;
1899};
1900
1901struct r300_asic {
1902 const unsigned *reg_safe_bm;
1903 unsigned reg_safe_bm_size;
1904 u32 resync_scratch;
1905 u32 hdp_cntl;
1906};
1907
1908struct r600_asic {
1909 unsigned max_pipes;
1910 unsigned max_tile_pipes;
1911 unsigned max_simds;
1912 unsigned max_backends;
1913 unsigned max_gprs;
1914 unsigned max_threads;
1915 unsigned max_stack_entries;
1916 unsigned max_hw_contexts;
1917 unsigned max_gs_threads;
1918 unsigned sx_max_export_size;
1919 unsigned sx_max_export_pos_size;
1920 unsigned sx_max_export_smx_size;
1921 unsigned sq_num_cf_insts;
1922 unsigned tiling_nbanks;
1923 unsigned tiling_npipes;
1924 unsigned tiling_group_size;
1925 unsigned tile_config;
1926 unsigned backend_map;
1927};
1928
1929struct rv770_asic {
1930 unsigned max_pipes;
1931 unsigned max_tile_pipes;
1932 unsigned max_simds;
1933 unsigned max_backends;
1934 unsigned max_gprs;
1935 unsigned max_threads;
1936 unsigned max_stack_entries;
1937 unsigned max_hw_contexts;
1938 unsigned max_gs_threads;
1939 unsigned sx_max_export_size;
1940 unsigned sx_max_export_pos_size;
1941 unsigned sx_max_export_smx_size;
1942 unsigned sq_num_cf_insts;
1943 unsigned sx_num_of_sets;
1944 unsigned sc_prim_fifo_size;
1945 unsigned sc_hiz_tile_fifo_size;
1946 unsigned sc_earlyz_tile_fifo_fize;
1947 unsigned tiling_nbanks;
1948 unsigned tiling_npipes;
1949 unsigned tiling_group_size;
1950 unsigned tile_config;
1951 unsigned backend_map;
1952};
1953
1954struct evergreen_asic {
1955 unsigned num_ses;
1956 unsigned max_pipes;
1957 unsigned max_tile_pipes;
1958 unsigned max_simds;
1959 unsigned max_backends;
1960 unsigned max_gprs;
1961 unsigned max_threads;
1962 unsigned max_stack_entries;
1963 unsigned max_hw_contexts;
1964 unsigned max_gs_threads;
1965 unsigned sx_max_export_size;
1966 unsigned sx_max_export_pos_size;
1967 unsigned sx_max_export_smx_size;
1968 unsigned sq_num_cf_insts;
1969 unsigned sx_num_of_sets;
1970 unsigned sc_prim_fifo_size;
1971 unsigned sc_hiz_tile_fifo_size;
1972 unsigned sc_earlyz_tile_fifo_size;
1973 unsigned tiling_nbanks;
1974 unsigned tiling_npipes;
1975 unsigned tiling_group_size;
1976 unsigned tile_config;
1977 unsigned backend_map;
1978};
1979
1980struct cayman_asic {
1981 unsigned max_shader_engines;
1982 unsigned max_pipes_per_simd;
1983 unsigned max_tile_pipes;
1984 unsigned max_simds_per_se;
1985 unsigned max_backends_per_se;
1986 unsigned max_texture_channel_caches;
1987 unsigned max_gprs;
1988 unsigned max_threads;
1989 unsigned max_gs_threads;
1990 unsigned max_stack_entries;
1991 unsigned sx_num_of_sets;
1992 unsigned sx_max_export_size;
1993 unsigned sx_max_export_pos_size;
1994 unsigned sx_max_export_smx_size;
1995 unsigned max_hw_contexts;
1996 unsigned sq_num_cf_insts;
1997 unsigned sc_prim_fifo_size;
1998 unsigned sc_hiz_tile_fifo_size;
1999 unsigned sc_earlyz_tile_fifo_size;
2000
2001 unsigned num_shader_engines;
2002 unsigned num_shader_pipes_per_simd;
2003 unsigned num_tile_pipes;
2004 unsigned num_simds_per_se;
2005 unsigned num_backends_per_se;
2006 unsigned backend_disable_mask_per_asic;
2007 unsigned backend_map;
2008 unsigned num_texture_channel_caches;
2009 unsigned mem_max_burst_length_bytes;
2010 unsigned mem_row_size_in_kb;
2011 unsigned shader_engine_tile_size;
2012 unsigned num_gpus;
2013 unsigned multi_gpu_tile_size;
2014
2015 unsigned tile_config;
2016};
2017
2018struct si_asic {
2019 unsigned max_shader_engines;
2020 unsigned max_tile_pipes;
2021 unsigned max_cu_per_sh;
2022 unsigned max_sh_per_se;
2023 unsigned max_backends_per_se;
2024 unsigned max_texture_channel_caches;
2025 unsigned max_gprs;
2026 unsigned max_gs_threads;
2027 unsigned max_hw_contexts;
2028 unsigned sc_prim_fifo_size_frontend;
2029 unsigned sc_prim_fifo_size_backend;
2030 unsigned sc_hiz_tile_fifo_size;
2031 unsigned sc_earlyz_tile_fifo_size;
2032
2033 unsigned num_tile_pipes;
2034 unsigned backend_enable_mask;
2035 unsigned backend_disable_mask_per_asic;
2036 unsigned backend_map;
2037 unsigned num_texture_channel_caches;
2038 unsigned mem_max_burst_length_bytes;
2039 unsigned mem_row_size_in_kb;
2040 unsigned shader_engine_tile_size;
2041 unsigned num_gpus;
2042 unsigned multi_gpu_tile_size;
2043
2044 unsigned tile_config;
2045 uint32_t tile_mode_array[32];
2046};
2047
2048struct cik_asic {
2049 unsigned max_shader_engines;
2050 unsigned max_tile_pipes;
2051 unsigned max_cu_per_sh;
2052 unsigned max_sh_per_se;
2053 unsigned max_backends_per_se;
2054 unsigned max_texture_channel_caches;
2055 unsigned max_gprs;
2056 unsigned max_gs_threads;
2057 unsigned max_hw_contexts;
2058 unsigned sc_prim_fifo_size_frontend;
2059 unsigned sc_prim_fifo_size_backend;
2060 unsigned sc_hiz_tile_fifo_size;
2061 unsigned sc_earlyz_tile_fifo_size;
2062
2063 unsigned num_tile_pipes;
2064 unsigned backend_enable_mask;
2065 unsigned backend_disable_mask_per_asic;
2066 unsigned backend_map;
2067 unsigned num_texture_channel_caches;
2068 unsigned mem_max_burst_length_bytes;
2069 unsigned mem_row_size_in_kb;
2070 unsigned shader_engine_tile_size;
2071 unsigned num_gpus;
2072 unsigned multi_gpu_tile_size;
2073
2074 unsigned tile_config;
2075 uint32_t tile_mode_array[32];
2076 uint32_t macrotile_mode_array[16];
2077};
2078
2079union radeon_asic_config {
2080 struct r300_asic r300;
2081 struct r100_asic r100;
2082 struct r600_asic r600;
2083 struct rv770_asic rv770;
2084 struct evergreen_asic evergreen;
2085 struct cayman_asic cayman;
2086 struct si_asic si;
2087 struct cik_asic cik;
2088};
2089
2090/*
2091 * asic initizalization from radeon_asic.c
2092 */
2093void radeon_agp_disable(struct radeon_device *rdev);
2094int radeon_asic_init(struct radeon_device *rdev);
2095
2096
2097/*
2098 * IOCTL.
2099 */
2100int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2101 struct drm_file *filp);
2102int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2103 struct drm_file *filp);
2104int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2105 struct drm_file *file_priv);
2106int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2107 struct drm_file *file_priv);
2108int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2109 struct drm_file *file_priv);
2110int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2111 struct drm_file *file_priv);
2112int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2113 struct drm_file *filp);
2114int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2115 struct drm_file *filp);
2116int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2117 struct drm_file *filp);
2118int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2119 struct drm_file *filp);
2120int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2121 struct drm_file *filp);
2122int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2123 struct drm_file *filp);
2124int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
2125int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2126 struct drm_file *filp);
2127int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2128 struct drm_file *filp);
2129
2130/* VRAM scratch page for HDP bug, default vram page */
2131struct r600_vram_scratch {
2132 struct radeon_bo *robj;
2133 volatile uint32_t *ptr;
2134 u64 gpu_addr;
2135};
2136
2137/*
2138 * ACPI
2139 */
2140struct radeon_atif_notification_cfg {
2141 bool enabled;
2142 int command_code;
2143};
2144
2145struct radeon_atif_notifications {
2146 bool display_switch;
2147 bool expansion_mode_change;
2148 bool thermal_state;
2149 bool forced_power_state;
2150 bool system_power_state;
2151 bool display_conf_change;
2152 bool px_gfx_switch;
2153 bool brightness_change;
2154 bool dgpu_display_event;
2155};
2156
2157struct radeon_atif_functions {
2158 bool system_params;
2159 bool sbios_requests;
2160 bool select_active_disp;
2161 bool lid_state;
2162 bool get_tv_standard;
2163 bool set_tv_standard;
2164 bool get_panel_expansion_mode;
2165 bool set_panel_expansion_mode;
2166 bool temperature_change;
2167 bool graphics_device_types;
2168};
2169
2170struct radeon_atif {
2171 struct radeon_atif_notifications notifications;
2172 struct radeon_atif_functions functions;
2173 struct radeon_atif_notification_cfg notification_cfg;
2174 struct radeon_encoder *encoder_for_bl;
2175};
2176
2177struct radeon_atcs_functions {
2178 bool get_ext_state;
2179 bool pcie_perf_req;
2180 bool pcie_dev_rdy;
2181 bool pcie_bus_width;
2182};
2183
2184struct radeon_atcs {
2185 struct radeon_atcs_functions functions;
2186};
2187
2188/*
2189 * Core structure, functions and helpers.
2190 */
2191typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2192typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2193
2194struct radeon_device {
2195 struct device *dev;
2196 struct drm_device *ddev;
2197 struct pci_dev *pdev;
2198 struct rw_semaphore exclusive_lock;
2199 /* ASIC */
2200 union radeon_asic_config config;
2201 enum radeon_family family;
2202 unsigned long flags;
2203 int usec_timeout;
2204 enum radeon_pll_errata pll_errata;
2205 int num_gb_pipes;
2206 int num_z_pipes;
2207 int disp_priority;
2208 /* BIOS */
2209 uint8_t *bios;
2210 bool is_atom_bios;
2211 uint16_t bios_header_start;
2212 struct radeon_bo *stollen_vga_memory;
2213 /* Register mmio */
2214 resource_size_t rmmio_base;
2215 resource_size_t rmmio_size;
2216 /* protects concurrent MM_INDEX/DATA based register access */
2217 spinlock_t mmio_idx_lock;
2218 /* protects concurrent SMC based register access */
2219 spinlock_t smc_idx_lock;
2220 /* protects concurrent PLL register access */
2221 spinlock_t pll_idx_lock;
2222 /* protects concurrent MC register access */
2223 spinlock_t mc_idx_lock;
2224 /* protects concurrent PCIE register access */
2225 spinlock_t pcie_idx_lock;
2226 /* protects concurrent PCIE_PORT register access */
2227 spinlock_t pciep_idx_lock;
2228 /* protects concurrent PIF register access */
2229 spinlock_t pif_idx_lock;
2230 /* protects concurrent CG register access */
2231 spinlock_t cg_idx_lock;
2232 /* protects concurrent UVD register access */
2233 spinlock_t uvd_idx_lock;
2234 /* protects concurrent RCU register access */
2235 spinlock_t rcu_idx_lock;
2236 /* protects concurrent DIDT register access */
2237 spinlock_t didt_idx_lock;
2238 /* protects concurrent ENDPOINT (audio) register access */
2239 spinlock_t end_idx_lock;
2240 void __iomem *rmmio;
2241 radeon_rreg_t mc_rreg;
2242 radeon_wreg_t mc_wreg;
2243 radeon_rreg_t pll_rreg;
2244 radeon_wreg_t pll_wreg;
2245 uint32_t pcie_reg_mask;
2246 radeon_rreg_t pciep_rreg;
2247 radeon_wreg_t pciep_wreg;
2248 /* io port */
2249 void __iomem *rio_mem;
2250 resource_size_t rio_mem_size;
2251 struct radeon_clock clock;
2252 struct radeon_mc mc;
2253 struct radeon_gart gart;
2254 struct radeon_mode_info mode_info;
2255 struct radeon_scratch scratch;
2256 struct radeon_doorbell doorbell;
2257 struct radeon_mman mman;
2258 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
2259 wait_queue_head_t fence_queue;
2260 struct mutex ring_lock;
2261 struct radeon_ring ring[RADEON_NUM_RINGS];
2262 bool ib_pool_ready;
2263 struct radeon_sa_manager ring_tmp_bo;
2264 struct radeon_irq irq;
2265 struct radeon_asic *asic;
2266 struct radeon_gem gem;
2267 struct radeon_pm pm;
2268 struct radeon_uvd uvd;
2269 struct radeon_vce vce;
2270 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
2271 struct radeon_wb wb;
2272 struct radeon_dummy_page dummy_page;
2273 bool shutdown;
2274 bool suspend;
2275 bool need_dma32;
2276 bool accel_working;
2277 bool fastfb_working; /* IGP feature*/
2278 bool needs_reset;
2279 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
2280 const struct firmware *me_fw; /* all family ME firmware */
2281 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
2282 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
2283 const struct firmware *mc_fw; /* NI MC firmware */
2284 const struct firmware *ce_fw; /* SI CE firmware */
2285 const struct firmware *mec_fw; /* CIK MEC firmware */
2286 const struct firmware *sdma_fw; /* CIK SDMA firmware */
2287 const struct firmware *smc_fw; /* SMC firmware */
2288 const struct firmware *uvd_fw; /* UVD firmware */
2289 const struct firmware *vce_fw; /* VCE firmware */
2290 struct r600_vram_scratch vram_scratch;
2291 int msi_enabled; /* msi enabled */
2292 struct r600_ih ih; /* r6/700 interrupt ring */
2293 struct radeon_rlc rlc;
2294 struct radeon_mec mec;
2295 struct work_struct hotplug_work;
2296 struct work_struct audio_work;
2297 struct work_struct reset_work;
2298 int num_crtc; /* number of crtcs */
2299 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
2300 bool has_uvd;
2301 struct r600_audio audio; /* audio stuff */
2302 struct notifier_block acpi_nb;
2303 /* only one userspace can use Hyperz features or CMASK at a time */
2304 struct drm_file *hyperz_filp;
2305 struct drm_file *cmask_filp;
2306 /* i2c buses */
2307 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
2308 /* debugfs */
2309 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2310 unsigned debugfs_count;
2311 /* virtual memory */
2312 struct radeon_vm_manager vm_manager;
2313 struct mutex gpu_clock_mutex;
2314 /* memory stats */
2315 atomic64_t vram_usage;
2316 atomic64_t gtt_usage;
2317 atomic64_t num_bytes_moved;
2318 /* ACPI interface */
2319 struct radeon_atif atif;
2320 struct radeon_atcs atcs;
2321 /* srbm instance registers */
2322 struct mutex srbm_mutex;
2323 /* clock, powergating flags */
2324 u32 cg_flags;
2325 u32 pg_flags;
2326
2327 struct dev_pm_domain vga_pm_domain;
2328 bool have_disp_power_ref;
2329};
2330
2331bool radeon_is_px(struct drm_device *dev);
2332int radeon_device_init(struct radeon_device *rdev,
2333 struct drm_device *ddev,
2334 struct pci_dev *pdev,
2335 uint32_t flags);
2336void radeon_device_fini(struct radeon_device *rdev);
2337int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2338
2339uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2340 bool always_indirect);
2341void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2342 bool always_indirect);
2343u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2344void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2345
2346u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2347void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
2348
2349/*
2350 * Cast helper
2351 */
2352#define to_radeon_fence(p) ((struct radeon_fence *)(p))
2353
2354/*
2355 * Registers read & write functions.
2356 */
2357#define RREG8(reg) readb((rdev->rmmio) + (reg))
2358#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2359#define RREG16(reg) readw((rdev->rmmio) + (reg))
2360#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2361#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2362#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2363#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2364#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2365#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
2366#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2367#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2368#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2369#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2370#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2371#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
2372#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2373#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
2374#define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2375#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
2376#define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2377#define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
2378#define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2379#define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
2380#define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2381#define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
2382#define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2383#define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2384#define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2385#define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
2386#define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2387#define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
2388#define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2389#define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
2390#define WREG32_P(reg, val, mask) \
2391 do { \
2392 uint32_t tmp_ = RREG32(reg); \
2393 tmp_ &= (mask); \
2394 tmp_ |= ((val) & ~(mask)); \
2395 WREG32(reg, tmp_); \
2396 } while (0)
2397#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2398#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2399#define WREG32_PLL_P(reg, val, mask) \
2400 do { \
2401 uint32_t tmp_ = RREG32_PLL(reg); \
2402 tmp_ &= (mask); \
2403 tmp_ |= ((val) & ~(mask)); \
2404 WREG32_PLL(reg, tmp_); \
2405 } while (0)
2406#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
2407#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2408#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
2409
2410#define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2411#define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
2412
2413/*
2414 * Indirect registers accessor
2415 */
2416static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2417{
2418 unsigned long flags;
2419 uint32_t r;
2420
2421 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
2422 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2423 r = RREG32(RADEON_PCIE_DATA);
2424 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
2425 return r;
2426}
2427
2428static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2429{
2430 unsigned long flags;
2431
2432 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
2433 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2434 WREG32(RADEON_PCIE_DATA, (v));
2435 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
2436}
2437
2438static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2439{
2440 unsigned long flags;
2441 u32 r;
2442
2443 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
2444 WREG32(TN_SMC_IND_INDEX_0, (reg));
2445 r = RREG32(TN_SMC_IND_DATA_0);
2446 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
2447 return r;
2448}
2449
2450static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2451{
2452 unsigned long flags;
2453
2454 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
2455 WREG32(TN_SMC_IND_INDEX_0, (reg));
2456 WREG32(TN_SMC_IND_DATA_0, (v));
2457 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
2458}
2459
2460static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2461{
2462 unsigned long flags;
2463 u32 r;
2464
2465 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
2466 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2467 r = RREG32(R600_RCU_DATA);
2468 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
2469 return r;
2470}
2471
2472static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2473{
2474 unsigned long flags;
2475
2476 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
2477 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2478 WREG32(R600_RCU_DATA, (v));
2479 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
2480}
2481
2482static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2483{
2484 unsigned long flags;
2485 u32 r;
2486
2487 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
2488 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2489 r = RREG32(EVERGREEN_CG_IND_DATA);
2490 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
2491 return r;
2492}
2493
2494static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2495{
2496 unsigned long flags;
2497
2498 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
2499 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2500 WREG32(EVERGREEN_CG_IND_DATA, (v));
2501 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
2502}
2503
2504static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2505{
2506 unsigned long flags;
2507 u32 r;
2508
2509 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2510 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2511 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
2512 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2513 return r;
2514}
2515
2516static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2517{
2518 unsigned long flags;
2519
2520 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2521 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2522 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
2523 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2524}
2525
2526static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2527{
2528 unsigned long flags;
2529 u32 r;
2530
2531 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2532 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2533 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
2534 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2535 return r;
2536}
2537
2538static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2539{
2540 unsigned long flags;
2541
2542 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2543 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2544 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
2545 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2546}
2547
2548static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2549{
2550 unsigned long flags;
2551 u32 r;
2552
2553 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
2554 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2555 r = RREG32(R600_UVD_CTX_DATA);
2556 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
2557 return r;
2558}
2559
2560static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2561{
2562 unsigned long flags;
2563
2564 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
2565 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2566 WREG32(R600_UVD_CTX_DATA, (v));
2567 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
2568}
2569
2570
2571static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
2572{
2573 unsigned long flags;
2574 u32 r;
2575
2576 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
2577 WREG32(CIK_DIDT_IND_INDEX, (reg));
2578 r = RREG32(CIK_DIDT_IND_DATA);
2579 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
2580 return r;
2581}
2582
2583static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2584{
2585 unsigned long flags;
2586
2587 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
2588 WREG32(CIK_DIDT_IND_INDEX, (reg));
2589 WREG32(CIK_DIDT_IND_DATA, (v));
2590 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
2591}
2592
2593void r100_pll_errata_after_index(struct radeon_device *rdev);
2594
2595
2596/*
2597 * ASICs helpers.
2598 */
2599#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2600 (rdev->pdev->device == 0x5969))
2601#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2602 (rdev->family == CHIP_RV200) || \
2603 (rdev->family == CHIP_RS100) || \
2604 (rdev->family == CHIP_RS200) || \
2605 (rdev->family == CHIP_RV250) || \
2606 (rdev->family == CHIP_RV280) || \
2607 (rdev->family == CHIP_RS300))
2608#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2609 (rdev->family == CHIP_RV350) || \
2610 (rdev->family == CHIP_R350) || \
2611 (rdev->family == CHIP_RV380) || \
2612 (rdev->family == CHIP_R420) || \
2613 (rdev->family == CHIP_R423) || \
2614 (rdev->family == CHIP_RV410) || \
2615 (rdev->family == CHIP_RS400) || \
2616 (rdev->family == CHIP_RS480))
2617#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2618 (rdev->ddev->pdev->device == 0x9443) || \
2619 (rdev->ddev->pdev->device == 0x944B) || \
2620 (rdev->ddev->pdev->device == 0x9506) || \
2621 (rdev->ddev->pdev->device == 0x9509) || \
2622 (rdev->ddev->pdev->device == 0x950F) || \
2623 (rdev->ddev->pdev->device == 0x689C) || \
2624 (rdev->ddev->pdev->device == 0x689D))
2625#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
2626#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2627 (rdev->family == CHIP_RS690) || \
2628 (rdev->family == CHIP_RS740) || \
2629 (rdev->family >= CHIP_R600))
2630#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2631#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
2632#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
2633#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2634 (rdev->flags & RADEON_IS_IGP))
2635#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2636#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2637#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2638 (rdev->flags & RADEON_IS_IGP))
2639#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
2640#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
2641#define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
2642#define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2643#define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
2644#define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2645 (rdev->family == CHIP_MULLINS))
2646
2647#define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2648 (rdev->ddev->pdev->device == 0x6850) || \
2649 (rdev->ddev->pdev->device == 0x6858) || \
2650 (rdev->ddev->pdev->device == 0x6859) || \
2651 (rdev->ddev->pdev->device == 0x6840) || \
2652 (rdev->ddev->pdev->device == 0x6841) || \
2653 (rdev->ddev->pdev->device == 0x6842) || \
2654 (rdev->ddev->pdev->device == 0x6843))
2655
2656/*
2657 * BIOS helpers.
2658 */
2659#define RBIOS8(i) (rdev->bios[i])
2660#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2661#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2662
2663int radeon_combios_init(struct radeon_device *rdev);
2664void radeon_combios_fini(struct radeon_device *rdev);
2665int radeon_atombios_init(struct radeon_device *rdev);
2666void radeon_atombios_fini(struct radeon_device *rdev);
2667
2668
2669/*
2670 * RING helpers.
2671 */
2672#if DRM_DEBUG_CODE == 0
2673static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2674{
2675 ring->ring[ring->wptr++] = v;
2676 ring->wptr &= ring->ptr_mask;
2677 ring->count_dw--;
2678 ring->ring_free_dw--;
2679}
2680#else
2681/* With debugging this is just too big to inline */
2682void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
2683#endif
2684
2685/*
2686 * ASICs macro.
2687 */
2688#define radeon_init(rdev) (rdev)->asic->init((rdev))
2689#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2690#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2691#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2692#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
2693#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2694#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
2695#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2696#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
2697#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2698#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2699#define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2700#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2701#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2702#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2703#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2704#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2705#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2706#define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm))
2707#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2708#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2709#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
2710#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2711#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2712#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2713#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2714#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2715#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2716#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2717#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2718#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2719#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
2720#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
2721#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
2722#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2723#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2724#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2725#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2726#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2727#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2728#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2729#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2730#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2731#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2732#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2733#define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
2734#define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2735#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2736#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2737#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
2738#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2739#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2740#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2741#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
2742#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2743#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2744#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2745#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2746#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2747#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
2748#define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc))
2749#define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2750#define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc))
2751#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2752#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
2753#define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
2754#define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
2755#define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2756#define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2757#define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2758#define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
2759#define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2760#define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2761#define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2762#define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
2763#define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2764#define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2765#define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2766#define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2767#define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
2768#define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
2769#define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
2770#define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
2771#define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
2772#define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
2773
2774/* Common functions */
2775/* AGP */
2776extern int radeon_gpu_reset(struct radeon_device *rdev);
2777extern void radeon_pci_config_reset(struct radeon_device *rdev);
2778extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
2779extern void radeon_agp_disable(struct radeon_device *rdev);
2780extern int radeon_modeset_init(struct radeon_device *rdev);
2781extern void radeon_modeset_fini(struct radeon_device *rdev);
2782extern bool radeon_card_posted(struct radeon_device *rdev);
2783extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
2784extern void radeon_update_display_priority(struct radeon_device *rdev);
2785extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
2786extern void radeon_scratch_init(struct radeon_device *rdev);
2787extern void radeon_wb_fini(struct radeon_device *rdev);
2788extern int radeon_wb_init(struct radeon_device *rdev);
2789extern void radeon_wb_disable(struct radeon_device *rdev);
2790extern void radeon_surface_init(struct radeon_device *rdev);
2791extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2792extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2793extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2794extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2795extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2796extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2797extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2798extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2799extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2800extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2801extern void radeon_program_register_sequence(struct radeon_device *rdev,
2802 const u32 *registers,
2803 const u32 array_size);
2804
2805/*
2806 * vm
2807 */
2808int radeon_vm_manager_init(struct radeon_device *rdev);
2809void radeon_vm_manager_fini(struct radeon_device *rdev);
2810int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
2811void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
2812struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev,
2813 struct radeon_vm *vm,
2814 struct list_head *head);
2815struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2816 struct radeon_vm *vm, int ring);
2817void radeon_vm_flush(struct radeon_device *rdev,
2818 struct radeon_vm *vm,
2819 int ring);
2820void radeon_vm_fence(struct radeon_device *rdev,
2821 struct radeon_vm *vm,
2822 struct radeon_fence *fence);
2823uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2824int radeon_vm_update_page_directory(struct radeon_device *rdev,
2825 struct radeon_vm *vm);
2826int radeon_vm_bo_update(struct radeon_device *rdev,
2827 struct radeon_vm *vm,
2828 struct radeon_bo *bo,
2829 struct ttm_mem_reg *mem);
2830void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2831 struct radeon_bo *bo);
2832struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2833 struct radeon_bo *bo);
2834struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2835 struct radeon_vm *vm,
2836 struct radeon_bo *bo);
2837int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2838 struct radeon_bo_va *bo_va,
2839 uint64_t offset,
2840 uint32_t flags);
2841int radeon_vm_bo_rmv(struct radeon_device *rdev,
2842 struct radeon_bo_va *bo_va);
2843
2844/* audio */
2845void r600_audio_update_hdmi(struct work_struct *work);
2846struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2847struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
2848void r600_audio_enable(struct radeon_device *rdev,
2849 struct r600_audio_pin *pin,
2850 bool enable);
2851void dce6_audio_enable(struct radeon_device *rdev,
2852 struct r600_audio_pin *pin,
2853 bool enable);
2854
2855/*
2856 * R600 vram scratch functions
2857 */
2858int r600_vram_scratch_init(struct radeon_device *rdev);
2859void r600_vram_scratch_fini(struct radeon_device *rdev);
2860
2861/*
2862 * r600 cs checking helper
2863 */
2864unsigned r600_mip_minify(unsigned size, unsigned level);
2865bool r600_fmt_is_valid_color(u32 format);
2866bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2867int r600_fmt_get_blocksize(u32 format);
2868int r600_fmt_get_nblocksx(u32 format, u32 w);
2869int r600_fmt_get_nblocksy(u32 format, u32 h);
2870
2871/*
2872 * r600 functions used by radeon_encoder.c
2873 */
2874struct radeon_hdmi_acr {
2875 u32 clock;
2876
2877 int n_32khz;
2878 int cts_32khz;
2879
2880 int n_44_1khz;
2881 int cts_44_1khz;
2882
2883 int n_48khz;
2884 int cts_48khz;
2885
2886};
2887
2888extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2889
2890extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2891 u32 tiling_pipe_num,
2892 u32 max_rb_num,
2893 u32 total_max_rb_num,
2894 u32 enabled_rb_mask);
2895
2896/*
2897 * evergreen functions used by radeon_encoder.c
2898 */
2899
2900extern int ni_init_microcode(struct radeon_device *rdev);
2901extern int ni_mc_load_microcode(struct radeon_device *rdev);
2902
2903/* radeon_acpi.c */
2904#if defined(CONFIG_ACPI)
2905extern int radeon_acpi_init(struct radeon_device *rdev);
2906extern void radeon_acpi_fini(struct radeon_device *rdev);
2907extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2908extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
2909 u8 perf_req, bool advertise);
2910extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
2911#else
2912static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2913static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2914#endif
2915
2916int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2917 struct radeon_cs_packet *pkt,
2918 unsigned idx);
2919bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
2920void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2921 struct radeon_cs_packet *pkt);
2922int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2923 struct radeon_cs_reloc **cs_reloc,
2924 int nomm);
2925int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2926 uint32_t *vline_start_end,
2927 uint32_t *vline_status);
2928
2929#include "radeon_object.h"
2930
2931#endif