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1/*
2 * MUSB OTG driver core code
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35/*
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
37 *
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
42 *
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
47 *
48 *
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
53 *
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
56 *
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
61 *
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
66 * each direction.
67 *
68 * RESULT: one device may be perceived as blocking another one.
69 *
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
74 *
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
80 */
81
82/*
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific information
87 * (plus recentrly, SOC or family details)
88 *
89 * Most of the conditional compilation will (someday) vanish.
90 */
91
92#include <linux/module.h>
93#include <linux/kernel.h>
94#include <linux/sched.h>
95#include <linux/slab.h>
96#include <linux/list.h>
97#include <linux/kobject.h>
98#include <linux/prefetch.h>
99#include <linux/platform_device.h>
100#include <linux/io.h>
101#include <linux/dma-mapping.h>
102#include <linux/usb.h>
103
104#include "musb_core.h"
105
106#define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
107
108
109#define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
110#define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
111
112#define MUSB_VERSION "6.0"
113
114#define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
115
116#define MUSB_DRIVER_NAME "musb-hdrc"
117const char musb_driver_name[] = MUSB_DRIVER_NAME;
118
119MODULE_DESCRIPTION(DRIVER_INFO);
120MODULE_AUTHOR(DRIVER_AUTHOR);
121MODULE_LICENSE("GPL");
122MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
123
124
125/*-------------------------------------------------------------------------*/
126
127static inline struct musb *dev_to_musb(struct device *dev)
128{
129 return dev_get_drvdata(dev);
130}
131
132/*-------------------------------------------------------------------------*/
133
134#ifndef CONFIG_BLACKFIN
135static int musb_ulpi_read(struct usb_phy *phy, u32 reg)
136{
137 void __iomem *addr = phy->io_priv;
138 int i = 0;
139 u8 r;
140 u8 power;
141 int ret;
142
143 pm_runtime_get_sync(phy->io_dev);
144
145 /* Make sure the transceiver is not in low power mode */
146 power = musb_readb(addr, MUSB_POWER);
147 power &= ~MUSB_POWER_SUSPENDM;
148 musb_writeb(addr, MUSB_POWER, power);
149
150 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
151 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
152 */
153
154 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg);
155 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
156 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
157
158 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
159 & MUSB_ULPI_REG_CMPLT)) {
160 i++;
161 if (i == 10000) {
162 ret = -ETIMEDOUT;
163 goto out;
164 }
165
166 }
167 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
168 r &= ~MUSB_ULPI_REG_CMPLT;
169 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
170
171 ret = musb_readb(addr, MUSB_ULPI_REG_DATA);
172
173out:
174 pm_runtime_put(phy->io_dev);
175
176 return ret;
177}
178
179static int musb_ulpi_write(struct usb_phy *phy, u32 val, u32 reg)
180{
181 void __iomem *addr = phy->io_priv;
182 int i = 0;
183 u8 r = 0;
184 u8 power;
185 int ret = 0;
186
187 pm_runtime_get_sync(phy->io_dev);
188
189 /* Make sure the transceiver is not in low power mode */
190 power = musb_readb(addr, MUSB_POWER);
191 power &= ~MUSB_POWER_SUSPENDM;
192 musb_writeb(addr, MUSB_POWER, power);
193
194 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg);
195 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)val);
196 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
197
198 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
199 & MUSB_ULPI_REG_CMPLT)) {
200 i++;
201 if (i == 10000) {
202 ret = -ETIMEDOUT;
203 goto out;
204 }
205 }
206
207 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
208 r &= ~MUSB_ULPI_REG_CMPLT;
209 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
210
211out:
212 pm_runtime_put(phy->io_dev);
213
214 return ret;
215}
216#else
217#define musb_ulpi_read NULL
218#define musb_ulpi_write NULL
219#endif
220
221static struct usb_phy_io_ops musb_ulpi_access = {
222 .read = musb_ulpi_read,
223 .write = musb_ulpi_write,
224};
225
226/*-------------------------------------------------------------------------*/
227
228static u32 musb_default_fifo_offset(u8 epnum)
229{
230 return 0x20 + (epnum * 4);
231}
232
233/* "flat" mapping: each endpoint has its own i/o address */
234static void musb_flat_ep_select(void __iomem *mbase, u8 epnum)
235{
236}
237
238static u32 musb_flat_ep_offset(u8 epnum, u16 offset)
239{
240 return 0x100 + (0x10 * epnum) + offset;
241}
242
243/* "indexed" mapping: INDEX register controls register bank select */
244static void musb_indexed_ep_select(void __iomem *mbase, u8 epnum)
245{
246 musb_writeb(mbase, MUSB_INDEX, epnum);
247}
248
249static u32 musb_indexed_ep_offset(u8 epnum, u16 offset)
250{
251 return 0x10 + offset;
252}
253
254static u32 musb_default_busctl_offset(u8 epnum, u16 offset)
255{
256 return 0x80 + (0x08 * epnum) + offset;
257}
258
259static u8 musb_default_readb(const void __iomem *addr, unsigned offset)
260{
261 return __raw_readb(addr + offset);
262}
263
264static void musb_default_writeb(void __iomem *addr, unsigned offset, u8 data)
265{
266 __raw_writeb(data, addr + offset);
267}
268
269static u16 musb_default_readw(const void __iomem *addr, unsigned offset)
270{
271 return __raw_readw(addr + offset);
272}
273
274static void musb_default_writew(void __iomem *addr, unsigned offset, u16 data)
275{
276 __raw_writew(data, addr + offset);
277}
278
279static u32 musb_default_readl(const void __iomem *addr, unsigned offset)
280{
281 return __raw_readl(addr + offset);
282}
283
284static void musb_default_writel(void __iomem *addr, unsigned offset, u32 data)
285{
286 __raw_writel(data, addr + offset);
287}
288
289/*
290 * Load an endpoint's FIFO
291 */
292static void musb_default_write_fifo(struct musb_hw_ep *hw_ep, u16 len,
293 const u8 *src)
294{
295 struct musb *musb = hw_ep->musb;
296 void __iomem *fifo = hw_ep->fifo;
297
298 if (unlikely(len == 0))
299 return;
300
301 prefetch((u8 *)src);
302
303 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
304 'T', hw_ep->epnum, fifo, len, src);
305
306 /* we can't assume unaligned reads work */
307 if (likely((0x01 & (unsigned long) src) == 0)) {
308 u16 index = 0;
309
310 /* best case is 32bit-aligned source address */
311 if ((0x02 & (unsigned long) src) == 0) {
312 if (len >= 4) {
313 iowrite32_rep(fifo, src + index, len >> 2);
314 index += len & ~0x03;
315 }
316 if (len & 0x02) {
317 __raw_writew(*(u16 *)&src[index], fifo);
318 index += 2;
319 }
320 } else {
321 if (len >= 2) {
322 iowrite16_rep(fifo, src + index, len >> 1);
323 index += len & ~0x01;
324 }
325 }
326 if (len & 0x01)
327 __raw_writeb(src[index], fifo);
328 } else {
329 /* byte aligned */
330 iowrite8_rep(fifo, src, len);
331 }
332}
333
334/*
335 * Unload an endpoint's FIFO
336 */
337static void musb_default_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
338{
339 struct musb *musb = hw_ep->musb;
340 void __iomem *fifo = hw_ep->fifo;
341
342 if (unlikely(len == 0))
343 return;
344
345 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
346 'R', hw_ep->epnum, fifo, len, dst);
347
348 /* we can't assume unaligned writes work */
349 if (likely((0x01 & (unsigned long) dst) == 0)) {
350 u16 index = 0;
351
352 /* best case is 32bit-aligned destination address */
353 if ((0x02 & (unsigned long) dst) == 0) {
354 if (len >= 4) {
355 ioread32_rep(fifo, dst, len >> 2);
356 index = len & ~0x03;
357 }
358 if (len & 0x02) {
359 *(u16 *)&dst[index] = __raw_readw(fifo);
360 index += 2;
361 }
362 } else {
363 if (len >= 2) {
364 ioread16_rep(fifo, dst, len >> 1);
365 index = len & ~0x01;
366 }
367 }
368 if (len & 0x01)
369 dst[index] = __raw_readb(fifo);
370 } else {
371 /* byte aligned */
372 ioread8_rep(fifo, dst, len);
373 }
374}
375
376/*
377 * Old style IO functions
378 */
379u8 (*musb_readb)(const void __iomem *addr, unsigned offset);
380EXPORT_SYMBOL_GPL(musb_readb);
381
382void (*musb_writeb)(void __iomem *addr, unsigned offset, u8 data);
383EXPORT_SYMBOL_GPL(musb_writeb);
384
385u16 (*musb_readw)(const void __iomem *addr, unsigned offset);
386EXPORT_SYMBOL_GPL(musb_readw);
387
388void (*musb_writew)(void __iomem *addr, unsigned offset, u16 data);
389EXPORT_SYMBOL_GPL(musb_writew);
390
391u32 (*musb_readl)(const void __iomem *addr, unsigned offset);
392EXPORT_SYMBOL_GPL(musb_readl);
393
394void (*musb_writel)(void __iomem *addr, unsigned offset, u32 data);
395EXPORT_SYMBOL_GPL(musb_writel);
396
397#ifndef CONFIG_MUSB_PIO_ONLY
398struct dma_controller *
399(*musb_dma_controller_create)(struct musb *musb, void __iomem *base);
400EXPORT_SYMBOL(musb_dma_controller_create);
401
402void (*musb_dma_controller_destroy)(struct dma_controller *c);
403EXPORT_SYMBOL(musb_dma_controller_destroy);
404#endif
405
406/*
407 * New style IO functions
408 */
409void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
410{
411 return hw_ep->musb->io.read_fifo(hw_ep, len, dst);
412}
413
414void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
415{
416 return hw_ep->musb->io.write_fifo(hw_ep, len, src);
417}
418
419/*-------------------------------------------------------------------------*/
420
421/* for high speed test mode; see USB 2.0 spec 7.1.20 */
422static const u8 musb_test_packet[53] = {
423 /* implicit SYNC then DATA0 to start */
424
425 /* JKJKJKJK x9 */
426 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
427 /* JJKKJJKK x8 */
428 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
429 /* JJJJKKKK x8 */
430 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
431 /* JJJJJJJKKKKKKK x8 */
432 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
433 /* JJJJJJJK x8 */
434 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
435 /* JKKKKKKK x10, JK */
436 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
437
438 /* implicit CRC16 then EOP to end */
439};
440
441void musb_load_testpacket(struct musb *musb)
442{
443 void __iomem *regs = musb->endpoints[0].regs;
444
445 musb_ep_select(musb->mregs, 0);
446 musb_write_fifo(musb->control_ep,
447 sizeof(musb_test_packet), musb_test_packet);
448 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
449}
450
451/*-------------------------------------------------------------------------*/
452
453/*
454 * Handles OTG hnp timeouts, such as b_ase0_brst
455 */
456static void musb_otg_timer_func(unsigned long data)
457{
458 struct musb *musb = (struct musb *)data;
459 unsigned long flags;
460
461 spin_lock_irqsave(&musb->lock, flags);
462 switch (musb->xceiv->otg->state) {
463 case OTG_STATE_B_WAIT_ACON:
464 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n");
465 musb_g_disconnect(musb);
466 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
467 musb->is_active = 0;
468 break;
469 case OTG_STATE_A_SUSPEND:
470 case OTG_STATE_A_WAIT_BCON:
471 dev_dbg(musb->controller, "HNP: %s timeout\n",
472 usb_otg_state_string(musb->xceiv->otg->state));
473 musb_platform_set_vbus(musb, 0);
474 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
475 break;
476 default:
477 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
478 usb_otg_state_string(musb->xceiv->otg->state));
479 }
480 spin_unlock_irqrestore(&musb->lock, flags);
481}
482
483/*
484 * Stops the HNP transition. Caller must take care of locking.
485 */
486void musb_hnp_stop(struct musb *musb)
487{
488 struct usb_hcd *hcd = musb->hcd;
489 void __iomem *mbase = musb->mregs;
490 u8 reg;
491
492 dev_dbg(musb->controller, "HNP: stop from %s\n",
493 usb_otg_state_string(musb->xceiv->otg->state));
494
495 switch (musb->xceiv->otg->state) {
496 case OTG_STATE_A_PERIPHERAL:
497 musb_g_disconnect(musb);
498 dev_dbg(musb->controller, "HNP: back to %s\n",
499 usb_otg_state_string(musb->xceiv->otg->state));
500 break;
501 case OTG_STATE_B_HOST:
502 dev_dbg(musb->controller, "HNP: Disabling HR\n");
503 if (hcd)
504 hcd->self.is_b_host = 0;
505 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
506 MUSB_DEV_MODE(musb);
507 reg = musb_readb(mbase, MUSB_POWER);
508 reg |= MUSB_POWER_SUSPENDM;
509 musb_writeb(mbase, MUSB_POWER, reg);
510 /* REVISIT: Start SESSION_REQUEST here? */
511 break;
512 default:
513 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n",
514 usb_otg_state_string(musb->xceiv->otg->state));
515 }
516
517 /*
518 * When returning to A state after HNP, avoid hub_port_rebounce(),
519 * which cause occasional OPT A "Did not receive reset after connect"
520 * errors.
521 */
522 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
523}
524
525static void musb_recover_from_babble(struct musb *musb);
526
527/*
528 * Interrupt Service Routine to record USB "global" interrupts.
529 * Since these do not happen often and signify things of
530 * paramount importance, it seems OK to check them individually;
531 * the order of the tests is specified in the manual
532 *
533 * @param musb instance pointer
534 * @param int_usb register contents
535 * @param devctl
536 * @param power
537 */
538
539static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
540 u8 devctl)
541{
542 irqreturn_t handled = IRQ_NONE;
543
544 dev_dbg(musb->controller, "<== DevCtl=%02x, int_usb=0x%x\n", devctl,
545 int_usb);
546
547 /* in host mode, the peripheral may issue remote wakeup.
548 * in peripheral mode, the host may resume the link.
549 * spurious RESUME irqs happen too, paired with SUSPEND.
550 */
551 if (int_usb & MUSB_INTR_RESUME) {
552 handled = IRQ_HANDLED;
553 dev_dbg(musb->controller, "RESUME (%s)\n",
554 usb_otg_state_string(musb->xceiv->otg->state));
555
556 if (devctl & MUSB_DEVCTL_HM) {
557 switch (musb->xceiv->otg->state) {
558 case OTG_STATE_A_SUSPEND:
559 /* remote wakeup? later, GetPortStatus
560 * will stop RESUME signaling
561 */
562
563 musb->port1_status |=
564 (USB_PORT_STAT_C_SUSPEND << 16)
565 | MUSB_PORT_STAT_RESUME;
566 musb->rh_timer = jiffies
567 + msecs_to_jiffies(USB_RESUME_TIMEOUT);
568 musb->need_finish_resume = 1;
569
570 musb->xceiv->otg->state = OTG_STATE_A_HOST;
571 musb->is_active = 1;
572 musb_host_resume_root_hub(musb);
573 break;
574 case OTG_STATE_B_WAIT_ACON:
575 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
576 musb->is_active = 1;
577 MUSB_DEV_MODE(musb);
578 break;
579 default:
580 WARNING("bogus %s RESUME (%s)\n",
581 "host",
582 usb_otg_state_string(musb->xceiv->otg->state));
583 }
584 } else {
585 switch (musb->xceiv->otg->state) {
586 case OTG_STATE_A_SUSPEND:
587 /* possibly DISCONNECT is upcoming */
588 musb->xceiv->otg->state = OTG_STATE_A_HOST;
589 musb_host_resume_root_hub(musb);
590 break;
591 case OTG_STATE_B_WAIT_ACON:
592 case OTG_STATE_B_PERIPHERAL:
593 /* disconnect while suspended? we may
594 * not get a disconnect irq...
595 */
596 if ((devctl & MUSB_DEVCTL_VBUS)
597 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
598 ) {
599 musb->int_usb |= MUSB_INTR_DISCONNECT;
600 musb->int_usb &= ~MUSB_INTR_SUSPEND;
601 break;
602 }
603 musb_g_resume(musb);
604 break;
605 case OTG_STATE_B_IDLE:
606 musb->int_usb &= ~MUSB_INTR_SUSPEND;
607 break;
608 default:
609 WARNING("bogus %s RESUME (%s)\n",
610 "peripheral",
611 usb_otg_state_string(musb->xceiv->otg->state));
612 }
613 }
614 }
615
616 /* see manual for the order of the tests */
617 if (int_usb & MUSB_INTR_SESSREQ) {
618 void __iomem *mbase = musb->mregs;
619
620 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
621 && (devctl & MUSB_DEVCTL_BDEVICE)) {
622 dev_dbg(musb->controller, "SessReq while on B state\n");
623 return IRQ_HANDLED;
624 }
625
626 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n",
627 usb_otg_state_string(musb->xceiv->otg->state));
628
629 /* IRQ arrives from ID pin sense or (later, if VBUS power
630 * is removed) SRP. responses are time critical:
631 * - turn on VBUS (with silicon-specific mechanism)
632 * - go through A_WAIT_VRISE
633 * - ... to A_WAIT_BCON.
634 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
635 */
636 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
637 musb->ep0_stage = MUSB_EP0_START;
638 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
639 MUSB_HST_MODE(musb);
640 musb_platform_set_vbus(musb, 1);
641
642 handled = IRQ_HANDLED;
643 }
644
645 if (int_usb & MUSB_INTR_VBUSERROR) {
646 int ignore = 0;
647
648 /* During connection as an A-Device, we may see a short
649 * current spikes causing voltage drop, because of cable
650 * and peripheral capacitance combined with vbus draw.
651 * (So: less common with truly self-powered devices, where
652 * vbus doesn't act like a power supply.)
653 *
654 * Such spikes are short; usually less than ~500 usec, max
655 * of ~2 msec. That is, they're not sustained overcurrent
656 * errors, though they're reported using VBUSERROR irqs.
657 *
658 * Workarounds: (a) hardware: use self powered devices.
659 * (b) software: ignore non-repeated VBUS errors.
660 *
661 * REVISIT: do delays from lots of DEBUG_KERNEL checks
662 * make trouble here, keeping VBUS < 4.4V ?
663 */
664 switch (musb->xceiv->otg->state) {
665 case OTG_STATE_A_HOST:
666 /* recovery is dicey once we've gotten past the
667 * initial stages of enumeration, but if VBUS
668 * stayed ok at the other end of the link, and
669 * another reset is due (at least for high speed,
670 * to redo the chirp etc), it might work OK...
671 */
672 case OTG_STATE_A_WAIT_BCON:
673 case OTG_STATE_A_WAIT_VRISE:
674 if (musb->vbuserr_retry) {
675 void __iomem *mbase = musb->mregs;
676
677 musb->vbuserr_retry--;
678 ignore = 1;
679 devctl |= MUSB_DEVCTL_SESSION;
680 musb_writeb(mbase, MUSB_DEVCTL, devctl);
681 } else {
682 musb->port1_status |=
683 USB_PORT_STAT_OVERCURRENT
684 | (USB_PORT_STAT_C_OVERCURRENT << 16);
685 }
686 break;
687 default:
688 break;
689 }
690
691 dev_printk(ignore ? KERN_DEBUG : KERN_ERR, musb->controller,
692 "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
693 usb_otg_state_string(musb->xceiv->otg->state),
694 devctl,
695 ({ char *s;
696 switch (devctl & MUSB_DEVCTL_VBUS) {
697 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
698 s = "<SessEnd"; break;
699 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
700 s = "<AValid"; break;
701 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
702 s = "<VBusValid"; break;
703 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
704 default:
705 s = "VALID"; break;
706 } s; }),
707 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
708 musb->port1_status);
709
710 /* go through A_WAIT_VFALL then start a new session */
711 if (!ignore)
712 musb_platform_set_vbus(musb, 0);
713 handled = IRQ_HANDLED;
714 }
715
716 if (int_usb & MUSB_INTR_SUSPEND) {
717 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x\n",
718 usb_otg_state_string(musb->xceiv->otg->state), devctl);
719 handled = IRQ_HANDLED;
720
721 switch (musb->xceiv->otg->state) {
722 case OTG_STATE_A_PERIPHERAL:
723 /* We also come here if the cable is removed, since
724 * this silicon doesn't report ID-no-longer-grounded.
725 *
726 * We depend on T(a_wait_bcon) to shut us down, and
727 * hope users don't do anything dicey during this
728 * undesired detour through A_WAIT_BCON.
729 */
730 musb_hnp_stop(musb);
731 musb_host_resume_root_hub(musb);
732 musb_root_disconnect(musb);
733 musb_platform_try_idle(musb, jiffies
734 + msecs_to_jiffies(musb->a_wait_bcon
735 ? : OTG_TIME_A_WAIT_BCON));
736
737 break;
738 case OTG_STATE_B_IDLE:
739 if (!musb->is_active)
740 break;
741 case OTG_STATE_B_PERIPHERAL:
742 musb_g_suspend(musb);
743 musb->is_active = musb->g.b_hnp_enable;
744 if (musb->is_active) {
745 musb->xceiv->otg->state = OTG_STATE_B_WAIT_ACON;
746 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
747 mod_timer(&musb->otg_timer, jiffies
748 + msecs_to_jiffies(
749 OTG_TIME_B_ASE0_BRST));
750 }
751 break;
752 case OTG_STATE_A_WAIT_BCON:
753 if (musb->a_wait_bcon != 0)
754 musb_platform_try_idle(musb, jiffies
755 + msecs_to_jiffies(musb->a_wait_bcon));
756 break;
757 case OTG_STATE_A_HOST:
758 musb->xceiv->otg->state = OTG_STATE_A_SUSPEND;
759 musb->is_active = musb->hcd->self.b_hnp_enable;
760 break;
761 case OTG_STATE_B_HOST:
762 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
763 dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n");
764 break;
765 default:
766 /* "should not happen" */
767 musb->is_active = 0;
768 break;
769 }
770 }
771
772 if (int_usb & MUSB_INTR_CONNECT) {
773 struct usb_hcd *hcd = musb->hcd;
774
775 handled = IRQ_HANDLED;
776 musb->is_active = 1;
777
778 musb->ep0_stage = MUSB_EP0_START;
779
780 musb->intrtxe = musb->epmask;
781 musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe);
782 musb->intrrxe = musb->epmask & 0xfffe;
783 musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe);
784 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
785 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
786 |USB_PORT_STAT_HIGH_SPEED
787 |USB_PORT_STAT_ENABLE
788 );
789 musb->port1_status |= USB_PORT_STAT_CONNECTION
790 |(USB_PORT_STAT_C_CONNECTION << 16);
791
792 /* high vs full speed is just a guess until after reset */
793 if (devctl & MUSB_DEVCTL_LSDEV)
794 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
795
796 /* indicate new connection to OTG machine */
797 switch (musb->xceiv->otg->state) {
798 case OTG_STATE_B_PERIPHERAL:
799 if (int_usb & MUSB_INTR_SUSPEND) {
800 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
801 int_usb &= ~MUSB_INTR_SUSPEND;
802 goto b_host;
803 } else
804 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
805 break;
806 case OTG_STATE_B_WAIT_ACON:
807 dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n");
808b_host:
809 musb->xceiv->otg->state = OTG_STATE_B_HOST;
810 if (musb->hcd)
811 musb->hcd->self.is_b_host = 1;
812 del_timer(&musb->otg_timer);
813 break;
814 default:
815 if ((devctl & MUSB_DEVCTL_VBUS)
816 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
817 musb->xceiv->otg->state = OTG_STATE_A_HOST;
818 if (hcd)
819 hcd->self.is_b_host = 0;
820 }
821 break;
822 }
823
824 musb_host_poke_root_hub(musb);
825
826 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",
827 usb_otg_state_string(musb->xceiv->otg->state), devctl);
828 }
829
830 if (int_usb & MUSB_INTR_DISCONNECT) {
831 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n",
832 usb_otg_state_string(musb->xceiv->otg->state),
833 MUSB_MODE(musb), devctl);
834 handled = IRQ_HANDLED;
835
836 switch (musb->xceiv->otg->state) {
837 case OTG_STATE_A_HOST:
838 case OTG_STATE_A_SUSPEND:
839 musb_host_resume_root_hub(musb);
840 musb_root_disconnect(musb);
841 if (musb->a_wait_bcon != 0)
842 musb_platform_try_idle(musb, jiffies
843 + msecs_to_jiffies(musb->a_wait_bcon));
844 break;
845 case OTG_STATE_B_HOST:
846 /* REVISIT this behaves for "real disconnect"
847 * cases; make sure the other transitions from
848 * from B_HOST act right too. The B_HOST code
849 * in hnp_stop() is currently not used...
850 */
851 musb_root_disconnect(musb);
852 if (musb->hcd)
853 musb->hcd->self.is_b_host = 0;
854 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
855 MUSB_DEV_MODE(musb);
856 musb_g_disconnect(musb);
857 break;
858 case OTG_STATE_A_PERIPHERAL:
859 musb_hnp_stop(musb);
860 musb_root_disconnect(musb);
861 /* FALLTHROUGH */
862 case OTG_STATE_B_WAIT_ACON:
863 /* FALLTHROUGH */
864 case OTG_STATE_B_PERIPHERAL:
865 case OTG_STATE_B_IDLE:
866 musb_g_disconnect(musb);
867 break;
868 default:
869 WARNING("unhandled DISCONNECT transition (%s)\n",
870 usb_otg_state_string(musb->xceiv->otg->state));
871 break;
872 }
873 }
874
875 /* mentor saves a bit: bus reset and babble share the same irq.
876 * only host sees babble; only peripheral sees bus reset.
877 */
878 if (int_usb & MUSB_INTR_RESET) {
879 handled = IRQ_HANDLED;
880 if (devctl & MUSB_DEVCTL_HM) {
881 /*
882 * When BABBLE happens what we can depends on which
883 * platform MUSB is running, because some platforms
884 * implemented proprietary means for 'recovering' from
885 * Babble conditions. One such platform is AM335x. In
886 * most cases, however, the only thing we can do is
887 * drop the session.
888 */
889 dev_err(musb->controller, "Babble\n");
890
891 if (is_host_active(musb))
892 musb_recover_from_babble(musb);
893 } else {
894 dev_dbg(musb->controller, "BUS RESET as %s\n",
895 usb_otg_state_string(musb->xceiv->otg->state));
896 switch (musb->xceiv->otg->state) {
897 case OTG_STATE_A_SUSPEND:
898 musb_g_reset(musb);
899 /* FALLTHROUGH */
900 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
901 /* never use invalid T(a_wait_bcon) */
902 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n",
903 usb_otg_state_string(musb->xceiv->otg->state),
904 TA_WAIT_BCON(musb));
905 mod_timer(&musb->otg_timer, jiffies
906 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
907 break;
908 case OTG_STATE_A_PERIPHERAL:
909 del_timer(&musb->otg_timer);
910 musb_g_reset(musb);
911 break;
912 case OTG_STATE_B_WAIT_ACON:
913 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",
914 usb_otg_state_string(musb->xceiv->otg->state));
915 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
916 musb_g_reset(musb);
917 break;
918 case OTG_STATE_B_IDLE:
919 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
920 /* FALLTHROUGH */
921 case OTG_STATE_B_PERIPHERAL:
922 musb_g_reset(musb);
923 break;
924 default:
925 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n",
926 usb_otg_state_string(musb->xceiv->otg->state));
927 }
928 }
929 }
930
931#if 0
932/* REVISIT ... this would be for multiplexing periodic endpoints, or
933 * supporting transfer phasing to prevent exceeding ISO bandwidth
934 * limits of a given frame or microframe.
935 *
936 * It's not needed for peripheral side, which dedicates endpoints;
937 * though it _might_ use SOF irqs for other purposes.
938 *
939 * And it's not currently needed for host side, which also dedicates
940 * endpoints, relies on TX/RX interval registers, and isn't claimed
941 * to support ISO transfers yet.
942 */
943 if (int_usb & MUSB_INTR_SOF) {
944 void __iomem *mbase = musb->mregs;
945 struct musb_hw_ep *ep;
946 u8 epnum;
947 u16 frame;
948
949 dev_dbg(musb->controller, "START_OF_FRAME\n");
950 handled = IRQ_HANDLED;
951
952 /* start any periodic Tx transfers waiting for current frame */
953 frame = musb_readw(mbase, MUSB_FRAME);
954 ep = musb->endpoints;
955 for (epnum = 1; (epnum < musb->nr_endpoints)
956 && (musb->epmask >= (1 << epnum));
957 epnum++, ep++) {
958 /*
959 * FIXME handle framecounter wraps (12 bits)
960 * eliminate duplicated StartUrb logic
961 */
962 if (ep->dwWaitFrame >= frame) {
963 ep->dwWaitFrame = 0;
964 pr_debug("SOF --> periodic TX%s on %d\n",
965 ep->tx_channel ? " DMA" : "",
966 epnum);
967 if (!ep->tx_channel)
968 musb_h_tx_start(musb, epnum);
969 else
970 cppi_hostdma_start(musb, epnum);
971 }
972 } /* end of for loop */
973 }
974#endif
975
976 schedule_work(&musb->irq_work);
977
978 return handled;
979}
980
981/*-------------------------------------------------------------------------*/
982
983static void musb_disable_interrupts(struct musb *musb)
984{
985 void __iomem *mbase = musb->mregs;
986 u16 temp;
987
988 /* disable interrupts */
989 musb_writeb(mbase, MUSB_INTRUSBE, 0);
990 musb->intrtxe = 0;
991 musb_writew(mbase, MUSB_INTRTXE, 0);
992 musb->intrrxe = 0;
993 musb_writew(mbase, MUSB_INTRRXE, 0);
994
995 /* flush pending interrupts */
996 temp = musb_readb(mbase, MUSB_INTRUSB);
997 temp = musb_readw(mbase, MUSB_INTRTX);
998 temp = musb_readw(mbase, MUSB_INTRRX);
999}
1000
1001static void musb_enable_interrupts(struct musb *musb)
1002{
1003 void __iomem *regs = musb->mregs;
1004
1005 /* Set INT enable registers, enable interrupts */
1006 musb->intrtxe = musb->epmask;
1007 musb_writew(regs, MUSB_INTRTXE, musb->intrtxe);
1008 musb->intrrxe = musb->epmask & 0xfffe;
1009 musb_writew(regs, MUSB_INTRRXE, musb->intrrxe);
1010 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
1011
1012}
1013
1014static void musb_generic_disable(struct musb *musb)
1015{
1016 void __iomem *mbase = musb->mregs;
1017
1018 musb_disable_interrupts(musb);
1019
1020 /* off */
1021 musb_writeb(mbase, MUSB_DEVCTL, 0);
1022}
1023
1024/*
1025 * Program the HDRC to start (enable interrupts, dma, etc.).
1026 */
1027void musb_start(struct musb *musb)
1028{
1029 void __iomem *regs = musb->mregs;
1030 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
1031 u8 power;
1032
1033 dev_dbg(musb->controller, "<== devctl %02x\n", devctl);
1034
1035 musb_enable_interrupts(musb);
1036 musb_writeb(regs, MUSB_TESTMODE, 0);
1037
1038 power = MUSB_POWER_ISOUPDATE;
1039 /*
1040 * treating UNKNOWN as unspecified maximum speed, in which case
1041 * we will default to high-speed.
1042 */
1043 if (musb->config->maximum_speed == USB_SPEED_HIGH ||
1044 musb->config->maximum_speed == USB_SPEED_UNKNOWN)
1045 power |= MUSB_POWER_HSENAB;
1046 musb_writeb(regs, MUSB_POWER, power);
1047
1048 musb->is_active = 0;
1049 devctl = musb_readb(regs, MUSB_DEVCTL);
1050 devctl &= ~MUSB_DEVCTL_SESSION;
1051
1052 /* session started after:
1053 * (a) ID-grounded irq, host mode;
1054 * (b) vbus present/connect IRQ, peripheral mode;
1055 * (c) peripheral initiates, using SRP
1056 */
1057 if (musb->port_mode != MUSB_PORT_MODE_HOST &&
1058 musb->xceiv->otg->state != OTG_STATE_A_WAIT_BCON &&
1059 (devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) {
1060 musb->is_active = 1;
1061 } else {
1062 devctl |= MUSB_DEVCTL_SESSION;
1063 }
1064
1065 musb_platform_enable(musb);
1066 musb_writeb(regs, MUSB_DEVCTL, devctl);
1067}
1068
1069/*
1070 * Make the HDRC stop (disable interrupts, etc.);
1071 * reversible by musb_start
1072 * called on gadget driver unregister
1073 * with controller locked, irqs blocked
1074 * acts as a NOP unless some role activated the hardware
1075 */
1076void musb_stop(struct musb *musb)
1077{
1078 /* stop IRQs, timers, ... */
1079 musb_platform_disable(musb);
1080 musb_generic_disable(musb);
1081 dev_dbg(musb->controller, "HDRC disabled\n");
1082
1083 /* FIXME
1084 * - mark host and/or peripheral drivers unusable/inactive
1085 * - disable DMA (and enable it in HdrcStart)
1086 * - make sure we can musb_start() after musb_stop(); with
1087 * OTG mode, gadget driver module rmmod/modprobe cycles that
1088 * - ...
1089 */
1090 musb_platform_try_idle(musb, 0);
1091}
1092
1093static void musb_shutdown(struct platform_device *pdev)
1094{
1095 struct musb *musb = dev_to_musb(&pdev->dev);
1096 unsigned long flags;
1097
1098 pm_runtime_get_sync(musb->controller);
1099
1100 musb_host_cleanup(musb);
1101 musb_gadget_cleanup(musb);
1102
1103 spin_lock_irqsave(&musb->lock, flags);
1104 musb_platform_disable(musb);
1105 musb_generic_disable(musb);
1106 spin_unlock_irqrestore(&musb->lock, flags);
1107
1108 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1109 musb_platform_exit(musb);
1110
1111 pm_runtime_put(musb->controller);
1112 /* FIXME power down */
1113}
1114
1115
1116/*-------------------------------------------------------------------------*/
1117
1118/*
1119 * The silicon either has hard-wired endpoint configurations, or else
1120 * "dynamic fifo" sizing. The driver has support for both, though at this
1121 * writing only the dynamic sizing is very well tested. Since we switched
1122 * away from compile-time hardware parameters, we can no longer rely on
1123 * dead code elimination to leave only the relevant one in the object file.
1124 *
1125 * We don't currently use dynamic fifo setup capability to do anything
1126 * more than selecting one of a bunch of predefined configurations.
1127 */
1128static ushort fifo_mode;
1129
1130/* "modprobe ... fifo_mode=1" etc */
1131module_param(fifo_mode, ushort, 0);
1132MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1133
1134/*
1135 * tables defining fifo_mode values. define more if you like.
1136 * for host side, make sure both halves of ep1 are set up.
1137 */
1138
1139/* mode 0 - fits in 2KB */
1140static struct musb_fifo_cfg mode_0_cfg[] = {
1141{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1142{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1143{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1144{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1145{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1146};
1147
1148/* mode 1 - fits in 4KB */
1149static struct musb_fifo_cfg mode_1_cfg[] = {
1150{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1151{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1152{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1153{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1154{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1155};
1156
1157/* mode 2 - fits in 4KB */
1158static struct musb_fifo_cfg mode_2_cfg[] = {
1159{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1160{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1161{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1162{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1163{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1164{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1165};
1166
1167/* mode 3 - fits in 4KB */
1168static struct musb_fifo_cfg mode_3_cfg[] = {
1169{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1170{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1171{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1172{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1173{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1174{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1175};
1176
1177/* mode 4 - fits in 16KB */
1178static struct musb_fifo_cfg mode_4_cfg[] = {
1179{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1180{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1181{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1182{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1183{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1184{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1185{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1186{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1187{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1188{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1189{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1190{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1191{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1192{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1193{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1194{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1195{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1196{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1197{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1198{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1199{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1200{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1201{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1202{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1203{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1204{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1205{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1206};
1207
1208/* mode 5 - fits in 8KB */
1209static struct musb_fifo_cfg mode_5_cfg[] = {
1210{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1211{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1212{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1213{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1214{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1215{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1216{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1217{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1218{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1219{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1220{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1221{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1222{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1223{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1224{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1225{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1226{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1227{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1228{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1229{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1230{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1231{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1232{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1233{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1234{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1235{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1236{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1237};
1238
1239/*
1240 * configure a fifo; for non-shared endpoints, this may be called
1241 * once for a tx fifo and once for an rx fifo.
1242 *
1243 * returns negative errno or offset for next fifo.
1244 */
1245static int
1246fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1247 const struct musb_fifo_cfg *cfg, u16 offset)
1248{
1249 void __iomem *mbase = musb->mregs;
1250 int size = 0;
1251 u16 maxpacket = cfg->maxpacket;
1252 u16 c_off = offset >> 3;
1253 u8 c_size;
1254
1255 /* expect hw_ep has already been zero-initialized */
1256
1257 size = ffs(max(maxpacket, (u16) 8)) - 1;
1258 maxpacket = 1 << size;
1259
1260 c_size = size - 3;
1261 if (cfg->mode == BUF_DOUBLE) {
1262 if ((offset + (maxpacket << 1)) >
1263 (1 << (musb->config->ram_bits + 2)))
1264 return -EMSGSIZE;
1265 c_size |= MUSB_FIFOSZ_DPB;
1266 } else {
1267 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1268 return -EMSGSIZE;
1269 }
1270
1271 /* configure the FIFO */
1272 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1273
1274 /* EP0 reserved endpoint for control, bidirectional;
1275 * EP1 reserved for bulk, two unidirectional halves.
1276 */
1277 if (hw_ep->epnum == 1)
1278 musb->bulk_ep = hw_ep;
1279 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1280 switch (cfg->style) {
1281 case FIFO_TX:
1282 musb_write_txfifosz(mbase, c_size);
1283 musb_write_txfifoadd(mbase, c_off);
1284 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1285 hw_ep->max_packet_sz_tx = maxpacket;
1286 break;
1287 case FIFO_RX:
1288 musb_write_rxfifosz(mbase, c_size);
1289 musb_write_rxfifoadd(mbase, c_off);
1290 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1291 hw_ep->max_packet_sz_rx = maxpacket;
1292 break;
1293 case FIFO_RXTX:
1294 musb_write_txfifosz(mbase, c_size);
1295 musb_write_txfifoadd(mbase, c_off);
1296 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1297 hw_ep->max_packet_sz_rx = maxpacket;
1298
1299 musb_write_rxfifosz(mbase, c_size);
1300 musb_write_rxfifoadd(mbase, c_off);
1301 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1302 hw_ep->max_packet_sz_tx = maxpacket;
1303
1304 hw_ep->is_shared_fifo = true;
1305 break;
1306 }
1307
1308 /* NOTE rx and tx endpoint irqs aren't managed separately,
1309 * which happens to be ok
1310 */
1311 musb->epmask |= (1 << hw_ep->epnum);
1312
1313 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1314}
1315
1316static struct musb_fifo_cfg ep0_cfg = {
1317 .style = FIFO_RXTX, .maxpacket = 64,
1318};
1319
1320static int ep_config_from_table(struct musb *musb)
1321{
1322 const struct musb_fifo_cfg *cfg;
1323 unsigned i, n;
1324 int offset;
1325 struct musb_hw_ep *hw_ep = musb->endpoints;
1326
1327 if (musb->config->fifo_cfg) {
1328 cfg = musb->config->fifo_cfg;
1329 n = musb->config->fifo_cfg_size;
1330 goto done;
1331 }
1332
1333 switch (fifo_mode) {
1334 default:
1335 fifo_mode = 0;
1336 /* FALLTHROUGH */
1337 case 0:
1338 cfg = mode_0_cfg;
1339 n = ARRAY_SIZE(mode_0_cfg);
1340 break;
1341 case 1:
1342 cfg = mode_1_cfg;
1343 n = ARRAY_SIZE(mode_1_cfg);
1344 break;
1345 case 2:
1346 cfg = mode_2_cfg;
1347 n = ARRAY_SIZE(mode_2_cfg);
1348 break;
1349 case 3:
1350 cfg = mode_3_cfg;
1351 n = ARRAY_SIZE(mode_3_cfg);
1352 break;
1353 case 4:
1354 cfg = mode_4_cfg;
1355 n = ARRAY_SIZE(mode_4_cfg);
1356 break;
1357 case 5:
1358 cfg = mode_5_cfg;
1359 n = ARRAY_SIZE(mode_5_cfg);
1360 break;
1361 }
1362
1363 pr_debug("%s: setup fifo_mode %d\n", musb_driver_name, fifo_mode);
1364
1365
1366done:
1367 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1368 /* assert(offset > 0) */
1369
1370 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1371 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1372 */
1373
1374 for (i = 0; i < n; i++) {
1375 u8 epn = cfg->hw_ep_num;
1376
1377 if (epn >= musb->config->num_eps) {
1378 pr_debug("%s: invalid ep %d\n",
1379 musb_driver_name, epn);
1380 return -EINVAL;
1381 }
1382 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1383 if (offset < 0) {
1384 pr_debug("%s: mem overrun, ep %d\n",
1385 musb_driver_name, epn);
1386 return offset;
1387 }
1388 epn++;
1389 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1390 }
1391
1392 pr_debug("%s: %d/%d max ep, %d/%d memory\n",
1393 musb_driver_name,
1394 n + 1, musb->config->num_eps * 2 - 1,
1395 offset, (1 << (musb->config->ram_bits + 2)));
1396
1397 if (!musb->bulk_ep) {
1398 pr_debug("%s: missing bulk\n", musb_driver_name);
1399 return -EINVAL;
1400 }
1401
1402 return 0;
1403}
1404
1405
1406/*
1407 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1408 * @param musb the controller
1409 */
1410static int ep_config_from_hw(struct musb *musb)
1411{
1412 u8 epnum = 0;
1413 struct musb_hw_ep *hw_ep;
1414 void __iomem *mbase = musb->mregs;
1415 int ret = 0;
1416
1417 dev_dbg(musb->controller, "<== static silicon ep config\n");
1418
1419 /* FIXME pick up ep0 maxpacket size */
1420
1421 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1422 musb_ep_select(mbase, epnum);
1423 hw_ep = musb->endpoints + epnum;
1424
1425 ret = musb_read_fifosize(musb, hw_ep, epnum);
1426 if (ret < 0)
1427 break;
1428
1429 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1430
1431 /* pick an RX/TX endpoint for bulk */
1432 if (hw_ep->max_packet_sz_tx < 512
1433 || hw_ep->max_packet_sz_rx < 512)
1434 continue;
1435
1436 /* REVISIT: this algorithm is lazy, we should at least
1437 * try to pick a double buffered endpoint.
1438 */
1439 if (musb->bulk_ep)
1440 continue;
1441 musb->bulk_ep = hw_ep;
1442 }
1443
1444 if (!musb->bulk_ep) {
1445 pr_debug("%s: missing bulk\n", musb_driver_name);
1446 return -EINVAL;
1447 }
1448
1449 return 0;
1450}
1451
1452enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1453
1454/* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1455 * configure endpoints, or take their config from silicon
1456 */
1457static int musb_core_init(u16 musb_type, struct musb *musb)
1458{
1459 u8 reg;
1460 char *type;
1461 char aInfo[90], aRevision[32], aDate[12];
1462 void __iomem *mbase = musb->mregs;
1463 int status = 0;
1464 int i;
1465
1466 /* log core options (read using indexed model) */
1467 reg = musb_read_configdata(mbase);
1468
1469 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1470 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1471 strcat(aInfo, ", dyn FIFOs");
1472 musb->dyn_fifo = true;
1473 }
1474 if (reg & MUSB_CONFIGDATA_MPRXE) {
1475 strcat(aInfo, ", bulk combine");
1476 musb->bulk_combine = true;
1477 }
1478 if (reg & MUSB_CONFIGDATA_MPTXE) {
1479 strcat(aInfo, ", bulk split");
1480 musb->bulk_split = true;
1481 }
1482 if (reg & MUSB_CONFIGDATA_HBRXE) {
1483 strcat(aInfo, ", HB-ISO Rx");
1484 musb->hb_iso_rx = true;
1485 }
1486 if (reg & MUSB_CONFIGDATA_HBTXE) {
1487 strcat(aInfo, ", HB-ISO Tx");
1488 musb->hb_iso_tx = true;
1489 }
1490 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1491 strcat(aInfo, ", SoftConn");
1492
1493 pr_debug("%s: ConfigData=0x%02x (%s)\n", musb_driver_name, reg, aInfo);
1494
1495 aDate[0] = 0;
1496 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1497 musb->is_multipoint = 1;
1498 type = "M";
1499 } else {
1500 musb->is_multipoint = 0;
1501 type = "";
1502#ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1503 pr_err("%s: kernel must blacklist external hubs\n",
1504 musb_driver_name);
1505#endif
1506 }
1507
1508 /* log release info */
1509 musb->hwvers = musb_read_hwvers(mbase);
1510 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1511 MUSB_HWVERS_MINOR(musb->hwvers),
1512 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1513 pr_debug("%s: %sHDRC RTL version %s %s\n",
1514 musb_driver_name, type, aRevision, aDate);
1515
1516 /* configure ep0 */
1517 musb_configure_ep0(musb);
1518
1519 /* discover endpoint configuration */
1520 musb->nr_endpoints = 1;
1521 musb->epmask = 1;
1522
1523 if (musb->dyn_fifo)
1524 status = ep_config_from_table(musb);
1525 else
1526 status = ep_config_from_hw(musb);
1527
1528 if (status < 0)
1529 return status;
1530
1531 /* finish init, and print endpoint config */
1532 for (i = 0; i < musb->nr_endpoints; i++) {
1533 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1534
1535 hw_ep->fifo = musb->io.fifo_offset(i) + mbase;
1536#if IS_ENABLED(CONFIG_USB_MUSB_TUSB6010)
1537 if (musb->io.quirks & MUSB_IN_TUSB) {
1538 hw_ep->fifo_async = musb->async + 0x400 +
1539 musb->io.fifo_offset(i);
1540 hw_ep->fifo_sync = musb->sync + 0x400 +
1541 musb->io.fifo_offset(i);
1542 hw_ep->fifo_sync_va =
1543 musb->sync_va + 0x400 + musb->io.fifo_offset(i);
1544
1545 if (i == 0)
1546 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1547 else
1548 hw_ep->conf = mbase + 0x400 +
1549 (((i - 1) & 0xf) << 2);
1550 }
1551#endif
1552
1553 hw_ep->regs = musb->io.ep_offset(i, 0) + mbase;
1554 hw_ep->rx_reinit = 1;
1555 hw_ep->tx_reinit = 1;
1556
1557 if (hw_ep->max_packet_sz_tx) {
1558 dev_dbg(musb->controller,
1559 "%s: hw_ep %d%s, %smax %d\n",
1560 musb_driver_name, i,
1561 hw_ep->is_shared_fifo ? "shared" : "tx",
1562 hw_ep->tx_double_buffered
1563 ? "doublebuffer, " : "",
1564 hw_ep->max_packet_sz_tx);
1565 }
1566 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1567 dev_dbg(musb->controller,
1568 "%s: hw_ep %d%s, %smax %d\n",
1569 musb_driver_name, i,
1570 "rx",
1571 hw_ep->rx_double_buffered
1572 ? "doublebuffer, " : "",
1573 hw_ep->max_packet_sz_rx);
1574 }
1575 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1576 dev_dbg(musb->controller, "hw_ep %d not configured\n", i);
1577 }
1578
1579 return 0;
1580}
1581
1582/*-------------------------------------------------------------------------*/
1583
1584/*
1585 * handle all the irqs defined by the HDRC core. for now we expect: other
1586 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1587 * will be assigned, and the irq will already have been acked.
1588 *
1589 * called in irq context with spinlock held, irqs blocked
1590 */
1591irqreturn_t musb_interrupt(struct musb *musb)
1592{
1593 irqreturn_t retval = IRQ_NONE;
1594 unsigned long status;
1595 unsigned long epnum;
1596 u8 devctl;
1597
1598 if (!musb->int_usb && !musb->int_tx && !musb->int_rx)
1599 return IRQ_NONE;
1600
1601 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1602
1603 dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n",
1604 is_host_active(musb) ? "host" : "peripheral",
1605 musb->int_usb, musb->int_tx, musb->int_rx);
1606
1607 /**
1608 * According to Mentor Graphics' documentation, flowchart on page 98,
1609 * IRQ should be handled as follows:
1610 *
1611 * . Resume IRQ
1612 * . Session Request IRQ
1613 * . VBUS Error IRQ
1614 * . Suspend IRQ
1615 * . Connect IRQ
1616 * . Disconnect IRQ
1617 * . Reset/Babble IRQ
1618 * . SOF IRQ (we're not using this one)
1619 * . Endpoint 0 IRQ
1620 * . TX Endpoints
1621 * . RX Endpoints
1622 *
1623 * We will be following that flowchart in order to avoid any problems
1624 * that might arise with internal Finite State Machine.
1625 */
1626
1627 if (musb->int_usb)
1628 retval |= musb_stage0_irq(musb, musb->int_usb, devctl);
1629
1630 if (musb->int_tx & 1) {
1631 if (is_host_active(musb))
1632 retval |= musb_h_ep0_irq(musb);
1633 else
1634 retval |= musb_g_ep0_irq(musb);
1635
1636 /* we have just handled endpoint 0 IRQ, clear it */
1637 musb->int_tx &= ~BIT(0);
1638 }
1639
1640 status = musb->int_tx;
1641
1642 for_each_set_bit(epnum, &status, 16) {
1643 retval = IRQ_HANDLED;
1644 if (is_host_active(musb))
1645 musb_host_tx(musb, epnum);
1646 else
1647 musb_g_tx(musb, epnum);
1648 }
1649
1650 status = musb->int_rx;
1651
1652 for_each_set_bit(epnum, &status, 16) {
1653 retval = IRQ_HANDLED;
1654 if (is_host_active(musb))
1655 musb_host_rx(musb, epnum);
1656 else
1657 musb_g_rx(musb, epnum);
1658 }
1659
1660 return retval;
1661}
1662EXPORT_SYMBOL_GPL(musb_interrupt);
1663
1664#ifndef CONFIG_MUSB_PIO_ONLY
1665static bool use_dma = 1;
1666
1667/* "modprobe ... use_dma=0" etc */
1668module_param(use_dma, bool, 0644);
1669MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1670
1671void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1672{
1673 /* called with controller lock already held */
1674
1675 if (!epnum) {
1676 if (!is_cppi_enabled(musb)) {
1677 /* endpoint 0 */
1678 if (is_host_active(musb))
1679 musb_h_ep0_irq(musb);
1680 else
1681 musb_g_ep0_irq(musb);
1682 }
1683 } else {
1684 /* endpoints 1..15 */
1685 if (transmit) {
1686 if (is_host_active(musb))
1687 musb_host_tx(musb, epnum);
1688 else
1689 musb_g_tx(musb, epnum);
1690 } else {
1691 /* receive */
1692 if (is_host_active(musb))
1693 musb_host_rx(musb, epnum);
1694 else
1695 musb_g_rx(musb, epnum);
1696 }
1697 }
1698}
1699EXPORT_SYMBOL_GPL(musb_dma_completion);
1700
1701#else
1702#define use_dma 0
1703#endif
1704
1705static void (*musb_phy_callback)(enum musb_vbus_id_status status);
1706
1707/*
1708 * musb_mailbox - optional phy notifier function
1709 * @status phy state change
1710 *
1711 * Optionally gets called from the USB PHY. Note that the USB PHY must be
1712 * disabled at the point the phy_callback is registered or unregistered.
1713 */
1714void musb_mailbox(enum musb_vbus_id_status status)
1715{
1716 if (musb_phy_callback)
1717 musb_phy_callback(status);
1718
1719};
1720EXPORT_SYMBOL_GPL(musb_mailbox);
1721
1722/*-------------------------------------------------------------------------*/
1723
1724static ssize_t
1725musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1726{
1727 struct musb *musb = dev_to_musb(dev);
1728 unsigned long flags;
1729 int ret = -EINVAL;
1730
1731 spin_lock_irqsave(&musb->lock, flags);
1732 ret = sprintf(buf, "%s\n", usb_otg_state_string(musb->xceiv->otg->state));
1733 spin_unlock_irqrestore(&musb->lock, flags);
1734
1735 return ret;
1736}
1737
1738static ssize_t
1739musb_mode_store(struct device *dev, struct device_attribute *attr,
1740 const char *buf, size_t n)
1741{
1742 struct musb *musb = dev_to_musb(dev);
1743 unsigned long flags;
1744 int status;
1745
1746 spin_lock_irqsave(&musb->lock, flags);
1747 if (sysfs_streq(buf, "host"))
1748 status = musb_platform_set_mode(musb, MUSB_HOST);
1749 else if (sysfs_streq(buf, "peripheral"))
1750 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1751 else if (sysfs_streq(buf, "otg"))
1752 status = musb_platform_set_mode(musb, MUSB_OTG);
1753 else
1754 status = -EINVAL;
1755 spin_unlock_irqrestore(&musb->lock, flags);
1756
1757 return (status == 0) ? n : status;
1758}
1759static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1760
1761static ssize_t
1762musb_vbus_store(struct device *dev, struct device_attribute *attr,
1763 const char *buf, size_t n)
1764{
1765 struct musb *musb = dev_to_musb(dev);
1766 unsigned long flags;
1767 unsigned long val;
1768
1769 if (sscanf(buf, "%lu", &val) < 1) {
1770 dev_err(dev, "Invalid VBUS timeout ms value\n");
1771 return -EINVAL;
1772 }
1773
1774 spin_lock_irqsave(&musb->lock, flags);
1775 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1776 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1777 if (musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)
1778 musb->is_active = 0;
1779 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1780 spin_unlock_irqrestore(&musb->lock, flags);
1781
1782 return n;
1783}
1784
1785static ssize_t
1786musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1787{
1788 struct musb *musb = dev_to_musb(dev);
1789 unsigned long flags;
1790 unsigned long val;
1791 int vbus;
1792 u8 devctl;
1793
1794 spin_lock_irqsave(&musb->lock, flags);
1795 val = musb->a_wait_bcon;
1796 vbus = musb_platform_get_vbus_status(musb);
1797 if (vbus < 0) {
1798 /* Use default MUSB method by means of DEVCTL register */
1799 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1800 if ((devctl & MUSB_DEVCTL_VBUS)
1801 == (3 << MUSB_DEVCTL_VBUS_SHIFT))
1802 vbus = 1;
1803 else
1804 vbus = 0;
1805 }
1806 spin_unlock_irqrestore(&musb->lock, flags);
1807
1808 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1809 vbus ? "on" : "off", val);
1810}
1811static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1812
1813/* Gadget drivers can't know that a host is connected so they might want
1814 * to start SRP, but users can. This allows userspace to trigger SRP.
1815 */
1816static ssize_t
1817musb_srp_store(struct device *dev, struct device_attribute *attr,
1818 const char *buf, size_t n)
1819{
1820 struct musb *musb = dev_to_musb(dev);
1821 unsigned short srp;
1822
1823 if (sscanf(buf, "%hu", &srp) != 1
1824 || (srp != 1)) {
1825 dev_err(dev, "SRP: Value must be 1\n");
1826 return -EINVAL;
1827 }
1828
1829 if (srp == 1)
1830 musb_g_wakeup(musb);
1831
1832 return n;
1833}
1834static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1835
1836static struct attribute *musb_attributes[] = {
1837 &dev_attr_mode.attr,
1838 &dev_attr_vbus.attr,
1839 &dev_attr_srp.attr,
1840 NULL
1841};
1842
1843static const struct attribute_group musb_attr_group = {
1844 .attrs = musb_attributes,
1845};
1846
1847/* Only used to provide driver mode change events */
1848static void musb_irq_work(struct work_struct *data)
1849{
1850 struct musb *musb = container_of(data, struct musb, irq_work);
1851
1852 if (musb->xceiv->otg->state != musb->xceiv_old_state) {
1853 musb->xceiv_old_state = musb->xceiv->otg->state;
1854 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1855 }
1856}
1857
1858static void musb_recover_from_babble(struct musb *musb)
1859{
1860 int ret;
1861 u8 devctl;
1862
1863 musb_disable_interrupts(musb);
1864
1865 /*
1866 * wait at least 320 cycles of 60MHz clock. That's 5.3us, we will give
1867 * it some slack and wait for 10us.
1868 */
1869 udelay(10);
1870
1871 ret = musb_platform_recover(musb);
1872 if (ret) {
1873 musb_enable_interrupts(musb);
1874 return;
1875 }
1876
1877 /* drop session bit */
1878 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1879 devctl &= ~MUSB_DEVCTL_SESSION;
1880 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
1881
1882 /* tell usbcore about it */
1883 musb_root_disconnect(musb);
1884
1885 /*
1886 * When a babble condition occurs, the musb controller
1887 * removes the session bit and the endpoint config is lost.
1888 */
1889 if (musb->dyn_fifo)
1890 ret = ep_config_from_table(musb);
1891 else
1892 ret = ep_config_from_hw(musb);
1893
1894 /* restart session */
1895 if (ret == 0)
1896 musb_start(musb);
1897}
1898
1899/* --------------------------------------------------------------------------
1900 * Init support
1901 */
1902
1903static struct musb *allocate_instance(struct device *dev,
1904 const struct musb_hdrc_config *config, void __iomem *mbase)
1905{
1906 struct musb *musb;
1907 struct musb_hw_ep *ep;
1908 int epnum;
1909 int ret;
1910
1911 musb = devm_kzalloc(dev, sizeof(*musb), GFP_KERNEL);
1912 if (!musb)
1913 return NULL;
1914
1915 INIT_LIST_HEAD(&musb->control);
1916 INIT_LIST_HEAD(&musb->in_bulk);
1917 INIT_LIST_HEAD(&musb->out_bulk);
1918
1919 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1920 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
1921 musb->mregs = mbase;
1922 musb->ctrl_base = mbase;
1923 musb->nIrq = -ENODEV;
1924 musb->config = config;
1925 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
1926 for (epnum = 0, ep = musb->endpoints;
1927 epnum < musb->config->num_eps;
1928 epnum++, ep++) {
1929 ep->musb = musb;
1930 ep->epnum = epnum;
1931 }
1932
1933 musb->controller = dev;
1934
1935 ret = musb_host_alloc(musb);
1936 if (ret < 0)
1937 goto err_free;
1938
1939 dev_set_drvdata(dev, musb);
1940
1941 return musb;
1942
1943err_free:
1944 return NULL;
1945}
1946
1947static void musb_free(struct musb *musb)
1948{
1949 /* this has multiple entry modes. it handles fault cleanup after
1950 * probe(), where things may be partially set up, as well as rmmod
1951 * cleanup after everything's been de-activated.
1952 */
1953
1954#ifdef CONFIG_SYSFS
1955 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
1956#endif
1957
1958 if (musb->nIrq >= 0) {
1959 if (musb->irq_wake)
1960 disable_irq_wake(musb->nIrq);
1961 free_irq(musb->nIrq, musb);
1962 }
1963
1964 musb_host_free(musb);
1965}
1966
1967static void musb_deassert_reset(struct work_struct *work)
1968{
1969 struct musb *musb;
1970 unsigned long flags;
1971
1972 musb = container_of(work, struct musb, deassert_reset_work.work);
1973
1974 spin_lock_irqsave(&musb->lock, flags);
1975
1976 if (musb->port1_status & USB_PORT_STAT_RESET)
1977 musb_port_reset(musb, false);
1978
1979 spin_unlock_irqrestore(&musb->lock, flags);
1980}
1981
1982/*
1983 * Perform generic per-controller initialization.
1984 *
1985 * @dev: the controller (already clocked, etc)
1986 * @nIrq: IRQ number
1987 * @ctrl: virtual address of controller registers,
1988 * not yet corrected for platform-specific offsets
1989 */
1990static int
1991musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1992{
1993 int status;
1994 struct musb *musb;
1995 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
1996
1997 /* The driver might handle more features than the board; OK.
1998 * Fail when the board needs a feature that's not enabled.
1999 */
2000 if (!plat) {
2001 dev_dbg(dev, "no platform_data?\n");
2002 status = -ENODEV;
2003 goto fail0;
2004 }
2005
2006 /* allocate */
2007 musb = allocate_instance(dev, plat->config, ctrl);
2008 if (!musb) {
2009 status = -ENOMEM;
2010 goto fail0;
2011 }
2012
2013 spin_lock_init(&musb->lock);
2014 musb->board_set_power = plat->set_power;
2015 musb->min_power = plat->min_power;
2016 musb->ops = plat->platform_ops;
2017 musb->port_mode = plat->mode;
2018
2019 /*
2020 * Initialize the default IO functions. At least omap2430 needs
2021 * these early. We initialize the platform specific IO functions
2022 * later on.
2023 */
2024 musb_readb = musb_default_readb;
2025 musb_writeb = musb_default_writeb;
2026 musb_readw = musb_default_readw;
2027 musb_writew = musb_default_writew;
2028 musb_readl = musb_default_readl;
2029 musb_writel = musb_default_writel;
2030
2031 /* We need musb_read/write functions initialized for PM */
2032 pm_runtime_use_autosuspend(musb->controller);
2033 pm_runtime_set_autosuspend_delay(musb->controller, 200);
2034 pm_runtime_enable(musb->controller);
2035
2036 /* The musb_platform_init() call:
2037 * - adjusts musb->mregs
2038 * - sets the musb->isr
2039 * - may initialize an integrated transceiver
2040 * - initializes musb->xceiv, usually by otg_get_phy()
2041 * - stops powering VBUS
2042 *
2043 * There are various transceiver configurations. Blackfin,
2044 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
2045 * external/discrete ones in various flavors (twl4030 family,
2046 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
2047 */
2048 status = musb_platform_init(musb);
2049 if (status < 0)
2050 goto fail1;
2051
2052 if (!musb->isr) {
2053 status = -ENODEV;
2054 goto fail2;
2055 }
2056
2057 if (musb->ops->quirks)
2058 musb->io.quirks = musb->ops->quirks;
2059
2060 /* Most devices use indexed offset or flat offset */
2061 if (musb->io.quirks & MUSB_INDEXED_EP) {
2062 musb->io.ep_offset = musb_indexed_ep_offset;
2063 musb->io.ep_select = musb_indexed_ep_select;
2064 } else {
2065 musb->io.ep_offset = musb_flat_ep_offset;
2066 musb->io.ep_select = musb_flat_ep_select;
2067 }
2068 /* And override them with platform specific ops if specified. */
2069 if (musb->ops->ep_offset)
2070 musb->io.ep_offset = musb->ops->ep_offset;
2071 if (musb->ops->ep_select)
2072 musb->io.ep_select = musb->ops->ep_select;
2073
2074 /* At least tusb6010 has its own offsets */
2075 if (musb->ops->ep_offset)
2076 musb->io.ep_offset = musb->ops->ep_offset;
2077 if (musb->ops->ep_select)
2078 musb->io.ep_select = musb->ops->ep_select;
2079
2080 if (musb->ops->fifo_mode)
2081 fifo_mode = musb->ops->fifo_mode;
2082 else
2083 fifo_mode = 4;
2084
2085 if (musb->ops->fifo_offset)
2086 musb->io.fifo_offset = musb->ops->fifo_offset;
2087 else
2088 musb->io.fifo_offset = musb_default_fifo_offset;
2089
2090 if (musb->ops->busctl_offset)
2091 musb->io.busctl_offset = musb->ops->busctl_offset;
2092 else
2093 musb->io.busctl_offset = musb_default_busctl_offset;
2094
2095 if (musb->ops->readb)
2096 musb_readb = musb->ops->readb;
2097 if (musb->ops->writeb)
2098 musb_writeb = musb->ops->writeb;
2099 if (musb->ops->readw)
2100 musb_readw = musb->ops->readw;
2101 if (musb->ops->writew)
2102 musb_writew = musb->ops->writew;
2103 if (musb->ops->readl)
2104 musb_readl = musb->ops->readl;
2105 if (musb->ops->writel)
2106 musb_writel = musb->ops->writel;
2107
2108#ifndef CONFIG_MUSB_PIO_ONLY
2109 if (!musb->ops->dma_init || !musb->ops->dma_exit) {
2110 dev_err(dev, "DMA controller not set\n");
2111 status = -ENODEV;
2112 goto fail2;
2113 }
2114 musb_dma_controller_create = musb->ops->dma_init;
2115 musb_dma_controller_destroy = musb->ops->dma_exit;
2116#endif
2117
2118 if (musb->ops->read_fifo)
2119 musb->io.read_fifo = musb->ops->read_fifo;
2120 else
2121 musb->io.read_fifo = musb_default_read_fifo;
2122
2123 if (musb->ops->write_fifo)
2124 musb->io.write_fifo = musb->ops->write_fifo;
2125 else
2126 musb->io.write_fifo = musb_default_write_fifo;
2127
2128 if (!musb->xceiv->io_ops) {
2129 musb->xceiv->io_dev = musb->controller;
2130 musb->xceiv->io_priv = musb->mregs;
2131 musb->xceiv->io_ops = &musb_ulpi_access;
2132 }
2133
2134 if (musb->ops->phy_callback)
2135 musb_phy_callback = musb->ops->phy_callback;
2136
2137 pm_runtime_get_sync(musb->controller);
2138
2139 status = usb_phy_init(musb->xceiv);
2140 if (status < 0)
2141 goto err_usb_phy_init;
2142
2143 if (use_dma && dev->dma_mask) {
2144 musb->dma_controller =
2145 musb_dma_controller_create(musb, musb->mregs);
2146 if (IS_ERR(musb->dma_controller)) {
2147 status = PTR_ERR(musb->dma_controller);
2148 goto fail2_5;
2149 }
2150 }
2151
2152 /* be sure interrupts are disabled before connecting ISR */
2153 musb_platform_disable(musb);
2154 musb_generic_disable(musb);
2155
2156 /* Init IRQ workqueue before request_irq */
2157 INIT_WORK(&musb->irq_work, musb_irq_work);
2158 INIT_DELAYED_WORK(&musb->deassert_reset_work, musb_deassert_reset);
2159 INIT_DELAYED_WORK(&musb->finish_resume_work, musb_host_finish_resume);
2160
2161 /* setup musb parts of the core (especially endpoints) */
2162 status = musb_core_init(plat->config->multipoint
2163 ? MUSB_CONTROLLER_MHDRC
2164 : MUSB_CONTROLLER_HDRC, musb);
2165 if (status < 0)
2166 goto fail3;
2167
2168 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
2169
2170 /* attach to the IRQ */
2171 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
2172 dev_err(dev, "request_irq %d failed!\n", nIrq);
2173 status = -ENODEV;
2174 goto fail3;
2175 }
2176 musb->nIrq = nIrq;
2177 /* FIXME this handles wakeup irqs wrong */
2178 if (enable_irq_wake(nIrq) == 0) {
2179 musb->irq_wake = 1;
2180 device_init_wakeup(dev, 1);
2181 } else {
2182 musb->irq_wake = 0;
2183 }
2184
2185 /* program PHY to use external vBus if required */
2186 if (plat->extvbus) {
2187 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
2188 busctl |= MUSB_ULPI_USE_EXTVBUS;
2189 musb_write_ulpi_buscontrol(musb->mregs, busctl);
2190 }
2191
2192 if (musb->xceiv->otg->default_a) {
2193 MUSB_HST_MODE(musb);
2194 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
2195 } else {
2196 MUSB_DEV_MODE(musb);
2197 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
2198 }
2199
2200 switch (musb->port_mode) {
2201 case MUSB_PORT_MODE_HOST:
2202 status = musb_host_setup(musb, plat->power);
2203 if (status < 0)
2204 goto fail3;
2205 status = musb_platform_set_mode(musb, MUSB_HOST);
2206 break;
2207 case MUSB_PORT_MODE_GADGET:
2208 status = musb_gadget_setup(musb);
2209 if (status < 0)
2210 goto fail3;
2211 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
2212 break;
2213 case MUSB_PORT_MODE_DUAL_ROLE:
2214 status = musb_host_setup(musb, plat->power);
2215 if (status < 0)
2216 goto fail3;
2217 status = musb_gadget_setup(musb);
2218 if (status) {
2219 musb_host_cleanup(musb);
2220 goto fail3;
2221 }
2222 status = musb_platform_set_mode(musb, MUSB_OTG);
2223 break;
2224 default:
2225 dev_err(dev, "unsupported port mode %d\n", musb->port_mode);
2226 break;
2227 }
2228
2229 if (status < 0)
2230 goto fail3;
2231
2232 status = musb_init_debugfs(musb);
2233 if (status < 0)
2234 goto fail4;
2235
2236 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
2237 if (status)
2238 goto fail5;
2239
2240 pm_runtime_put(musb->controller);
2241
2242 /*
2243 * For why this is currently needed, see commit 3e43a0725637
2244 * ("usb: musb: core: add pm_runtime_irq_safe()")
2245 */
2246 pm_runtime_irq_safe(musb->controller);
2247
2248 return 0;
2249
2250fail5:
2251 musb_exit_debugfs(musb);
2252
2253fail4:
2254 musb_gadget_cleanup(musb);
2255 musb_host_cleanup(musb);
2256
2257fail3:
2258 cancel_work_sync(&musb->irq_work);
2259 cancel_delayed_work_sync(&musb->finish_resume_work);
2260 cancel_delayed_work_sync(&musb->deassert_reset_work);
2261 if (musb->dma_controller)
2262 musb_dma_controller_destroy(musb->dma_controller);
2263
2264fail2_5:
2265 usb_phy_shutdown(musb->xceiv);
2266
2267err_usb_phy_init:
2268 pm_runtime_put_sync(musb->controller);
2269
2270fail2:
2271 if (musb->irq_wake)
2272 device_init_wakeup(dev, 0);
2273 musb_platform_exit(musb);
2274
2275fail1:
2276 pm_runtime_disable(musb->controller);
2277 dev_err(musb->controller,
2278 "musb_init_controller failed with status %d\n", status);
2279
2280 musb_free(musb);
2281
2282fail0:
2283
2284 return status;
2285
2286}
2287
2288/*-------------------------------------------------------------------------*/
2289
2290/* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2291 * bridge to a platform device; this driver then suffices.
2292 */
2293static int musb_probe(struct platform_device *pdev)
2294{
2295 struct device *dev = &pdev->dev;
2296 int irq = platform_get_irq_byname(pdev, "mc");
2297 struct resource *iomem;
2298 void __iomem *base;
2299
2300 if (irq <= 0)
2301 return -ENODEV;
2302
2303 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2304 base = devm_ioremap_resource(dev, iomem);
2305 if (IS_ERR(base))
2306 return PTR_ERR(base);
2307
2308 return musb_init_controller(dev, irq, base);
2309}
2310
2311static int musb_remove(struct platform_device *pdev)
2312{
2313 struct device *dev = &pdev->dev;
2314 struct musb *musb = dev_to_musb(dev);
2315
2316 /* this gets called on rmmod.
2317 * - Host mode: host may still be active
2318 * - Peripheral mode: peripheral is deactivated (or never-activated)
2319 * - OTG mode: both roles are deactivated (or never-activated)
2320 */
2321 musb_exit_debugfs(musb);
2322 musb_shutdown(pdev);
2323 musb_phy_callback = NULL;
2324
2325 if (musb->dma_controller)
2326 musb_dma_controller_destroy(musb->dma_controller);
2327
2328 usb_phy_shutdown(musb->xceiv);
2329
2330 cancel_work_sync(&musb->irq_work);
2331 cancel_delayed_work_sync(&musb->finish_resume_work);
2332 cancel_delayed_work_sync(&musb->deassert_reset_work);
2333 musb_free(musb);
2334 device_init_wakeup(dev, 0);
2335 return 0;
2336}
2337
2338#ifdef CONFIG_PM
2339
2340static void musb_save_context(struct musb *musb)
2341{
2342 int i;
2343 void __iomem *musb_base = musb->mregs;
2344 void __iomem *epio;
2345
2346 musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2347 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2348 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
2349 musb->context.power = musb_readb(musb_base, MUSB_POWER);
2350 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2351 musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2352 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2353
2354 for (i = 0; i < musb->config->num_eps; ++i) {
2355 struct musb_hw_ep *hw_ep;
2356
2357 hw_ep = &musb->endpoints[i];
2358 if (!hw_ep)
2359 continue;
2360
2361 epio = hw_ep->regs;
2362 if (!epio)
2363 continue;
2364
2365 musb_writeb(musb_base, MUSB_INDEX, i);
2366 musb->context.index_regs[i].txmaxp =
2367 musb_readw(epio, MUSB_TXMAXP);
2368 musb->context.index_regs[i].txcsr =
2369 musb_readw(epio, MUSB_TXCSR);
2370 musb->context.index_regs[i].rxmaxp =
2371 musb_readw(epio, MUSB_RXMAXP);
2372 musb->context.index_regs[i].rxcsr =
2373 musb_readw(epio, MUSB_RXCSR);
2374
2375 if (musb->dyn_fifo) {
2376 musb->context.index_regs[i].txfifoadd =
2377 musb_read_txfifoadd(musb_base);
2378 musb->context.index_regs[i].rxfifoadd =
2379 musb_read_rxfifoadd(musb_base);
2380 musb->context.index_regs[i].txfifosz =
2381 musb_read_txfifosz(musb_base);
2382 musb->context.index_regs[i].rxfifosz =
2383 musb_read_rxfifosz(musb_base);
2384 }
2385
2386 musb->context.index_regs[i].txtype =
2387 musb_readb(epio, MUSB_TXTYPE);
2388 musb->context.index_regs[i].txinterval =
2389 musb_readb(epio, MUSB_TXINTERVAL);
2390 musb->context.index_regs[i].rxtype =
2391 musb_readb(epio, MUSB_RXTYPE);
2392 musb->context.index_regs[i].rxinterval =
2393 musb_readb(epio, MUSB_RXINTERVAL);
2394
2395 musb->context.index_regs[i].txfunaddr =
2396 musb_read_txfunaddr(musb, i);
2397 musb->context.index_regs[i].txhubaddr =
2398 musb_read_txhubaddr(musb, i);
2399 musb->context.index_regs[i].txhubport =
2400 musb_read_txhubport(musb, i);
2401
2402 musb->context.index_regs[i].rxfunaddr =
2403 musb_read_rxfunaddr(musb, i);
2404 musb->context.index_regs[i].rxhubaddr =
2405 musb_read_rxhubaddr(musb, i);
2406 musb->context.index_regs[i].rxhubport =
2407 musb_read_rxhubport(musb, i);
2408 }
2409}
2410
2411static void musb_restore_context(struct musb *musb)
2412{
2413 int i;
2414 void __iomem *musb_base = musb->mregs;
2415 void __iomem *epio;
2416 u8 power;
2417
2418 musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2419 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2420 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
2421
2422 /* Don't affect SUSPENDM/RESUME bits in POWER reg */
2423 power = musb_readb(musb_base, MUSB_POWER);
2424 power &= MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME;
2425 musb->context.power &= ~(MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME);
2426 power |= musb->context.power;
2427 musb_writeb(musb_base, MUSB_POWER, power);
2428
2429 musb_writew(musb_base, MUSB_INTRTXE, musb->intrtxe);
2430 musb_writew(musb_base, MUSB_INTRRXE, musb->intrrxe);
2431 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2432 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
2433
2434 for (i = 0; i < musb->config->num_eps; ++i) {
2435 struct musb_hw_ep *hw_ep;
2436
2437 hw_ep = &musb->endpoints[i];
2438 if (!hw_ep)
2439 continue;
2440
2441 epio = hw_ep->regs;
2442 if (!epio)
2443 continue;
2444
2445 musb_writeb(musb_base, MUSB_INDEX, i);
2446 musb_writew(epio, MUSB_TXMAXP,
2447 musb->context.index_regs[i].txmaxp);
2448 musb_writew(epio, MUSB_TXCSR,
2449 musb->context.index_regs[i].txcsr);
2450 musb_writew(epio, MUSB_RXMAXP,
2451 musb->context.index_regs[i].rxmaxp);
2452 musb_writew(epio, MUSB_RXCSR,
2453 musb->context.index_regs[i].rxcsr);
2454
2455 if (musb->dyn_fifo) {
2456 musb_write_txfifosz(musb_base,
2457 musb->context.index_regs[i].txfifosz);
2458 musb_write_rxfifosz(musb_base,
2459 musb->context.index_regs[i].rxfifosz);
2460 musb_write_txfifoadd(musb_base,
2461 musb->context.index_regs[i].txfifoadd);
2462 musb_write_rxfifoadd(musb_base,
2463 musb->context.index_regs[i].rxfifoadd);
2464 }
2465
2466 musb_writeb(epio, MUSB_TXTYPE,
2467 musb->context.index_regs[i].txtype);
2468 musb_writeb(epio, MUSB_TXINTERVAL,
2469 musb->context.index_regs[i].txinterval);
2470 musb_writeb(epio, MUSB_RXTYPE,
2471 musb->context.index_regs[i].rxtype);
2472 musb_writeb(epio, MUSB_RXINTERVAL,
2473
2474 musb->context.index_regs[i].rxinterval);
2475 musb_write_txfunaddr(musb, i,
2476 musb->context.index_regs[i].txfunaddr);
2477 musb_write_txhubaddr(musb, i,
2478 musb->context.index_regs[i].txhubaddr);
2479 musb_write_txhubport(musb, i,
2480 musb->context.index_regs[i].txhubport);
2481
2482 musb_write_rxfunaddr(musb, i,
2483 musb->context.index_regs[i].rxfunaddr);
2484 musb_write_rxhubaddr(musb, i,
2485 musb->context.index_regs[i].rxhubaddr);
2486 musb_write_rxhubport(musb, i,
2487 musb->context.index_regs[i].rxhubport);
2488 }
2489 musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
2490}
2491
2492static int musb_suspend(struct device *dev)
2493{
2494 struct musb *musb = dev_to_musb(dev);
2495 unsigned long flags;
2496
2497 musb_platform_disable(musb);
2498 musb_generic_disable(musb);
2499
2500 spin_lock_irqsave(&musb->lock, flags);
2501
2502 if (is_peripheral_active(musb)) {
2503 /* FIXME force disconnect unless we know USB will wake
2504 * the system up quickly enough to respond ...
2505 */
2506 } else if (is_host_active(musb)) {
2507 /* we know all the children are suspended; sometimes
2508 * they will even be wakeup-enabled.
2509 */
2510 }
2511
2512 musb_save_context(musb);
2513
2514 spin_unlock_irqrestore(&musb->lock, flags);
2515 return 0;
2516}
2517
2518static int musb_resume(struct device *dev)
2519{
2520 struct musb *musb = dev_to_musb(dev);
2521 u8 devctl;
2522 u8 mask;
2523
2524 /*
2525 * For static cmos like DaVinci, register values were preserved
2526 * unless for some reason the whole soc powered down or the USB
2527 * module got reset through the PSC (vs just being disabled).
2528 *
2529 * For the DSPS glue layer though, a full register restore has to
2530 * be done. As it shouldn't harm other platforms, we do it
2531 * unconditionally.
2532 */
2533
2534 musb_restore_context(musb);
2535
2536 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2537 mask = MUSB_DEVCTL_BDEVICE | MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV;
2538 if ((devctl & mask) != (musb->context.devctl & mask))
2539 musb->port1_status = 0;
2540 if (musb->need_finish_resume) {
2541 musb->need_finish_resume = 0;
2542 schedule_delayed_work(&musb->finish_resume_work,
2543 msecs_to_jiffies(USB_RESUME_TIMEOUT));
2544 }
2545
2546 /*
2547 * The USB HUB code expects the device to be in RPM_ACTIVE once it came
2548 * out of suspend
2549 */
2550 pm_runtime_disable(dev);
2551 pm_runtime_set_active(dev);
2552 pm_runtime_enable(dev);
2553
2554 musb_start(musb);
2555
2556 return 0;
2557}
2558
2559static int musb_runtime_suspend(struct device *dev)
2560{
2561 struct musb *musb = dev_to_musb(dev);
2562
2563 musb_save_context(musb);
2564
2565 return 0;
2566}
2567
2568static int musb_runtime_resume(struct device *dev)
2569{
2570 struct musb *musb = dev_to_musb(dev);
2571 static int first = 1;
2572
2573 /*
2574 * When pm_runtime_get_sync called for the first time in driver
2575 * init, some of the structure is still not initialized which is
2576 * used in restore function. But clock needs to be
2577 * enabled before any register access, so
2578 * pm_runtime_get_sync has to be called.
2579 * Also context restore without save does not make
2580 * any sense
2581 */
2582 if (!first)
2583 musb_restore_context(musb);
2584 first = 0;
2585
2586 if (musb->need_finish_resume) {
2587 musb->need_finish_resume = 0;
2588 schedule_delayed_work(&musb->finish_resume_work,
2589 msecs_to_jiffies(USB_RESUME_TIMEOUT));
2590 }
2591
2592 return 0;
2593}
2594
2595static const struct dev_pm_ops musb_dev_pm_ops = {
2596 .suspend = musb_suspend,
2597 .resume = musb_resume,
2598 .runtime_suspend = musb_runtime_suspend,
2599 .runtime_resume = musb_runtime_resume,
2600};
2601
2602#define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2603#else
2604#define MUSB_DEV_PM_OPS NULL
2605#endif
2606
2607static struct platform_driver musb_driver = {
2608 .driver = {
2609 .name = (char *)musb_driver_name,
2610 .bus = &platform_bus_type,
2611 .pm = MUSB_DEV_PM_OPS,
2612 },
2613 .probe = musb_probe,
2614 .remove = musb_remove,
2615 .shutdown = musb_shutdown,
2616};
2617
2618module_platform_driver(musb_driver);
1/*
2 * MUSB OTG driver core code
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35/*
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
37 *
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
42 *
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
47 *
48 *
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
53 *
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
56 *
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
61 *
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
66 * each direction.
67 *
68 * RESULT: one device may be perceived as blocking another one.
69 *
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
74 *
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
80 */
81
82/*
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific informarion
87 * (plus recentrly, SOC or family details)
88 *
89 * Most of the conditional compilation will (someday) vanish.
90 */
91
92#include <linux/module.h>
93#include <linux/kernel.h>
94#include <linux/sched.h>
95#include <linux/slab.h>
96#include <linux/init.h>
97#include <linux/list.h>
98#include <linux/kobject.h>
99#include <linux/prefetch.h>
100#include <linux/platform_device.h>
101#include <linux/io.h>
102
103#include "musb_core.h"
104
105#define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
106
107
108#define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
109#define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
110
111#define MUSB_VERSION "6.0"
112
113#define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
114
115#define MUSB_DRIVER_NAME "musb-hdrc"
116const char musb_driver_name[] = MUSB_DRIVER_NAME;
117
118MODULE_DESCRIPTION(DRIVER_INFO);
119MODULE_AUTHOR(DRIVER_AUTHOR);
120MODULE_LICENSE("GPL");
121MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
122
123
124/*-------------------------------------------------------------------------*/
125
126static inline struct musb *dev_to_musb(struct device *dev)
127{
128 return dev_get_drvdata(dev);
129}
130
131/*-------------------------------------------------------------------------*/
132
133#ifndef CONFIG_BLACKFIN
134static int musb_ulpi_read(struct otg_transceiver *otg, u32 offset)
135{
136 void __iomem *addr = otg->io_priv;
137 int i = 0;
138 u8 r;
139 u8 power;
140
141 /* Make sure the transceiver is not in low power mode */
142 power = musb_readb(addr, MUSB_POWER);
143 power &= ~MUSB_POWER_SUSPENDM;
144 musb_writeb(addr, MUSB_POWER, power);
145
146 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
147 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
148 */
149
150 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
151 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
152 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
153
154 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
155 & MUSB_ULPI_REG_CMPLT)) {
156 i++;
157 if (i == 10000)
158 return -ETIMEDOUT;
159
160 }
161 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
162 r &= ~MUSB_ULPI_REG_CMPLT;
163 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
164
165 return musb_readb(addr, MUSB_ULPI_REG_DATA);
166}
167
168static int musb_ulpi_write(struct otg_transceiver *otg,
169 u32 offset, u32 data)
170{
171 void __iomem *addr = otg->io_priv;
172 int i = 0;
173 u8 r = 0;
174 u8 power;
175
176 /* Make sure the transceiver is not in low power mode */
177 power = musb_readb(addr, MUSB_POWER);
178 power &= ~MUSB_POWER_SUSPENDM;
179 musb_writeb(addr, MUSB_POWER, power);
180
181 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
182 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data);
183 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
184
185 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
186 & MUSB_ULPI_REG_CMPLT)) {
187 i++;
188 if (i == 10000)
189 return -ETIMEDOUT;
190 }
191
192 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
193 r &= ~MUSB_ULPI_REG_CMPLT;
194 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
195
196 return 0;
197}
198#else
199#define musb_ulpi_read NULL
200#define musb_ulpi_write NULL
201#endif
202
203static struct otg_io_access_ops musb_ulpi_access = {
204 .read = musb_ulpi_read,
205 .write = musb_ulpi_write,
206};
207
208/*-------------------------------------------------------------------------*/
209
210#if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN)
211
212/*
213 * Load an endpoint's FIFO
214 */
215void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
216{
217 struct musb *musb = hw_ep->musb;
218 void __iomem *fifo = hw_ep->fifo;
219
220 prefetch((u8 *)src);
221
222 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
223 'T', hw_ep->epnum, fifo, len, src);
224
225 /* we can't assume unaligned reads work */
226 if (likely((0x01 & (unsigned long) src) == 0)) {
227 u16 index = 0;
228
229 /* best case is 32bit-aligned source address */
230 if ((0x02 & (unsigned long) src) == 0) {
231 if (len >= 4) {
232 writesl(fifo, src + index, len >> 2);
233 index += len & ~0x03;
234 }
235 if (len & 0x02) {
236 musb_writew(fifo, 0, *(u16 *)&src[index]);
237 index += 2;
238 }
239 } else {
240 if (len >= 2) {
241 writesw(fifo, src + index, len >> 1);
242 index += len & ~0x01;
243 }
244 }
245 if (len & 0x01)
246 musb_writeb(fifo, 0, src[index]);
247 } else {
248 /* byte aligned */
249 writesb(fifo, src, len);
250 }
251}
252
253#if !defined(CONFIG_USB_MUSB_AM35X)
254/*
255 * Unload an endpoint's FIFO
256 */
257void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
258{
259 struct musb *musb = hw_ep->musb;
260 void __iomem *fifo = hw_ep->fifo;
261
262 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
263 'R', hw_ep->epnum, fifo, len, dst);
264
265 /* we can't assume unaligned writes work */
266 if (likely((0x01 & (unsigned long) dst) == 0)) {
267 u16 index = 0;
268
269 /* best case is 32bit-aligned destination address */
270 if ((0x02 & (unsigned long) dst) == 0) {
271 if (len >= 4) {
272 readsl(fifo, dst, len >> 2);
273 index = len & ~0x03;
274 }
275 if (len & 0x02) {
276 *(u16 *)&dst[index] = musb_readw(fifo, 0);
277 index += 2;
278 }
279 } else {
280 if (len >= 2) {
281 readsw(fifo, dst, len >> 1);
282 index = len & ~0x01;
283 }
284 }
285 if (len & 0x01)
286 dst[index] = musb_readb(fifo, 0);
287 } else {
288 /* byte aligned */
289 readsb(fifo, dst, len);
290 }
291}
292#endif
293
294#endif /* normal PIO */
295
296
297/*-------------------------------------------------------------------------*/
298
299/* for high speed test mode; see USB 2.0 spec 7.1.20 */
300static const u8 musb_test_packet[53] = {
301 /* implicit SYNC then DATA0 to start */
302
303 /* JKJKJKJK x9 */
304 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
305 /* JJKKJJKK x8 */
306 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
307 /* JJJJKKKK x8 */
308 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
309 /* JJJJJJJKKKKKKK x8 */
310 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
311 /* JJJJJJJK x8 */
312 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
313 /* JKKKKKKK x10, JK */
314 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
315
316 /* implicit CRC16 then EOP to end */
317};
318
319void musb_load_testpacket(struct musb *musb)
320{
321 void __iomem *regs = musb->endpoints[0].regs;
322
323 musb_ep_select(musb->mregs, 0);
324 musb_write_fifo(musb->control_ep,
325 sizeof(musb_test_packet), musb_test_packet);
326 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
327}
328
329/*-------------------------------------------------------------------------*/
330
331/*
332 * Handles OTG hnp timeouts, such as b_ase0_brst
333 */
334void musb_otg_timer_func(unsigned long data)
335{
336 struct musb *musb = (struct musb *)data;
337 unsigned long flags;
338
339 spin_lock_irqsave(&musb->lock, flags);
340 switch (musb->xceiv->state) {
341 case OTG_STATE_B_WAIT_ACON:
342 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n");
343 musb_g_disconnect(musb);
344 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
345 musb->is_active = 0;
346 break;
347 case OTG_STATE_A_SUSPEND:
348 case OTG_STATE_A_WAIT_BCON:
349 dev_dbg(musb->controller, "HNP: %s timeout\n",
350 otg_state_string(musb->xceiv->state));
351 musb_platform_set_vbus(musb, 0);
352 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
353 break;
354 default:
355 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
356 otg_state_string(musb->xceiv->state));
357 }
358 musb->ignore_disconnect = 0;
359 spin_unlock_irqrestore(&musb->lock, flags);
360}
361
362/*
363 * Stops the HNP transition. Caller must take care of locking.
364 */
365void musb_hnp_stop(struct musb *musb)
366{
367 struct usb_hcd *hcd = musb_to_hcd(musb);
368 void __iomem *mbase = musb->mregs;
369 u8 reg;
370
371 dev_dbg(musb->controller, "HNP: stop from %s\n", otg_state_string(musb->xceiv->state));
372
373 switch (musb->xceiv->state) {
374 case OTG_STATE_A_PERIPHERAL:
375 musb_g_disconnect(musb);
376 dev_dbg(musb->controller, "HNP: back to %s\n",
377 otg_state_string(musb->xceiv->state));
378 break;
379 case OTG_STATE_B_HOST:
380 dev_dbg(musb->controller, "HNP: Disabling HR\n");
381 hcd->self.is_b_host = 0;
382 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
383 MUSB_DEV_MODE(musb);
384 reg = musb_readb(mbase, MUSB_POWER);
385 reg |= MUSB_POWER_SUSPENDM;
386 musb_writeb(mbase, MUSB_POWER, reg);
387 /* REVISIT: Start SESSION_REQUEST here? */
388 break;
389 default:
390 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n",
391 otg_state_string(musb->xceiv->state));
392 }
393
394 /*
395 * When returning to A state after HNP, avoid hub_port_rebounce(),
396 * which cause occasional OPT A "Did not receive reset after connect"
397 * errors.
398 */
399 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
400}
401
402/*
403 * Interrupt Service Routine to record USB "global" interrupts.
404 * Since these do not happen often and signify things of
405 * paramount importance, it seems OK to check them individually;
406 * the order of the tests is specified in the manual
407 *
408 * @param musb instance pointer
409 * @param int_usb register contents
410 * @param devctl
411 * @param power
412 */
413
414static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
415 u8 devctl, u8 power)
416{
417 irqreturn_t handled = IRQ_NONE;
418
419 dev_dbg(musb->controller, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl,
420 int_usb);
421
422 /* in host mode, the peripheral may issue remote wakeup.
423 * in peripheral mode, the host may resume the link.
424 * spurious RESUME irqs happen too, paired with SUSPEND.
425 */
426 if (int_usb & MUSB_INTR_RESUME) {
427 handled = IRQ_HANDLED;
428 dev_dbg(musb->controller, "RESUME (%s)\n", otg_state_string(musb->xceiv->state));
429
430 if (devctl & MUSB_DEVCTL_HM) {
431 void __iomem *mbase = musb->mregs;
432
433 switch (musb->xceiv->state) {
434 case OTG_STATE_A_SUSPEND:
435 /* remote wakeup? later, GetPortStatus
436 * will stop RESUME signaling
437 */
438
439 if (power & MUSB_POWER_SUSPENDM) {
440 /* spurious */
441 musb->int_usb &= ~MUSB_INTR_SUSPEND;
442 dev_dbg(musb->controller, "Spurious SUSPENDM\n");
443 break;
444 }
445
446 power &= ~MUSB_POWER_SUSPENDM;
447 musb_writeb(mbase, MUSB_POWER,
448 power | MUSB_POWER_RESUME);
449
450 musb->port1_status |=
451 (USB_PORT_STAT_C_SUSPEND << 16)
452 | MUSB_PORT_STAT_RESUME;
453 musb->rh_timer = jiffies
454 + msecs_to_jiffies(20);
455
456 musb->xceiv->state = OTG_STATE_A_HOST;
457 musb->is_active = 1;
458 usb_hcd_resume_root_hub(musb_to_hcd(musb));
459 break;
460 case OTG_STATE_B_WAIT_ACON:
461 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
462 musb->is_active = 1;
463 MUSB_DEV_MODE(musb);
464 break;
465 default:
466 WARNING("bogus %s RESUME (%s)\n",
467 "host",
468 otg_state_string(musb->xceiv->state));
469 }
470 } else {
471 switch (musb->xceiv->state) {
472 case OTG_STATE_A_SUSPEND:
473 /* possibly DISCONNECT is upcoming */
474 musb->xceiv->state = OTG_STATE_A_HOST;
475 usb_hcd_resume_root_hub(musb_to_hcd(musb));
476 break;
477 case OTG_STATE_B_WAIT_ACON:
478 case OTG_STATE_B_PERIPHERAL:
479 /* disconnect while suspended? we may
480 * not get a disconnect irq...
481 */
482 if ((devctl & MUSB_DEVCTL_VBUS)
483 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
484 ) {
485 musb->int_usb |= MUSB_INTR_DISCONNECT;
486 musb->int_usb &= ~MUSB_INTR_SUSPEND;
487 break;
488 }
489 musb_g_resume(musb);
490 break;
491 case OTG_STATE_B_IDLE:
492 musb->int_usb &= ~MUSB_INTR_SUSPEND;
493 break;
494 default:
495 WARNING("bogus %s RESUME (%s)\n",
496 "peripheral",
497 otg_state_string(musb->xceiv->state));
498 }
499 }
500 }
501
502 /* see manual for the order of the tests */
503 if (int_usb & MUSB_INTR_SESSREQ) {
504 void __iomem *mbase = musb->mregs;
505
506 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
507 && (devctl & MUSB_DEVCTL_BDEVICE)) {
508 dev_dbg(musb->controller, "SessReq while on B state\n");
509 return IRQ_HANDLED;
510 }
511
512 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n",
513 otg_state_string(musb->xceiv->state));
514
515 /* IRQ arrives from ID pin sense or (later, if VBUS power
516 * is removed) SRP. responses are time critical:
517 * - turn on VBUS (with silicon-specific mechanism)
518 * - go through A_WAIT_VRISE
519 * - ... to A_WAIT_BCON.
520 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
521 */
522 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
523 musb->ep0_stage = MUSB_EP0_START;
524 musb->xceiv->state = OTG_STATE_A_IDLE;
525 MUSB_HST_MODE(musb);
526 musb_platform_set_vbus(musb, 1);
527
528 handled = IRQ_HANDLED;
529 }
530
531 if (int_usb & MUSB_INTR_VBUSERROR) {
532 int ignore = 0;
533
534 /* During connection as an A-Device, we may see a short
535 * current spikes causing voltage drop, because of cable
536 * and peripheral capacitance combined with vbus draw.
537 * (So: less common with truly self-powered devices, where
538 * vbus doesn't act like a power supply.)
539 *
540 * Such spikes are short; usually less than ~500 usec, max
541 * of ~2 msec. That is, they're not sustained overcurrent
542 * errors, though they're reported using VBUSERROR irqs.
543 *
544 * Workarounds: (a) hardware: use self powered devices.
545 * (b) software: ignore non-repeated VBUS errors.
546 *
547 * REVISIT: do delays from lots of DEBUG_KERNEL checks
548 * make trouble here, keeping VBUS < 4.4V ?
549 */
550 switch (musb->xceiv->state) {
551 case OTG_STATE_A_HOST:
552 /* recovery is dicey once we've gotten past the
553 * initial stages of enumeration, but if VBUS
554 * stayed ok at the other end of the link, and
555 * another reset is due (at least for high speed,
556 * to redo the chirp etc), it might work OK...
557 */
558 case OTG_STATE_A_WAIT_BCON:
559 case OTG_STATE_A_WAIT_VRISE:
560 if (musb->vbuserr_retry) {
561 void __iomem *mbase = musb->mregs;
562
563 musb->vbuserr_retry--;
564 ignore = 1;
565 devctl |= MUSB_DEVCTL_SESSION;
566 musb_writeb(mbase, MUSB_DEVCTL, devctl);
567 } else {
568 musb->port1_status |=
569 USB_PORT_STAT_OVERCURRENT
570 | (USB_PORT_STAT_C_OVERCURRENT << 16);
571 }
572 break;
573 default:
574 break;
575 }
576
577 dev_dbg(musb->controller, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
578 otg_state_string(musb->xceiv->state),
579 devctl,
580 ({ char *s;
581 switch (devctl & MUSB_DEVCTL_VBUS) {
582 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
583 s = "<SessEnd"; break;
584 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
585 s = "<AValid"; break;
586 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
587 s = "<VBusValid"; break;
588 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
589 default:
590 s = "VALID"; break;
591 }; s; }),
592 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
593 musb->port1_status);
594
595 /* go through A_WAIT_VFALL then start a new session */
596 if (!ignore)
597 musb_platform_set_vbus(musb, 0);
598 handled = IRQ_HANDLED;
599 }
600
601 if (int_usb & MUSB_INTR_SUSPEND) {
602 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x power %02x\n",
603 otg_state_string(musb->xceiv->state), devctl, power);
604 handled = IRQ_HANDLED;
605
606 switch (musb->xceiv->state) {
607 case OTG_STATE_A_PERIPHERAL:
608 /* We also come here if the cable is removed, since
609 * this silicon doesn't report ID-no-longer-grounded.
610 *
611 * We depend on T(a_wait_bcon) to shut us down, and
612 * hope users don't do anything dicey during this
613 * undesired detour through A_WAIT_BCON.
614 */
615 musb_hnp_stop(musb);
616 usb_hcd_resume_root_hub(musb_to_hcd(musb));
617 musb_root_disconnect(musb);
618 musb_platform_try_idle(musb, jiffies
619 + msecs_to_jiffies(musb->a_wait_bcon
620 ? : OTG_TIME_A_WAIT_BCON));
621
622 break;
623 case OTG_STATE_B_IDLE:
624 if (!musb->is_active)
625 break;
626 case OTG_STATE_B_PERIPHERAL:
627 musb_g_suspend(musb);
628 musb->is_active = is_otg_enabled(musb)
629 && musb->xceiv->gadget->b_hnp_enable;
630 if (musb->is_active) {
631 musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
632 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
633 mod_timer(&musb->otg_timer, jiffies
634 + msecs_to_jiffies(
635 OTG_TIME_B_ASE0_BRST));
636 }
637 break;
638 case OTG_STATE_A_WAIT_BCON:
639 if (musb->a_wait_bcon != 0)
640 musb_platform_try_idle(musb, jiffies
641 + msecs_to_jiffies(musb->a_wait_bcon));
642 break;
643 case OTG_STATE_A_HOST:
644 musb->xceiv->state = OTG_STATE_A_SUSPEND;
645 musb->is_active = is_otg_enabled(musb)
646 && musb->xceiv->host->b_hnp_enable;
647 break;
648 case OTG_STATE_B_HOST:
649 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
650 dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n");
651 break;
652 default:
653 /* "should not happen" */
654 musb->is_active = 0;
655 break;
656 }
657 }
658
659 if (int_usb & MUSB_INTR_CONNECT) {
660 struct usb_hcd *hcd = musb_to_hcd(musb);
661
662 handled = IRQ_HANDLED;
663 musb->is_active = 1;
664 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
665
666 musb->ep0_stage = MUSB_EP0_START;
667
668 /* flush endpoints when transitioning from Device Mode */
669 if (is_peripheral_active(musb)) {
670 /* REVISIT HNP; just force disconnect */
671 }
672 musb_writew(musb->mregs, MUSB_INTRTXE, musb->epmask);
673 musb_writew(musb->mregs, MUSB_INTRRXE, musb->epmask & 0xfffe);
674 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
675 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
676 |USB_PORT_STAT_HIGH_SPEED
677 |USB_PORT_STAT_ENABLE
678 );
679 musb->port1_status |= USB_PORT_STAT_CONNECTION
680 |(USB_PORT_STAT_C_CONNECTION << 16);
681
682 /* high vs full speed is just a guess until after reset */
683 if (devctl & MUSB_DEVCTL_LSDEV)
684 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
685
686 /* indicate new connection to OTG machine */
687 switch (musb->xceiv->state) {
688 case OTG_STATE_B_PERIPHERAL:
689 if (int_usb & MUSB_INTR_SUSPEND) {
690 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
691 int_usb &= ~MUSB_INTR_SUSPEND;
692 goto b_host;
693 } else
694 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
695 break;
696 case OTG_STATE_B_WAIT_ACON:
697 dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n");
698b_host:
699 musb->xceiv->state = OTG_STATE_B_HOST;
700 hcd->self.is_b_host = 1;
701 musb->ignore_disconnect = 0;
702 del_timer(&musb->otg_timer);
703 break;
704 default:
705 if ((devctl & MUSB_DEVCTL_VBUS)
706 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
707 musb->xceiv->state = OTG_STATE_A_HOST;
708 hcd->self.is_b_host = 0;
709 }
710 break;
711 }
712
713 /* poke the root hub */
714 MUSB_HST_MODE(musb);
715 if (hcd->status_urb)
716 usb_hcd_poll_rh_status(hcd);
717 else
718 usb_hcd_resume_root_hub(hcd);
719
720 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",
721 otg_state_string(musb->xceiv->state), devctl);
722 }
723
724 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
725 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n",
726 otg_state_string(musb->xceiv->state),
727 MUSB_MODE(musb), devctl);
728 handled = IRQ_HANDLED;
729
730 switch (musb->xceiv->state) {
731 case OTG_STATE_A_HOST:
732 case OTG_STATE_A_SUSPEND:
733 usb_hcd_resume_root_hub(musb_to_hcd(musb));
734 musb_root_disconnect(musb);
735 if (musb->a_wait_bcon != 0 && is_otg_enabled(musb))
736 musb_platform_try_idle(musb, jiffies
737 + msecs_to_jiffies(musb->a_wait_bcon));
738 break;
739 case OTG_STATE_B_HOST:
740 /* REVISIT this behaves for "real disconnect"
741 * cases; make sure the other transitions from
742 * from B_HOST act right too. The B_HOST code
743 * in hnp_stop() is currently not used...
744 */
745 musb_root_disconnect(musb);
746 musb_to_hcd(musb)->self.is_b_host = 0;
747 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
748 MUSB_DEV_MODE(musb);
749 musb_g_disconnect(musb);
750 break;
751 case OTG_STATE_A_PERIPHERAL:
752 musb_hnp_stop(musb);
753 musb_root_disconnect(musb);
754 /* FALLTHROUGH */
755 case OTG_STATE_B_WAIT_ACON:
756 /* FALLTHROUGH */
757 case OTG_STATE_B_PERIPHERAL:
758 case OTG_STATE_B_IDLE:
759 musb_g_disconnect(musb);
760 break;
761 default:
762 WARNING("unhandled DISCONNECT transition (%s)\n",
763 otg_state_string(musb->xceiv->state));
764 break;
765 }
766 }
767
768 /* mentor saves a bit: bus reset and babble share the same irq.
769 * only host sees babble; only peripheral sees bus reset.
770 */
771 if (int_usb & MUSB_INTR_RESET) {
772 handled = IRQ_HANDLED;
773 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) {
774 /*
775 * Looks like non-HS BABBLE can be ignored, but
776 * HS BABBLE is an error condition. For HS the solution
777 * is to avoid babble in the first place and fix what
778 * caused BABBLE. When HS BABBLE happens we can only
779 * stop the session.
780 */
781 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
782 dev_dbg(musb->controller, "BABBLE devctl: %02x\n", devctl);
783 else {
784 ERR("Stopping host session -- babble\n");
785 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
786 }
787 } else if (is_peripheral_capable()) {
788 dev_dbg(musb->controller, "BUS RESET as %s\n",
789 otg_state_string(musb->xceiv->state));
790 switch (musb->xceiv->state) {
791 case OTG_STATE_A_SUSPEND:
792 /* We need to ignore disconnect on suspend
793 * otherwise tusb 2.0 won't reconnect after a
794 * power cycle, which breaks otg compliance.
795 */
796 musb->ignore_disconnect = 1;
797 musb_g_reset(musb);
798 /* FALLTHROUGH */
799 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
800 /* never use invalid T(a_wait_bcon) */
801 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n",
802 otg_state_string(musb->xceiv->state),
803 TA_WAIT_BCON(musb));
804 mod_timer(&musb->otg_timer, jiffies
805 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
806 break;
807 case OTG_STATE_A_PERIPHERAL:
808 musb->ignore_disconnect = 0;
809 del_timer(&musb->otg_timer);
810 musb_g_reset(musb);
811 break;
812 case OTG_STATE_B_WAIT_ACON:
813 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",
814 otg_state_string(musb->xceiv->state));
815 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
816 musb_g_reset(musb);
817 break;
818 case OTG_STATE_B_IDLE:
819 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
820 /* FALLTHROUGH */
821 case OTG_STATE_B_PERIPHERAL:
822 musb_g_reset(musb);
823 break;
824 default:
825 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n",
826 otg_state_string(musb->xceiv->state));
827 }
828 }
829 }
830
831#if 0
832/* REVISIT ... this would be for multiplexing periodic endpoints, or
833 * supporting transfer phasing to prevent exceeding ISO bandwidth
834 * limits of a given frame or microframe.
835 *
836 * It's not needed for peripheral side, which dedicates endpoints;
837 * though it _might_ use SOF irqs for other purposes.
838 *
839 * And it's not currently needed for host side, which also dedicates
840 * endpoints, relies on TX/RX interval registers, and isn't claimed
841 * to support ISO transfers yet.
842 */
843 if (int_usb & MUSB_INTR_SOF) {
844 void __iomem *mbase = musb->mregs;
845 struct musb_hw_ep *ep;
846 u8 epnum;
847 u16 frame;
848
849 dev_dbg(musb->controller, "START_OF_FRAME\n");
850 handled = IRQ_HANDLED;
851
852 /* start any periodic Tx transfers waiting for current frame */
853 frame = musb_readw(mbase, MUSB_FRAME);
854 ep = musb->endpoints;
855 for (epnum = 1; (epnum < musb->nr_endpoints)
856 && (musb->epmask >= (1 << epnum));
857 epnum++, ep++) {
858 /*
859 * FIXME handle framecounter wraps (12 bits)
860 * eliminate duplicated StartUrb logic
861 */
862 if (ep->dwWaitFrame >= frame) {
863 ep->dwWaitFrame = 0;
864 pr_debug("SOF --> periodic TX%s on %d\n",
865 ep->tx_channel ? " DMA" : "",
866 epnum);
867 if (!ep->tx_channel)
868 musb_h_tx_start(musb, epnum);
869 else
870 cppi_hostdma_start(musb, epnum);
871 }
872 } /* end of for loop */
873 }
874#endif
875
876 schedule_work(&musb->irq_work);
877
878 return handled;
879}
880
881/*-------------------------------------------------------------------------*/
882
883/*
884* Program the HDRC to start (enable interrupts, dma, etc.).
885*/
886void musb_start(struct musb *musb)
887{
888 void __iomem *regs = musb->mregs;
889 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
890
891 dev_dbg(musb->controller, "<== devctl %02x\n", devctl);
892
893 /* Set INT enable registers, enable interrupts */
894 musb_writew(regs, MUSB_INTRTXE, musb->epmask);
895 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe);
896 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
897
898 musb_writeb(regs, MUSB_TESTMODE, 0);
899
900 /* put into basic highspeed mode and start session */
901 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
902 | MUSB_POWER_HSENAB
903 /* ENSUSPEND wedges tusb */
904 /* | MUSB_POWER_ENSUSPEND */
905 );
906
907 musb->is_active = 0;
908 devctl = musb_readb(regs, MUSB_DEVCTL);
909 devctl &= ~MUSB_DEVCTL_SESSION;
910
911 if (is_otg_enabled(musb)) {
912 /* session started after:
913 * (a) ID-grounded irq, host mode;
914 * (b) vbus present/connect IRQ, peripheral mode;
915 * (c) peripheral initiates, using SRP
916 */
917 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
918 musb->is_active = 1;
919 else
920 devctl |= MUSB_DEVCTL_SESSION;
921
922 } else if (is_host_enabled(musb)) {
923 /* assume ID pin is hard-wired to ground */
924 devctl |= MUSB_DEVCTL_SESSION;
925
926 } else /* peripheral is enabled */ {
927 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
928 musb->is_active = 1;
929 }
930 musb_platform_enable(musb);
931 musb_writeb(regs, MUSB_DEVCTL, devctl);
932}
933
934
935static void musb_generic_disable(struct musb *musb)
936{
937 void __iomem *mbase = musb->mregs;
938 u16 temp;
939
940 /* disable interrupts */
941 musb_writeb(mbase, MUSB_INTRUSBE, 0);
942 musb_writew(mbase, MUSB_INTRTXE, 0);
943 musb_writew(mbase, MUSB_INTRRXE, 0);
944
945 /* off */
946 musb_writeb(mbase, MUSB_DEVCTL, 0);
947
948 /* flush pending interrupts */
949 temp = musb_readb(mbase, MUSB_INTRUSB);
950 temp = musb_readw(mbase, MUSB_INTRTX);
951 temp = musb_readw(mbase, MUSB_INTRRX);
952
953}
954
955/*
956 * Make the HDRC stop (disable interrupts, etc.);
957 * reversible by musb_start
958 * called on gadget driver unregister
959 * with controller locked, irqs blocked
960 * acts as a NOP unless some role activated the hardware
961 */
962void musb_stop(struct musb *musb)
963{
964 /* stop IRQs, timers, ... */
965 musb_platform_disable(musb);
966 musb_generic_disable(musb);
967 dev_dbg(musb->controller, "HDRC disabled\n");
968
969 /* FIXME
970 * - mark host and/or peripheral drivers unusable/inactive
971 * - disable DMA (and enable it in HdrcStart)
972 * - make sure we can musb_start() after musb_stop(); with
973 * OTG mode, gadget driver module rmmod/modprobe cycles that
974 * - ...
975 */
976 musb_platform_try_idle(musb, 0);
977}
978
979static void musb_shutdown(struct platform_device *pdev)
980{
981 struct musb *musb = dev_to_musb(&pdev->dev);
982 unsigned long flags;
983
984 pm_runtime_get_sync(musb->controller);
985 spin_lock_irqsave(&musb->lock, flags);
986 musb_platform_disable(musb);
987 musb_generic_disable(musb);
988 spin_unlock_irqrestore(&musb->lock, flags);
989
990 if (!is_otg_enabled(musb) && is_host_enabled(musb))
991 usb_remove_hcd(musb_to_hcd(musb));
992 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
993 musb_platform_exit(musb);
994
995 pm_runtime_put(musb->controller);
996 /* FIXME power down */
997}
998
999
1000/*-------------------------------------------------------------------------*/
1001
1002/*
1003 * The silicon either has hard-wired endpoint configurations, or else
1004 * "dynamic fifo" sizing. The driver has support for both, though at this
1005 * writing only the dynamic sizing is very well tested. Since we switched
1006 * away from compile-time hardware parameters, we can no longer rely on
1007 * dead code elimination to leave only the relevant one in the object file.
1008 *
1009 * We don't currently use dynamic fifo setup capability to do anything
1010 * more than selecting one of a bunch of predefined configurations.
1011 */
1012#if defined(CONFIG_USB_MUSB_TUSB6010) \
1013 || defined(CONFIG_USB_MUSB_TUSB6010_MODULE) \
1014 || defined(CONFIG_USB_MUSB_OMAP2PLUS) \
1015 || defined(CONFIG_USB_MUSB_OMAP2PLUS_MODULE) \
1016 || defined(CONFIG_USB_MUSB_AM35X) \
1017 || defined(CONFIG_USB_MUSB_AM35X_MODULE)
1018static ushort __initdata fifo_mode = 4;
1019#elif defined(CONFIG_USB_MUSB_UX500) \
1020 || defined(CONFIG_USB_MUSB_UX500_MODULE)
1021static ushort __initdata fifo_mode = 5;
1022#else
1023static ushort __initdata fifo_mode = 2;
1024#endif
1025
1026/* "modprobe ... fifo_mode=1" etc */
1027module_param(fifo_mode, ushort, 0);
1028MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1029
1030/*
1031 * tables defining fifo_mode values. define more if you like.
1032 * for host side, make sure both halves of ep1 are set up.
1033 */
1034
1035/* mode 0 - fits in 2KB */
1036static struct musb_fifo_cfg __initdata mode_0_cfg[] = {
1037{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1038{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1039{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1040{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1041{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1042};
1043
1044/* mode 1 - fits in 4KB */
1045static struct musb_fifo_cfg __initdata mode_1_cfg[] = {
1046{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1047{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1048{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1049{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1050{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1051};
1052
1053/* mode 2 - fits in 4KB */
1054static struct musb_fifo_cfg __initdata mode_2_cfg[] = {
1055{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1056{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1057{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1058{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1059{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1060{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1061};
1062
1063/* mode 3 - fits in 4KB */
1064static struct musb_fifo_cfg __initdata mode_3_cfg[] = {
1065{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1066{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1067{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1068{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1069{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1070{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1071};
1072
1073/* mode 4 - fits in 16KB */
1074static struct musb_fifo_cfg __initdata mode_4_cfg[] = {
1075{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1076{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1077{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1078{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1079{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1080{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1081{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1082{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1083{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1084{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1085{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1086{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1087{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1088{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1089{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1090{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1091{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1092{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1093{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1094{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1095{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1096{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1097{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1098{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1099{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1100{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1101{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1102};
1103
1104/* mode 5 - fits in 8KB */
1105static struct musb_fifo_cfg __initdata mode_5_cfg[] = {
1106{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1107{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1108{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1109{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1110{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1111{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1112{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1113{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1114{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1115{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1116{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1117{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1118{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1119{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1120{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1121{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1122{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1123{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1124{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1125{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1126{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1127{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1128{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1129{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1130{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1131{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1132{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1133};
1134
1135/*
1136 * configure a fifo; for non-shared endpoints, this may be called
1137 * once for a tx fifo and once for an rx fifo.
1138 *
1139 * returns negative errno or offset for next fifo.
1140 */
1141static int __init
1142fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1143 const struct musb_fifo_cfg *cfg, u16 offset)
1144{
1145 void __iomem *mbase = musb->mregs;
1146 int size = 0;
1147 u16 maxpacket = cfg->maxpacket;
1148 u16 c_off = offset >> 3;
1149 u8 c_size;
1150
1151 /* expect hw_ep has already been zero-initialized */
1152
1153 size = ffs(max(maxpacket, (u16) 8)) - 1;
1154 maxpacket = 1 << size;
1155
1156 c_size = size - 3;
1157 if (cfg->mode == BUF_DOUBLE) {
1158 if ((offset + (maxpacket << 1)) >
1159 (1 << (musb->config->ram_bits + 2)))
1160 return -EMSGSIZE;
1161 c_size |= MUSB_FIFOSZ_DPB;
1162 } else {
1163 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1164 return -EMSGSIZE;
1165 }
1166
1167 /* configure the FIFO */
1168 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1169
1170 /* EP0 reserved endpoint for control, bidirectional;
1171 * EP1 reserved for bulk, two unidirection halves.
1172 */
1173 if (hw_ep->epnum == 1)
1174 musb->bulk_ep = hw_ep;
1175 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1176 switch (cfg->style) {
1177 case FIFO_TX:
1178 musb_write_txfifosz(mbase, c_size);
1179 musb_write_txfifoadd(mbase, c_off);
1180 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1181 hw_ep->max_packet_sz_tx = maxpacket;
1182 break;
1183 case FIFO_RX:
1184 musb_write_rxfifosz(mbase, c_size);
1185 musb_write_rxfifoadd(mbase, c_off);
1186 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1187 hw_ep->max_packet_sz_rx = maxpacket;
1188 break;
1189 case FIFO_RXTX:
1190 musb_write_txfifosz(mbase, c_size);
1191 musb_write_txfifoadd(mbase, c_off);
1192 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1193 hw_ep->max_packet_sz_rx = maxpacket;
1194
1195 musb_write_rxfifosz(mbase, c_size);
1196 musb_write_rxfifoadd(mbase, c_off);
1197 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1198 hw_ep->max_packet_sz_tx = maxpacket;
1199
1200 hw_ep->is_shared_fifo = true;
1201 break;
1202 }
1203
1204 /* NOTE rx and tx endpoint irqs aren't managed separately,
1205 * which happens to be ok
1206 */
1207 musb->epmask |= (1 << hw_ep->epnum);
1208
1209 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1210}
1211
1212static struct musb_fifo_cfg __initdata ep0_cfg = {
1213 .style = FIFO_RXTX, .maxpacket = 64,
1214};
1215
1216static int __init ep_config_from_table(struct musb *musb)
1217{
1218 const struct musb_fifo_cfg *cfg;
1219 unsigned i, n;
1220 int offset;
1221 struct musb_hw_ep *hw_ep = musb->endpoints;
1222
1223 if (musb->config->fifo_cfg) {
1224 cfg = musb->config->fifo_cfg;
1225 n = musb->config->fifo_cfg_size;
1226 goto done;
1227 }
1228
1229 switch (fifo_mode) {
1230 default:
1231 fifo_mode = 0;
1232 /* FALLTHROUGH */
1233 case 0:
1234 cfg = mode_0_cfg;
1235 n = ARRAY_SIZE(mode_0_cfg);
1236 break;
1237 case 1:
1238 cfg = mode_1_cfg;
1239 n = ARRAY_SIZE(mode_1_cfg);
1240 break;
1241 case 2:
1242 cfg = mode_2_cfg;
1243 n = ARRAY_SIZE(mode_2_cfg);
1244 break;
1245 case 3:
1246 cfg = mode_3_cfg;
1247 n = ARRAY_SIZE(mode_3_cfg);
1248 break;
1249 case 4:
1250 cfg = mode_4_cfg;
1251 n = ARRAY_SIZE(mode_4_cfg);
1252 break;
1253 case 5:
1254 cfg = mode_5_cfg;
1255 n = ARRAY_SIZE(mode_5_cfg);
1256 break;
1257 }
1258
1259 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1260 musb_driver_name, fifo_mode);
1261
1262
1263done:
1264 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1265 /* assert(offset > 0) */
1266
1267 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1268 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1269 */
1270
1271 for (i = 0; i < n; i++) {
1272 u8 epn = cfg->hw_ep_num;
1273
1274 if (epn >= musb->config->num_eps) {
1275 pr_debug("%s: invalid ep %d\n",
1276 musb_driver_name, epn);
1277 return -EINVAL;
1278 }
1279 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1280 if (offset < 0) {
1281 pr_debug("%s: mem overrun, ep %d\n",
1282 musb_driver_name, epn);
1283 return -EINVAL;
1284 }
1285 epn++;
1286 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1287 }
1288
1289 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1290 musb_driver_name,
1291 n + 1, musb->config->num_eps * 2 - 1,
1292 offset, (1 << (musb->config->ram_bits + 2)));
1293
1294 if (!musb->bulk_ep) {
1295 pr_debug("%s: missing bulk\n", musb_driver_name);
1296 return -EINVAL;
1297 }
1298
1299 return 0;
1300}
1301
1302
1303/*
1304 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1305 * @param musb the controller
1306 */
1307static int __init ep_config_from_hw(struct musb *musb)
1308{
1309 u8 epnum = 0;
1310 struct musb_hw_ep *hw_ep;
1311 void *mbase = musb->mregs;
1312 int ret = 0;
1313
1314 dev_dbg(musb->controller, "<== static silicon ep config\n");
1315
1316 /* FIXME pick up ep0 maxpacket size */
1317
1318 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1319 musb_ep_select(mbase, epnum);
1320 hw_ep = musb->endpoints + epnum;
1321
1322 ret = musb_read_fifosize(musb, hw_ep, epnum);
1323 if (ret < 0)
1324 break;
1325
1326 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1327
1328 /* pick an RX/TX endpoint for bulk */
1329 if (hw_ep->max_packet_sz_tx < 512
1330 || hw_ep->max_packet_sz_rx < 512)
1331 continue;
1332
1333 /* REVISIT: this algorithm is lazy, we should at least
1334 * try to pick a double buffered endpoint.
1335 */
1336 if (musb->bulk_ep)
1337 continue;
1338 musb->bulk_ep = hw_ep;
1339 }
1340
1341 if (!musb->bulk_ep) {
1342 pr_debug("%s: missing bulk\n", musb_driver_name);
1343 return -EINVAL;
1344 }
1345
1346 return 0;
1347}
1348
1349enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1350
1351/* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1352 * configure endpoints, or take their config from silicon
1353 */
1354static int __init musb_core_init(u16 musb_type, struct musb *musb)
1355{
1356 u8 reg;
1357 char *type;
1358 char aInfo[90], aRevision[32], aDate[12];
1359 void __iomem *mbase = musb->mregs;
1360 int status = 0;
1361 int i;
1362
1363 /* log core options (read using indexed model) */
1364 reg = musb_read_configdata(mbase);
1365
1366 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1367 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1368 strcat(aInfo, ", dyn FIFOs");
1369 musb->dyn_fifo = true;
1370 }
1371 if (reg & MUSB_CONFIGDATA_MPRXE) {
1372 strcat(aInfo, ", bulk combine");
1373 musb->bulk_combine = true;
1374 }
1375 if (reg & MUSB_CONFIGDATA_MPTXE) {
1376 strcat(aInfo, ", bulk split");
1377 musb->bulk_split = true;
1378 }
1379 if (reg & MUSB_CONFIGDATA_HBRXE) {
1380 strcat(aInfo, ", HB-ISO Rx");
1381 musb->hb_iso_rx = true;
1382 }
1383 if (reg & MUSB_CONFIGDATA_HBTXE) {
1384 strcat(aInfo, ", HB-ISO Tx");
1385 musb->hb_iso_tx = true;
1386 }
1387 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1388 strcat(aInfo, ", SoftConn");
1389
1390 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1391 musb_driver_name, reg, aInfo);
1392
1393 aDate[0] = 0;
1394 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1395 musb->is_multipoint = 1;
1396 type = "M";
1397 } else {
1398 musb->is_multipoint = 0;
1399 type = "";
1400#ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1401 printk(KERN_ERR
1402 "%s: kernel must blacklist external hubs\n",
1403 musb_driver_name);
1404#endif
1405 }
1406
1407 /* log release info */
1408 musb->hwvers = musb_read_hwvers(mbase);
1409 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1410 MUSB_HWVERS_MINOR(musb->hwvers),
1411 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1412 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1413 musb_driver_name, type, aRevision, aDate);
1414
1415 /* configure ep0 */
1416 musb_configure_ep0(musb);
1417
1418 /* discover endpoint configuration */
1419 musb->nr_endpoints = 1;
1420 musb->epmask = 1;
1421
1422 if (musb->dyn_fifo)
1423 status = ep_config_from_table(musb);
1424 else
1425 status = ep_config_from_hw(musb);
1426
1427 if (status < 0)
1428 return status;
1429
1430 /* finish init, and print endpoint config */
1431 for (i = 0; i < musb->nr_endpoints; i++) {
1432 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1433
1434 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1435#ifdef CONFIG_USB_MUSB_TUSB6010
1436 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1437 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1438 hw_ep->fifo_sync_va =
1439 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1440
1441 if (i == 0)
1442 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1443 else
1444 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1445#endif
1446
1447 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
1448 hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
1449 hw_ep->rx_reinit = 1;
1450 hw_ep->tx_reinit = 1;
1451
1452 if (hw_ep->max_packet_sz_tx) {
1453 dev_dbg(musb->controller,
1454 "%s: hw_ep %d%s, %smax %d\n",
1455 musb_driver_name, i,
1456 hw_ep->is_shared_fifo ? "shared" : "tx",
1457 hw_ep->tx_double_buffered
1458 ? "doublebuffer, " : "",
1459 hw_ep->max_packet_sz_tx);
1460 }
1461 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1462 dev_dbg(musb->controller,
1463 "%s: hw_ep %d%s, %smax %d\n",
1464 musb_driver_name, i,
1465 "rx",
1466 hw_ep->rx_double_buffered
1467 ? "doublebuffer, " : "",
1468 hw_ep->max_packet_sz_rx);
1469 }
1470 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1471 dev_dbg(musb->controller, "hw_ep %d not configured\n", i);
1472 }
1473
1474 return 0;
1475}
1476
1477/*-------------------------------------------------------------------------*/
1478
1479#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430) || \
1480 defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_U8500) || \
1481 defined(CONFIG_ARCH_U5500)
1482
1483static irqreturn_t generic_interrupt(int irq, void *__hci)
1484{
1485 unsigned long flags;
1486 irqreturn_t retval = IRQ_NONE;
1487 struct musb *musb = __hci;
1488
1489 spin_lock_irqsave(&musb->lock, flags);
1490
1491 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
1492 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
1493 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
1494
1495 if (musb->int_usb || musb->int_tx || musb->int_rx)
1496 retval = musb_interrupt(musb);
1497
1498 spin_unlock_irqrestore(&musb->lock, flags);
1499
1500 return retval;
1501}
1502
1503#else
1504#define generic_interrupt NULL
1505#endif
1506
1507/*
1508 * handle all the irqs defined by the HDRC core. for now we expect: other
1509 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1510 * will be assigned, and the irq will already have been acked.
1511 *
1512 * called in irq context with spinlock held, irqs blocked
1513 */
1514irqreturn_t musb_interrupt(struct musb *musb)
1515{
1516 irqreturn_t retval = IRQ_NONE;
1517 u8 devctl, power;
1518 int ep_num;
1519 u32 reg;
1520
1521 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1522 power = musb_readb(musb->mregs, MUSB_POWER);
1523
1524 dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n",
1525 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1526 musb->int_usb, musb->int_tx, musb->int_rx);
1527
1528 /* the core can interrupt us for multiple reasons; docs have
1529 * a generic interrupt flowchart to follow
1530 */
1531 if (musb->int_usb)
1532 retval |= musb_stage0_irq(musb, musb->int_usb,
1533 devctl, power);
1534
1535 /* "stage 1" is handling endpoint irqs */
1536
1537 /* handle endpoint 0 first */
1538 if (musb->int_tx & 1) {
1539 if (devctl & MUSB_DEVCTL_HM)
1540 retval |= musb_h_ep0_irq(musb);
1541 else
1542 retval |= musb_g_ep0_irq(musb);
1543 }
1544
1545 /* RX on endpoints 1-15 */
1546 reg = musb->int_rx >> 1;
1547 ep_num = 1;
1548 while (reg) {
1549 if (reg & 1) {
1550 /* musb_ep_select(musb->mregs, ep_num); */
1551 /* REVISIT just retval = ep->rx_irq(...) */
1552 retval = IRQ_HANDLED;
1553 if (devctl & MUSB_DEVCTL_HM) {
1554 if (is_host_capable())
1555 musb_host_rx(musb, ep_num);
1556 } else {
1557 if (is_peripheral_capable())
1558 musb_g_rx(musb, ep_num);
1559 }
1560 }
1561
1562 reg >>= 1;
1563 ep_num++;
1564 }
1565
1566 /* TX on endpoints 1-15 */
1567 reg = musb->int_tx >> 1;
1568 ep_num = 1;
1569 while (reg) {
1570 if (reg & 1) {
1571 /* musb_ep_select(musb->mregs, ep_num); */
1572 /* REVISIT just retval |= ep->tx_irq(...) */
1573 retval = IRQ_HANDLED;
1574 if (devctl & MUSB_DEVCTL_HM) {
1575 if (is_host_capable())
1576 musb_host_tx(musb, ep_num);
1577 } else {
1578 if (is_peripheral_capable())
1579 musb_g_tx(musb, ep_num);
1580 }
1581 }
1582 reg >>= 1;
1583 ep_num++;
1584 }
1585
1586 return retval;
1587}
1588EXPORT_SYMBOL_GPL(musb_interrupt);
1589
1590#ifndef CONFIG_MUSB_PIO_ONLY
1591static int __initdata use_dma = 1;
1592
1593/* "modprobe ... use_dma=0" etc */
1594module_param(use_dma, bool, 0);
1595MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1596
1597void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1598{
1599 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1600
1601 /* called with controller lock already held */
1602
1603 if (!epnum) {
1604#ifndef CONFIG_USB_TUSB_OMAP_DMA
1605 if (!is_cppi_enabled()) {
1606 /* endpoint 0 */
1607 if (devctl & MUSB_DEVCTL_HM)
1608 musb_h_ep0_irq(musb);
1609 else
1610 musb_g_ep0_irq(musb);
1611 }
1612#endif
1613 } else {
1614 /* endpoints 1..15 */
1615 if (transmit) {
1616 if (devctl & MUSB_DEVCTL_HM) {
1617 if (is_host_capable())
1618 musb_host_tx(musb, epnum);
1619 } else {
1620 if (is_peripheral_capable())
1621 musb_g_tx(musb, epnum);
1622 }
1623 } else {
1624 /* receive */
1625 if (devctl & MUSB_DEVCTL_HM) {
1626 if (is_host_capable())
1627 musb_host_rx(musb, epnum);
1628 } else {
1629 if (is_peripheral_capable())
1630 musb_g_rx(musb, epnum);
1631 }
1632 }
1633 }
1634}
1635
1636#else
1637#define use_dma 0
1638#endif
1639
1640/*-------------------------------------------------------------------------*/
1641
1642#ifdef CONFIG_SYSFS
1643
1644static ssize_t
1645musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1646{
1647 struct musb *musb = dev_to_musb(dev);
1648 unsigned long flags;
1649 int ret = -EINVAL;
1650
1651 spin_lock_irqsave(&musb->lock, flags);
1652 ret = sprintf(buf, "%s\n", otg_state_string(musb->xceiv->state));
1653 spin_unlock_irqrestore(&musb->lock, flags);
1654
1655 return ret;
1656}
1657
1658static ssize_t
1659musb_mode_store(struct device *dev, struct device_attribute *attr,
1660 const char *buf, size_t n)
1661{
1662 struct musb *musb = dev_to_musb(dev);
1663 unsigned long flags;
1664 int status;
1665
1666 spin_lock_irqsave(&musb->lock, flags);
1667 if (sysfs_streq(buf, "host"))
1668 status = musb_platform_set_mode(musb, MUSB_HOST);
1669 else if (sysfs_streq(buf, "peripheral"))
1670 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1671 else if (sysfs_streq(buf, "otg"))
1672 status = musb_platform_set_mode(musb, MUSB_OTG);
1673 else
1674 status = -EINVAL;
1675 spin_unlock_irqrestore(&musb->lock, flags);
1676
1677 return (status == 0) ? n : status;
1678}
1679static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1680
1681static ssize_t
1682musb_vbus_store(struct device *dev, struct device_attribute *attr,
1683 const char *buf, size_t n)
1684{
1685 struct musb *musb = dev_to_musb(dev);
1686 unsigned long flags;
1687 unsigned long val;
1688
1689 if (sscanf(buf, "%lu", &val) < 1) {
1690 dev_err(dev, "Invalid VBUS timeout ms value\n");
1691 return -EINVAL;
1692 }
1693
1694 spin_lock_irqsave(&musb->lock, flags);
1695 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1696 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1697 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
1698 musb->is_active = 0;
1699 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1700 spin_unlock_irqrestore(&musb->lock, flags);
1701
1702 return n;
1703}
1704
1705static ssize_t
1706musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1707{
1708 struct musb *musb = dev_to_musb(dev);
1709 unsigned long flags;
1710 unsigned long val;
1711 int vbus;
1712
1713 spin_lock_irqsave(&musb->lock, flags);
1714 val = musb->a_wait_bcon;
1715 /* FIXME get_vbus_status() is normally #defined as false...
1716 * and is effectively TUSB-specific.
1717 */
1718 vbus = musb_platform_get_vbus_status(musb);
1719 spin_unlock_irqrestore(&musb->lock, flags);
1720
1721 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1722 vbus ? "on" : "off", val);
1723}
1724static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1725
1726/* Gadget drivers can't know that a host is connected so they might want
1727 * to start SRP, but users can. This allows userspace to trigger SRP.
1728 */
1729static ssize_t
1730musb_srp_store(struct device *dev, struct device_attribute *attr,
1731 const char *buf, size_t n)
1732{
1733 struct musb *musb = dev_to_musb(dev);
1734 unsigned short srp;
1735
1736 if (sscanf(buf, "%hu", &srp) != 1
1737 || (srp != 1)) {
1738 dev_err(dev, "SRP: Value must be 1\n");
1739 return -EINVAL;
1740 }
1741
1742 if (srp == 1)
1743 musb_g_wakeup(musb);
1744
1745 return n;
1746}
1747static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1748
1749static struct attribute *musb_attributes[] = {
1750 &dev_attr_mode.attr,
1751 &dev_attr_vbus.attr,
1752 &dev_attr_srp.attr,
1753 NULL
1754};
1755
1756static const struct attribute_group musb_attr_group = {
1757 .attrs = musb_attributes,
1758};
1759
1760#endif /* sysfs */
1761
1762/* Only used to provide driver mode change events */
1763static void musb_irq_work(struct work_struct *data)
1764{
1765 struct musb *musb = container_of(data, struct musb, irq_work);
1766 static int old_state;
1767
1768 if (musb->xceiv->state != old_state) {
1769 old_state = musb->xceiv->state;
1770 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1771 }
1772}
1773
1774/* --------------------------------------------------------------------------
1775 * Init support
1776 */
1777
1778static struct musb *__init
1779allocate_instance(struct device *dev,
1780 struct musb_hdrc_config *config, void __iomem *mbase)
1781{
1782 struct musb *musb;
1783 struct musb_hw_ep *ep;
1784 int epnum;
1785 struct usb_hcd *hcd;
1786
1787 hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
1788 if (!hcd)
1789 return NULL;
1790 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1791
1792 musb = hcd_to_musb(hcd);
1793 INIT_LIST_HEAD(&musb->control);
1794 INIT_LIST_HEAD(&musb->in_bulk);
1795 INIT_LIST_HEAD(&musb->out_bulk);
1796
1797 hcd->uses_new_polling = 1;
1798 hcd->has_tt = 1;
1799
1800 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1801 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
1802 dev_set_drvdata(dev, musb);
1803 musb->mregs = mbase;
1804 musb->ctrl_base = mbase;
1805 musb->nIrq = -ENODEV;
1806 musb->config = config;
1807 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
1808 for (epnum = 0, ep = musb->endpoints;
1809 epnum < musb->config->num_eps;
1810 epnum++, ep++) {
1811 ep->musb = musb;
1812 ep->epnum = epnum;
1813 }
1814
1815 musb->controller = dev;
1816
1817 return musb;
1818}
1819
1820static void musb_free(struct musb *musb)
1821{
1822 /* this has multiple entry modes. it handles fault cleanup after
1823 * probe(), where things may be partially set up, as well as rmmod
1824 * cleanup after everything's been de-activated.
1825 */
1826
1827#ifdef CONFIG_SYSFS
1828 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
1829#endif
1830
1831 musb_gadget_cleanup(musb);
1832
1833 if (musb->nIrq >= 0) {
1834 if (musb->irq_wake)
1835 disable_irq_wake(musb->nIrq);
1836 free_irq(musb->nIrq, musb);
1837 }
1838 if (is_dma_capable() && musb->dma_controller) {
1839 struct dma_controller *c = musb->dma_controller;
1840
1841 (void) c->stop(c);
1842 dma_controller_destroy(c);
1843 }
1844
1845 kfree(musb);
1846}
1847
1848/*
1849 * Perform generic per-controller initialization.
1850 *
1851 * @pDevice: the controller (already clocked, etc)
1852 * @nIrq: irq
1853 * @mregs: virtual address of controller registers,
1854 * not yet corrected for platform-specific offsets
1855 */
1856static int __init
1857musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1858{
1859 int status;
1860 struct musb *musb;
1861 struct musb_hdrc_platform_data *plat = dev->platform_data;
1862
1863 /* The driver might handle more features than the board; OK.
1864 * Fail when the board needs a feature that's not enabled.
1865 */
1866 if (!plat) {
1867 dev_dbg(dev, "no platform_data?\n");
1868 status = -ENODEV;
1869 goto fail0;
1870 }
1871
1872 /* allocate */
1873 musb = allocate_instance(dev, plat->config, ctrl);
1874 if (!musb) {
1875 status = -ENOMEM;
1876 goto fail0;
1877 }
1878
1879 pm_runtime_use_autosuspend(musb->controller);
1880 pm_runtime_set_autosuspend_delay(musb->controller, 200);
1881 pm_runtime_enable(musb->controller);
1882
1883 spin_lock_init(&musb->lock);
1884 musb->board_mode = plat->mode;
1885 musb->board_set_power = plat->set_power;
1886 musb->min_power = plat->min_power;
1887 musb->ops = plat->platform_ops;
1888
1889 /* The musb_platform_init() call:
1890 * - adjusts musb->mregs and musb->isr if needed,
1891 * - may initialize an integrated tranceiver
1892 * - initializes musb->xceiv, usually by otg_get_transceiver()
1893 * - stops powering VBUS
1894 *
1895 * There are various transceiver configurations. Blackfin,
1896 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
1897 * external/discrete ones in various flavors (twl4030 family,
1898 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
1899 */
1900 musb->isr = generic_interrupt;
1901 status = musb_platform_init(musb);
1902 if (status < 0)
1903 goto fail1;
1904
1905 if (!musb->isr) {
1906 status = -ENODEV;
1907 goto fail3;
1908 }
1909
1910 if (!musb->xceiv->io_ops) {
1911 musb->xceiv->io_priv = musb->mregs;
1912 musb->xceiv->io_ops = &musb_ulpi_access;
1913 }
1914
1915#ifndef CONFIG_MUSB_PIO_ONLY
1916 if (use_dma && dev->dma_mask) {
1917 struct dma_controller *c;
1918
1919 c = dma_controller_create(musb, musb->mregs);
1920 musb->dma_controller = c;
1921 if (c)
1922 (void) c->start(c);
1923 }
1924#endif
1925 /* ideally this would be abstracted in platform setup */
1926 if (!is_dma_capable() || !musb->dma_controller)
1927 dev->dma_mask = NULL;
1928
1929 /* be sure interrupts are disabled before connecting ISR */
1930 musb_platform_disable(musb);
1931 musb_generic_disable(musb);
1932
1933 /* setup musb parts of the core (especially endpoints) */
1934 status = musb_core_init(plat->config->multipoint
1935 ? MUSB_CONTROLLER_MHDRC
1936 : MUSB_CONTROLLER_HDRC, musb);
1937 if (status < 0)
1938 goto fail3;
1939
1940 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
1941
1942 /* Init IRQ workqueue before request_irq */
1943 INIT_WORK(&musb->irq_work, musb_irq_work);
1944
1945 /* attach to the IRQ */
1946 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
1947 dev_err(dev, "request_irq %d failed!\n", nIrq);
1948 status = -ENODEV;
1949 goto fail3;
1950 }
1951 musb->nIrq = nIrq;
1952/* FIXME this handles wakeup irqs wrong */
1953 if (enable_irq_wake(nIrq) == 0) {
1954 musb->irq_wake = 1;
1955 device_init_wakeup(dev, 1);
1956 } else {
1957 musb->irq_wake = 0;
1958 }
1959
1960 /* host side needs more setup */
1961 if (is_host_enabled(musb)) {
1962 struct usb_hcd *hcd = musb_to_hcd(musb);
1963
1964 otg_set_host(musb->xceiv, &hcd->self);
1965
1966 if (is_otg_enabled(musb))
1967 hcd->self.otg_port = 1;
1968 musb->xceiv->host = &hcd->self;
1969 hcd->power_budget = 2 * (plat->power ? : 250);
1970
1971 /* program PHY to use external vBus if required */
1972 if (plat->extvbus) {
1973 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
1974 busctl |= MUSB_ULPI_USE_EXTVBUS;
1975 musb_write_ulpi_buscontrol(musb->mregs, busctl);
1976 }
1977 }
1978
1979 /* For the host-only role, we can activate right away.
1980 * (We expect the ID pin to be forcibly grounded!!)
1981 * Otherwise, wait till the gadget driver hooks up.
1982 */
1983 if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
1984 struct usb_hcd *hcd = musb_to_hcd(musb);
1985
1986 MUSB_HST_MODE(musb);
1987 musb->xceiv->default_a = 1;
1988 musb->xceiv->state = OTG_STATE_A_IDLE;
1989
1990 status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
1991
1992 hcd->self.uses_pio_for_control = 1;
1993 dev_dbg(musb->controller, "%s mode, status %d, devctl %02x %c\n",
1994 "HOST", status,
1995 musb_readb(musb->mregs, MUSB_DEVCTL),
1996 (musb_readb(musb->mregs, MUSB_DEVCTL)
1997 & MUSB_DEVCTL_BDEVICE
1998 ? 'B' : 'A'));
1999
2000 } else /* peripheral is enabled */ {
2001 MUSB_DEV_MODE(musb);
2002 musb->xceiv->default_a = 0;
2003 musb->xceiv->state = OTG_STATE_B_IDLE;
2004
2005 status = musb_gadget_setup(musb);
2006
2007 dev_dbg(musb->controller, "%s mode, status %d, dev%02x\n",
2008 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
2009 status,
2010 musb_readb(musb->mregs, MUSB_DEVCTL));
2011
2012 }
2013 if (status < 0)
2014 goto fail3;
2015
2016 pm_runtime_put(musb->controller);
2017
2018 status = musb_init_debugfs(musb);
2019 if (status < 0)
2020 goto fail4;
2021
2022#ifdef CONFIG_SYSFS
2023 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
2024 if (status)
2025 goto fail5;
2026#endif
2027
2028 dev_info(dev, "USB %s mode controller at %p using %s, IRQ %d\n",
2029 ({char *s;
2030 switch (musb->board_mode) {
2031 case MUSB_HOST: s = "Host"; break;
2032 case MUSB_PERIPHERAL: s = "Peripheral"; break;
2033 default: s = "OTG"; break;
2034 }; s; }),
2035 ctrl,
2036 (is_dma_capable() && musb->dma_controller)
2037 ? "DMA" : "PIO",
2038 musb->nIrq);
2039
2040 return 0;
2041
2042fail5:
2043 musb_exit_debugfs(musb);
2044
2045fail4:
2046 if (!is_otg_enabled(musb) && is_host_enabled(musb))
2047 usb_remove_hcd(musb_to_hcd(musb));
2048 else
2049 musb_gadget_cleanup(musb);
2050
2051fail3:
2052 if (musb->irq_wake)
2053 device_init_wakeup(dev, 0);
2054 musb_platform_exit(musb);
2055
2056fail1:
2057 dev_err(musb->controller,
2058 "musb_init_controller failed with status %d\n", status);
2059
2060 musb_free(musb);
2061
2062fail0:
2063
2064 return status;
2065
2066}
2067
2068/*-------------------------------------------------------------------------*/
2069
2070/* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2071 * bridge to a platform device; this driver then suffices.
2072 */
2073
2074#ifndef CONFIG_MUSB_PIO_ONLY
2075static u64 *orig_dma_mask;
2076#endif
2077
2078static int __init musb_probe(struct platform_device *pdev)
2079{
2080 struct device *dev = &pdev->dev;
2081 int irq = platform_get_irq_byname(pdev, "mc");
2082 int status;
2083 struct resource *iomem;
2084 void __iomem *base;
2085
2086 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2087 if (!iomem || irq <= 0)
2088 return -ENODEV;
2089
2090 base = ioremap(iomem->start, resource_size(iomem));
2091 if (!base) {
2092 dev_err(dev, "ioremap failed\n");
2093 return -ENOMEM;
2094 }
2095
2096#ifndef CONFIG_MUSB_PIO_ONLY
2097 /* clobbered by use_dma=n */
2098 orig_dma_mask = dev->dma_mask;
2099#endif
2100 status = musb_init_controller(dev, irq, base);
2101 if (status < 0)
2102 iounmap(base);
2103
2104 return status;
2105}
2106
2107static int __exit musb_remove(struct platform_device *pdev)
2108{
2109 struct musb *musb = dev_to_musb(&pdev->dev);
2110 void __iomem *ctrl_base = musb->ctrl_base;
2111
2112 /* this gets called on rmmod.
2113 * - Host mode: host may still be active
2114 * - Peripheral mode: peripheral is deactivated (or never-activated)
2115 * - OTG mode: both roles are deactivated (or never-activated)
2116 */
2117 pm_runtime_get_sync(musb->controller);
2118 musb_exit_debugfs(musb);
2119 musb_shutdown(pdev);
2120
2121 pm_runtime_put(musb->controller);
2122 musb_free(musb);
2123 iounmap(ctrl_base);
2124 device_init_wakeup(&pdev->dev, 0);
2125#ifndef CONFIG_MUSB_PIO_ONLY
2126 pdev->dev.dma_mask = orig_dma_mask;
2127#endif
2128 return 0;
2129}
2130
2131#ifdef CONFIG_PM
2132
2133static void musb_save_context(struct musb *musb)
2134{
2135 int i;
2136 void __iomem *musb_base = musb->mregs;
2137 void __iomem *epio;
2138
2139 if (is_host_enabled(musb)) {
2140 musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2141 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2142 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
2143 }
2144 musb->context.power = musb_readb(musb_base, MUSB_POWER);
2145 musb->context.intrtxe = musb_readw(musb_base, MUSB_INTRTXE);
2146 musb->context.intrrxe = musb_readw(musb_base, MUSB_INTRRXE);
2147 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2148 musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2149 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2150
2151 for (i = 0; i < musb->config->num_eps; ++i) {
2152 struct musb_hw_ep *hw_ep;
2153
2154 hw_ep = &musb->endpoints[i];
2155 if (!hw_ep)
2156 continue;
2157
2158 epio = hw_ep->regs;
2159 if (!epio)
2160 continue;
2161
2162 musb->context.index_regs[i].txmaxp =
2163 musb_readw(epio, MUSB_TXMAXP);
2164 musb->context.index_regs[i].txcsr =
2165 musb_readw(epio, MUSB_TXCSR);
2166 musb->context.index_regs[i].rxmaxp =
2167 musb_readw(epio, MUSB_RXMAXP);
2168 musb->context.index_regs[i].rxcsr =
2169 musb_readw(epio, MUSB_RXCSR);
2170
2171 if (musb->dyn_fifo) {
2172 musb->context.index_regs[i].txfifoadd =
2173 musb_read_txfifoadd(musb_base);
2174 musb->context.index_regs[i].rxfifoadd =
2175 musb_read_rxfifoadd(musb_base);
2176 musb->context.index_regs[i].txfifosz =
2177 musb_read_txfifosz(musb_base);
2178 musb->context.index_regs[i].rxfifosz =
2179 musb_read_rxfifosz(musb_base);
2180 }
2181 if (is_host_enabled(musb)) {
2182 musb->context.index_regs[i].txtype =
2183 musb_readb(epio, MUSB_TXTYPE);
2184 musb->context.index_regs[i].txinterval =
2185 musb_readb(epio, MUSB_TXINTERVAL);
2186 musb->context.index_regs[i].rxtype =
2187 musb_readb(epio, MUSB_RXTYPE);
2188 musb->context.index_regs[i].rxinterval =
2189 musb_readb(epio, MUSB_RXINTERVAL);
2190
2191 musb->context.index_regs[i].txfunaddr =
2192 musb_read_txfunaddr(musb_base, i);
2193 musb->context.index_regs[i].txhubaddr =
2194 musb_read_txhubaddr(musb_base, i);
2195 musb->context.index_regs[i].txhubport =
2196 musb_read_txhubport(musb_base, i);
2197
2198 musb->context.index_regs[i].rxfunaddr =
2199 musb_read_rxfunaddr(musb_base, i);
2200 musb->context.index_regs[i].rxhubaddr =
2201 musb_read_rxhubaddr(musb_base, i);
2202 musb->context.index_regs[i].rxhubport =
2203 musb_read_rxhubport(musb_base, i);
2204 }
2205 }
2206}
2207
2208static void musb_restore_context(struct musb *musb)
2209{
2210 int i;
2211 void __iomem *musb_base = musb->mregs;
2212 void __iomem *ep_target_regs;
2213 void __iomem *epio;
2214
2215 if (is_host_enabled(musb)) {
2216 musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2217 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2218 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
2219 }
2220 musb_writeb(musb_base, MUSB_POWER, musb->context.power);
2221 musb_writew(musb_base, MUSB_INTRTXE, musb->context.intrtxe);
2222 musb_writew(musb_base, MUSB_INTRRXE, musb->context.intrrxe);
2223 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2224 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
2225
2226 for (i = 0; i < musb->config->num_eps; ++i) {
2227 struct musb_hw_ep *hw_ep;
2228
2229 hw_ep = &musb->endpoints[i];
2230 if (!hw_ep)
2231 continue;
2232
2233 epio = hw_ep->regs;
2234 if (!epio)
2235 continue;
2236
2237 musb_writew(epio, MUSB_TXMAXP,
2238 musb->context.index_regs[i].txmaxp);
2239 musb_writew(epio, MUSB_TXCSR,
2240 musb->context.index_regs[i].txcsr);
2241 musb_writew(epio, MUSB_RXMAXP,
2242 musb->context.index_regs[i].rxmaxp);
2243 musb_writew(epio, MUSB_RXCSR,
2244 musb->context.index_regs[i].rxcsr);
2245
2246 if (musb->dyn_fifo) {
2247 musb_write_txfifosz(musb_base,
2248 musb->context.index_regs[i].txfifosz);
2249 musb_write_rxfifosz(musb_base,
2250 musb->context.index_regs[i].rxfifosz);
2251 musb_write_txfifoadd(musb_base,
2252 musb->context.index_regs[i].txfifoadd);
2253 musb_write_rxfifoadd(musb_base,
2254 musb->context.index_regs[i].rxfifoadd);
2255 }
2256
2257 if (is_host_enabled(musb)) {
2258 musb_writeb(epio, MUSB_TXTYPE,
2259 musb->context.index_regs[i].txtype);
2260 musb_writeb(epio, MUSB_TXINTERVAL,
2261 musb->context.index_regs[i].txinterval);
2262 musb_writeb(epio, MUSB_RXTYPE,
2263 musb->context.index_regs[i].rxtype);
2264 musb_writeb(epio, MUSB_RXINTERVAL,
2265
2266 musb->context.index_regs[i].rxinterval);
2267 musb_write_txfunaddr(musb_base, i,
2268 musb->context.index_regs[i].txfunaddr);
2269 musb_write_txhubaddr(musb_base, i,
2270 musb->context.index_regs[i].txhubaddr);
2271 musb_write_txhubport(musb_base, i,
2272 musb->context.index_regs[i].txhubport);
2273
2274 ep_target_regs =
2275 musb_read_target_reg_base(i, musb_base);
2276
2277 musb_write_rxfunaddr(ep_target_regs,
2278 musb->context.index_regs[i].rxfunaddr);
2279 musb_write_rxhubaddr(ep_target_regs,
2280 musb->context.index_regs[i].rxhubaddr);
2281 musb_write_rxhubport(ep_target_regs,
2282 musb->context.index_regs[i].rxhubport);
2283 }
2284 }
2285 musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
2286}
2287
2288static int musb_suspend(struct device *dev)
2289{
2290 struct musb *musb = dev_to_musb(dev);
2291 unsigned long flags;
2292
2293 spin_lock_irqsave(&musb->lock, flags);
2294
2295 if (is_peripheral_active(musb)) {
2296 /* FIXME force disconnect unless we know USB will wake
2297 * the system up quickly enough to respond ...
2298 */
2299 } else if (is_host_active(musb)) {
2300 /* we know all the children are suspended; sometimes
2301 * they will even be wakeup-enabled.
2302 */
2303 }
2304
2305 musb_save_context(musb);
2306
2307 spin_unlock_irqrestore(&musb->lock, flags);
2308 return 0;
2309}
2310
2311static int musb_resume_noirq(struct device *dev)
2312{
2313 struct musb *musb = dev_to_musb(dev);
2314
2315 musb_restore_context(musb);
2316
2317 /* for static cmos like DaVinci, register values were preserved
2318 * unless for some reason the whole soc powered down or the USB
2319 * module got reset through the PSC (vs just being disabled).
2320 */
2321 return 0;
2322}
2323
2324static int musb_runtime_suspend(struct device *dev)
2325{
2326 struct musb *musb = dev_to_musb(dev);
2327
2328 musb_save_context(musb);
2329
2330 return 0;
2331}
2332
2333static int musb_runtime_resume(struct device *dev)
2334{
2335 struct musb *musb = dev_to_musb(dev);
2336 static int first = 1;
2337
2338 /*
2339 * When pm_runtime_get_sync called for the first time in driver
2340 * init, some of the structure is still not initialized which is
2341 * used in restore function. But clock needs to be
2342 * enabled before any register access, so
2343 * pm_runtime_get_sync has to be called.
2344 * Also context restore without save does not make
2345 * any sense
2346 */
2347 if (!first)
2348 musb_restore_context(musb);
2349 first = 0;
2350
2351 return 0;
2352}
2353
2354static const struct dev_pm_ops musb_dev_pm_ops = {
2355 .suspend = musb_suspend,
2356 .resume_noirq = musb_resume_noirq,
2357 .runtime_suspend = musb_runtime_suspend,
2358 .runtime_resume = musb_runtime_resume,
2359};
2360
2361#define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2362#else
2363#define MUSB_DEV_PM_OPS NULL
2364#endif
2365
2366static struct platform_driver musb_driver = {
2367 .driver = {
2368 .name = (char *)musb_driver_name,
2369 .bus = &platform_bus_type,
2370 .owner = THIS_MODULE,
2371 .pm = MUSB_DEV_PM_OPS,
2372 },
2373 .remove = __exit_p(musb_remove),
2374 .shutdown = musb_shutdown,
2375};
2376
2377/*-------------------------------------------------------------------------*/
2378
2379static int __init musb_init(void)
2380{
2381 if (usb_disabled())
2382 return 0;
2383
2384 pr_info("%s: version " MUSB_VERSION ", "
2385 "?dma?"
2386 ", "
2387 "otg (peripheral+host)",
2388 musb_driver_name);
2389 return platform_driver_probe(&musb_driver, musb_probe);
2390}
2391
2392/* make us init after usbcore and i2c (transceivers, regulators, etc)
2393 * and before usb gadget and host-side drivers start to register
2394 */
2395fs_initcall(musb_init);
2396
2397static void __exit musb_cleanup(void)
2398{
2399 platform_driver_unregister(&musb_driver);
2400}
2401module_exit(musb_cleanup);