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1/*
2 * Driver for Cirrus Logic EP93xx SPI controller.
3 *
4 * Copyright (C) 2010-2011 Mika Westerberg
5 *
6 * Explicit FIFO handling code was inspired by amba-pl022 driver.
7 *
8 * Chip select support using other than built-in GPIOs by H. Hartley Sweeten.
9 *
10 * For more information about the SPI controller see documentation on Cirrus
11 * Logic web site:
12 * http://www.cirrus.com/en/pubs/manual/EP93xx_Users_Guide_UM1.pdf
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
19#include <linux/io.h>
20#include <linux/clk.h>
21#include <linux/err.h>
22#include <linux/delay.h>
23#include <linux/device.h>
24#include <linux/dmaengine.h>
25#include <linux/bitops.h>
26#include <linux/interrupt.h>
27#include <linux/module.h>
28#include <linux/platform_device.h>
29#include <linux/sched.h>
30#include <linux/scatterlist.h>
31#include <linux/spi/spi.h>
32
33#include <linux/platform_data/dma-ep93xx.h>
34#include <linux/platform_data/spi-ep93xx.h>
35
36#define SSPCR0 0x0000
37#define SSPCR0_MODE_SHIFT 6
38#define SSPCR0_SCR_SHIFT 8
39
40#define SSPCR1 0x0004
41#define SSPCR1_RIE BIT(0)
42#define SSPCR1_TIE BIT(1)
43#define SSPCR1_RORIE BIT(2)
44#define SSPCR1_LBM BIT(3)
45#define SSPCR1_SSE BIT(4)
46#define SSPCR1_MS BIT(5)
47#define SSPCR1_SOD BIT(6)
48
49#define SSPDR 0x0008
50
51#define SSPSR 0x000c
52#define SSPSR_TFE BIT(0)
53#define SSPSR_TNF BIT(1)
54#define SSPSR_RNE BIT(2)
55#define SSPSR_RFF BIT(3)
56#define SSPSR_BSY BIT(4)
57#define SSPCPSR 0x0010
58
59#define SSPIIR 0x0014
60#define SSPIIR_RIS BIT(0)
61#define SSPIIR_TIS BIT(1)
62#define SSPIIR_RORIS BIT(2)
63#define SSPICR SSPIIR
64
65/* timeout in milliseconds */
66#define SPI_TIMEOUT 5
67/* maximum depth of RX/TX FIFO */
68#define SPI_FIFO_SIZE 8
69
70/**
71 * struct ep93xx_spi - EP93xx SPI controller structure
72 * @pdev: pointer to platform device
73 * @clk: clock for the controller
74 * @regs_base: pointer to ioremap()'d registers
75 * @sspdr_phys: physical address of the SSPDR register
76 * @wait: wait here until given transfer is completed
77 * @current_msg: message that is currently processed (or %NULL if none)
78 * @tx: current byte in transfer to transmit
79 * @rx: current byte in transfer to receive
80 * @fifo_level: how full is FIFO (%0..%SPI_FIFO_SIZE - %1). Receiving one
81 * frame decreases this level and sending one frame increases it.
82 * @dma_rx: RX DMA channel
83 * @dma_tx: TX DMA channel
84 * @dma_rx_data: RX parameters passed to the DMA engine
85 * @dma_tx_data: TX parameters passed to the DMA engine
86 * @rx_sgt: sg table for RX transfers
87 * @tx_sgt: sg table for TX transfers
88 * @zeropage: dummy page used as RX buffer when only TX buffer is passed in by
89 * the client
90 */
91struct ep93xx_spi {
92 const struct platform_device *pdev;
93 struct clk *clk;
94 void __iomem *regs_base;
95 unsigned long sspdr_phys;
96 struct completion wait;
97 struct spi_message *current_msg;
98 size_t tx;
99 size_t rx;
100 size_t fifo_level;
101 struct dma_chan *dma_rx;
102 struct dma_chan *dma_tx;
103 struct ep93xx_dma_data dma_rx_data;
104 struct ep93xx_dma_data dma_tx_data;
105 struct sg_table rx_sgt;
106 struct sg_table tx_sgt;
107 void *zeropage;
108};
109
110/**
111 * struct ep93xx_spi_chip - SPI device hardware settings
112 * @spi: back pointer to the SPI device
113 * @ops: private chip operations
114 */
115struct ep93xx_spi_chip {
116 const struct spi_device *spi;
117 struct ep93xx_spi_chip_ops *ops;
118};
119
120/* converts bits per word to CR0.DSS value */
121#define bits_per_word_to_dss(bpw) ((bpw) - 1)
122
123static void ep93xx_spi_write_u8(const struct ep93xx_spi *espi,
124 u16 reg, u8 value)
125{
126 writeb(value, espi->regs_base + reg);
127}
128
129static u8 ep93xx_spi_read_u8(const struct ep93xx_spi *spi, u16 reg)
130{
131 return readb(spi->regs_base + reg);
132}
133
134static void ep93xx_spi_write_u16(const struct ep93xx_spi *espi,
135 u16 reg, u16 value)
136{
137 writew(value, espi->regs_base + reg);
138}
139
140static u16 ep93xx_spi_read_u16(const struct ep93xx_spi *spi, u16 reg)
141{
142 return readw(spi->regs_base + reg);
143}
144
145static int ep93xx_spi_enable(const struct ep93xx_spi *espi)
146{
147 u8 regval;
148 int err;
149
150 err = clk_enable(espi->clk);
151 if (err)
152 return err;
153
154 regval = ep93xx_spi_read_u8(espi, SSPCR1);
155 regval |= SSPCR1_SSE;
156 ep93xx_spi_write_u8(espi, SSPCR1, regval);
157
158 return 0;
159}
160
161static void ep93xx_spi_disable(const struct ep93xx_spi *espi)
162{
163 u8 regval;
164
165 regval = ep93xx_spi_read_u8(espi, SSPCR1);
166 regval &= ~SSPCR1_SSE;
167 ep93xx_spi_write_u8(espi, SSPCR1, regval);
168
169 clk_disable(espi->clk);
170}
171
172static void ep93xx_spi_enable_interrupts(const struct ep93xx_spi *espi)
173{
174 u8 regval;
175
176 regval = ep93xx_spi_read_u8(espi, SSPCR1);
177 regval |= (SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE);
178 ep93xx_spi_write_u8(espi, SSPCR1, regval);
179}
180
181static void ep93xx_spi_disable_interrupts(const struct ep93xx_spi *espi)
182{
183 u8 regval;
184
185 regval = ep93xx_spi_read_u8(espi, SSPCR1);
186 regval &= ~(SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE);
187 ep93xx_spi_write_u8(espi, SSPCR1, regval);
188}
189
190/**
191 * ep93xx_spi_calc_divisors() - calculates SPI clock divisors
192 * @espi: ep93xx SPI controller struct
193 * @rate: desired SPI output clock rate
194 * @div_cpsr: pointer to return the cpsr (pre-scaler) divider
195 * @div_scr: pointer to return the scr divider
196 */
197static int ep93xx_spi_calc_divisors(const struct ep93xx_spi *espi,
198 u32 rate, u8 *div_cpsr, u8 *div_scr)
199{
200 struct spi_master *master = platform_get_drvdata(espi->pdev);
201 unsigned long spi_clk_rate = clk_get_rate(espi->clk);
202 int cpsr, scr;
203
204 /*
205 * Make sure that max value is between values supported by the
206 * controller. Note that minimum value is already checked in
207 * ep93xx_spi_transfer_one_message().
208 */
209 rate = clamp(rate, master->min_speed_hz, master->max_speed_hz);
210
211 /*
212 * Calculate divisors so that we can get speed according the
213 * following formula:
214 * rate = spi_clock_rate / (cpsr * (1 + scr))
215 *
216 * cpsr must be even number and starts from 2, scr can be any number
217 * between 0 and 255.
218 */
219 for (cpsr = 2; cpsr <= 254; cpsr += 2) {
220 for (scr = 0; scr <= 255; scr++) {
221 if ((spi_clk_rate / (cpsr * (scr + 1))) <= rate) {
222 *div_scr = (u8)scr;
223 *div_cpsr = (u8)cpsr;
224 return 0;
225 }
226 }
227 }
228
229 return -EINVAL;
230}
231
232static void ep93xx_spi_cs_control(struct spi_device *spi, bool control)
233{
234 struct ep93xx_spi_chip *chip = spi_get_ctldata(spi);
235 int value = (spi->mode & SPI_CS_HIGH) ? control : !control;
236
237 if (chip->ops && chip->ops->cs_control)
238 chip->ops->cs_control(spi, value);
239}
240
241/**
242 * ep93xx_spi_setup() - setup an SPI device
243 * @spi: SPI device to setup
244 *
245 * This function sets up SPI device mode, speed etc. Can be called multiple
246 * times for a single device. Returns %0 in case of success, negative error in
247 * case of failure. When this function returns success, the device is
248 * deselected.
249 */
250static int ep93xx_spi_setup(struct spi_device *spi)
251{
252 struct ep93xx_spi *espi = spi_master_get_devdata(spi->master);
253 struct ep93xx_spi_chip *chip;
254
255 chip = spi_get_ctldata(spi);
256 if (!chip) {
257 dev_dbg(&espi->pdev->dev, "initial setup for %s\n",
258 spi->modalias);
259
260 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
261 if (!chip)
262 return -ENOMEM;
263
264 chip->spi = spi;
265 chip->ops = spi->controller_data;
266
267 if (chip->ops && chip->ops->setup) {
268 int ret = chip->ops->setup(spi);
269
270 if (ret) {
271 kfree(chip);
272 return ret;
273 }
274 }
275
276 spi_set_ctldata(spi, chip);
277 }
278
279 ep93xx_spi_cs_control(spi, false);
280 return 0;
281}
282
283/**
284 * ep93xx_spi_cleanup() - cleans up master controller specific state
285 * @spi: SPI device to cleanup
286 *
287 * This function releases master controller specific state for given @spi
288 * device.
289 */
290static void ep93xx_spi_cleanup(struct spi_device *spi)
291{
292 struct ep93xx_spi_chip *chip;
293
294 chip = spi_get_ctldata(spi);
295 if (chip) {
296 if (chip->ops && chip->ops->cleanup)
297 chip->ops->cleanup(spi);
298 spi_set_ctldata(spi, NULL);
299 kfree(chip);
300 }
301}
302
303/**
304 * ep93xx_spi_chip_setup() - configures hardware according to given @chip
305 * @espi: ep93xx SPI controller struct
306 * @chip: chip specific settings
307 * @speed_hz: transfer speed
308 * @bits_per_word: transfer bits_per_word
309 */
310static int ep93xx_spi_chip_setup(const struct ep93xx_spi *espi,
311 const struct ep93xx_spi_chip *chip,
312 u32 speed_hz, u8 bits_per_word)
313{
314 u8 dss = bits_per_word_to_dss(bits_per_word);
315 u8 div_cpsr = 0;
316 u8 div_scr = 0;
317 u16 cr0;
318 int err;
319
320 err = ep93xx_spi_calc_divisors(espi, speed_hz, &div_cpsr, &div_scr);
321 if (err)
322 return err;
323
324 cr0 = div_scr << SSPCR0_SCR_SHIFT;
325 cr0 |= (chip->spi->mode & (SPI_CPHA|SPI_CPOL)) << SSPCR0_MODE_SHIFT;
326 cr0 |= dss;
327
328 dev_dbg(&espi->pdev->dev, "setup: mode %d, cpsr %d, scr %d, dss %d\n",
329 chip->spi->mode, div_cpsr, div_scr, dss);
330 dev_dbg(&espi->pdev->dev, "setup: cr0 %#x\n", cr0);
331
332 ep93xx_spi_write_u8(espi, SSPCPSR, div_cpsr);
333 ep93xx_spi_write_u16(espi, SSPCR0, cr0);
334
335 return 0;
336}
337
338static void ep93xx_do_write(struct ep93xx_spi *espi, struct spi_transfer *t)
339{
340 if (t->bits_per_word > 8) {
341 u16 tx_val = 0;
342
343 if (t->tx_buf)
344 tx_val = ((u16 *)t->tx_buf)[espi->tx];
345 ep93xx_spi_write_u16(espi, SSPDR, tx_val);
346 espi->tx += sizeof(tx_val);
347 } else {
348 u8 tx_val = 0;
349
350 if (t->tx_buf)
351 tx_val = ((u8 *)t->tx_buf)[espi->tx];
352 ep93xx_spi_write_u8(espi, SSPDR, tx_val);
353 espi->tx += sizeof(tx_val);
354 }
355}
356
357static void ep93xx_do_read(struct ep93xx_spi *espi, struct spi_transfer *t)
358{
359 if (t->bits_per_word > 8) {
360 u16 rx_val;
361
362 rx_val = ep93xx_spi_read_u16(espi, SSPDR);
363 if (t->rx_buf)
364 ((u16 *)t->rx_buf)[espi->rx] = rx_val;
365 espi->rx += sizeof(rx_val);
366 } else {
367 u8 rx_val;
368
369 rx_val = ep93xx_spi_read_u8(espi, SSPDR);
370 if (t->rx_buf)
371 ((u8 *)t->rx_buf)[espi->rx] = rx_val;
372 espi->rx += sizeof(rx_val);
373 }
374}
375
376/**
377 * ep93xx_spi_read_write() - perform next RX/TX transfer
378 * @espi: ep93xx SPI controller struct
379 *
380 * This function transfers next bytes (or half-words) to/from RX/TX FIFOs. If
381 * called several times, the whole transfer will be completed. Returns
382 * %-EINPROGRESS when current transfer was not yet completed otherwise %0.
383 *
384 * When this function is finished, RX FIFO should be empty and TX FIFO should be
385 * full.
386 */
387static int ep93xx_spi_read_write(struct ep93xx_spi *espi)
388{
389 struct spi_message *msg = espi->current_msg;
390 struct spi_transfer *t = msg->state;
391
392 /* read as long as RX FIFO has frames in it */
393 while ((ep93xx_spi_read_u8(espi, SSPSR) & SSPSR_RNE)) {
394 ep93xx_do_read(espi, t);
395 espi->fifo_level--;
396 }
397
398 /* write as long as TX FIFO has room */
399 while (espi->fifo_level < SPI_FIFO_SIZE && espi->tx < t->len) {
400 ep93xx_do_write(espi, t);
401 espi->fifo_level++;
402 }
403
404 if (espi->rx == t->len)
405 return 0;
406
407 return -EINPROGRESS;
408}
409
410static void ep93xx_spi_pio_transfer(struct ep93xx_spi *espi)
411{
412 /*
413 * Now everything is set up for the current transfer. We prime the TX
414 * FIFO, enable interrupts, and wait for the transfer to complete.
415 */
416 if (ep93xx_spi_read_write(espi)) {
417 ep93xx_spi_enable_interrupts(espi);
418 wait_for_completion(&espi->wait);
419 }
420}
421
422/**
423 * ep93xx_spi_dma_prepare() - prepares a DMA transfer
424 * @espi: ep93xx SPI controller struct
425 * @dir: DMA transfer direction
426 *
427 * Function configures the DMA, maps the buffer and prepares the DMA
428 * descriptor. Returns a valid DMA descriptor in case of success and ERR_PTR
429 * in case of failure.
430 */
431static struct dma_async_tx_descriptor *
432ep93xx_spi_dma_prepare(struct ep93xx_spi *espi, enum dma_transfer_direction dir)
433{
434 struct spi_transfer *t = espi->current_msg->state;
435 struct dma_async_tx_descriptor *txd;
436 enum dma_slave_buswidth buswidth;
437 struct dma_slave_config conf;
438 struct scatterlist *sg;
439 struct sg_table *sgt;
440 struct dma_chan *chan;
441 const void *buf, *pbuf;
442 size_t len = t->len;
443 int i, ret, nents;
444
445 if (t->bits_per_word > 8)
446 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
447 else
448 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
449
450 memset(&conf, 0, sizeof(conf));
451 conf.direction = dir;
452
453 if (dir == DMA_DEV_TO_MEM) {
454 chan = espi->dma_rx;
455 buf = t->rx_buf;
456 sgt = &espi->rx_sgt;
457
458 conf.src_addr = espi->sspdr_phys;
459 conf.src_addr_width = buswidth;
460 } else {
461 chan = espi->dma_tx;
462 buf = t->tx_buf;
463 sgt = &espi->tx_sgt;
464
465 conf.dst_addr = espi->sspdr_phys;
466 conf.dst_addr_width = buswidth;
467 }
468
469 ret = dmaengine_slave_config(chan, &conf);
470 if (ret)
471 return ERR_PTR(ret);
472
473 /*
474 * We need to split the transfer into PAGE_SIZE'd chunks. This is
475 * because we are using @espi->zeropage to provide a zero RX buffer
476 * for the TX transfers and we have only allocated one page for that.
477 *
478 * For performance reasons we allocate a new sg_table only when
479 * needed. Otherwise we will re-use the current one. Eventually the
480 * last sg_table is released in ep93xx_spi_release_dma().
481 */
482
483 nents = DIV_ROUND_UP(len, PAGE_SIZE);
484 if (nents != sgt->nents) {
485 sg_free_table(sgt);
486
487 ret = sg_alloc_table(sgt, nents, GFP_KERNEL);
488 if (ret)
489 return ERR_PTR(ret);
490 }
491
492 pbuf = buf;
493 for_each_sg(sgt->sgl, sg, sgt->nents, i) {
494 size_t bytes = min_t(size_t, len, PAGE_SIZE);
495
496 if (buf) {
497 sg_set_page(sg, virt_to_page(pbuf), bytes,
498 offset_in_page(pbuf));
499 } else {
500 sg_set_page(sg, virt_to_page(espi->zeropage),
501 bytes, 0);
502 }
503
504 pbuf += bytes;
505 len -= bytes;
506 }
507
508 if (WARN_ON(len)) {
509 dev_warn(&espi->pdev->dev, "len = %zu expected 0!\n", len);
510 return ERR_PTR(-EINVAL);
511 }
512
513 nents = dma_map_sg(chan->device->dev, sgt->sgl, sgt->nents, dir);
514 if (!nents)
515 return ERR_PTR(-ENOMEM);
516
517 txd = dmaengine_prep_slave_sg(chan, sgt->sgl, nents, dir, DMA_CTRL_ACK);
518 if (!txd) {
519 dma_unmap_sg(chan->device->dev, sgt->sgl, sgt->nents, dir);
520 return ERR_PTR(-ENOMEM);
521 }
522 return txd;
523}
524
525/**
526 * ep93xx_spi_dma_finish() - finishes with a DMA transfer
527 * @espi: ep93xx SPI controller struct
528 * @dir: DMA transfer direction
529 *
530 * Function finishes with the DMA transfer. After this, the DMA buffer is
531 * unmapped.
532 */
533static void ep93xx_spi_dma_finish(struct ep93xx_spi *espi,
534 enum dma_transfer_direction dir)
535{
536 struct dma_chan *chan;
537 struct sg_table *sgt;
538
539 if (dir == DMA_DEV_TO_MEM) {
540 chan = espi->dma_rx;
541 sgt = &espi->rx_sgt;
542 } else {
543 chan = espi->dma_tx;
544 sgt = &espi->tx_sgt;
545 }
546
547 dma_unmap_sg(chan->device->dev, sgt->sgl, sgt->nents, dir);
548}
549
550static void ep93xx_spi_dma_callback(void *callback_param)
551{
552 complete(callback_param);
553}
554
555static void ep93xx_spi_dma_transfer(struct ep93xx_spi *espi)
556{
557 struct spi_message *msg = espi->current_msg;
558 struct dma_async_tx_descriptor *rxd, *txd;
559
560 rxd = ep93xx_spi_dma_prepare(espi, DMA_DEV_TO_MEM);
561 if (IS_ERR(rxd)) {
562 dev_err(&espi->pdev->dev, "DMA RX failed: %ld\n", PTR_ERR(rxd));
563 msg->status = PTR_ERR(rxd);
564 return;
565 }
566
567 txd = ep93xx_spi_dma_prepare(espi, DMA_MEM_TO_DEV);
568 if (IS_ERR(txd)) {
569 ep93xx_spi_dma_finish(espi, DMA_DEV_TO_MEM);
570 dev_err(&espi->pdev->dev, "DMA TX failed: %ld\n", PTR_ERR(rxd));
571 msg->status = PTR_ERR(txd);
572 return;
573 }
574
575 /* We are ready when RX is done */
576 rxd->callback = ep93xx_spi_dma_callback;
577 rxd->callback_param = &espi->wait;
578
579 /* Now submit both descriptors and wait while they finish */
580 dmaengine_submit(rxd);
581 dmaengine_submit(txd);
582
583 dma_async_issue_pending(espi->dma_rx);
584 dma_async_issue_pending(espi->dma_tx);
585
586 wait_for_completion(&espi->wait);
587
588 ep93xx_spi_dma_finish(espi, DMA_MEM_TO_DEV);
589 ep93xx_spi_dma_finish(espi, DMA_DEV_TO_MEM);
590}
591
592/**
593 * ep93xx_spi_process_transfer() - processes one SPI transfer
594 * @espi: ep93xx SPI controller struct
595 * @msg: current message
596 * @t: transfer to process
597 *
598 * This function processes one SPI transfer given in @t. Function waits until
599 * transfer is complete (may sleep) and updates @msg->status based on whether
600 * transfer was successfully processed or not.
601 */
602static void ep93xx_spi_process_transfer(struct ep93xx_spi *espi,
603 struct spi_message *msg,
604 struct spi_transfer *t)
605{
606 struct ep93xx_spi_chip *chip = spi_get_ctldata(msg->spi);
607 int err;
608
609 msg->state = t;
610
611 err = ep93xx_spi_chip_setup(espi, chip, t->speed_hz, t->bits_per_word);
612 if (err) {
613 dev_err(&espi->pdev->dev,
614 "failed to setup chip for transfer\n");
615 msg->status = err;
616 return;
617 }
618
619 espi->rx = 0;
620 espi->tx = 0;
621
622 /*
623 * There is no point of setting up DMA for the transfers which will
624 * fit into the FIFO and can be transferred with a single interrupt.
625 * So in these cases we will be using PIO and don't bother for DMA.
626 */
627 if (espi->dma_rx && t->len > SPI_FIFO_SIZE)
628 ep93xx_spi_dma_transfer(espi);
629 else
630 ep93xx_spi_pio_transfer(espi);
631
632 /*
633 * In case of error during transmit, we bail out from processing
634 * the message.
635 */
636 if (msg->status)
637 return;
638
639 msg->actual_length += t->len;
640
641 /*
642 * After this transfer is finished, perform any possible
643 * post-transfer actions requested by the protocol driver.
644 */
645 if (t->delay_usecs) {
646 set_current_state(TASK_UNINTERRUPTIBLE);
647 schedule_timeout(usecs_to_jiffies(t->delay_usecs));
648 }
649 if (t->cs_change) {
650 if (!list_is_last(&t->transfer_list, &msg->transfers)) {
651 /*
652 * In case protocol driver is asking us to drop the
653 * chipselect briefly, we let the scheduler to handle
654 * any "delay" here.
655 */
656 ep93xx_spi_cs_control(msg->spi, false);
657 cond_resched();
658 ep93xx_spi_cs_control(msg->spi, true);
659 }
660 }
661}
662
663/*
664 * ep93xx_spi_process_message() - process one SPI message
665 * @espi: ep93xx SPI controller struct
666 * @msg: message to process
667 *
668 * This function processes a single SPI message. We go through all transfers in
669 * the message and pass them to ep93xx_spi_process_transfer(). Chipselect is
670 * asserted during the whole message (unless per transfer cs_change is set).
671 *
672 * @msg->status contains %0 in case of success or negative error code in case of
673 * failure.
674 */
675static void ep93xx_spi_process_message(struct ep93xx_spi *espi,
676 struct spi_message *msg)
677{
678 unsigned long timeout;
679 struct spi_transfer *t;
680 int err;
681
682 /*
683 * Enable the SPI controller and its clock.
684 */
685 err = ep93xx_spi_enable(espi);
686 if (err) {
687 dev_err(&espi->pdev->dev, "failed to enable SPI controller\n");
688 msg->status = err;
689 return;
690 }
691
692 /*
693 * Just to be sure: flush any data from RX FIFO.
694 */
695 timeout = jiffies + msecs_to_jiffies(SPI_TIMEOUT);
696 while (ep93xx_spi_read_u16(espi, SSPSR) & SSPSR_RNE) {
697 if (time_after(jiffies, timeout)) {
698 dev_warn(&espi->pdev->dev,
699 "timeout while flushing RX FIFO\n");
700 msg->status = -ETIMEDOUT;
701 return;
702 }
703 ep93xx_spi_read_u16(espi, SSPDR);
704 }
705
706 /*
707 * We explicitly handle FIFO level. This way we don't have to check TX
708 * FIFO status using %SSPSR_TNF bit which may cause RX FIFO overruns.
709 */
710 espi->fifo_level = 0;
711
712 /*
713 * Assert the chipselect.
714 */
715 ep93xx_spi_cs_control(msg->spi, true);
716
717 list_for_each_entry(t, &msg->transfers, transfer_list) {
718 ep93xx_spi_process_transfer(espi, msg, t);
719 if (msg->status)
720 break;
721 }
722
723 /*
724 * Now the whole message is transferred (or failed for some reason). We
725 * deselect the device and disable the SPI controller.
726 */
727 ep93xx_spi_cs_control(msg->spi, false);
728 ep93xx_spi_disable(espi);
729}
730
731static int ep93xx_spi_transfer_one_message(struct spi_master *master,
732 struct spi_message *msg)
733{
734 struct ep93xx_spi *espi = spi_master_get_devdata(master);
735
736 msg->state = NULL;
737 msg->status = 0;
738 msg->actual_length = 0;
739
740 espi->current_msg = msg;
741 ep93xx_spi_process_message(espi, msg);
742 espi->current_msg = NULL;
743
744 spi_finalize_current_message(master);
745
746 return 0;
747}
748
749static irqreturn_t ep93xx_spi_interrupt(int irq, void *dev_id)
750{
751 struct ep93xx_spi *espi = dev_id;
752 u8 irq_status = ep93xx_spi_read_u8(espi, SSPIIR);
753
754 /*
755 * If we got ROR (receive overrun) interrupt we know that something is
756 * wrong. Just abort the message.
757 */
758 if (unlikely(irq_status & SSPIIR_RORIS)) {
759 /* clear the overrun interrupt */
760 ep93xx_spi_write_u8(espi, SSPICR, 0);
761 dev_warn(&espi->pdev->dev,
762 "receive overrun, aborting the message\n");
763 espi->current_msg->status = -EIO;
764 } else {
765 /*
766 * Interrupt is either RX (RIS) or TX (TIS). For both cases we
767 * simply execute next data transfer.
768 */
769 if (ep93xx_spi_read_write(espi)) {
770 /*
771 * In normal case, there still is some processing left
772 * for current transfer. Let's wait for the next
773 * interrupt then.
774 */
775 return IRQ_HANDLED;
776 }
777 }
778
779 /*
780 * Current transfer is finished, either with error or with success. In
781 * any case we disable interrupts and notify the worker to handle
782 * any post-processing of the message.
783 */
784 ep93xx_spi_disable_interrupts(espi);
785 complete(&espi->wait);
786 return IRQ_HANDLED;
787}
788
789static bool ep93xx_spi_dma_filter(struct dma_chan *chan, void *filter_param)
790{
791 if (ep93xx_dma_chan_is_m2p(chan))
792 return false;
793
794 chan->private = filter_param;
795 return true;
796}
797
798static int ep93xx_spi_setup_dma(struct ep93xx_spi *espi)
799{
800 dma_cap_mask_t mask;
801 int ret;
802
803 espi->zeropage = (void *)get_zeroed_page(GFP_KERNEL);
804 if (!espi->zeropage)
805 return -ENOMEM;
806
807 dma_cap_zero(mask);
808 dma_cap_set(DMA_SLAVE, mask);
809
810 espi->dma_rx_data.port = EP93XX_DMA_SSP;
811 espi->dma_rx_data.direction = DMA_DEV_TO_MEM;
812 espi->dma_rx_data.name = "ep93xx-spi-rx";
813
814 espi->dma_rx = dma_request_channel(mask, ep93xx_spi_dma_filter,
815 &espi->dma_rx_data);
816 if (!espi->dma_rx) {
817 ret = -ENODEV;
818 goto fail_free_page;
819 }
820
821 espi->dma_tx_data.port = EP93XX_DMA_SSP;
822 espi->dma_tx_data.direction = DMA_MEM_TO_DEV;
823 espi->dma_tx_data.name = "ep93xx-spi-tx";
824
825 espi->dma_tx = dma_request_channel(mask, ep93xx_spi_dma_filter,
826 &espi->dma_tx_data);
827 if (!espi->dma_tx) {
828 ret = -ENODEV;
829 goto fail_release_rx;
830 }
831
832 return 0;
833
834fail_release_rx:
835 dma_release_channel(espi->dma_rx);
836 espi->dma_rx = NULL;
837fail_free_page:
838 free_page((unsigned long)espi->zeropage);
839
840 return ret;
841}
842
843static void ep93xx_spi_release_dma(struct ep93xx_spi *espi)
844{
845 if (espi->dma_rx) {
846 dma_release_channel(espi->dma_rx);
847 sg_free_table(&espi->rx_sgt);
848 }
849 if (espi->dma_tx) {
850 dma_release_channel(espi->dma_tx);
851 sg_free_table(&espi->tx_sgt);
852 }
853
854 if (espi->zeropage)
855 free_page((unsigned long)espi->zeropage);
856}
857
858static int ep93xx_spi_probe(struct platform_device *pdev)
859{
860 struct spi_master *master;
861 struct ep93xx_spi_info *info;
862 struct ep93xx_spi *espi;
863 struct resource *res;
864 int irq;
865 int error;
866
867 info = dev_get_platdata(&pdev->dev);
868
869 irq = platform_get_irq(pdev, 0);
870 if (irq < 0) {
871 dev_err(&pdev->dev, "failed to get irq resources\n");
872 return -EBUSY;
873 }
874
875 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
876 if (!res) {
877 dev_err(&pdev->dev, "unable to get iomem resource\n");
878 return -ENODEV;
879 }
880
881 master = spi_alloc_master(&pdev->dev, sizeof(*espi));
882 if (!master)
883 return -ENOMEM;
884
885 master->setup = ep93xx_spi_setup;
886 master->transfer_one_message = ep93xx_spi_transfer_one_message;
887 master->cleanup = ep93xx_spi_cleanup;
888 master->bus_num = pdev->id;
889 master->num_chipselect = info->num_chipselect;
890 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
891 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
892
893 platform_set_drvdata(pdev, master);
894
895 espi = spi_master_get_devdata(master);
896
897 espi->clk = devm_clk_get(&pdev->dev, NULL);
898 if (IS_ERR(espi->clk)) {
899 dev_err(&pdev->dev, "unable to get spi clock\n");
900 error = PTR_ERR(espi->clk);
901 goto fail_release_master;
902 }
903
904 init_completion(&espi->wait);
905
906 /*
907 * Calculate maximum and minimum supported clock rates
908 * for the controller.
909 */
910 master->max_speed_hz = clk_get_rate(espi->clk) / 2;
911 master->min_speed_hz = clk_get_rate(espi->clk) / (254 * 256);
912 espi->pdev = pdev;
913
914 espi->sspdr_phys = res->start + SSPDR;
915
916 espi->regs_base = devm_ioremap_resource(&pdev->dev, res);
917 if (IS_ERR(espi->regs_base)) {
918 error = PTR_ERR(espi->regs_base);
919 goto fail_release_master;
920 }
921
922 error = devm_request_irq(&pdev->dev, irq, ep93xx_spi_interrupt,
923 0, "ep93xx-spi", espi);
924 if (error) {
925 dev_err(&pdev->dev, "failed to request irq\n");
926 goto fail_release_master;
927 }
928
929 if (info->use_dma && ep93xx_spi_setup_dma(espi))
930 dev_warn(&pdev->dev, "DMA setup failed. Falling back to PIO\n");
931
932 /* make sure that the hardware is disabled */
933 ep93xx_spi_write_u8(espi, SSPCR1, 0);
934
935 error = devm_spi_register_master(&pdev->dev, master);
936 if (error) {
937 dev_err(&pdev->dev, "failed to register SPI master\n");
938 goto fail_free_dma;
939 }
940
941 dev_info(&pdev->dev, "EP93xx SPI Controller at 0x%08lx irq %d\n",
942 (unsigned long)res->start, irq);
943
944 return 0;
945
946fail_free_dma:
947 ep93xx_spi_release_dma(espi);
948fail_release_master:
949 spi_master_put(master);
950
951 return error;
952}
953
954static int ep93xx_spi_remove(struct platform_device *pdev)
955{
956 struct spi_master *master = platform_get_drvdata(pdev);
957 struct ep93xx_spi *espi = spi_master_get_devdata(master);
958
959 ep93xx_spi_release_dma(espi);
960
961 return 0;
962}
963
964static struct platform_driver ep93xx_spi_driver = {
965 .driver = {
966 .name = "ep93xx-spi",
967 },
968 .probe = ep93xx_spi_probe,
969 .remove = ep93xx_spi_remove,
970};
971module_platform_driver(ep93xx_spi_driver);
972
973MODULE_DESCRIPTION("EP93xx SPI Controller driver");
974MODULE_AUTHOR("Mika Westerberg <mika.westerberg@iki.fi>");
975MODULE_LICENSE("GPL");
976MODULE_ALIAS("platform:ep93xx-spi");
1/*
2 * Driver for Cirrus Logic EP93xx SPI controller.
3 *
4 * Copyright (C) 2010-2011 Mika Westerberg
5 *
6 * Explicit FIFO handling code was inspired by amba-pl022 driver.
7 *
8 * Chip select support using other than built-in GPIOs by H. Hartley Sweeten.
9 *
10 * For more information about the SPI controller see documentation on Cirrus
11 * Logic web site:
12 * http://www.cirrus.com/en/pubs/manual/EP93xx_Users_Guide_UM1.pdf
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
19#include <linux/io.h>
20#include <linux/clk.h>
21#include <linux/err.h>
22#include <linux/delay.h>
23#include <linux/device.h>
24#include <linux/dmaengine.h>
25#include <linux/bitops.h>
26#include <linux/interrupt.h>
27#include <linux/platform_device.h>
28#include <linux/workqueue.h>
29#include <linux/sched.h>
30#include <linux/scatterlist.h>
31#include <linux/spi/spi.h>
32
33#include <mach/dma.h>
34#include <mach/ep93xx_spi.h>
35
36#define SSPCR0 0x0000
37#define SSPCR0_MODE_SHIFT 6
38#define SSPCR0_SCR_SHIFT 8
39
40#define SSPCR1 0x0004
41#define SSPCR1_RIE BIT(0)
42#define SSPCR1_TIE BIT(1)
43#define SSPCR1_RORIE BIT(2)
44#define SSPCR1_LBM BIT(3)
45#define SSPCR1_SSE BIT(4)
46#define SSPCR1_MS BIT(5)
47#define SSPCR1_SOD BIT(6)
48
49#define SSPDR 0x0008
50
51#define SSPSR 0x000c
52#define SSPSR_TFE BIT(0)
53#define SSPSR_TNF BIT(1)
54#define SSPSR_RNE BIT(2)
55#define SSPSR_RFF BIT(3)
56#define SSPSR_BSY BIT(4)
57#define SSPCPSR 0x0010
58
59#define SSPIIR 0x0014
60#define SSPIIR_RIS BIT(0)
61#define SSPIIR_TIS BIT(1)
62#define SSPIIR_RORIS BIT(2)
63#define SSPICR SSPIIR
64
65/* timeout in milliseconds */
66#define SPI_TIMEOUT 5
67/* maximum depth of RX/TX FIFO */
68#define SPI_FIFO_SIZE 8
69
70/**
71 * struct ep93xx_spi - EP93xx SPI controller structure
72 * @lock: spinlock that protects concurrent accesses to fields @running,
73 * @current_msg and @msg_queue
74 * @pdev: pointer to platform device
75 * @clk: clock for the controller
76 * @regs_base: pointer to ioremap()'d registers
77 * @sspdr_phys: physical address of the SSPDR register
78 * @irq: IRQ number used by the driver
79 * @min_rate: minimum clock rate (in Hz) supported by the controller
80 * @max_rate: maximum clock rate (in Hz) supported by the controller
81 * @running: is the queue running
82 * @wq: workqueue used by the driver
83 * @msg_work: work that is queued for the driver
84 * @wait: wait here until given transfer is completed
85 * @msg_queue: queue for the messages
86 * @current_msg: message that is currently processed (or %NULL if none)
87 * @tx: current byte in transfer to transmit
88 * @rx: current byte in transfer to receive
89 * @fifo_level: how full is FIFO (%0..%SPI_FIFO_SIZE - %1). Receiving one
90 * frame decreases this level and sending one frame increases it.
91 * @dma_rx: RX DMA channel
92 * @dma_tx: TX DMA channel
93 * @dma_rx_data: RX parameters passed to the DMA engine
94 * @dma_tx_data: TX parameters passed to the DMA engine
95 * @rx_sgt: sg table for RX transfers
96 * @tx_sgt: sg table for TX transfers
97 * @zeropage: dummy page used as RX buffer when only TX buffer is passed in by
98 * the client
99 *
100 * This structure holds EP93xx SPI controller specific information. When
101 * @running is %true, driver accepts transfer requests from protocol drivers.
102 * @current_msg is used to hold pointer to the message that is currently
103 * processed. If @current_msg is %NULL, it means that no processing is going
104 * on.
105 *
106 * Most of the fields are only written once and they can be accessed without
107 * taking the @lock. Fields that are accessed concurrently are: @current_msg,
108 * @running, and @msg_queue.
109 */
110struct ep93xx_spi {
111 spinlock_t lock;
112 const struct platform_device *pdev;
113 struct clk *clk;
114 void __iomem *regs_base;
115 unsigned long sspdr_phys;
116 int irq;
117 unsigned long min_rate;
118 unsigned long max_rate;
119 bool running;
120 struct workqueue_struct *wq;
121 struct work_struct msg_work;
122 struct completion wait;
123 struct list_head msg_queue;
124 struct spi_message *current_msg;
125 size_t tx;
126 size_t rx;
127 size_t fifo_level;
128 struct dma_chan *dma_rx;
129 struct dma_chan *dma_tx;
130 struct ep93xx_dma_data dma_rx_data;
131 struct ep93xx_dma_data dma_tx_data;
132 struct sg_table rx_sgt;
133 struct sg_table tx_sgt;
134 void *zeropage;
135};
136
137/**
138 * struct ep93xx_spi_chip - SPI device hardware settings
139 * @spi: back pointer to the SPI device
140 * @rate: max rate in hz this chip supports
141 * @div_cpsr: cpsr (pre-scaler) divider
142 * @div_scr: scr divider
143 * @dss: bits per word (4 - 16 bits)
144 * @ops: private chip operations
145 *
146 * This structure is used to store hardware register specific settings for each
147 * SPI device. Settings are written to hardware by function
148 * ep93xx_spi_chip_setup().
149 */
150struct ep93xx_spi_chip {
151 const struct spi_device *spi;
152 unsigned long rate;
153 u8 div_cpsr;
154 u8 div_scr;
155 u8 dss;
156 struct ep93xx_spi_chip_ops *ops;
157};
158
159/* converts bits per word to CR0.DSS value */
160#define bits_per_word_to_dss(bpw) ((bpw) - 1)
161
162static inline void
163ep93xx_spi_write_u8(const struct ep93xx_spi *espi, u16 reg, u8 value)
164{
165 __raw_writeb(value, espi->regs_base + reg);
166}
167
168static inline u8
169ep93xx_spi_read_u8(const struct ep93xx_spi *spi, u16 reg)
170{
171 return __raw_readb(spi->regs_base + reg);
172}
173
174static inline void
175ep93xx_spi_write_u16(const struct ep93xx_spi *espi, u16 reg, u16 value)
176{
177 __raw_writew(value, espi->regs_base + reg);
178}
179
180static inline u16
181ep93xx_spi_read_u16(const struct ep93xx_spi *spi, u16 reg)
182{
183 return __raw_readw(spi->regs_base + reg);
184}
185
186static int ep93xx_spi_enable(const struct ep93xx_spi *espi)
187{
188 u8 regval;
189 int err;
190
191 err = clk_enable(espi->clk);
192 if (err)
193 return err;
194
195 regval = ep93xx_spi_read_u8(espi, SSPCR1);
196 regval |= SSPCR1_SSE;
197 ep93xx_spi_write_u8(espi, SSPCR1, regval);
198
199 return 0;
200}
201
202static void ep93xx_spi_disable(const struct ep93xx_spi *espi)
203{
204 u8 regval;
205
206 regval = ep93xx_spi_read_u8(espi, SSPCR1);
207 regval &= ~SSPCR1_SSE;
208 ep93xx_spi_write_u8(espi, SSPCR1, regval);
209
210 clk_disable(espi->clk);
211}
212
213static void ep93xx_spi_enable_interrupts(const struct ep93xx_spi *espi)
214{
215 u8 regval;
216
217 regval = ep93xx_spi_read_u8(espi, SSPCR1);
218 regval |= (SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE);
219 ep93xx_spi_write_u8(espi, SSPCR1, regval);
220}
221
222static void ep93xx_spi_disable_interrupts(const struct ep93xx_spi *espi)
223{
224 u8 regval;
225
226 regval = ep93xx_spi_read_u8(espi, SSPCR1);
227 regval &= ~(SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE);
228 ep93xx_spi_write_u8(espi, SSPCR1, regval);
229}
230
231/**
232 * ep93xx_spi_calc_divisors() - calculates SPI clock divisors
233 * @espi: ep93xx SPI controller struct
234 * @chip: divisors are calculated for this chip
235 * @rate: desired SPI output clock rate
236 *
237 * Function calculates cpsr (clock pre-scaler) and scr divisors based on
238 * given @rate and places them to @chip->div_cpsr and @chip->div_scr. If,
239 * for some reason, divisors cannot be calculated nothing is stored and
240 * %-EINVAL is returned.
241 */
242static int ep93xx_spi_calc_divisors(const struct ep93xx_spi *espi,
243 struct ep93xx_spi_chip *chip,
244 unsigned long rate)
245{
246 unsigned long spi_clk_rate = clk_get_rate(espi->clk);
247 int cpsr, scr;
248
249 /*
250 * Make sure that max value is between values supported by the
251 * controller. Note that minimum value is already checked in
252 * ep93xx_spi_transfer().
253 */
254 rate = clamp(rate, espi->min_rate, espi->max_rate);
255
256 /*
257 * Calculate divisors so that we can get speed according the
258 * following formula:
259 * rate = spi_clock_rate / (cpsr * (1 + scr))
260 *
261 * cpsr must be even number and starts from 2, scr can be any number
262 * between 0 and 255.
263 */
264 for (cpsr = 2; cpsr <= 254; cpsr += 2) {
265 for (scr = 0; scr <= 255; scr++) {
266 if ((spi_clk_rate / (cpsr * (scr + 1))) <= rate) {
267 chip->div_scr = (u8)scr;
268 chip->div_cpsr = (u8)cpsr;
269 return 0;
270 }
271 }
272 }
273
274 return -EINVAL;
275}
276
277static void ep93xx_spi_cs_control(struct spi_device *spi, bool control)
278{
279 struct ep93xx_spi_chip *chip = spi_get_ctldata(spi);
280 int value = (spi->mode & SPI_CS_HIGH) ? control : !control;
281
282 if (chip->ops && chip->ops->cs_control)
283 chip->ops->cs_control(spi, value);
284}
285
286/**
287 * ep93xx_spi_setup() - setup an SPI device
288 * @spi: SPI device to setup
289 *
290 * This function sets up SPI device mode, speed etc. Can be called multiple
291 * times for a single device. Returns %0 in case of success, negative error in
292 * case of failure. When this function returns success, the device is
293 * deselected.
294 */
295static int ep93xx_spi_setup(struct spi_device *spi)
296{
297 struct ep93xx_spi *espi = spi_master_get_devdata(spi->master);
298 struct ep93xx_spi_chip *chip;
299
300 if (spi->bits_per_word < 4 || spi->bits_per_word > 16) {
301 dev_err(&espi->pdev->dev, "invalid bits per word %d\n",
302 spi->bits_per_word);
303 return -EINVAL;
304 }
305
306 chip = spi_get_ctldata(spi);
307 if (!chip) {
308 dev_dbg(&espi->pdev->dev, "initial setup for %s\n",
309 spi->modalias);
310
311 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
312 if (!chip)
313 return -ENOMEM;
314
315 chip->spi = spi;
316 chip->ops = spi->controller_data;
317
318 if (chip->ops && chip->ops->setup) {
319 int ret = chip->ops->setup(spi);
320 if (ret) {
321 kfree(chip);
322 return ret;
323 }
324 }
325
326 spi_set_ctldata(spi, chip);
327 }
328
329 if (spi->max_speed_hz != chip->rate) {
330 int err;
331
332 err = ep93xx_spi_calc_divisors(espi, chip, spi->max_speed_hz);
333 if (err != 0) {
334 spi_set_ctldata(spi, NULL);
335 kfree(chip);
336 return err;
337 }
338 chip->rate = spi->max_speed_hz;
339 }
340
341 chip->dss = bits_per_word_to_dss(spi->bits_per_word);
342
343 ep93xx_spi_cs_control(spi, false);
344 return 0;
345}
346
347/**
348 * ep93xx_spi_transfer() - queue message to be transferred
349 * @spi: target SPI device
350 * @msg: message to be transferred
351 *
352 * This function is called by SPI device drivers when they are going to transfer
353 * a new message. It simply puts the message in the queue and schedules
354 * workqueue to perform the actual transfer later on.
355 *
356 * Returns %0 on success and negative error in case of failure.
357 */
358static int ep93xx_spi_transfer(struct spi_device *spi, struct spi_message *msg)
359{
360 struct ep93xx_spi *espi = spi_master_get_devdata(spi->master);
361 struct spi_transfer *t;
362 unsigned long flags;
363
364 if (!msg || !msg->complete)
365 return -EINVAL;
366
367 /* first validate each transfer */
368 list_for_each_entry(t, &msg->transfers, transfer_list) {
369 if (t->bits_per_word) {
370 if (t->bits_per_word < 4 || t->bits_per_word > 16)
371 return -EINVAL;
372 }
373 if (t->speed_hz && t->speed_hz < espi->min_rate)
374 return -EINVAL;
375 }
376
377 /*
378 * Now that we own the message, let's initialize it so that it is
379 * suitable for us. We use @msg->status to signal whether there was
380 * error in transfer and @msg->state is used to hold pointer to the
381 * current transfer (or %NULL if no active current transfer).
382 */
383 msg->state = NULL;
384 msg->status = 0;
385 msg->actual_length = 0;
386
387 spin_lock_irqsave(&espi->lock, flags);
388 if (!espi->running) {
389 spin_unlock_irqrestore(&espi->lock, flags);
390 return -ESHUTDOWN;
391 }
392 list_add_tail(&msg->queue, &espi->msg_queue);
393 queue_work(espi->wq, &espi->msg_work);
394 spin_unlock_irqrestore(&espi->lock, flags);
395
396 return 0;
397}
398
399/**
400 * ep93xx_spi_cleanup() - cleans up master controller specific state
401 * @spi: SPI device to cleanup
402 *
403 * This function releases master controller specific state for given @spi
404 * device.
405 */
406static void ep93xx_spi_cleanup(struct spi_device *spi)
407{
408 struct ep93xx_spi_chip *chip;
409
410 chip = spi_get_ctldata(spi);
411 if (chip) {
412 if (chip->ops && chip->ops->cleanup)
413 chip->ops->cleanup(spi);
414 spi_set_ctldata(spi, NULL);
415 kfree(chip);
416 }
417}
418
419/**
420 * ep93xx_spi_chip_setup() - configures hardware according to given @chip
421 * @espi: ep93xx SPI controller struct
422 * @chip: chip specific settings
423 *
424 * This function sets up the actual hardware registers with settings given in
425 * @chip. Note that no validation is done so make sure that callers validate
426 * settings before calling this.
427 */
428static void ep93xx_spi_chip_setup(const struct ep93xx_spi *espi,
429 const struct ep93xx_spi_chip *chip)
430{
431 u16 cr0;
432
433 cr0 = chip->div_scr << SSPCR0_SCR_SHIFT;
434 cr0 |= (chip->spi->mode & (SPI_CPHA|SPI_CPOL)) << SSPCR0_MODE_SHIFT;
435 cr0 |= chip->dss;
436
437 dev_dbg(&espi->pdev->dev, "setup: mode %d, cpsr %d, scr %d, dss %d\n",
438 chip->spi->mode, chip->div_cpsr, chip->div_scr, chip->dss);
439 dev_dbg(&espi->pdev->dev, "setup: cr0 %#x", cr0);
440
441 ep93xx_spi_write_u8(espi, SSPCPSR, chip->div_cpsr);
442 ep93xx_spi_write_u16(espi, SSPCR0, cr0);
443}
444
445static inline int bits_per_word(const struct ep93xx_spi *espi)
446{
447 struct spi_message *msg = espi->current_msg;
448 struct spi_transfer *t = msg->state;
449
450 return t->bits_per_word ? t->bits_per_word : msg->spi->bits_per_word;
451}
452
453static void ep93xx_do_write(struct ep93xx_spi *espi, struct spi_transfer *t)
454{
455 if (bits_per_word(espi) > 8) {
456 u16 tx_val = 0;
457
458 if (t->tx_buf)
459 tx_val = ((u16 *)t->tx_buf)[espi->tx];
460 ep93xx_spi_write_u16(espi, SSPDR, tx_val);
461 espi->tx += sizeof(tx_val);
462 } else {
463 u8 tx_val = 0;
464
465 if (t->tx_buf)
466 tx_val = ((u8 *)t->tx_buf)[espi->tx];
467 ep93xx_spi_write_u8(espi, SSPDR, tx_val);
468 espi->tx += sizeof(tx_val);
469 }
470}
471
472static void ep93xx_do_read(struct ep93xx_spi *espi, struct spi_transfer *t)
473{
474 if (bits_per_word(espi) > 8) {
475 u16 rx_val;
476
477 rx_val = ep93xx_spi_read_u16(espi, SSPDR);
478 if (t->rx_buf)
479 ((u16 *)t->rx_buf)[espi->rx] = rx_val;
480 espi->rx += sizeof(rx_val);
481 } else {
482 u8 rx_val;
483
484 rx_val = ep93xx_spi_read_u8(espi, SSPDR);
485 if (t->rx_buf)
486 ((u8 *)t->rx_buf)[espi->rx] = rx_val;
487 espi->rx += sizeof(rx_val);
488 }
489}
490
491/**
492 * ep93xx_spi_read_write() - perform next RX/TX transfer
493 * @espi: ep93xx SPI controller struct
494 *
495 * This function transfers next bytes (or half-words) to/from RX/TX FIFOs. If
496 * called several times, the whole transfer will be completed. Returns
497 * %-EINPROGRESS when current transfer was not yet completed otherwise %0.
498 *
499 * When this function is finished, RX FIFO should be empty and TX FIFO should be
500 * full.
501 */
502static int ep93xx_spi_read_write(struct ep93xx_spi *espi)
503{
504 struct spi_message *msg = espi->current_msg;
505 struct spi_transfer *t = msg->state;
506
507 /* read as long as RX FIFO has frames in it */
508 while ((ep93xx_spi_read_u8(espi, SSPSR) & SSPSR_RNE)) {
509 ep93xx_do_read(espi, t);
510 espi->fifo_level--;
511 }
512
513 /* write as long as TX FIFO has room */
514 while (espi->fifo_level < SPI_FIFO_SIZE && espi->tx < t->len) {
515 ep93xx_do_write(espi, t);
516 espi->fifo_level++;
517 }
518
519 if (espi->rx == t->len)
520 return 0;
521
522 return -EINPROGRESS;
523}
524
525static void ep93xx_spi_pio_transfer(struct ep93xx_spi *espi)
526{
527 /*
528 * Now everything is set up for the current transfer. We prime the TX
529 * FIFO, enable interrupts, and wait for the transfer to complete.
530 */
531 if (ep93xx_spi_read_write(espi)) {
532 ep93xx_spi_enable_interrupts(espi);
533 wait_for_completion(&espi->wait);
534 }
535}
536
537/**
538 * ep93xx_spi_dma_prepare() - prepares a DMA transfer
539 * @espi: ep93xx SPI controller struct
540 * @dir: DMA transfer direction
541 *
542 * Function configures the DMA, maps the buffer and prepares the DMA
543 * descriptor. Returns a valid DMA descriptor in case of success and ERR_PTR
544 * in case of failure.
545 */
546static struct dma_async_tx_descriptor *
547ep93xx_spi_dma_prepare(struct ep93xx_spi *espi, enum dma_data_direction dir)
548{
549 struct spi_transfer *t = espi->current_msg->state;
550 struct dma_async_tx_descriptor *txd;
551 enum dma_slave_buswidth buswidth;
552 struct dma_slave_config conf;
553 struct scatterlist *sg;
554 struct sg_table *sgt;
555 struct dma_chan *chan;
556 const void *buf, *pbuf;
557 size_t len = t->len;
558 int i, ret, nents;
559
560 if (bits_per_word(espi) > 8)
561 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
562 else
563 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
564
565 memset(&conf, 0, sizeof(conf));
566 conf.direction = dir;
567
568 if (dir == DMA_FROM_DEVICE) {
569 chan = espi->dma_rx;
570 buf = t->rx_buf;
571 sgt = &espi->rx_sgt;
572
573 conf.src_addr = espi->sspdr_phys;
574 conf.src_addr_width = buswidth;
575 } else {
576 chan = espi->dma_tx;
577 buf = t->tx_buf;
578 sgt = &espi->tx_sgt;
579
580 conf.dst_addr = espi->sspdr_phys;
581 conf.dst_addr_width = buswidth;
582 }
583
584 ret = dmaengine_slave_config(chan, &conf);
585 if (ret)
586 return ERR_PTR(ret);
587
588 /*
589 * We need to split the transfer into PAGE_SIZE'd chunks. This is
590 * because we are using @espi->zeropage to provide a zero RX buffer
591 * for the TX transfers and we have only allocated one page for that.
592 *
593 * For performance reasons we allocate a new sg_table only when
594 * needed. Otherwise we will re-use the current one. Eventually the
595 * last sg_table is released in ep93xx_spi_release_dma().
596 */
597
598 nents = DIV_ROUND_UP(len, PAGE_SIZE);
599 if (nents != sgt->nents) {
600 sg_free_table(sgt);
601
602 ret = sg_alloc_table(sgt, nents, GFP_KERNEL);
603 if (ret)
604 return ERR_PTR(ret);
605 }
606
607 pbuf = buf;
608 for_each_sg(sgt->sgl, sg, sgt->nents, i) {
609 size_t bytes = min_t(size_t, len, PAGE_SIZE);
610
611 if (buf) {
612 sg_set_page(sg, virt_to_page(pbuf), bytes,
613 offset_in_page(pbuf));
614 } else {
615 sg_set_page(sg, virt_to_page(espi->zeropage),
616 bytes, 0);
617 }
618
619 pbuf += bytes;
620 len -= bytes;
621 }
622
623 if (WARN_ON(len)) {
624 dev_warn(&espi->pdev->dev, "len = %d expected 0!", len);
625 return ERR_PTR(-EINVAL);
626 }
627
628 nents = dma_map_sg(chan->device->dev, sgt->sgl, sgt->nents, dir);
629 if (!nents)
630 return ERR_PTR(-ENOMEM);
631
632 txd = chan->device->device_prep_slave_sg(chan, sgt->sgl, nents,
633 dir, DMA_CTRL_ACK);
634 if (!txd) {
635 dma_unmap_sg(chan->device->dev, sgt->sgl, sgt->nents, dir);
636 return ERR_PTR(-ENOMEM);
637 }
638 return txd;
639}
640
641/**
642 * ep93xx_spi_dma_finish() - finishes with a DMA transfer
643 * @espi: ep93xx SPI controller struct
644 * @dir: DMA transfer direction
645 *
646 * Function finishes with the DMA transfer. After this, the DMA buffer is
647 * unmapped.
648 */
649static void ep93xx_spi_dma_finish(struct ep93xx_spi *espi,
650 enum dma_data_direction dir)
651{
652 struct dma_chan *chan;
653 struct sg_table *sgt;
654
655 if (dir == DMA_FROM_DEVICE) {
656 chan = espi->dma_rx;
657 sgt = &espi->rx_sgt;
658 } else {
659 chan = espi->dma_tx;
660 sgt = &espi->tx_sgt;
661 }
662
663 dma_unmap_sg(chan->device->dev, sgt->sgl, sgt->nents, dir);
664}
665
666static void ep93xx_spi_dma_callback(void *callback_param)
667{
668 complete(callback_param);
669}
670
671static void ep93xx_spi_dma_transfer(struct ep93xx_spi *espi)
672{
673 struct spi_message *msg = espi->current_msg;
674 struct dma_async_tx_descriptor *rxd, *txd;
675
676 rxd = ep93xx_spi_dma_prepare(espi, DMA_FROM_DEVICE);
677 if (IS_ERR(rxd)) {
678 dev_err(&espi->pdev->dev, "DMA RX failed: %ld\n", PTR_ERR(rxd));
679 msg->status = PTR_ERR(rxd);
680 return;
681 }
682
683 txd = ep93xx_spi_dma_prepare(espi, DMA_TO_DEVICE);
684 if (IS_ERR(txd)) {
685 ep93xx_spi_dma_finish(espi, DMA_FROM_DEVICE);
686 dev_err(&espi->pdev->dev, "DMA TX failed: %ld\n", PTR_ERR(rxd));
687 msg->status = PTR_ERR(txd);
688 return;
689 }
690
691 /* We are ready when RX is done */
692 rxd->callback = ep93xx_spi_dma_callback;
693 rxd->callback_param = &espi->wait;
694
695 /* Now submit both descriptors and wait while they finish */
696 dmaengine_submit(rxd);
697 dmaengine_submit(txd);
698
699 dma_async_issue_pending(espi->dma_rx);
700 dma_async_issue_pending(espi->dma_tx);
701
702 wait_for_completion(&espi->wait);
703
704 ep93xx_spi_dma_finish(espi, DMA_TO_DEVICE);
705 ep93xx_spi_dma_finish(espi, DMA_FROM_DEVICE);
706}
707
708/**
709 * ep93xx_spi_process_transfer() - processes one SPI transfer
710 * @espi: ep93xx SPI controller struct
711 * @msg: current message
712 * @t: transfer to process
713 *
714 * This function processes one SPI transfer given in @t. Function waits until
715 * transfer is complete (may sleep) and updates @msg->status based on whether
716 * transfer was successfully processed or not.
717 */
718static void ep93xx_spi_process_transfer(struct ep93xx_spi *espi,
719 struct spi_message *msg,
720 struct spi_transfer *t)
721{
722 struct ep93xx_spi_chip *chip = spi_get_ctldata(msg->spi);
723
724 msg->state = t;
725
726 /*
727 * Handle any transfer specific settings if needed. We use
728 * temporary chip settings here and restore original later when
729 * the transfer is finished.
730 */
731 if (t->speed_hz || t->bits_per_word) {
732 struct ep93xx_spi_chip tmp_chip = *chip;
733
734 if (t->speed_hz) {
735 int err;
736
737 err = ep93xx_spi_calc_divisors(espi, &tmp_chip,
738 t->speed_hz);
739 if (err) {
740 dev_err(&espi->pdev->dev,
741 "failed to adjust speed\n");
742 msg->status = err;
743 return;
744 }
745 }
746
747 if (t->bits_per_word)
748 tmp_chip.dss = bits_per_word_to_dss(t->bits_per_word);
749
750 /*
751 * Set up temporary new hw settings for this transfer.
752 */
753 ep93xx_spi_chip_setup(espi, &tmp_chip);
754 }
755
756 espi->rx = 0;
757 espi->tx = 0;
758
759 /*
760 * There is no point of setting up DMA for the transfers which will
761 * fit into the FIFO and can be transferred with a single interrupt.
762 * So in these cases we will be using PIO and don't bother for DMA.
763 */
764 if (espi->dma_rx && t->len > SPI_FIFO_SIZE)
765 ep93xx_spi_dma_transfer(espi);
766 else
767 ep93xx_spi_pio_transfer(espi);
768
769 /*
770 * In case of error during transmit, we bail out from processing
771 * the message.
772 */
773 if (msg->status)
774 return;
775
776 msg->actual_length += t->len;
777
778 /*
779 * After this transfer is finished, perform any possible
780 * post-transfer actions requested by the protocol driver.
781 */
782 if (t->delay_usecs) {
783 set_current_state(TASK_UNINTERRUPTIBLE);
784 schedule_timeout(usecs_to_jiffies(t->delay_usecs));
785 }
786 if (t->cs_change) {
787 if (!list_is_last(&t->transfer_list, &msg->transfers)) {
788 /*
789 * In case protocol driver is asking us to drop the
790 * chipselect briefly, we let the scheduler to handle
791 * any "delay" here.
792 */
793 ep93xx_spi_cs_control(msg->spi, false);
794 cond_resched();
795 ep93xx_spi_cs_control(msg->spi, true);
796 }
797 }
798
799 if (t->speed_hz || t->bits_per_word)
800 ep93xx_spi_chip_setup(espi, chip);
801}
802
803/*
804 * ep93xx_spi_process_message() - process one SPI message
805 * @espi: ep93xx SPI controller struct
806 * @msg: message to process
807 *
808 * This function processes a single SPI message. We go through all transfers in
809 * the message and pass them to ep93xx_spi_process_transfer(). Chipselect is
810 * asserted during the whole message (unless per transfer cs_change is set).
811 *
812 * @msg->status contains %0 in case of success or negative error code in case of
813 * failure.
814 */
815static void ep93xx_spi_process_message(struct ep93xx_spi *espi,
816 struct spi_message *msg)
817{
818 unsigned long timeout;
819 struct spi_transfer *t;
820 int err;
821
822 /*
823 * Enable the SPI controller and its clock.
824 */
825 err = ep93xx_spi_enable(espi);
826 if (err) {
827 dev_err(&espi->pdev->dev, "failed to enable SPI controller\n");
828 msg->status = err;
829 return;
830 }
831
832 /*
833 * Just to be sure: flush any data from RX FIFO.
834 */
835 timeout = jiffies + msecs_to_jiffies(SPI_TIMEOUT);
836 while (ep93xx_spi_read_u16(espi, SSPSR) & SSPSR_RNE) {
837 if (time_after(jiffies, timeout)) {
838 dev_warn(&espi->pdev->dev,
839 "timeout while flushing RX FIFO\n");
840 msg->status = -ETIMEDOUT;
841 return;
842 }
843 ep93xx_spi_read_u16(espi, SSPDR);
844 }
845
846 /*
847 * We explicitly handle FIFO level. This way we don't have to check TX
848 * FIFO status using %SSPSR_TNF bit which may cause RX FIFO overruns.
849 */
850 espi->fifo_level = 0;
851
852 /*
853 * Update SPI controller registers according to spi device and assert
854 * the chipselect.
855 */
856 ep93xx_spi_chip_setup(espi, spi_get_ctldata(msg->spi));
857 ep93xx_spi_cs_control(msg->spi, true);
858
859 list_for_each_entry(t, &msg->transfers, transfer_list) {
860 ep93xx_spi_process_transfer(espi, msg, t);
861 if (msg->status)
862 break;
863 }
864
865 /*
866 * Now the whole message is transferred (or failed for some reason). We
867 * deselect the device and disable the SPI controller.
868 */
869 ep93xx_spi_cs_control(msg->spi, false);
870 ep93xx_spi_disable(espi);
871}
872
873#define work_to_espi(work) (container_of((work), struct ep93xx_spi, msg_work))
874
875/**
876 * ep93xx_spi_work() - EP93xx SPI workqueue worker function
877 * @work: work struct
878 *
879 * Workqueue worker function. This function is called when there are new
880 * SPI messages to be processed. Message is taken out from the queue and then
881 * passed to ep93xx_spi_process_message().
882 *
883 * After message is transferred, protocol driver is notified by calling
884 * @msg->complete(). In case of error, @msg->status is set to negative error
885 * number, otherwise it contains zero (and @msg->actual_length is updated).
886 */
887static void ep93xx_spi_work(struct work_struct *work)
888{
889 struct ep93xx_spi *espi = work_to_espi(work);
890 struct spi_message *msg;
891
892 spin_lock_irq(&espi->lock);
893 if (!espi->running || espi->current_msg ||
894 list_empty(&espi->msg_queue)) {
895 spin_unlock_irq(&espi->lock);
896 return;
897 }
898 msg = list_first_entry(&espi->msg_queue, struct spi_message, queue);
899 list_del_init(&msg->queue);
900 espi->current_msg = msg;
901 spin_unlock_irq(&espi->lock);
902
903 ep93xx_spi_process_message(espi, msg);
904
905 /*
906 * Update the current message and re-schedule ourselves if there are
907 * more messages in the queue.
908 */
909 spin_lock_irq(&espi->lock);
910 espi->current_msg = NULL;
911 if (espi->running && !list_empty(&espi->msg_queue))
912 queue_work(espi->wq, &espi->msg_work);
913 spin_unlock_irq(&espi->lock);
914
915 /* notify the protocol driver that we are done with this message */
916 msg->complete(msg->context);
917}
918
919static irqreturn_t ep93xx_spi_interrupt(int irq, void *dev_id)
920{
921 struct ep93xx_spi *espi = dev_id;
922 u8 irq_status = ep93xx_spi_read_u8(espi, SSPIIR);
923
924 /*
925 * If we got ROR (receive overrun) interrupt we know that something is
926 * wrong. Just abort the message.
927 */
928 if (unlikely(irq_status & SSPIIR_RORIS)) {
929 /* clear the overrun interrupt */
930 ep93xx_spi_write_u8(espi, SSPICR, 0);
931 dev_warn(&espi->pdev->dev,
932 "receive overrun, aborting the message\n");
933 espi->current_msg->status = -EIO;
934 } else {
935 /*
936 * Interrupt is either RX (RIS) or TX (TIS). For both cases we
937 * simply execute next data transfer.
938 */
939 if (ep93xx_spi_read_write(espi)) {
940 /*
941 * In normal case, there still is some processing left
942 * for current transfer. Let's wait for the next
943 * interrupt then.
944 */
945 return IRQ_HANDLED;
946 }
947 }
948
949 /*
950 * Current transfer is finished, either with error or with success. In
951 * any case we disable interrupts and notify the worker to handle
952 * any post-processing of the message.
953 */
954 ep93xx_spi_disable_interrupts(espi);
955 complete(&espi->wait);
956 return IRQ_HANDLED;
957}
958
959static bool ep93xx_spi_dma_filter(struct dma_chan *chan, void *filter_param)
960{
961 if (ep93xx_dma_chan_is_m2p(chan))
962 return false;
963
964 chan->private = filter_param;
965 return true;
966}
967
968static int ep93xx_spi_setup_dma(struct ep93xx_spi *espi)
969{
970 dma_cap_mask_t mask;
971 int ret;
972
973 espi->zeropage = (void *)get_zeroed_page(GFP_KERNEL);
974 if (!espi->zeropage)
975 return -ENOMEM;
976
977 dma_cap_zero(mask);
978 dma_cap_set(DMA_SLAVE, mask);
979
980 espi->dma_rx_data.port = EP93XX_DMA_SSP;
981 espi->dma_rx_data.direction = DMA_FROM_DEVICE;
982 espi->dma_rx_data.name = "ep93xx-spi-rx";
983
984 espi->dma_rx = dma_request_channel(mask, ep93xx_spi_dma_filter,
985 &espi->dma_rx_data);
986 if (!espi->dma_rx) {
987 ret = -ENODEV;
988 goto fail_free_page;
989 }
990
991 espi->dma_tx_data.port = EP93XX_DMA_SSP;
992 espi->dma_tx_data.direction = DMA_TO_DEVICE;
993 espi->dma_tx_data.name = "ep93xx-spi-tx";
994
995 espi->dma_tx = dma_request_channel(mask, ep93xx_spi_dma_filter,
996 &espi->dma_tx_data);
997 if (!espi->dma_tx) {
998 ret = -ENODEV;
999 goto fail_release_rx;
1000 }
1001
1002 return 0;
1003
1004fail_release_rx:
1005 dma_release_channel(espi->dma_rx);
1006 espi->dma_rx = NULL;
1007fail_free_page:
1008 free_page((unsigned long)espi->zeropage);
1009
1010 return ret;
1011}
1012
1013static void ep93xx_spi_release_dma(struct ep93xx_spi *espi)
1014{
1015 if (espi->dma_rx) {
1016 dma_release_channel(espi->dma_rx);
1017 sg_free_table(&espi->rx_sgt);
1018 }
1019 if (espi->dma_tx) {
1020 dma_release_channel(espi->dma_tx);
1021 sg_free_table(&espi->tx_sgt);
1022 }
1023
1024 if (espi->zeropage)
1025 free_page((unsigned long)espi->zeropage);
1026}
1027
1028static int __init ep93xx_spi_probe(struct platform_device *pdev)
1029{
1030 struct spi_master *master;
1031 struct ep93xx_spi_info *info;
1032 struct ep93xx_spi *espi;
1033 struct resource *res;
1034 int error;
1035
1036 info = pdev->dev.platform_data;
1037
1038 master = spi_alloc_master(&pdev->dev, sizeof(*espi));
1039 if (!master) {
1040 dev_err(&pdev->dev, "failed to allocate spi master\n");
1041 return -ENOMEM;
1042 }
1043
1044 master->setup = ep93xx_spi_setup;
1045 master->transfer = ep93xx_spi_transfer;
1046 master->cleanup = ep93xx_spi_cleanup;
1047 master->bus_num = pdev->id;
1048 master->num_chipselect = info->num_chipselect;
1049 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1050
1051 platform_set_drvdata(pdev, master);
1052
1053 espi = spi_master_get_devdata(master);
1054
1055 espi->clk = clk_get(&pdev->dev, NULL);
1056 if (IS_ERR(espi->clk)) {
1057 dev_err(&pdev->dev, "unable to get spi clock\n");
1058 error = PTR_ERR(espi->clk);
1059 goto fail_release_master;
1060 }
1061
1062 spin_lock_init(&espi->lock);
1063 init_completion(&espi->wait);
1064
1065 /*
1066 * Calculate maximum and minimum supported clock rates
1067 * for the controller.
1068 */
1069 espi->max_rate = clk_get_rate(espi->clk) / 2;
1070 espi->min_rate = clk_get_rate(espi->clk) / (254 * 256);
1071 espi->pdev = pdev;
1072
1073 espi->irq = platform_get_irq(pdev, 0);
1074 if (espi->irq < 0) {
1075 error = -EBUSY;
1076 dev_err(&pdev->dev, "failed to get irq resources\n");
1077 goto fail_put_clock;
1078 }
1079
1080 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1081 if (!res) {
1082 dev_err(&pdev->dev, "unable to get iomem resource\n");
1083 error = -ENODEV;
1084 goto fail_put_clock;
1085 }
1086
1087 res = request_mem_region(res->start, resource_size(res), pdev->name);
1088 if (!res) {
1089 dev_err(&pdev->dev, "unable to request iomem resources\n");
1090 error = -EBUSY;
1091 goto fail_put_clock;
1092 }
1093
1094 espi->sspdr_phys = res->start + SSPDR;
1095 espi->regs_base = ioremap(res->start, resource_size(res));
1096 if (!espi->regs_base) {
1097 dev_err(&pdev->dev, "failed to map resources\n");
1098 error = -ENODEV;
1099 goto fail_free_mem;
1100 }
1101
1102 error = request_irq(espi->irq, ep93xx_spi_interrupt, 0,
1103 "ep93xx-spi", espi);
1104 if (error) {
1105 dev_err(&pdev->dev, "failed to request irq\n");
1106 goto fail_unmap_regs;
1107 }
1108
1109 if (info->use_dma && ep93xx_spi_setup_dma(espi))
1110 dev_warn(&pdev->dev, "DMA setup failed. Falling back to PIO\n");
1111
1112 espi->wq = create_singlethread_workqueue("ep93xx_spid");
1113 if (!espi->wq) {
1114 dev_err(&pdev->dev, "unable to create workqueue\n");
1115 goto fail_free_dma;
1116 }
1117 INIT_WORK(&espi->msg_work, ep93xx_spi_work);
1118 INIT_LIST_HEAD(&espi->msg_queue);
1119 espi->running = true;
1120
1121 /* make sure that the hardware is disabled */
1122 ep93xx_spi_write_u8(espi, SSPCR1, 0);
1123
1124 error = spi_register_master(master);
1125 if (error) {
1126 dev_err(&pdev->dev, "failed to register SPI master\n");
1127 goto fail_free_queue;
1128 }
1129
1130 dev_info(&pdev->dev, "EP93xx SPI Controller at 0x%08lx irq %d\n",
1131 (unsigned long)res->start, espi->irq);
1132
1133 return 0;
1134
1135fail_free_queue:
1136 destroy_workqueue(espi->wq);
1137fail_free_dma:
1138 ep93xx_spi_release_dma(espi);
1139 free_irq(espi->irq, espi);
1140fail_unmap_regs:
1141 iounmap(espi->regs_base);
1142fail_free_mem:
1143 release_mem_region(res->start, resource_size(res));
1144fail_put_clock:
1145 clk_put(espi->clk);
1146fail_release_master:
1147 spi_master_put(master);
1148 platform_set_drvdata(pdev, NULL);
1149
1150 return error;
1151}
1152
1153static int __exit ep93xx_spi_remove(struct platform_device *pdev)
1154{
1155 struct spi_master *master = platform_get_drvdata(pdev);
1156 struct ep93xx_spi *espi = spi_master_get_devdata(master);
1157 struct resource *res;
1158
1159 spin_lock_irq(&espi->lock);
1160 espi->running = false;
1161 spin_unlock_irq(&espi->lock);
1162
1163 destroy_workqueue(espi->wq);
1164
1165 /*
1166 * Complete remaining messages with %-ESHUTDOWN status.
1167 */
1168 spin_lock_irq(&espi->lock);
1169 while (!list_empty(&espi->msg_queue)) {
1170 struct spi_message *msg;
1171
1172 msg = list_first_entry(&espi->msg_queue,
1173 struct spi_message, queue);
1174 list_del_init(&msg->queue);
1175 msg->status = -ESHUTDOWN;
1176 spin_unlock_irq(&espi->lock);
1177 msg->complete(msg->context);
1178 spin_lock_irq(&espi->lock);
1179 }
1180 spin_unlock_irq(&espi->lock);
1181
1182 ep93xx_spi_release_dma(espi);
1183 free_irq(espi->irq, espi);
1184 iounmap(espi->regs_base);
1185 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1186 release_mem_region(res->start, resource_size(res));
1187 clk_put(espi->clk);
1188 platform_set_drvdata(pdev, NULL);
1189
1190 spi_unregister_master(master);
1191 return 0;
1192}
1193
1194static struct platform_driver ep93xx_spi_driver = {
1195 .driver = {
1196 .name = "ep93xx-spi",
1197 .owner = THIS_MODULE,
1198 },
1199 .remove = __exit_p(ep93xx_spi_remove),
1200};
1201
1202static int __init ep93xx_spi_init(void)
1203{
1204 return platform_driver_probe(&ep93xx_spi_driver, ep93xx_spi_probe);
1205}
1206module_init(ep93xx_spi_init);
1207
1208static void __exit ep93xx_spi_exit(void)
1209{
1210 platform_driver_unregister(&ep93xx_spi_driver);
1211}
1212module_exit(ep93xx_spi_exit);
1213
1214MODULE_DESCRIPTION("EP93xx SPI Controller driver");
1215MODULE_AUTHOR("Mika Westerberg <mika.westerberg@iki.fi>");
1216MODULE_LICENSE("GPL");
1217MODULE_ALIAS("platform:ep93xx-spi");