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1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2016 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27#ifndef _I40E_TXRX_H_
28#define _I40E_TXRX_H_
29
30/* Interrupt Throttling and Rate Limiting Goodies */
31
32#define I40E_MAX_ITR 0x0FF0 /* reg uses 2 usec resolution */
33#define I40E_MIN_ITR 0x0001 /* reg uses 2 usec resolution */
34#define I40E_ITR_100K 0x0005
35#define I40E_ITR_50K 0x000A
36#define I40E_ITR_20K 0x0019
37#define I40E_ITR_18K 0x001B
38#define I40E_ITR_8K 0x003E
39#define I40E_ITR_4K 0x007A
40#define I40E_MAX_INTRL 0x3B /* reg uses 4 usec resolution */
41#define I40E_ITR_RX_DEF I40E_ITR_20K
42#define I40E_ITR_TX_DEF I40E_ITR_20K
43#define I40E_ITR_DYNAMIC 0x8000 /* use top bit as a flag */
44#define I40E_MIN_INT_RATE 250 /* ~= 1000000 / (I40E_MAX_ITR * 2) */
45#define I40E_MAX_INT_RATE 500000 /* == 1000000 / (I40E_MIN_ITR * 2) */
46#define I40E_DEFAULT_IRQ_WORK 256
47#define ITR_TO_REG(setting) ((setting & ~I40E_ITR_DYNAMIC) >> 1)
48#define ITR_IS_DYNAMIC(setting) (!!(setting & I40E_ITR_DYNAMIC))
49#define ITR_REG_TO_USEC(itr_reg) (itr_reg << 1)
50/* 0x40 is the enable bit for interrupt rate limiting, and must be set if
51 * the value of the rate limit is non-zero
52 */
53#define INTRL_ENA BIT(6)
54#define INTRL_REG_TO_USEC(intrl) ((intrl & ~INTRL_ENA) << 2)
55#define INTRL_USEC_TO_REG(set) ((set) ? ((set) >> 2) | INTRL_ENA : 0)
56#define I40E_INTRL_8K 125 /* 8000 ints/sec */
57#define I40E_INTRL_62K 16 /* 62500 ints/sec */
58#define I40E_INTRL_83K 12 /* 83333 ints/sec */
59
60#define I40E_QUEUE_END_OF_LIST 0x7FF
61
62/* this enum matches hardware bits and is meant to be used by DYN_CTLN
63 * registers and QINT registers or more generally anywhere in the manual
64 * mentioning ITR_INDX, ITR_NONE cannot be used as an index 'n' into any
65 * register but instead is a special value meaning "don't update" ITR0/1/2.
66 */
67enum i40e_dyn_idx_t {
68 I40E_IDX_ITR0 = 0,
69 I40E_IDX_ITR1 = 1,
70 I40E_IDX_ITR2 = 2,
71 I40E_ITR_NONE = 3 /* ITR_NONE must not be used as an index */
72};
73
74/* these are indexes into ITRN registers */
75#define I40E_RX_ITR I40E_IDX_ITR0
76#define I40E_TX_ITR I40E_IDX_ITR1
77#define I40E_PE_ITR I40E_IDX_ITR2
78
79/* Supported RSS offloads */
80#define I40E_DEFAULT_RSS_HENA ( \
81 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \
82 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \
83 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \
84 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \
85 BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV4) | \
86 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \
87 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \
88 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \
89 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \
90 BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV6) | \
91 BIT_ULL(I40E_FILTER_PCTYPE_L2_PAYLOAD))
92
93#define I40E_DEFAULT_RSS_HENA_EXPANDED (I40E_DEFAULT_RSS_HENA | \
94 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \
95 BIT_ULL(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \
96 BIT_ULL(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \
97 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK) | \
98 BIT_ULL(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \
99 BIT_ULL(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
100
101#define i40e_pf_get_default_rss_hena(pf) \
102 (((pf)->flags & I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE) ? \
103 I40E_DEFAULT_RSS_HENA_EXPANDED : I40E_DEFAULT_RSS_HENA)
104
105/* Supported Rx Buffer Sizes */
106#define I40E_RXBUFFER_512 512 /* Used for packet split */
107#define I40E_RXBUFFER_2048 2048
108#define I40E_RXBUFFER_3072 3072 /* For FCoE MTU of 2158 */
109#define I40E_RXBUFFER_4096 4096
110#define I40E_RXBUFFER_8192 8192
111#define I40E_MAX_RXBUFFER 9728 /* largest size for single descriptor */
112
113/* NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we
114 * reserve 2 more, and skb_shared_info adds an additional 384 bytes more,
115 * this adds up to 512 bytes of extra data meaning the smallest allocation
116 * we could have is 1K.
117 * i.e. RXBUFFER_512 --> size-1024 slab
118 */
119#define I40E_RX_HDR_SIZE I40E_RXBUFFER_512
120
121/* How many Rx Buffers do we bundle into one write to the hardware ? */
122#define I40E_RX_BUFFER_WRITE 16 /* Must be power of 2 */
123#define I40E_RX_INCREMENT(r, i) \
124 do { \
125 (i)++; \
126 if ((i) == (r)->count) \
127 i = 0; \
128 r->next_to_clean = i; \
129 } while (0)
130
131#define I40E_RX_NEXT_DESC(r, i, n) \
132 do { \
133 (i)++; \
134 if ((i) == (r)->count) \
135 i = 0; \
136 (n) = I40E_RX_DESC((r), (i)); \
137 } while (0)
138
139#define I40E_RX_NEXT_DESC_PREFETCH(r, i, n) \
140 do { \
141 I40E_RX_NEXT_DESC((r), (i), (n)); \
142 prefetch((n)); \
143 } while (0)
144
145#define i40e_rx_desc i40e_32byte_rx_desc
146
147#define I40E_MAX_BUFFER_TXD 8
148#define I40E_MIN_TX_LEN 17
149#define I40E_MAX_DATA_PER_TXD 8192
150
151/* Tx Descriptors needed, worst case */
152#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), I40E_MAX_DATA_PER_TXD)
153#define DESC_NEEDED (MAX_SKB_FRAGS + 4)
154#define I40E_MIN_DESC_PENDING 4
155
156#define I40E_TX_FLAGS_HW_VLAN BIT(1)
157#define I40E_TX_FLAGS_SW_VLAN BIT(2)
158#define I40E_TX_FLAGS_TSO BIT(3)
159#define I40E_TX_FLAGS_IPV4 BIT(4)
160#define I40E_TX_FLAGS_IPV6 BIT(5)
161#define I40E_TX_FLAGS_FCCRC BIT(6)
162#define I40E_TX_FLAGS_FSO BIT(7)
163#define I40E_TX_FLAGS_TSYN BIT(8)
164#define I40E_TX_FLAGS_FD_SB BIT(9)
165#define I40E_TX_FLAGS_UDP_TUNNEL BIT(10)
166#define I40E_TX_FLAGS_VLAN_MASK 0xffff0000
167#define I40E_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000
168#define I40E_TX_FLAGS_VLAN_PRIO_SHIFT 29
169#define I40E_TX_FLAGS_VLAN_SHIFT 16
170
171struct i40e_tx_buffer {
172 struct i40e_tx_desc *next_to_watch;
173 union {
174 struct sk_buff *skb;
175 void *raw_buf;
176 };
177 unsigned int bytecount;
178 unsigned short gso_segs;
179
180 DEFINE_DMA_UNMAP_ADDR(dma);
181 DEFINE_DMA_UNMAP_LEN(len);
182 u32 tx_flags;
183};
184
185struct i40e_rx_buffer {
186 struct sk_buff *skb;
187 void *hdr_buf;
188 dma_addr_t dma;
189 struct page *page;
190 dma_addr_t page_dma;
191 unsigned int page_offset;
192};
193
194struct i40e_queue_stats {
195 u64 packets;
196 u64 bytes;
197};
198
199struct i40e_tx_queue_stats {
200 u64 restart_queue;
201 u64 tx_busy;
202 u64 tx_done_old;
203 u64 tx_linearize;
204 u64 tx_force_wb;
205 u64 tx_lost_interrupt;
206};
207
208struct i40e_rx_queue_stats {
209 u64 non_eop_descs;
210 u64 alloc_page_failed;
211 u64 alloc_buff_failed;
212 u64 page_reuse_count;
213 u64 realloc_count;
214};
215
216enum i40e_ring_state_t {
217 __I40E_TX_FDIR_INIT_DONE,
218 __I40E_TX_XPS_INIT_DONE,
219 __I40E_RX_PS_ENABLED,
220 __I40E_RX_16BYTE_DESC_ENABLED,
221};
222
223#define ring_is_ps_enabled(ring) \
224 test_bit(__I40E_RX_PS_ENABLED, &(ring)->state)
225#define set_ring_ps_enabled(ring) \
226 set_bit(__I40E_RX_PS_ENABLED, &(ring)->state)
227#define clear_ring_ps_enabled(ring) \
228 clear_bit(__I40E_RX_PS_ENABLED, &(ring)->state)
229#define ring_is_16byte_desc_enabled(ring) \
230 test_bit(__I40E_RX_16BYTE_DESC_ENABLED, &(ring)->state)
231#define set_ring_16byte_desc_enabled(ring) \
232 set_bit(__I40E_RX_16BYTE_DESC_ENABLED, &(ring)->state)
233#define clear_ring_16byte_desc_enabled(ring) \
234 clear_bit(__I40E_RX_16BYTE_DESC_ENABLED, &(ring)->state)
235
236/* struct that defines a descriptor ring, associated with a VSI */
237struct i40e_ring {
238 struct i40e_ring *next; /* pointer to next ring in q_vector */
239 void *desc; /* Descriptor ring memory */
240 struct device *dev; /* Used for DMA mapping */
241 struct net_device *netdev; /* netdev ring maps to */
242 union {
243 struct i40e_tx_buffer *tx_bi;
244 struct i40e_rx_buffer *rx_bi;
245 };
246 unsigned long state;
247 u16 queue_index; /* Queue number of ring */
248 u8 dcb_tc; /* Traffic class of ring */
249 u8 __iomem *tail;
250
251 /* high bit set means dynamic, use accessor routines to read/write.
252 * hardware only supports 2us resolution for the ITR registers.
253 * these values always store the USER setting, and must be converted
254 * before programming to a register.
255 */
256 u16 rx_itr_setting;
257 u16 tx_itr_setting;
258
259 u16 count; /* Number of descriptors */
260 u16 reg_idx; /* HW register index of the ring */
261 u16 rx_hdr_len;
262 u16 rx_buf_len;
263 u8 dtype;
264#define I40E_RX_DTYPE_NO_SPLIT 0
265#define I40E_RX_DTYPE_HEADER_SPLIT 1
266#define I40E_RX_DTYPE_SPLIT_ALWAYS 2
267#define I40E_RX_SPLIT_L2 0x1
268#define I40E_RX_SPLIT_IP 0x2
269#define I40E_RX_SPLIT_TCP_UDP 0x4
270#define I40E_RX_SPLIT_SCTP 0x8
271
272 /* used in interrupt processing */
273 u16 next_to_use;
274 u16 next_to_clean;
275
276 u8 atr_sample_rate;
277 u8 atr_count;
278
279 unsigned long last_rx_timestamp;
280
281 bool ring_active; /* is ring online or not */
282 bool arm_wb; /* do something to arm write back */
283 u8 packet_stride;
284
285 u16 flags;
286#define I40E_TXR_FLAGS_WB_ON_ITR BIT(0)
287#define I40E_TXR_FLAGS_LAST_XMIT_MORE_SET BIT(2)
288
289 /* stats structs */
290 struct i40e_queue_stats stats;
291 struct u64_stats_sync syncp;
292 union {
293 struct i40e_tx_queue_stats tx_stats;
294 struct i40e_rx_queue_stats rx_stats;
295 };
296
297 unsigned int size; /* length of descriptor ring in bytes */
298 dma_addr_t dma; /* physical address of ring */
299
300 struct i40e_vsi *vsi; /* Backreference to associated VSI */
301 struct i40e_q_vector *q_vector; /* Backreference to associated vector */
302
303 struct rcu_head rcu; /* to avoid race on free */
304} ____cacheline_internodealigned_in_smp;
305
306enum i40e_latency_range {
307 I40E_LOWEST_LATENCY = 0,
308 I40E_LOW_LATENCY = 1,
309 I40E_BULK_LATENCY = 2,
310 I40E_ULTRA_LATENCY = 3,
311};
312
313struct i40e_ring_container {
314 /* array of pointers to rings */
315 struct i40e_ring *ring;
316 unsigned int total_bytes; /* total bytes processed this int */
317 unsigned int total_packets; /* total packets processed this int */
318 u16 count;
319 enum i40e_latency_range latency_range;
320 u16 itr;
321};
322
323/* iterator for handling rings in ring container */
324#define i40e_for_each_ring(pos, head) \
325 for (pos = (head).ring; pos != NULL; pos = pos->next)
326
327bool i40e_alloc_rx_buffers_ps(struct i40e_ring *rxr, u16 cleaned_count);
328bool i40e_alloc_rx_buffers_1buf(struct i40e_ring *rxr, u16 cleaned_count);
329void i40e_alloc_rx_headers(struct i40e_ring *rxr);
330netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
331void i40e_clean_tx_ring(struct i40e_ring *tx_ring);
332void i40e_clean_rx_ring(struct i40e_ring *rx_ring);
333int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring);
334int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring);
335void i40e_free_tx_resources(struct i40e_ring *tx_ring);
336void i40e_free_rx_resources(struct i40e_ring *rx_ring);
337int i40e_napi_poll(struct napi_struct *napi, int budget);
338#ifdef I40E_FCOE
339void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
340 struct i40e_tx_buffer *first, u32 tx_flags,
341 const u8 hdr_len, u32 td_cmd, u32 td_offset);
342int i40e_tx_prepare_vlan_flags(struct sk_buff *skb,
343 struct i40e_ring *tx_ring, u32 *flags);
344#endif
345void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector);
346u32 i40e_get_tx_pending(struct i40e_ring *ring, bool in_sw);
347int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size);
348bool __i40e_chk_linearize(struct sk_buff *skb);
349
350/**
351 * i40e_get_head - Retrieve head from head writeback
352 * @tx_ring: tx ring to fetch head of
353 *
354 * Returns value of Tx ring head based on value stored
355 * in head write-back location
356 **/
357static inline u32 i40e_get_head(struct i40e_ring *tx_ring)
358{
359 void *head = (struct i40e_tx_desc *)tx_ring->desc + tx_ring->count;
360
361 return le32_to_cpu(*(volatile __le32 *)head);
362}
363
364/**
365 * i40e_xmit_descriptor_count - calculate number of Tx descriptors needed
366 * @skb: send buffer
367 * @tx_ring: ring to send buffer on
368 *
369 * Returns number of data descriptors needed for this skb. Returns 0 to indicate
370 * there is not enough descriptors available in this ring since we need at least
371 * one descriptor.
372 **/
373static inline int i40e_xmit_descriptor_count(struct sk_buff *skb)
374{
375 const struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
376 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
377 int count = 0, size = skb_headlen(skb);
378
379 for (;;) {
380 count += TXD_USE_COUNT(size);
381
382 if (!nr_frags--)
383 break;
384
385 size = skb_frag_size(frag++);
386 }
387
388 return count;
389}
390
391/**
392 * i40e_maybe_stop_tx - 1st level check for Tx stop conditions
393 * @tx_ring: the ring to be checked
394 * @size: the size buffer we want to assure is available
395 *
396 * Returns 0 if stop is not needed
397 **/
398static inline int i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
399{
400 if (likely(I40E_DESC_UNUSED(tx_ring) >= size))
401 return 0;
402 return __i40e_maybe_stop_tx(tx_ring, size);
403}
404
405/**
406 * i40e_chk_linearize - Check if there are more than 8 fragments per packet
407 * @skb: send buffer
408 * @count: number of buffers used
409 *
410 * Note: Our HW can't scatter-gather more than 8 fragments to build
411 * a packet on the wire and so we need to figure out the cases where we
412 * need to linearize the skb.
413 **/
414static inline bool i40e_chk_linearize(struct sk_buff *skb, int count)
415{
416 /* Both TSO and single send will work if count is less than 8 */
417 if (likely(count < I40E_MAX_BUFFER_TXD))
418 return false;
419
420 if (skb_is_gso(skb))
421 return __i40e_chk_linearize(skb);
422
423 /* we can support up to 8 data buffers for a single send */
424 return count != I40E_MAX_BUFFER_TXD;
425}
426#endif /* _I40E_TXRX_H_ */