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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * arch/sparc64/mm/init.c
4 *
5 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
6 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
7 */
8
9#include <linux/extable.h>
10#include <linux/kernel.h>
11#include <linux/sched.h>
12#include <linux/string.h>
13#include <linux/init.h>
14#include <linux/bootmem.h>
15#include <linux/mm.h>
16#include <linux/hugetlb.h>
17#include <linux/initrd.h>
18#include <linux/swap.h>
19#include <linux/pagemap.h>
20#include <linux/poison.h>
21#include <linux/fs.h>
22#include <linux/seq_file.h>
23#include <linux/kprobes.h>
24#include <linux/cache.h>
25#include <linux/sort.h>
26#include <linux/ioport.h>
27#include <linux/percpu.h>
28#include <linux/memblock.h>
29#include <linux/mmzone.h>
30#include <linux/gfp.h>
31
32#include <asm/head.h>
33#include <asm/page.h>
34#include <asm/pgalloc.h>
35#include <asm/pgtable.h>
36#include <asm/oplib.h>
37#include <asm/iommu.h>
38#include <asm/io.h>
39#include <linux/uaccess.h>
40#include <asm/mmu_context.h>
41#include <asm/tlbflush.h>
42#include <asm/dma.h>
43#include <asm/starfire.h>
44#include <asm/tlb.h>
45#include <asm/spitfire.h>
46#include <asm/sections.h>
47#include <asm/tsb.h>
48#include <asm/hypervisor.h>
49#include <asm/prom.h>
50#include <asm/mdesc.h>
51#include <asm/cpudata.h>
52#include <asm/setup.h>
53#include <asm/irq.h>
54
55#include "init_64.h"
56
57unsigned long kern_linear_pte_xor[4] __read_mostly;
58static unsigned long page_cache4v_flag;
59
60/* A bitmap, two bits for every 256MB of physical memory. These two
61 * bits determine what page size we use for kernel linear
62 * translations. They form an index into kern_linear_pte_xor[]. The
63 * value in the indexed slot is XOR'd with the TLB miss virtual
64 * address to form the resulting TTE. The mapping is:
65 *
66 * 0 ==> 4MB
67 * 1 ==> 256MB
68 * 2 ==> 2GB
69 * 3 ==> 16GB
70 *
71 * All sun4v chips support 256MB pages. Only SPARC-T4 and later
72 * support 2GB pages, and hopefully future cpus will support the 16GB
73 * pages as well. For slots 2 and 3, we encode a 256MB TTE xor there
74 * if these larger page sizes are not supported by the cpu.
75 *
76 * It would be nice to determine this from the machine description
77 * 'cpu' properties, but we need to have this table setup before the
78 * MDESC is initialized.
79 */
80
81#ifndef CONFIG_DEBUG_PAGEALLOC
82/* A special kernel TSB for 4MB, 256MB, 2GB and 16GB linear mappings.
83 * Space is allocated for this right after the trap table in
84 * arch/sparc64/kernel/head.S
85 */
86extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
87#endif
88extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
89
90static unsigned long cpu_pgsz_mask;
91
92#define MAX_BANKS 1024
93
94static struct linux_prom64_registers pavail[MAX_BANKS];
95static int pavail_ents;
96
97u64 numa_latency[MAX_NUMNODES][MAX_NUMNODES];
98
99static int cmp_p64(const void *a, const void *b)
100{
101 const struct linux_prom64_registers *x = a, *y = b;
102
103 if (x->phys_addr > y->phys_addr)
104 return 1;
105 if (x->phys_addr < y->phys_addr)
106 return -1;
107 return 0;
108}
109
110static void __init read_obp_memory(const char *property,
111 struct linux_prom64_registers *regs,
112 int *num_ents)
113{
114 phandle node = prom_finddevice("/memory");
115 int prop_size = prom_getproplen(node, property);
116 int ents, ret, i;
117
118 ents = prop_size / sizeof(struct linux_prom64_registers);
119 if (ents > MAX_BANKS) {
120 prom_printf("The machine has more %s property entries than "
121 "this kernel can support (%d).\n",
122 property, MAX_BANKS);
123 prom_halt();
124 }
125
126 ret = prom_getproperty(node, property, (char *) regs, prop_size);
127 if (ret == -1) {
128 prom_printf("Couldn't get %s property from /memory.\n",
129 property);
130 prom_halt();
131 }
132
133 /* Sanitize what we got from the firmware, by page aligning
134 * everything.
135 */
136 for (i = 0; i < ents; i++) {
137 unsigned long base, size;
138
139 base = regs[i].phys_addr;
140 size = regs[i].reg_size;
141
142 size &= PAGE_MASK;
143 if (base & ~PAGE_MASK) {
144 unsigned long new_base = PAGE_ALIGN(base);
145
146 size -= new_base - base;
147 if ((long) size < 0L)
148 size = 0UL;
149 base = new_base;
150 }
151 if (size == 0UL) {
152 /* If it is empty, simply get rid of it.
153 * This simplifies the logic of the other
154 * functions that process these arrays.
155 */
156 memmove(®s[i], ®s[i + 1],
157 (ents - i - 1) * sizeof(regs[0]));
158 i--;
159 ents--;
160 continue;
161 }
162 regs[i].phys_addr = base;
163 regs[i].reg_size = size;
164 }
165
166 *num_ents = ents;
167
168 sort(regs, ents, sizeof(struct linux_prom64_registers),
169 cmp_p64, NULL);
170}
171
172/* Kernel physical address base and size in bytes. */
173unsigned long kern_base __read_mostly;
174unsigned long kern_size __read_mostly;
175
176/* Initial ramdisk setup */
177extern unsigned long sparc_ramdisk_image64;
178extern unsigned int sparc_ramdisk_image;
179extern unsigned int sparc_ramdisk_size;
180
181struct page *mem_map_zero __read_mostly;
182EXPORT_SYMBOL(mem_map_zero);
183
184unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
185
186unsigned long sparc64_kern_pri_context __read_mostly;
187unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
188unsigned long sparc64_kern_sec_context __read_mostly;
189
190int num_kernel_image_mappings;
191
192#ifdef CONFIG_DEBUG_DCFLUSH
193atomic_t dcpage_flushes = ATOMIC_INIT(0);
194#ifdef CONFIG_SMP
195atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
196#endif
197#endif
198
199inline void flush_dcache_page_impl(struct page *page)
200{
201 BUG_ON(tlb_type == hypervisor);
202#ifdef CONFIG_DEBUG_DCFLUSH
203 atomic_inc(&dcpage_flushes);
204#endif
205
206#ifdef DCACHE_ALIASING_POSSIBLE
207 __flush_dcache_page(page_address(page),
208 ((tlb_type == spitfire) &&
209 page_mapping_file(page) != NULL));
210#else
211 if (page_mapping_file(page) != NULL &&
212 tlb_type == spitfire)
213 __flush_icache_page(__pa(page_address(page)));
214#endif
215}
216
217#define PG_dcache_dirty PG_arch_1
218#define PG_dcache_cpu_shift 32UL
219#define PG_dcache_cpu_mask \
220 ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
221
222#define dcache_dirty_cpu(page) \
223 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
224
225static inline void set_dcache_dirty(struct page *page, int this_cpu)
226{
227 unsigned long mask = this_cpu;
228 unsigned long non_cpu_bits;
229
230 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
231 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
232
233 __asm__ __volatile__("1:\n\t"
234 "ldx [%2], %%g7\n\t"
235 "and %%g7, %1, %%g1\n\t"
236 "or %%g1, %0, %%g1\n\t"
237 "casx [%2], %%g7, %%g1\n\t"
238 "cmp %%g7, %%g1\n\t"
239 "bne,pn %%xcc, 1b\n\t"
240 " nop"
241 : /* no outputs */
242 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
243 : "g1", "g7");
244}
245
246static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
247{
248 unsigned long mask = (1UL << PG_dcache_dirty);
249
250 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
251 "1:\n\t"
252 "ldx [%2], %%g7\n\t"
253 "srlx %%g7, %4, %%g1\n\t"
254 "and %%g1, %3, %%g1\n\t"
255 "cmp %%g1, %0\n\t"
256 "bne,pn %%icc, 2f\n\t"
257 " andn %%g7, %1, %%g1\n\t"
258 "casx [%2], %%g7, %%g1\n\t"
259 "cmp %%g7, %%g1\n\t"
260 "bne,pn %%xcc, 1b\n\t"
261 " nop\n"
262 "2:"
263 : /* no outputs */
264 : "r" (cpu), "r" (mask), "r" (&page->flags),
265 "i" (PG_dcache_cpu_mask),
266 "i" (PG_dcache_cpu_shift)
267 : "g1", "g7");
268}
269
270static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
271{
272 unsigned long tsb_addr = (unsigned long) ent;
273
274 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
275 tsb_addr = __pa(tsb_addr);
276
277 __tsb_insert(tsb_addr, tag, pte);
278}
279
280unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
281
282static void flush_dcache(unsigned long pfn)
283{
284 struct page *page;
285
286 page = pfn_to_page(pfn);
287 if (page) {
288 unsigned long pg_flags;
289
290 pg_flags = page->flags;
291 if (pg_flags & (1UL << PG_dcache_dirty)) {
292 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
293 PG_dcache_cpu_mask);
294 int this_cpu = get_cpu();
295
296 /* This is just to optimize away some function calls
297 * in the SMP case.
298 */
299 if (cpu == this_cpu)
300 flush_dcache_page_impl(page);
301 else
302 smp_flush_dcache_page_impl(page, cpu);
303
304 clear_dcache_dirty_cpu(page, cpu);
305
306 put_cpu();
307 }
308 }
309}
310
311/* mm->context.lock must be held */
312static void __update_mmu_tsb_insert(struct mm_struct *mm, unsigned long tsb_index,
313 unsigned long tsb_hash_shift, unsigned long address,
314 unsigned long tte)
315{
316 struct tsb *tsb = mm->context.tsb_block[tsb_index].tsb;
317 unsigned long tag;
318
319 if (unlikely(!tsb))
320 return;
321
322 tsb += ((address >> tsb_hash_shift) &
323 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
324 tag = (address >> 22UL);
325 tsb_insert(tsb, tag, tte);
326}
327
328#ifdef CONFIG_HUGETLB_PAGE
329static void __init add_huge_page_size(unsigned long size)
330{
331 unsigned int order;
332
333 if (size_to_hstate(size))
334 return;
335
336 order = ilog2(size) - PAGE_SHIFT;
337 hugetlb_add_hstate(order);
338}
339
340static int __init hugetlbpage_init(void)
341{
342 add_huge_page_size(1UL << HPAGE_64K_SHIFT);
343 add_huge_page_size(1UL << HPAGE_SHIFT);
344 add_huge_page_size(1UL << HPAGE_256MB_SHIFT);
345 add_huge_page_size(1UL << HPAGE_2GB_SHIFT);
346
347 return 0;
348}
349
350arch_initcall(hugetlbpage_init);
351
352static void __init pud_huge_patch(void)
353{
354 struct pud_huge_patch_entry *p;
355 unsigned long addr;
356
357 p = &__pud_huge_patch;
358 addr = p->addr;
359 *(unsigned int *)addr = p->insn;
360
361 __asm__ __volatile__("flush %0" : : "r" (addr));
362}
363
364static int __init setup_hugepagesz(char *string)
365{
366 unsigned long long hugepage_size;
367 unsigned int hugepage_shift;
368 unsigned short hv_pgsz_idx;
369 unsigned int hv_pgsz_mask;
370 int rc = 0;
371
372 hugepage_size = memparse(string, &string);
373 hugepage_shift = ilog2(hugepage_size);
374
375 switch (hugepage_shift) {
376 case HPAGE_16GB_SHIFT:
377 hv_pgsz_mask = HV_PGSZ_MASK_16GB;
378 hv_pgsz_idx = HV_PGSZ_IDX_16GB;
379 pud_huge_patch();
380 break;
381 case HPAGE_2GB_SHIFT:
382 hv_pgsz_mask = HV_PGSZ_MASK_2GB;
383 hv_pgsz_idx = HV_PGSZ_IDX_2GB;
384 break;
385 case HPAGE_256MB_SHIFT:
386 hv_pgsz_mask = HV_PGSZ_MASK_256MB;
387 hv_pgsz_idx = HV_PGSZ_IDX_256MB;
388 break;
389 case HPAGE_SHIFT:
390 hv_pgsz_mask = HV_PGSZ_MASK_4MB;
391 hv_pgsz_idx = HV_PGSZ_IDX_4MB;
392 break;
393 case HPAGE_64K_SHIFT:
394 hv_pgsz_mask = HV_PGSZ_MASK_64K;
395 hv_pgsz_idx = HV_PGSZ_IDX_64K;
396 break;
397 default:
398 hv_pgsz_mask = 0;
399 }
400
401 if ((hv_pgsz_mask & cpu_pgsz_mask) == 0U) {
402 hugetlb_bad_size();
403 pr_err("hugepagesz=%llu not supported by MMU.\n",
404 hugepage_size);
405 goto out;
406 }
407
408 add_huge_page_size(hugepage_size);
409 rc = 1;
410
411out:
412 return rc;
413}
414__setup("hugepagesz=", setup_hugepagesz);
415#endif /* CONFIG_HUGETLB_PAGE */
416
417void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
418{
419 struct mm_struct *mm;
420 unsigned long flags;
421 bool is_huge_tsb;
422 pte_t pte = *ptep;
423
424 if (tlb_type != hypervisor) {
425 unsigned long pfn = pte_pfn(pte);
426
427 if (pfn_valid(pfn))
428 flush_dcache(pfn);
429 }
430
431 mm = vma->vm_mm;
432
433 /* Don't insert a non-valid PTE into the TSB, we'll deadlock. */
434 if (!pte_accessible(mm, pte))
435 return;
436
437 spin_lock_irqsave(&mm->context.lock, flags);
438
439 is_huge_tsb = false;
440#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
441 if (mm->context.hugetlb_pte_count || mm->context.thp_pte_count) {
442 unsigned long hugepage_size = PAGE_SIZE;
443
444 if (is_vm_hugetlb_page(vma))
445 hugepage_size = huge_page_size(hstate_vma(vma));
446
447 if (hugepage_size >= PUD_SIZE) {
448 unsigned long mask = 0x1ffc00000UL;
449
450 /* Transfer bits [32:22] from address to resolve
451 * at 4M granularity.
452 */
453 pte_val(pte) &= ~mask;
454 pte_val(pte) |= (address & mask);
455 } else if (hugepage_size >= PMD_SIZE) {
456 /* We are fabricating 8MB pages using 4MB
457 * real hw pages.
458 */
459 pte_val(pte) |= (address & (1UL << REAL_HPAGE_SHIFT));
460 }
461
462 if (hugepage_size >= PMD_SIZE) {
463 __update_mmu_tsb_insert(mm, MM_TSB_HUGE,
464 REAL_HPAGE_SHIFT, address, pte_val(pte));
465 is_huge_tsb = true;
466 }
467 }
468#endif
469 if (!is_huge_tsb)
470 __update_mmu_tsb_insert(mm, MM_TSB_BASE, PAGE_SHIFT,
471 address, pte_val(pte));
472
473 spin_unlock_irqrestore(&mm->context.lock, flags);
474}
475
476void flush_dcache_page(struct page *page)
477{
478 struct address_space *mapping;
479 int this_cpu;
480
481 if (tlb_type == hypervisor)
482 return;
483
484 /* Do not bother with the expensive D-cache flush if it
485 * is merely the zero page. The 'bigcore' testcase in GDB
486 * causes this case to run millions of times.
487 */
488 if (page == ZERO_PAGE(0))
489 return;
490
491 this_cpu = get_cpu();
492
493 mapping = page_mapping_file(page);
494 if (mapping && !mapping_mapped(mapping)) {
495 int dirty = test_bit(PG_dcache_dirty, &page->flags);
496 if (dirty) {
497 int dirty_cpu = dcache_dirty_cpu(page);
498
499 if (dirty_cpu == this_cpu)
500 goto out;
501 smp_flush_dcache_page_impl(page, dirty_cpu);
502 }
503 set_dcache_dirty(page, this_cpu);
504 } else {
505 /* We could delay the flush for the !page_mapping
506 * case too. But that case is for exec env/arg
507 * pages and those are %99 certainly going to get
508 * faulted into the tlb (and thus flushed) anyways.
509 */
510 flush_dcache_page_impl(page);
511 }
512
513out:
514 put_cpu();
515}
516EXPORT_SYMBOL(flush_dcache_page);
517
518void __kprobes flush_icache_range(unsigned long start, unsigned long end)
519{
520 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
521 if (tlb_type == spitfire) {
522 unsigned long kaddr;
523
524 /* This code only runs on Spitfire cpus so this is
525 * why we can assume _PAGE_PADDR_4U.
526 */
527 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
528 unsigned long paddr, mask = _PAGE_PADDR_4U;
529
530 if (kaddr >= PAGE_OFFSET)
531 paddr = kaddr & mask;
532 else {
533 pgd_t *pgdp = pgd_offset_k(kaddr);
534 pud_t *pudp = pud_offset(pgdp, kaddr);
535 pmd_t *pmdp = pmd_offset(pudp, kaddr);
536 pte_t *ptep = pte_offset_kernel(pmdp, kaddr);
537
538 paddr = pte_val(*ptep) & mask;
539 }
540 __flush_icache_page(paddr);
541 }
542 }
543}
544EXPORT_SYMBOL(flush_icache_range);
545
546void mmu_info(struct seq_file *m)
547{
548 static const char *pgsz_strings[] = {
549 "8K", "64K", "512K", "4MB", "32MB",
550 "256MB", "2GB", "16GB",
551 };
552 int i, printed;
553
554 if (tlb_type == cheetah)
555 seq_printf(m, "MMU Type\t: Cheetah\n");
556 else if (tlb_type == cheetah_plus)
557 seq_printf(m, "MMU Type\t: Cheetah+\n");
558 else if (tlb_type == spitfire)
559 seq_printf(m, "MMU Type\t: Spitfire\n");
560 else if (tlb_type == hypervisor)
561 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
562 else
563 seq_printf(m, "MMU Type\t: ???\n");
564
565 seq_printf(m, "MMU PGSZs\t: ");
566 printed = 0;
567 for (i = 0; i < ARRAY_SIZE(pgsz_strings); i++) {
568 if (cpu_pgsz_mask & (1UL << i)) {
569 seq_printf(m, "%s%s",
570 printed ? "," : "", pgsz_strings[i]);
571 printed++;
572 }
573 }
574 seq_putc(m, '\n');
575
576#ifdef CONFIG_DEBUG_DCFLUSH
577 seq_printf(m, "DCPageFlushes\t: %d\n",
578 atomic_read(&dcpage_flushes));
579#ifdef CONFIG_SMP
580 seq_printf(m, "DCPageFlushesXC\t: %d\n",
581 atomic_read(&dcpage_flushes_xcall));
582#endif /* CONFIG_SMP */
583#endif /* CONFIG_DEBUG_DCFLUSH */
584}
585
586struct linux_prom_translation prom_trans[512] __read_mostly;
587unsigned int prom_trans_ents __read_mostly;
588
589unsigned long kern_locked_tte_data;
590
591/* The obp translations are saved based on 8k pagesize, since obp can
592 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
593 * HI_OBP_ADDRESS range are handled in ktlb.S.
594 */
595static inline int in_obp_range(unsigned long vaddr)
596{
597 return (vaddr >= LOW_OBP_ADDRESS &&
598 vaddr < HI_OBP_ADDRESS);
599}
600
601static int cmp_ptrans(const void *a, const void *b)
602{
603 const struct linux_prom_translation *x = a, *y = b;
604
605 if (x->virt > y->virt)
606 return 1;
607 if (x->virt < y->virt)
608 return -1;
609 return 0;
610}
611
612/* Read OBP translations property into 'prom_trans[]'. */
613static void __init read_obp_translations(void)
614{
615 int n, node, ents, first, last, i;
616
617 node = prom_finddevice("/virtual-memory");
618 n = prom_getproplen(node, "translations");
619 if (unlikely(n == 0 || n == -1)) {
620 prom_printf("prom_mappings: Couldn't get size.\n");
621 prom_halt();
622 }
623 if (unlikely(n > sizeof(prom_trans))) {
624 prom_printf("prom_mappings: Size %d is too big.\n", n);
625 prom_halt();
626 }
627
628 if ((n = prom_getproperty(node, "translations",
629 (char *)&prom_trans[0],
630 sizeof(prom_trans))) == -1) {
631 prom_printf("prom_mappings: Couldn't get property.\n");
632 prom_halt();
633 }
634
635 n = n / sizeof(struct linux_prom_translation);
636
637 ents = n;
638
639 sort(prom_trans, ents, sizeof(struct linux_prom_translation),
640 cmp_ptrans, NULL);
641
642 /* Now kick out all the non-OBP entries. */
643 for (i = 0; i < ents; i++) {
644 if (in_obp_range(prom_trans[i].virt))
645 break;
646 }
647 first = i;
648 for (; i < ents; i++) {
649 if (!in_obp_range(prom_trans[i].virt))
650 break;
651 }
652 last = i;
653
654 for (i = 0; i < (last - first); i++) {
655 struct linux_prom_translation *src = &prom_trans[i + first];
656 struct linux_prom_translation *dest = &prom_trans[i];
657
658 *dest = *src;
659 }
660 for (; i < ents; i++) {
661 struct linux_prom_translation *dest = &prom_trans[i];
662 dest->virt = dest->size = dest->data = 0x0UL;
663 }
664
665 prom_trans_ents = last - first;
666
667 if (tlb_type == spitfire) {
668 /* Clear diag TTE bits. */
669 for (i = 0; i < prom_trans_ents; i++)
670 prom_trans[i].data &= ~0x0003fe0000000000UL;
671 }
672
673 /* Force execute bit on. */
674 for (i = 0; i < prom_trans_ents; i++)
675 prom_trans[i].data |= (tlb_type == hypervisor ?
676 _PAGE_EXEC_4V : _PAGE_EXEC_4U);
677}
678
679static void __init hypervisor_tlb_lock(unsigned long vaddr,
680 unsigned long pte,
681 unsigned long mmu)
682{
683 unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
684
685 if (ret != 0) {
686 prom_printf("hypervisor_tlb_lock[%lx:%x:%lx:%lx]: "
687 "errors with %lx\n", vaddr, 0, pte, mmu, ret);
688 prom_halt();
689 }
690}
691
692static unsigned long kern_large_tte(unsigned long paddr);
693
694static void __init remap_kernel(void)
695{
696 unsigned long phys_page, tte_vaddr, tte_data;
697 int i, tlb_ent = sparc64_highest_locked_tlbent();
698
699 tte_vaddr = (unsigned long) KERNBASE;
700 phys_page = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
701 tte_data = kern_large_tte(phys_page);
702
703 kern_locked_tte_data = tte_data;
704
705 /* Now lock us into the TLBs via Hypervisor or OBP. */
706 if (tlb_type == hypervisor) {
707 for (i = 0; i < num_kernel_image_mappings; i++) {
708 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
709 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
710 tte_vaddr += 0x400000;
711 tte_data += 0x400000;
712 }
713 } else {
714 for (i = 0; i < num_kernel_image_mappings; i++) {
715 prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr);
716 prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr);
717 tte_vaddr += 0x400000;
718 tte_data += 0x400000;
719 }
720 sparc64_highest_unlocked_tlb_ent = tlb_ent - i;
721 }
722 if (tlb_type == cheetah_plus) {
723 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
724 CTX_CHEETAH_PLUS_NUC);
725 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
726 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
727 }
728}
729
730
731static void __init inherit_prom_mappings(void)
732{
733 /* Now fixup OBP's idea about where we really are mapped. */
734 printk("Remapping the kernel... ");
735 remap_kernel();
736 printk("done.\n");
737}
738
739void prom_world(int enter)
740{
741 if (!enter)
742 set_fs(get_fs());
743
744 __asm__ __volatile__("flushw");
745}
746
747void __flush_dcache_range(unsigned long start, unsigned long end)
748{
749 unsigned long va;
750
751 if (tlb_type == spitfire) {
752 int n = 0;
753
754 for (va = start; va < end; va += 32) {
755 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
756 if (++n >= 512)
757 break;
758 }
759 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
760 start = __pa(start);
761 end = __pa(end);
762 for (va = start; va < end; va += 32)
763 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
764 "membar #Sync"
765 : /* no outputs */
766 : "r" (va),
767 "i" (ASI_DCACHE_INVALIDATE));
768 }
769}
770EXPORT_SYMBOL(__flush_dcache_range);
771
772/* get_new_mmu_context() uses "cache + 1". */
773DEFINE_SPINLOCK(ctx_alloc_lock);
774unsigned long tlb_context_cache = CTX_FIRST_VERSION;
775#define MAX_CTX_NR (1UL << CTX_NR_BITS)
776#define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR)
777DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
778DEFINE_PER_CPU(struct mm_struct *, per_cpu_secondary_mm) = {0};
779
780static void mmu_context_wrap(void)
781{
782 unsigned long old_ver = tlb_context_cache & CTX_VERSION_MASK;
783 unsigned long new_ver, new_ctx, old_ctx;
784 struct mm_struct *mm;
785 int cpu;
786
787 bitmap_zero(mmu_context_bmap, 1 << CTX_NR_BITS);
788
789 /* Reserve kernel context */
790 set_bit(0, mmu_context_bmap);
791
792 new_ver = (tlb_context_cache & CTX_VERSION_MASK) + CTX_FIRST_VERSION;
793 if (unlikely(new_ver == 0))
794 new_ver = CTX_FIRST_VERSION;
795 tlb_context_cache = new_ver;
796
797 /*
798 * Make sure that any new mm that are added into per_cpu_secondary_mm,
799 * are going to go through get_new_mmu_context() path.
800 */
801 mb();
802
803 /*
804 * Updated versions to current on those CPUs that had valid secondary
805 * contexts
806 */
807 for_each_online_cpu(cpu) {
808 /*
809 * If a new mm is stored after we took this mm from the array,
810 * it will go into get_new_mmu_context() path, because we
811 * already bumped the version in tlb_context_cache.
812 */
813 mm = per_cpu(per_cpu_secondary_mm, cpu);
814
815 if (unlikely(!mm || mm == &init_mm))
816 continue;
817
818 old_ctx = mm->context.sparc64_ctx_val;
819 if (likely((old_ctx & CTX_VERSION_MASK) == old_ver)) {
820 new_ctx = (old_ctx & ~CTX_VERSION_MASK) | new_ver;
821 set_bit(new_ctx & CTX_NR_MASK, mmu_context_bmap);
822 mm->context.sparc64_ctx_val = new_ctx;
823 }
824 }
825}
826
827/* Caller does TLB context flushing on local CPU if necessary.
828 * The caller also ensures that CTX_VALID(mm->context) is false.
829 *
830 * We must be careful about boundary cases so that we never
831 * let the user have CTX 0 (nucleus) or we ever use a CTX
832 * version of zero (and thus NO_CONTEXT would not be caught
833 * by version mis-match tests in mmu_context.h).
834 *
835 * Always invoked with interrupts disabled.
836 */
837void get_new_mmu_context(struct mm_struct *mm)
838{
839 unsigned long ctx, new_ctx;
840 unsigned long orig_pgsz_bits;
841
842 spin_lock(&ctx_alloc_lock);
843retry:
844 /* wrap might have happened, test again if our context became valid */
845 if (unlikely(CTX_VALID(mm->context)))
846 goto out;
847 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
848 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
849 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
850 if (new_ctx >= (1 << CTX_NR_BITS)) {
851 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
852 if (new_ctx >= ctx) {
853 mmu_context_wrap();
854 goto retry;
855 }
856 }
857 if (mm->context.sparc64_ctx_val)
858 cpumask_clear(mm_cpumask(mm));
859 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
860 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
861 tlb_context_cache = new_ctx;
862 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
863out:
864 spin_unlock(&ctx_alloc_lock);
865}
866
867static int numa_enabled = 1;
868static int numa_debug;
869
870static int __init early_numa(char *p)
871{
872 if (!p)
873 return 0;
874
875 if (strstr(p, "off"))
876 numa_enabled = 0;
877
878 if (strstr(p, "debug"))
879 numa_debug = 1;
880
881 return 0;
882}
883early_param("numa", early_numa);
884
885#define numadbg(f, a...) \
886do { if (numa_debug) \
887 printk(KERN_INFO f, ## a); \
888} while (0)
889
890static void __init find_ramdisk(unsigned long phys_base)
891{
892#ifdef CONFIG_BLK_DEV_INITRD
893 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
894 unsigned long ramdisk_image;
895
896 /* Older versions of the bootloader only supported a
897 * 32-bit physical address for the ramdisk image
898 * location, stored at sparc_ramdisk_image. Newer
899 * SILO versions set sparc_ramdisk_image to zero and
900 * provide a full 64-bit physical address at
901 * sparc_ramdisk_image64.
902 */
903 ramdisk_image = sparc_ramdisk_image;
904 if (!ramdisk_image)
905 ramdisk_image = sparc_ramdisk_image64;
906
907 /* Another bootloader quirk. The bootloader normalizes
908 * the physical address to KERNBASE, so we have to
909 * factor that back out and add in the lowest valid
910 * physical page address to get the true physical address.
911 */
912 ramdisk_image -= KERNBASE;
913 ramdisk_image += phys_base;
914
915 numadbg("Found ramdisk at physical address 0x%lx, size %u\n",
916 ramdisk_image, sparc_ramdisk_size);
917
918 initrd_start = ramdisk_image;
919 initrd_end = ramdisk_image + sparc_ramdisk_size;
920
921 memblock_reserve(initrd_start, sparc_ramdisk_size);
922
923 initrd_start += PAGE_OFFSET;
924 initrd_end += PAGE_OFFSET;
925 }
926#endif
927}
928
929struct node_mem_mask {
930 unsigned long mask;
931 unsigned long match;
932};
933static struct node_mem_mask node_masks[MAX_NUMNODES];
934static int num_node_masks;
935
936#ifdef CONFIG_NEED_MULTIPLE_NODES
937
938struct mdesc_mlgroup {
939 u64 node;
940 u64 latency;
941 u64 match;
942 u64 mask;
943};
944
945static struct mdesc_mlgroup *mlgroups;
946static int num_mlgroups;
947
948int numa_cpu_lookup_table[NR_CPUS];
949cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES];
950
951struct mdesc_mblock {
952 u64 base;
953 u64 size;
954 u64 offset; /* RA-to-PA */
955};
956static struct mdesc_mblock *mblocks;
957static int num_mblocks;
958
959static struct mdesc_mblock * __init addr_to_mblock(unsigned long addr)
960{
961 struct mdesc_mblock *m = NULL;
962 int i;
963
964 for (i = 0; i < num_mblocks; i++) {
965 m = &mblocks[i];
966
967 if (addr >= m->base &&
968 addr < (m->base + m->size)) {
969 break;
970 }
971 }
972
973 return m;
974}
975
976static u64 __init memblock_nid_range_sun4u(u64 start, u64 end, int *nid)
977{
978 int prev_nid, new_nid;
979
980 prev_nid = -1;
981 for ( ; start < end; start += PAGE_SIZE) {
982 for (new_nid = 0; new_nid < num_node_masks; new_nid++) {
983 struct node_mem_mask *p = &node_masks[new_nid];
984
985 if ((start & p->mask) == p->match) {
986 if (prev_nid == -1)
987 prev_nid = new_nid;
988 break;
989 }
990 }
991
992 if (new_nid == num_node_masks) {
993 prev_nid = 0;
994 WARN_ONCE(1, "addr[%Lx] doesn't match a NUMA node rule. Some memory will be owned by node 0.",
995 start);
996 break;
997 }
998
999 if (prev_nid != new_nid)
1000 break;
1001 }
1002 *nid = prev_nid;
1003
1004 return start > end ? end : start;
1005}
1006
1007static u64 __init memblock_nid_range(u64 start, u64 end, int *nid)
1008{
1009 u64 ret_end, pa_start, m_mask, m_match, m_end;
1010 struct mdesc_mblock *mblock;
1011 int _nid, i;
1012
1013 if (tlb_type != hypervisor)
1014 return memblock_nid_range_sun4u(start, end, nid);
1015
1016 mblock = addr_to_mblock(start);
1017 if (!mblock) {
1018 WARN_ONCE(1, "memblock_nid_range: Can't find mblock addr[%Lx]",
1019 start);
1020
1021 _nid = 0;
1022 ret_end = end;
1023 goto done;
1024 }
1025
1026 pa_start = start + mblock->offset;
1027 m_match = 0;
1028 m_mask = 0;
1029
1030 for (_nid = 0; _nid < num_node_masks; _nid++) {
1031 struct node_mem_mask *const m = &node_masks[_nid];
1032
1033 if ((pa_start & m->mask) == m->match) {
1034 m_match = m->match;
1035 m_mask = m->mask;
1036 break;
1037 }
1038 }
1039
1040 if (num_node_masks == _nid) {
1041 /* We could not find NUMA group, so default to 0, but lets
1042 * search for latency group, so we could calculate the correct
1043 * end address that we return
1044 */
1045 _nid = 0;
1046
1047 for (i = 0; i < num_mlgroups; i++) {
1048 struct mdesc_mlgroup *const m = &mlgroups[i];
1049
1050 if ((pa_start & m->mask) == m->match) {
1051 m_match = m->match;
1052 m_mask = m->mask;
1053 break;
1054 }
1055 }
1056
1057 if (i == num_mlgroups) {
1058 WARN_ONCE(1, "memblock_nid_range: Can't find latency group addr[%Lx]",
1059 start);
1060
1061 ret_end = end;
1062 goto done;
1063 }
1064 }
1065
1066 /*
1067 * Each latency group has match and mask, and each memory block has an
1068 * offset. An address belongs to a latency group if its address matches
1069 * the following formula: ((addr + offset) & mask) == match
1070 * It is, however, slow to check every single page if it matches a
1071 * particular latency group. As optimization we calculate end value by
1072 * using bit arithmetics.
1073 */
1074 m_end = m_match + (1ul << __ffs(m_mask)) - mblock->offset;
1075 m_end += pa_start & ~((1ul << fls64(m_mask)) - 1);
1076 ret_end = m_end > end ? end : m_end;
1077
1078done:
1079 *nid = _nid;
1080 return ret_end;
1081}
1082#endif
1083
1084/* This must be invoked after performing all of the necessary
1085 * memblock_set_node() calls for 'nid'. We need to be able to get
1086 * correct data from get_pfn_range_for_nid().
1087 */
1088static void __init allocate_node_data(int nid)
1089{
1090 struct pglist_data *p;
1091 unsigned long start_pfn, end_pfn;
1092#ifdef CONFIG_NEED_MULTIPLE_NODES
1093 unsigned long paddr;
1094
1095 paddr = memblock_alloc_try_nid(sizeof(struct pglist_data), SMP_CACHE_BYTES, nid);
1096 if (!paddr) {
1097 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid);
1098 prom_halt();
1099 }
1100 NODE_DATA(nid) = __va(paddr);
1101 memset(NODE_DATA(nid), 0, sizeof(struct pglist_data));
1102
1103 NODE_DATA(nid)->node_id = nid;
1104#endif
1105
1106 p = NODE_DATA(nid);
1107
1108 get_pfn_range_for_nid(nid, &start_pfn, &end_pfn);
1109 p->node_start_pfn = start_pfn;
1110 p->node_spanned_pages = end_pfn - start_pfn;
1111}
1112
1113static void init_node_masks_nonnuma(void)
1114{
1115#ifdef CONFIG_NEED_MULTIPLE_NODES
1116 int i;
1117#endif
1118
1119 numadbg("Initializing tables for non-numa.\n");
1120
1121 node_masks[0].mask = 0;
1122 node_masks[0].match = 0;
1123 num_node_masks = 1;
1124
1125#ifdef CONFIG_NEED_MULTIPLE_NODES
1126 for (i = 0; i < NR_CPUS; i++)
1127 numa_cpu_lookup_table[i] = 0;
1128
1129 cpumask_setall(&numa_cpumask_lookup_table[0]);
1130#endif
1131}
1132
1133#ifdef CONFIG_NEED_MULTIPLE_NODES
1134struct pglist_data *node_data[MAX_NUMNODES];
1135
1136EXPORT_SYMBOL(numa_cpu_lookup_table);
1137EXPORT_SYMBOL(numa_cpumask_lookup_table);
1138EXPORT_SYMBOL(node_data);
1139
1140static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio,
1141 u32 cfg_handle)
1142{
1143 u64 arc;
1144
1145 mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) {
1146 u64 target = mdesc_arc_target(md, arc);
1147 const u64 *val;
1148
1149 val = mdesc_get_property(md, target,
1150 "cfg-handle", NULL);
1151 if (val && *val == cfg_handle)
1152 return 0;
1153 }
1154 return -ENODEV;
1155}
1156
1157static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp,
1158 u32 cfg_handle)
1159{
1160 u64 arc, candidate, best_latency = ~(u64)0;
1161
1162 candidate = MDESC_NODE_NULL;
1163 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1164 u64 target = mdesc_arc_target(md, arc);
1165 const char *name = mdesc_node_name(md, target);
1166 const u64 *val;
1167
1168 if (strcmp(name, "pio-latency-group"))
1169 continue;
1170
1171 val = mdesc_get_property(md, target, "latency", NULL);
1172 if (!val)
1173 continue;
1174
1175 if (*val < best_latency) {
1176 candidate = target;
1177 best_latency = *val;
1178 }
1179 }
1180
1181 if (candidate == MDESC_NODE_NULL)
1182 return -ENODEV;
1183
1184 return scan_pio_for_cfg_handle(md, candidate, cfg_handle);
1185}
1186
1187int of_node_to_nid(struct device_node *dp)
1188{
1189 const struct linux_prom64_registers *regs;
1190 struct mdesc_handle *md;
1191 u32 cfg_handle;
1192 int count, nid;
1193 u64 grp;
1194
1195 /* This is the right thing to do on currently supported
1196 * SUN4U NUMA platforms as well, as the PCI controller does
1197 * not sit behind any particular memory controller.
1198 */
1199 if (!mlgroups)
1200 return -1;
1201
1202 regs = of_get_property(dp, "reg", NULL);
1203 if (!regs)
1204 return -1;
1205
1206 cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff;
1207
1208 md = mdesc_grab();
1209
1210 count = 0;
1211 nid = -1;
1212 mdesc_for_each_node_by_name(md, grp, "group") {
1213 if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) {
1214 nid = count;
1215 break;
1216 }
1217 count++;
1218 }
1219
1220 mdesc_release(md);
1221
1222 return nid;
1223}
1224
1225static void __init add_node_ranges(void)
1226{
1227 struct memblock_region *reg;
1228 unsigned long prev_max;
1229
1230memblock_resized:
1231 prev_max = memblock.memory.max;
1232
1233 for_each_memblock(memory, reg) {
1234 unsigned long size = reg->size;
1235 unsigned long start, end;
1236
1237 start = reg->base;
1238 end = start + size;
1239 while (start < end) {
1240 unsigned long this_end;
1241 int nid;
1242
1243 this_end = memblock_nid_range(start, end, &nid);
1244
1245 numadbg("Setting memblock NUMA node nid[%d] "
1246 "start[%lx] end[%lx]\n",
1247 nid, start, this_end);
1248
1249 memblock_set_node(start, this_end - start,
1250 &memblock.memory, nid);
1251 if (memblock.memory.max != prev_max)
1252 goto memblock_resized;
1253 start = this_end;
1254 }
1255 }
1256}
1257
1258static int __init grab_mlgroups(struct mdesc_handle *md)
1259{
1260 unsigned long paddr;
1261 int count = 0;
1262 u64 node;
1263
1264 mdesc_for_each_node_by_name(md, node, "memory-latency-group")
1265 count++;
1266 if (!count)
1267 return -ENOENT;
1268
1269 paddr = memblock_alloc(count * sizeof(struct mdesc_mlgroup),
1270 SMP_CACHE_BYTES);
1271 if (!paddr)
1272 return -ENOMEM;
1273
1274 mlgroups = __va(paddr);
1275 num_mlgroups = count;
1276
1277 count = 0;
1278 mdesc_for_each_node_by_name(md, node, "memory-latency-group") {
1279 struct mdesc_mlgroup *m = &mlgroups[count++];
1280 const u64 *val;
1281
1282 m->node = node;
1283
1284 val = mdesc_get_property(md, node, "latency", NULL);
1285 m->latency = *val;
1286 val = mdesc_get_property(md, node, "address-match", NULL);
1287 m->match = *val;
1288 val = mdesc_get_property(md, node, "address-mask", NULL);
1289 m->mask = *val;
1290
1291 numadbg("MLGROUP[%d]: node[%llx] latency[%llx] "
1292 "match[%llx] mask[%llx]\n",
1293 count - 1, m->node, m->latency, m->match, m->mask);
1294 }
1295
1296 return 0;
1297}
1298
1299static int __init grab_mblocks(struct mdesc_handle *md)
1300{
1301 unsigned long paddr;
1302 int count = 0;
1303 u64 node;
1304
1305 mdesc_for_each_node_by_name(md, node, "mblock")
1306 count++;
1307 if (!count)
1308 return -ENOENT;
1309
1310 paddr = memblock_alloc(count * sizeof(struct mdesc_mblock),
1311 SMP_CACHE_BYTES);
1312 if (!paddr)
1313 return -ENOMEM;
1314
1315 mblocks = __va(paddr);
1316 num_mblocks = count;
1317
1318 count = 0;
1319 mdesc_for_each_node_by_name(md, node, "mblock") {
1320 struct mdesc_mblock *m = &mblocks[count++];
1321 const u64 *val;
1322
1323 val = mdesc_get_property(md, node, "base", NULL);
1324 m->base = *val;
1325 val = mdesc_get_property(md, node, "size", NULL);
1326 m->size = *val;
1327 val = mdesc_get_property(md, node,
1328 "address-congruence-offset", NULL);
1329
1330 /* The address-congruence-offset property is optional.
1331 * Explicity zero it be identifty this.
1332 */
1333 if (val)
1334 m->offset = *val;
1335 else
1336 m->offset = 0UL;
1337
1338 numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n",
1339 count - 1, m->base, m->size, m->offset);
1340 }
1341
1342 return 0;
1343}
1344
1345static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md,
1346 u64 grp, cpumask_t *mask)
1347{
1348 u64 arc;
1349
1350 cpumask_clear(mask);
1351
1352 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) {
1353 u64 target = mdesc_arc_target(md, arc);
1354 const char *name = mdesc_node_name(md, target);
1355 const u64 *id;
1356
1357 if (strcmp(name, "cpu"))
1358 continue;
1359 id = mdesc_get_property(md, target, "id", NULL);
1360 if (*id < nr_cpu_ids)
1361 cpumask_set_cpu(*id, mask);
1362 }
1363}
1364
1365static struct mdesc_mlgroup * __init find_mlgroup(u64 node)
1366{
1367 int i;
1368
1369 for (i = 0; i < num_mlgroups; i++) {
1370 struct mdesc_mlgroup *m = &mlgroups[i];
1371 if (m->node == node)
1372 return m;
1373 }
1374 return NULL;
1375}
1376
1377int __node_distance(int from, int to)
1378{
1379 if ((from >= MAX_NUMNODES) || (to >= MAX_NUMNODES)) {
1380 pr_warn("Returning default NUMA distance value for %d->%d\n",
1381 from, to);
1382 return (from == to) ? LOCAL_DISTANCE : REMOTE_DISTANCE;
1383 }
1384 return numa_latency[from][to];
1385}
1386
1387static int __init find_best_numa_node_for_mlgroup(struct mdesc_mlgroup *grp)
1388{
1389 int i;
1390
1391 for (i = 0; i < MAX_NUMNODES; i++) {
1392 struct node_mem_mask *n = &node_masks[i];
1393
1394 if ((grp->mask == n->mask) && (grp->match == n->match))
1395 break;
1396 }
1397 return i;
1398}
1399
1400static void __init find_numa_latencies_for_group(struct mdesc_handle *md,
1401 u64 grp, int index)
1402{
1403 u64 arc;
1404
1405 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1406 int tnode;
1407 u64 target = mdesc_arc_target(md, arc);
1408 struct mdesc_mlgroup *m = find_mlgroup(target);
1409
1410 if (!m)
1411 continue;
1412 tnode = find_best_numa_node_for_mlgroup(m);
1413 if (tnode == MAX_NUMNODES)
1414 continue;
1415 numa_latency[index][tnode] = m->latency;
1416 }
1417}
1418
1419static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp,
1420 int index)
1421{
1422 struct mdesc_mlgroup *candidate = NULL;
1423 u64 arc, best_latency = ~(u64)0;
1424 struct node_mem_mask *n;
1425
1426 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1427 u64 target = mdesc_arc_target(md, arc);
1428 struct mdesc_mlgroup *m = find_mlgroup(target);
1429 if (!m)
1430 continue;
1431 if (m->latency < best_latency) {
1432 candidate = m;
1433 best_latency = m->latency;
1434 }
1435 }
1436 if (!candidate)
1437 return -ENOENT;
1438
1439 if (num_node_masks != index) {
1440 printk(KERN_ERR "Inconsistent NUMA state, "
1441 "index[%d] != num_node_masks[%d]\n",
1442 index, num_node_masks);
1443 return -EINVAL;
1444 }
1445
1446 n = &node_masks[num_node_masks++];
1447
1448 n->mask = candidate->mask;
1449 n->match = candidate->match;
1450
1451 numadbg("NUMA NODE[%d]: mask[%lx] match[%lx] (latency[%llx])\n",
1452 index, n->mask, n->match, candidate->latency);
1453
1454 return 0;
1455}
1456
1457static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp,
1458 int index)
1459{
1460 cpumask_t mask;
1461 int cpu;
1462
1463 numa_parse_mdesc_group_cpus(md, grp, &mask);
1464
1465 for_each_cpu(cpu, &mask)
1466 numa_cpu_lookup_table[cpu] = index;
1467 cpumask_copy(&numa_cpumask_lookup_table[index], &mask);
1468
1469 if (numa_debug) {
1470 printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index);
1471 for_each_cpu(cpu, &mask)
1472 printk("%d ", cpu);
1473 printk("]\n");
1474 }
1475
1476 return numa_attach_mlgroup(md, grp, index);
1477}
1478
1479static int __init numa_parse_mdesc(void)
1480{
1481 struct mdesc_handle *md = mdesc_grab();
1482 int i, j, err, count;
1483 u64 node;
1484
1485 node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups");
1486 if (node == MDESC_NODE_NULL) {
1487 mdesc_release(md);
1488 return -ENOENT;
1489 }
1490
1491 err = grab_mblocks(md);
1492 if (err < 0)
1493 goto out;
1494
1495 err = grab_mlgroups(md);
1496 if (err < 0)
1497 goto out;
1498
1499 count = 0;
1500 mdesc_for_each_node_by_name(md, node, "group") {
1501 err = numa_parse_mdesc_group(md, node, count);
1502 if (err < 0)
1503 break;
1504 count++;
1505 }
1506
1507 count = 0;
1508 mdesc_for_each_node_by_name(md, node, "group") {
1509 find_numa_latencies_for_group(md, node, count);
1510 count++;
1511 }
1512
1513 /* Normalize numa latency matrix according to ACPI SLIT spec. */
1514 for (i = 0; i < MAX_NUMNODES; i++) {
1515 u64 self_latency = numa_latency[i][i];
1516
1517 for (j = 0; j < MAX_NUMNODES; j++) {
1518 numa_latency[i][j] =
1519 (numa_latency[i][j] * LOCAL_DISTANCE) /
1520 self_latency;
1521 }
1522 }
1523
1524 add_node_ranges();
1525
1526 for (i = 0; i < num_node_masks; i++) {
1527 allocate_node_data(i);
1528 node_set_online(i);
1529 }
1530
1531 err = 0;
1532out:
1533 mdesc_release(md);
1534 return err;
1535}
1536
1537static int __init numa_parse_jbus(void)
1538{
1539 unsigned long cpu, index;
1540
1541 /* NUMA node id is encoded in bits 36 and higher, and there is
1542 * a 1-to-1 mapping from CPU ID to NUMA node ID.
1543 */
1544 index = 0;
1545 for_each_present_cpu(cpu) {
1546 numa_cpu_lookup_table[cpu] = index;
1547 cpumask_copy(&numa_cpumask_lookup_table[index], cpumask_of(cpu));
1548 node_masks[index].mask = ~((1UL << 36UL) - 1UL);
1549 node_masks[index].match = cpu << 36UL;
1550
1551 index++;
1552 }
1553 num_node_masks = index;
1554
1555 add_node_ranges();
1556
1557 for (index = 0; index < num_node_masks; index++) {
1558 allocate_node_data(index);
1559 node_set_online(index);
1560 }
1561
1562 return 0;
1563}
1564
1565static int __init numa_parse_sun4u(void)
1566{
1567 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1568 unsigned long ver;
1569
1570 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
1571 if ((ver >> 32UL) == __JALAPENO_ID ||
1572 (ver >> 32UL) == __SERRANO_ID)
1573 return numa_parse_jbus();
1574 }
1575 return -1;
1576}
1577
1578static int __init bootmem_init_numa(void)
1579{
1580 int i, j;
1581 int err = -1;
1582
1583 numadbg("bootmem_init_numa()\n");
1584
1585 /* Some sane defaults for numa latency values */
1586 for (i = 0; i < MAX_NUMNODES; i++) {
1587 for (j = 0; j < MAX_NUMNODES; j++)
1588 numa_latency[i][j] = (i == j) ?
1589 LOCAL_DISTANCE : REMOTE_DISTANCE;
1590 }
1591
1592 if (numa_enabled) {
1593 if (tlb_type == hypervisor)
1594 err = numa_parse_mdesc();
1595 else
1596 err = numa_parse_sun4u();
1597 }
1598 return err;
1599}
1600
1601#else
1602
1603static int bootmem_init_numa(void)
1604{
1605 return -1;
1606}
1607
1608#endif
1609
1610static void __init bootmem_init_nonnuma(void)
1611{
1612 unsigned long top_of_ram = memblock_end_of_DRAM();
1613 unsigned long total_ram = memblock_phys_mem_size();
1614
1615 numadbg("bootmem_init_nonnuma()\n");
1616
1617 printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
1618 top_of_ram, total_ram);
1619 printk(KERN_INFO "Memory hole size: %ldMB\n",
1620 (top_of_ram - total_ram) >> 20);
1621
1622 init_node_masks_nonnuma();
1623 memblock_set_node(0, (phys_addr_t)ULLONG_MAX, &memblock.memory, 0);
1624 allocate_node_data(0);
1625 node_set_online(0);
1626}
1627
1628static unsigned long __init bootmem_init(unsigned long phys_base)
1629{
1630 unsigned long end_pfn;
1631
1632 end_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT;
1633 max_pfn = max_low_pfn = end_pfn;
1634 min_low_pfn = (phys_base >> PAGE_SHIFT);
1635
1636 if (bootmem_init_numa() < 0)
1637 bootmem_init_nonnuma();
1638
1639 /* Dump memblock with node info. */
1640 memblock_dump_all();
1641
1642 /* XXX cpu notifier XXX */
1643
1644 sparse_memory_present_with_active_regions(MAX_NUMNODES);
1645 sparse_init();
1646
1647 return end_pfn;
1648}
1649
1650static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1651static int pall_ents __initdata;
1652
1653static unsigned long max_phys_bits = 40;
1654
1655bool kern_addr_valid(unsigned long addr)
1656{
1657 pgd_t *pgd;
1658 pud_t *pud;
1659 pmd_t *pmd;
1660 pte_t *pte;
1661
1662 if ((long)addr < 0L) {
1663 unsigned long pa = __pa(addr);
1664
1665 if ((pa >> max_phys_bits) != 0UL)
1666 return false;
1667
1668 return pfn_valid(pa >> PAGE_SHIFT);
1669 }
1670
1671 if (addr >= (unsigned long) KERNBASE &&
1672 addr < (unsigned long)&_end)
1673 return true;
1674
1675 pgd = pgd_offset_k(addr);
1676 if (pgd_none(*pgd))
1677 return 0;
1678
1679 pud = pud_offset(pgd, addr);
1680 if (pud_none(*pud))
1681 return 0;
1682
1683 if (pud_large(*pud))
1684 return pfn_valid(pud_pfn(*pud));
1685
1686 pmd = pmd_offset(pud, addr);
1687 if (pmd_none(*pmd))
1688 return 0;
1689
1690 if (pmd_large(*pmd))
1691 return pfn_valid(pmd_pfn(*pmd));
1692
1693 pte = pte_offset_kernel(pmd, addr);
1694 if (pte_none(*pte))
1695 return 0;
1696
1697 return pfn_valid(pte_pfn(*pte));
1698}
1699EXPORT_SYMBOL(kern_addr_valid);
1700
1701static unsigned long __ref kernel_map_hugepud(unsigned long vstart,
1702 unsigned long vend,
1703 pud_t *pud)
1704{
1705 const unsigned long mask16gb = (1UL << 34) - 1UL;
1706 u64 pte_val = vstart;
1707
1708 /* Each PUD is 8GB */
1709 if ((vstart & mask16gb) ||
1710 (vend - vstart <= mask16gb)) {
1711 pte_val ^= kern_linear_pte_xor[2];
1712 pud_val(*pud) = pte_val | _PAGE_PUD_HUGE;
1713
1714 return vstart + PUD_SIZE;
1715 }
1716
1717 pte_val ^= kern_linear_pte_xor[3];
1718 pte_val |= _PAGE_PUD_HUGE;
1719
1720 vend = vstart + mask16gb + 1UL;
1721 while (vstart < vend) {
1722 pud_val(*pud) = pte_val;
1723
1724 pte_val += PUD_SIZE;
1725 vstart += PUD_SIZE;
1726 pud++;
1727 }
1728 return vstart;
1729}
1730
1731static bool kernel_can_map_hugepud(unsigned long vstart, unsigned long vend,
1732 bool guard)
1733{
1734 if (guard && !(vstart & ~PUD_MASK) && (vend - vstart) >= PUD_SIZE)
1735 return true;
1736
1737 return false;
1738}
1739
1740static unsigned long __ref kernel_map_hugepmd(unsigned long vstart,
1741 unsigned long vend,
1742 pmd_t *pmd)
1743{
1744 const unsigned long mask256mb = (1UL << 28) - 1UL;
1745 const unsigned long mask2gb = (1UL << 31) - 1UL;
1746 u64 pte_val = vstart;
1747
1748 /* Each PMD is 8MB */
1749 if ((vstart & mask256mb) ||
1750 (vend - vstart <= mask256mb)) {
1751 pte_val ^= kern_linear_pte_xor[0];
1752 pmd_val(*pmd) = pte_val | _PAGE_PMD_HUGE;
1753
1754 return vstart + PMD_SIZE;
1755 }
1756
1757 if ((vstart & mask2gb) ||
1758 (vend - vstart <= mask2gb)) {
1759 pte_val ^= kern_linear_pte_xor[1];
1760 pte_val |= _PAGE_PMD_HUGE;
1761 vend = vstart + mask256mb + 1UL;
1762 } else {
1763 pte_val ^= kern_linear_pte_xor[2];
1764 pte_val |= _PAGE_PMD_HUGE;
1765 vend = vstart + mask2gb + 1UL;
1766 }
1767
1768 while (vstart < vend) {
1769 pmd_val(*pmd) = pte_val;
1770
1771 pte_val += PMD_SIZE;
1772 vstart += PMD_SIZE;
1773 pmd++;
1774 }
1775
1776 return vstart;
1777}
1778
1779static bool kernel_can_map_hugepmd(unsigned long vstart, unsigned long vend,
1780 bool guard)
1781{
1782 if (guard && !(vstart & ~PMD_MASK) && (vend - vstart) >= PMD_SIZE)
1783 return true;
1784
1785 return false;
1786}
1787
1788static unsigned long __ref kernel_map_range(unsigned long pstart,
1789 unsigned long pend, pgprot_t prot,
1790 bool use_huge)
1791{
1792 unsigned long vstart = PAGE_OFFSET + pstart;
1793 unsigned long vend = PAGE_OFFSET + pend;
1794 unsigned long alloc_bytes = 0UL;
1795
1796 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1797 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1798 vstart, vend);
1799 prom_halt();
1800 }
1801
1802 while (vstart < vend) {
1803 unsigned long this_end, paddr = __pa(vstart);
1804 pgd_t *pgd = pgd_offset_k(vstart);
1805 pud_t *pud;
1806 pmd_t *pmd;
1807 pte_t *pte;
1808
1809 if (pgd_none(*pgd)) {
1810 pud_t *new;
1811
1812 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1813 alloc_bytes += PAGE_SIZE;
1814 pgd_populate(&init_mm, pgd, new);
1815 }
1816 pud = pud_offset(pgd, vstart);
1817 if (pud_none(*pud)) {
1818 pmd_t *new;
1819
1820 if (kernel_can_map_hugepud(vstart, vend, use_huge)) {
1821 vstart = kernel_map_hugepud(vstart, vend, pud);
1822 continue;
1823 }
1824 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1825 alloc_bytes += PAGE_SIZE;
1826 pud_populate(&init_mm, pud, new);
1827 }
1828
1829 pmd = pmd_offset(pud, vstart);
1830 if (pmd_none(*pmd)) {
1831 pte_t *new;
1832
1833 if (kernel_can_map_hugepmd(vstart, vend, use_huge)) {
1834 vstart = kernel_map_hugepmd(vstart, vend, pmd);
1835 continue;
1836 }
1837 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1838 alloc_bytes += PAGE_SIZE;
1839 pmd_populate_kernel(&init_mm, pmd, new);
1840 }
1841
1842 pte = pte_offset_kernel(pmd, vstart);
1843 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1844 if (this_end > vend)
1845 this_end = vend;
1846
1847 while (vstart < this_end) {
1848 pte_val(*pte) = (paddr | pgprot_val(prot));
1849
1850 vstart += PAGE_SIZE;
1851 paddr += PAGE_SIZE;
1852 pte++;
1853 }
1854 }
1855
1856 return alloc_bytes;
1857}
1858
1859static void __init flush_all_kernel_tsbs(void)
1860{
1861 int i;
1862
1863 for (i = 0; i < KERNEL_TSB_NENTRIES; i++) {
1864 struct tsb *ent = &swapper_tsb[i];
1865
1866 ent->tag = (1UL << TSB_TAG_INVALID_BIT);
1867 }
1868#ifndef CONFIG_DEBUG_PAGEALLOC
1869 for (i = 0; i < KERNEL_TSB4M_NENTRIES; i++) {
1870 struct tsb *ent = &swapper_4m_tsb[i];
1871
1872 ent->tag = (1UL << TSB_TAG_INVALID_BIT);
1873 }
1874#endif
1875}
1876
1877extern unsigned int kvmap_linear_patch[1];
1878
1879static void __init kernel_physical_mapping_init(void)
1880{
1881 unsigned long i, mem_alloced = 0UL;
1882 bool use_huge = true;
1883
1884#ifdef CONFIG_DEBUG_PAGEALLOC
1885 use_huge = false;
1886#endif
1887 for (i = 0; i < pall_ents; i++) {
1888 unsigned long phys_start, phys_end;
1889
1890 phys_start = pall[i].phys_addr;
1891 phys_end = phys_start + pall[i].reg_size;
1892
1893 mem_alloced += kernel_map_range(phys_start, phys_end,
1894 PAGE_KERNEL, use_huge);
1895 }
1896
1897 printk("Allocated %ld bytes for kernel page tables.\n",
1898 mem_alloced);
1899
1900 kvmap_linear_patch[0] = 0x01000000; /* nop */
1901 flushi(&kvmap_linear_patch[0]);
1902
1903 flush_all_kernel_tsbs();
1904
1905 __flush_tlb_all();
1906}
1907
1908#ifdef CONFIG_DEBUG_PAGEALLOC
1909void __kernel_map_pages(struct page *page, int numpages, int enable)
1910{
1911 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1912 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1913
1914 kernel_map_range(phys_start, phys_end,
1915 (enable ? PAGE_KERNEL : __pgprot(0)), false);
1916
1917 flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1918 PAGE_OFFSET + phys_end);
1919
1920 /* we should perform an IPI and flush all tlbs,
1921 * but that can deadlock->flush only current cpu.
1922 */
1923 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1924 PAGE_OFFSET + phys_end);
1925}
1926#endif
1927
1928unsigned long __init find_ecache_flush_span(unsigned long size)
1929{
1930 int i;
1931
1932 for (i = 0; i < pavail_ents; i++) {
1933 if (pavail[i].reg_size >= size)
1934 return pavail[i].phys_addr;
1935 }
1936
1937 return ~0UL;
1938}
1939
1940unsigned long PAGE_OFFSET;
1941EXPORT_SYMBOL(PAGE_OFFSET);
1942
1943unsigned long VMALLOC_END = 0x0000010000000000UL;
1944EXPORT_SYMBOL(VMALLOC_END);
1945
1946unsigned long sparc64_va_hole_top = 0xfffff80000000000UL;
1947unsigned long sparc64_va_hole_bottom = 0x0000080000000000UL;
1948
1949static void __init setup_page_offset(void)
1950{
1951 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1952 /* Cheetah/Panther support a full 64-bit virtual
1953 * address, so we can use all that our page tables
1954 * support.
1955 */
1956 sparc64_va_hole_top = 0xfff0000000000000UL;
1957 sparc64_va_hole_bottom = 0x0010000000000000UL;
1958
1959 max_phys_bits = 42;
1960 } else if (tlb_type == hypervisor) {
1961 switch (sun4v_chip_type) {
1962 case SUN4V_CHIP_NIAGARA1:
1963 case SUN4V_CHIP_NIAGARA2:
1964 /* T1 and T2 support 48-bit virtual addresses. */
1965 sparc64_va_hole_top = 0xffff800000000000UL;
1966 sparc64_va_hole_bottom = 0x0000800000000000UL;
1967
1968 max_phys_bits = 39;
1969 break;
1970 case SUN4V_CHIP_NIAGARA3:
1971 /* T3 supports 48-bit virtual addresses. */
1972 sparc64_va_hole_top = 0xffff800000000000UL;
1973 sparc64_va_hole_bottom = 0x0000800000000000UL;
1974
1975 max_phys_bits = 43;
1976 break;
1977 case SUN4V_CHIP_NIAGARA4:
1978 case SUN4V_CHIP_NIAGARA5:
1979 case SUN4V_CHIP_SPARC64X:
1980 case SUN4V_CHIP_SPARC_M6:
1981 /* T4 and later support 52-bit virtual addresses. */
1982 sparc64_va_hole_top = 0xfff8000000000000UL;
1983 sparc64_va_hole_bottom = 0x0008000000000000UL;
1984 max_phys_bits = 47;
1985 break;
1986 case SUN4V_CHIP_SPARC_M7:
1987 case SUN4V_CHIP_SPARC_SN:
1988 /* M7 and later support 52-bit virtual addresses. */
1989 sparc64_va_hole_top = 0xfff8000000000000UL;
1990 sparc64_va_hole_bottom = 0x0008000000000000UL;
1991 max_phys_bits = 49;
1992 break;
1993 case SUN4V_CHIP_SPARC_M8:
1994 default:
1995 /* M8 and later support 54-bit virtual addresses.
1996 * However, restricting M8 and above VA bits to 53
1997 * as 4-level page table cannot support more than
1998 * 53 VA bits.
1999 */
2000 sparc64_va_hole_top = 0xfff0000000000000UL;
2001 sparc64_va_hole_bottom = 0x0010000000000000UL;
2002 max_phys_bits = 51;
2003 break;
2004 }
2005 }
2006
2007 if (max_phys_bits > MAX_PHYS_ADDRESS_BITS) {
2008 prom_printf("MAX_PHYS_ADDRESS_BITS is too small, need %lu\n",
2009 max_phys_bits);
2010 prom_halt();
2011 }
2012
2013 PAGE_OFFSET = sparc64_va_hole_top;
2014 VMALLOC_END = ((sparc64_va_hole_bottom >> 1) +
2015 (sparc64_va_hole_bottom >> 2));
2016
2017 pr_info("MM: PAGE_OFFSET is 0x%016lx (max_phys_bits == %lu)\n",
2018 PAGE_OFFSET, max_phys_bits);
2019 pr_info("MM: VMALLOC [0x%016lx --> 0x%016lx]\n",
2020 VMALLOC_START, VMALLOC_END);
2021 pr_info("MM: VMEMMAP [0x%016lx --> 0x%016lx]\n",
2022 VMEMMAP_BASE, VMEMMAP_BASE << 1);
2023}
2024
2025static void __init tsb_phys_patch(void)
2026{
2027 struct tsb_ldquad_phys_patch_entry *pquad;
2028 struct tsb_phys_patch_entry *p;
2029
2030 pquad = &__tsb_ldquad_phys_patch;
2031 while (pquad < &__tsb_ldquad_phys_patch_end) {
2032 unsigned long addr = pquad->addr;
2033
2034 if (tlb_type == hypervisor)
2035 *(unsigned int *) addr = pquad->sun4v_insn;
2036 else
2037 *(unsigned int *) addr = pquad->sun4u_insn;
2038 wmb();
2039 __asm__ __volatile__("flush %0"
2040 : /* no outputs */
2041 : "r" (addr));
2042
2043 pquad++;
2044 }
2045
2046 p = &__tsb_phys_patch;
2047 while (p < &__tsb_phys_patch_end) {
2048 unsigned long addr = p->addr;
2049
2050 *(unsigned int *) addr = p->insn;
2051 wmb();
2052 __asm__ __volatile__("flush %0"
2053 : /* no outputs */
2054 : "r" (addr));
2055
2056 p++;
2057 }
2058}
2059
2060/* Don't mark as init, we give this to the Hypervisor. */
2061#ifndef CONFIG_DEBUG_PAGEALLOC
2062#define NUM_KTSB_DESCR 2
2063#else
2064#define NUM_KTSB_DESCR 1
2065#endif
2066static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
2067
2068/* The swapper TSBs are loaded with a base sequence of:
2069 *
2070 * sethi %uhi(SYMBOL), REG1
2071 * sethi %hi(SYMBOL), REG2
2072 * or REG1, %ulo(SYMBOL), REG1
2073 * or REG2, %lo(SYMBOL), REG2
2074 * sllx REG1, 32, REG1
2075 * or REG1, REG2, REG1
2076 *
2077 * When we use physical addressing for the TSB accesses, we patch the
2078 * first four instructions in the above sequence.
2079 */
2080
2081static void patch_one_ktsb_phys(unsigned int *start, unsigned int *end, unsigned long pa)
2082{
2083 unsigned long high_bits, low_bits;
2084
2085 high_bits = (pa >> 32) & 0xffffffff;
2086 low_bits = (pa >> 0) & 0xffffffff;
2087
2088 while (start < end) {
2089 unsigned int *ia = (unsigned int *)(unsigned long)*start;
2090
2091 ia[0] = (ia[0] & ~0x3fffff) | (high_bits >> 10);
2092 __asm__ __volatile__("flush %0" : : "r" (ia));
2093
2094 ia[1] = (ia[1] & ~0x3fffff) | (low_bits >> 10);
2095 __asm__ __volatile__("flush %0" : : "r" (ia + 1));
2096
2097 ia[2] = (ia[2] & ~0x1fff) | (high_bits & 0x3ff);
2098 __asm__ __volatile__("flush %0" : : "r" (ia + 2));
2099
2100 ia[3] = (ia[3] & ~0x1fff) | (low_bits & 0x3ff);
2101 __asm__ __volatile__("flush %0" : : "r" (ia + 3));
2102
2103 start++;
2104 }
2105}
2106
2107static void ktsb_phys_patch(void)
2108{
2109 extern unsigned int __swapper_tsb_phys_patch;
2110 extern unsigned int __swapper_tsb_phys_patch_end;
2111 unsigned long ktsb_pa;
2112
2113 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
2114 patch_one_ktsb_phys(&__swapper_tsb_phys_patch,
2115 &__swapper_tsb_phys_patch_end, ktsb_pa);
2116#ifndef CONFIG_DEBUG_PAGEALLOC
2117 {
2118 extern unsigned int __swapper_4m_tsb_phys_patch;
2119 extern unsigned int __swapper_4m_tsb_phys_patch_end;
2120 ktsb_pa = (kern_base +
2121 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
2122 patch_one_ktsb_phys(&__swapper_4m_tsb_phys_patch,
2123 &__swapper_4m_tsb_phys_patch_end, ktsb_pa);
2124 }
2125#endif
2126}
2127
2128static void __init sun4v_ktsb_init(void)
2129{
2130 unsigned long ktsb_pa;
2131
2132 /* First KTSB for PAGE_SIZE mappings. */
2133 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
2134
2135 switch (PAGE_SIZE) {
2136 case 8 * 1024:
2137 default:
2138 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
2139 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
2140 break;
2141
2142 case 64 * 1024:
2143 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
2144 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
2145 break;
2146
2147 case 512 * 1024:
2148 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
2149 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
2150 break;
2151
2152 case 4 * 1024 * 1024:
2153 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
2154 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
2155 break;
2156 }
2157
2158 ktsb_descr[0].assoc = 1;
2159 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
2160 ktsb_descr[0].ctx_idx = 0;
2161 ktsb_descr[0].tsb_base = ktsb_pa;
2162 ktsb_descr[0].resv = 0;
2163
2164#ifndef CONFIG_DEBUG_PAGEALLOC
2165 /* Second KTSB for 4MB/256MB/2GB/16GB mappings. */
2166 ktsb_pa = (kern_base +
2167 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
2168
2169 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
2170 ktsb_descr[1].pgsz_mask = ((HV_PGSZ_MASK_4MB |
2171 HV_PGSZ_MASK_256MB |
2172 HV_PGSZ_MASK_2GB |
2173 HV_PGSZ_MASK_16GB) &
2174 cpu_pgsz_mask);
2175 ktsb_descr[1].assoc = 1;
2176 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
2177 ktsb_descr[1].ctx_idx = 0;
2178 ktsb_descr[1].tsb_base = ktsb_pa;
2179 ktsb_descr[1].resv = 0;
2180#endif
2181}
2182
2183void sun4v_ktsb_register(void)
2184{
2185 unsigned long pa, ret;
2186
2187 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
2188
2189 ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
2190 if (ret != 0) {
2191 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
2192 "errors with %lx\n", pa, ret);
2193 prom_halt();
2194 }
2195}
2196
2197static void __init sun4u_linear_pte_xor_finalize(void)
2198{
2199#ifndef CONFIG_DEBUG_PAGEALLOC
2200 /* This is where we would add Panther support for
2201 * 32MB and 256MB pages.
2202 */
2203#endif
2204}
2205
2206static void __init sun4v_linear_pte_xor_finalize(void)
2207{
2208 unsigned long pagecv_flag;
2209
2210 /* Bit 9 of TTE is no longer CV bit on M7 processor and it instead
2211 * enables MCD error. Do not set bit 9 on M7 processor.
2212 */
2213 switch (sun4v_chip_type) {
2214 case SUN4V_CHIP_SPARC_M7:
2215 case SUN4V_CHIP_SPARC_M8:
2216 case SUN4V_CHIP_SPARC_SN:
2217 pagecv_flag = 0x00;
2218 break;
2219 default:
2220 pagecv_flag = _PAGE_CV_4V;
2221 break;
2222 }
2223#ifndef CONFIG_DEBUG_PAGEALLOC
2224 if (cpu_pgsz_mask & HV_PGSZ_MASK_256MB) {
2225 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
2226 PAGE_OFFSET;
2227 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | pagecv_flag |
2228 _PAGE_P_4V | _PAGE_W_4V);
2229 } else {
2230 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
2231 }
2232
2233 if (cpu_pgsz_mask & HV_PGSZ_MASK_2GB) {
2234 kern_linear_pte_xor[2] = (_PAGE_VALID | _PAGE_SZ2GB_4V) ^
2235 PAGE_OFFSET;
2236 kern_linear_pte_xor[2] |= (_PAGE_CP_4V | pagecv_flag |
2237 _PAGE_P_4V | _PAGE_W_4V);
2238 } else {
2239 kern_linear_pte_xor[2] = kern_linear_pte_xor[1];
2240 }
2241
2242 if (cpu_pgsz_mask & HV_PGSZ_MASK_16GB) {
2243 kern_linear_pte_xor[3] = (_PAGE_VALID | _PAGE_SZ16GB_4V) ^
2244 PAGE_OFFSET;
2245 kern_linear_pte_xor[3] |= (_PAGE_CP_4V | pagecv_flag |
2246 _PAGE_P_4V | _PAGE_W_4V);
2247 } else {
2248 kern_linear_pte_xor[3] = kern_linear_pte_xor[2];
2249 }
2250#endif
2251}
2252
2253/* paging_init() sets up the page tables */
2254
2255static unsigned long last_valid_pfn;
2256
2257static void sun4u_pgprot_init(void);
2258static void sun4v_pgprot_init(void);
2259
2260static phys_addr_t __init available_memory(void)
2261{
2262 phys_addr_t available = 0ULL;
2263 phys_addr_t pa_start, pa_end;
2264 u64 i;
2265
2266 for_each_free_mem_range(i, NUMA_NO_NODE, MEMBLOCK_NONE, &pa_start,
2267 &pa_end, NULL)
2268 available = available + (pa_end - pa_start);
2269
2270 return available;
2271}
2272
2273#define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
2274#define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
2275#define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
2276#define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
2277#define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
2278#define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
2279
2280/* We need to exclude reserved regions. This exclusion will include
2281 * vmlinux and initrd. To be more precise the initrd size could be used to
2282 * compute a new lower limit because it is freed later during initialization.
2283 */
2284static void __init reduce_memory(phys_addr_t limit_ram)
2285{
2286 phys_addr_t avail_ram = available_memory();
2287 phys_addr_t pa_start, pa_end;
2288 u64 i;
2289
2290 if (limit_ram >= avail_ram)
2291 return;
2292
2293 for_each_free_mem_range(i, NUMA_NO_NODE, MEMBLOCK_NONE, &pa_start,
2294 &pa_end, NULL) {
2295 phys_addr_t region_size = pa_end - pa_start;
2296 phys_addr_t clip_start = pa_start;
2297
2298 avail_ram = avail_ram - region_size;
2299 /* Are we consuming too much? */
2300 if (avail_ram < limit_ram) {
2301 phys_addr_t give_back = limit_ram - avail_ram;
2302
2303 region_size = region_size - give_back;
2304 clip_start = clip_start + give_back;
2305 }
2306
2307 memblock_remove(clip_start, region_size);
2308
2309 if (avail_ram <= limit_ram)
2310 break;
2311 i = 0UL;
2312 }
2313}
2314
2315void __init paging_init(void)
2316{
2317 unsigned long end_pfn, shift, phys_base;
2318 unsigned long real_end, i;
2319
2320 setup_page_offset();
2321
2322 /* These build time checkes make sure that the dcache_dirty_cpu()
2323 * page->flags usage will work.
2324 *
2325 * When a page gets marked as dcache-dirty, we store the
2326 * cpu number starting at bit 32 in the page->flags. Also,
2327 * functions like clear_dcache_dirty_cpu use the cpu mask
2328 * in 13-bit signed-immediate instruction fields.
2329 */
2330
2331 /*
2332 * Page flags must not reach into upper 32 bits that are used
2333 * for the cpu number
2334 */
2335 BUILD_BUG_ON(NR_PAGEFLAGS > 32);
2336
2337 /*
2338 * The bit fields placed in the high range must not reach below
2339 * the 32 bit boundary. Otherwise we cannot place the cpu field
2340 * at the 32 bit boundary.
2341 */
2342 BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
2343 ilog2(roundup_pow_of_two(NR_CPUS)) > 32);
2344
2345 BUILD_BUG_ON(NR_CPUS > 4096);
2346
2347 kern_base = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
2348 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
2349
2350 /* Invalidate both kernel TSBs. */
2351 memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
2352#ifndef CONFIG_DEBUG_PAGEALLOC
2353 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
2354#endif
2355
2356 /* TTE.cv bit on sparc v9 occupies the same position as TTE.mcde
2357 * bit on M7 processor. This is a conflicting usage of the same
2358 * bit. Enabling TTE.cv on M7 would turn on Memory Corruption
2359 * Detection error on all pages and this will lead to problems
2360 * later. Kernel does not run with MCD enabled and hence rest
2361 * of the required steps to fully configure memory corruption
2362 * detection are not taken. We need to ensure TTE.mcde is not
2363 * set on M7 processor. Compute the value of cacheability
2364 * flag for use later taking this into consideration.
2365 */
2366 switch (sun4v_chip_type) {
2367 case SUN4V_CHIP_SPARC_M7:
2368 case SUN4V_CHIP_SPARC_M8:
2369 case SUN4V_CHIP_SPARC_SN:
2370 page_cache4v_flag = _PAGE_CP_4V;
2371 break;
2372 default:
2373 page_cache4v_flag = _PAGE_CACHE_4V;
2374 break;
2375 }
2376
2377 if (tlb_type == hypervisor)
2378 sun4v_pgprot_init();
2379 else
2380 sun4u_pgprot_init();
2381
2382 if (tlb_type == cheetah_plus ||
2383 tlb_type == hypervisor) {
2384 tsb_phys_patch();
2385 ktsb_phys_patch();
2386 }
2387
2388 if (tlb_type == hypervisor)
2389 sun4v_patch_tlb_handlers();
2390
2391 /* Find available physical memory...
2392 *
2393 * Read it twice in order to work around a bug in openfirmware.
2394 * The call to grab this table itself can cause openfirmware to
2395 * allocate memory, which in turn can take away some space from
2396 * the list of available memory. Reading it twice makes sure
2397 * we really do get the final value.
2398 */
2399 read_obp_translations();
2400 read_obp_memory("reg", &pall[0], &pall_ents);
2401 read_obp_memory("available", &pavail[0], &pavail_ents);
2402 read_obp_memory("available", &pavail[0], &pavail_ents);
2403
2404 phys_base = 0xffffffffffffffffUL;
2405 for (i = 0; i < pavail_ents; i++) {
2406 phys_base = min(phys_base, pavail[i].phys_addr);
2407 memblock_add(pavail[i].phys_addr, pavail[i].reg_size);
2408 }
2409
2410 memblock_reserve(kern_base, kern_size);
2411
2412 find_ramdisk(phys_base);
2413
2414 if (cmdline_memory_size)
2415 reduce_memory(cmdline_memory_size);
2416
2417 memblock_allow_resize();
2418 memblock_dump_all();
2419
2420 set_bit(0, mmu_context_bmap);
2421
2422 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
2423
2424 real_end = (unsigned long)_end;
2425 num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << ILOG2_4MB);
2426 printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
2427 num_kernel_image_mappings);
2428
2429 /* Set kernel pgd to upper alias so physical page computations
2430 * work.
2431 */
2432 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
2433
2434 memset(swapper_pg_dir, 0, sizeof(swapper_pg_dir));
2435
2436 inherit_prom_mappings();
2437
2438 /* Ok, we can use our TLB miss and window trap handlers safely. */
2439 setup_tba();
2440
2441 __flush_tlb_all();
2442
2443 prom_build_devicetree();
2444 of_populate_present_mask();
2445#ifndef CONFIG_SMP
2446 of_fill_in_cpu_data();
2447#endif
2448
2449 if (tlb_type == hypervisor) {
2450 sun4v_mdesc_init();
2451 mdesc_populate_present_mask(cpu_all_mask);
2452#ifndef CONFIG_SMP
2453 mdesc_fill_in_cpu_data(cpu_all_mask);
2454#endif
2455 mdesc_get_page_sizes(cpu_all_mask, &cpu_pgsz_mask);
2456
2457 sun4v_linear_pte_xor_finalize();
2458
2459 sun4v_ktsb_init();
2460 sun4v_ktsb_register();
2461 } else {
2462 unsigned long impl, ver;
2463
2464 cpu_pgsz_mask = (HV_PGSZ_MASK_8K | HV_PGSZ_MASK_64K |
2465 HV_PGSZ_MASK_512K | HV_PGSZ_MASK_4MB);
2466
2467 __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
2468 impl = ((ver >> 32) & 0xffff);
2469 if (impl == PANTHER_IMPL)
2470 cpu_pgsz_mask |= (HV_PGSZ_MASK_32MB |
2471 HV_PGSZ_MASK_256MB);
2472
2473 sun4u_linear_pte_xor_finalize();
2474 }
2475
2476 /* Flush the TLBs and the 4M TSB so that the updated linear
2477 * pte XOR settings are realized for all mappings.
2478 */
2479 __flush_tlb_all();
2480#ifndef CONFIG_DEBUG_PAGEALLOC
2481 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
2482#endif
2483 __flush_tlb_all();
2484
2485 /* Setup bootmem... */
2486 last_valid_pfn = end_pfn = bootmem_init(phys_base);
2487
2488 kernel_physical_mapping_init();
2489
2490 {
2491 unsigned long max_zone_pfns[MAX_NR_ZONES];
2492
2493 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
2494
2495 max_zone_pfns[ZONE_NORMAL] = end_pfn;
2496
2497 free_area_init_nodes(max_zone_pfns);
2498 }
2499
2500 printk("Booting Linux...\n");
2501}
2502
2503int page_in_phys_avail(unsigned long paddr)
2504{
2505 int i;
2506
2507 paddr &= PAGE_MASK;
2508
2509 for (i = 0; i < pavail_ents; i++) {
2510 unsigned long start, end;
2511
2512 start = pavail[i].phys_addr;
2513 end = start + pavail[i].reg_size;
2514
2515 if (paddr >= start && paddr < end)
2516 return 1;
2517 }
2518 if (paddr >= kern_base && paddr < (kern_base + kern_size))
2519 return 1;
2520#ifdef CONFIG_BLK_DEV_INITRD
2521 if (paddr >= __pa(initrd_start) &&
2522 paddr < __pa(PAGE_ALIGN(initrd_end)))
2523 return 1;
2524#endif
2525
2526 return 0;
2527}
2528
2529static void __init register_page_bootmem_info(void)
2530{
2531#ifdef CONFIG_NEED_MULTIPLE_NODES
2532 int i;
2533
2534 for_each_online_node(i)
2535 if (NODE_DATA(i)->node_spanned_pages)
2536 register_page_bootmem_info_node(NODE_DATA(i));
2537#endif
2538}
2539void __init mem_init(void)
2540{
2541 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
2542
2543 free_all_bootmem();
2544
2545 /*
2546 * Must be done after boot memory is put on freelist, because here we
2547 * might set fields in deferred struct pages that have not yet been
2548 * initialized, and free_all_bootmem() initializes all the reserved
2549 * deferred pages for us.
2550 */
2551 register_page_bootmem_info();
2552
2553 /*
2554 * Set up the zero page, mark it reserved, so that page count
2555 * is not manipulated when freeing the page from user ptes.
2556 */
2557 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
2558 if (mem_map_zero == NULL) {
2559 prom_printf("paging_init: Cannot alloc zero page.\n");
2560 prom_halt();
2561 }
2562 mark_page_reserved(mem_map_zero);
2563
2564 mem_init_print_info(NULL);
2565
2566 if (tlb_type == cheetah || tlb_type == cheetah_plus)
2567 cheetah_ecache_flush_init();
2568}
2569
2570void free_initmem(void)
2571{
2572 unsigned long addr, initend;
2573 int do_free = 1;
2574
2575 /* If the physical memory maps were trimmed by kernel command
2576 * line options, don't even try freeing this initmem stuff up.
2577 * The kernel image could have been in the trimmed out region
2578 * and if so the freeing below will free invalid page structs.
2579 */
2580 if (cmdline_memory_size)
2581 do_free = 0;
2582
2583 /*
2584 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
2585 */
2586 addr = PAGE_ALIGN((unsigned long)(__init_begin));
2587 initend = (unsigned long)(__init_end) & PAGE_MASK;
2588 for (; addr < initend; addr += PAGE_SIZE) {
2589 unsigned long page;
2590
2591 page = (addr +
2592 ((unsigned long) __va(kern_base)) -
2593 ((unsigned long) KERNBASE));
2594 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
2595
2596 if (do_free)
2597 free_reserved_page(virt_to_page(page));
2598 }
2599}
2600
2601#ifdef CONFIG_BLK_DEV_INITRD
2602void free_initrd_mem(unsigned long start, unsigned long end)
2603{
2604 free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM,
2605 "initrd");
2606}
2607#endif
2608
2609pgprot_t PAGE_KERNEL __read_mostly;
2610EXPORT_SYMBOL(PAGE_KERNEL);
2611
2612pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
2613pgprot_t PAGE_COPY __read_mostly;
2614
2615pgprot_t PAGE_SHARED __read_mostly;
2616EXPORT_SYMBOL(PAGE_SHARED);
2617
2618unsigned long pg_iobits __read_mostly;
2619
2620unsigned long _PAGE_IE __read_mostly;
2621EXPORT_SYMBOL(_PAGE_IE);
2622
2623unsigned long _PAGE_E __read_mostly;
2624EXPORT_SYMBOL(_PAGE_E);
2625
2626unsigned long _PAGE_CACHE __read_mostly;
2627EXPORT_SYMBOL(_PAGE_CACHE);
2628
2629#ifdef CONFIG_SPARSEMEM_VMEMMAP
2630int __meminit vmemmap_populate(unsigned long vstart, unsigned long vend,
2631 int node, struct vmem_altmap *altmap)
2632{
2633 unsigned long pte_base;
2634
2635 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2636 _PAGE_CP_4U | _PAGE_CV_4U |
2637 _PAGE_P_4U | _PAGE_W_4U);
2638 if (tlb_type == hypervisor)
2639 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2640 page_cache4v_flag | _PAGE_P_4V | _PAGE_W_4V);
2641
2642 pte_base |= _PAGE_PMD_HUGE;
2643
2644 vstart = vstart & PMD_MASK;
2645 vend = ALIGN(vend, PMD_SIZE);
2646 for (; vstart < vend; vstart += PMD_SIZE) {
2647 pgd_t *pgd = vmemmap_pgd_populate(vstart, node);
2648 unsigned long pte;
2649 pud_t *pud;
2650 pmd_t *pmd;
2651
2652 if (!pgd)
2653 return -ENOMEM;
2654
2655 pud = vmemmap_pud_populate(pgd, vstart, node);
2656 if (!pud)
2657 return -ENOMEM;
2658
2659 pmd = pmd_offset(pud, vstart);
2660 pte = pmd_val(*pmd);
2661 if (!(pte & _PAGE_VALID)) {
2662 void *block = vmemmap_alloc_block(PMD_SIZE, node);
2663
2664 if (!block)
2665 return -ENOMEM;
2666
2667 pmd_val(*pmd) = pte_base | __pa(block);
2668 }
2669 }
2670
2671 return 0;
2672}
2673
2674void vmemmap_free(unsigned long start, unsigned long end,
2675 struct vmem_altmap *altmap)
2676{
2677}
2678#endif /* CONFIG_SPARSEMEM_VMEMMAP */
2679
2680static void prot_init_common(unsigned long page_none,
2681 unsigned long page_shared,
2682 unsigned long page_copy,
2683 unsigned long page_readonly,
2684 unsigned long page_exec_bit)
2685{
2686 PAGE_COPY = __pgprot(page_copy);
2687 PAGE_SHARED = __pgprot(page_shared);
2688
2689 protection_map[0x0] = __pgprot(page_none);
2690 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
2691 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
2692 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
2693 protection_map[0x4] = __pgprot(page_readonly);
2694 protection_map[0x5] = __pgprot(page_readonly);
2695 protection_map[0x6] = __pgprot(page_copy);
2696 protection_map[0x7] = __pgprot(page_copy);
2697 protection_map[0x8] = __pgprot(page_none);
2698 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
2699 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
2700 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
2701 protection_map[0xc] = __pgprot(page_readonly);
2702 protection_map[0xd] = __pgprot(page_readonly);
2703 protection_map[0xe] = __pgprot(page_shared);
2704 protection_map[0xf] = __pgprot(page_shared);
2705}
2706
2707static void __init sun4u_pgprot_init(void)
2708{
2709 unsigned long page_none, page_shared, page_copy, page_readonly;
2710 unsigned long page_exec_bit;
2711 int i;
2712
2713 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2714 _PAGE_CACHE_4U | _PAGE_P_4U |
2715 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2716 _PAGE_EXEC_4U);
2717 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2718 _PAGE_CACHE_4U | _PAGE_P_4U |
2719 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2720 _PAGE_EXEC_4U | _PAGE_L_4U);
2721
2722 _PAGE_IE = _PAGE_IE_4U;
2723 _PAGE_E = _PAGE_E_4U;
2724 _PAGE_CACHE = _PAGE_CACHE_4U;
2725
2726 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
2727 __ACCESS_BITS_4U | _PAGE_E_4U);
2728
2729#ifdef CONFIG_DEBUG_PAGEALLOC
2730 kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
2731#else
2732 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
2733 PAGE_OFFSET;
2734#endif
2735 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
2736 _PAGE_P_4U | _PAGE_W_4U);
2737
2738 for (i = 1; i < 4; i++)
2739 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2740
2741 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
2742 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
2743 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
2744
2745
2746 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
2747 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2748 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
2749 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2750 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2751 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2752 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2753
2754 page_exec_bit = _PAGE_EXEC_4U;
2755
2756 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2757 page_exec_bit);
2758}
2759
2760static void __init sun4v_pgprot_init(void)
2761{
2762 unsigned long page_none, page_shared, page_copy, page_readonly;
2763 unsigned long page_exec_bit;
2764 int i;
2765
2766 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
2767 page_cache4v_flag | _PAGE_P_4V |
2768 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
2769 _PAGE_EXEC_4V);
2770 PAGE_KERNEL_LOCKED = PAGE_KERNEL;
2771
2772 _PAGE_IE = _PAGE_IE_4V;
2773 _PAGE_E = _PAGE_E_4V;
2774 _PAGE_CACHE = page_cache4v_flag;
2775
2776#ifdef CONFIG_DEBUG_PAGEALLOC
2777 kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
2778#else
2779 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
2780 PAGE_OFFSET;
2781#endif
2782 kern_linear_pte_xor[0] |= (page_cache4v_flag | _PAGE_P_4V |
2783 _PAGE_W_4V);
2784
2785 for (i = 1; i < 4; i++)
2786 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2787
2788 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
2789 __ACCESS_BITS_4V | _PAGE_E_4V);
2790
2791 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
2792 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
2793 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
2794 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
2795
2796 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | page_cache4v_flag;
2797 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2798 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
2799 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2800 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2801 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2802 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2803
2804 page_exec_bit = _PAGE_EXEC_4V;
2805
2806 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2807 page_exec_bit);
2808}
2809
2810unsigned long pte_sz_bits(unsigned long sz)
2811{
2812 if (tlb_type == hypervisor) {
2813 switch (sz) {
2814 case 8 * 1024:
2815 default:
2816 return _PAGE_SZ8K_4V;
2817 case 64 * 1024:
2818 return _PAGE_SZ64K_4V;
2819 case 512 * 1024:
2820 return _PAGE_SZ512K_4V;
2821 case 4 * 1024 * 1024:
2822 return _PAGE_SZ4MB_4V;
2823 }
2824 } else {
2825 switch (sz) {
2826 case 8 * 1024:
2827 default:
2828 return _PAGE_SZ8K_4U;
2829 case 64 * 1024:
2830 return _PAGE_SZ64K_4U;
2831 case 512 * 1024:
2832 return _PAGE_SZ512K_4U;
2833 case 4 * 1024 * 1024:
2834 return _PAGE_SZ4MB_4U;
2835 }
2836 }
2837}
2838
2839pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
2840{
2841 pte_t pte;
2842
2843 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot));
2844 pte_val(pte) |= (((unsigned long)space) << 32);
2845 pte_val(pte) |= pte_sz_bits(page_size);
2846
2847 return pte;
2848}
2849
2850static unsigned long kern_large_tte(unsigned long paddr)
2851{
2852 unsigned long val;
2853
2854 val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2855 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
2856 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
2857 if (tlb_type == hypervisor)
2858 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2859 page_cache4v_flag | _PAGE_P_4V |
2860 _PAGE_EXEC_4V | _PAGE_W_4V);
2861
2862 return val | paddr;
2863}
2864
2865/* If not locked, zap it. */
2866void __flush_tlb_all(void)
2867{
2868 unsigned long pstate;
2869 int i;
2870
2871 __asm__ __volatile__("flushw\n\t"
2872 "rdpr %%pstate, %0\n\t"
2873 "wrpr %0, %1, %%pstate"
2874 : "=r" (pstate)
2875 : "i" (PSTATE_IE));
2876 if (tlb_type == hypervisor) {
2877 sun4v_mmu_demap_all();
2878 } else if (tlb_type == spitfire) {
2879 for (i = 0; i < 64; i++) {
2880 /* Spitfire Errata #32 workaround */
2881 /* NOTE: Always runs on spitfire, so no
2882 * cheetah+ page size encodings.
2883 */
2884 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2885 "flush %%g6"
2886 : /* No outputs */
2887 : "r" (0),
2888 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2889
2890 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
2891 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2892 "membar #Sync"
2893 : /* no outputs */
2894 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
2895 spitfire_put_dtlb_data(i, 0x0UL);
2896 }
2897
2898 /* Spitfire Errata #32 workaround */
2899 /* NOTE: Always runs on spitfire, so no
2900 * cheetah+ page size encodings.
2901 */
2902 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2903 "flush %%g6"
2904 : /* No outputs */
2905 : "r" (0),
2906 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2907
2908 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
2909 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2910 "membar #Sync"
2911 : /* no outputs */
2912 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
2913 spitfire_put_itlb_data(i, 0x0UL);
2914 }
2915 }
2916 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
2917 cheetah_flush_dtlb_all();
2918 cheetah_flush_itlb_all();
2919 }
2920 __asm__ __volatile__("wrpr %0, 0, %%pstate"
2921 : : "r" (pstate));
2922}
2923
2924pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
2925 unsigned long address)
2926{
2927 struct page *page = alloc_page(GFP_KERNEL | __GFP_ZERO);
2928 pte_t *pte = NULL;
2929
2930 if (page)
2931 pte = (pte_t *) page_address(page);
2932
2933 return pte;
2934}
2935
2936pgtable_t pte_alloc_one(struct mm_struct *mm,
2937 unsigned long address)
2938{
2939 struct page *page = alloc_page(GFP_KERNEL | __GFP_ZERO);
2940 if (!page)
2941 return NULL;
2942 if (!pgtable_page_ctor(page)) {
2943 free_unref_page(page);
2944 return NULL;
2945 }
2946 return (pte_t *) page_address(page);
2947}
2948
2949void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
2950{
2951 free_page((unsigned long)pte);
2952}
2953
2954static void __pte_free(pgtable_t pte)
2955{
2956 struct page *page = virt_to_page(pte);
2957
2958 pgtable_page_dtor(page);
2959 __free_page(page);
2960}
2961
2962void pte_free(struct mm_struct *mm, pgtable_t pte)
2963{
2964 __pte_free(pte);
2965}
2966
2967void pgtable_free(void *table, bool is_page)
2968{
2969 if (is_page)
2970 __pte_free(table);
2971 else
2972 kmem_cache_free(pgtable_cache, table);
2973}
2974
2975#ifdef CONFIG_TRANSPARENT_HUGEPAGE
2976void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
2977 pmd_t *pmd)
2978{
2979 unsigned long pte, flags;
2980 struct mm_struct *mm;
2981 pmd_t entry = *pmd;
2982
2983 if (!pmd_large(entry) || !pmd_young(entry))
2984 return;
2985
2986 pte = pmd_val(entry);
2987
2988 /* Don't insert a non-valid PMD into the TSB, we'll deadlock. */
2989 if (!(pte & _PAGE_VALID))
2990 return;
2991
2992 /* We are fabricating 8MB pages using 4MB real hw pages. */
2993 pte |= (addr & (1UL << REAL_HPAGE_SHIFT));
2994
2995 mm = vma->vm_mm;
2996
2997 spin_lock_irqsave(&mm->context.lock, flags);
2998
2999 if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL)
3000 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT,
3001 addr, pte);
3002
3003 spin_unlock_irqrestore(&mm->context.lock, flags);
3004}
3005#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
3006
3007#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
3008static void context_reload(void *__data)
3009{
3010 struct mm_struct *mm = __data;
3011
3012 if (mm == current->mm)
3013 load_secondary_context(mm);
3014}
3015
3016void hugetlb_setup(struct pt_regs *regs)
3017{
3018 struct mm_struct *mm = current->mm;
3019 struct tsb_config *tp;
3020
3021 if (faulthandler_disabled() || !mm) {
3022 const struct exception_table_entry *entry;
3023
3024 entry = search_exception_tables(regs->tpc);
3025 if (entry) {
3026 regs->tpc = entry->fixup;
3027 regs->tnpc = regs->tpc + 4;
3028 return;
3029 }
3030 pr_alert("Unexpected HugeTLB setup in atomic context.\n");
3031 die_if_kernel("HugeTSB in atomic", regs);
3032 }
3033
3034 tp = &mm->context.tsb_block[MM_TSB_HUGE];
3035 if (likely(tp->tsb == NULL))
3036 tsb_grow(mm, MM_TSB_HUGE, 0);
3037
3038 tsb_context_switch(mm);
3039 smp_tsb_sync(mm);
3040
3041 /* On UltraSPARC-III+ and later, configure the second half of
3042 * the Data-TLB for huge pages.
3043 */
3044 if (tlb_type == cheetah_plus) {
3045 bool need_context_reload = false;
3046 unsigned long ctx;
3047
3048 spin_lock_irq(&ctx_alloc_lock);
3049 ctx = mm->context.sparc64_ctx_val;
3050 ctx &= ~CTX_PGSZ_MASK;
3051 ctx |= CTX_PGSZ_BASE << CTX_PGSZ0_SHIFT;
3052 ctx |= CTX_PGSZ_HUGE << CTX_PGSZ1_SHIFT;
3053
3054 if (ctx != mm->context.sparc64_ctx_val) {
3055 /* When changing the page size fields, we
3056 * must perform a context flush so that no
3057 * stale entries match. This flush must
3058 * occur with the original context register
3059 * settings.
3060 */
3061 do_flush_tlb_mm(mm);
3062
3063 /* Reload the context register of all processors
3064 * also executing in this address space.
3065 */
3066 mm->context.sparc64_ctx_val = ctx;
3067 need_context_reload = true;
3068 }
3069 spin_unlock_irq(&ctx_alloc_lock);
3070
3071 if (need_context_reload)
3072 on_each_cpu(context_reload, mm, 0);
3073 }
3074}
3075#endif
3076
3077static struct resource code_resource = {
3078 .name = "Kernel code",
3079 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
3080};
3081
3082static struct resource data_resource = {
3083 .name = "Kernel data",
3084 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
3085};
3086
3087static struct resource bss_resource = {
3088 .name = "Kernel bss",
3089 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
3090};
3091
3092static inline resource_size_t compute_kern_paddr(void *addr)
3093{
3094 return (resource_size_t) (addr - KERNBASE + kern_base);
3095}
3096
3097static void __init kernel_lds_init(void)
3098{
3099 code_resource.start = compute_kern_paddr(_text);
3100 code_resource.end = compute_kern_paddr(_etext - 1);
3101 data_resource.start = compute_kern_paddr(_etext);
3102 data_resource.end = compute_kern_paddr(_edata - 1);
3103 bss_resource.start = compute_kern_paddr(__bss_start);
3104 bss_resource.end = compute_kern_paddr(_end - 1);
3105}
3106
3107static int __init report_memory(void)
3108{
3109 int i;
3110 struct resource *res;
3111
3112 kernel_lds_init();
3113
3114 for (i = 0; i < pavail_ents; i++) {
3115 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
3116
3117 if (!res) {
3118 pr_warn("Failed to allocate source.\n");
3119 break;
3120 }
3121
3122 res->name = "System RAM";
3123 res->start = pavail[i].phys_addr;
3124 res->end = pavail[i].phys_addr + pavail[i].reg_size - 1;
3125 res->flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM;
3126
3127 if (insert_resource(&iomem_resource, res) < 0) {
3128 pr_warn("Resource insertion failed.\n");
3129 break;
3130 }
3131
3132 insert_resource(res, &code_resource);
3133 insert_resource(res, &data_resource);
3134 insert_resource(res, &bss_resource);
3135 }
3136
3137 return 0;
3138}
3139arch_initcall(report_memory);
3140
3141#ifdef CONFIG_SMP
3142#define do_flush_tlb_kernel_range smp_flush_tlb_kernel_range
3143#else
3144#define do_flush_tlb_kernel_range __flush_tlb_kernel_range
3145#endif
3146
3147void flush_tlb_kernel_range(unsigned long start, unsigned long end)
3148{
3149 if (start < HI_OBP_ADDRESS && end > LOW_OBP_ADDRESS) {
3150 if (start < LOW_OBP_ADDRESS) {
3151 flush_tsb_kernel_range(start, LOW_OBP_ADDRESS);
3152 do_flush_tlb_kernel_range(start, LOW_OBP_ADDRESS);
3153 }
3154 if (end > HI_OBP_ADDRESS) {
3155 flush_tsb_kernel_range(HI_OBP_ADDRESS, end);
3156 do_flush_tlb_kernel_range(HI_OBP_ADDRESS, end);
3157 }
3158 } else {
3159 flush_tsb_kernel_range(start, end);
3160 do_flush_tlb_kernel_range(start, end);
3161 }
3162}
3163
3164void copy_user_highpage(struct page *to, struct page *from,
3165 unsigned long vaddr, struct vm_area_struct *vma)
3166{
3167 char *vfrom, *vto;
3168
3169 vfrom = kmap_atomic(from);
3170 vto = kmap_atomic(to);
3171 copy_user_page(vto, vfrom, vaddr, to);
3172 kunmap_atomic(vto);
3173 kunmap_atomic(vfrom);
3174
3175 /* If this page has ADI enabled, copy over any ADI tags
3176 * as well
3177 */
3178 if (vma->vm_flags & VM_SPARC_ADI) {
3179 unsigned long pfrom, pto, i, adi_tag;
3180
3181 pfrom = page_to_phys(from);
3182 pto = page_to_phys(to);
3183
3184 for (i = pfrom; i < (pfrom + PAGE_SIZE); i += adi_blksize()) {
3185 asm volatile("ldxa [%1] %2, %0\n\t"
3186 : "=r" (adi_tag)
3187 : "r" (i), "i" (ASI_MCD_REAL));
3188 asm volatile("stxa %0, [%1] %2\n\t"
3189 :
3190 : "r" (adi_tag), "r" (pto),
3191 "i" (ASI_MCD_REAL));
3192 pto += adi_blksize();
3193 }
3194 asm volatile("membar #Sync\n\t");
3195 }
3196}
3197EXPORT_SYMBOL(copy_user_highpage);
3198
3199void copy_highpage(struct page *to, struct page *from)
3200{
3201 char *vfrom, *vto;
3202
3203 vfrom = kmap_atomic(from);
3204 vto = kmap_atomic(to);
3205 copy_page(vto, vfrom);
3206 kunmap_atomic(vto);
3207 kunmap_atomic(vfrom);
3208
3209 /* If this platform is ADI enabled, copy any ADI tags
3210 * as well
3211 */
3212 if (adi_capable()) {
3213 unsigned long pfrom, pto, i, adi_tag;
3214
3215 pfrom = page_to_phys(from);
3216 pto = page_to_phys(to);
3217
3218 for (i = pfrom; i < (pfrom + PAGE_SIZE); i += adi_blksize()) {
3219 asm volatile("ldxa [%1] %2, %0\n\t"
3220 : "=r" (adi_tag)
3221 : "r" (i), "i" (ASI_MCD_REAL));
3222 asm volatile("stxa %0, [%1] %2\n\t"
3223 :
3224 : "r" (adi_tag), "r" (pto),
3225 "i" (ASI_MCD_REAL));
3226 pto += adi_blksize();
3227 }
3228 asm volatile("membar #Sync\n\t");
3229 }
3230}
3231EXPORT_SYMBOL(copy_highpage);
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * arch/sparc64/mm/init.c
4 *
5 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
6 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
7 */
8
9#include <linux/extable.h>
10#include <linux/kernel.h>
11#include <linux/sched.h>
12#include <linux/string.h>
13#include <linux/init.h>
14#include <linux/memblock.h>
15#include <linux/mm.h>
16#include <linux/hugetlb.h>
17#include <linux/initrd.h>
18#include <linux/swap.h>
19#include <linux/pagemap.h>
20#include <linux/poison.h>
21#include <linux/fs.h>
22#include <linux/seq_file.h>
23#include <linux/kprobes.h>
24#include <linux/cache.h>
25#include <linux/sort.h>
26#include <linux/ioport.h>
27#include <linux/percpu.h>
28#include <linux/mmzone.h>
29#include <linux/gfp.h>
30#include <linux/bootmem_info.h>
31
32#include <asm/head.h>
33#include <asm/page.h>
34#include <asm/pgalloc.h>
35#include <asm/oplib.h>
36#include <asm/iommu.h>
37#include <asm/io.h>
38#include <linux/uaccess.h>
39#include <asm/mmu_context.h>
40#include <asm/tlbflush.h>
41#include <asm/dma.h>
42#include <asm/starfire.h>
43#include <asm/tlb.h>
44#include <asm/spitfire.h>
45#include <asm/sections.h>
46#include <asm/tsb.h>
47#include <asm/hypervisor.h>
48#include <asm/prom.h>
49#include <asm/mdesc.h>
50#include <asm/cpudata.h>
51#include <asm/setup.h>
52#include <asm/irq.h>
53
54#include "init_64.h"
55
56unsigned long kern_linear_pte_xor[4] __read_mostly;
57static unsigned long page_cache4v_flag;
58
59/* A bitmap, two bits for every 256MB of physical memory. These two
60 * bits determine what page size we use for kernel linear
61 * translations. They form an index into kern_linear_pte_xor[]. The
62 * value in the indexed slot is XOR'd with the TLB miss virtual
63 * address to form the resulting TTE. The mapping is:
64 *
65 * 0 ==> 4MB
66 * 1 ==> 256MB
67 * 2 ==> 2GB
68 * 3 ==> 16GB
69 *
70 * All sun4v chips support 256MB pages. Only SPARC-T4 and later
71 * support 2GB pages, and hopefully future cpus will support the 16GB
72 * pages as well. For slots 2 and 3, we encode a 256MB TTE xor there
73 * if these larger page sizes are not supported by the cpu.
74 *
75 * It would be nice to determine this from the machine description
76 * 'cpu' properties, but we need to have this table setup before the
77 * MDESC is initialized.
78 */
79
80#ifndef CONFIG_DEBUG_PAGEALLOC
81/* A special kernel TSB for 4MB, 256MB, 2GB and 16GB linear mappings.
82 * Space is allocated for this right after the trap table in
83 * arch/sparc64/kernel/head.S
84 */
85extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
86#endif
87extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
88
89static unsigned long cpu_pgsz_mask;
90
91#define MAX_BANKS 1024
92
93static struct linux_prom64_registers pavail[MAX_BANKS];
94static int pavail_ents;
95
96u64 numa_latency[MAX_NUMNODES][MAX_NUMNODES];
97
98static int cmp_p64(const void *a, const void *b)
99{
100 const struct linux_prom64_registers *x = a, *y = b;
101
102 if (x->phys_addr > y->phys_addr)
103 return 1;
104 if (x->phys_addr < y->phys_addr)
105 return -1;
106 return 0;
107}
108
109static void __init read_obp_memory(const char *property,
110 struct linux_prom64_registers *regs,
111 int *num_ents)
112{
113 phandle node = prom_finddevice("/memory");
114 int prop_size = prom_getproplen(node, property);
115 int ents, ret, i;
116
117 ents = prop_size / sizeof(struct linux_prom64_registers);
118 if (ents > MAX_BANKS) {
119 prom_printf("The machine has more %s property entries than "
120 "this kernel can support (%d).\n",
121 property, MAX_BANKS);
122 prom_halt();
123 }
124
125 ret = prom_getproperty(node, property, (char *) regs, prop_size);
126 if (ret == -1) {
127 prom_printf("Couldn't get %s property from /memory.\n",
128 property);
129 prom_halt();
130 }
131
132 /* Sanitize what we got from the firmware, by page aligning
133 * everything.
134 */
135 for (i = 0; i < ents; i++) {
136 unsigned long base, size;
137
138 base = regs[i].phys_addr;
139 size = regs[i].reg_size;
140
141 size &= PAGE_MASK;
142 if (base & ~PAGE_MASK) {
143 unsigned long new_base = PAGE_ALIGN(base);
144
145 size -= new_base - base;
146 if ((long) size < 0L)
147 size = 0UL;
148 base = new_base;
149 }
150 if (size == 0UL) {
151 /* If it is empty, simply get rid of it.
152 * This simplifies the logic of the other
153 * functions that process these arrays.
154 */
155 memmove(®s[i], ®s[i + 1],
156 (ents - i - 1) * sizeof(regs[0]));
157 i--;
158 ents--;
159 continue;
160 }
161 regs[i].phys_addr = base;
162 regs[i].reg_size = size;
163 }
164
165 *num_ents = ents;
166
167 sort(regs, ents, sizeof(struct linux_prom64_registers),
168 cmp_p64, NULL);
169}
170
171/* Kernel physical address base and size in bytes. */
172unsigned long kern_base __read_mostly;
173unsigned long kern_size __read_mostly;
174
175/* Initial ramdisk setup */
176extern unsigned long sparc_ramdisk_image64;
177extern unsigned int sparc_ramdisk_image;
178extern unsigned int sparc_ramdisk_size;
179
180struct page *mem_map_zero __read_mostly;
181EXPORT_SYMBOL(mem_map_zero);
182
183unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
184
185unsigned long sparc64_kern_pri_context __read_mostly;
186unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
187unsigned long sparc64_kern_sec_context __read_mostly;
188
189int num_kernel_image_mappings;
190
191#ifdef CONFIG_DEBUG_DCFLUSH
192atomic_t dcpage_flushes = ATOMIC_INIT(0);
193#ifdef CONFIG_SMP
194atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
195#endif
196#endif
197
198inline void flush_dcache_folio_impl(struct folio *folio)
199{
200 unsigned int i, nr = folio_nr_pages(folio);
201
202 BUG_ON(tlb_type == hypervisor);
203#ifdef CONFIG_DEBUG_DCFLUSH
204 atomic_inc(&dcpage_flushes);
205#endif
206
207#ifdef DCACHE_ALIASING_POSSIBLE
208 for (i = 0; i < nr; i++)
209 __flush_dcache_page(folio_address(folio) + i * PAGE_SIZE,
210 ((tlb_type == spitfire) &&
211 folio_flush_mapping(folio) != NULL));
212#else
213 if (folio_flush_mapping(folio) != NULL &&
214 tlb_type == spitfire) {
215 for (i = 0; i < nr; i++)
216 __flush_icache_page((pfn + i) * PAGE_SIZE);
217 }
218#endif
219}
220
221#define PG_dcache_dirty PG_arch_1
222#define PG_dcache_cpu_shift 32UL
223#define PG_dcache_cpu_mask \
224 ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
225
226#define dcache_dirty_cpu(folio) \
227 (((folio)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
228
229static inline void set_dcache_dirty(struct folio *folio, int this_cpu)
230{
231 unsigned long mask = this_cpu;
232 unsigned long non_cpu_bits;
233
234 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
235 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
236
237 __asm__ __volatile__("1:\n\t"
238 "ldx [%2], %%g7\n\t"
239 "and %%g7, %1, %%g1\n\t"
240 "or %%g1, %0, %%g1\n\t"
241 "casx [%2], %%g7, %%g1\n\t"
242 "cmp %%g7, %%g1\n\t"
243 "bne,pn %%xcc, 1b\n\t"
244 " nop"
245 : /* no outputs */
246 : "r" (mask), "r" (non_cpu_bits), "r" (&folio->flags)
247 : "g1", "g7");
248}
249
250static inline void clear_dcache_dirty_cpu(struct folio *folio, unsigned long cpu)
251{
252 unsigned long mask = (1UL << PG_dcache_dirty);
253
254 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
255 "1:\n\t"
256 "ldx [%2], %%g7\n\t"
257 "srlx %%g7, %4, %%g1\n\t"
258 "and %%g1, %3, %%g1\n\t"
259 "cmp %%g1, %0\n\t"
260 "bne,pn %%icc, 2f\n\t"
261 " andn %%g7, %1, %%g1\n\t"
262 "casx [%2], %%g7, %%g1\n\t"
263 "cmp %%g7, %%g1\n\t"
264 "bne,pn %%xcc, 1b\n\t"
265 " nop\n"
266 "2:"
267 : /* no outputs */
268 : "r" (cpu), "r" (mask), "r" (&folio->flags),
269 "i" (PG_dcache_cpu_mask),
270 "i" (PG_dcache_cpu_shift)
271 : "g1", "g7");
272}
273
274static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
275{
276 unsigned long tsb_addr = (unsigned long) ent;
277
278 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
279 tsb_addr = __pa(tsb_addr);
280
281 __tsb_insert(tsb_addr, tag, pte);
282}
283
284unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
285
286static void flush_dcache(unsigned long pfn)
287{
288 struct page *page;
289
290 page = pfn_to_page(pfn);
291 if (page) {
292 struct folio *folio = page_folio(page);
293 unsigned long pg_flags;
294
295 pg_flags = folio->flags;
296 if (pg_flags & (1UL << PG_dcache_dirty)) {
297 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
298 PG_dcache_cpu_mask);
299 int this_cpu = get_cpu();
300
301 /* This is just to optimize away some function calls
302 * in the SMP case.
303 */
304 if (cpu == this_cpu)
305 flush_dcache_folio_impl(folio);
306 else
307 smp_flush_dcache_folio_impl(folio, cpu);
308
309 clear_dcache_dirty_cpu(folio, cpu);
310
311 put_cpu();
312 }
313 }
314}
315
316/* mm->context.lock must be held */
317static void __update_mmu_tsb_insert(struct mm_struct *mm, unsigned long tsb_index,
318 unsigned long tsb_hash_shift, unsigned long address,
319 unsigned long tte)
320{
321 struct tsb *tsb = mm->context.tsb_block[tsb_index].tsb;
322 unsigned long tag;
323
324 if (unlikely(!tsb))
325 return;
326
327 tsb += ((address >> tsb_hash_shift) &
328 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
329 tag = (address >> 22UL);
330 tsb_insert(tsb, tag, tte);
331}
332
333#ifdef CONFIG_HUGETLB_PAGE
334static int __init hugetlbpage_init(void)
335{
336 hugetlb_add_hstate(HPAGE_64K_SHIFT - PAGE_SHIFT);
337 hugetlb_add_hstate(HPAGE_SHIFT - PAGE_SHIFT);
338 hugetlb_add_hstate(HPAGE_256MB_SHIFT - PAGE_SHIFT);
339 hugetlb_add_hstate(HPAGE_2GB_SHIFT - PAGE_SHIFT);
340
341 return 0;
342}
343
344arch_initcall(hugetlbpage_init);
345
346static void __init pud_huge_patch(void)
347{
348 struct pud_huge_patch_entry *p;
349 unsigned long addr;
350
351 p = &__pud_huge_patch;
352 addr = p->addr;
353 *(unsigned int *)addr = p->insn;
354
355 __asm__ __volatile__("flush %0" : : "r" (addr));
356}
357
358bool __init arch_hugetlb_valid_size(unsigned long size)
359{
360 unsigned int hugepage_shift = ilog2(size);
361 unsigned short hv_pgsz_idx;
362 unsigned int hv_pgsz_mask;
363
364 switch (hugepage_shift) {
365 case HPAGE_16GB_SHIFT:
366 hv_pgsz_mask = HV_PGSZ_MASK_16GB;
367 hv_pgsz_idx = HV_PGSZ_IDX_16GB;
368 pud_huge_patch();
369 break;
370 case HPAGE_2GB_SHIFT:
371 hv_pgsz_mask = HV_PGSZ_MASK_2GB;
372 hv_pgsz_idx = HV_PGSZ_IDX_2GB;
373 break;
374 case HPAGE_256MB_SHIFT:
375 hv_pgsz_mask = HV_PGSZ_MASK_256MB;
376 hv_pgsz_idx = HV_PGSZ_IDX_256MB;
377 break;
378 case HPAGE_SHIFT:
379 hv_pgsz_mask = HV_PGSZ_MASK_4MB;
380 hv_pgsz_idx = HV_PGSZ_IDX_4MB;
381 break;
382 case HPAGE_64K_SHIFT:
383 hv_pgsz_mask = HV_PGSZ_MASK_64K;
384 hv_pgsz_idx = HV_PGSZ_IDX_64K;
385 break;
386 default:
387 hv_pgsz_mask = 0;
388 }
389
390 if ((hv_pgsz_mask & cpu_pgsz_mask) == 0U)
391 return false;
392
393 return true;
394}
395#endif /* CONFIG_HUGETLB_PAGE */
396
397void update_mmu_cache_range(struct vm_fault *vmf, struct vm_area_struct *vma,
398 unsigned long address, pte_t *ptep, unsigned int nr)
399{
400 struct mm_struct *mm;
401 unsigned long flags;
402 bool is_huge_tsb;
403 pte_t pte = *ptep;
404 unsigned int i;
405
406 if (tlb_type != hypervisor) {
407 unsigned long pfn = pte_pfn(pte);
408
409 if (pfn_valid(pfn))
410 flush_dcache(pfn);
411 }
412
413 mm = vma->vm_mm;
414
415 /* Don't insert a non-valid PTE into the TSB, we'll deadlock. */
416 if (!pte_accessible(mm, pte))
417 return;
418
419 spin_lock_irqsave(&mm->context.lock, flags);
420
421 is_huge_tsb = false;
422#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
423 if (mm->context.hugetlb_pte_count || mm->context.thp_pte_count) {
424 unsigned long hugepage_size = PAGE_SIZE;
425
426 if (is_vm_hugetlb_page(vma))
427 hugepage_size = huge_page_size(hstate_vma(vma));
428
429 if (hugepage_size >= PUD_SIZE) {
430 unsigned long mask = 0x1ffc00000UL;
431
432 /* Transfer bits [32:22] from address to resolve
433 * at 4M granularity.
434 */
435 pte_val(pte) &= ~mask;
436 pte_val(pte) |= (address & mask);
437 } else if (hugepage_size >= PMD_SIZE) {
438 /* We are fabricating 8MB pages using 4MB
439 * real hw pages.
440 */
441 pte_val(pte) |= (address & (1UL << REAL_HPAGE_SHIFT));
442 }
443
444 if (hugepage_size >= PMD_SIZE) {
445 __update_mmu_tsb_insert(mm, MM_TSB_HUGE,
446 REAL_HPAGE_SHIFT, address, pte_val(pte));
447 is_huge_tsb = true;
448 }
449 }
450#endif
451 if (!is_huge_tsb) {
452 for (i = 0; i < nr; i++) {
453 __update_mmu_tsb_insert(mm, MM_TSB_BASE, PAGE_SHIFT,
454 address, pte_val(pte));
455 address += PAGE_SIZE;
456 pte_val(pte) += PAGE_SIZE;
457 }
458 }
459
460 spin_unlock_irqrestore(&mm->context.lock, flags);
461}
462
463void flush_dcache_folio(struct folio *folio)
464{
465 unsigned long pfn = folio_pfn(folio);
466 struct address_space *mapping;
467 int this_cpu;
468
469 if (tlb_type == hypervisor)
470 return;
471
472 /* Do not bother with the expensive D-cache flush if it
473 * is merely the zero page. The 'bigcore' testcase in GDB
474 * causes this case to run millions of times.
475 */
476 if (is_zero_pfn(pfn))
477 return;
478
479 this_cpu = get_cpu();
480
481 mapping = folio_flush_mapping(folio);
482 if (mapping && !mapping_mapped(mapping)) {
483 bool dirty = test_bit(PG_dcache_dirty, &folio->flags);
484 if (dirty) {
485 int dirty_cpu = dcache_dirty_cpu(folio);
486
487 if (dirty_cpu == this_cpu)
488 goto out;
489 smp_flush_dcache_folio_impl(folio, dirty_cpu);
490 }
491 set_dcache_dirty(folio, this_cpu);
492 } else {
493 /* We could delay the flush for the !page_mapping
494 * case too. But that case is for exec env/arg
495 * pages and those are %99 certainly going to get
496 * faulted into the tlb (and thus flushed) anyways.
497 */
498 flush_dcache_folio_impl(folio);
499 }
500
501out:
502 put_cpu();
503}
504EXPORT_SYMBOL(flush_dcache_folio);
505
506void __kprobes flush_icache_range(unsigned long start, unsigned long end)
507{
508 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
509 if (tlb_type == spitfire) {
510 unsigned long kaddr;
511
512 /* This code only runs on Spitfire cpus so this is
513 * why we can assume _PAGE_PADDR_4U.
514 */
515 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
516 unsigned long paddr, mask = _PAGE_PADDR_4U;
517
518 if (kaddr >= PAGE_OFFSET)
519 paddr = kaddr & mask;
520 else {
521 pte_t *ptep = virt_to_kpte(kaddr);
522
523 paddr = pte_val(*ptep) & mask;
524 }
525 __flush_icache_page(paddr);
526 }
527 }
528}
529EXPORT_SYMBOL(flush_icache_range);
530
531void mmu_info(struct seq_file *m)
532{
533 static const char *pgsz_strings[] = {
534 "8K", "64K", "512K", "4MB", "32MB",
535 "256MB", "2GB", "16GB",
536 };
537 int i, printed;
538
539 if (tlb_type == cheetah)
540 seq_printf(m, "MMU Type\t: Cheetah\n");
541 else if (tlb_type == cheetah_plus)
542 seq_printf(m, "MMU Type\t: Cheetah+\n");
543 else if (tlb_type == spitfire)
544 seq_printf(m, "MMU Type\t: Spitfire\n");
545 else if (tlb_type == hypervisor)
546 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
547 else
548 seq_printf(m, "MMU Type\t: ???\n");
549
550 seq_printf(m, "MMU PGSZs\t: ");
551 printed = 0;
552 for (i = 0; i < ARRAY_SIZE(pgsz_strings); i++) {
553 if (cpu_pgsz_mask & (1UL << i)) {
554 seq_printf(m, "%s%s",
555 printed ? "," : "", pgsz_strings[i]);
556 printed++;
557 }
558 }
559 seq_putc(m, '\n');
560
561#ifdef CONFIG_DEBUG_DCFLUSH
562 seq_printf(m, "DCPageFlushes\t: %d\n",
563 atomic_read(&dcpage_flushes));
564#ifdef CONFIG_SMP
565 seq_printf(m, "DCPageFlushesXC\t: %d\n",
566 atomic_read(&dcpage_flushes_xcall));
567#endif /* CONFIG_SMP */
568#endif /* CONFIG_DEBUG_DCFLUSH */
569}
570
571struct linux_prom_translation prom_trans[512] __read_mostly;
572unsigned int prom_trans_ents __read_mostly;
573
574unsigned long kern_locked_tte_data;
575
576/* The obp translations are saved based on 8k pagesize, since obp can
577 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
578 * HI_OBP_ADDRESS range are handled in ktlb.S.
579 */
580static inline int in_obp_range(unsigned long vaddr)
581{
582 return (vaddr >= LOW_OBP_ADDRESS &&
583 vaddr < HI_OBP_ADDRESS);
584}
585
586static int cmp_ptrans(const void *a, const void *b)
587{
588 const struct linux_prom_translation *x = a, *y = b;
589
590 if (x->virt > y->virt)
591 return 1;
592 if (x->virt < y->virt)
593 return -1;
594 return 0;
595}
596
597/* Read OBP translations property into 'prom_trans[]'. */
598static void __init read_obp_translations(void)
599{
600 int n, node, ents, first, last, i;
601
602 node = prom_finddevice("/virtual-memory");
603 n = prom_getproplen(node, "translations");
604 if (unlikely(n == 0 || n == -1)) {
605 prom_printf("prom_mappings: Couldn't get size.\n");
606 prom_halt();
607 }
608 if (unlikely(n > sizeof(prom_trans))) {
609 prom_printf("prom_mappings: Size %d is too big.\n", n);
610 prom_halt();
611 }
612
613 if ((n = prom_getproperty(node, "translations",
614 (char *)&prom_trans[0],
615 sizeof(prom_trans))) == -1) {
616 prom_printf("prom_mappings: Couldn't get property.\n");
617 prom_halt();
618 }
619
620 n = n / sizeof(struct linux_prom_translation);
621
622 ents = n;
623
624 sort(prom_trans, ents, sizeof(struct linux_prom_translation),
625 cmp_ptrans, NULL);
626
627 /* Now kick out all the non-OBP entries. */
628 for (i = 0; i < ents; i++) {
629 if (in_obp_range(prom_trans[i].virt))
630 break;
631 }
632 first = i;
633 for (; i < ents; i++) {
634 if (!in_obp_range(prom_trans[i].virt))
635 break;
636 }
637 last = i;
638
639 for (i = 0; i < (last - first); i++) {
640 struct linux_prom_translation *src = &prom_trans[i + first];
641 struct linux_prom_translation *dest = &prom_trans[i];
642
643 *dest = *src;
644 }
645 for (; i < ents; i++) {
646 struct linux_prom_translation *dest = &prom_trans[i];
647 dest->virt = dest->size = dest->data = 0x0UL;
648 }
649
650 prom_trans_ents = last - first;
651
652 if (tlb_type == spitfire) {
653 /* Clear diag TTE bits. */
654 for (i = 0; i < prom_trans_ents; i++)
655 prom_trans[i].data &= ~0x0003fe0000000000UL;
656 }
657
658 /* Force execute bit on. */
659 for (i = 0; i < prom_trans_ents; i++)
660 prom_trans[i].data |= (tlb_type == hypervisor ?
661 _PAGE_EXEC_4V : _PAGE_EXEC_4U);
662}
663
664static void __init hypervisor_tlb_lock(unsigned long vaddr,
665 unsigned long pte,
666 unsigned long mmu)
667{
668 unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
669
670 if (ret != 0) {
671 prom_printf("hypervisor_tlb_lock[%lx:%x:%lx:%lx]: "
672 "errors with %lx\n", vaddr, 0, pte, mmu, ret);
673 prom_halt();
674 }
675}
676
677static unsigned long kern_large_tte(unsigned long paddr);
678
679static void __init remap_kernel(void)
680{
681 unsigned long phys_page, tte_vaddr, tte_data;
682 int i, tlb_ent = sparc64_highest_locked_tlbent();
683
684 tte_vaddr = (unsigned long) KERNBASE;
685 phys_page = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
686 tte_data = kern_large_tte(phys_page);
687
688 kern_locked_tte_data = tte_data;
689
690 /* Now lock us into the TLBs via Hypervisor or OBP. */
691 if (tlb_type == hypervisor) {
692 for (i = 0; i < num_kernel_image_mappings; i++) {
693 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
694 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
695 tte_vaddr += 0x400000;
696 tte_data += 0x400000;
697 }
698 } else {
699 for (i = 0; i < num_kernel_image_mappings; i++) {
700 prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr);
701 prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr);
702 tte_vaddr += 0x400000;
703 tte_data += 0x400000;
704 }
705 sparc64_highest_unlocked_tlb_ent = tlb_ent - i;
706 }
707 if (tlb_type == cheetah_plus) {
708 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
709 CTX_CHEETAH_PLUS_NUC);
710 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
711 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
712 }
713}
714
715
716static void __init inherit_prom_mappings(void)
717{
718 /* Now fixup OBP's idea about where we really are mapped. */
719 printk("Remapping the kernel... ");
720 remap_kernel();
721 printk("done.\n");
722}
723
724void prom_world(int enter)
725{
726 /*
727 * No need to change the address space any more, just flush
728 * the register windows
729 */
730 __asm__ __volatile__("flushw");
731}
732
733void __flush_dcache_range(unsigned long start, unsigned long end)
734{
735 unsigned long va;
736
737 if (tlb_type == spitfire) {
738 int n = 0;
739
740 for (va = start; va < end; va += 32) {
741 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
742 if (++n >= 512)
743 break;
744 }
745 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
746 start = __pa(start);
747 end = __pa(end);
748 for (va = start; va < end; va += 32)
749 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
750 "membar #Sync"
751 : /* no outputs */
752 : "r" (va),
753 "i" (ASI_DCACHE_INVALIDATE));
754 }
755}
756EXPORT_SYMBOL(__flush_dcache_range);
757
758/* get_new_mmu_context() uses "cache + 1". */
759DEFINE_SPINLOCK(ctx_alloc_lock);
760unsigned long tlb_context_cache = CTX_FIRST_VERSION;
761#define MAX_CTX_NR (1UL << CTX_NR_BITS)
762#define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR)
763DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
764DEFINE_PER_CPU(struct mm_struct *, per_cpu_secondary_mm) = {0};
765
766static void mmu_context_wrap(void)
767{
768 unsigned long old_ver = tlb_context_cache & CTX_VERSION_MASK;
769 unsigned long new_ver, new_ctx, old_ctx;
770 struct mm_struct *mm;
771 int cpu;
772
773 bitmap_zero(mmu_context_bmap, 1 << CTX_NR_BITS);
774
775 /* Reserve kernel context */
776 set_bit(0, mmu_context_bmap);
777
778 new_ver = (tlb_context_cache & CTX_VERSION_MASK) + CTX_FIRST_VERSION;
779 if (unlikely(new_ver == 0))
780 new_ver = CTX_FIRST_VERSION;
781 tlb_context_cache = new_ver;
782
783 /*
784 * Make sure that any new mm that are added into per_cpu_secondary_mm,
785 * are going to go through get_new_mmu_context() path.
786 */
787 mb();
788
789 /*
790 * Updated versions to current on those CPUs that had valid secondary
791 * contexts
792 */
793 for_each_online_cpu(cpu) {
794 /*
795 * If a new mm is stored after we took this mm from the array,
796 * it will go into get_new_mmu_context() path, because we
797 * already bumped the version in tlb_context_cache.
798 */
799 mm = per_cpu(per_cpu_secondary_mm, cpu);
800
801 if (unlikely(!mm || mm == &init_mm))
802 continue;
803
804 old_ctx = mm->context.sparc64_ctx_val;
805 if (likely((old_ctx & CTX_VERSION_MASK) == old_ver)) {
806 new_ctx = (old_ctx & ~CTX_VERSION_MASK) | new_ver;
807 set_bit(new_ctx & CTX_NR_MASK, mmu_context_bmap);
808 mm->context.sparc64_ctx_val = new_ctx;
809 }
810 }
811}
812
813/* Caller does TLB context flushing on local CPU if necessary.
814 * The caller also ensures that CTX_VALID(mm->context) is false.
815 *
816 * We must be careful about boundary cases so that we never
817 * let the user have CTX 0 (nucleus) or we ever use a CTX
818 * version of zero (and thus NO_CONTEXT would not be caught
819 * by version mis-match tests in mmu_context.h).
820 *
821 * Always invoked with interrupts disabled.
822 */
823void get_new_mmu_context(struct mm_struct *mm)
824{
825 unsigned long ctx, new_ctx;
826 unsigned long orig_pgsz_bits;
827
828 spin_lock(&ctx_alloc_lock);
829retry:
830 /* wrap might have happened, test again if our context became valid */
831 if (unlikely(CTX_VALID(mm->context)))
832 goto out;
833 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
834 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
835 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
836 if (new_ctx >= (1 << CTX_NR_BITS)) {
837 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
838 if (new_ctx >= ctx) {
839 mmu_context_wrap();
840 goto retry;
841 }
842 }
843 if (mm->context.sparc64_ctx_val)
844 cpumask_clear(mm_cpumask(mm));
845 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
846 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
847 tlb_context_cache = new_ctx;
848 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
849out:
850 spin_unlock(&ctx_alloc_lock);
851}
852
853static int numa_enabled = 1;
854static int numa_debug;
855
856static int __init early_numa(char *p)
857{
858 if (!p)
859 return 0;
860
861 if (strstr(p, "off"))
862 numa_enabled = 0;
863
864 if (strstr(p, "debug"))
865 numa_debug = 1;
866
867 return 0;
868}
869early_param("numa", early_numa);
870
871#define numadbg(f, a...) \
872do { if (numa_debug) \
873 printk(KERN_INFO f, ## a); \
874} while (0)
875
876static void __init find_ramdisk(unsigned long phys_base)
877{
878#ifdef CONFIG_BLK_DEV_INITRD
879 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
880 unsigned long ramdisk_image;
881
882 /* Older versions of the bootloader only supported a
883 * 32-bit physical address for the ramdisk image
884 * location, stored at sparc_ramdisk_image. Newer
885 * SILO versions set sparc_ramdisk_image to zero and
886 * provide a full 64-bit physical address at
887 * sparc_ramdisk_image64.
888 */
889 ramdisk_image = sparc_ramdisk_image;
890 if (!ramdisk_image)
891 ramdisk_image = sparc_ramdisk_image64;
892
893 /* Another bootloader quirk. The bootloader normalizes
894 * the physical address to KERNBASE, so we have to
895 * factor that back out and add in the lowest valid
896 * physical page address to get the true physical address.
897 */
898 ramdisk_image -= KERNBASE;
899 ramdisk_image += phys_base;
900
901 numadbg("Found ramdisk at physical address 0x%lx, size %u\n",
902 ramdisk_image, sparc_ramdisk_size);
903
904 initrd_start = ramdisk_image;
905 initrd_end = ramdisk_image + sparc_ramdisk_size;
906
907 memblock_reserve(initrd_start, sparc_ramdisk_size);
908
909 initrd_start += PAGE_OFFSET;
910 initrd_end += PAGE_OFFSET;
911 }
912#endif
913}
914
915struct node_mem_mask {
916 unsigned long mask;
917 unsigned long match;
918};
919static struct node_mem_mask node_masks[MAX_NUMNODES];
920static int num_node_masks;
921
922#ifdef CONFIG_NUMA
923
924struct mdesc_mlgroup {
925 u64 node;
926 u64 latency;
927 u64 match;
928 u64 mask;
929};
930
931static struct mdesc_mlgroup *mlgroups;
932static int num_mlgroups;
933
934int numa_cpu_lookup_table[NR_CPUS];
935cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES];
936
937struct mdesc_mblock {
938 u64 base;
939 u64 size;
940 u64 offset; /* RA-to-PA */
941};
942static struct mdesc_mblock *mblocks;
943static int num_mblocks;
944
945static struct mdesc_mblock * __init addr_to_mblock(unsigned long addr)
946{
947 struct mdesc_mblock *m = NULL;
948 int i;
949
950 for (i = 0; i < num_mblocks; i++) {
951 m = &mblocks[i];
952
953 if (addr >= m->base &&
954 addr < (m->base + m->size)) {
955 break;
956 }
957 }
958
959 return m;
960}
961
962static u64 __init memblock_nid_range_sun4u(u64 start, u64 end, int *nid)
963{
964 int prev_nid, new_nid;
965
966 prev_nid = NUMA_NO_NODE;
967 for ( ; start < end; start += PAGE_SIZE) {
968 for (new_nid = 0; new_nid < num_node_masks; new_nid++) {
969 struct node_mem_mask *p = &node_masks[new_nid];
970
971 if ((start & p->mask) == p->match) {
972 if (prev_nid == NUMA_NO_NODE)
973 prev_nid = new_nid;
974 break;
975 }
976 }
977
978 if (new_nid == num_node_masks) {
979 prev_nid = 0;
980 WARN_ONCE(1, "addr[%Lx] doesn't match a NUMA node rule. Some memory will be owned by node 0.",
981 start);
982 break;
983 }
984
985 if (prev_nid != new_nid)
986 break;
987 }
988 *nid = prev_nid;
989
990 return start > end ? end : start;
991}
992
993static u64 __init memblock_nid_range(u64 start, u64 end, int *nid)
994{
995 u64 ret_end, pa_start, m_mask, m_match, m_end;
996 struct mdesc_mblock *mblock;
997 int _nid, i;
998
999 if (tlb_type != hypervisor)
1000 return memblock_nid_range_sun4u(start, end, nid);
1001
1002 mblock = addr_to_mblock(start);
1003 if (!mblock) {
1004 WARN_ONCE(1, "memblock_nid_range: Can't find mblock addr[%Lx]",
1005 start);
1006
1007 _nid = 0;
1008 ret_end = end;
1009 goto done;
1010 }
1011
1012 pa_start = start + mblock->offset;
1013 m_match = 0;
1014 m_mask = 0;
1015
1016 for (_nid = 0; _nid < num_node_masks; _nid++) {
1017 struct node_mem_mask *const m = &node_masks[_nid];
1018
1019 if ((pa_start & m->mask) == m->match) {
1020 m_match = m->match;
1021 m_mask = m->mask;
1022 break;
1023 }
1024 }
1025
1026 if (num_node_masks == _nid) {
1027 /* We could not find NUMA group, so default to 0, but lets
1028 * search for latency group, so we could calculate the correct
1029 * end address that we return
1030 */
1031 _nid = 0;
1032
1033 for (i = 0; i < num_mlgroups; i++) {
1034 struct mdesc_mlgroup *const m = &mlgroups[i];
1035
1036 if ((pa_start & m->mask) == m->match) {
1037 m_match = m->match;
1038 m_mask = m->mask;
1039 break;
1040 }
1041 }
1042
1043 if (i == num_mlgroups) {
1044 WARN_ONCE(1, "memblock_nid_range: Can't find latency group addr[%Lx]",
1045 start);
1046
1047 ret_end = end;
1048 goto done;
1049 }
1050 }
1051
1052 /*
1053 * Each latency group has match and mask, and each memory block has an
1054 * offset. An address belongs to a latency group if its address matches
1055 * the following formula: ((addr + offset) & mask) == match
1056 * It is, however, slow to check every single page if it matches a
1057 * particular latency group. As optimization we calculate end value by
1058 * using bit arithmetics.
1059 */
1060 m_end = m_match + (1ul << __ffs(m_mask)) - mblock->offset;
1061 m_end += pa_start & ~((1ul << fls64(m_mask)) - 1);
1062 ret_end = m_end > end ? end : m_end;
1063
1064done:
1065 *nid = _nid;
1066 return ret_end;
1067}
1068#endif
1069
1070/* This must be invoked after performing all of the necessary
1071 * memblock_set_node() calls for 'nid'. We need to be able to get
1072 * correct data from get_pfn_range_for_nid().
1073 */
1074static void __init allocate_node_data(int nid)
1075{
1076 struct pglist_data *p;
1077 unsigned long start_pfn, end_pfn;
1078#ifdef CONFIG_NUMA
1079
1080 NODE_DATA(nid) = memblock_alloc_node(sizeof(struct pglist_data),
1081 SMP_CACHE_BYTES, nid);
1082 if (!NODE_DATA(nid)) {
1083 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid);
1084 prom_halt();
1085 }
1086
1087 NODE_DATA(nid)->node_id = nid;
1088#endif
1089
1090 p = NODE_DATA(nid);
1091
1092 get_pfn_range_for_nid(nid, &start_pfn, &end_pfn);
1093 p->node_start_pfn = start_pfn;
1094 p->node_spanned_pages = end_pfn - start_pfn;
1095}
1096
1097static void init_node_masks_nonnuma(void)
1098{
1099#ifdef CONFIG_NUMA
1100 int i;
1101#endif
1102
1103 numadbg("Initializing tables for non-numa.\n");
1104
1105 node_masks[0].mask = 0;
1106 node_masks[0].match = 0;
1107 num_node_masks = 1;
1108
1109#ifdef CONFIG_NUMA
1110 for (i = 0; i < NR_CPUS; i++)
1111 numa_cpu_lookup_table[i] = 0;
1112
1113 cpumask_setall(&numa_cpumask_lookup_table[0]);
1114#endif
1115}
1116
1117#ifdef CONFIG_NUMA
1118struct pglist_data *node_data[MAX_NUMNODES];
1119
1120EXPORT_SYMBOL(numa_cpu_lookup_table);
1121EXPORT_SYMBOL(numa_cpumask_lookup_table);
1122EXPORT_SYMBOL(node_data);
1123
1124static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio,
1125 u32 cfg_handle)
1126{
1127 u64 arc;
1128
1129 mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) {
1130 u64 target = mdesc_arc_target(md, arc);
1131 const u64 *val;
1132
1133 val = mdesc_get_property(md, target,
1134 "cfg-handle", NULL);
1135 if (val && *val == cfg_handle)
1136 return 0;
1137 }
1138 return -ENODEV;
1139}
1140
1141static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp,
1142 u32 cfg_handle)
1143{
1144 u64 arc, candidate, best_latency = ~(u64)0;
1145
1146 candidate = MDESC_NODE_NULL;
1147 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1148 u64 target = mdesc_arc_target(md, arc);
1149 const char *name = mdesc_node_name(md, target);
1150 const u64 *val;
1151
1152 if (strcmp(name, "pio-latency-group"))
1153 continue;
1154
1155 val = mdesc_get_property(md, target, "latency", NULL);
1156 if (!val)
1157 continue;
1158
1159 if (*val < best_latency) {
1160 candidate = target;
1161 best_latency = *val;
1162 }
1163 }
1164
1165 if (candidate == MDESC_NODE_NULL)
1166 return -ENODEV;
1167
1168 return scan_pio_for_cfg_handle(md, candidate, cfg_handle);
1169}
1170
1171int of_node_to_nid(struct device_node *dp)
1172{
1173 const struct linux_prom64_registers *regs;
1174 struct mdesc_handle *md;
1175 u32 cfg_handle;
1176 int count, nid;
1177 u64 grp;
1178
1179 /* This is the right thing to do on currently supported
1180 * SUN4U NUMA platforms as well, as the PCI controller does
1181 * not sit behind any particular memory controller.
1182 */
1183 if (!mlgroups)
1184 return -1;
1185
1186 regs = of_get_property(dp, "reg", NULL);
1187 if (!regs)
1188 return -1;
1189
1190 cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff;
1191
1192 md = mdesc_grab();
1193
1194 count = 0;
1195 nid = NUMA_NO_NODE;
1196 mdesc_for_each_node_by_name(md, grp, "group") {
1197 if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) {
1198 nid = count;
1199 break;
1200 }
1201 count++;
1202 }
1203
1204 mdesc_release(md);
1205
1206 return nid;
1207}
1208
1209static void __init add_node_ranges(void)
1210{
1211 phys_addr_t start, end;
1212 unsigned long prev_max;
1213 u64 i;
1214
1215memblock_resized:
1216 prev_max = memblock.memory.max;
1217
1218 for_each_mem_range(i, &start, &end) {
1219 while (start < end) {
1220 unsigned long this_end;
1221 int nid;
1222
1223 this_end = memblock_nid_range(start, end, &nid);
1224
1225 numadbg("Setting memblock NUMA node nid[%d] "
1226 "start[%llx] end[%lx]\n",
1227 nid, start, this_end);
1228
1229 memblock_set_node(start, this_end - start,
1230 &memblock.memory, nid);
1231 if (memblock.memory.max != prev_max)
1232 goto memblock_resized;
1233 start = this_end;
1234 }
1235 }
1236}
1237
1238static int __init grab_mlgroups(struct mdesc_handle *md)
1239{
1240 unsigned long paddr;
1241 int count = 0;
1242 u64 node;
1243
1244 mdesc_for_each_node_by_name(md, node, "memory-latency-group")
1245 count++;
1246 if (!count)
1247 return -ENOENT;
1248
1249 paddr = memblock_phys_alloc(count * sizeof(struct mdesc_mlgroup),
1250 SMP_CACHE_BYTES);
1251 if (!paddr)
1252 return -ENOMEM;
1253
1254 mlgroups = __va(paddr);
1255 num_mlgroups = count;
1256
1257 count = 0;
1258 mdesc_for_each_node_by_name(md, node, "memory-latency-group") {
1259 struct mdesc_mlgroup *m = &mlgroups[count++];
1260 const u64 *val;
1261
1262 m->node = node;
1263
1264 val = mdesc_get_property(md, node, "latency", NULL);
1265 m->latency = *val;
1266 val = mdesc_get_property(md, node, "address-match", NULL);
1267 m->match = *val;
1268 val = mdesc_get_property(md, node, "address-mask", NULL);
1269 m->mask = *val;
1270
1271 numadbg("MLGROUP[%d]: node[%llx] latency[%llx] "
1272 "match[%llx] mask[%llx]\n",
1273 count - 1, m->node, m->latency, m->match, m->mask);
1274 }
1275
1276 return 0;
1277}
1278
1279static int __init grab_mblocks(struct mdesc_handle *md)
1280{
1281 unsigned long paddr;
1282 int count = 0;
1283 u64 node;
1284
1285 mdesc_for_each_node_by_name(md, node, "mblock")
1286 count++;
1287 if (!count)
1288 return -ENOENT;
1289
1290 paddr = memblock_phys_alloc(count * sizeof(struct mdesc_mblock),
1291 SMP_CACHE_BYTES);
1292 if (!paddr)
1293 return -ENOMEM;
1294
1295 mblocks = __va(paddr);
1296 num_mblocks = count;
1297
1298 count = 0;
1299 mdesc_for_each_node_by_name(md, node, "mblock") {
1300 struct mdesc_mblock *m = &mblocks[count++];
1301 const u64 *val;
1302
1303 val = mdesc_get_property(md, node, "base", NULL);
1304 m->base = *val;
1305 val = mdesc_get_property(md, node, "size", NULL);
1306 m->size = *val;
1307 val = mdesc_get_property(md, node,
1308 "address-congruence-offset", NULL);
1309
1310 /* The address-congruence-offset property is optional.
1311 * Explicity zero it be identifty this.
1312 */
1313 if (val)
1314 m->offset = *val;
1315 else
1316 m->offset = 0UL;
1317
1318 numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n",
1319 count - 1, m->base, m->size, m->offset);
1320 }
1321
1322 return 0;
1323}
1324
1325static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md,
1326 u64 grp, cpumask_t *mask)
1327{
1328 u64 arc;
1329
1330 cpumask_clear(mask);
1331
1332 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) {
1333 u64 target = mdesc_arc_target(md, arc);
1334 const char *name = mdesc_node_name(md, target);
1335 const u64 *id;
1336
1337 if (strcmp(name, "cpu"))
1338 continue;
1339 id = mdesc_get_property(md, target, "id", NULL);
1340 if (*id < nr_cpu_ids)
1341 cpumask_set_cpu(*id, mask);
1342 }
1343}
1344
1345static struct mdesc_mlgroup * __init find_mlgroup(u64 node)
1346{
1347 int i;
1348
1349 for (i = 0; i < num_mlgroups; i++) {
1350 struct mdesc_mlgroup *m = &mlgroups[i];
1351 if (m->node == node)
1352 return m;
1353 }
1354 return NULL;
1355}
1356
1357int __node_distance(int from, int to)
1358{
1359 if ((from >= MAX_NUMNODES) || (to >= MAX_NUMNODES)) {
1360 pr_warn("Returning default NUMA distance value for %d->%d\n",
1361 from, to);
1362 return (from == to) ? LOCAL_DISTANCE : REMOTE_DISTANCE;
1363 }
1364 return numa_latency[from][to];
1365}
1366EXPORT_SYMBOL(__node_distance);
1367
1368static int __init find_best_numa_node_for_mlgroup(struct mdesc_mlgroup *grp)
1369{
1370 int i;
1371
1372 for (i = 0; i < MAX_NUMNODES; i++) {
1373 struct node_mem_mask *n = &node_masks[i];
1374
1375 if ((grp->mask == n->mask) && (grp->match == n->match))
1376 break;
1377 }
1378 return i;
1379}
1380
1381static void __init find_numa_latencies_for_group(struct mdesc_handle *md,
1382 u64 grp, int index)
1383{
1384 u64 arc;
1385
1386 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1387 int tnode;
1388 u64 target = mdesc_arc_target(md, arc);
1389 struct mdesc_mlgroup *m = find_mlgroup(target);
1390
1391 if (!m)
1392 continue;
1393 tnode = find_best_numa_node_for_mlgroup(m);
1394 if (tnode == MAX_NUMNODES)
1395 continue;
1396 numa_latency[index][tnode] = m->latency;
1397 }
1398}
1399
1400static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp,
1401 int index)
1402{
1403 struct mdesc_mlgroup *candidate = NULL;
1404 u64 arc, best_latency = ~(u64)0;
1405 struct node_mem_mask *n;
1406
1407 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1408 u64 target = mdesc_arc_target(md, arc);
1409 struct mdesc_mlgroup *m = find_mlgroup(target);
1410 if (!m)
1411 continue;
1412 if (m->latency < best_latency) {
1413 candidate = m;
1414 best_latency = m->latency;
1415 }
1416 }
1417 if (!candidate)
1418 return -ENOENT;
1419
1420 if (num_node_masks != index) {
1421 printk(KERN_ERR "Inconsistent NUMA state, "
1422 "index[%d] != num_node_masks[%d]\n",
1423 index, num_node_masks);
1424 return -EINVAL;
1425 }
1426
1427 n = &node_masks[num_node_masks++];
1428
1429 n->mask = candidate->mask;
1430 n->match = candidate->match;
1431
1432 numadbg("NUMA NODE[%d]: mask[%lx] match[%lx] (latency[%llx])\n",
1433 index, n->mask, n->match, candidate->latency);
1434
1435 return 0;
1436}
1437
1438static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp,
1439 int index)
1440{
1441 cpumask_t mask;
1442 int cpu;
1443
1444 numa_parse_mdesc_group_cpus(md, grp, &mask);
1445
1446 for_each_cpu(cpu, &mask)
1447 numa_cpu_lookup_table[cpu] = index;
1448 cpumask_copy(&numa_cpumask_lookup_table[index], &mask);
1449
1450 if (numa_debug) {
1451 printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index);
1452 for_each_cpu(cpu, &mask)
1453 printk("%d ", cpu);
1454 printk("]\n");
1455 }
1456
1457 return numa_attach_mlgroup(md, grp, index);
1458}
1459
1460static int __init numa_parse_mdesc(void)
1461{
1462 struct mdesc_handle *md = mdesc_grab();
1463 int i, j, err, count;
1464 u64 node;
1465
1466 node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups");
1467 if (node == MDESC_NODE_NULL) {
1468 mdesc_release(md);
1469 return -ENOENT;
1470 }
1471
1472 err = grab_mblocks(md);
1473 if (err < 0)
1474 goto out;
1475
1476 err = grab_mlgroups(md);
1477 if (err < 0)
1478 goto out;
1479
1480 count = 0;
1481 mdesc_for_each_node_by_name(md, node, "group") {
1482 err = numa_parse_mdesc_group(md, node, count);
1483 if (err < 0)
1484 break;
1485 count++;
1486 }
1487
1488 count = 0;
1489 mdesc_for_each_node_by_name(md, node, "group") {
1490 find_numa_latencies_for_group(md, node, count);
1491 count++;
1492 }
1493
1494 /* Normalize numa latency matrix according to ACPI SLIT spec. */
1495 for (i = 0; i < MAX_NUMNODES; i++) {
1496 u64 self_latency = numa_latency[i][i];
1497
1498 for (j = 0; j < MAX_NUMNODES; j++) {
1499 numa_latency[i][j] =
1500 (numa_latency[i][j] * LOCAL_DISTANCE) /
1501 self_latency;
1502 }
1503 }
1504
1505 add_node_ranges();
1506
1507 for (i = 0; i < num_node_masks; i++) {
1508 allocate_node_data(i);
1509 node_set_online(i);
1510 }
1511
1512 err = 0;
1513out:
1514 mdesc_release(md);
1515 return err;
1516}
1517
1518static int __init numa_parse_jbus(void)
1519{
1520 unsigned long cpu, index;
1521
1522 /* NUMA node id is encoded in bits 36 and higher, and there is
1523 * a 1-to-1 mapping from CPU ID to NUMA node ID.
1524 */
1525 index = 0;
1526 for_each_present_cpu(cpu) {
1527 numa_cpu_lookup_table[cpu] = index;
1528 cpumask_copy(&numa_cpumask_lookup_table[index], cpumask_of(cpu));
1529 node_masks[index].mask = ~((1UL << 36UL) - 1UL);
1530 node_masks[index].match = cpu << 36UL;
1531
1532 index++;
1533 }
1534 num_node_masks = index;
1535
1536 add_node_ranges();
1537
1538 for (index = 0; index < num_node_masks; index++) {
1539 allocate_node_data(index);
1540 node_set_online(index);
1541 }
1542
1543 return 0;
1544}
1545
1546static int __init numa_parse_sun4u(void)
1547{
1548 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1549 unsigned long ver;
1550
1551 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
1552 if ((ver >> 32UL) == __JALAPENO_ID ||
1553 (ver >> 32UL) == __SERRANO_ID)
1554 return numa_parse_jbus();
1555 }
1556 return -1;
1557}
1558
1559static int __init bootmem_init_numa(void)
1560{
1561 int i, j;
1562 int err = -1;
1563
1564 numadbg("bootmem_init_numa()\n");
1565
1566 /* Some sane defaults for numa latency values */
1567 for (i = 0; i < MAX_NUMNODES; i++) {
1568 for (j = 0; j < MAX_NUMNODES; j++)
1569 numa_latency[i][j] = (i == j) ?
1570 LOCAL_DISTANCE : REMOTE_DISTANCE;
1571 }
1572
1573 if (numa_enabled) {
1574 if (tlb_type == hypervisor)
1575 err = numa_parse_mdesc();
1576 else
1577 err = numa_parse_sun4u();
1578 }
1579 return err;
1580}
1581
1582#else
1583
1584static int bootmem_init_numa(void)
1585{
1586 return -1;
1587}
1588
1589#endif
1590
1591static void __init bootmem_init_nonnuma(void)
1592{
1593 unsigned long top_of_ram = memblock_end_of_DRAM();
1594 unsigned long total_ram = memblock_phys_mem_size();
1595
1596 numadbg("bootmem_init_nonnuma()\n");
1597
1598 printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
1599 top_of_ram, total_ram);
1600 printk(KERN_INFO "Memory hole size: %ldMB\n",
1601 (top_of_ram - total_ram) >> 20);
1602
1603 init_node_masks_nonnuma();
1604 memblock_set_node(0, PHYS_ADDR_MAX, &memblock.memory, 0);
1605 allocate_node_data(0);
1606 node_set_online(0);
1607}
1608
1609static unsigned long __init bootmem_init(unsigned long phys_base)
1610{
1611 unsigned long end_pfn;
1612
1613 end_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT;
1614 max_pfn = max_low_pfn = end_pfn;
1615 min_low_pfn = (phys_base >> PAGE_SHIFT);
1616
1617 if (bootmem_init_numa() < 0)
1618 bootmem_init_nonnuma();
1619
1620 /* Dump memblock with node info. */
1621 memblock_dump_all();
1622
1623 /* XXX cpu notifier XXX */
1624
1625 sparse_init();
1626
1627 return end_pfn;
1628}
1629
1630static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1631static int pall_ents __initdata;
1632
1633static unsigned long max_phys_bits = 40;
1634
1635bool kern_addr_valid(unsigned long addr)
1636{
1637 pgd_t *pgd;
1638 p4d_t *p4d;
1639 pud_t *pud;
1640 pmd_t *pmd;
1641 pte_t *pte;
1642
1643 if ((long)addr < 0L) {
1644 unsigned long pa = __pa(addr);
1645
1646 if ((pa >> max_phys_bits) != 0UL)
1647 return false;
1648
1649 return pfn_valid(pa >> PAGE_SHIFT);
1650 }
1651
1652 if (addr >= (unsigned long) KERNBASE &&
1653 addr < (unsigned long)&_end)
1654 return true;
1655
1656 pgd = pgd_offset_k(addr);
1657 if (pgd_none(*pgd))
1658 return false;
1659
1660 p4d = p4d_offset(pgd, addr);
1661 if (p4d_none(*p4d))
1662 return false;
1663
1664 pud = pud_offset(p4d, addr);
1665 if (pud_none(*pud))
1666 return false;
1667
1668 if (pud_leaf(*pud))
1669 return pfn_valid(pud_pfn(*pud));
1670
1671 pmd = pmd_offset(pud, addr);
1672 if (pmd_none(*pmd))
1673 return false;
1674
1675 if (pmd_leaf(*pmd))
1676 return pfn_valid(pmd_pfn(*pmd));
1677
1678 pte = pte_offset_kernel(pmd, addr);
1679 if (pte_none(*pte))
1680 return false;
1681
1682 return pfn_valid(pte_pfn(*pte));
1683}
1684
1685static unsigned long __ref kernel_map_hugepud(unsigned long vstart,
1686 unsigned long vend,
1687 pud_t *pud)
1688{
1689 const unsigned long mask16gb = (1UL << 34) - 1UL;
1690 u64 pte_val = vstart;
1691
1692 /* Each PUD is 8GB */
1693 if ((vstart & mask16gb) ||
1694 (vend - vstart <= mask16gb)) {
1695 pte_val ^= kern_linear_pte_xor[2];
1696 pud_val(*pud) = pte_val | _PAGE_PUD_HUGE;
1697
1698 return vstart + PUD_SIZE;
1699 }
1700
1701 pte_val ^= kern_linear_pte_xor[3];
1702 pte_val |= _PAGE_PUD_HUGE;
1703
1704 vend = vstart + mask16gb + 1UL;
1705 while (vstart < vend) {
1706 pud_val(*pud) = pte_val;
1707
1708 pte_val += PUD_SIZE;
1709 vstart += PUD_SIZE;
1710 pud++;
1711 }
1712 return vstart;
1713}
1714
1715static bool kernel_can_map_hugepud(unsigned long vstart, unsigned long vend,
1716 bool guard)
1717{
1718 if (guard && !(vstart & ~PUD_MASK) && (vend - vstart) >= PUD_SIZE)
1719 return true;
1720
1721 return false;
1722}
1723
1724static unsigned long __ref kernel_map_hugepmd(unsigned long vstart,
1725 unsigned long vend,
1726 pmd_t *pmd)
1727{
1728 const unsigned long mask256mb = (1UL << 28) - 1UL;
1729 const unsigned long mask2gb = (1UL << 31) - 1UL;
1730 u64 pte_val = vstart;
1731
1732 /* Each PMD is 8MB */
1733 if ((vstart & mask256mb) ||
1734 (vend - vstart <= mask256mb)) {
1735 pte_val ^= kern_linear_pte_xor[0];
1736 pmd_val(*pmd) = pte_val | _PAGE_PMD_HUGE;
1737
1738 return vstart + PMD_SIZE;
1739 }
1740
1741 if ((vstart & mask2gb) ||
1742 (vend - vstart <= mask2gb)) {
1743 pte_val ^= kern_linear_pte_xor[1];
1744 pte_val |= _PAGE_PMD_HUGE;
1745 vend = vstart + mask256mb + 1UL;
1746 } else {
1747 pte_val ^= kern_linear_pte_xor[2];
1748 pte_val |= _PAGE_PMD_HUGE;
1749 vend = vstart + mask2gb + 1UL;
1750 }
1751
1752 while (vstart < vend) {
1753 pmd_val(*pmd) = pte_val;
1754
1755 pte_val += PMD_SIZE;
1756 vstart += PMD_SIZE;
1757 pmd++;
1758 }
1759
1760 return vstart;
1761}
1762
1763static bool kernel_can_map_hugepmd(unsigned long vstart, unsigned long vend,
1764 bool guard)
1765{
1766 if (guard && !(vstart & ~PMD_MASK) && (vend - vstart) >= PMD_SIZE)
1767 return true;
1768
1769 return false;
1770}
1771
1772static unsigned long __ref kernel_map_range(unsigned long pstart,
1773 unsigned long pend, pgprot_t prot,
1774 bool use_huge)
1775{
1776 unsigned long vstart = PAGE_OFFSET + pstart;
1777 unsigned long vend = PAGE_OFFSET + pend;
1778 unsigned long alloc_bytes = 0UL;
1779
1780 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1781 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1782 vstart, vend);
1783 prom_halt();
1784 }
1785
1786 while (vstart < vend) {
1787 unsigned long this_end, paddr = __pa(vstart);
1788 pgd_t *pgd = pgd_offset_k(vstart);
1789 p4d_t *p4d;
1790 pud_t *pud;
1791 pmd_t *pmd;
1792 pte_t *pte;
1793
1794 if (pgd_none(*pgd)) {
1795 pud_t *new;
1796
1797 new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE,
1798 PAGE_SIZE);
1799 if (!new)
1800 goto err_alloc;
1801 alloc_bytes += PAGE_SIZE;
1802 pgd_populate(&init_mm, pgd, new);
1803 }
1804
1805 p4d = p4d_offset(pgd, vstart);
1806 if (p4d_none(*p4d)) {
1807 pud_t *new;
1808
1809 new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE,
1810 PAGE_SIZE);
1811 if (!new)
1812 goto err_alloc;
1813 alloc_bytes += PAGE_SIZE;
1814 p4d_populate(&init_mm, p4d, new);
1815 }
1816
1817 pud = pud_offset(p4d, vstart);
1818 if (pud_none(*pud)) {
1819 pmd_t *new;
1820
1821 if (kernel_can_map_hugepud(vstart, vend, use_huge)) {
1822 vstart = kernel_map_hugepud(vstart, vend, pud);
1823 continue;
1824 }
1825 new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE,
1826 PAGE_SIZE);
1827 if (!new)
1828 goto err_alloc;
1829 alloc_bytes += PAGE_SIZE;
1830 pud_populate(&init_mm, pud, new);
1831 }
1832
1833 pmd = pmd_offset(pud, vstart);
1834 if (pmd_none(*pmd)) {
1835 pte_t *new;
1836
1837 if (kernel_can_map_hugepmd(vstart, vend, use_huge)) {
1838 vstart = kernel_map_hugepmd(vstart, vend, pmd);
1839 continue;
1840 }
1841 new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE,
1842 PAGE_SIZE);
1843 if (!new)
1844 goto err_alloc;
1845 alloc_bytes += PAGE_SIZE;
1846 pmd_populate_kernel(&init_mm, pmd, new);
1847 }
1848
1849 pte = pte_offset_kernel(pmd, vstart);
1850 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1851 if (this_end > vend)
1852 this_end = vend;
1853
1854 while (vstart < this_end) {
1855 pte_val(*pte) = (paddr | pgprot_val(prot));
1856
1857 vstart += PAGE_SIZE;
1858 paddr += PAGE_SIZE;
1859 pte++;
1860 }
1861 }
1862
1863 return alloc_bytes;
1864
1865err_alloc:
1866 panic("%s: Failed to allocate %lu bytes align=%lx from=%lx\n",
1867 __func__, PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1868 return -ENOMEM;
1869}
1870
1871static void __init flush_all_kernel_tsbs(void)
1872{
1873 int i;
1874
1875 for (i = 0; i < KERNEL_TSB_NENTRIES; i++) {
1876 struct tsb *ent = &swapper_tsb[i];
1877
1878 ent->tag = (1UL << TSB_TAG_INVALID_BIT);
1879 }
1880#ifndef CONFIG_DEBUG_PAGEALLOC
1881 for (i = 0; i < KERNEL_TSB4M_NENTRIES; i++) {
1882 struct tsb *ent = &swapper_4m_tsb[i];
1883
1884 ent->tag = (1UL << TSB_TAG_INVALID_BIT);
1885 }
1886#endif
1887}
1888
1889extern unsigned int kvmap_linear_patch[1];
1890
1891static void __init kernel_physical_mapping_init(void)
1892{
1893 unsigned long i, mem_alloced = 0UL;
1894 bool use_huge = true;
1895
1896#ifdef CONFIG_DEBUG_PAGEALLOC
1897 use_huge = false;
1898#endif
1899 for (i = 0; i < pall_ents; i++) {
1900 unsigned long phys_start, phys_end;
1901
1902 phys_start = pall[i].phys_addr;
1903 phys_end = phys_start + pall[i].reg_size;
1904
1905 mem_alloced += kernel_map_range(phys_start, phys_end,
1906 PAGE_KERNEL, use_huge);
1907 }
1908
1909 printk("Allocated %ld bytes for kernel page tables.\n",
1910 mem_alloced);
1911
1912 kvmap_linear_patch[0] = 0x01000000; /* nop */
1913 flushi(&kvmap_linear_patch[0]);
1914
1915 flush_all_kernel_tsbs();
1916
1917 __flush_tlb_all();
1918}
1919
1920#ifdef CONFIG_DEBUG_PAGEALLOC
1921void __kernel_map_pages(struct page *page, int numpages, int enable)
1922{
1923 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1924 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1925
1926 kernel_map_range(phys_start, phys_end,
1927 (enable ? PAGE_KERNEL : __pgprot(0)), false);
1928
1929 flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1930 PAGE_OFFSET + phys_end);
1931
1932 /* we should perform an IPI and flush all tlbs,
1933 * but that can deadlock->flush only current cpu.
1934 */
1935 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1936 PAGE_OFFSET + phys_end);
1937}
1938#endif
1939
1940unsigned long __init find_ecache_flush_span(unsigned long size)
1941{
1942 int i;
1943
1944 for (i = 0; i < pavail_ents; i++) {
1945 if (pavail[i].reg_size >= size)
1946 return pavail[i].phys_addr;
1947 }
1948
1949 return ~0UL;
1950}
1951
1952unsigned long PAGE_OFFSET;
1953EXPORT_SYMBOL(PAGE_OFFSET);
1954
1955unsigned long VMALLOC_END = 0x0000010000000000UL;
1956EXPORT_SYMBOL(VMALLOC_END);
1957
1958unsigned long sparc64_va_hole_top = 0xfffff80000000000UL;
1959unsigned long sparc64_va_hole_bottom = 0x0000080000000000UL;
1960
1961static void __init setup_page_offset(void)
1962{
1963 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1964 /* Cheetah/Panther support a full 64-bit virtual
1965 * address, so we can use all that our page tables
1966 * support.
1967 */
1968 sparc64_va_hole_top = 0xfff0000000000000UL;
1969 sparc64_va_hole_bottom = 0x0010000000000000UL;
1970
1971 max_phys_bits = 42;
1972 } else if (tlb_type == hypervisor) {
1973 switch (sun4v_chip_type) {
1974 case SUN4V_CHIP_NIAGARA1:
1975 case SUN4V_CHIP_NIAGARA2:
1976 /* T1 and T2 support 48-bit virtual addresses. */
1977 sparc64_va_hole_top = 0xffff800000000000UL;
1978 sparc64_va_hole_bottom = 0x0000800000000000UL;
1979
1980 max_phys_bits = 39;
1981 break;
1982 case SUN4V_CHIP_NIAGARA3:
1983 /* T3 supports 48-bit virtual addresses. */
1984 sparc64_va_hole_top = 0xffff800000000000UL;
1985 sparc64_va_hole_bottom = 0x0000800000000000UL;
1986
1987 max_phys_bits = 43;
1988 break;
1989 case SUN4V_CHIP_NIAGARA4:
1990 case SUN4V_CHIP_NIAGARA5:
1991 case SUN4V_CHIP_SPARC64X:
1992 case SUN4V_CHIP_SPARC_M6:
1993 /* T4 and later support 52-bit virtual addresses. */
1994 sparc64_va_hole_top = 0xfff8000000000000UL;
1995 sparc64_va_hole_bottom = 0x0008000000000000UL;
1996 max_phys_bits = 47;
1997 break;
1998 case SUN4V_CHIP_SPARC_M7:
1999 case SUN4V_CHIP_SPARC_SN:
2000 /* M7 and later support 52-bit virtual addresses. */
2001 sparc64_va_hole_top = 0xfff8000000000000UL;
2002 sparc64_va_hole_bottom = 0x0008000000000000UL;
2003 max_phys_bits = 49;
2004 break;
2005 case SUN4V_CHIP_SPARC_M8:
2006 default:
2007 /* M8 and later support 54-bit virtual addresses.
2008 * However, restricting M8 and above VA bits to 53
2009 * as 4-level page table cannot support more than
2010 * 53 VA bits.
2011 */
2012 sparc64_va_hole_top = 0xfff0000000000000UL;
2013 sparc64_va_hole_bottom = 0x0010000000000000UL;
2014 max_phys_bits = 51;
2015 break;
2016 }
2017 }
2018
2019 if (max_phys_bits > MAX_PHYS_ADDRESS_BITS) {
2020 prom_printf("MAX_PHYS_ADDRESS_BITS is too small, need %lu\n",
2021 max_phys_bits);
2022 prom_halt();
2023 }
2024
2025 PAGE_OFFSET = sparc64_va_hole_top;
2026 VMALLOC_END = ((sparc64_va_hole_bottom >> 1) +
2027 (sparc64_va_hole_bottom >> 2));
2028
2029 pr_info("MM: PAGE_OFFSET is 0x%016lx (max_phys_bits == %lu)\n",
2030 PAGE_OFFSET, max_phys_bits);
2031 pr_info("MM: VMALLOC [0x%016lx --> 0x%016lx]\n",
2032 VMALLOC_START, VMALLOC_END);
2033 pr_info("MM: VMEMMAP [0x%016lx --> 0x%016lx]\n",
2034 VMEMMAP_BASE, VMEMMAP_BASE << 1);
2035}
2036
2037static void __init tsb_phys_patch(void)
2038{
2039 struct tsb_ldquad_phys_patch_entry *pquad;
2040 struct tsb_phys_patch_entry *p;
2041
2042 pquad = &__tsb_ldquad_phys_patch;
2043 while (pquad < &__tsb_ldquad_phys_patch_end) {
2044 unsigned long addr = pquad->addr;
2045
2046 if (tlb_type == hypervisor)
2047 *(unsigned int *) addr = pquad->sun4v_insn;
2048 else
2049 *(unsigned int *) addr = pquad->sun4u_insn;
2050 wmb();
2051 __asm__ __volatile__("flush %0"
2052 : /* no outputs */
2053 : "r" (addr));
2054
2055 pquad++;
2056 }
2057
2058 p = &__tsb_phys_patch;
2059 while (p < &__tsb_phys_patch_end) {
2060 unsigned long addr = p->addr;
2061
2062 *(unsigned int *) addr = p->insn;
2063 wmb();
2064 __asm__ __volatile__("flush %0"
2065 : /* no outputs */
2066 : "r" (addr));
2067
2068 p++;
2069 }
2070}
2071
2072/* Don't mark as init, we give this to the Hypervisor. */
2073#ifndef CONFIG_DEBUG_PAGEALLOC
2074#define NUM_KTSB_DESCR 2
2075#else
2076#define NUM_KTSB_DESCR 1
2077#endif
2078static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
2079
2080/* The swapper TSBs are loaded with a base sequence of:
2081 *
2082 * sethi %uhi(SYMBOL), REG1
2083 * sethi %hi(SYMBOL), REG2
2084 * or REG1, %ulo(SYMBOL), REG1
2085 * or REG2, %lo(SYMBOL), REG2
2086 * sllx REG1, 32, REG1
2087 * or REG1, REG2, REG1
2088 *
2089 * When we use physical addressing for the TSB accesses, we patch the
2090 * first four instructions in the above sequence.
2091 */
2092
2093static void patch_one_ktsb_phys(unsigned int *start, unsigned int *end, unsigned long pa)
2094{
2095 unsigned long high_bits, low_bits;
2096
2097 high_bits = (pa >> 32) & 0xffffffff;
2098 low_bits = (pa >> 0) & 0xffffffff;
2099
2100 while (start < end) {
2101 unsigned int *ia = (unsigned int *)(unsigned long)*start;
2102
2103 ia[0] = (ia[0] & ~0x3fffff) | (high_bits >> 10);
2104 __asm__ __volatile__("flush %0" : : "r" (ia));
2105
2106 ia[1] = (ia[1] & ~0x3fffff) | (low_bits >> 10);
2107 __asm__ __volatile__("flush %0" : : "r" (ia + 1));
2108
2109 ia[2] = (ia[2] & ~0x1fff) | (high_bits & 0x3ff);
2110 __asm__ __volatile__("flush %0" : : "r" (ia + 2));
2111
2112 ia[3] = (ia[3] & ~0x1fff) | (low_bits & 0x3ff);
2113 __asm__ __volatile__("flush %0" : : "r" (ia + 3));
2114
2115 start++;
2116 }
2117}
2118
2119static void ktsb_phys_patch(void)
2120{
2121 extern unsigned int __swapper_tsb_phys_patch;
2122 extern unsigned int __swapper_tsb_phys_patch_end;
2123 unsigned long ktsb_pa;
2124
2125 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
2126 patch_one_ktsb_phys(&__swapper_tsb_phys_patch,
2127 &__swapper_tsb_phys_patch_end, ktsb_pa);
2128#ifndef CONFIG_DEBUG_PAGEALLOC
2129 {
2130 extern unsigned int __swapper_4m_tsb_phys_patch;
2131 extern unsigned int __swapper_4m_tsb_phys_patch_end;
2132 ktsb_pa = (kern_base +
2133 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
2134 patch_one_ktsb_phys(&__swapper_4m_tsb_phys_patch,
2135 &__swapper_4m_tsb_phys_patch_end, ktsb_pa);
2136 }
2137#endif
2138}
2139
2140static void __init sun4v_ktsb_init(void)
2141{
2142 unsigned long ktsb_pa;
2143
2144 /* First KTSB for PAGE_SIZE mappings. */
2145 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
2146
2147 switch (PAGE_SIZE) {
2148 case 8 * 1024:
2149 default:
2150 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
2151 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
2152 break;
2153
2154 case 64 * 1024:
2155 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
2156 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
2157 break;
2158
2159 case 512 * 1024:
2160 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
2161 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
2162 break;
2163
2164 case 4 * 1024 * 1024:
2165 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
2166 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
2167 break;
2168 }
2169
2170 ktsb_descr[0].assoc = 1;
2171 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
2172 ktsb_descr[0].ctx_idx = 0;
2173 ktsb_descr[0].tsb_base = ktsb_pa;
2174 ktsb_descr[0].resv = 0;
2175
2176#ifndef CONFIG_DEBUG_PAGEALLOC
2177 /* Second KTSB for 4MB/256MB/2GB/16GB mappings. */
2178 ktsb_pa = (kern_base +
2179 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
2180
2181 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
2182 ktsb_descr[1].pgsz_mask = ((HV_PGSZ_MASK_4MB |
2183 HV_PGSZ_MASK_256MB |
2184 HV_PGSZ_MASK_2GB |
2185 HV_PGSZ_MASK_16GB) &
2186 cpu_pgsz_mask);
2187 ktsb_descr[1].assoc = 1;
2188 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
2189 ktsb_descr[1].ctx_idx = 0;
2190 ktsb_descr[1].tsb_base = ktsb_pa;
2191 ktsb_descr[1].resv = 0;
2192#endif
2193}
2194
2195void sun4v_ktsb_register(void)
2196{
2197 unsigned long pa, ret;
2198
2199 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
2200
2201 ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
2202 if (ret != 0) {
2203 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
2204 "errors with %lx\n", pa, ret);
2205 prom_halt();
2206 }
2207}
2208
2209static void __init sun4u_linear_pte_xor_finalize(void)
2210{
2211#ifndef CONFIG_DEBUG_PAGEALLOC
2212 /* This is where we would add Panther support for
2213 * 32MB and 256MB pages.
2214 */
2215#endif
2216}
2217
2218static void __init sun4v_linear_pte_xor_finalize(void)
2219{
2220 unsigned long pagecv_flag;
2221
2222 /* Bit 9 of TTE is no longer CV bit on M7 processor and it instead
2223 * enables MCD error. Do not set bit 9 on M7 processor.
2224 */
2225 switch (sun4v_chip_type) {
2226 case SUN4V_CHIP_SPARC_M7:
2227 case SUN4V_CHIP_SPARC_M8:
2228 case SUN4V_CHIP_SPARC_SN:
2229 pagecv_flag = 0x00;
2230 break;
2231 default:
2232 pagecv_flag = _PAGE_CV_4V;
2233 break;
2234 }
2235#ifndef CONFIG_DEBUG_PAGEALLOC
2236 if (cpu_pgsz_mask & HV_PGSZ_MASK_256MB) {
2237 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
2238 PAGE_OFFSET;
2239 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | pagecv_flag |
2240 _PAGE_P_4V | _PAGE_W_4V);
2241 } else {
2242 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
2243 }
2244
2245 if (cpu_pgsz_mask & HV_PGSZ_MASK_2GB) {
2246 kern_linear_pte_xor[2] = (_PAGE_VALID | _PAGE_SZ2GB_4V) ^
2247 PAGE_OFFSET;
2248 kern_linear_pte_xor[2] |= (_PAGE_CP_4V | pagecv_flag |
2249 _PAGE_P_4V | _PAGE_W_4V);
2250 } else {
2251 kern_linear_pte_xor[2] = kern_linear_pte_xor[1];
2252 }
2253
2254 if (cpu_pgsz_mask & HV_PGSZ_MASK_16GB) {
2255 kern_linear_pte_xor[3] = (_PAGE_VALID | _PAGE_SZ16GB_4V) ^
2256 PAGE_OFFSET;
2257 kern_linear_pte_xor[3] |= (_PAGE_CP_4V | pagecv_flag |
2258 _PAGE_P_4V | _PAGE_W_4V);
2259 } else {
2260 kern_linear_pte_xor[3] = kern_linear_pte_xor[2];
2261 }
2262#endif
2263}
2264
2265/* paging_init() sets up the page tables */
2266
2267static unsigned long last_valid_pfn;
2268
2269static void sun4u_pgprot_init(void);
2270static void sun4v_pgprot_init(void);
2271
2272#define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
2273#define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
2274#define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
2275#define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
2276#define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
2277#define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
2278
2279/* We need to exclude reserved regions. This exclusion will include
2280 * vmlinux and initrd. To be more precise the initrd size could be used to
2281 * compute a new lower limit because it is freed later during initialization.
2282 */
2283static void __init reduce_memory(phys_addr_t limit_ram)
2284{
2285 limit_ram += memblock_reserved_size();
2286 memblock_enforce_memory_limit(limit_ram);
2287}
2288
2289void __init paging_init(void)
2290{
2291 unsigned long end_pfn, shift, phys_base;
2292 unsigned long real_end, i;
2293
2294 setup_page_offset();
2295
2296 /* These build time checkes make sure that the dcache_dirty_cpu()
2297 * folio->flags usage will work.
2298 *
2299 * When a page gets marked as dcache-dirty, we store the
2300 * cpu number starting at bit 32 in the folio->flags. Also,
2301 * functions like clear_dcache_dirty_cpu use the cpu mask
2302 * in 13-bit signed-immediate instruction fields.
2303 */
2304
2305 /*
2306 * Page flags must not reach into upper 32 bits that are used
2307 * for the cpu number
2308 */
2309 BUILD_BUG_ON(NR_PAGEFLAGS > 32);
2310
2311 /*
2312 * The bit fields placed in the high range must not reach below
2313 * the 32 bit boundary. Otherwise we cannot place the cpu field
2314 * at the 32 bit boundary.
2315 */
2316 BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
2317 ilog2(roundup_pow_of_two(NR_CPUS)) > 32);
2318
2319 BUILD_BUG_ON(NR_CPUS > 4096);
2320
2321 kern_base = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
2322 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
2323
2324 /* Invalidate both kernel TSBs. */
2325 memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
2326#ifndef CONFIG_DEBUG_PAGEALLOC
2327 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
2328#endif
2329
2330 /* TTE.cv bit on sparc v9 occupies the same position as TTE.mcde
2331 * bit on M7 processor. This is a conflicting usage of the same
2332 * bit. Enabling TTE.cv on M7 would turn on Memory Corruption
2333 * Detection error on all pages and this will lead to problems
2334 * later. Kernel does not run with MCD enabled and hence rest
2335 * of the required steps to fully configure memory corruption
2336 * detection are not taken. We need to ensure TTE.mcde is not
2337 * set on M7 processor. Compute the value of cacheability
2338 * flag for use later taking this into consideration.
2339 */
2340 switch (sun4v_chip_type) {
2341 case SUN4V_CHIP_SPARC_M7:
2342 case SUN4V_CHIP_SPARC_M8:
2343 case SUN4V_CHIP_SPARC_SN:
2344 page_cache4v_flag = _PAGE_CP_4V;
2345 break;
2346 default:
2347 page_cache4v_flag = _PAGE_CACHE_4V;
2348 break;
2349 }
2350
2351 if (tlb_type == hypervisor)
2352 sun4v_pgprot_init();
2353 else
2354 sun4u_pgprot_init();
2355
2356 if (tlb_type == cheetah_plus ||
2357 tlb_type == hypervisor) {
2358 tsb_phys_patch();
2359 ktsb_phys_patch();
2360 }
2361
2362 if (tlb_type == hypervisor)
2363 sun4v_patch_tlb_handlers();
2364
2365 /* Find available physical memory...
2366 *
2367 * Read it twice in order to work around a bug in openfirmware.
2368 * The call to grab this table itself can cause openfirmware to
2369 * allocate memory, which in turn can take away some space from
2370 * the list of available memory. Reading it twice makes sure
2371 * we really do get the final value.
2372 */
2373 read_obp_translations();
2374 read_obp_memory("reg", &pall[0], &pall_ents);
2375 read_obp_memory("available", &pavail[0], &pavail_ents);
2376 read_obp_memory("available", &pavail[0], &pavail_ents);
2377
2378 phys_base = 0xffffffffffffffffUL;
2379 for (i = 0; i < pavail_ents; i++) {
2380 phys_base = min(phys_base, pavail[i].phys_addr);
2381 memblock_add(pavail[i].phys_addr, pavail[i].reg_size);
2382 }
2383
2384 memblock_reserve(kern_base, kern_size);
2385
2386 find_ramdisk(phys_base);
2387
2388 if (cmdline_memory_size)
2389 reduce_memory(cmdline_memory_size);
2390
2391 memblock_allow_resize();
2392 memblock_dump_all();
2393
2394 set_bit(0, mmu_context_bmap);
2395
2396 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
2397
2398 real_end = (unsigned long)_end;
2399 num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << ILOG2_4MB);
2400 printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
2401 num_kernel_image_mappings);
2402
2403 /* Set kernel pgd to upper alias so physical page computations
2404 * work.
2405 */
2406 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
2407
2408 memset(swapper_pg_dir, 0, sizeof(swapper_pg_dir));
2409
2410 inherit_prom_mappings();
2411
2412 /* Ok, we can use our TLB miss and window trap handlers safely. */
2413 setup_tba();
2414
2415 __flush_tlb_all();
2416
2417 prom_build_devicetree();
2418 of_populate_present_mask();
2419#ifndef CONFIG_SMP
2420 of_fill_in_cpu_data();
2421#endif
2422
2423 if (tlb_type == hypervisor) {
2424 sun4v_mdesc_init();
2425 mdesc_populate_present_mask(cpu_all_mask);
2426#ifndef CONFIG_SMP
2427 mdesc_fill_in_cpu_data(cpu_all_mask);
2428#endif
2429 mdesc_get_page_sizes(cpu_all_mask, &cpu_pgsz_mask);
2430
2431 sun4v_linear_pte_xor_finalize();
2432
2433 sun4v_ktsb_init();
2434 sun4v_ktsb_register();
2435 } else {
2436 unsigned long impl, ver;
2437
2438 cpu_pgsz_mask = (HV_PGSZ_MASK_8K | HV_PGSZ_MASK_64K |
2439 HV_PGSZ_MASK_512K | HV_PGSZ_MASK_4MB);
2440
2441 __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
2442 impl = ((ver >> 32) & 0xffff);
2443 if (impl == PANTHER_IMPL)
2444 cpu_pgsz_mask |= (HV_PGSZ_MASK_32MB |
2445 HV_PGSZ_MASK_256MB);
2446
2447 sun4u_linear_pte_xor_finalize();
2448 }
2449
2450 /* Flush the TLBs and the 4M TSB so that the updated linear
2451 * pte XOR settings are realized for all mappings.
2452 */
2453 __flush_tlb_all();
2454#ifndef CONFIG_DEBUG_PAGEALLOC
2455 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
2456#endif
2457 __flush_tlb_all();
2458
2459 /* Setup bootmem... */
2460 last_valid_pfn = end_pfn = bootmem_init(phys_base);
2461
2462 kernel_physical_mapping_init();
2463
2464 {
2465 unsigned long max_zone_pfns[MAX_NR_ZONES];
2466
2467 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
2468
2469 max_zone_pfns[ZONE_NORMAL] = end_pfn;
2470
2471 free_area_init(max_zone_pfns);
2472 }
2473
2474 printk("Booting Linux...\n");
2475}
2476
2477int page_in_phys_avail(unsigned long paddr)
2478{
2479 int i;
2480
2481 paddr &= PAGE_MASK;
2482
2483 for (i = 0; i < pavail_ents; i++) {
2484 unsigned long start, end;
2485
2486 start = pavail[i].phys_addr;
2487 end = start + pavail[i].reg_size;
2488
2489 if (paddr >= start && paddr < end)
2490 return 1;
2491 }
2492 if (paddr >= kern_base && paddr < (kern_base + kern_size))
2493 return 1;
2494#ifdef CONFIG_BLK_DEV_INITRD
2495 if (paddr >= __pa(initrd_start) &&
2496 paddr < __pa(PAGE_ALIGN(initrd_end)))
2497 return 1;
2498#endif
2499
2500 return 0;
2501}
2502
2503static void __init register_page_bootmem_info(void)
2504{
2505#ifdef CONFIG_NUMA
2506 int i;
2507
2508 for_each_online_node(i)
2509 if (NODE_DATA(i)->node_spanned_pages)
2510 register_page_bootmem_info_node(NODE_DATA(i));
2511#endif
2512}
2513void __init mem_init(void)
2514{
2515 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
2516
2517 memblock_free_all();
2518
2519 /*
2520 * Must be done after boot memory is put on freelist, because here we
2521 * might set fields in deferred struct pages that have not yet been
2522 * initialized, and memblock_free_all() initializes all the reserved
2523 * deferred pages for us.
2524 */
2525 register_page_bootmem_info();
2526
2527 /*
2528 * Set up the zero page, mark it reserved, so that page count
2529 * is not manipulated when freeing the page from user ptes.
2530 */
2531 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
2532 if (mem_map_zero == NULL) {
2533 prom_printf("paging_init: Cannot alloc zero page.\n");
2534 prom_halt();
2535 }
2536 mark_page_reserved(mem_map_zero);
2537
2538
2539 if (tlb_type == cheetah || tlb_type == cheetah_plus)
2540 cheetah_ecache_flush_init();
2541}
2542
2543void free_initmem(void)
2544{
2545 unsigned long addr, initend;
2546 int do_free = 1;
2547
2548 /* If the physical memory maps were trimmed by kernel command
2549 * line options, don't even try freeing this initmem stuff up.
2550 * The kernel image could have been in the trimmed out region
2551 * and if so the freeing below will free invalid page structs.
2552 */
2553 if (cmdline_memory_size)
2554 do_free = 0;
2555
2556 /*
2557 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
2558 */
2559 addr = PAGE_ALIGN((unsigned long)(__init_begin));
2560 initend = (unsigned long)(__init_end) & PAGE_MASK;
2561 for (; addr < initend; addr += PAGE_SIZE) {
2562 unsigned long page;
2563
2564 page = (addr +
2565 ((unsigned long) __va(kern_base)) -
2566 ((unsigned long) KERNBASE));
2567 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
2568
2569 if (do_free)
2570 free_reserved_page(virt_to_page(page));
2571 }
2572}
2573
2574pgprot_t PAGE_KERNEL __read_mostly;
2575EXPORT_SYMBOL(PAGE_KERNEL);
2576
2577pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
2578pgprot_t PAGE_COPY __read_mostly;
2579
2580pgprot_t PAGE_SHARED __read_mostly;
2581EXPORT_SYMBOL(PAGE_SHARED);
2582
2583unsigned long pg_iobits __read_mostly;
2584
2585unsigned long _PAGE_IE __read_mostly;
2586EXPORT_SYMBOL(_PAGE_IE);
2587
2588unsigned long _PAGE_E __read_mostly;
2589EXPORT_SYMBOL(_PAGE_E);
2590
2591unsigned long _PAGE_CACHE __read_mostly;
2592EXPORT_SYMBOL(_PAGE_CACHE);
2593
2594#ifdef CONFIG_SPARSEMEM_VMEMMAP
2595int __meminit vmemmap_populate(unsigned long vstart, unsigned long vend,
2596 int node, struct vmem_altmap *altmap)
2597{
2598 unsigned long pte_base;
2599
2600 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2601 _PAGE_CP_4U | _PAGE_CV_4U |
2602 _PAGE_P_4U | _PAGE_W_4U);
2603 if (tlb_type == hypervisor)
2604 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2605 page_cache4v_flag | _PAGE_P_4V | _PAGE_W_4V);
2606
2607 pte_base |= _PAGE_PMD_HUGE;
2608
2609 vstart = vstart & PMD_MASK;
2610 vend = ALIGN(vend, PMD_SIZE);
2611 for (; vstart < vend; vstart += PMD_SIZE) {
2612 pgd_t *pgd = vmemmap_pgd_populate(vstart, node);
2613 unsigned long pte;
2614 p4d_t *p4d;
2615 pud_t *pud;
2616 pmd_t *pmd;
2617
2618 if (!pgd)
2619 return -ENOMEM;
2620
2621 p4d = vmemmap_p4d_populate(pgd, vstart, node);
2622 if (!p4d)
2623 return -ENOMEM;
2624
2625 pud = vmemmap_pud_populate(p4d, vstart, node);
2626 if (!pud)
2627 return -ENOMEM;
2628
2629 pmd = pmd_offset(pud, vstart);
2630 pte = pmd_val(*pmd);
2631 if (!(pte & _PAGE_VALID)) {
2632 void *block = vmemmap_alloc_block(PMD_SIZE, node);
2633
2634 if (!block)
2635 return -ENOMEM;
2636
2637 pmd_val(*pmd) = pte_base | __pa(block);
2638 }
2639 }
2640
2641 return 0;
2642}
2643
2644void vmemmap_free(unsigned long start, unsigned long end,
2645 struct vmem_altmap *altmap)
2646{
2647}
2648#endif /* CONFIG_SPARSEMEM_VMEMMAP */
2649
2650/* These are actually filled in at boot time by sun4{u,v}_pgprot_init() */
2651static pgprot_t protection_map[16] __ro_after_init;
2652
2653static void prot_init_common(unsigned long page_none,
2654 unsigned long page_shared,
2655 unsigned long page_copy,
2656 unsigned long page_readonly,
2657 unsigned long page_exec_bit)
2658{
2659 PAGE_COPY = __pgprot(page_copy);
2660 PAGE_SHARED = __pgprot(page_shared);
2661
2662 protection_map[0x0] = __pgprot(page_none);
2663 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
2664 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
2665 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
2666 protection_map[0x4] = __pgprot(page_readonly);
2667 protection_map[0x5] = __pgprot(page_readonly);
2668 protection_map[0x6] = __pgprot(page_copy);
2669 protection_map[0x7] = __pgprot(page_copy);
2670 protection_map[0x8] = __pgprot(page_none);
2671 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
2672 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
2673 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
2674 protection_map[0xc] = __pgprot(page_readonly);
2675 protection_map[0xd] = __pgprot(page_readonly);
2676 protection_map[0xe] = __pgprot(page_shared);
2677 protection_map[0xf] = __pgprot(page_shared);
2678}
2679
2680static void __init sun4u_pgprot_init(void)
2681{
2682 unsigned long page_none, page_shared, page_copy, page_readonly;
2683 unsigned long page_exec_bit;
2684 int i;
2685
2686 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2687 _PAGE_CACHE_4U | _PAGE_P_4U |
2688 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2689 _PAGE_EXEC_4U);
2690 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2691 _PAGE_CACHE_4U | _PAGE_P_4U |
2692 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2693 _PAGE_EXEC_4U | _PAGE_L_4U);
2694
2695 _PAGE_IE = _PAGE_IE_4U;
2696 _PAGE_E = _PAGE_E_4U;
2697 _PAGE_CACHE = _PAGE_CACHE_4U;
2698
2699 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
2700 __ACCESS_BITS_4U | _PAGE_E_4U);
2701
2702#ifdef CONFIG_DEBUG_PAGEALLOC
2703 kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
2704#else
2705 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
2706 PAGE_OFFSET;
2707#endif
2708 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
2709 _PAGE_P_4U | _PAGE_W_4U);
2710
2711 for (i = 1; i < 4; i++)
2712 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2713
2714 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
2715 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
2716 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
2717
2718
2719 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
2720 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2721 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
2722 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2723 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2724 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2725 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2726
2727 page_exec_bit = _PAGE_EXEC_4U;
2728
2729 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2730 page_exec_bit);
2731}
2732
2733static void __init sun4v_pgprot_init(void)
2734{
2735 unsigned long page_none, page_shared, page_copy, page_readonly;
2736 unsigned long page_exec_bit;
2737 int i;
2738
2739 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
2740 page_cache4v_flag | _PAGE_P_4V |
2741 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
2742 _PAGE_EXEC_4V);
2743 PAGE_KERNEL_LOCKED = PAGE_KERNEL;
2744
2745 _PAGE_IE = _PAGE_IE_4V;
2746 _PAGE_E = _PAGE_E_4V;
2747 _PAGE_CACHE = page_cache4v_flag;
2748
2749#ifdef CONFIG_DEBUG_PAGEALLOC
2750 kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
2751#else
2752 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
2753 PAGE_OFFSET;
2754#endif
2755 kern_linear_pte_xor[0] |= (page_cache4v_flag | _PAGE_P_4V |
2756 _PAGE_W_4V);
2757
2758 for (i = 1; i < 4; i++)
2759 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2760
2761 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
2762 __ACCESS_BITS_4V | _PAGE_E_4V);
2763
2764 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
2765 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
2766 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
2767 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
2768
2769 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | page_cache4v_flag;
2770 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2771 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
2772 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2773 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2774 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2775 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2776
2777 page_exec_bit = _PAGE_EXEC_4V;
2778
2779 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2780 page_exec_bit);
2781}
2782
2783unsigned long pte_sz_bits(unsigned long sz)
2784{
2785 if (tlb_type == hypervisor) {
2786 switch (sz) {
2787 case 8 * 1024:
2788 default:
2789 return _PAGE_SZ8K_4V;
2790 case 64 * 1024:
2791 return _PAGE_SZ64K_4V;
2792 case 512 * 1024:
2793 return _PAGE_SZ512K_4V;
2794 case 4 * 1024 * 1024:
2795 return _PAGE_SZ4MB_4V;
2796 }
2797 } else {
2798 switch (sz) {
2799 case 8 * 1024:
2800 default:
2801 return _PAGE_SZ8K_4U;
2802 case 64 * 1024:
2803 return _PAGE_SZ64K_4U;
2804 case 512 * 1024:
2805 return _PAGE_SZ512K_4U;
2806 case 4 * 1024 * 1024:
2807 return _PAGE_SZ4MB_4U;
2808 }
2809 }
2810}
2811
2812pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
2813{
2814 pte_t pte;
2815
2816 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot));
2817 pte_val(pte) |= (((unsigned long)space) << 32);
2818 pte_val(pte) |= pte_sz_bits(page_size);
2819
2820 return pte;
2821}
2822
2823static unsigned long kern_large_tte(unsigned long paddr)
2824{
2825 unsigned long val;
2826
2827 val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2828 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
2829 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
2830 if (tlb_type == hypervisor)
2831 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2832 page_cache4v_flag | _PAGE_P_4V |
2833 _PAGE_EXEC_4V | _PAGE_W_4V);
2834
2835 return val | paddr;
2836}
2837
2838/* If not locked, zap it. */
2839void __flush_tlb_all(void)
2840{
2841 unsigned long pstate;
2842 int i;
2843
2844 __asm__ __volatile__("flushw\n\t"
2845 "rdpr %%pstate, %0\n\t"
2846 "wrpr %0, %1, %%pstate"
2847 : "=r" (pstate)
2848 : "i" (PSTATE_IE));
2849 if (tlb_type == hypervisor) {
2850 sun4v_mmu_demap_all();
2851 } else if (tlb_type == spitfire) {
2852 for (i = 0; i < 64; i++) {
2853 /* Spitfire Errata #32 workaround */
2854 /* NOTE: Always runs on spitfire, so no
2855 * cheetah+ page size encodings.
2856 */
2857 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2858 "flush %%g6"
2859 : /* No outputs */
2860 : "r" (0),
2861 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2862
2863 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
2864 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2865 "membar #Sync"
2866 : /* no outputs */
2867 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
2868 spitfire_put_dtlb_data(i, 0x0UL);
2869 }
2870
2871 /* Spitfire Errata #32 workaround */
2872 /* NOTE: Always runs on spitfire, so no
2873 * cheetah+ page size encodings.
2874 */
2875 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2876 "flush %%g6"
2877 : /* No outputs */
2878 : "r" (0),
2879 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2880
2881 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
2882 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2883 "membar #Sync"
2884 : /* no outputs */
2885 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
2886 spitfire_put_itlb_data(i, 0x0UL);
2887 }
2888 }
2889 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
2890 cheetah_flush_dtlb_all();
2891 cheetah_flush_itlb_all();
2892 }
2893 __asm__ __volatile__("wrpr %0, 0, %%pstate"
2894 : : "r" (pstate));
2895}
2896
2897pte_t *pte_alloc_one_kernel(struct mm_struct *mm)
2898{
2899 struct page *page = alloc_page(GFP_KERNEL | __GFP_ZERO);
2900 pte_t *pte = NULL;
2901
2902 if (page)
2903 pte = (pte_t *) page_address(page);
2904
2905 return pte;
2906}
2907
2908pgtable_t pte_alloc_one(struct mm_struct *mm)
2909{
2910 struct ptdesc *ptdesc = pagetable_alloc(GFP_KERNEL | __GFP_ZERO, 0);
2911
2912 if (!ptdesc)
2913 return NULL;
2914 if (!pagetable_pte_ctor(ptdesc)) {
2915 pagetable_free(ptdesc);
2916 return NULL;
2917 }
2918 return ptdesc_address(ptdesc);
2919}
2920
2921void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
2922{
2923 free_page((unsigned long)pte);
2924}
2925
2926static void __pte_free(pgtable_t pte)
2927{
2928 struct ptdesc *ptdesc = virt_to_ptdesc(pte);
2929
2930 pagetable_pte_dtor(ptdesc);
2931 pagetable_free(ptdesc);
2932}
2933
2934void pte_free(struct mm_struct *mm, pgtable_t pte)
2935{
2936 __pte_free(pte);
2937}
2938
2939void pgtable_free(void *table, bool is_page)
2940{
2941 if (is_page)
2942 __pte_free(table);
2943 else
2944 kmem_cache_free(pgtable_cache, table);
2945}
2946
2947#ifdef CONFIG_TRANSPARENT_HUGEPAGE
2948static void pte_free_now(struct rcu_head *head)
2949{
2950 struct page *page;
2951
2952 page = container_of(head, struct page, rcu_head);
2953 __pte_free((pgtable_t)page_address(page));
2954}
2955
2956void pte_free_defer(struct mm_struct *mm, pgtable_t pgtable)
2957{
2958 struct page *page;
2959
2960 page = virt_to_page(pgtable);
2961 call_rcu(&page->rcu_head, pte_free_now);
2962}
2963
2964void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
2965 pmd_t *pmd)
2966{
2967 unsigned long pte, flags;
2968 struct mm_struct *mm;
2969 pmd_t entry = *pmd;
2970
2971 if (!pmd_leaf(entry) || !pmd_young(entry))
2972 return;
2973
2974 pte = pmd_val(entry);
2975
2976 /* Don't insert a non-valid PMD into the TSB, we'll deadlock. */
2977 if (!(pte & _PAGE_VALID))
2978 return;
2979
2980 /* We are fabricating 8MB pages using 4MB real hw pages. */
2981 pte |= (addr & (1UL << REAL_HPAGE_SHIFT));
2982
2983 mm = vma->vm_mm;
2984
2985 spin_lock_irqsave(&mm->context.lock, flags);
2986
2987 if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL)
2988 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT,
2989 addr, pte);
2990
2991 spin_unlock_irqrestore(&mm->context.lock, flags);
2992}
2993#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
2994
2995#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
2996static void context_reload(void *__data)
2997{
2998 struct mm_struct *mm = __data;
2999
3000 if (mm == current->mm)
3001 load_secondary_context(mm);
3002}
3003
3004void hugetlb_setup(struct pt_regs *regs)
3005{
3006 struct mm_struct *mm = current->mm;
3007 struct tsb_config *tp;
3008
3009 if (faulthandler_disabled() || !mm) {
3010 const struct exception_table_entry *entry;
3011
3012 entry = search_exception_tables(regs->tpc);
3013 if (entry) {
3014 regs->tpc = entry->fixup;
3015 regs->tnpc = regs->tpc + 4;
3016 return;
3017 }
3018 pr_alert("Unexpected HugeTLB setup in atomic context.\n");
3019 die_if_kernel("HugeTSB in atomic", regs);
3020 }
3021
3022 tp = &mm->context.tsb_block[MM_TSB_HUGE];
3023 if (likely(tp->tsb == NULL))
3024 tsb_grow(mm, MM_TSB_HUGE, 0);
3025
3026 tsb_context_switch(mm);
3027 smp_tsb_sync(mm);
3028
3029 /* On UltraSPARC-III+ and later, configure the second half of
3030 * the Data-TLB for huge pages.
3031 */
3032 if (tlb_type == cheetah_plus) {
3033 bool need_context_reload = false;
3034 unsigned long ctx;
3035
3036 spin_lock_irq(&ctx_alloc_lock);
3037 ctx = mm->context.sparc64_ctx_val;
3038 ctx &= ~CTX_PGSZ_MASK;
3039 ctx |= CTX_PGSZ_BASE << CTX_PGSZ0_SHIFT;
3040 ctx |= CTX_PGSZ_HUGE << CTX_PGSZ1_SHIFT;
3041
3042 if (ctx != mm->context.sparc64_ctx_val) {
3043 /* When changing the page size fields, we
3044 * must perform a context flush so that no
3045 * stale entries match. This flush must
3046 * occur with the original context register
3047 * settings.
3048 */
3049 do_flush_tlb_mm(mm);
3050
3051 /* Reload the context register of all processors
3052 * also executing in this address space.
3053 */
3054 mm->context.sparc64_ctx_val = ctx;
3055 need_context_reload = true;
3056 }
3057 spin_unlock_irq(&ctx_alloc_lock);
3058
3059 if (need_context_reload)
3060 on_each_cpu(context_reload, mm, 0);
3061 }
3062}
3063#endif
3064
3065static struct resource code_resource = {
3066 .name = "Kernel code",
3067 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
3068};
3069
3070static struct resource data_resource = {
3071 .name = "Kernel data",
3072 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
3073};
3074
3075static struct resource bss_resource = {
3076 .name = "Kernel bss",
3077 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
3078};
3079
3080static inline resource_size_t compute_kern_paddr(void *addr)
3081{
3082 return (resource_size_t) (addr - KERNBASE + kern_base);
3083}
3084
3085static void __init kernel_lds_init(void)
3086{
3087 code_resource.start = compute_kern_paddr(_text);
3088 code_resource.end = compute_kern_paddr(_etext - 1);
3089 data_resource.start = compute_kern_paddr(_etext);
3090 data_resource.end = compute_kern_paddr(_edata - 1);
3091 bss_resource.start = compute_kern_paddr(__bss_start);
3092 bss_resource.end = compute_kern_paddr(_end - 1);
3093}
3094
3095static int __init report_memory(void)
3096{
3097 int i;
3098 struct resource *res;
3099
3100 kernel_lds_init();
3101
3102 for (i = 0; i < pavail_ents; i++) {
3103 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
3104
3105 if (!res) {
3106 pr_warn("Failed to allocate source.\n");
3107 break;
3108 }
3109
3110 res->name = "System RAM";
3111 res->start = pavail[i].phys_addr;
3112 res->end = pavail[i].phys_addr + pavail[i].reg_size - 1;
3113 res->flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM;
3114
3115 if (insert_resource(&iomem_resource, res) < 0) {
3116 pr_warn("Resource insertion failed.\n");
3117 break;
3118 }
3119
3120 insert_resource(res, &code_resource);
3121 insert_resource(res, &data_resource);
3122 insert_resource(res, &bss_resource);
3123 }
3124
3125 return 0;
3126}
3127arch_initcall(report_memory);
3128
3129#ifdef CONFIG_SMP
3130#define do_flush_tlb_kernel_range smp_flush_tlb_kernel_range
3131#else
3132#define do_flush_tlb_kernel_range __flush_tlb_kernel_range
3133#endif
3134
3135void flush_tlb_kernel_range(unsigned long start, unsigned long end)
3136{
3137 if (start < HI_OBP_ADDRESS && end > LOW_OBP_ADDRESS) {
3138 if (start < LOW_OBP_ADDRESS) {
3139 flush_tsb_kernel_range(start, LOW_OBP_ADDRESS);
3140 do_flush_tlb_kernel_range(start, LOW_OBP_ADDRESS);
3141 }
3142 if (end > HI_OBP_ADDRESS) {
3143 flush_tsb_kernel_range(HI_OBP_ADDRESS, end);
3144 do_flush_tlb_kernel_range(HI_OBP_ADDRESS, end);
3145 }
3146 } else {
3147 flush_tsb_kernel_range(start, end);
3148 do_flush_tlb_kernel_range(start, end);
3149 }
3150}
3151
3152void copy_user_highpage(struct page *to, struct page *from,
3153 unsigned long vaddr, struct vm_area_struct *vma)
3154{
3155 char *vfrom, *vto;
3156
3157 vfrom = kmap_atomic(from);
3158 vto = kmap_atomic(to);
3159 copy_user_page(vto, vfrom, vaddr, to);
3160 kunmap_atomic(vto);
3161 kunmap_atomic(vfrom);
3162
3163 /* If this page has ADI enabled, copy over any ADI tags
3164 * as well
3165 */
3166 if (vma->vm_flags & VM_SPARC_ADI) {
3167 unsigned long pfrom, pto, i, adi_tag;
3168
3169 pfrom = page_to_phys(from);
3170 pto = page_to_phys(to);
3171
3172 for (i = pfrom; i < (pfrom + PAGE_SIZE); i += adi_blksize()) {
3173 asm volatile("ldxa [%1] %2, %0\n\t"
3174 : "=r" (adi_tag)
3175 : "r" (i), "i" (ASI_MCD_REAL));
3176 asm volatile("stxa %0, [%1] %2\n\t"
3177 :
3178 : "r" (adi_tag), "r" (pto),
3179 "i" (ASI_MCD_REAL));
3180 pto += adi_blksize();
3181 }
3182 asm volatile("membar #Sync\n\t");
3183 }
3184}
3185EXPORT_SYMBOL(copy_user_highpage);
3186
3187void copy_highpage(struct page *to, struct page *from)
3188{
3189 char *vfrom, *vto;
3190
3191 vfrom = kmap_atomic(from);
3192 vto = kmap_atomic(to);
3193 copy_page(vto, vfrom);
3194 kunmap_atomic(vto);
3195 kunmap_atomic(vfrom);
3196
3197 /* If this platform is ADI enabled, copy any ADI tags
3198 * as well
3199 */
3200 if (adi_capable()) {
3201 unsigned long pfrom, pto, i, adi_tag;
3202
3203 pfrom = page_to_phys(from);
3204 pto = page_to_phys(to);
3205
3206 for (i = pfrom; i < (pfrom + PAGE_SIZE); i += adi_blksize()) {
3207 asm volatile("ldxa [%1] %2, %0\n\t"
3208 : "=r" (adi_tag)
3209 : "r" (i), "i" (ASI_MCD_REAL));
3210 asm volatile("stxa %0, [%1] %2\n\t"
3211 :
3212 : "r" (adi_tag), "r" (pto),
3213 "i" (ASI_MCD_REAL));
3214 pto += adi_blksize();
3215 }
3216 asm volatile("membar #Sync\n\t");
3217 }
3218}
3219EXPORT_SYMBOL(copy_highpage);
3220
3221pgprot_t vm_get_page_prot(unsigned long vm_flags)
3222{
3223 unsigned long prot = pgprot_val(protection_map[vm_flags &
3224 (VM_READ|VM_WRITE|VM_EXEC|VM_SHARED)]);
3225
3226 if (vm_flags & VM_SPARC_ADI)
3227 prot |= _PAGE_MCD_4V;
3228
3229 return __pgprot(prot);
3230}
3231EXPORT_SYMBOL(vm_get_page_prot);