1/*
   2 * This file is subject to the terms and conditions of the GNU General Public
   3 * License.  See the file "COPYING" in the main directory of this archive
   4 * for more details.
   5 *
   6 * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
   7 * Copyright (C) 2000 Silicon Graphics, Inc.
   8 * Modified for further R[236]000 support by Paul M. Antoine, 1996.
   9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
  10 * Copyright (C) 2000, 07 MIPS Technologies, Inc.
  11 * Copyright (C) 2003, 2004  Maciej W. Rozycki
  12 */
  13#ifndef _ASM_MIPSREGS_H
  14#define _ASM_MIPSREGS_H
  15
  16#include <linux/linkage.h>
  17#include <linux/types.h>
  18#include <asm/hazards.h>
  19#include <asm/war.h>
  20
  21/*
  22 * The following macros are especially useful for __asm__
  23 * inline assembler.
  24 */
  25#ifndef __STR
  26#define __STR(x) #x
  27#endif
  28#ifndef STR
  29#define STR(x) __STR(x)
  30#endif
  31
  32/*
  33 *  Configure language
  34 */
  35#ifdef __ASSEMBLY__
  36#define _ULCAST_
  37#define _U64CAST_
  38#else
  39#define _ULCAST_ (unsigned long)
  40#define _U64CAST_ (u64)
  41#endif
  42
  43/*
  44 * Coprocessor 0 register names
 
 
 
  45 */
  46#define CP0_INDEX $0
  47#define CP0_RANDOM $1
  48#define CP0_ENTRYLO0 $2
  49#define CP0_ENTRYLO1 $3
  50#define CP0_CONF $3
  51#define CP0_GLOBALNUMBER $3, 1
  52#define CP0_CONTEXT $4
  53#define CP0_PAGEMASK $5
  54#define CP0_SEGCTL0 $5, 2
  55#define CP0_SEGCTL1 $5, 3
  56#define CP0_SEGCTL2 $5, 4
  57#define CP0_WIRED $6
  58#define CP0_INFO $7
  59#define CP0_HWRENA $7
  60#define CP0_BADVADDR $8
  61#define CP0_BADINSTR $8, 1
  62#define CP0_COUNT $9
  63#define CP0_ENTRYHI $10
  64#define CP0_GUESTCTL1 $10, 4
  65#define CP0_GUESTCTL2 $10, 5
  66#define CP0_GUESTCTL3 $10, 6
  67#define CP0_COMPARE $11
  68#define CP0_GUESTCTL0EXT $11, 4
  69#define CP0_STATUS $12
  70#define CP0_GUESTCTL0 $12, 6
  71#define CP0_GTOFFSET $12, 7
  72#define CP0_CAUSE $13
  73#define CP0_EPC $14
  74#define CP0_PRID $15
  75#define CP0_EBASE $15, 1
  76#define CP0_CMGCRBASE $15, 3
  77#define CP0_CONFIG $16
  78#define CP0_CONFIG3 $16, 3
  79#define CP0_CONFIG5 $16, 5
  80#define CP0_LLADDR $17
  81#define CP0_WATCHLO $18
  82#define CP0_WATCHHI $19
  83#define CP0_XCONTEXT $20
  84#define CP0_FRAMEMASK $21
  85#define CP0_DIAGNOSTIC $22
  86#define CP0_DEBUG $23
  87#define CP0_DEPC $24
  88#define CP0_PERFORMANCE $25
  89#define CP0_ECC $26
  90#define CP0_CACHEERR $27
  91#define CP0_TAGLO $28
  92#define CP0_TAGHI $29
  93#define CP0_ERROREPC $30
  94#define CP0_DESAVE $31
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  95
  96/*
  97 * R4640/R4650 cp0 register names.  These registers are listed
  98 * here only for completeness; without MMU these CPUs are not useable
  99 * by Linux.  A future ELKS port might take make Linux run on them
 100 * though ...
 101 */
 102#define CP0_IBASE $0
 103#define CP0_IBOUND $1
 104#define CP0_DBASE $2
 105#define CP0_DBOUND $3
 106#define CP0_CALG $17
 107#define CP0_IWATCH $18
 108#define CP0_DWATCH $19
 109
 110/*
 111 * Coprocessor 0 Set 1 register names
 112 */
 113#define CP0_S1_DERRADDR0  $26
 114#define CP0_S1_DERRADDR1  $27
 115#define CP0_S1_INTCONTROL $20
 116
 117/*
 118 * Coprocessor 0 Set 2 register names
 119 */
 120#define CP0_S2_SRSCTL	  $12	/* MIPSR2 */
 121
 122/*
 123 * Coprocessor 0 Set 3 register names
 124 */
 125#define CP0_S3_SRSMAP	  $12	/* MIPSR2 */
 126
 127/*
 128 *  TX39 Series
 129 */
 130#define CP0_TX39_CACHE	$7
 131
 132
 133/* Generic EntryLo bit definitions */
 134#define ENTRYLO_G		(_ULCAST_(1) << 0)
 135#define ENTRYLO_V		(_ULCAST_(1) << 1)
 136#define ENTRYLO_D		(_ULCAST_(1) << 2)
 137#define ENTRYLO_C_SHIFT		3
 138#define ENTRYLO_C		(_ULCAST_(7) << ENTRYLO_C_SHIFT)
 139
 140/* R3000 EntryLo bit definitions */
 141#define R3K_ENTRYLO_G		(_ULCAST_(1) << 8)
 142#define R3K_ENTRYLO_V		(_ULCAST_(1) << 9)
 143#define R3K_ENTRYLO_D		(_ULCAST_(1) << 10)
 144#define R3K_ENTRYLO_N		(_ULCAST_(1) << 11)
 145
 146/* MIPS32/64 EntryLo bit definitions */
 147#define MIPS_ENTRYLO_PFN_SHIFT	6
 148#define MIPS_ENTRYLO_XI		(_ULCAST_(1) << (BITS_PER_LONG - 2))
 149#define MIPS_ENTRYLO_RI		(_ULCAST_(1) << (BITS_PER_LONG - 1))
 150
 151/*
 152 * MIPSr6+ GlobalNumber register definitions
 153 */
 154#define MIPS_GLOBALNUMBER_VP_SHF	0
 155#define MIPS_GLOBALNUMBER_VP		(_ULCAST_(0xff) << MIPS_GLOBALNUMBER_VP_SHF)
 156#define MIPS_GLOBALNUMBER_CORE_SHF	8
 157#define MIPS_GLOBALNUMBER_CORE		(_ULCAST_(0xff) << MIPS_GLOBALNUMBER_CORE_SHF)
 158#define MIPS_GLOBALNUMBER_CLUSTER_SHF	16
 159#define MIPS_GLOBALNUMBER_CLUSTER	(_ULCAST_(0xf) << MIPS_GLOBALNUMBER_CLUSTER_SHF)
 160
 161/*
 162 * Values for PageMask register
 163 */
 164#ifdef CONFIG_CPU_VR41XX
 165
 166/* Why doesn't stupidity hurt ... */
 167
 168#define PM_1K		0x00000000
 169#define PM_4K		0x00001800
 170#define PM_16K		0x00007800
 171#define PM_64K		0x0001f800
 172#define PM_256K		0x0007f800
 173
 174#else
 175
 176#define PM_4K		0x00000000
 177#define PM_8K		0x00002000
 178#define PM_16K		0x00006000
 179#define PM_32K		0x0000e000
 180#define PM_64K		0x0001e000
 181#define PM_128K		0x0003e000
 182#define PM_256K		0x0007e000
 183#define PM_512K		0x000fe000
 184#define PM_1M		0x001fe000
 185#define PM_2M		0x003fe000
 186#define PM_4M		0x007fe000
 187#define PM_8M		0x00ffe000
 188#define PM_16M		0x01ffe000
 189#define PM_32M		0x03ffe000
 190#define PM_64M		0x07ffe000
 191#define PM_256M		0x1fffe000
 192#define PM_1G		0x7fffe000
 193
 194#endif
 195
 196/*
 197 * Default page size for a given kernel configuration
 198 */
 199#ifdef CONFIG_PAGE_SIZE_4KB
 200#define PM_DEFAULT_MASK PM_4K
 201#elif defined(CONFIG_PAGE_SIZE_8KB)
 202#define PM_DEFAULT_MASK PM_8K
 203#elif defined(CONFIG_PAGE_SIZE_16KB)
 204#define PM_DEFAULT_MASK PM_16K
 205#elif defined(CONFIG_PAGE_SIZE_32KB)
 206#define PM_DEFAULT_MASK PM_32K
 207#elif defined(CONFIG_PAGE_SIZE_64KB)
 208#define PM_DEFAULT_MASK PM_64K
 209#else
 210#error Bad page size configuration!
 211#endif
 212
 213/*
 214 * Default huge tlb size for a given kernel configuration
 215 */
 216#ifdef CONFIG_PAGE_SIZE_4KB
 217#define PM_HUGE_MASK	PM_1M
 218#elif defined(CONFIG_PAGE_SIZE_8KB)
 219#define PM_HUGE_MASK	PM_4M
 220#elif defined(CONFIG_PAGE_SIZE_16KB)
 221#define PM_HUGE_MASK	PM_16M
 222#elif defined(CONFIG_PAGE_SIZE_32KB)
 223#define PM_HUGE_MASK	PM_64M
 224#elif defined(CONFIG_PAGE_SIZE_64KB)
 225#define PM_HUGE_MASK	PM_256M
 226#elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
 227#error Bad page size configuration for hugetlbfs!
 228#endif
 229
 230/*
 231 * Wired register bits
 232 */
 233#define MIPSR6_WIRED_LIMIT_SHIFT 16
 234#define MIPSR6_WIRED_LIMIT	(_ULCAST_(0xffff) << MIPSR6_WIRED_LIMIT_SHIFT)
 235#define MIPSR6_WIRED_WIRED_SHIFT 0
 236#define MIPSR6_WIRED_WIRED	(_ULCAST_(0xffff) << MIPSR6_WIRED_WIRED_SHIFT)
 237
 238/*
 239 * Values used for computation of new tlb entries
 240 */
 241#define PL_4K		12
 242#define PL_16K		14
 243#define PL_64K		16
 244#define PL_256K		18
 245#define PL_1M		20
 246#define PL_4M		22
 247#define PL_16M		24
 248#define PL_64M		26
 249#define PL_256M		28
 250
 251/*
 252 * PageGrain bits
 253 */
 254#define PG_RIE		(_ULCAST_(1) <<	 31)
 255#define PG_XIE		(_ULCAST_(1) <<	 30)
 256#define PG_ELPA		(_ULCAST_(1) <<	 29)
 257#define PG_ESP		(_ULCAST_(1) <<	 28)
 258#define PG_IEC		(_ULCAST_(1) <<  27)
 259
 260/* MIPS32/64 EntryHI bit definitions */
 261#define MIPS_ENTRYHI_EHINV	(_ULCAST_(1) << 10)
 262#define MIPS_ENTRYHI_ASIDX	(_ULCAST_(0x3) << 8)
 263#define MIPS_ENTRYHI_ASID	(_ULCAST_(0xff) << 0)
 264
 265/*
 266 * R4x00 interrupt enable / cause bits
 267 */
 268#define IE_SW0		(_ULCAST_(1) <<	 8)
 269#define IE_SW1		(_ULCAST_(1) <<	 9)
 270#define IE_IRQ0		(_ULCAST_(1) << 10)
 271#define IE_IRQ1		(_ULCAST_(1) << 11)
 272#define IE_IRQ2		(_ULCAST_(1) << 12)
 273#define IE_IRQ3		(_ULCAST_(1) << 13)
 274#define IE_IRQ4		(_ULCAST_(1) << 14)
 275#define IE_IRQ5		(_ULCAST_(1) << 15)
 276
 277/*
 278 * R4x00 interrupt cause bits
 279 */
 280#define C_SW0		(_ULCAST_(1) <<	 8)
 281#define C_SW1		(_ULCAST_(1) <<	 9)
 282#define C_IRQ0		(_ULCAST_(1) << 10)
 283#define C_IRQ1		(_ULCAST_(1) << 11)
 284#define C_IRQ2		(_ULCAST_(1) << 12)
 285#define C_IRQ3		(_ULCAST_(1) << 13)
 286#define C_IRQ4		(_ULCAST_(1) << 14)
 287#define C_IRQ5		(_ULCAST_(1) << 15)
 288
 289/*
 290 * Bitfields in the R4xx0 cp0 status register
 291 */
 292#define ST0_IE			0x00000001
 293#define ST0_EXL			0x00000002
 294#define ST0_ERL			0x00000004
 295#define ST0_KSU			0x00000018
 296#  define KSU_USER		0x00000010
 297#  define KSU_SUPERVISOR	0x00000008
 298#  define KSU_KERNEL		0x00000000
 299#define ST0_UX			0x00000020
 300#define ST0_SX			0x00000040
 301#define ST0_KX			0x00000080
 302#define ST0_DE			0x00010000
 303#define ST0_CE			0x00020000
 304
 
 
 
 
 
 
 305/*
 306 * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
 307 * cacheops in userspace.  This bit exists only on RM7000 and RM9000
 308 * processors.
 309 */
 310#define ST0_CO			0x08000000
 311
 312/*
 313 * Bitfields in the R[23]000 cp0 status register.
 314 */
 315#define ST0_IEC			0x00000001
 316#define ST0_KUC			0x00000002
 317#define ST0_IEP			0x00000004
 318#define ST0_KUP			0x00000008
 319#define ST0_IEO			0x00000010
 320#define ST0_KUO			0x00000020
 321/* bits 6 & 7 are reserved on R[23]000 */
 322#define ST0_ISC			0x00010000
 323#define ST0_SWC			0x00020000
 324#define ST0_CM			0x00080000
 325
 326/*
 327 * Bits specific to the R4640/R4650
 328 */
 329#define ST0_UM			(_ULCAST_(1) <<	 4)
 330#define ST0_IL			(_ULCAST_(1) << 23)
 331#define ST0_DL			(_ULCAST_(1) << 24)
 332
 333/*
 334 * Enable the MIPS MDMX and DSP ASEs
 335 */
 336#define ST0_MX			0x01000000
 337
 338/*
 339 * Status register bits available in all MIPS CPUs.
 340 */
 341#define ST0_IM			0x0000ff00
 342#define	 STATUSB_IP0		8
 343#define	 STATUSF_IP0		(_ULCAST_(1) <<	 8)
 344#define	 STATUSB_IP1		9
 345#define	 STATUSF_IP1		(_ULCAST_(1) <<	 9)
 346#define	 STATUSB_IP2		10
 347#define	 STATUSF_IP2		(_ULCAST_(1) << 10)
 348#define	 STATUSB_IP3		11
 349#define	 STATUSF_IP3		(_ULCAST_(1) << 11)
 350#define	 STATUSB_IP4		12
 351#define	 STATUSF_IP4		(_ULCAST_(1) << 12)
 352#define	 STATUSB_IP5		13
 353#define	 STATUSF_IP5		(_ULCAST_(1) << 13)
 354#define	 STATUSB_IP6		14
 355#define	 STATUSF_IP6		(_ULCAST_(1) << 14)
 356#define	 STATUSB_IP7		15
 357#define	 STATUSF_IP7		(_ULCAST_(1) << 15)
 358#define	 STATUSB_IP8		0
 359#define	 STATUSF_IP8		(_ULCAST_(1) <<	 0)
 360#define	 STATUSB_IP9		1
 361#define	 STATUSF_IP9		(_ULCAST_(1) <<	 1)
 362#define	 STATUSB_IP10		2
 363#define	 STATUSF_IP10		(_ULCAST_(1) <<	 2)
 364#define	 STATUSB_IP11		3
 365#define	 STATUSF_IP11		(_ULCAST_(1) <<	 3)
 366#define	 STATUSB_IP12		4
 367#define	 STATUSF_IP12		(_ULCAST_(1) <<	 4)
 368#define	 STATUSB_IP13		5
 369#define	 STATUSF_IP13		(_ULCAST_(1) <<	 5)
 370#define	 STATUSB_IP14		6
 371#define	 STATUSF_IP14		(_ULCAST_(1) <<	 6)
 372#define	 STATUSB_IP15		7
 373#define	 STATUSF_IP15		(_ULCAST_(1) <<	 7)
 374#define ST0_CH			0x00040000
 375#define ST0_NMI			0x00080000
 376#define ST0_SR			0x00100000
 377#define ST0_TS			0x00200000
 378#define ST0_BEV			0x00400000
 379#define ST0_RE			0x02000000
 380#define ST0_FR			0x04000000
 381#define ST0_CU			0xf0000000
 382#define ST0_CU0			0x10000000
 383#define ST0_CU1			0x20000000
 384#define ST0_CU2			0x40000000
 385#define ST0_CU3			0x80000000
 386#define ST0_XX			0x80000000	/* MIPS IV naming */
 387
 
 
 
 
 
 
 
 388/*
 389 * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
 390 */
 391#define INTCTLB_IPFDC		23
 392#define INTCTLF_IPFDC		(_ULCAST_(7) << INTCTLB_IPFDC)
 393#define INTCTLB_IPPCI		26
 394#define INTCTLF_IPPCI		(_ULCAST_(7) << INTCTLB_IPPCI)
 395#define INTCTLB_IPTI		29
 396#define INTCTLF_IPTI		(_ULCAST_(7) << INTCTLB_IPTI)
 397
 398/*
 399 * Bitfields and bit numbers in the coprocessor 0 cause register.
 400 *
 401 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
 402 */
 403#define CAUSEB_EXCCODE		2
 404#define CAUSEF_EXCCODE		(_ULCAST_(31)  <<  2)
 405#define CAUSEB_IP		8
 406#define CAUSEF_IP		(_ULCAST_(255) <<  8)
 407#define	 CAUSEB_IP0		8
 408#define	 CAUSEF_IP0		(_ULCAST_(1)   <<  8)
 409#define	 CAUSEB_IP1		9
 410#define	 CAUSEF_IP1		(_ULCAST_(1)   <<  9)
 411#define	 CAUSEB_IP2		10
 412#define	 CAUSEF_IP2		(_ULCAST_(1)   << 10)
 413#define	 CAUSEB_IP3		11
 414#define	 CAUSEF_IP3		(_ULCAST_(1)   << 11)
 415#define	 CAUSEB_IP4		12
 416#define	 CAUSEF_IP4		(_ULCAST_(1)   << 12)
 417#define	 CAUSEB_IP5		13
 418#define	 CAUSEF_IP5		(_ULCAST_(1)   << 13)
 419#define	 CAUSEB_IP6		14
 420#define	 CAUSEF_IP6		(_ULCAST_(1)   << 14)
 421#define	 CAUSEB_IP7		15
 422#define	 CAUSEF_IP7		(_ULCAST_(1)   << 15)
 423#define CAUSEB_FDCI		21
 424#define CAUSEF_FDCI		(_ULCAST_(1)   << 21)
 425#define CAUSEB_WP		22
 426#define CAUSEF_WP		(_ULCAST_(1)   << 22)
 427#define CAUSEB_IV		23
 428#define CAUSEF_IV		(_ULCAST_(1)   << 23)
 429#define CAUSEB_PCI		26
 430#define CAUSEF_PCI		(_ULCAST_(1)   << 26)
 431#define CAUSEB_DC		27
 432#define CAUSEF_DC		(_ULCAST_(1)   << 27)
 433#define CAUSEB_CE		28
 434#define CAUSEF_CE		(_ULCAST_(3)   << 28)
 435#define CAUSEB_TI		30
 436#define CAUSEF_TI		(_ULCAST_(1)   << 30)
 437#define CAUSEB_BD		31
 438#define CAUSEF_BD		(_ULCAST_(1)   << 31)
 439
 440/*
 441 * Cause.ExcCode trap codes.
 442 */
 443#define EXCCODE_INT		0	/* Interrupt pending */
 444#define EXCCODE_MOD		1	/* TLB modified fault */
 445#define EXCCODE_TLBL		2	/* TLB miss on load or ifetch */
 446#define EXCCODE_TLBS		3	/* TLB miss on a store */
 447#define EXCCODE_ADEL		4	/* Address error on a load or ifetch */
 448#define EXCCODE_ADES		5	/* Address error on a store */
 449#define EXCCODE_IBE		6	/* Bus error on an ifetch */
 450#define EXCCODE_DBE		7	/* Bus error on a load or store */
 451#define EXCCODE_SYS		8	/* System call */
 452#define EXCCODE_BP		9	/* Breakpoint */
 453#define EXCCODE_RI		10	/* Reserved instruction exception */
 454#define EXCCODE_CPU		11	/* Coprocessor unusable */
 455#define EXCCODE_OV		12	/* Arithmetic overflow */
 456#define EXCCODE_TR		13	/* Trap instruction */
 457#define EXCCODE_MSAFPE		14	/* MSA floating point exception */
 458#define EXCCODE_FPE		15	/* Floating point exception */
 459#define EXCCODE_TLBRI		19	/* TLB Read-Inhibit exception */
 460#define EXCCODE_TLBXI		20	/* TLB Execution-Inhibit exception */
 461#define EXCCODE_MSADIS		21	/* MSA disabled exception */
 462#define EXCCODE_MDMX		22	/* MDMX unusable exception */
 463#define EXCCODE_WATCH		23	/* Watch address reference */
 464#define EXCCODE_MCHECK		24	/* Machine check */
 465#define EXCCODE_THREAD		25	/* Thread exceptions (MT) */
 466#define EXCCODE_DSPDIS		26	/* DSP disabled exception */
 467#define EXCCODE_GE		27	/* Virtualized guest exception (VZ) */
 
 468
 469/* Implementation specific trap codes used by MIPS cores */
 470#define MIPS_EXCCODE_TLBPAR	16	/* TLB parity error exception */
 471
 
 
 
 472/*
 473 * Bits in the coprocessor 0 config register.
 474 */
 475/* Generic bits.  */
 476#define CONF_CM_CACHABLE_NO_WA		0
 477#define CONF_CM_CACHABLE_WA		1
 478#define CONF_CM_UNCACHED		2
 479#define CONF_CM_CACHABLE_NONCOHERENT	3
 480#define CONF_CM_CACHABLE_CE		4
 481#define CONF_CM_CACHABLE_COW		5
 482#define CONF_CM_CACHABLE_CUW		6
 483#define CONF_CM_CACHABLE_ACCELERATED	7
 484#define CONF_CM_CMASK			7
 485#define CONF_BE			(_ULCAST_(1) << 15)
 486
 487/* Bits common to various processors.  */
 488#define CONF_CU			(_ULCAST_(1) <<	 3)
 489#define CONF_DB			(_ULCAST_(1) <<	 4)
 490#define CONF_IB			(_ULCAST_(1) <<	 5)
 491#define CONF_DC			(_ULCAST_(7) <<	 6)
 492#define CONF_IC			(_ULCAST_(7) <<	 9)
 493#define CONF_EB			(_ULCAST_(1) << 13)
 494#define CONF_EM			(_ULCAST_(1) << 14)
 495#define CONF_SM			(_ULCAST_(1) << 16)
 496#define CONF_SC			(_ULCAST_(1) << 17)
 497#define CONF_EW			(_ULCAST_(3) << 18)
 498#define CONF_EP			(_ULCAST_(15)<< 24)
 499#define CONF_EC			(_ULCAST_(7) << 28)
 500#define CONF_CM			(_ULCAST_(1) << 31)
 501
 502/* Bits specific to the R4xx0.	*/
 503#define R4K_CONF_SW		(_ULCAST_(1) << 20)
 504#define R4K_CONF_SS		(_ULCAST_(1) << 21)
 505#define R4K_CONF_SB		(_ULCAST_(3) << 22)
 506
 507/* Bits specific to the R5000.	*/
 508#define R5K_CONF_SE		(_ULCAST_(1) << 12)
 509#define R5K_CONF_SS		(_ULCAST_(3) << 20)
 510
 511/* Bits specific to the RM7000.	 */
 512#define RM7K_CONF_SE		(_ULCAST_(1) <<	 3)
 513#define RM7K_CONF_TE		(_ULCAST_(1) << 12)
 514#define RM7K_CONF_CLK		(_ULCAST_(1) << 16)
 515#define RM7K_CONF_TC		(_ULCAST_(1) << 17)
 516#define RM7K_CONF_SI		(_ULCAST_(3) << 20)
 517#define RM7K_CONF_SC		(_ULCAST_(1) << 31)
 518
 519/* Bits specific to the R10000.	 */
 520#define R10K_CONF_DN		(_ULCAST_(3) <<	 3)
 521#define R10K_CONF_CT		(_ULCAST_(1) <<	 5)
 522#define R10K_CONF_PE		(_ULCAST_(1) <<	 6)
 523#define R10K_CONF_PM		(_ULCAST_(3) <<	 7)
 524#define R10K_CONF_EC		(_ULCAST_(15)<<	 9)
 525#define R10K_CONF_SB		(_ULCAST_(1) << 13)
 526#define R10K_CONF_SK		(_ULCAST_(1) << 14)
 527#define R10K_CONF_SS		(_ULCAST_(7) << 16)
 528#define R10K_CONF_SC		(_ULCAST_(7) << 19)
 529#define R10K_CONF_DC		(_ULCAST_(7) << 26)
 530#define R10K_CONF_IC		(_ULCAST_(7) << 29)
 531
 532/* Bits specific to the VR41xx.	 */
 533#define VR41_CONF_CS		(_ULCAST_(1) << 12)
 534#define VR41_CONF_P4K		(_ULCAST_(1) << 13)
 535#define VR41_CONF_BP		(_ULCAST_(1) << 16)
 536#define VR41_CONF_M16		(_ULCAST_(1) << 20)
 537#define VR41_CONF_AD		(_ULCAST_(1) << 23)
 538
 539/* Bits specific to the R30xx.	*/
 540#define R30XX_CONF_FDM		(_ULCAST_(1) << 19)
 541#define R30XX_CONF_REV		(_ULCAST_(1) << 22)
 542#define R30XX_CONF_AC		(_ULCAST_(1) << 23)
 543#define R30XX_CONF_RF		(_ULCAST_(1) << 24)
 544#define R30XX_CONF_HALT		(_ULCAST_(1) << 25)
 545#define R30XX_CONF_FPINT	(_ULCAST_(7) << 26)
 546#define R30XX_CONF_DBR		(_ULCAST_(1) << 29)
 547#define R30XX_CONF_SB		(_ULCAST_(1) << 30)
 548#define R30XX_CONF_LOCK		(_ULCAST_(1) << 31)
 549
 550/* Bits specific to the TX49.  */
 551#define TX49_CONF_DC		(_ULCAST_(1) << 16)
 552#define TX49_CONF_IC		(_ULCAST_(1) << 17)  /* conflict with CONF_SC */
 553#define TX49_CONF_HALT		(_ULCAST_(1) << 18)
 554#define TX49_CONF_CWFON		(_ULCAST_(1) << 27)
 555
 556/* Bits specific to the MIPS32/64 PRA.	*/
 557#define MIPS_CONF_VI		(_ULCAST_(1) <<  3)
 558#define MIPS_CONF_MT		(_ULCAST_(7) <<	 7)
 559#define MIPS_CONF_MT_TLB	(_ULCAST_(1) <<  7)
 560#define MIPS_CONF_MT_FTLB	(_ULCAST_(4) <<  7)
 561#define MIPS_CONF_AR		(_ULCAST_(7) << 10)
 562#define MIPS_CONF_AT		(_ULCAST_(3) << 13)
 
 
 
 
 
 
 
 
 
 
 
 563#define MIPS_CONF_M		(_ULCAST_(1) << 31)
 564
 565/*
 566 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
 567 */
 568#define MIPS_CONF1_FP		(_ULCAST_(1) <<	 0)
 569#define MIPS_CONF1_EP		(_ULCAST_(1) <<	 1)
 570#define MIPS_CONF1_CA		(_ULCAST_(1) <<	 2)
 571#define MIPS_CONF1_WR		(_ULCAST_(1) <<	 3)
 572#define MIPS_CONF1_PC		(_ULCAST_(1) <<	 4)
 573#define MIPS_CONF1_MD		(_ULCAST_(1) <<	 5)
 574#define MIPS_CONF1_C2		(_ULCAST_(1) <<	 6)
 575#define MIPS_CONF1_DA_SHF	7
 576#define MIPS_CONF1_DA_SZ	3
 577#define MIPS_CONF1_DA		(_ULCAST_(7) <<	 7)
 578#define MIPS_CONF1_DL_SHF	10
 579#define MIPS_CONF1_DL_SZ	3
 580#define MIPS_CONF1_DL		(_ULCAST_(7) << 10)
 581#define MIPS_CONF1_DS_SHF	13
 582#define MIPS_CONF1_DS_SZ	3
 583#define MIPS_CONF1_DS		(_ULCAST_(7) << 13)
 584#define MIPS_CONF1_IA_SHF	16
 585#define MIPS_CONF1_IA_SZ	3
 586#define MIPS_CONF1_IA		(_ULCAST_(7) << 16)
 587#define MIPS_CONF1_IL_SHF	19
 588#define MIPS_CONF1_IL_SZ	3
 589#define MIPS_CONF1_IL		(_ULCAST_(7) << 19)
 590#define MIPS_CONF1_IS_SHF	22
 591#define MIPS_CONF1_IS_SZ	3
 592#define MIPS_CONF1_IS		(_ULCAST_(7) << 22)
 593#define MIPS_CONF1_TLBS_SHIFT   (25)
 594#define MIPS_CONF1_TLBS_SIZE    (6)
 595#define MIPS_CONF1_TLBS         (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
 596
 597#define MIPS_CONF2_SA		(_ULCAST_(15)<<	 0)
 598#define MIPS_CONF2_SL		(_ULCAST_(15)<<	 4)
 599#define MIPS_CONF2_SS		(_ULCAST_(15)<<	 8)
 600#define MIPS_CONF2_SU		(_ULCAST_(15)<< 12)
 601#define MIPS_CONF2_TA		(_ULCAST_(15)<< 16)
 602#define MIPS_CONF2_TL		(_ULCAST_(15)<< 20)
 603#define MIPS_CONF2_TS		(_ULCAST_(15)<< 24)
 604#define MIPS_CONF2_TU		(_ULCAST_(7) << 28)
 605
 606#define MIPS_CONF3_TL		(_ULCAST_(1) <<	 0)
 607#define MIPS_CONF3_SM		(_ULCAST_(1) <<	 1)
 608#define MIPS_CONF3_MT		(_ULCAST_(1) <<	 2)
 609#define MIPS_CONF3_CDMM		(_ULCAST_(1) <<	 3)
 610#define MIPS_CONF3_SP		(_ULCAST_(1) <<	 4)
 611#define MIPS_CONF3_VINT		(_ULCAST_(1) <<	 5)
 612#define MIPS_CONF3_VEIC		(_ULCAST_(1) <<	 6)
 613#define MIPS_CONF3_LPA		(_ULCAST_(1) <<	 7)
 614#define MIPS_CONF3_ITL		(_ULCAST_(1) <<	 8)
 615#define MIPS_CONF3_CTXTC	(_ULCAST_(1) <<	 9)
 616#define MIPS_CONF3_DSP		(_ULCAST_(1) << 10)
 617#define MIPS_CONF3_DSP2P	(_ULCAST_(1) << 11)
 618#define MIPS_CONF3_RXI		(_ULCAST_(1) << 12)
 619#define MIPS_CONF3_ULRI		(_ULCAST_(1) << 13)
 620#define MIPS_CONF3_ISA		(_ULCAST_(3) << 14)
 621#define MIPS_CONF3_ISA_OE	(_ULCAST_(1) << 16)
 622#define MIPS_CONF3_MCU		(_ULCAST_(1) << 17)
 623#define MIPS_CONF3_MMAR		(_ULCAST_(7) << 18)
 624#define MIPS_CONF3_IPLW		(_ULCAST_(3) << 21)
 625#define MIPS_CONF3_VZ		(_ULCAST_(1) << 23)
 626#define MIPS_CONF3_PW		(_ULCAST_(1) << 24)
 627#define MIPS_CONF3_SC		(_ULCAST_(1) << 25)
 628#define MIPS_CONF3_BI		(_ULCAST_(1) << 26)
 629#define MIPS_CONF3_BP		(_ULCAST_(1) << 27)
 630#define MIPS_CONF3_MSA		(_ULCAST_(1) << 28)
 631#define MIPS_CONF3_CMGCR	(_ULCAST_(1) << 29)
 632#define MIPS_CONF3_BPG		(_ULCAST_(1) << 30)
 633
 634#define MIPS_CONF4_MMUSIZEEXT_SHIFT	(0)
 635#define MIPS_CONF4_MMUSIZEEXT	(_ULCAST_(255) << 0)
 636#define MIPS_CONF4_FTLBSETS_SHIFT	(0)
 637#define MIPS_CONF4_FTLBSETS	(_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
 638#define MIPS_CONF4_FTLBWAYS_SHIFT	(4)
 639#define MIPS_CONF4_FTLBWAYS	(_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
 640#define MIPS_CONF4_FTLBPAGESIZE_SHIFT	(8)
 641/* bits 10:8 in FTLB-only configurations */
 642#define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
 643/* bits 12:8 in VTLB-FTLB only configurations */
 644#define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
 645#define MIPS_CONF4_MMUEXTDEF	(_ULCAST_(3) << 14)
 646#define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
 647#define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT	(_ULCAST_(2) << 14)
 648#define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT	(_ULCAST_(3) << 14)
 649#define MIPS_CONF4_KSCREXIST_SHIFT	(16)
 650#define MIPS_CONF4_KSCREXIST	(_ULCAST_(255) << MIPS_CONF4_KSCREXIST_SHIFT)
 651#define MIPS_CONF4_VTLBSIZEEXT_SHIFT	(24)
 652#define MIPS_CONF4_VTLBSIZEEXT	(_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
 653#define MIPS_CONF4_AE		(_ULCAST_(1) << 28)
 654#define MIPS_CONF4_IE		(_ULCAST_(3) << 29)
 655#define MIPS_CONF4_TLBINV	(_ULCAST_(2) << 29)
 656
 657#define MIPS_CONF5_NF		(_ULCAST_(1) << 0)
 658#define MIPS_CONF5_UFR		(_ULCAST_(1) << 2)
 659#define MIPS_CONF5_MRP		(_ULCAST_(1) << 3)
 660#define MIPS_CONF5_LLB		(_ULCAST_(1) << 4)
 661#define MIPS_CONF5_MVH		(_ULCAST_(1) << 5)
 662#define MIPS_CONF5_VP		(_ULCAST_(1) << 7)
 663#define MIPS_CONF5_SBRI		(_ULCAST_(1) << 6)
 664#define MIPS_CONF5_FRE		(_ULCAST_(1) << 8)
 665#define MIPS_CONF5_UFE		(_ULCAST_(1) << 9)
 666#define MIPS_CONF5_CA2		(_ULCAST_(1) << 14)
 
 667#define MIPS_CONF5_CRCP		(_ULCAST_(1) << 18)
 668#define MIPS_CONF5_MSAEN	(_ULCAST_(1) << 27)
 669#define MIPS_CONF5_EVA		(_ULCAST_(1) << 28)
 670#define MIPS_CONF5_CV		(_ULCAST_(1) << 29)
 671#define MIPS_CONF5_K		(_ULCAST_(1) << 30)
 672
 673#define MIPS_CONF6_SYND		(_ULCAST_(1) << 13)
 
 
 
 
 
 
 
 
 
 
 674/* proAptiv FTLB on/off bit */
 675#define MIPS_CONF6_FTLBEN	(_ULCAST_(1) << 15)
 676/* Loongson-3 FTLB on/off bit */
 677#define MIPS_CONF6_FTLBDIS	(_ULCAST_(1) << 22)
 678/* FTLB probability bits */
 679#define MIPS_CONF6_FTLBP_SHIFT	(16)
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 680
 681#define MIPS_CONF7_WII		(_ULCAST_(1) << 31)
 682
 683#define MIPS_CONF7_RPS		(_ULCAST_(1) << 2)
 684
 685#define MIPS_CONF7_IAR		(_ULCAST_(1) << 10)
 686#define MIPS_CONF7_AR		(_ULCAST_(1) << 16)
 687
 
 
 
 
 
 
 
 
 
 
 
 688/* WatchLo* register definitions */
 689#define MIPS_WATCHLO_IRW	(_ULCAST_(0x7) << 0)
 690
 691/* WatchHi* register definitions */
 692#define MIPS_WATCHHI_M		(_ULCAST_(1) << 31)
 693#define MIPS_WATCHHI_G		(_ULCAST_(1) << 30)
 694#define MIPS_WATCHHI_WM		(_ULCAST_(0x3) << 28)
 695#define MIPS_WATCHHI_WM_R_RVA	(_ULCAST_(0) << 28)
 696#define MIPS_WATCHHI_WM_R_GPA	(_ULCAST_(1) << 28)
 697#define MIPS_WATCHHI_WM_G_GVA	(_ULCAST_(2) << 28)
 698#define MIPS_WATCHHI_EAS	(_ULCAST_(0x3) << 24)
 699#define MIPS_WATCHHI_ASID	(_ULCAST_(0xff) << 16)
 700#define MIPS_WATCHHI_MASK	(_ULCAST_(0x1ff) << 3)
 701#define MIPS_WATCHHI_I		(_ULCAST_(1) << 2)
 702#define MIPS_WATCHHI_R		(_ULCAST_(1) << 1)
 703#define MIPS_WATCHHI_W		(_ULCAST_(1) << 0)
 704#define MIPS_WATCHHI_IRW	(_ULCAST_(0x7) << 0)
 705
 706/* PerfCnt control register definitions */
 707#define MIPS_PERFCTRL_EXL	(_ULCAST_(1) << 0)
 708#define MIPS_PERFCTRL_K		(_ULCAST_(1) << 1)
 709#define MIPS_PERFCTRL_S		(_ULCAST_(1) << 2)
 710#define MIPS_PERFCTRL_U		(_ULCAST_(1) << 3)
 711#define MIPS_PERFCTRL_IE	(_ULCAST_(1) << 4)
 712#define MIPS_PERFCTRL_EVENT_S	5
 713#define MIPS_PERFCTRL_EVENT	(_ULCAST_(0x3ff) << MIPS_PERFCTRL_EVENT_S)
 714#define MIPS_PERFCTRL_PCTD	(_ULCAST_(1) << 15)
 715#define MIPS_PERFCTRL_EC	(_ULCAST_(0x3) << 23)
 716#define MIPS_PERFCTRL_EC_R	(_ULCAST_(0) << 23)
 717#define MIPS_PERFCTRL_EC_RI	(_ULCAST_(1) << 23)
 718#define MIPS_PERFCTRL_EC_G	(_ULCAST_(2) << 23)
 719#define MIPS_PERFCTRL_EC_GRI	(_ULCAST_(3) << 23)
 720#define MIPS_PERFCTRL_W		(_ULCAST_(1) << 30)
 721#define MIPS_PERFCTRL_M		(_ULCAST_(1) << 31)
 722
 723/* PerfCnt control register MT extensions used by MIPS cores */
 724#define MIPS_PERFCTRL_VPEID_S	16
 725#define MIPS_PERFCTRL_VPEID	(_ULCAST_(0xf) << MIPS_PERFCTRL_VPEID_S)
 726#define MIPS_PERFCTRL_TCID_S	22
 727#define MIPS_PERFCTRL_TCID	(_ULCAST_(0xff) << MIPS_PERFCTRL_TCID_S)
 728#define MIPS_PERFCTRL_MT_EN	(_ULCAST_(0x3) << 20)
 729#define MIPS_PERFCTRL_MT_EN_ALL	(_ULCAST_(0) << 20)
 730#define MIPS_PERFCTRL_MT_EN_VPE	(_ULCAST_(1) << 20)
 731#define MIPS_PERFCTRL_MT_EN_TC	(_ULCAST_(2) << 20)
 732
 733/* PerfCnt control register MT extensions used by BMIPS5000 */
 734#define BRCM_PERFCTRL_TC	(_ULCAST_(1) << 30)
 735
 736/* PerfCnt control register MT extensions used by Netlogic XLR */
 737#define XLR_PERFCTRL_ALLTHREADS	(_ULCAST_(1) << 13)
 738
 739/* MAAR bit definitions */
 740#define MIPS_MAAR_VH		(_U64CAST_(1) << 63)
 741#define MIPS_MAAR_ADDR		((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)
 742#define MIPS_MAAR_ADDR_SHIFT	12
 743#define MIPS_MAAR_S		(_ULCAST_(1) << 1)
 744#define MIPS_MAAR_VL		(_ULCAST_(1) << 0)
 
 
 
 
 
 
 
 
 745
 746/* MAARI bit definitions */
 747#define MIPS_MAARI_INDEX	(_ULCAST_(0x3f) << 0)
 748
 749/* EBase bit definitions */
 750#define MIPS_EBASE_CPUNUM_SHIFT	0
 751#define MIPS_EBASE_CPUNUM	(_ULCAST_(0x3ff) << 0)
 752#define MIPS_EBASE_WG_SHIFT	11
 753#define MIPS_EBASE_WG		(_ULCAST_(1) << 11)
 754#define MIPS_EBASE_BASE_SHIFT	12
 755#define MIPS_EBASE_BASE		(~_ULCAST_((1 << MIPS_EBASE_BASE_SHIFT) - 1))
 756
 757/* CMGCRBase bit definitions */
 758#define MIPS_CMGCRB_BASE	11
 759#define MIPS_CMGCRF_BASE	(~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
 760
 761/* LLAddr bit definitions */
 762#define MIPS_LLADDR_LLB_SHIFT	0
 763#define MIPS_LLADDR_LLB		(_ULCAST_(1) << MIPS_LLADDR_LLB_SHIFT)
 764
 765/*
 766 * Bits in the MIPS32 Memory Segmentation registers.
 767 */
 768#define MIPS_SEGCFG_PA_SHIFT	9
 769#define MIPS_SEGCFG_PA		(_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
 770#define MIPS_SEGCFG_AM_SHIFT	4
 771#define MIPS_SEGCFG_AM		(_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
 772#define MIPS_SEGCFG_EU_SHIFT	3
 773#define MIPS_SEGCFG_EU		(_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
 774#define MIPS_SEGCFG_C_SHIFT	0
 775#define MIPS_SEGCFG_C		(_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
 776
 777#define MIPS_SEGCFG_UUSK	_ULCAST_(7)
 778#define MIPS_SEGCFG_USK		_ULCAST_(5)
 779#define MIPS_SEGCFG_MUSUK	_ULCAST_(4)
 780#define MIPS_SEGCFG_MUSK	_ULCAST_(3)
 781#define MIPS_SEGCFG_MSK		_ULCAST_(2)
 782#define MIPS_SEGCFG_MK		_ULCAST_(1)
 783#define MIPS_SEGCFG_UK		_ULCAST_(0)
 784
 785#define MIPS_PWFIELD_GDI_SHIFT	24
 786#define MIPS_PWFIELD_GDI_MASK	0x3f000000
 787#define MIPS_PWFIELD_UDI_SHIFT	18
 788#define MIPS_PWFIELD_UDI_MASK	0x00fc0000
 789#define MIPS_PWFIELD_MDI_SHIFT	12
 790#define MIPS_PWFIELD_MDI_MASK	0x0003f000
 791#define MIPS_PWFIELD_PTI_SHIFT	6
 792#define MIPS_PWFIELD_PTI_MASK	0x00000fc0
 793#define MIPS_PWFIELD_PTEI_SHIFT	0
 794#define MIPS_PWFIELD_PTEI_MASK	0x0000003f
 795
 796#define MIPS_PWSIZE_PS_SHIFT	30
 797#define MIPS_PWSIZE_PS_MASK	0x40000000
 798#define MIPS_PWSIZE_GDW_SHIFT	24
 799#define MIPS_PWSIZE_GDW_MASK	0x3f000000
 800#define MIPS_PWSIZE_UDW_SHIFT	18
 801#define MIPS_PWSIZE_UDW_MASK	0x00fc0000
 802#define MIPS_PWSIZE_MDW_SHIFT	12
 803#define MIPS_PWSIZE_MDW_MASK	0x0003f000
 804#define MIPS_PWSIZE_PTW_SHIFT	6
 805#define MIPS_PWSIZE_PTW_MASK	0x00000fc0
 806#define MIPS_PWSIZE_PTEW_SHIFT	0
 807#define MIPS_PWSIZE_PTEW_MASK	0x0000003f
 808
 809#define MIPS_PWCTL_PWEN_SHIFT	31
 810#define MIPS_PWCTL_PWEN_MASK	0x80000000
 811#define MIPS_PWCTL_XK_SHIFT	28
 812#define MIPS_PWCTL_XK_MASK	0x10000000
 813#define MIPS_PWCTL_XS_SHIFT	27
 814#define MIPS_PWCTL_XS_MASK	0x08000000
 815#define MIPS_PWCTL_XU_SHIFT	26
 816#define MIPS_PWCTL_XU_MASK	0x04000000
 817#define MIPS_PWCTL_DPH_SHIFT	7
 818#define MIPS_PWCTL_DPH_MASK	0x00000080
 819#define MIPS_PWCTL_HUGEPG_SHIFT	6
 820#define MIPS_PWCTL_HUGEPG_MASK	0x00000060
 821#define MIPS_PWCTL_PSN_SHIFT	0
 822#define MIPS_PWCTL_PSN_MASK	0x0000003f
 823
 824/* GuestCtl0 fields */
 825#define MIPS_GCTL0_GM_SHIFT	31
 826#define MIPS_GCTL0_GM		(_ULCAST_(1) << MIPS_GCTL0_GM_SHIFT)
 827#define MIPS_GCTL0_RI_SHIFT	30
 828#define MIPS_GCTL0_RI		(_ULCAST_(1) << MIPS_GCTL0_RI_SHIFT)
 829#define MIPS_GCTL0_MC_SHIFT	29
 830#define MIPS_GCTL0_MC		(_ULCAST_(1) << MIPS_GCTL0_MC_SHIFT)
 831#define MIPS_GCTL0_CP0_SHIFT	28
 832#define MIPS_GCTL0_CP0		(_ULCAST_(1) << MIPS_GCTL0_CP0_SHIFT)
 833#define MIPS_GCTL0_AT_SHIFT	26
 834#define MIPS_GCTL0_AT		(_ULCAST_(0x3) << MIPS_GCTL0_AT_SHIFT)
 835#define MIPS_GCTL0_GT_SHIFT	25
 836#define MIPS_GCTL0_GT		(_ULCAST_(1) << MIPS_GCTL0_GT_SHIFT)
 837#define MIPS_GCTL0_CG_SHIFT	24
 838#define MIPS_GCTL0_CG		(_ULCAST_(1) << MIPS_GCTL0_CG_SHIFT)
 839#define MIPS_GCTL0_CF_SHIFT	23
 840#define MIPS_GCTL0_CF		(_ULCAST_(1) << MIPS_GCTL0_CF_SHIFT)
 841#define MIPS_GCTL0_G1_SHIFT	22
 842#define MIPS_GCTL0_G1		(_ULCAST_(1) << MIPS_GCTL0_G1_SHIFT)
 843#define MIPS_GCTL0_G0E_SHIFT	19
 844#define MIPS_GCTL0_G0E		(_ULCAST_(1) << MIPS_GCTL0_G0E_SHIFT)
 845#define MIPS_GCTL0_PT_SHIFT	18
 846#define MIPS_GCTL0_PT		(_ULCAST_(1) << MIPS_GCTL0_PT_SHIFT)
 847#define MIPS_GCTL0_RAD_SHIFT	9
 848#define MIPS_GCTL0_RAD		(_ULCAST_(1) << MIPS_GCTL0_RAD_SHIFT)
 849#define MIPS_GCTL0_DRG_SHIFT	8
 850#define MIPS_GCTL0_DRG		(_ULCAST_(1) << MIPS_GCTL0_DRG_SHIFT)
 851#define MIPS_GCTL0_G2_SHIFT	7
 852#define MIPS_GCTL0_G2		(_ULCAST_(1) << MIPS_GCTL0_G2_SHIFT)
 853#define MIPS_GCTL0_GEXC_SHIFT	2
 854#define MIPS_GCTL0_GEXC		(_ULCAST_(0x1f) << MIPS_GCTL0_GEXC_SHIFT)
 855#define MIPS_GCTL0_SFC2_SHIFT	1
 856#define MIPS_GCTL0_SFC2		(_ULCAST_(1) << MIPS_GCTL0_SFC2_SHIFT)
 857#define MIPS_GCTL0_SFC1_SHIFT	0
 858#define MIPS_GCTL0_SFC1		(_ULCAST_(1) << MIPS_GCTL0_SFC1_SHIFT)
 859
 860/* GuestCtl0.AT Guest address translation control */
 861#define MIPS_GCTL0_AT_ROOT	1  /* Guest MMU under Root control */
 862#define MIPS_GCTL0_AT_GUEST	3  /* Guest MMU under Guest control */
 863
 864/* GuestCtl0.GExcCode Hypervisor exception cause codes */
 865#define MIPS_GCTL0_GEXC_GPSI	0  /* Guest Privileged Sensitive Instruction */
 866#define MIPS_GCTL0_GEXC_GSFC	1  /* Guest Software Field Change */
 867#define MIPS_GCTL0_GEXC_HC	2  /* Hypercall */
 868#define MIPS_GCTL0_GEXC_GRR	3  /* Guest Reserved Instruction Redirect */
 869#define MIPS_GCTL0_GEXC_GVA	8  /* Guest Virtual Address available */
 870#define MIPS_GCTL0_GEXC_GHFC	9  /* Guest Hardware Field Change */
 871#define MIPS_GCTL0_GEXC_GPA	10 /* Guest Physical Address available */
 872
 873/* GuestCtl0Ext fields */
 874#define MIPS_GCTL0EXT_RPW_SHIFT	8
 875#define MIPS_GCTL0EXT_RPW	(_ULCAST_(0x3) << MIPS_GCTL0EXT_RPW_SHIFT)
 876#define MIPS_GCTL0EXT_NCC_SHIFT	6
 877#define MIPS_GCTL0EXT_NCC	(_ULCAST_(0x3) << MIPS_GCTL0EXT_NCC_SHIFT)
 878#define MIPS_GCTL0EXT_CGI_SHIFT	4
 879#define MIPS_GCTL0EXT_CGI	(_ULCAST_(1) << MIPS_GCTL0EXT_CGI_SHIFT)
 880#define MIPS_GCTL0EXT_FCD_SHIFT	3
 881#define MIPS_GCTL0EXT_FCD	(_ULCAST_(1) << MIPS_GCTL0EXT_FCD_SHIFT)
 882#define MIPS_GCTL0EXT_OG_SHIFT	2
 883#define MIPS_GCTL0EXT_OG	(_ULCAST_(1) << MIPS_GCTL0EXT_OG_SHIFT)
 884#define MIPS_GCTL0EXT_BG_SHIFT	1
 885#define MIPS_GCTL0EXT_BG	(_ULCAST_(1) << MIPS_GCTL0EXT_BG_SHIFT)
 886#define MIPS_GCTL0EXT_MG_SHIFT	0
 887#define MIPS_GCTL0EXT_MG	(_ULCAST_(1) << MIPS_GCTL0EXT_MG_SHIFT)
 888
 889/* GuestCtl0Ext.RPW Root page walk configuration */
 890#define MIPS_GCTL0EXT_RPW_BOTH	0  /* Root PW for GPA->RPA and RVA->RPA */
 891#define MIPS_GCTL0EXT_RPW_GPA	2  /* Root PW for GPA->RPA */
 892#define MIPS_GCTL0EXT_RPW_RVA	3  /* Root PW for RVA->RPA */
 893
 894/* GuestCtl0Ext.NCC Nested cache coherency attributes */
 895#define MIPS_GCTL0EXT_NCC_IND	0  /* Guest CCA independent of Root CCA */
 896#define MIPS_GCTL0EXT_NCC_MOD	1  /* Guest CCA modified by Root CCA */
 897
 898/* GuestCtl1 fields */
 899#define MIPS_GCTL1_ID_SHIFT	0
 900#define MIPS_GCTL1_ID_WIDTH	8
 901#define MIPS_GCTL1_ID		(_ULCAST_(0xff) << MIPS_GCTL1_ID_SHIFT)
 902#define MIPS_GCTL1_RID_SHIFT	16
 903#define MIPS_GCTL1_RID_WIDTH	8
 904#define MIPS_GCTL1_RID		(_ULCAST_(0xff) << MIPS_GCTL1_RID_SHIFT)
 905#define MIPS_GCTL1_EID_SHIFT	24
 906#define MIPS_GCTL1_EID_WIDTH	8
 907#define MIPS_GCTL1_EID		(_ULCAST_(0xff) << MIPS_GCTL1_EID_SHIFT)
 908
 909/* GuestID reserved for root context */
 910#define MIPS_GCTL1_ROOT_GUESTID	0
 911
 912/* CDMMBase register bit definitions */
 913#define MIPS_CDMMBASE_SIZE_SHIFT 0
 914#define MIPS_CDMMBASE_SIZE	(_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
 915#define MIPS_CDMMBASE_CI	(_ULCAST_(1) << 9)
 916#define MIPS_CDMMBASE_EN	(_ULCAST_(1) << 10)
 917#define MIPS_CDMMBASE_ADDR_SHIFT 11
 918#define MIPS_CDMMBASE_ADDR_START 15
 919
 920/* RDHWR register numbers */
 921#define MIPS_HWR_CPUNUM		0	/* CPU number */
 922#define MIPS_HWR_SYNCISTEP	1	/* SYNCI step size */
 923#define MIPS_HWR_CC		2	/* Cycle counter */
 924#define MIPS_HWR_CCRES		3	/* Cycle counter resolution */
 925#define MIPS_HWR_ULR		29	/* UserLocal */
 926#define MIPS_HWR_IMPL1		30	/* Implementation dependent */
 927#define MIPS_HWR_IMPL2		31	/* Implementation dependent */
 928
 929/* Bits in HWREna register */
 930#define MIPS_HWRENA_CPUNUM	(_ULCAST_(1) << MIPS_HWR_CPUNUM)
 931#define MIPS_HWRENA_SYNCISTEP	(_ULCAST_(1) << MIPS_HWR_SYNCISTEP)
 932#define MIPS_HWRENA_CC		(_ULCAST_(1) << MIPS_HWR_CC)
 933#define MIPS_HWRENA_CCRES	(_ULCAST_(1) << MIPS_HWR_CCRES)
 934#define MIPS_HWRENA_ULR		(_ULCAST_(1) << MIPS_HWR_ULR)
 935#define MIPS_HWRENA_IMPL1	(_ULCAST_(1) << MIPS_HWR_IMPL1)
 936#define MIPS_HWRENA_IMPL2	(_ULCAST_(1) << MIPS_HWR_IMPL2)
 937
 938/*
 939 * Bitfields in the TX39 family CP0 Configuration Register 3
 940 */
 941#define TX39_CONF_ICS_SHIFT	19
 942#define TX39_CONF_ICS_MASK	0x00380000
 943#define TX39_CONF_ICS_1KB	0x00000000
 944#define TX39_CONF_ICS_2KB	0x00080000
 945#define TX39_CONF_ICS_4KB	0x00100000
 946#define TX39_CONF_ICS_8KB	0x00180000
 947#define TX39_CONF_ICS_16KB	0x00200000
 948
 949#define TX39_CONF_DCS_SHIFT	16
 950#define TX39_CONF_DCS_MASK	0x00070000
 951#define TX39_CONF_DCS_1KB	0x00000000
 952#define TX39_CONF_DCS_2KB	0x00010000
 953#define TX39_CONF_DCS_4KB	0x00020000
 954#define TX39_CONF_DCS_8KB	0x00030000
 955#define TX39_CONF_DCS_16KB	0x00040000
 956
 957#define TX39_CONF_CWFON		0x00004000
 958#define TX39_CONF_WBON		0x00002000
 959#define TX39_CONF_RF_SHIFT	10
 960#define TX39_CONF_RF_MASK	0x00000c00
 961#define TX39_CONF_DOZE		0x00000200
 962#define TX39_CONF_HALT		0x00000100
 963#define TX39_CONF_LOCK		0x00000080
 964#define TX39_CONF_ICE		0x00000020
 965#define TX39_CONF_DCE		0x00000010
 966#define TX39_CONF_IRSIZE_SHIFT	2
 967#define TX39_CONF_IRSIZE_MASK	0x0000000c
 968#define TX39_CONF_DRSIZE_SHIFT	0
 969#define TX39_CONF_DRSIZE_MASK	0x00000003
 970
 971/*
 972 * Interesting Bits in the R10K CP0 Branch Diagnostic Register
 973 */
 974/* Disable Branch Target Address Cache */
 975#define R10K_DIAG_D_BTAC	(_ULCAST_(1) << 27)
 976/* Enable Branch Prediction Global History */
 977#define R10K_DIAG_E_GHIST	(_ULCAST_(1) << 26)
 978/* Disable Branch Return Cache */
 979#define R10K_DIAG_D_BRC		(_ULCAST_(1) << 22)
 980
 
 
 981/* Flush ITLB */
 982#define LOONGSON_DIAG_ITLB	(_ULCAST_(1) << 2)
 983/* Flush DTLB */
 984#define LOONGSON_DIAG_DTLB	(_ULCAST_(1) << 3)
 
 
 985/* Flush VTLB */
 986#define LOONGSON_DIAG_VTLB	(_ULCAST_(1) << 12)
 987/* Flush FTLB */
 988#define LOONGSON_DIAG_FTLB	(_ULCAST_(1) << 13)
 989
 
 
 
 
 
 
 
 990/* CvmCtl register field definitions */
 991#define CVMCTL_IPPCI_SHIFT	7
 992#define CVMCTL_IPPCI		(_U64CAST_(0x7) << CVMCTL_IPPCI_SHIFT)
 993#define CVMCTL_IPTI_SHIFT	4
 994#define CVMCTL_IPTI		(_U64CAST_(0x7) << CVMCTL_IPTI_SHIFT)
 995
 996/* CvmMemCtl2 register field definitions */
 997#define CVMMEMCTL2_INHIBITTS	(_U64CAST_(1) << 17)
 998
 999/* CvmVMConfig register field definitions */
1000#define CVMVMCONF_DGHT		(_U64CAST_(1) << 60)
1001#define CVMVMCONF_MMUSIZEM1_S	12
1002#define CVMVMCONF_MMUSIZEM1	(_U64CAST_(0xff) << CVMVMCONF_MMUSIZEM1_S)
1003#define CVMVMCONF_RMMUSIZEM1_S	0
1004#define CVMVMCONF_RMMUSIZEM1	(_U64CAST_(0xff) << CVMVMCONF_RMMUSIZEM1_S)
1005
 
 
 
 
1006/*
1007 * Coprocessor 1 (FPU) register names
1008 */
1009#define CP1_REVISION	$0
1010#define CP1_UFR		$1
1011#define CP1_UNFR	$4
1012#define CP1_FCCR	$25
1013#define CP1_FEXR	$26
1014#define CP1_FENR	$28
1015#define CP1_STATUS	$31
1016
1017
1018/*
1019 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
1020 */
1021#define MIPS_FPIR_S		(_ULCAST_(1) << 16)
1022#define MIPS_FPIR_D		(_ULCAST_(1) << 17)
1023#define MIPS_FPIR_PS		(_ULCAST_(1) << 18)
1024#define MIPS_FPIR_3D		(_ULCAST_(1) << 19)
1025#define MIPS_FPIR_W		(_ULCAST_(1) << 20)
1026#define MIPS_FPIR_L		(_ULCAST_(1) << 21)
1027#define MIPS_FPIR_F64		(_ULCAST_(1) << 22)
1028#define MIPS_FPIR_HAS2008	(_ULCAST_(1) << 23)
1029#define MIPS_FPIR_UFRP		(_ULCAST_(1) << 28)
1030#define MIPS_FPIR_FREP		(_ULCAST_(1) << 29)
1031
1032/*
1033 * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register.
1034 */
1035#define MIPS_FCCR_CONDX_S	0
1036#define MIPS_FCCR_CONDX		(_ULCAST_(255) << MIPS_FCCR_CONDX_S)
1037#define MIPS_FCCR_COND0_S	0
1038#define MIPS_FCCR_COND0		(_ULCAST_(1) << MIPS_FCCR_COND0_S)
1039#define MIPS_FCCR_COND1_S	1
1040#define MIPS_FCCR_COND1		(_ULCAST_(1) << MIPS_FCCR_COND1_S)
1041#define MIPS_FCCR_COND2_S	2
1042#define MIPS_FCCR_COND2		(_ULCAST_(1) << MIPS_FCCR_COND2_S)
1043#define MIPS_FCCR_COND3_S	3
1044#define MIPS_FCCR_COND3		(_ULCAST_(1) << MIPS_FCCR_COND3_S)
1045#define MIPS_FCCR_COND4_S	4
1046#define MIPS_FCCR_COND4		(_ULCAST_(1) << MIPS_FCCR_COND4_S)
1047#define MIPS_FCCR_COND5_S	5
1048#define MIPS_FCCR_COND5		(_ULCAST_(1) << MIPS_FCCR_COND5_S)
1049#define MIPS_FCCR_COND6_S	6
1050#define MIPS_FCCR_COND6		(_ULCAST_(1) << MIPS_FCCR_COND6_S)
1051#define MIPS_FCCR_COND7_S	7
1052#define MIPS_FCCR_COND7		(_ULCAST_(1) << MIPS_FCCR_COND7_S)
1053
1054/*
1055 * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register.
1056 */
1057#define MIPS_FENR_FS_S		2
1058#define MIPS_FENR_FS		(_ULCAST_(1) << MIPS_FENR_FS_S)
1059
1060/*
1061 * FPU Status Register Values
1062 */
1063#define FPU_CSR_COND_S	23					/* $fcc0 */
1064#define FPU_CSR_COND	(_ULCAST_(1) << FPU_CSR_COND_S)
1065
1066#define FPU_CSR_FS_S	24		/* flush denormalised results to 0 */
1067#define FPU_CSR_FS	(_ULCAST_(1) << FPU_CSR_FS_S)
1068
1069#define FPU_CSR_CONDX_S	25					/* $fcc[7:1] */
1070#define FPU_CSR_CONDX	(_ULCAST_(127) << FPU_CSR_CONDX_S)
1071#define FPU_CSR_COND1_S	25					/* $fcc1 */
1072#define FPU_CSR_COND1	(_ULCAST_(1) << FPU_CSR_COND1_S)
1073#define FPU_CSR_COND2_S	26					/* $fcc2 */
1074#define FPU_CSR_COND2	(_ULCAST_(1) << FPU_CSR_COND2_S)
1075#define FPU_CSR_COND3_S	27					/* $fcc3 */
1076#define FPU_CSR_COND3	(_ULCAST_(1) << FPU_CSR_COND3_S)
1077#define FPU_CSR_COND4_S	28					/* $fcc4 */
1078#define FPU_CSR_COND4	(_ULCAST_(1) << FPU_CSR_COND4_S)
1079#define FPU_CSR_COND5_S	29					/* $fcc5 */
1080#define FPU_CSR_COND5	(_ULCAST_(1) << FPU_CSR_COND5_S)
1081#define FPU_CSR_COND6_S	30					/* $fcc6 */
1082#define FPU_CSR_COND6	(_ULCAST_(1) << FPU_CSR_COND6_S)
1083#define FPU_CSR_COND7_S	31					/* $fcc7 */
1084#define FPU_CSR_COND7	(_ULCAST_(1) << FPU_CSR_COND7_S)
1085
1086/*
1087 * Bits 22:20 of the FPU Status Register will be read as 0,
1088 * and should be written as zero.
 
 
1089 */
1090#define FPU_CSR_RSVD	(_ULCAST_(7) << 20)
1091
 
1092#define FPU_CSR_ABS2008	(_ULCAST_(1) << 19)
1093#define FPU_CSR_NAN2008	(_ULCAST_(1) << 18)
1094
1095/*
1096 * X the exception cause indicator
1097 * E the exception enable
1098 * S the sticky/flag bit
1099*/
1100#define FPU_CSR_ALL_X	0x0003f000
1101#define FPU_CSR_UNI_X	0x00020000
1102#define FPU_CSR_INV_X	0x00010000
1103#define FPU_CSR_DIV_X	0x00008000
1104#define FPU_CSR_OVF_X	0x00004000
1105#define FPU_CSR_UDF_X	0x00002000
1106#define FPU_CSR_INE_X	0x00001000
1107
1108#define FPU_CSR_ALL_E	0x00000f80
1109#define FPU_CSR_INV_E	0x00000800
1110#define FPU_CSR_DIV_E	0x00000400
1111#define FPU_CSR_OVF_E	0x00000200
1112#define FPU_CSR_UDF_E	0x00000100
1113#define FPU_CSR_INE_E	0x00000080
1114
1115#define FPU_CSR_ALL_S	0x0000007c
1116#define FPU_CSR_INV_S	0x00000040
1117#define FPU_CSR_DIV_S	0x00000020
1118#define FPU_CSR_OVF_S	0x00000010
1119#define FPU_CSR_UDF_S	0x00000008
1120#define FPU_CSR_INE_S	0x00000004
1121
1122/* Bits 0 and 1 of FPU Status Register specify the rounding mode */
1123#define FPU_CSR_RM	0x00000003
1124#define FPU_CSR_RN	0x0	/* nearest */
1125#define FPU_CSR_RZ	0x1	/* towards zero */
1126#define FPU_CSR_RU	0x2	/* towards +Infinity */
1127#define FPU_CSR_RD	0x3	/* towards -Infinity */
1128
1129
1130#ifndef __ASSEMBLY__
1131
1132/*
1133 * Macros for handling the ISA mode bit for MIPS16 and microMIPS.
1134 */
1135#if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \
1136    defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
1137#define get_isa16_mode(x)		((x) & 0x1)
1138#define msk_isa16_mode(x)		((x) & ~0x1)
1139#define set_isa16_mode(x)		do { (x) |= 0x1; } while(0)
1140#else
1141#define get_isa16_mode(x)		0
1142#define msk_isa16_mode(x)		(x)
1143#define set_isa16_mode(x)		do { } while(0)
1144#endif
1145
1146/*
1147 * microMIPS instructions can be 16-bit or 32-bit in length. This
1148 * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
1149 */
1150static inline int mm_insn_16bit(u16 insn)
1151{
1152	u16 opcode = (insn >> 10) & 0x7;
1153
1154	return (opcode >= 1 && opcode <= 3) ? 1 : 0;
1155}
1156
1157/*
1158 * Helper macros for generating raw instruction encodings in inline asm.
1159 */
1160#ifdef CONFIG_CPU_MICROMIPS
1161#define _ASM_INSN16_IF_MM(_enc)			\
1162	".insn\n\t"				\
1163	".hword (" #_enc ")\n\t"
1164#define _ASM_INSN32_IF_MM(_enc)			\
1165	".insn\n\t"				\
1166	".hword ((" #_enc ") >> 16)\n\t"	\
1167	".hword ((" #_enc ") & 0xffff)\n\t"
1168#else
1169#define _ASM_INSN_IF_MIPS(_enc)			\
1170	".insn\n\t"				\
1171	".word (" #_enc ")\n\t"
1172#endif
1173
1174#ifndef _ASM_INSN16_IF_MM
1175#define _ASM_INSN16_IF_MM(_enc)
1176#endif
1177#ifndef _ASM_INSN32_IF_MM
1178#define _ASM_INSN32_IF_MM(_enc)
1179#endif
1180#ifndef _ASM_INSN_IF_MIPS
1181#define _ASM_INSN_IF_MIPS(_enc)
1182#endif
1183
1184/*
1185 * parse_r var, r - Helper assembler macro for parsing register names.
1186 *
1187 * This converts the register name in $n form provided in \r to the
1188 * corresponding register number, which is assigned to the variable \var. It is
1189 * needed to allow explicit encoding of instructions in inline assembly where
1190 * registers are chosen by the compiler in $n form, allowing us to avoid using
1191 * fixed register numbers.
1192 *
1193 * It also allows newer instructions (not implemented by the assembler) to be
1194 * transparently implemented using assembler macros, instead of needing separate
1195 * cases depending on toolchain support.
1196 *
1197 * Simple usage example:
1198 * __asm__ __volatile__("parse_r __rt, %0\n\t"
1199 *			".insn\n\t"
1200 *			"# di    %0\n\t"
1201 *			".word   (0x41606000 | (__rt << 16))"
1202 *			: "=r" (status);
1203 */
1204
1205/* Match an individual register number and assign to \var */
1206#define _IFC_REG(n)				\
1207	".ifc	\\r, $" #n "\n\t"		\
1208	"\\var	= " #n "\n\t"			\
1209	".endif\n\t"
1210
1211__asm__(".macro	parse_r var r\n\t"
1212	"\\var	= -1\n\t"
1213	_IFC_REG(0)  _IFC_REG(1)  _IFC_REG(2)  _IFC_REG(3)
1214	_IFC_REG(4)  _IFC_REG(5)  _IFC_REG(6)  _IFC_REG(7)
1215	_IFC_REG(8)  _IFC_REG(9)  _IFC_REG(10) _IFC_REG(11)
1216	_IFC_REG(12) _IFC_REG(13) _IFC_REG(14) _IFC_REG(15)
1217	_IFC_REG(16) _IFC_REG(17) _IFC_REG(18) _IFC_REG(19)
1218	_IFC_REG(20) _IFC_REG(21) _IFC_REG(22) _IFC_REG(23)
1219	_IFC_REG(24) _IFC_REG(25) _IFC_REG(26) _IFC_REG(27)
1220	_IFC_REG(28) _IFC_REG(29) _IFC_REG(30) _IFC_REG(31)
1221	".iflt	\\var\n\t"
1222	".error	\"Unable to parse register name \\r\"\n\t"
1223	".endif\n\t"
1224	".endm");
1225
1226#undef _IFC_REG
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1227
1228/*
1229 * C macros for generating assembler macros for common instruction formats.
1230 *
1231 * The names of the operands can be chosen by the caller, and the encoding of
1232 * register operand \<Rn> is assigned to __<Rn> where it can be accessed from
1233 * the ENC encodings.
1234 */
1235
1236/* Instructions with no operands */
1237#define _ASM_MACRO_0(OP, ENC)						\
1238	__asm__(".macro	" #OP "\n\t"					\
 
 
 
 
 
 
 
 
 
 
 
1239		ENC							\
1240		".endm")
 
1241
1242/* Instructions with 2 register operands */
1243#define _ASM_MACRO_2R(OP, R1, R2, ENC)					\
1244	__asm__(".macro	" #OP " " #R1 ", " #R2 "\n\t"			\
 
1245		"parse_r __" #R1 ", \\" #R1 "\n\t"			\
1246		"parse_r __" #R2 ", \\" #R2 "\n\t"			\
1247		ENC							\
1248		".endm")
 
1249
1250/* Instructions with 3 register operands */
1251#define _ASM_MACRO_3R(OP, R1, R2, R3, ENC)				\
1252	__asm__(".macro	" #OP " " #R1 ", " #R2 ", " #R3 "\n\t"		\
 
1253		"parse_r __" #R1 ", \\" #R1 "\n\t"			\
1254		"parse_r __" #R2 ", \\" #R2 "\n\t"			\
1255		"parse_r __" #R3 ", \\" #R3 "\n\t"			\
1256		ENC							\
1257		".endm")
 
1258
1259/* Instructions with 2 register operands and 1 optional select operand */
1260#define _ASM_MACRO_2R_1S(OP, R1, R2, SEL3, ENC)				\
1261	__asm__(".macro	" #OP " " #R1 ", " #R2 ", " #SEL3 " = 0\n\t"	\
 
1262		"parse_r __" #R1 ", \\" #R1 "\n\t"			\
1263		"parse_r __" #R2 ", \\" #R2 "\n\t"			\
1264		ENC							\
1265		".endm")
 
1266
1267/*
1268 * TLB Invalidate Flush
1269 */
1270static inline void tlbinvf(void)
1271{
1272	__asm__ __volatile__(
1273		".set push\n\t"
1274		".set noreorder\n\t"
1275		"# tlbinvf\n\t"
1276		_ASM_INSN_IF_MIPS(0x42000004)
1277		_ASM_INSN32_IF_MM(0x0000537c)
1278		".set pop");
1279}
1280
1281
1282/*
1283 * Functions to access the R10000 performance counters.	 These are basically
1284 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
1285 * performance counter number encoded into bits 1 ... 5 of the instruction.
1286 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
1287 * disassembler these will look like an access to sel 0 or 1.
1288 */
1289#define read_r10k_perf_cntr(counter)				\
1290({								\
1291	unsigned int __res;					\
1292	__asm__ __volatile__(					\
1293	"mfpc\t%0, %1"						\
1294	: "=r" (__res)						\
1295	: "i" (counter));					\
1296								\
1297	__res;							\
1298})
1299
1300#define write_r10k_perf_cntr(counter,val)			\
1301do {								\
1302	__asm__ __volatile__(					\
1303	"mtpc\t%0, %1"						\
1304	:							\
1305	: "r" (val), "i" (counter));				\
1306} while (0)
1307
1308#define read_r10k_perf_event(counter)				\
1309({								\
1310	unsigned int __res;					\
1311	__asm__ __volatile__(					\
1312	"mfps\t%0, %1"						\
1313	: "=r" (__res)						\
1314	: "i" (counter));					\
1315								\
1316	__res;							\
1317})
1318
1319#define write_r10k_perf_cntl(counter,val)			\
1320do {								\
1321	__asm__ __volatile__(					\
1322	"mtps\t%0, %1"						\
1323	:							\
1324	: "r" (val), "i" (counter));				\
1325} while (0)
1326
1327
1328/*
1329 * Macros to access the system control coprocessor
1330 */
1331
1332#define ___read_32bit_c0_register(source, sel, vol)			\
1333({ unsigned int __res;							\
1334	if (sel == 0)							\
1335		__asm__ vol(						\
1336			"mfc0\t%0, " #source "\n\t"			\
1337			: "=r" (__res));				\
1338	else								\
1339		__asm__ vol(						\
 
1340			".set\tmips32\n\t"				\
1341			"mfc0\t%0, " #source ", " #sel "\n\t"		\
1342			".set\tmips0\n\t"				\
1343			: "=r" (__res));				\
1344	__res;								\
1345})
1346
1347#define ___read_64bit_c0_register(source, sel, vol)			\
1348({ unsigned long long __res;						\
1349	if (sizeof(unsigned long) == 4)					\
1350		__res = __read_64bit_c0_split(source, sel, vol);	\
1351	else if (sel == 0)						\
1352		__asm__ vol(						\
 
1353			".set\tmips3\n\t"				\
1354			"dmfc0\t%0, " #source "\n\t"			\
1355			".set\tmips0"					\
1356			: "=r" (__res));				\
1357	else								\
1358		__asm__ vol(						\
 
1359			".set\tmips64\n\t"				\
1360			"dmfc0\t%0, " #source ", " #sel "\n\t"		\
1361			".set\tmips0"					\
1362			: "=r" (__res));				\
1363	__res;								\
1364})
1365
1366#define __read_32bit_c0_register(source, sel)				\
1367	___read_32bit_c0_register(source, sel, __volatile__)
1368
1369#define __read_const_32bit_c0_register(source, sel)			\
1370	___read_32bit_c0_register(source, sel,)
1371
1372#define __read_64bit_c0_register(source, sel)				\
1373	___read_64bit_c0_register(source, sel, __volatile__)
1374
1375#define __read_const_64bit_c0_register(source, sel)			\
1376	___read_64bit_c0_register(source, sel,)
1377
1378#define __write_32bit_c0_register(register, sel, value)			\
1379do {									\
1380	if (sel == 0)							\
1381		__asm__ __volatile__(					\
1382			"mtc0\t%z0, " #register "\n\t"			\
1383			: : "Jr" ((unsigned int)(value)));		\
1384	else								\
1385		__asm__ __volatile__(					\
 
1386			".set\tmips32\n\t"				\
1387			"mtc0\t%z0, " #register ", " #sel "\n\t"	\
1388			".set\tmips0"					\
1389			: : "Jr" ((unsigned int)(value)));		\
1390} while (0)
1391
1392#define __write_64bit_c0_register(register, sel, value)			\
1393do {									\
1394	if (sizeof(unsigned long) == 4)					\
1395		__write_64bit_c0_split(register, sel, value);		\
1396	else if (sel == 0)						\
1397		__asm__ __volatile__(					\
 
1398			".set\tmips3\n\t"				\
1399			"dmtc0\t%z0, " #register "\n\t"			\
1400			".set\tmips0"					\
1401			: : "Jr" (value));				\
1402	else								\
1403		__asm__ __volatile__(					\
 
1404			".set\tmips64\n\t"				\
1405			"dmtc0\t%z0, " #register ", " #sel "\n\t"	\
1406			".set\tmips0"					\
1407			: : "Jr" (value));				\
1408} while (0)
1409
1410#define __read_ulong_c0_register(reg, sel)				\
1411	((sizeof(unsigned long) == 4) ?					\
1412	(unsigned long) __read_32bit_c0_register(reg, sel) :		\
1413	(unsigned long) __read_64bit_c0_register(reg, sel))
1414
1415#define __read_const_ulong_c0_register(reg, sel)			\
1416	((sizeof(unsigned long) == 4) ?					\
1417	(unsigned long) __read_const_32bit_c0_register(reg, sel) :	\
1418	(unsigned long) __read_const_64bit_c0_register(reg, sel))
1419
1420#define __write_ulong_c0_register(reg, sel, val)			\
1421do {									\
1422	if (sizeof(unsigned long) == 4)					\
1423		__write_32bit_c0_register(reg, sel, val);		\
1424	else								\
1425		__write_64bit_c0_register(reg, sel, val);		\
1426} while (0)
1427
1428/*
1429 * On RM7000/RM9000 these are uses to access cop0 set 1 registers
1430 */
1431#define __read_32bit_c0_ctrl_register(source)				\
1432({ unsigned int __res;							\
1433	__asm__ __volatile__(						\
1434		"cfc0\t%0, " #source "\n\t"				\
1435		: "=r" (__res));					\
1436	__res;								\
1437})
1438
1439#define __write_32bit_c0_ctrl_register(register, value)			\
1440do {									\
1441	__asm__ __volatile__(						\
1442		"ctc0\t%z0, " #register "\n\t"				\
1443		: : "Jr" ((unsigned int)(value)));			\
1444} while (0)
1445
1446/*
1447 * These versions are only needed for systems with more than 38 bits of
1448 * physical address space running the 32-bit kernel.  That's none atm :-)
1449 */
1450#define __read_64bit_c0_split(source, sel, vol)				\
1451({									\
1452	unsigned long long __val;					\
1453	unsigned long __flags;						\
1454									\
1455	local_irq_save(__flags);					\
1456	if (sel == 0)							\
1457		__asm__ vol(						\
 
1458			".set\tmips64\n\t"				\
1459			"dmfc0\t%L0, " #source "\n\t"			\
1460			"dsra\t%M0, %L0, 32\n\t"			\
1461			"sll\t%L0, %L0, 0\n\t"				\
1462			".set\tmips0"					\
1463			: "=r" (__val));				\
1464	else								\
1465		__asm__ vol(						\
 
1466			".set\tmips64\n\t"				\
1467			"dmfc0\t%L0, " #source ", " #sel "\n\t"		\
1468			"dsra\t%M0, %L0, 32\n\t"			\
1469			"sll\t%L0, %L0, 0\n\t"				\
1470			".set\tmips0"					\
1471			: "=r" (__val));				\
1472	local_irq_restore(__flags);					\
1473									\
1474	__val;								\
1475})
1476
1477#define __write_64bit_c0_split(source, sel, val)			\
1478do {									\
1479	unsigned long long __tmp;					\
1480	unsigned long __flags;						\
1481									\
1482	local_irq_save(__flags);					\
1483	if (sel == 0)							\
 
 
 
 
 
 
 
 
1484		__asm__ __volatile__(					\
 
1485			".set\tmips64\n\t"				\
1486			"dsll\t%L0, %L1, 32\n\t"			\
1487			"dsrl\t%L0, %L0, 32\n\t"			\
1488			"dsll\t%M0, %M1, 32\n\t"			\
1489			"or\t%L0, %L0, %M0\n\t"				\
1490			"dmtc0\t%L0, " #source "\n\t"			\
1491			".set\tmips0"					\
1492			: "=&r,r" (__tmp)				\
1493			: "r,0" (val));					\
1494	else								\
1495		__asm__ __volatile__(					\
 
1496			".set\tmips64\n\t"				\
1497			"dsll\t%L0, %L1, 32\n\t"			\
1498			"dsrl\t%L0, %L0, 32\n\t"			\
1499			"dsll\t%M0, %M1, 32\n\t"			\
1500			"or\t%L0, %L0, %M0\n\t"				\
1501			"dmtc0\t%L0, " #source ", " #sel "\n\t"		\
1502			".set\tmips0"					\
1503			: "=&r,r" (__tmp)				\
1504			: "r,0" (val));					\
1505	local_irq_restore(__flags);					\
1506} while (0)
1507
1508#ifndef TOOLCHAIN_SUPPORTS_XPA
1509_ASM_MACRO_2R_1S(mfhc0, rt, rs, sel,
1510	_ASM_INSN_IF_MIPS(0x40400000 | __rt << 16 | __rs << 11 | \\sel)
1511	_ASM_INSN32_IF_MM(0x000000f4 | __rt << 21 | __rs << 16 | \\sel << 11));
1512_ASM_MACRO_2R_1S(mthc0, rt, rd, sel,
1513	_ASM_INSN_IF_MIPS(0x40c00000 | __rt << 16 | __rd << 11 | \\sel)
1514	_ASM_INSN32_IF_MM(0x000002f4 | __rt << 21 | __rd << 16 | \\sel << 11));
1515#define _ASM_SET_XPA ""
 
 
 
1516#else	/* !TOOLCHAIN_SUPPORTS_XPA */
1517#define _ASM_SET_XPA ".set\txpa\n\t"
 
 
 
1518#endif
1519
1520#define __readx_32bit_c0_register(source, sel)				\
1521({									\
1522	unsigned int __res;						\
1523									\
1524	__asm__ __volatile__(						\
1525	"	.set	push					\n"	\
1526	"	.set	mips32r2				\n"	\
1527	_ASM_SET_XPA							\
1528	"	mfhc0	%0, " #source ", %1			\n"	\
 
1529	"	.set	pop					\n"	\
1530	: "=r" (__res)							\
1531	: "i" (sel));							\
1532	__res;								\
1533})
1534
1535#define __writex_32bit_c0_register(register, sel, value)		\
1536do {									\
1537	__asm__ __volatile__(						\
1538	"	.set	push					\n"	\
1539	"	.set	mips32r2				\n"	\
1540	_ASM_SET_XPA							\
1541	"	mthc0	%z0, " #register ", %1			\n"	\
 
1542	"	.set	pop					\n"	\
1543	:								\
1544	: "Jr" (value), "i" (sel));					\
1545} while (0)
1546
1547#define read_c0_index()		__read_32bit_c0_register($0, 0)
1548#define write_c0_index(val)	__write_32bit_c0_register($0, 0, val)
1549
1550#define read_c0_random()	__read_32bit_c0_register($1, 0)
1551#define write_c0_random(val)	__write_32bit_c0_register($1, 0, val)
1552
1553#define read_c0_entrylo0()	__read_ulong_c0_register($2, 0)
1554#define write_c0_entrylo0(val)	__write_ulong_c0_register($2, 0, val)
1555
1556#define readx_c0_entrylo0()	__readx_32bit_c0_register($2, 0)
1557#define writex_c0_entrylo0(val)	__writex_32bit_c0_register($2, 0, val)
1558
1559#define read_c0_entrylo1()	__read_ulong_c0_register($3, 0)
1560#define write_c0_entrylo1(val)	__write_ulong_c0_register($3, 0, val)
1561
1562#define readx_c0_entrylo1()	__readx_32bit_c0_register($3, 0)
1563#define writex_c0_entrylo1(val)	__writex_32bit_c0_register($3, 0, val)
1564
1565#define read_c0_conf()		__read_32bit_c0_register($3, 0)
1566#define write_c0_conf(val)	__write_32bit_c0_register($3, 0, val)
1567
1568#define read_c0_globalnumber()	__read_32bit_c0_register($3, 1)
1569
1570#define read_c0_context()	__read_ulong_c0_register($4, 0)
1571#define write_c0_context(val)	__write_ulong_c0_register($4, 0, val)
1572
1573#define read_c0_contextconfig()		__read_32bit_c0_register($4, 1)
1574#define write_c0_contextconfig(val)	__write_32bit_c0_register($4, 1, val)
1575
1576#define read_c0_userlocal()	__read_ulong_c0_register($4, 2)
1577#define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
1578
1579#define read_c0_xcontextconfig()	__read_ulong_c0_register($4, 3)
1580#define write_c0_xcontextconfig(val)	__write_ulong_c0_register($4, 3, val)
1581
 
 
 
1582#define read_c0_pagemask()	__read_32bit_c0_register($5, 0)
1583#define write_c0_pagemask(val)	__write_32bit_c0_register($5, 0, val)
1584
1585#define read_c0_pagegrain()	__read_32bit_c0_register($5, 1)
1586#define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
1587
1588#define read_c0_wired()		__read_32bit_c0_register($6, 0)
1589#define write_c0_wired(val)	__write_32bit_c0_register($6, 0, val)
1590
1591#define read_c0_info()		__read_32bit_c0_register($7, 0)
1592
1593#define read_c0_cache()		__read_32bit_c0_register($7, 0) /* TX39xx */
1594#define write_c0_cache(val)	__write_32bit_c0_register($7, 0, val)
1595
1596#define read_c0_badvaddr()	__read_ulong_c0_register($8, 0)
1597#define write_c0_badvaddr(val)	__write_ulong_c0_register($8, 0, val)
1598
1599#define read_c0_badinstr()	__read_32bit_c0_register($8, 1)
1600#define read_c0_badinstrp()	__read_32bit_c0_register($8, 2)
1601
1602#define read_c0_count()		__read_32bit_c0_register($9, 0)
1603#define write_c0_count(val)	__write_32bit_c0_register($9, 0, val)
1604
1605#define read_c0_count2()	__read_32bit_c0_register($9, 6) /* pnx8550 */
1606#define write_c0_count2(val)	__write_32bit_c0_register($9, 6, val)
1607
1608#define read_c0_count3()	__read_32bit_c0_register($9, 7) /* pnx8550 */
1609#define write_c0_count3(val)	__write_32bit_c0_register($9, 7, val)
1610
1611#define read_c0_entryhi()	__read_ulong_c0_register($10, 0)
1612#define write_c0_entryhi(val)	__write_ulong_c0_register($10, 0, val)
1613
1614#define read_c0_guestctl1()	__read_32bit_c0_register($10, 4)
1615#define write_c0_guestctl1(val)	__write_32bit_c0_register($10, 4, val)
1616
1617#define read_c0_guestctl2()	__read_32bit_c0_register($10, 5)
1618#define write_c0_guestctl2(val)	__write_32bit_c0_register($10, 5, val)
1619
1620#define read_c0_guestctl3()	__read_32bit_c0_register($10, 6)
1621#define write_c0_guestctl3(val)	__write_32bit_c0_register($10, 6, val)
1622
1623#define read_c0_compare()	__read_32bit_c0_register($11, 0)
1624#define write_c0_compare(val)	__write_32bit_c0_register($11, 0, val)
1625
1626#define read_c0_guestctl0ext()	__read_32bit_c0_register($11, 4)
1627#define write_c0_guestctl0ext(val) __write_32bit_c0_register($11, 4, val)
1628
1629#define read_c0_compare2()	__read_32bit_c0_register($11, 6) /* pnx8550 */
1630#define write_c0_compare2(val)	__write_32bit_c0_register($11, 6, val)
1631
1632#define read_c0_compare3()	__read_32bit_c0_register($11, 7) /* pnx8550 */
1633#define write_c0_compare3(val)	__write_32bit_c0_register($11, 7, val)
1634
1635#define read_c0_status()	__read_32bit_c0_register($12, 0)
1636
1637#define write_c0_status(val)	__write_32bit_c0_register($12, 0, val)
1638
1639#define read_c0_guestctl0()	__read_32bit_c0_register($12, 6)
1640#define write_c0_guestctl0(val)	__write_32bit_c0_register($12, 6, val)
1641
1642#define read_c0_gtoffset()	__read_32bit_c0_register($12, 7)
1643#define write_c0_gtoffset(val)	__write_32bit_c0_register($12, 7, val)
1644
1645#define read_c0_cause()		__read_32bit_c0_register($13, 0)
1646#define write_c0_cause(val)	__write_32bit_c0_register($13, 0, val)
1647
1648#define read_c0_epc()		__read_ulong_c0_register($14, 0)
1649#define write_c0_epc(val)	__write_ulong_c0_register($14, 0, val)
1650
1651#define read_c0_prid()		__read_const_32bit_c0_register($15, 0)
1652
1653#define read_c0_cmgcrbase()	__read_ulong_c0_register($15, 3)
1654
1655#define read_c0_config()	__read_32bit_c0_register($16, 0)
1656#define read_c0_config1()	__read_32bit_c0_register($16, 1)
1657#define read_c0_config2()	__read_32bit_c0_register($16, 2)
1658#define read_c0_config3()	__read_32bit_c0_register($16, 3)
1659#define read_c0_config4()	__read_32bit_c0_register($16, 4)
1660#define read_c0_config5()	__read_32bit_c0_register($16, 5)
1661#define read_c0_config6()	__read_32bit_c0_register($16, 6)
1662#define read_c0_config7()	__read_32bit_c0_register($16, 7)
1663#define write_c0_config(val)	__write_32bit_c0_register($16, 0, val)
1664#define write_c0_config1(val)	__write_32bit_c0_register($16, 1, val)
1665#define write_c0_config2(val)	__write_32bit_c0_register($16, 2, val)
1666#define write_c0_config3(val)	__write_32bit_c0_register($16, 3, val)
1667#define write_c0_config4(val)	__write_32bit_c0_register($16, 4, val)
1668#define write_c0_config5(val)	__write_32bit_c0_register($16, 5, val)
1669#define write_c0_config6(val)	__write_32bit_c0_register($16, 6, val)
1670#define write_c0_config7(val)	__write_32bit_c0_register($16, 7, val)
1671
1672#define read_c0_lladdr()	__read_ulong_c0_register($17, 0)
1673#define write_c0_lladdr(val)	__write_ulong_c0_register($17, 0, val)
1674#define read_c0_maar()		__read_ulong_c0_register($17, 1)
1675#define write_c0_maar(val)	__write_ulong_c0_register($17, 1, val)
 
 
1676#define read_c0_maari()		__read_32bit_c0_register($17, 2)
1677#define write_c0_maari(val)	__write_32bit_c0_register($17, 2, val)
1678
1679/*
1680 * The WatchLo register.  There may be up to 8 of them.
1681 */
1682#define read_c0_watchlo0()	__read_ulong_c0_register($18, 0)
1683#define read_c0_watchlo1()	__read_ulong_c0_register($18, 1)
1684#define read_c0_watchlo2()	__read_ulong_c0_register($18, 2)
1685#define read_c0_watchlo3()	__read_ulong_c0_register($18, 3)
1686#define read_c0_watchlo4()	__read_ulong_c0_register($18, 4)
1687#define read_c0_watchlo5()	__read_ulong_c0_register($18, 5)
1688#define read_c0_watchlo6()	__read_ulong_c0_register($18, 6)
1689#define read_c0_watchlo7()	__read_ulong_c0_register($18, 7)
1690#define write_c0_watchlo0(val)	__write_ulong_c0_register($18, 0, val)
1691#define write_c0_watchlo1(val)	__write_ulong_c0_register($18, 1, val)
1692#define write_c0_watchlo2(val)	__write_ulong_c0_register($18, 2, val)
1693#define write_c0_watchlo3(val)	__write_ulong_c0_register($18, 3, val)
1694#define write_c0_watchlo4(val)	__write_ulong_c0_register($18, 4, val)
1695#define write_c0_watchlo5(val)	__write_ulong_c0_register($18, 5, val)
1696#define write_c0_watchlo6(val)	__write_ulong_c0_register($18, 6, val)
1697#define write_c0_watchlo7(val)	__write_ulong_c0_register($18, 7, val)
1698
1699/*
1700 * The WatchHi register.  There may be up to 8 of them.
1701 */
1702#define read_c0_watchhi0()	__read_32bit_c0_register($19, 0)
1703#define read_c0_watchhi1()	__read_32bit_c0_register($19, 1)
1704#define read_c0_watchhi2()	__read_32bit_c0_register($19, 2)
1705#define read_c0_watchhi3()	__read_32bit_c0_register($19, 3)
1706#define read_c0_watchhi4()	__read_32bit_c0_register($19, 4)
1707#define read_c0_watchhi5()	__read_32bit_c0_register($19, 5)
1708#define read_c0_watchhi6()	__read_32bit_c0_register($19, 6)
1709#define read_c0_watchhi7()	__read_32bit_c0_register($19, 7)
1710
1711#define write_c0_watchhi0(val)	__write_32bit_c0_register($19, 0, val)
1712#define write_c0_watchhi1(val)	__write_32bit_c0_register($19, 1, val)
1713#define write_c0_watchhi2(val)	__write_32bit_c0_register($19, 2, val)
1714#define write_c0_watchhi3(val)	__write_32bit_c0_register($19, 3, val)
1715#define write_c0_watchhi4(val)	__write_32bit_c0_register($19, 4, val)
1716#define write_c0_watchhi5(val)	__write_32bit_c0_register($19, 5, val)
1717#define write_c0_watchhi6(val)	__write_32bit_c0_register($19, 6, val)
1718#define write_c0_watchhi7(val)	__write_32bit_c0_register($19, 7, val)
1719
1720#define read_c0_xcontext()	__read_ulong_c0_register($20, 0)
1721#define write_c0_xcontext(val)	__write_ulong_c0_register($20, 0, val)
1722
1723#define read_c0_intcontrol()	__read_32bit_c0_ctrl_register($20)
1724#define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
1725
1726#define read_c0_framemask()	__read_32bit_c0_register($21, 0)
1727#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
1728
1729#define read_c0_diag()		__read_32bit_c0_register($22, 0)
1730#define write_c0_diag(val)	__write_32bit_c0_register($22, 0, val)
1731
1732/* R10K CP0 Branch Diagnostic register is 64bits wide */
1733#define read_c0_r10k_diag()	__read_64bit_c0_register($22, 0)
1734#define write_c0_r10k_diag(val)	__write_64bit_c0_register($22, 0, val)
1735
1736#define read_c0_diag1()		__read_32bit_c0_register($22, 1)
1737#define write_c0_diag1(val)	__write_32bit_c0_register($22, 1, val)
1738
1739#define read_c0_diag2()		__read_32bit_c0_register($22, 2)
1740#define write_c0_diag2(val)	__write_32bit_c0_register($22, 2, val)
1741
1742#define read_c0_diag3()		__read_32bit_c0_register($22, 3)
1743#define write_c0_diag3(val)	__write_32bit_c0_register($22, 3, val)
1744
1745#define read_c0_diag4()		__read_32bit_c0_register($22, 4)
1746#define write_c0_diag4(val)	__write_32bit_c0_register($22, 4, val)
1747
1748#define read_c0_diag5()		__read_32bit_c0_register($22, 5)
1749#define write_c0_diag5(val)	__write_32bit_c0_register($22, 5, val)
1750
1751#define read_c0_debug()		__read_32bit_c0_register($23, 0)
1752#define write_c0_debug(val)	__write_32bit_c0_register($23, 0, val)
1753
1754#define read_c0_depc()		__read_ulong_c0_register($24, 0)
1755#define write_c0_depc(val)	__write_ulong_c0_register($24, 0, val)
1756
1757/*
1758 * MIPS32 / MIPS64 performance counters
1759 */
1760#define read_c0_perfctrl0()	__read_32bit_c0_register($25, 0)
1761#define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1762#define read_c0_perfcntr0()	__read_32bit_c0_register($25, 1)
1763#define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
1764#define read_c0_perfcntr0_64()	__read_64bit_c0_register($25, 1)
1765#define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
1766#define read_c0_perfctrl1()	__read_32bit_c0_register($25, 2)
1767#define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
1768#define read_c0_perfcntr1()	__read_32bit_c0_register($25, 3)
1769#define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
1770#define read_c0_perfcntr1_64()	__read_64bit_c0_register($25, 3)
1771#define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
1772#define read_c0_perfctrl2()	__read_32bit_c0_register($25, 4)
1773#define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
1774#define read_c0_perfcntr2()	__read_32bit_c0_register($25, 5)
1775#define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
1776#define read_c0_perfcntr2_64()	__read_64bit_c0_register($25, 5)
1777#define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
1778#define read_c0_perfctrl3()	__read_32bit_c0_register($25, 6)
1779#define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
1780#define read_c0_perfcntr3()	__read_32bit_c0_register($25, 7)
1781#define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1782#define read_c0_perfcntr3_64()	__read_64bit_c0_register($25, 7)
1783#define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
1784
1785#define read_c0_ecc()		__read_32bit_c0_register($26, 0)
1786#define write_c0_ecc(val)	__write_32bit_c0_register($26, 0, val)
1787
1788#define read_c0_derraddr0()	__read_ulong_c0_register($26, 1)
1789#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1790
1791#define read_c0_cacheerr()	__read_32bit_c0_register($27, 0)
1792
1793#define read_c0_derraddr1()	__read_ulong_c0_register($27, 1)
1794#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1795
1796#define read_c0_taglo()		__read_32bit_c0_register($28, 0)
1797#define write_c0_taglo(val)	__write_32bit_c0_register($28, 0, val)
1798
1799#define read_c0_dtaglo()	__read_32bit_c0_register($28, 2)
1800#define write_c0_dtaglo(val)	__write_32bit_c0_register($28, 2, val)
1801
1802#define read_c0_ddatalo()	__read_32bit_c0_register($28, 3)
1803#define write_c0_ddatalo(val)	__write_32bit_c0_register($28, 3, val)
1804
1805#define read_c0_staglo()	__read_32bit_c0_register($28, 4)
1806#define write_c0_staglo(val)	__write_32bit_c0_register($28, 4, val)
1807
1808#define read_c0_taghi()		__read_32bit_c0_register($29, 0)
1809#define write_c0_taghi(val)	__write_32bit_c0_register($29, 0, val)
1810
1811#define read_c0_errorepc()	__read_ulong_c0_register($30, 0)
1812#define write_c0_errorepc(val)	__write_ulong_c0_register($30, 0, val)
1813
1814/* MIPSR2 */
1815#define read_c0_hwrena()	__read_32bit_c0_register($7, 0)
1816#define write_c0_hwrena(val)	__write_32bit_c0_register($7, 0, val)
1817
1818#define read_c0_intctl()	__read_32bit_c0_register($12, 1)
1819#define write_c0_intctl(val)	__write_32bit_c0_register($12, 1, val)
1820
1821#define read_c0_srsctl()	__read_32bit_c0_register($12, 2)
1822#define write_c0_srsctl(val)	__write_32bit_c0_register($12, 2, val)
1823
1824#define read_c0_srsmap()	__read_32bit_c0_register($12, 3)
1825#define write_c0_srsmap(val)	__write_32bit_c0_register($12, 3, val)
1826
1827#define read_c0_ebase()		__read_32bit_c0_register($15, 1)
1828#define write_c0_ebase(val)	__write_32bit_c0_register($15, 1, val)
1829
1830#define read_c0_ebase_64()	__read_64bit_c0_register($15, 1)
1831#define write_c0_ebase_64(val)	__write_64bit_c0_register($15, 1, val)
1832
1833#define read_c0_cdmmbase()	__read_ulong_c0_register($15, 2)
1834#define write_c0_cdmmbase(val)	__write_ulong_c0_register($15, 2, val)
1835
1836/* MIPSR3 */
1837#define read_c0_segctl0()	__read_32bit_c0_register($5, 2)
1838#define write_c0_segctl0(val)	__write_32bit_c0_register($5, 2, val)
1839
1840#define read_c0_segctl1()	__read_32bit_c0_register($5, 3)
1841#define write_c0_segctl1(val)	__write_32bit_c0_register($5, 3, val)
1842
1843#define read_c0_segctl2()	__read_32bit_c0_register($5, 4)
1844#define write_c0_segctl2(val)	__write_32bit_c0_register($5, 4, val)
1845
1846/* Hardware Page Table Walker */
1847#define read_c0_pwbase()	__read_ulong_c0_register($5, 5)
1848#define write_c0_pwbase(val)	__write_ulong_c0_register($5, 5, val)
1849
1850#define read_c0_pwfield()	__read_ulong_c0_register($5, 6)
1851#define write_c0_pwfield(val)	__write_ulong_c0_register($5, 6, val)
1852
1853#define read_c0_pwsize()	__read_ulong_c0_register($5, 7)
1854#define write_c0_pwsize(val)	__write_ulong_c0_register($5, 7, val)
1855
1856#define read_c0_pwctl()		__read_32bit_c0_register($6, 6)
1857#define write_c0_pwctl(val)	__write_32bit_c0_register($6, 6, val)
1858
1859#define read_c0_pgd()		__read_64bit_c0_register($9, 7)
1860#define write_c0_pgd(val)	__write_64bit_c0_register($9, 7, val)
1861
1862#define read_c0_kpgd()		__read_64bit_c0_register($31, 7)
1863#define write_c0_kpgd(val)	__write_64bit_c0_register($31, 7, val)
1864
1865/* Cavium OCTEON (cnMIPS) */
1866#define read_c0_cvmcount()	__read_ulong_c0_register($9, 6)
1867#define write_c0_cvmcount(val)	__write_ulong_c0_register($9, 6, val)
1868
1869#define read_c0_cvmctl()	__read_64bit_c0_register($9, 7)
1870#define write_c0_cvmctl(val)	__write_64bit_c0_register($9, 7, val)
1871
1872#define read_c0_cvmmemctl()	__read_64bit_c0_register($11, 7)
1873#define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1874
1875#define read_c0_cvmmemctl2()	__read_64bit_c0_register($16, 6)
1876#define write_c0_cvmmemctl2(val) __write_64bit_c0_register($16, 6, val)
1877
1878#define read_c0_cvmvmconfig()	__read_64bit_c0_register($16, 7)
1879#define write_c0_cvmvmconfig(val) __write_64bit_c0_register($16, 7, val)
1880
1881/*
1882 * The cacheerr registers are not standardized.	 On OCTEON, they are
1883 * 64 bits wide.
1884 */
1885#define read_octeon_c0_icacheerr()	__read_64bit_c0_register($27, 0)
1886#define write_octeon_c0_icacheerr(val)	__write_64bit_c0_register($27, 0, val)
1887
1888#define read_octeon_c0_dcacheerr()	__read_64bit_c0_register($27, 1)
1889#define write_octeon_c0_dcacheerr(val)	__write_64bit_c0_register($27, 1, val)
1890
1891/* BMIPS3300 */
1892#define read_c0_brcm_config_0()		__read_32bit_c0_register($22, 0)
1893#define write_c0_brcm_config_0(val)	__write_32bit_c0_register($22, 0, val)
1894
1895#define read_c0_brcm_bus_pll()		__read_32bit_c0_register($22, 4)
1896#define write_c0_brcm_bus_pll(val)	__write_32bit_c0_register($22, 4, val)
1897
1898#define read_c0_brcm_reset()		__read_32bit_c0_register($22, 5)
1899#define write_c0_brcm_reset(val)	__write_32bit_c0_register($22, 5, val)
1900
1901/* BMIPS43xx */
1902#define read_c0_brcm_cmt_intr()		__read_32bit_c0_register($22, 1)
1903#define write_c0_brcm_cmt_intr(val)	__write_32bit_c0_register($22, 1, val)
1904
1905#define read_c0_brcm_cmt_ctrl()		__read_32bit_c0_register($22, 2)
1906#define write_c0_brcm_cmt_ctrl(val)	__write_32bit_c0_register($22, 2, val)
1907
1908#define read_c0_brcm_cmt_local()	__read_32bit_c0_register($22, 3)
1909#define write_c0_brcm_cmt_local(val)	__write_32bit_c0_register($22, 3, val)
1910
1911#define read_c0_brcm_config_1()		__read_32bit_c0_register($22, 5)
1912#define write_c0_brcm_config_1(val)	__write_32bit_c0_register($22, 5, val)
1913
1914#define read_c0_brcm_cbr()		__read_32bit_c0_register($22, 6)
1915#define write_c0_brcm_cbr(val)		__write_32bit_c0_register($22, 6, val)
1916
1917/* BMIPS5000 */
1918#define read_c0_brcm_config()		__read_32bit_c0_register($22, 0)
1919#define write_c0_brcm_config(val)	__write_32bit_c0_register($22, 0, val)
1920
1921#define read_c0_brcm_mode()		__read_32bit_c0_register($22, 1)
1922#define write_c0_brcm_mode(val)		__write_32bit_c0_register($22, 1, val)
1923
1924#define read_c0_brcm_action()		__read_32bit_c0_register($22, 2)
1925#define write_c0_brcm_action(val)	__write_32bit_c0_register($22, 2, val)
1926
1927#define read_c0_brcm_edsp()		__read_32bit_c0_register($22, 3)
1928#define write_c0_brcm_edsp(val)		__write_32bit_c0_register($22, 3, val)
1929
1930#define read_c0_brcm_bootvec()		__read_32bit_c0_register($22, 4)
1931#define write_c0_brcm_bootvec(val)	__write_32bit_c0_register($22, 4, val)
1932
1933#define read_c0_brcm_sleepcount()	__read_32bit_c0_register($22, 7)
1934#define write_c0_brcm_sleepcount(val)	__write_32bit_c0_register($22, 7, val)
1935
 
 
 
1936/*
1937 * Macros to access the guest system control coprocessor
1938 */
1939
1940#ifndef TOOLCHAIN_SUPPORTS_VIRT
1941_ASM_MACRO_2R_1S(mfgc0, rt, rs, sel,
1942	_ASM_INSN_IF_MIPS(0x40600000 | __rt << 16 | __rs << 11 | \\sel)
1943	_ASM_INSN32_IF_MM(0x000004fc | __rt << 21 | __rs << 16 | \\sel << 11));
1944_ASM_MACRO_2R_1S(dmfgc0, rt, rs, sel,
1945	_ASM_INSN_IF_MIPS(0x40600100 | __rt << 16 | __rs << 11 | \\sel)
1946	_ASM_INSN32_IF_MM(0x580004fc | __rt << 21 | __rs << 16 | \\sel << 11));
1947_ASM_MACRO_2R_1S(mtgc0, rt, rd, sel,
1948	_ASM_INSN_IF_MIPS(0x40600200 | __rt << 16 | __rd << 11 | \\sel)
1949	_ASM_INSN32_IF_MM(0x000006fc | __rt << 21 | __rd << 16 | \\sel << 11));
1950_ASM_MACRO_2R_1S(dmtgc0, rt, rd, sel,
1951	_ASM_INSN_IF_MIPS(0x40600300 | __rt << 16 | __rd << 11 | \\sel)
1952	_ASM_INSN32_IF_MM(0x580006fc | __rt << 21 | __rd << 16 | \\sel << 11));
1953_ASM_MACRO_0(tlbgp,    _ASM_INSN_IF_MIPS(0x42000010)
1954		       _ASM_INSN32_IF_MM(0x0000017c));
1955_ASM_MACRO_0(tlbgr,    _ASM_INSN_IF_MIPS(0x42000009)
1956		       _ASM_INSN32_IF_MM(0x0000117c));
1957_ASM_MACRO_0(tlbgwi,   _ASM_INSN_IF_MIPS(0x4200000a)
1958		       _ASM_INSN32_IF_MM(0x0000217c));
1959_ASM_MACRO_0(tlbgwr,   _ASM_INSN_IF_MIPS(0x4200000e)
1960		       _ASM_INSN32_IF_MM(0x0000317c));
1961_ASM_MACRO_0(tlbginvf, _ASM_INSN_IF_MIPS(0x4200000c)
1962		       _ASM_INSN32_IF_MM(0x0000517c));
1963#define _ASM_SET_VIRT ""
 
 
 
 
 
 
 
 
 
 
 
 
 
1964#else	/* !TOOLCHAIN_SUPPORTS_VIRT */
1965#define _ASM_SET_VIRT ".set\tvirt\n\t"
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1966#endif
1967
1968#define __read_32bit_gc0_register(source, sel)				\
1969({ int __res;								\
1970	__asm__ __volatile__(						\
1971		".set\tpush\n\t"					\
1972		".set\tmips32r2\n\t"					\
1973		_ASM_SET_VIRT						\
1974		"mfgc0\t%0, " #source ", %1\n\t"			\
 
1975		".set\tpop"						\
1976		: "=r" (__res)						\
1977		: "i" (sel));						\
1978	__res;								\
1979})
1980
1981#define __read_64bit_gc0_register(source, sel)				\
1982({ unsigned long long __res;						\
1983	__asm__ __volatile__(						\
1984		".set\tpush\n\t"					\
1985		".set\tmips64r2\n\t"					\
1986		_ASM_SET_VIRT						\
1987		"dmfgc0\t%0, " #source ", %1\n\t"			\
 
1988		".set\tpop"						\
1989		: "=r" (__res)						\
1990		: "i" (sel));						\
1991	__res;								\
1992})
1993
1994#define __write_32bit_gc0_register(register, sel, value)		\
1995do {									\
1996	__asm__ __volatile__(						\
1997		".set\tpush\n\t"					\
1998		".set\tmips32r2\n\t"					\
1999		_ASM_SET_VIRT						\
2000		"mtgc0\t%z0, " #register ", %1\n\t"			\
 
2001		".set\tpop"						\
2002		: : "Jr" ((unsigned int)(value)),			\
2003		    "i" (sel));						\
2004} while (0)
2005
2006#define __write_64bit_gc0_register(register, sel, value)		\
2007do {									\
2008	__asm__ __volatile__(						\
2009		".set\tpush\n\t"					\
2010		".set\tmips64r2\n\t"					\
2011		_ASM_SET_VIRT						\
2012		"dmtgc0\t%z0, " #register ", %1\n\t"			\
 
2013		".set\tpop"						\
2014		: : "Jr" (value),					\
2015		    "i" (sel));						\
2016} while (0)
2017
2018#define __read_ulong_gc0_register(reg, sel)				\
2019	((sizeof(unsigned long) == 4) ?					\
2020	(unsigned long) __read_32bit_gc0_register(reg, sel) :		\
2021	(unsigned long) __read_64bit_gc0_register(reg, sel))
2022
2023#define __write_ulong_gc0_register(reg, sel, val)			\
2024do {									\
2025	if (sizeof(unsigned long) == 4)					\
2026		__write_32bit_gc0_register(reg, sel, val);		\
2027	else								\
2028		__write_64bit_gc0_register(reg, sel, val);		\
2029} while (0)
2030
2031#define read_gc0_index()		__read_32bit_gc0_register($0, 0)
2032#define write_gc0_index(val)		__write_32bit_gc0_register($0, 0, val)
2033
2034#define read_gc0_entrylo0()		__read_ulong_gc0_register($2, 0)
2035#define write_gc0_entrylo0(val)		__write_ulong_gc0_register($2, 0, val)
2036
2037#define read_gc0_entrylo1()		__read_ulong_gc0_register($3, 0)
2038#define write_gc0_entrylo1(val)		__write_ulong_gc0_register($3, 0, val)
2039
2040#define read_gc0_context()		__read_ulong_gc0_register($4, 0)
2041#define write_gc0_context(val)		__write_ulong_gc0_register($4, 0, val)
2042
2043#define read_gc0_contextconfig()	__read_32bit_gc0_register($4, 1)
2044#define write_gc0_contextconfig(val)	__write_32bit_gc0_register($4, 1, val)
2045
2046#define read_gc0_userlocal()		__read_ulong_gc0_register($4, 2)
2047#define write_gc0_userlocal(val)	__write_ulong_gc0_register($4, 2, val)
2048
2049#define read_gc0_xcontextconfig()	__read_ulong_gc0_register($4, 3)
2050#define write_gc0_xcontextconfig(val)	__write_ulong_gc0_register($4, 3, val)
2051
2052#define read_gc0_pagemask()		__read_32bit_gc0_register($5, 0)
2053#define write_gc0_pagemask(val)		__write_32bit_gc0_register($5, 0, val)
2054
2055#define read_gc0_pagegrain()		__read_32bit_gc0_register($5, 1)
2056#define write_gc0_pagegrain(val)	__write_32bit_gc0_register($5, 1, val)
2057
2058#define read_gc0_segctl0()		__read_ulong_gc0_register($5, 2)
2059#define write_gc0_segctl0(val)		__write_ulong_gc0_register($5, 2, val)
2060
2061#define read_gc0_segctl1()		__read_ulong_gc0_register($5, 3)
2062#define write_gc0_segctl1(val)		__write_ulong_gc0_register($5, 3, val)
2063
2064#define read_gc0_segctl2()		__read_ulong_gc0_register($5, 4)
2065#define write_gc0_segctl2(val)		__write_ulong_gc0_register($5, 4, val)
2066
2067#define read_gc0_pwbase()		__read_ulong_gc0_register($5, 5)
2068#define write_gc0_pwbase(val)		__write_ulong_gc0_register($5, 5, val)
2069
2070#define read_gc0_pwfield()		__read_ulong_gc0_register($5, 6)
2071#define write_gc0_pwfield(val)		__write_ulong_gc0_register($5, 6, val)
2072
2073#define read_gc0_pwsize()		__read_ulong_gc0_register($5, 7)
2074#define write_gc0_pwsize(val)		__write_ulong_gc0_register($5, 7, val)
2075
2076#define read_gc0_wired()		__read_32bit_gc0_register($6, 0)
2077#define write_gc0_wired(val)		__write_32bit_gc0_register($6, 0, val)
2078
2079#define read_gc0_pwctl()		__read_32bit_gc0_register($6, 6)
2080#define write_gc0_pwctl(val)		__write_32bit_gc0_register($6, 6, val)
2081
2082#define read_gc0_hwrena()		__read_32bit_gc0_register($7, 0)
2083#define write_gc0_hwrena(val)		__write_32bit_gc0_register($7, 0, val)
2084
2085#define read_gc0_badvaddr()		__read_ulong_gc0_register($8, 0)
2086#define write_gc0_badvaddr(val)		__write_ulong_gc0_register($8, 0, val)
2087
2088#define read_gc0_badinstr()		__read_32bit_gc0_register($8, 1)
2089#define write_gc0_badinstr(val)		__write_32bit_gc0_register($8, 1, val)
2090
2091#define read_gc0_badinstrp()		__read_32bit_gc0_register($8, 2)
2092#define write_gc0_badinstrp(val)	__write_32bit_gc0_register($8, 2, val)
2093
2094#define read_gc0_count()		__read_32bit_gc0_register($9, 0)
2095
2096#define read_gc0_entryhi()		__read_ulong_gc0_register($10, 0)
2097#define write_gc0_entryhi(val)		__write_ulong_gc0_register($10, 0, val)
2098
2099#define read_gc0_compare()		__read_32bit_gc0_register($11, 0)
2100#define write_gc0_compare(val)		__write_32bit_gc0_register($11, 0, val)
2101
2102#define read_gc0_status()		__read_32bit_gc0_register($12, 0)
2103#define write_gc0_status(val)		__write_32bit_gc0_register($12, 0, val)
2104
2105#define read_gc0_intctl()		__read_32bit_gc0_register($12, 1)
2106#define write_gc0_intctl(val)		__write_32bit_gc0_register($12, 1, val)
2107
2108#define read_gc0_cause()		__read_32bit_gc0_register($13, 0)
2109#define write_gc0_cause(val)		__write_32bit_gc0_register($13, 0, val)
2110
2111#define read_gc0_epc()			__read_ulong_gc0_register($14, 0)
2112#define write_gc0_epc(val)		__write_ulong_gc0_register($14, 0, val)
2113
2114#define read_gc0_prid()			__read_32bit_gc0_register($15, 0)
2115
2116#define read_gc0_ebase()		__read_32bit_gc0_register($15, 1)
2117#define write_gc0_ebase(val)		__write_32bit_gc0_register($15, 1, val)
2118
2119#define read_gc0_ebase_64()		__read_64bit_gc0_register($15, 1)
2120#define write_gc0_ebase_64(val)		__write_64bit_gc0_register($15, 1, val)
2121
2122#define read_gc0_config()		__read_32bit_gc0_register($16, 0)
2123#define read_gc0_config1()		__read_32bit_gc0_register($16, 1)
2124#define read_gc0_config2()		__read_32bit_gc0_register($16, 2)
2125#define read_gc0_config3()		__read_32bit_gc0_register($16, 3)
2126#define read_gc0_config4()		__read_32bit_gc0_register($16, 4)
2127#define read_gc0_config5()		__read_32bit_gc0_register($16, 5)
2128#define read_gc0_config6()		__read_32bit_gc0_register($16, 6)
2129#define read_gc0_config7()		__read_32bit_gc0_register($16, 7)
2130#define write_gc0_config(val)		__write_32bit_gc0_register($16, 0, val)
2131#define write_gc0_config1(val)		__write_32bit_gc0_register($16, 1, val)
2132#define write_gc0_config2(val)		__write_32bit_gc0_register($16, 2, val)
2133#define write_gc0_config3(val)		__write_32bit_gc0_register($16, 3, val)
2134#define write_gc0_config4(val)		__write_32bit_gc0_register($16, 4, val)
2135#define write_gc0_config5(val)		__write_32bit_gc0_register($16, 5, val)
2136#define write_gc0_config6(val)		__write_32bit_gc0_register($16, 6, val)
2137#define write_gc0_config7(val)		__write_32bit_gc0_register($16, 7, val)
2138
2139#define read_gc0_lladdr()		__read_ulong_gc0_register($17, 0)
2140#define write_gc0_lladdr(val)		__write_ulong_gc0_register($17, 0, val)
2141
2142#define read_gc0_watchlo0()		__read_ulong_gc0_register($18, 0)
2143#define read_gc0_watchlo1()		__read_ulong_gc0_register($18, 1)
2144#define read_gc0_watchlo2()		__read_ulong_gc0_register($18, 2)
2145#define read_gc0_watchlo3()		__read_ulong_gc0_register($18, 3)
2146#define read_gc0_watchlo4()		__read_ulong_gc0_register($18, 4)
2147#define read_gc0_watchlo5()		__read_ulong_gc0_register($18, 5)
2148#define read_gc0_watchlo6()		__read_ulong_gc0_register($18, 6)
2149#define read_gc0_watchlo7()		__read_ulong_gc0_register($18, 7)
2150#define write_gc0_watchlo0(val)		__write_ulong_gc0_register($18, 0, val)
2151#define write_gc0_watchlo1(val)		__write_ulong_gc0_register($18, 1, val)
2152#define write_gc0_watchlo2(val)		__write_ulong_gc0_register($18, 2, val)
2153#define write_gc0_watchlo3(val)		__write_ulong_gc0_register($18, 3, val)
2154#define write_gc0_watchlo4(val)		__write_ulong_gc0_register($18, 4, val)
2155#define write_gc0_watchlo5(val)		__write_ulong_gc0_register($18, 5, val)
2156#define write_gc0_watchlo6(val)		__write_ulong_gc0_register($18, 6, val)
2157#define write_gc0_watchlo7(val)		__write_ulong_gc0_register($18, 7, val)
2158
2159#define read_gc0_watchhi0()		__read_32bit_gc0_register($19, 0)
2160#define read_gc0_watchhi1()		__read_32bit_gc0_register($19, 1)
2161#define read_gc0_watchhi2()		__read_32bit_gc0_register($19, 2)
2162#define read_gc0_watchhi3()		__read_32bit_gc0_register($19, 3)
2163#define read_gc0_watchhi4()		__read_32bit_gc0_register($19, 4)
2164#define read_gc0_watchhi5()		__read_32bit_gc0_register($19, 5)
2165#define read_gc0_watchhi6()		__read_32bit_gc0_register($19, 6)
2166#define read_gc0_watchhi7()		__read_32bit_gc0_register($19, 7)
2167#define write_gc0_watchhi0(val)		__write_32bit_gc0_register($19, 0, val)
2168#define write_gc0_watchhi1(val)		__write_32bit_gc0_register($19, 1, val)
2169#define write_gc0_watchhi2(val)		__write_32bit_gc0_register($19, 2, val)
2170#define write_gc0_watchhi3(val)		__write_32bit_gc0_register($19, 3, val)
2171#define write_gc0_watchhi4(val)		__write_32bit_gc0_register($19, 4, val)
2172#define write_gc0_watchhi5(val)		__write_32bit_gc0_register($19, 5, val)
2173#define write_gc0_watchhi6(val)		__write_32bit_gc0_register($19, 6, val)
2174#define write_gc0_watchhi7(val)		__write_32bit_gc0_register($19, 7, val)
2175
2176#define read_gc0_xcontext()		__read_ulong_gc0_register($20, 0)
2177#define write_gc0_xcontext(val)		__write_ulong_gc0_register($20, 0, val)
2178
2179#define read_gc0_perfctrl0()		__read_32bit_gc0_register($25, 0)
2180#define write_gc0_perfctrl0(val)	__write_32bit_gc0_register($25, 0, val)
2181#define read_gc0_perfcntr0()		__read_32bit_gc0_register($25, 1)
2182#define write_gc0_perfcntr0(val)	__write_32bit_gc0_register($25, 1, val)
2183#define read_gc0_perfcntr0_64()		__read_64bit_gc0_register($25, 1)
2184#define write_gc0_perfcntr0_64(val)	__write_64bit_gc0_register($25, 1, val)
2185#define read_gc0_perfctrl1()		__read_32bit_gc0_register($25, 2)
2186#define write_gc0_perfctrl1(val)	__write_32bit_gc0_register($25, 2, val)
2187#define read_gc0_perfcntr1()		__read_32bit_gc0_register($25, 3)
2188#define write_gc0_perfcntr1(val)	__write_32bit_gc0_register($25, 3, val)
2189#define read_gc0_perfcntr1_64()		__read_64bit_gc0_register($25, 3)
2190#define write_gc0_perfcntr1_64(val)	__write_64bit_gc0_register($25, 3, val)
2191#define read_gc0_perfctrl2()		__read_32bit_gc0_register($25, 4)
2192#define write_gc0_perfctrl2(val)	__write_32bit_gc0_register($25, 4, val)
2193#define read_gc0_perfcntr2()		__read_32bit_gc0_register($25, 5)
2194#define write_gc0_perfcntr2(val)	__write_32bit_gc0_register($25, 5, val)
2195#define read_gc0_perfcntr2_64()		__read_64bit_gc0_register($25, 5)
2196#define write_gc0_perfcntr2_64(val)	__write_64bit_gc0_register($25, 5, val)
2197#define read_gc0_perfctrl3()		__read_32bit_gc0_register($25, 6)
2198#define write_gc0_perfctrl3(val)	__write_32bit_gc0_register($25, 6, val)
2199#define read_gc0_perfcntr3()		__read_32bit_gc0_register($25, 7)
2200#define write_gc0_perfcntr3(val)	__write_32bit_gc0_register($25, 7, val)
2201#define read_gc0_perfcntr3_64()		__read_64bit_gc0_register($25, 7)
2202#define write_gc0_perfcntr3_64(val)	__write_64bit_gc0_register($25, 7, val)
2203
2204#define read_gc0_errorepc()		__read_ulong_gc0_register($30, 0)
2205#define write_gc0_errorepc(val)		__write_ulong_gc0_register($30, 0, val)
2206
2207#define read_gc0_kscratch1()		__read_ulong_gc0_register($31, 2)
2208#define read_gc0_kscratch2()		__read_ulong_gc0_register($31, 3)
2209#define read_gc0_kscratch3()		__read_ulong_gc0_register($31, 4)
2210#define read_gc0_kscratch4()		__read_ulong_gc0_register($31, 5)
2211#define read_gc0_kscratch5()		__read_ulong_gc0_register($31, 6)
2212#define read_gc0_kscratch6()		__read_ulong_gc0_register($31, 7)
2213#define write_gc0_kscratch1(val)	__write_ulong_gc0_register($31, 2, val)
2214#define write_gc0_kscratch2(val)	__write_ulong_gc0_register($31, 3, val)
2215#define write_gc0_kscratch3(val)	__write_ulong_gc0_register($31, 4, val)
2216#define write_gc0_kscratch4(val)	__write_ulong_gc0_register($31, 5, val)
2217#define write_gc0_kscratch5(val)	__write_ulong_gc0_register($31, 6, val)
2218#define write_gc0_kscratch6(val)	__write_ulong_gc0_register($31, 7, val)
2219
2220/* Cavium OCTEON (cnMIPS) */
2221#define read_gc0_cvmcount()		__read_ulong_gc0_register($9, 6)
2222#define write_gc0_cvmcount(val)		__write_ulong_gc0_register($9, 6, val)
2223
2224#define read_gc0_cvmctl()		__read_64bit_gc0_register($9, 7)
2225#define write_gc0_cvmctl(val)		__write_64bit_gc0_register($9, 7, val)
2226
2227#define read_gc0_cvmmemctl()		__read_64bit_gc0_register($11, 7)
2228#define write_gc0_cvmmemctl(val)	__write_64bit_gc0_register($11, 7, val)
2229
2230#define read_gc0_cvmmemctl2()		__read_64bit_gc0_register($16, 6)
2231#define write_gc0_cvmmemctl2(val)	__write_64bit_gc0_register($16, 6, val)
2232
2233/*
2234 * Macros to access the floating point coprocessor control registers
2235 */
2236#define _read_32bit_cp1_register(source, gas_hardfloat)			\
2237({									\
2238	unsigned int __res;						\
2239									\
2240	__asm__ __volatile__(						\
2241	"	.set	push					\n"	\
2242	"	.set	reorder					\n"	\
2243	"	# gas fails to assemble cfc1 for some archs,	\n"	\
2244	"	# like Octeon.					\n"	\
2245	"	.set	mips1					\n"	\
2246	"	"STR(gas_hardfloat)"				\n"	\
2247	"	cfc1	%0,"STR(source)"			\n"	\
2248	"	.set	pop					\n"	\
2249	: "=r" (__res));						\
2250	__res;								\
2251})
2252
2253#define _write_32bit_cp1_register(dest, val, gas_hardfloat)		\
2254do {									\
2255	__asm__ __volatile__(						\
2256	"	.set	push					\n"	\
2257	"	.set	reorder					\n"	\
2258	"	"STR(gas_hardfloat)"				\n"	\
2259	"	ctc1	%0,"STR(dest)"				\n"	\
2260	"	.set	pop					\n"	\
2261	: : "r" (val));							\
2262} while (0)
2263
2264#ifdef GAS_HAS_SET_HARDFLOAT
2265#define read_32bit_cp1_register(source)					\
2266	_read_32bit_cp1_register(source, .set hardfloat)
2267#define write_32bit_cp1_register(dest, val)				\
2268	_write_32bit_cp1_register(dest, val, .set hardfloat)
2269#else
2270#define read_32bit_cp1_register(source)					\
2271	_read_32bit_cp1_register(source, )
2272#define write_32bit_cp1_register(dest, val)				\
2273	_write_32bit_cp1_register(dest, val, )
2274#endif
2275
2276#ifdef HAVE_AS_DSP
2277#define rddsp(mask)							\
2278({									\
2279	unsigned int __dspctl;						\
2280									\
2281	__asm__ __volatile__(						\
2282	"	.set push					\n"	\
 
2283	"	.set dsp					\n"	\
2284	"	rddsp	%0, %x1					\n"	\
2285	"	.set pop					\n"	\
2286	: "=r" (__dspctl)						\
2287	: "i" (mask));							\
2288	__dspctl;							\
2289})
2290
2291#define wrdsp(val, mask)						\
2292do {									\
2293	__asm__ __volatile__(						\
2294	"	.set push					\n"	\
 
2295	"	.set dsp					\n"	\
2296	"	wrdsp	%0, %x1					\n"	\
2297	"	.set pop					\n"	\
2298	:								\
2299	: "r" (val), "i" (mask));					\
2300} while (0)
2301
2302#define mflo0()								\
2303({									\
2304	long mflo0;							\
2305	__asm__(							\
2306	"	.set push					\n"	\
 
2307	"	.set dsp					\n"	\
2308	"	mflo %0, $ac0					\n"	\
2309	"	.set pop					\n" 	\
2310	: "=r" (mflo0)); 						\
2311	mflo0;								\
2312})
2313
2314#define mflo1()								\
2315({									\
2316	long mflo1;							\
2317	__asm__(							\
2318	"	.set push					\n"	\
 
2319	"	.set dsp					\n"	\
2320	"	mflo %0, $ac1					\n"	\
2321	"	.set pop					\n" 	\
2322	: "=r" (mflo1)); 						\
2323	mflo1;								\
2324})
2325
2326#define mflo2()								\
2327({									\
2328	long mflo2;							\
2329	__asm__(							\
2330	"	.set push					\n"	\
 
2331	"	.set dsp					\n"	\
2332	"	mflo %0, $ac2					\n"	\
2333	"	.set pop					\n" 	\
2334	: "=r" (mflo2)); 						\
2335	mflo2;								\
2336})
2337
2338#define mflo3()								\
2339({									\
2340	long mflo3;							\
2341	__asm__(							\
2342	"	.set push					\n"	\
 
2343	"	.set dsp					\n"	\
2344	"	mflo %0, $ac3					\n"	\
2345	"	.set pop					\n" 	\
2346	: "=r" (mflo3)); 						\
2347	mflo3;								\
2348})
2349
2350#define mfhi0()								\
2351({									\
2352	long mfhi0;							\
2353	__asm__(							\
2354	"	.set push					\n"	\
 
2355	"	.set dsp					\n"	\
2356	"	mfhi %0, $ac0					\n"	\
2357	"	.set pop					\n" 	\
2358	: "=r" (mfhi0)); 						\
2359	mfhi0;								\
2360})
2361
2362#define mfhi1()								\
2363({									\
2364	long mfhi1;							\
2365	__asm__(							\
2366	"	.set push					\n"	\
 
2367	"	.set dsp					\n"	\
2368	"	mfhi %0, $ac1					\n"	\
2369	"	.set pop					\n" 	\
2370	: "=r" (mfhi1)); 						\
2371	mfhi1;								\
2372})
2373
2374#define mfhi2()								\
2375({									\
2376	long mfhi2;							\
2377	__asm__(							\
2378	"	.set push					\n"	\
 
2379	"	.set dsp					\n"	\
2380	"	mfhi %0, $ac2					\n"	\
2381	"	.set pop					\n" 	\
2382	: "=r" (mfhi2)); 						\
2383	mfhi2;								\
2384})
2385
2386#define mfhi3()								\
2387({									\
2388	long mfhi3;							\
2389	__asm__(							\
2390	"	.set push					\n"	\
 
2391	"	.set dsp					\n"	\
2392	"	mfhi %0, $ac3					\n"	\
2393	"	.set pop					\n" 	\
2394	: "=r" (mfhi3)); 						\
2395	mfhi3;								\
2396})
2397
2398
2399#define mtlo0(x)							\
2400({									\
2401	__asm__(							\
2402	"	.set push					\n"	\
 
2403	"	.set dsp					\n"	\
2404	"	mtlo %0, $ac0					\n"	\
2405	"	.set pop					\n"	\
2406	:								\
2407	: "r" (x));							\
2408})
2409
2410#define mtlo1(x)							\
2411({									\
2412	__asm__(							\
2413	"	.set push					\n"	\
 
2414	"	.set dsp					\n"	\
2415	"	mtlo %0, $ac1					\n"	\
2416	"	.set pop					\n"	\
2417	:								\
2418	: "r" (x));							\
2419})
2420
2421#define mtlo2(x)							\
2422({									\
2423	__asm__(							\
2424	"	.set push					\n"	\
 
2425	"	.set dsp					\n"	\
2426	"	mtlo %0, $ac2					\n"	\
2427	"	.set pop					\n"	\
2428	:								\
2429	: "r" (x));							\
2430})
2431
2432#define mtlo3(x)							\
2433({									\
2434	__asm__(							\
2435	"	.set push					\n"	\
 
2436	"	.set dsp					\n"	\
2437	"	mtlo %0, $ac3					\n"	\
2438	"	.set pop					\n"	\
2439	:								\
2440	: "r" (x));							\
2441})
2442
2443#define mthi0(x)							\
2444({									\
2445	__asm__(							\
2446	"	.set push					\n"	\
 
2447	"	.set dsp					\n"	\
2448	"	mthi %0, $ac0					\n"	\
2449	"	.set pop					\n"	\
2450	:								\
2451	: "r" (x));							\
2452})
2453
2454#define mthi1(x)							\
2455({									\
2456	__asm__(							\
2457	"	.set push					\n"	\
 
2458	"	.set dsp					\n"	\
2459	"	mthi %0, $ac1					\n"	\
2460	"	.set pop					\n"	\
2461	:								\
2462	: "r" (x));							\
2463})
2464
2465#define mthi2(x)							\
2466({									\
2467	__asm__(							\
2468	"	.set push					\n"	\
 
2469	"	.set dsp					\n"	\
2470	"	mthi %0, $ac2					\n"	\
2471	"	.set pop					\n"	\
2472	:								\
2473	: "r" (x));							\
2474})
2475
2476#define mthi3(x)							\
2477({									\
2478	__asm__(							\
2479	"	.set push					\n"	\
 
2480	"	.set dsp					\n"	\
2481	"	mthi %0, $ac3					\n"	\
2482	"	.set pop					\n"	\
2483	:								\
2484	: "r" (x));							\
2485})
2486
2487#else
2488
2489#define rddsp(mask)							\
2490({									\
2491	unsigned int __res;						\
2492									\
2493	__asm__ __volatile__(						\
2494	"	.set	push					\n"	\
2495	"	.set	noat					\n"	\
2496	"	# rddsp $1, %x1					\n"	\
2497	_ASM_INSN_IF_MIPS(0x7c000cb8 | (%x1 << 16))			\
2498	_ASM_INSN32_IF_MM(0x0020067c | (%x1 << 14))			\
2499	"	move	%0, $1					\n"	\
2500	"	.set	pop					\n"	\
2501	: "=r" (__res)							\
2502	: "i" (mask));							\
2503	__res;								\
2504})
2505
2506#define wrdsp(val, mask)						\
2507do {									\
2508	__asm__ __volatile__(						\
2509	"	.set	push					\n"	\
2510	"	.set	noat					\n"	\
2511	"	move	$1, %0					\n"	\
2512	"	# wrdsp $1, %x1					\n"	\
2513	_ASM_INSN_IF_MIPS(0x7c2004f8 | (%x1 << 11))			\
2514	_ASM_INSN32_IF_MM(0x0020167c | (%x1 << 14))			\
2515	"	.set	pop					\n"	\
2516	:								\
2517	: "r" (val), "i" (mask));					\
2518} while (0)
2519
2520#define _dsp_mfxxx(ins)							\
2521({									\
2522	unsigned long __treg;						\
2523									\
2524	__asm__ __volatile__(						\
2525	"	.set	push					\n"	\
2526	"	.set	noat					\n"	\
2527	_ASM_INSN_IF_MIPS(0x00000810 | %X1)				\
2528	_ASM_INSN32_IF_MM(0x0001007c | %x1)				\
2529	"	move	%0, $1					\n"	\
2530	"	.set	pop					\n"	\
2531	: "=r" (__treg)							\
2532	: "i" (ins));							\
2533	__treg;								\
2534})
2535
2536#define _dsp_mtxxx(val, ins)						\
2537do {									\
2538	__asm__ __volatile__(						\
2539	"	.set	push					\n"	\
2540	"	.set	noat					\n"	\
2541	"	move	$1, %0					\n"	\
2542	_ASM_INSN_IF_MIPS(0x00200011 | %X1)				\
2543	_ASM_INSN32_IF_MM(0x0001207c | %x1)				\
2544	"	.set	pop					\n"	\
2545	:								\
2546	: "r" (val), "i" (ins));					\
2547} while (0)
2548
2549#ifdef CONFIG_CPU_MICROMIPS
2550
2551#define _dsp_mflo(reg) _dsp_mfxxx((reg << 14) | 0x1000)
2552#define _dsp_mfhi(reg) _dsp_mfxxx((reg << 14) | 0x0000)
2553
2554#define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x1000))
2555#define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x0000))
2556
2557#else  /* !CONFIG_CPU_MICROMIPS */
2558
2559#define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
2560#define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
2561
2562#define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
2563#define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
2564
2565#endif /* CONFIG_CPU_MICROMIPS */
2566
2567#define mflo0() _dsp_mflo(0)
2568#define mflo1() _dsp_mflo(1)
2569#define mflo2() _dsp_mflo(2)
2570#define mflo3() _dsp_mflo(3)
2571
2572#define mfhi0() _dsp_mfhi(0)
2573#define mfhi1() _dsp_mfhi(1)
2574#define mfhi2() _dsp_mfhi(2)
2575#define mfhi3() _dsp_mfhi(3)
2576
2577#define mtlo0(x) _dsp_mtlo(x, 0)
2578#define mtlo1(x) _dsp_mtlo(x, 1)
2579#define mtlo2(x) _dsp_mtlo(x, 2)
2580#define mtlo3(x) _dsp_mtlo(x, 3)
2581
2582#define mthi0(x) _dsp_mthi(x, 0)
2583#define mthi1(x) _dsp_mthi(x, 1)
2584#define mthi2(x) _dsp_mthi(x, 2)
2585#define mthi3(x) _dsp_mthi(x, 3)
2586
2587#endif
2588
2589/*
2590 * TLB operations.
2591 *
2592 * It is responsibility of the caller to take care of any TLB hazards.
2593 */
2594static inline void tlb_probe(void)
2595{
2596	__asm__ __volatile__(
2597		".set noreorder\n\t"
2598		"tlbp\n\t"
2599		".set reorder");
2600}
2601
2602static inline void tlb_read(void)
2603{
2604#if MIPS34K_MISSED_ITLB_WAR
2605	int res = 0;
2606
2607	__asm__ __volatile__(
2608	"	.set	push					\n"
2609	"	.set	noreorder				\n"
2610	"	.set	noat					\n"
2611	"	.set	mips32r2				\n"
2612	"	.word	0x41610001		# dvpe $1	\n"
2613	"	move	%0, $1					\n"
2614	"	ehb						\n"
2615	"	.set	pop					\n"
2616	: "=r" (res));
2617
2618	instruction_hazard();
2619#endif
2620
2621	__asm__ __volatile__(
2622		".set noreorder\n\t"
2623		"tlbr\n\t"
2624		".set reorder");
2625
2626#if MIPS34K_MISSED_ITLB_WAR
2627	if ((res & _ULCAST_(1)))
2628		__asm__ __volatile__(
2629		"	.set	push				\n"
2630		"	.set	noreorder			\n"
2631		"	.set	noat				\n"
2632		"	.set	mips32r2			\n"
2633		"	.word	0x41600021	# evpe		\n"
2634		"	ehb					\n"
2635		"	.set	pop				\n");
2636#endif
2637}
2638
2639static inline void tlb_write_indexed(void)
2640{
2641	__asm__ __volatile__(
2642		".set noreorder\n\t"
2643		"tlbwi\n\t"
2644		".set reorder");
2645}
2646
2647static inline void tlb_write_random(void)
2648{
2649	__asm__ __volatile__(
2650		".set noreorder\n\t"
2651		"tlbwr\n\t"
2652		".set reorder");
2653}
2654
2655/*
2656 * Guest TLB operations.
2657 *
2658 * It is responsibility of the caller to take care of any TLB hazards.
2659 */
2660static inline void guest_tlb_probe(void)
2661{
2662	__asm__ __volatile__(
2663		".set push\n\t"
2664		".set noreorder\n\t"
2665		_ASM_SET_VIRT
2666		"tlbgp\n\t"
2667		".set pop");
2668}
2669
2670static inline void guest_tlb_read(void)
2671{
2672	__asm__ __volatile__(
2673		".set push\n\t"
2674		".set noreorder\n\t"
2675		_ASM_SET_VIRT
2676		"tlbgr\n\t"
2677		".set pop");
2678}
2679
2680static inline void guest_tlb_write_indexed(void)
2681{
2682	__asm__ __volatile__(
2683		".set push\n\t"
2684		".set noreorder\n\t"
2685		_ASM_SET_VIRT
2686		"tlbgwi\n\t"
2687		".set pop");
2688}
2689
2690static inline void guest_tlb_write_random(void)
2691{
2692	__asm__ __volatile__(
2693		".set push\n\t"
2694		".set noreorder\n\t"
2695		_ASM_SET_VIRT
2696		"tlbgwr\n\t"
2697		".set pop");
2698}
2699
2700/*
2701 * Guest TLB Invalidate Flush
2702 */
2703static inline void guest_tlbinvf(void)
2704{
2705	__asm__ __volatile__(
2706		".set push\n\t"
2707		".set noreorder\n\t"
2708		_ASM_SET_VIRT
2709		"tlbginvf\n\t"
2710		".set pop");
2711}
2712
2713/*
2714 * Manipulate bits in a register.
2715 */
2716#define __BUILD_SET_COMMON(name)				\
2717static inline unsigned int					\
2718set_##name(unsigned int set)					\
2719{								\
2720	unsigned int res, new;					\
2721								\
2722	res = read_##name();					\
2723	new = res | set;					\
2724	write_##name(new);					\
2725								\
2726	return res;						\
2727}								\
2728								\
2729static inline unsigned int					\
2730clear_##name(unsigned int clear)				\
2731{								\
2732	unsigned int res, new;					\
2733								\
2734	res = read_##name();					\
2735	new = res & ~clear;					\
2736	write_##name(new);					\
2737								\
2738	return res;						\
2739}								\
2740								\
2741static inline unsigned int					\
2742change_##name(unsigned int change, unsigned int val)		\
2743{								\
2744	unsigned int res, new;					\
2745								\
2746	res = read_##name();					\
2747	new = res & ~change;					\
2748	new |= (val & change);					\
2749	write_##name(new);					\
2750								\
2751	return res;						\
2752}
2753
2754/*
2755 * Manipulate bits in a c0 register.
2756 */
2757#define __BUILD_SET_C0(name)	__BUILD_SET_COMMON(c0_##name)
2758
2759__BUILD_SET_C0(status)
2760__BUILD_SET_C0(cause)
2761__BUILD_SET_C0(config)
2762__BUILD_SET_C0(config5)
 
 
 
2763__BUILD_SET_C0(intcontrol)
2764__BUILD_SET_C0(intctl)
2765__BUILD_SET_C0(srsmap)
2766__BUILD_SET_C0(pagegrain)
2767__BUILD_SET_C0(guestctl0)
2768__BUILD_SET_C0(guestctl0ext)
2769__BUILD_SET_C0(guestctl1)
2770__BUILD_SET_C0(guestctl2)
2771__BUILD_SET_C0(guestctl3)
2772__BUILD_SET_C0(brcm_config_0)
2773__BUILD_SET_C0(brcm_bus_pll)
2774__BUILD_SET_C0(brcm_reset)
2775__BUILD_SET_C0(brcm_cmt_intr)
2776__BUILD_SET_C0(brcm_cmt_ctrl)
2777__BUILD_SET_C0(brcm_config)
2778__BUILD_SET_C0(brcm_mode)
2779
2780/*
2781 * Manipulate bits in a guest c0 register.
2782 */
2783#define __BUILD_SET_GC0(name)	__BUILD_SET_COMMON(gc0_##name)
2784
2785__BUILD_SET_GC0(wired)
2786__BUILD_SET_GC0(status)
2787__BUILD_SET_GC0(cause)
2788__BUILD_SET_GC0(ebase)
2789__BUILD_SET_GC0(config1)
2790
2791/*
2792 * Return low 10 bits of ebase.
2793 * Note that under KVM (MIPSVZ) this returns vcpu id.
2794 */
2795static inline unsigned int get_ebase_cpunum(void)
2796{
2797	return read_c0_ebase() & MIPS_EBASE_CPUNUM;
2798}
2799
2800#endif /* !__ASSEMBLY__ */
2801
2802#endif /* _ASM_MIPSREGS_H */