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1/* bpf_jit_comp.c : BPF JIT compiler
2 *
3 * Copyright (C) 2011-2013 Eric Dumazet (eric.dumazet@gmail.com)
4 * Internal BPF Copyright (c) 2011-2014 PLUMgrid, http://plumgrid.com
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; version 2
9 * of the License.
10 */
11#include <linux/netdevice.h>
12#include <linux/filter.h>
13#include <linux/if_vlan.h>
14#include <linux/bpf.h>
15
16#include <asm/set_memory.h>
17#include <asm/nospec-branch.h>
18
19/*
20 * assembly code in arch/x86/net/bpf_jit.S
21 */
22extern u8 sk_load_word[], sk_load_half[], sk_load_byte[];
23extern u8 sk_load_word_positive_offset[], sk_load_half_positive_offset[];
24extern u8 sk_load_byte_positive_offset[];
25extern u8 sk_load_word_negative_offset[], sk_load_half_negative_offset[];
26extern u8 sk_load_byte_negative_offset[];
27
28static u8 *emit_code(u8 *ptr, u32 bytes, unsigned int len)
29{
30 if (len == 1)
31 *ptr = bytes;
32 else if (len == 2)
33 *(u16 *)ptr = bytes;
34 else {
35 *(u32 *)ptr = bytes;
36 barrier();
37 }
38 return ptr + len;
39}
40
41#define EMIT(bytes, len) \
42 do { prog = emit_code(prog, bytes, len); cnt += len; } while (0)
43
44#define EMIT1(b1) EMIT(b1, 1)
45#define EMIT2(b1, b2) EMIT((b1) + ((b2) << 8), 2)
46#define EMIT3(b1, b2, b3) EMIT((b1) + ((b2) << 8) + ((b3) << 16), 3)
47#define EMIT4(b1, b2, b3, b4) EMIT((b1) + ((b2) << 8) + ((b3) << 16) + ((b4) << 24), 4)
48#define EMIT1_off32(b1, off) \
49 do {EMIT1(b1); EMIT(off, 4); } while (0)
50#define EMIT2_off32(b1, b2, off) \
51 do {EMIT2(b1, b2); EMIT(off, 4); } while (0)
52#define EMIT3_off32(b1, b2, b3, off) \
53 do {EMIT3(b1, b2, b3); EMIT(off, 4); } while (0)
54#define EMIT4_off32(b1, b2, b3, b4, off) \
55 do {EMIT4(b1, b2, b3, b4); EMIT(off, 4); } while (0)
56
57static bool is_imm8(int value)
58{
59 return value <= 127 && value >= -128;
60}
61
62static bool is_simm32(s64 value)
63{
64 return value == (s64)(s32)value;
65}
66
67static bool is_uimm32(u64 value)
68{
69 return value == (u64)(u32)value;
70}
71
72/* mov dst, src */
73#define EMIT_mov(DST, SRC) \
74 do {if (DST != SRC) \
75 EMIT3(add_2mod(0x48, DST, SRC), 0x89, add_2reg(0xC0, DST, SRC)); \
76 } while (0)
77
78static int bpf_size_to_x86_bytes(int bpf_size)
79{
80 if (bpf_size == BPF_W)
81 return 4;
82 else if (bpf_size == BPF_H)
83 return 2;
84 else if (bpf_size == BPF_B)
85 return 1;
86 else if (bpf_size == BPF_DW)
87 return 4; /* imm32 */
88 else
89 return 0;
90}
91
92/* list of x86 cond jumps opcodes (. + s8)
93 * Add 0x10 (and an extra 0x0f) to generate far jumps (. + s32)
94 */
95#define X86_JB 0x72
96#define X86_JAE 0x73
97#define X86_JE 0x74
98#define X86_JNE 0x75
99#define X86_JBE 0x76
100#define X86_JA 0x77
101#define X86_JL 0x7C
102#define X86_JGE 0x7D
103#define X86_JLE 0x7E
104#define X86_JG 0x7F
105
106#define CHOOSE_LOAD_FUNC(K, func) \
107 ((int)K < 0 ? ((int)K >= SKF_LL_OFF ? func##_negative_offset : func) : func##_positive_offset)
108
109/* pick a register outside of BPF range for JIT internal work */
110#define AUX_REG (MAX_BPF_JIT_REG + 1)
111
112/* The following table maps BPF registers to x64 registers.
113 *
114 * x64 register r12 is unused, since if used as base address
115 * register in load/store instructions, it always needs an
116 * extra byte of encoding and is callee saved.
117 *
118 * r9 caches skb->len - skb->data_len
119 * r10 caches skb->data, and used for blinding (if enabled)
120 */
121static const int reg2hex[] = {
122 [BPF_REG_0] = 0, /* rax */
123 [BPF_REG_1] = 7, /* rdi */
124 [BPF_REG_2] = 6, /* rsi */
125 [BPF_REG_3] = 2, /* rdx */
126 [BPF_REG_4] = 1, /* rcx */
127 [BPF_REG_5] = 0, /* r8 */
128 [BPF_REG_6] = 3, /* rbx callee saved */
129 [BPF_REG_7] = 5, /* r13 callee saved */
130 [BPF_REG_8] = 6, /* r14 callee saved */
131 [BPF_REG_9] = 7, /* r15 callee saved */
132 [BPF_REG_FP] = 5, /* rbp readonly */
133 [BPF_REG_AX] = 2, /* r10 temp register */
134 [AUX_REG] = 3, /* r11 temp register */
135};
136
137/* is_ereg() == true if BPF register 'reg' maps to x64 r8..r15
138 * which need extra byte of encoding.
139 * rax,rcx,...,rbp have simpler encoding
140 */
141static bool is_ereg(u32 reg)
142{
143 return (1 << reg) & (BIT(BPF_REG_5) |
144 BIT(AUX_REG) |
145 BIT(BPF_REG_7) |
146 BIT(BPF_REG_8) |
147 BIT(BPF_REG_9) |
148 BIT(BPF_REG_AX));
149}
150
151static bool is_axreg(u32 reg)
152{
153 return reg == BPF_REG_0;
154}
155
156/* add modifiers if 'reg' maps to x64 registers r8..r15 */
157static u8 add_1mod(u8 byte, u32 reg)
158{
159 if (is_ereg(reg))
160 byte |= 1;
161 return byte;
162}
163
164static u8 add_2mod(u8 byte, u32 r1, u32 r2)
165{
166 if (is_ereg(r1))
167 byte |= 1;
168 if (is_ereg(r2))
169 byte |= 4;
170 return byte;
171}
172
173/* encode 'dst_reg' register into x64 opcode 'byte' */
174static u8 add_1reg(u8 byte, u32 dst_reg)
175{
176 return byte + reg2hex[dst_reg];
177}
178
179/* encode 'dst_reg' and 'src_reg' registers into x64 opcode 'byte' */
180static u8 add_2reg(u8 byte, u32 dst_reg, u32 src_reg)
181{
182 return byte + reg2hex[dst_reg] + (reg2hex[src_reg] << 3);
183}
184
185static void jit_fill_hole(void *area, unsigned int size)
186{
187 /* fill whole space with int3 instructions */
188 memset(area, 0xcc, size);
189}
190
191struct jit_context {
192 int cleanup_addr; /* epilogue code offset */
193 bool seen_ld_abs;
194 bool seen_ax_reg;
195};
196
197/* maximum number of bytes emitted while JITing one eBPF insn */
198#define BPF_MAX_INSN_SIZE 128
199#define BPF_INSN_SAFETY 64
200
201#define AUX_STACK_SPACE \
202 (32 /* space for rbx, r13, r14, r15 */ + \
203 8 /* space for skb_copy_bits() buffer */)
204
205#define PROLOGUE_SIZE 37
206
207/* emit x64 prologue code for BPF program and check it's size.
208 * bpf_tail_call helper will skip it while jumping into another program
209 */
210static void emit_prologue(u8 **pprog, u32 stack_depth, bool ebpf_from_cbpf)
211{
212 u8 *prog = *pprog;
213 int cnt = 0;
214
215 EMIT1(0x55); /* push rbp */
216 EMIT3(0x48, 0x89, 0xE5); /* mov rbp,rsp */
217
218 /* sub rsp, rounded_stack_depth + AUX_STACK_SPACE */
219 EMIT3_off32(0x48, 0x81, 0xEC,
220 round_up(stack_depth, 8) + AUX_STACK_SPACE);
221
222 /* sub rbp, AUX_STACK_SPACE */
223 EMIT4(0x48, 0x83, 0xED, AUX_STACK_SPACE);
224
225 /* all classic BPF filters use R6(rbx) save it */
226
227 /* mov qword ptr [rbp+0],rbx */
228 EMIT4(0x48, 0x89, 0x5D, 0);
229
230 /* bpf_convert_filter() maps classic BPF register X to R7 and uses R8
231 * as temporary, so all tcpdump filters need to spill/fill R7(r13) and
232 * R8(r14). R9(r15) spill could be made conditional, but there is only
233 * one 'bpf_error' return path out of helper functions inside bpf_jit.S
234 * The overhead of extra spill is negligible for any filter other
235 * than synthetic ones. Therefore not worth adding complexity.
236 */
237
238 /* mov qword ptr [rbp+8],r13 */
239 EMIT4(0x4C, 0x89, 0x6D, 8);
240 /* mov qword ptr [rbp+16],r14 */
241 EMIT4(0x4C, 0x89, 0x75, 16);
242 /* mov qword ptr [rbp+24],r15 */
243 EMIT4(0x4C, 0x89, 0x7D, 24);
244
245 if (!ebpf_from_cbpf) {
246 /* Clear the tail call counter (tail_call_cnt): for eBPF tail
247 * calls we need to reset the counter to 0. It's done in two
248 * instructions, resetting rax register to 0, and moving it
249 * to the counter location.
250 */
251
252 /* xor eax, eax */
253 EMIT2(0x31, 0xc0);
254 /* mov qword ptr [rbp+32], rax */
255 EMIT4(0x48, 0x89, 0x45, 32);
256
257 BUILD_BUG_ON(cnt != PROLOGUE_SIZE);
258 }
259
260 *pprog = prog;
261}
262
263/* generate the following code:
264 * ... bpf_tail_call(void *ctx, struct bpf_array *array, u64 index) ...
265 * if (index >= array->map.max_entries)
266 * goto out;
267 * if (++tail_call_cnt > MAX_TAIL_CALL_CNT)
268 * goto out;
269 * prog = array->ptrs[index];
270 * if (prog == NULL)
271 * goto out;
272 * goto *(prog->bpf_func + prologue_size);
273 * out:
274 */
275static void emit_bpf_tail_call(u8 **pprog)
276{
277 u8 *prog = *pprog;
278 int label1, label2, label3;
279 int cnt = 0;
280
281 /* rdi - pointer to ctx
282 * rsi - pointer to bpf_array
283 * rdx - index in bpf_array
284 */
285
286 /* if (index >= array->map.max_entries)
287 * goto out;
288 */
289 EMIT2(0x89, 0xD2); /* mov edx, edx */
290 EMIT3(0x39, 0x56, /* cmp dword ptr [rsi + 16], edx */
291 offsetof(struct bpf_array, map.max_entries));
292#define OFFSET1 (41 + RETPOLINE_RAX_BPF_JIT_SIZE) /* number of bytes to jump */
293 EMIT2(X86_JBE, OFFSET1); /* jbe out */
294 label1 = cnt;
295
296 /* if (tail_call_cnt > MAX_TAIL_CALL_CNT)
297 * goto out;
298 */
299 EMIT2_off32(0x8B, 0x85, 36); /* mov eax, dword ptr [rbp + 36] */
300 EMIT3(0x83, 0xF8, MAX_TAIL_CALL_CNT); /* cmp eax, MAX_TAIL_CALL_CNT */
301#define OFFSET2 (30 + RETPOLINE_RAX_BPF_JIT_SIZE)
302 EMIT2(X86_JA, OFFSET2); /* ja out */
303 label2 = cnt;
304 EMIT3(0x83, 0xC0, 0x01); /* add eax, 1 */
305 EMIT2_off32(0x89, 0x85, 36); /* mov dword ptr [rbp + 36], eax */
306
307 /* prog = array->ptrs[index]; */
308 EMIT4_off32(0x48, 0x8B, 0x84, 0xD6, /* mov rax, [rsi + rdx * 8 + offsetof(...)] */
309 offsetof(struct bpf_array, ptrs));
310
311 /* if (prog == NULL)
312 * goto out;
313 */
314 EMIT3(0x48, 0x85, 0xC0); /* test rax,rax */
315#define OFFSET3 (8 + RETPOLINE_RAX_BPF_JIT_SIZE)
316 EMIT2(X86_JE, OFFSET3); /* je out */
317 label3 = cnt;
318
319 /* goto *(prog->bpf_func + prologue_size); */
320 EMIT4(0x48, 0x8B, 0x40, /* mov rax, qword ptr [rax + 32] */
321 offsetof(struct bpf_prog, bpf_func));
322 EMIT4(0x48, 0x83, 0xC0, PROLOGUE_SIZE); /* add rax, prologue_size */
323
324 /* now we're ready to jump into next BPF program
325 * rdi == ctx (1st arg)
326 * rax == prog->bpf_func + prologue_size
327 */
328 RETPOLINE_RAX_BPF_JIT();
329
330 /* out: */
331 BUILD_BUG_ON(cnt - label1 != OFFSET1);
332 BUILD_BUG_ON(cnt - label2 != OFFSET2);
333 BUILD_BUG_ON(cnt - label3 != OFFSET3);
334 *pprog = prog;
335}
336
337
338static void emit_load_skb_data_hlen(u8 **pprog)
339{
340 u8 *prog = *pprog;
341 int cnt = 0;
342
343 /* r9d = skb->len - skb->data_len (headlen)
344 * r10 = skb->data
345 */
346 /* mov %r9d, off32(%rdi) */
347 EMIT3_off32(0x44, 0x8b, 0x8f, offsetof(struct sk_buff, len));
348
349 /* sub %r9d, off32(%rdi) */
350 EMIT3_off32(0x44, 0x2b, 0x8f, offsetof(struct sk_buff, data_len));
351
352 /* mov %r10, off32(%rdi) */
353 EMIT3_off32(0x4c, 0x8b, 0x97, offsetof(struct sk_buff, data));
354 *pprog = prog;
355}
356
357static void emit_mov_imm32(u8 **pprog, bool sign_propagate,
358 u32 dst_reg, const u32 imm32)
359{
360 u8 *prog = *pprog;
361 u8 b1, b2, b3;
362 int cnt = 0;
363
364 /* optimization: if imm32 is positive, use 'mov %eax, imm32'
365 * (which zero-extends imm32) to save 2 bytes.
366 */
367 if (sign_propagate && (s32)imm32 < 0) {
368 /* 'mov %rax, imm32' sign extends imm32 */
369 b1 = add_1mod(0x48, dst_reg);
370 b2 = 0xC7;
371 b3 = 0xC0;
372 EMIT3_off32(b1, b2, add_1reg(b3, dst_reg), imm32);
373 goto done;
374 }
375
376 /* optimization: if imm32 is zero, use 'xor %eax, %eax'
377 * to save 3 bytes.
378 */
379 if (imm32 == 0) {
380 if (is_ereg(dst_reg))
381 EMIT1(add_2mod(0x40, dst_reg, dst_reg));
382 b2 = 0x31; /* xor */
383 b3 = 0xC0;
384 EMIT2(b2, add_2reg(b3, dst_reg, dst_reg));
385 goto done;
386 }
387
388 /* mov %eax, imm32 */
389 if (is_ereg(dst_reg))
390 EMIT1(add_1mod(0x40, dst_reg));
391 EMIT1_off32(add_1reg(0xB8, dst_reg), imm32);
392done:
393 *pprog = prog;
394}
395
396static void emit_mov_imm64(u8 **pprog, u32 dst_reg,
397 const u32 imm32_hi, const u32 imm32_lo)
398{
399 u8 *prog = *pprog;
400 int cnt = 0;
401
402 if (is_uimm32(((u64)imm32_hi << 32) | (u32)imm32_lo)) {
403 /* For emitting plain u32, where sign bit must not be
404 * propagated LLVM tends to load imm64 over mov32
405 * directly, so save couple of bytes by just doing
406 * 'mov %eax, imm32' instead.
407 */
408 emit_mov_imm32(&prog, false, dst_reg, imm32_lo);
409 } else {
410 /* movabsq %rax, imm64 */
411 EMIT2(add_1mod(0x48, dst_reg), add_1reg(0xB8, dst_reg));
412 EMIT(imm32_lo, 4);
413 EMIT(imm32_hi, 4);
414 }
415
416 *pprog = prog;
417}
418
419static void emit_mov_reg(u8 **pprog, bool is64, u32 dst_reg, u32 src_reg)
420{
421 u8 *prog = *pprog;
422 int cnt = 0;
423
424 if (is64) {
425 /* mov dst, src */
426 EMIT_mov(dst_reg, src_reg);
427 } else {
428 /* mov32 dst, src */
429 if (is_ereg(dst_reg) || is_ereg(src_reg))
430 EMIT1(add_2mod(0x40, dst_reg, src_reg));
431 EMIT2(0x89, add_2reg(0xC0, dst_reg, src_reg));
432 }
433
434 *pprog = prog;
435}
436
437static int do_jit(struct bpf_prog *bpf_prog, int *addrs, u8 *image,
438 int oldproglen, struct jit_context *ctx)
439{
440 struct bpf_insn *insn = bpf_prog->insnsi;
441 int insn_cnt = bpf_prog->len;
442 bool seen_ld_abs = ctx->seen_ld_abs | (oldproglen == 0);
443 bool seen_ax_reg = ctx->seen_ax_reg | (oldproglen == 0);
444 bool seen_exit = false;
445 u8 temp[BPF_MAX_INSN_SIZE + BPF_INSN_SAFETY];
446 int i, cnt = 0;
447 int proglen = 0;
448 u8 *prog = temp;
449
450 emit_prologue(&prog, bpf_prog->aux->stack_depth,
451 bpf_prog_was_classic(bpf_prog));
452
453 if (seen_ld_abs)
454 emit_load_skb_data_hlen(&prog);
455
456 for (i = 0; i < insn_cnt; i++, insn++) {
457 const s32 imm32 = insn->imm;
458 u32 dst_reg = insn->dst_reg;
459 u32 src_reg = insn->src_reg;
460 u8 b2 = 0, b3 = 0;
461 s64 jmp_offset;
462 u8 jmp_cond;
463 bool reload_skb_data;
464 int ilen;
465 u8 *func;
466
467 if (dst_reg == BPF_REG_AX || src_reg == BPF_REG_AX)
468 ctx->seen_ax_reg = seen_ax_reg = true;
469
470 switch (insn->code) {
471 /* ALU */
472 case BPF_ALU | BPF_ADD | BPF_X:
473 case BPF_ALU | BPF_SUB | BPF_X:
474 case BPF_ALU | BPF_AND | BPF_X:
475 case BPF_ALU | BPF_OR | BPF_X:
476 case BPF_ALU | BPF_XOR | BPF_X:
477 case BPF_ALU64 | BPF_ADD | BPF_X:
478 case BPF_ALU64 | BPF_SUB | BPF_X:
479 case BPF_ALU64 | BPF_AND | BPF_X:
480 case BPF_ALU64 | BPF_OR | BPF_X:
481 case BPF_ALU64 | BPF_XOR | BPF_X:
482 switch (BPF_OP(insn->code)) {
483 case BPF_ADD: b2 = 0x01; break;
484 case BPF_SUB: b2 = 0x29; break;
485 case BPF_AND: b2 = 0x21; break;
486 case BPF_OR: b2 = 0x09; break;
487 case BPF_XOR: b2 = 0x31; break;
488 }
489 if (BPF_CLASS(insn->code) == BPF_ALU64)
490 EMIT1(add_2mod(0x48, dst_reg, src_reg));
491 else if (is_ereg(dst_reg) || is_ereg(src_reg))
492 EMIT1(add_2mod(0x40, dst_reg, src_reg));
493 EMIT2(b2, add_2reg(0xC0, dst_reg, src_reg));
494 break;
495
496 case BPF_ALU64 | BPF_MOV | BPF_X:
497 case BPF_ALU | BPF_MOV | BPF_X:
498 emit_mov_reg(&prog,
499 BPF_CLASS(insn->code) == BPF_ALU64,
500 dst_reg, src_reg);
501 break;
502
503 /* neg dst */
504 case BPF_ALU | BPF_NEG:
505 case BPF_ALU64 | BPF_NEG:
506 if (BPF_CLASS(insn->code) == BPF_ALU64)
507 EMIT1(add_1mod(0x48, dst_reg));
508 else if (is_ereg(dst_reg))
509 EMIT1(add_1mod(0x40, dst_reg));
510 EMIT2(0xF7, add_1reg(0xD8, dst_reg));
511 break;
512
513 case BPF_ALU | BPF_ADD | BPF_K:
514 case BPF_ALU | BPF_SUB | BPF_K:
515 case BPF_ALU | BPF_AND | BPF_K:
516 case BPF_ALU | BPF_OR | BPF_K:
517 case BPF_ALU | BPF_XOR | BPF_K:
518 case BPF_ALU64 | BPF_ADD | BPF_K:
519 case BPF_ALU64 | BPF_SUB | BPF_K:
520 case BPF_ALU64 | BPF_AND | BPF_K:
521 case BPF_ALU64 | BPF_OR | BPF_K:
522 case BPF_ALU64 | BPF_XOR | BPF_K:
523 if (BPF_CLASS(insn->code) == BPF_ALU64)
524 EMIT1(add_1mod(0x48, dst_reg));
525 else if (is_ereg(dst_reg))
526 EMIT1(add_1mod(0x40, dst_reg));
527
528 /* b3 holds 'normal' opcode, b2 short form only valid
529 * in case dst is eax/rax.
530 */
531 switch (BPF_OP(insn->code)) {
532 case BPF_ADD:
533 b3 = 0xC0;
534 b2 = 0x05;
535 break;
536 case BPF_SUB:
537 b3 = 0xE8;
538 b2 = 0x2D;
539 break;
540 case BPF_AND:
541 b3 = 0xE0;
542 b2 = 0x25;
543 break;
544 case BPF_OR:
545 b3 = 0xC8;
546 b2 = 0x0D;
547 break;
548 case BPF_XOR:
549 b3 = 0xF0;
550 b2 = 0x35;
551 break;
552 }
553
554 if (is_imm8(imm32))
555 EMIT3(0x83, add_1reg(b3, dst_reg), imm32);
556 else if (is_axreg(dst_reg))
557 EMIT1_off32(b2, imm32);
558 else
559 EMIT2_off32(0x81, add_1reg(b3, dst_reg), imm32);
560 break;
561
562 case BPF_ALU64 | BPF_MOV | BPF_K:
563 case BPF_ALU | BPF_MOV | BPF_K:
564 emit_mov_imm32(&prog, BPF_CLASS(insn->code) == BPF_ALU64,
565 dst_reg, imm32);
566 break;
567
568 case BPF_LD | BPF_IMM | BPF_DW:
569 emit_mov_imm64(&prog, dst_reg, insn[1].imm, insn[0].imm);
570 insn++;
571 i++;
572 break;
573
574 /* dst %= src, dst /= src, dst %= imm32, dst /= imm32 */
575 case BPF_ALU | BPF_MOD | BPF_X:
576 case BPF_ALU | BPF_DIV | BPF_X:
577 case BPF_ALU | BPF_MOD | BPF_K:
578 case BPF_ALU | BPF_DIV | BPF_K:
579 case BPF_ALU64 | BPF_MOD | BPF_X:
580 case BPF_ALU64 | BPF_DIV | BPF_X:
581 case BPF_ALU64 | BPF_MOD | BPF_K:
582 case BPF_ALU64 | BPF_DIV | BPF_K:
583 EMIT1(0x50); /* push rax */
584 EMIT1(0x52); /* push rdx */
585
586 if (BPF_SRC(insn->code) == BPF_X)
587 /* mov r11, src_reg */
588 EMIT_mov(AUX_REG, src_reg);
589 else
590 /* mov r11, imm32 */
591 EMIT3_off32(0x49, 0xC7, 0xC3, imm32);
592
593 /* mov rax, dst_reg */
594 EMIT_mov(BPF_REG_0, dst_reg);
595
596 /* xor edx, edx
597 * equivalent to 'xor rdx, rdx', but one byte less
598 */
599 EMIT2(0x31, 0xd2);
600
601 if (BPF_CLASS(insn->code) == BPF_ALU64)
602 /* div r11 */
603 EMIT3(0x49, 0xF7, 0xF3);
604 else
605 /* div r11d */
606 EMIT3(0x41, 0xF7, 0xF3);
607
608 if (BPF_OP(insn->code) == BPF_MOD)
609 /* mov r11, rdx */
610 EMIT3(0x49, 0x89, 0xD3);
611 else
612 /* mov r11, rax */
613 EMIT3(0x49, 0x89, 0xC3);
614
615 EMIT1(0x5A); /* pop rdx */
616 EMIT1(0x58); /* pop rax */
617
618 /* mov dst_reg, r11 */
619 EMIT_mov(dst_reg, AUX_REG);
620 break;
621
622 case BPF_ALU | BPF_MUL | BPF_K:
623 case BPF_ALU | BPF_MUL | BPF_X:
624 case BPF_ALU64 | BPF_MUL | BPF_K:
625 case BPF_ALU64 | BPF_MUL | BPF_X:
626 {
627 bool is64 = BPF_CLASS(insn->code) == BPF_ALU64;
628
629 if (dst_reg != BPF_REG_0)
630 EMIT1(0x50); /* push rax */
631 if (dst_reg != BPF_REG_3)
632 EMIT1(0x52); /* push rdx */
633
634 /* mov r11, dst_reg */
635 EMIT_mov(AUX_REG, dst_reg);
636
637 if (BPF_SRC(insn->code) == BPF_X)
638 emit_mov_reg(&prog, is64, BPF_REG_0, src_reg);
639 else
640 emit_mov_imm32(&prog, is64, BPF_REG_0, imm32);
641
642 if (is64)
643 EMIT1(add_1mod(0x48, AUX_REG));
644 else if (is_ereg(AUX_REG))
645 EMIT1(add_1mod(0x40, AUX_REG));
646 /* mul(q) r11 */
647 EMIT2(0xF7, add_1reg(0xE0, AUX_REG));
648
649 if (dst_reg != BPF_REG_3)
650 EMIT1(0x5A); /* pop rdx */
651 if (dst_reg != BPF_REG_0) {
652 /* mov dst_reg, rax */
653 EMIT_mov(dst_reg, BPF_REG_0);
654 EMIT1(0x58); /* pop rax */
655 }
656 break;
657 }
658 /* shifts */
659 case BPF_ALU | BPF_LSH | BPF_K:
660 case BPF_ALU | BPF_RSH | BPF_K:
661 case BPF_ALU | BPF_ARSH | BPF_K:
662 case BPF_ALU64 | BPF_LSH | BPF_K:
663 case BPF_ALU64 | BPF_RSH | BPF_K:
664 case BPF_ALU64 | BPF_ARSH | BPF_K:
665 if (BPF_CLASS(insn->code) == BPF_ALU64)
666 EMIT1(add_1mod(0x48, dst_reg));
667 else if (is_ereg(dst_reg))
668 EMIT1(add_1mod(0x40, dst_reg));
669
670 switch (BPF_OP(insn->code)) {
671 case BPF_LSH: b3 = 0xE0; break;
672 case BPF_RSH: b3 = 0xE8; break;
673 case BPF_ARSH: b3 = 0xF8; break;
674 }
675
676 if (imm32 == 1)
677 EMIT2(0xD1, add_1reg(b3, dst_reg));
678 else
679 EMIT3(0xC1, add_1reg(b3, dst_reg), imm32);
680 break;
681
682 case BPF_ALU | BPF_LSH | BPF_X:
683 case BPF_ALU | BPF_RSH | BPF_X:
684 case BPF_ALU | BPF_ARSH | BPF_X:
685 case BPF_ALU64 | BPF_LSH | BPF_X:
686 case BPF_ALU64 | BPF_RSH | BPF_X:
687 case BPF_ALU64 | BPF_ARSH | BPF_X:
688
689 /* check for bad case when dst_reg == rcx */
690 if (dst_reg == BPF_REG_4) {
691 /* mov r11, dst_reg */
692 EMIT_mov(AUX_REG, dst_reg);
693 dst_reg = AUX_REG;
694 }
695
696 if (src_reg != BPF_REG_4) { /* common case */
697 EMIT1(0x51); /* push rcx */
698
699 /* mov rcx, src_reg */
700 EMIT_mov(BPF_REG_4, src_reg);
701 }
702
703 /* shl %rax, %cl | shr %rax, %cl | sar %rax, %cl */
704 if (BPF_CLASS(insn->code) == BPF_ALU64)
705 EMIT1(add_1mod(0x48, dst_reg));
706 else if (is_ereg(dst_reg))
707 EMIT1(add_1mod(0x40, dst_reg));
708
709 switch (BPF_OP(insn->code)) {
710 case BPF_LSH: b3 = 0xE0; break;
711 case BPF_RSH: b3 = 0xE8; break;
712 case BPF_ARSH: b3 = 0xF8; break;
713 }
714 EMIT2(0xD3, add_1reg(b3, dst_reg));
715
716 if (src_reg != BPF_REG_4)
717 EMIT1(0x59); /* pop rcx */
718
719 if (insn->dst_reg == BPF_REG_4)
720 /* mov dst_reg, r11 */
721 EMIT_mov(insn->dst_reg, AUX_REG);
722 break;
723
724 case BPF_ALU | BPF_END | BPF_FROM_BE:
725 switch (imm32) {
726 case 16:
727 /* emit 'ror %ax, 8' to swap lower 2 bytes */
728 EMIT1(0x66);
729 if (is_ereg(dst_reg))
730 EMIT1(0x41);
731 EMIT3(0xC1, add_1reg(0xC8, dst_reg), 8);
732
733 /* emit 'movzwl eax, ax' */
734 if (is_ereg(dst_reg))
735 EMIT3(0x45, 0x0F, 0xB7);
736 else
737 EMIT2(0x0F, 0xB7);
738 EMIT1(add_2reg(0xC0, dst_reg, dst_reg));
739 break;
740 case 32:
741 /* emit 'bswap eax' to swap lower 4 bytes */
742 if (is_ereg(dst_reg))
743 EMIT2(0x41, 0x0F);
744 else
745 EMIT1(0x0F);
746 EMIT1(add_1reg(0xC8, dst_reg));
747 break;
748 case 64:
749 /* emit 'bswap rax' to swap 8 bytes */
750 EMIT3(add_1mod(0x48, dst_reg), 0x0F,
751 add_1reg(0xC8, dst_reg));
752 break;
753 }
754 break;
755
756 case BPF_ALU | BPF_END | BPF_FROM_LE:
757 switch (imm32) {
758 case 16:
759 /* emit 'movzwl eax, ax' to zero extend 16-bit
760 * into 64 bit
761 */
762 if (is_ereg(dst_reg))
763 EMIT3(0x45, 0x0F, 0xB7);
764 else
765 EMIT2(0x0F, 0xB7);
766 EMIT1(add_2reg(0xC0, dst_reg, dst_reg));
767 break;
768 case 32:
769 /* emit 'mov eax, eax' to clear upper 32-bits */
770 if (is_ereg(dst_reg))
771 EMIT1(0x45);
772 EMIT2(0x89, add_2reg(0xC0, dst_reg, dst_reg));
773 break;
774 case 64:
775 /* nop */
776 break;
777 }
778 break;
779
780 /* ST: *(u8*)(dst_reg + off) = imm */
781 case BPF_ST | BPF_MEM | BPF_B:
782 if (is_ereg(dst_reg))
783 EMIT2(0x41, 0xC6);
784 else
785 EMIT1(0xC6);
786 goto st;
787 case BPF_ST | BPF_MEM | BPF_H:
788 if (is_ereg(dst_reg))
789 EMIT3(0x66, 0x41, 0xC7);
790 else
791 EMIT2(0x66, 0xC7);
792 goto st;
793 case BPF_ST | BPF_MEM | BPF_W:
794 if (is_ereg(dst_reg))
795 EMIT2(0x41, 0xC7);
796 else
797 EMIT1(0xC7);
798 goto st;
799 case BPF_ST | BPF_MEM | BPF_DW:
800 EMIT2(add_1mod(0x48, dst_reg), 0xC7);
801
802st: if (is_imm8(insn->off))
803 EMIT2(add_1reg(0x40, dst_reg), insn->off);
804 else
805 EMIT1_off32(add_1reg(0x80, dst_reg), insn->off);
806
807 EMIT(imm32, bpf_size_to_x86_bytes(BPF_SIZE(insn->code)));
808 break;
809
810 /* STX: *(u8*)(dst_reg + off) = src_reg */
811 case BPF_STX | BPF_MEM | BPF_B:
812 /* emit 'mov byte ptr [rax + off], al' */
813 if (is_ereg(dst_reg) || is_ereg(src_reg) ||
814 /* have to add extra byte for x86 SIL, DIL regs */
815 src_reg == BPF_REG_1 || src_reg == BPF_REG_2)
816 EMIT2(add_2mod(0x40, dst_reg, src_reg), 0x88);
817 else
818 EMIT1(0x88);
819 goto stx;
820 case BPF_STX | BPF_MEM | BPF_H:
821 if (is_ereg(dst_reg) || is_ereg(src_reg))
822 EMIT3(0x66, add_2mod(0x40, dst_reg, src_reg), 0x89);
823 else
824 EMIT2(0x66, 0x89);
825 goto stx;
826 case BPF_STX | BPF_MEM | BPF_W:
827 if (is_ereg(dst_reg) || is_ereg(src_reg))
828 EMIT2(add_2mod(0x40, dst_reg, src_reg), 0x89);
829 else
830 EMIT1(0x89);
831 goto stx;
832 case BPF_STX | BPF_MEM | BPF_DW:
833 EMIT2(add_2mod(0x48, dst_reg, src_reg), 0x89);
834stx: if (is_imm8(insn->off))
835 EMIT2(add_2reg(0x40, dst_reg, src_reg), insn->off);
836 else
837 EMIT1_off32(add_2reg(0x80, dst_reg, src_reg),
838 insn->off);
839 break;
840
841 /* LDX: dst_reg = *(u8*)(src_reg + off) */
842 case BPF_LDX | BPF_MEM | BPF_B:
843 /* emit 'movzx rax, byte ptr [rax + off]' */
844 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xB6);
845 goto ldx;
846 case BPF_LDX | BPF_MEM | BPF_H:
847 /* emit 'movzx rax, word ptr [rax + off]' */
848 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xB7);
849 goto ldx;
850 case BPF_LDX | BPF_MEM | BPF_W:
851 /* emit 'mov eax, dword ptr [rax+0x14]' */
852 if (is_ereg(dst_reg) || is_ereg(src_reg))
853 EMIT2(add_2mod(0x40, src_reg, dst_reg), 0x8B);
854 else
855 EMIT1(0x8B);
856 goto ldx;
857 case BPF_LDX | BPF_MEM | BPF_DW:
858 /* emit 'mov rax, qword ptr [rax+0x14]' */
859 EMIT2(add_2mod(0x48, src_reg, dst_reg), 0x8B);
860ldx: /* if insn->off == 0 we can save one extra byte, but
861 * special case of x86 r13 which always needs an offset
862 * is not worth the hassle
863 */
864 if (is_imm8(insn->off))
865 EMIT2(add_2reg(0x40, src_reg, dst_reg), insn->off);
866 else
867 EMIT1_off32(add_2reg(0x80, src_reg, dst_reg),
868 insn->off);
869 break;
870
871 /* STX XADD: lock *(u32*)(dst_reg + off) += src_reg */
872 case BPF_STX | BPF_XADD | BPF_W:
873 /* emit 'lock add dword ptr [rax + off], eax' */
874 if (is_ereg(dst_reg) || is_ereg(src_reg))
875 EMIT3(0xF0, add_2mod(0x40, dst_reg, src_reg), 0x01);
876 else
877 EMIT2(0xF0, 0x01);
878 goto xadd;
879 case BPF_STX | BPF_XADD | BPF_DW:
880 EMIT3(0xF0, add_2mod(0x48, dst_reg, src_reg), 0x01);
881xadd: if (is_imm8(insn->off))
882 EMIT2(add_2reg(0x40, dst_reg, src_reg), insn->off);
883 else
884 EMIT1_off32(add_2reg(0x80, dst_reg, src_reg),
885 insn->off);
886 break;
887
888 /* call */
889 case BPF_JMP | BPF_CALL:
890 func = (u8 *) __bpf_call_base + imm32;
891 jmp_offset = func - (image + addrs[i]);
892 if (seen_ld_abs) {
893 reload_skb_data = bpf_helper_changes_pkt_data(func);
894 if (reload_skb_data) {
895 EMIT1(0x57); /* push %rdi */
896 jmp_offset += 22; /* pop, mov, sub, mov */
897 } else {
898 EMIT2(0x41, 0x52); /* push %r10 */
899 EMIT2(0x41, 0x51); /* push %r9 */
900 /* need to adjust jmp offset, since
901 * pop %r9, pop %r10 take 4 bytes after call insn
902 */
903 jmp_offset += 4;
904 }
905 }
906 if (!imm32 || !is_simm32(jmp_offset)) {
907 pr_err("unsupported bpf func %d addr %p image %p\n",
908 imm32, func, image);
909 return -EINVAL;
910 }
911 EMIT1_off32(0xE8, jmp_offset);
912 if (seen_ld_abs) {
913 if (reload_skb_data) {
914 EMIT1(0x5F); /* pop %rdi */
915 emit_load_skb_data_hlen(&prog);
916 } else {
917 EMIT2(0x41, 0x59); /* pop %r9 */
918 EMIT2(0x41, 0x5A); /* pop %r10 */
919 }
920 }
921 break;
922
923 case BPF_JMP | BPF_TAIL_CALL:
924 emit_bpf_tail_call(&prog);
925 break;
926
927 /* cond jump */
928 case BPF_JMP | BPF_JEQ | BPF_X:
929 case BPF_JMP | BPF_JNE | BPF_X:
930 case BPF_JMP | BPF_JGT | BPF_X:
931 case BPF_JMP | BPF_JLT | BPF_X:
932 case BPF_JMP | BPF_JGE | BPF_X:
933 case BPF_JMP | BPF_JLE | BPF_X:
934 case BPF_JMP | BPF_JSGT | BPF_X:
935 case BPF_JMP | BPF_JSLT | BPF_X:
936 case BPF_JMP | BPF_JSGE | BPF_X:
937 case BPF_JMP | BPF_JSLE | BPF_X:
938 /* cmp dst_reg, src_reg */
939 EMIT3(add_2mod(0x48, dst_reg, src_reg), 0x39,
940 add_2reg(0xC0, dst_reg, src_reg));
941 goto emit_cond_jmp;
942
943 case BPF_JMP | BPF_JSET | BPF_X:
944 /* test dst_reg, src_reg */
945 EMIT3(add_2mod(0x48, dst_reg, src_reg), 0x85,
946 add_2reg(0xC0, dst_reg, src_reg));
947 goto emit_cond_jmp;
948
949 case BPF_JMP | BPF_JSET | BPF_K:
950 /* test dst_reg, imm32 */
951 EMIT1(add_1mod(0x48, dst_reg));
952 EMIT2_off32(0xF7, add_1reg(0xC0, dst_reg), imm32);
953 goto emit_cond_jmp;
954
955 case BPF_JMP | BPF_JEQ | BPF_K:
956 case BPF_JMP | BPF_JNE | BPF_K:
957 case BPF_JMP | BPF_JGT | BPF_K:
958 case BPF_JMP | BPF_JLT | BPF_K:
959 case BPF_JMP | BPF_JGE | BPF_K:
960 case BPF_JMP | BPF_JLE | BPF_K:
961 case BPF_JMP | BPF_JSGT | BPF_K:
962 case BPF_JMP | BPF_JSLT | BPF_K:
963 case BPF_JMP | BPF_JSGE | BPF_K:
964 case BPF_JMP | BPF_JSLE | BPF_K:
965 /* cmp dst_reg, imm8/32 */
966 EMIT1(add_1mod(0x48, dst_reg));
967
968 if (is_imm8(imm32))
969 EMIT3(0x83, add_1reg(0xF8, dst_reg), imm32);
970 else
971 EMIT2_off32(0x81, add_1reg(0xF8, dst_reg), imm32);
972
973emit_cond_jmp: /* convert BPF opcode to x86 */
974 switch (BPF_OP(insn->code)) {
975 case BPF_JEQ:
976 jmp_cond = X86_JE;
977 break;
978 case BPF_JSET:
979 case BPF_JNE:
980 jmp_cond = X86_JNE;
981 break;
982 case BPF_JGT:
983 /* GT is unsigned '>', JA in x86 */
984 jmp_cond = X86_JA;
985 break;
986 case BPF_JLT:
987 /* LT is unsigned '<', JB in x86 */
988 jmp_cond = X86_JB;
989 break;
990 case BPF_JGE:
991 /* GE is unsigned '>=', JAE in x86 */
992 jmp_cond = X86_JAE;
993 break;
994 case BPF_JLE:
995 /* LE is unsigned '<=', JBE in x86 */
996 jmp_cond = X86_JBE;
997 break;
998 case BPF_JSGT:
999 /* signed '>', GT in x86 */
1000 jmp_cond = X86_JG;
1001 break;
1002 case BPF_JSLT:
1003 /* signed '<', LT in x86 */
1004 jmp_cond = X86_JL;
1005 break;
1006 case BPF_JSGE:
1007 /* signed '>=', GE in x86 */
1008 jmp_cond = X86_JGE;
1009 break;
1010 case BPF_JSLE:
1011 /* signed '<=', LE in x86 */
1012 jmp_cond = X86_JLE;
1013 break;
1014 default: /* to silence gcc warning */
1015 return -EFAULT;
1016 }
1017 jmp_offset = addrs[i + insn->off] - addrs[i];
1018 if (is_imm8(jmp_offset)) {
1019 EMIT2(jmp_cond, jmp_offset);
1020 } else if (is_simm32(jmp_offset)) {
1021 EMIT2_off32(0x0F, jmp_cond + 0x10, jmp_offset);
1022 } else {
1023 pr_err("cond_jmp gen bug %llx\n", jmp_offset);
1024 return -EFAULT;
1025 }
1026
1027 break;
1028
1029 case BPF_JMP | BPF_JA:
1030 if (insn->off == -1)
1031 /* -1 jmp instructions will always jump
1032 * backwards two bytes. Explicitly handling
1033 * this case avoids wasting too many passes
1034 * when there are long sequences of replaced
1035 * dead code.
1036 */
1037 jmp_offset = -2;
1038 else
1039 jmp_offset = addrs[i + insn->off] - addrs[i];
1040
1041 if (!jmp_offset)
1042 /* optimize out nop jumps */
1043 break;
1044emit_jmp:
1045 if (is_imm8(jmp_offset)) {
1046 EMIT2(0xEB, jmp_offset);
1047 } else if (is_simm32(jmp_offset)) {
1048 EMIT1_off32(0xE9, jmp_offset);
1049 } else {
1050 pr_err("jmp gen bug %llx\n", jmp_offset);
1051 return -EFAULT;
1052 }
1053 break;
1054
1055 case BPF_LD | BPF_IND | BPF_W:
1056 func = sk_load_word;
1057 goto common_load;
1058 case BPF_LD | BPF_ABS | BPF_W:
1059 func = CHOOSE_LOAD_FUNC(imm32, sk_load_word);
1060common_load:
1061 ctx->seen_ld_abs = seen_ld_abs = true;
1062 jmp_offset = func - (image + addrs[i]);
1063 if (!func || !is_simm32(jmp_offset)) {
1064 pr_err("unsupported bpf func %d addr %p image %p\n",
1065 imm32, func, image);
1066 return -EINVAL;
1067 }
1068 if (BPF_MODE(insn->code) == BPF_ABS) {
1069 /* mov %esi, imm32 */
1070 EMIT1_off32(0xBE, imm32);
1071 } else {
1072 /* mov %rsi, src_reg */
1073 EMIT_mov(BPF_REG_2, src_reg);
1074 if (imm32) {
1075 if (is_imm8(imm32))
1076 /* add %esi, imm8 */
1077 EMIT3(0x83, 0xC6, imm32);
1078 else
1079 /* add %esi, imm32 */
1080 EMIT2_off32(0x81, 0xC6, imm32);
1081 }
1082 }
1083 /* skb pointer is in R6 (%rbx), it will be copied into
1084 * %rdi if skb_copy_bits() call is necessary.
1085 * sk_load_* helpers also use %r10 and %r9d.
1086 * See bpf_jit.S
1087 */
1088 if (seen_ax_reg)
1089 /* r10 = skb->data, mov %r10, off32(%rbx) */
1090 EMIT3_off32(0x4c, 0x8b, 0x93,
1091 offsetof(struct sk_buff, data));
1092 EMIT1_off32(0xE8, jmp_offset); /* call */
1093 break;
1094
1095 case BPF_LD | BPF_IND | BPF_H:
1096 func = sk_load_half;
1097 goto common_load;
1098 case BPF_LD | BPF_ABS | BPF_H:
1099 func = CHOOSE_LOAD_FUNC(imm32, sk_load_half);
1100 goto common_load;
1101 case BPF_LD | BPF_IND | BPF_B:
1102 func = sk_load_byte;
1103 goto common_load;
1104 case BPF_LD | BPF_ABS | BPF_B:
1105 func = CHOOSE_LOAD_FUNC(imm32, sk_load_byte);
1106 goto common_load;
1107
1108 case BPF_JMP | BPF_EXIT:
1109 if (seen_exit) {
1110 jmp_offset = ctx->cleanup_addr - addrs[i];
1111 goto emit_jmp;
1112 }
1113 seen_exit = true;
1114 /* update cleanup_addr */
1115 ctx->cleanup_addr = proglen;
1116 /* mov rbx, qword ptr [rbp+0] */
1117 EMIT4(0x48, 0x8B, 0x5D, 0);
1118 /* mov r13, qword ptr [rbp+8] */
1119 EMIT4(0x4C, 0x8B, 0x6D, 8);
1120 /* mov r14, qword ptr [rbp+16] */
1121 EMIT4(0x4C, 0x8B, 0x75, 16);
1122 /* mov r15, qword ptr [rbp+24] */
1123 EMIT4(0x4C, 0x8B, 0x7D, 24);
1124
1125 /* add rbp, AUX_STACK_SPACE */
1126 EMIT4(0x48, 0x83, 0xC5, AUX_STACK_SPACE);
1127 EMIT1(0xC9); /* leave */
1128 EMIT1(0xC3); /* ret */
1129 break;
1130
1131 default:
1132 /* By design x64 JIT should support all BPF instructions
1133 * This error will be seen if new instruction was added
1134 * to interpreter, but not to JIT
1135 * or if there is junk in bpf_prog
1136 */
1137 pr_err("bpf_jit: unknown opcode %02x\n", insn->code);
1138 return -EINVAL;
1139 }
1140
1141 ilen = prog - temp;
1142 if (ilen > BPF_MAX_INSN_SIZE) {
1143 pr_err("bpf_jit: fatal insn size error\n");
1144 return -EFAULT;
1145 }
1146
1147 if (image) {
1148 if (unlikely(proglen + ilen > oldproglen)) {
1149 pr_err("bpf_jit: fatal error\n");
1150 return -EFAULT;
1151 }
1152 memcpy(image + proglen, temp, ilen);
1153 }
1154 proglen += ilen;
1155 addrs[i] = proglen;
1156 prog = temp;
1157 }
1158 return proglen;
1159}
1160
1161struct x64_jit_data {
1162 struct bpf_binary_header *header;
1163 int *addrs;
1164 u8 *image;
1165 int proglen;
1166 struct jit_context ctx;
1167};
1168
1169struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog)
1170{
1171 struct bpf_binary_header *header = NULL;
1172 struct bpf_prog *tmp, *orig_prog = prog;
1173 struct x64_jit_data *jit_data;
1174 int proglen, oldproglen = 0;
1175 struct jit_context ctx = {};
1176 bool tmp_blinded = false;
1177 bool extra_pass = false;
1178 u8 *image = NULL;
1179 int *addrs;
1180 int pass;
1181 int i;
1182
1183 if (!prog->jit_requested)
1184 return orig_prog;
1185
1186 tmp = bpf_jit_blind_constants(prog);
1187 /* If blinding was requested and we failed during blinding,
1188 * we must fall back to the interpreter.
1189 */
1190 if (IS_ERR(tmp))
1191 return orig_prog;
1192 if (tmp != prog) {
1193 tmp_blinded = true;
1194 prog = tmp;
1195 }
1196
1197 jit_data = prog->aux->jit_data;
1198 if (!jit_data) {
1199 jit_data = kzalloc(sizeof(*jit_data), GFP_KERNEL);
1200 if (!jit_data) {
1201 prog = orig_prog;
1202 goto out;
1203 }
1204 prog->aux->jit_data = jit_data;
1205 }
1206 addrs = jit_data->addrs;
1207 if (addrs) {
1208 ctx = jit_data->ctx;
1209 oldproglen = jit_data->proglen;
1210 image = jit_data->image;
1211 header = jit_data->header;
1212 extra_pass = true;
1213 goto skip_init_addrs;
1214 }
1215 addrs = kmalloc(prog->len * sizeof(*addrs), GFP_KERNEL);
1216 if (!addrs) {
1217 prog = orig_prog;
1218 goto out_addrs;
1219 }
1220
1221 /* Before first pass, make a rough estimation of addrs[]
1222 * each bpf instruction is translated to less than 64 bytes
1223 */
1224 for (proglen = 0, i = 0; i < prog->len; i++) {
1225 proglen += 64;
1226 addrs[i] = proglen;
1227 }
1228 ctx.cleanup_addr = proglen;
1229skip_init_addrs:
1230
1231 /* JITed image shrinks with every pass and the loop iterates
1232 * until the image stops shrinking. Very large bpf programs
1233 * may converge on the last pass. In such case do one more
1234 * pass to emit the final image
1235 */
1236 for (pass = 0; pass < 20 || image; pass++) {
1237 proglen = do_jit(prog, addrs, image, oldproglen, &ctx);
1238 if (proglen <= 0) {
1239out_image:
1240 image = NULL;
1241 if (header)
1242 bpf_jit_binary_free(header);
1243 prog = orig_prog;
1244 goto out_addrs;
1245 }
1246 if (image) {
1247 if (proglen != oldproglen) {
1248 pr_err("bpf_jit: proglen=%d != oldproglen=%d\n",
1249 proglen, oldproglen);
1250 goto out_image;
1251 }
1252 break;
1253 }
1254 if (proglen == oldproglen) {
1255 header = bpf_jit_binary_alloc(proglen, &image,
1256 1, jit_fill_hole);
1257 if (!header) {
1258 prog = orig_prog;
1259 goto out_addrs;
1260 }
1261 }
1262 oldproglen = proglen;
1263 cond_resched();
1264 }
1265
1266 if (bpf_jit_enable > 1)
1267 bpf_jit_dump(prog->len, proglen, pass + 1, image);
1268
1269 if (image) {
1270 if (!prog->is_func || extra_pass) {
1271 bpf_jit_binary_lock_ro(header);
1272 } else {
1273 jit_data->addrs = addrs;
1274 jit_data->ctx = ctx;
1275 jit_data->proglen = proglen;
1276 jit_data->image = image;
1277 jit_data->header = header;
1278 }
1279 prog->bpf_func = (void *)image;
1280 prog->jited = 1;
1281 prog->jited_len = proglen;
1282 } else {
1283 prog = orig_prog;
1284 }
1285
1286 if (!image || !prog->is_func || extra_pass) {
1287out_addrs:
1288 kfree(addrs);
1289 kfree(jit_data);
1290 prog->aux->jit_data = NULL;
1291 }
1292out:
1293 if (tmp_blinded)
1294 bpf_jit_prog_release_other(prog, prog == orig_prog ?
1295 tmp : orig_prog);
1296 return prog;
1297}
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * BPF JIT compiler
4 *
5 * Copyright (C) 2011-2013 Eric Dumazet (eric.dumazet@gmail.com)
6 * Copyright (c) 2011-2014 PLUMgrid, http://plumgrid.com
7 */
8#include <linux/netdevice.h>
9#include <linux/filter.h>
10#include <linux/if_vlan.h>
11#include <linux/bpf.h>
12#include <linux/memory.h>
13#include <linux/sort.h>
14#include <asm/extable.h>
15#include <asm/ftrace.h>
16#include <asm/set_memory.h>
17#include <asm/nospec-branch.h>
18#include <asm/text-patching.h>
19#include <asm/unwind.h>
20#include <asm/cfi.h>
21
22static bool all_callee_regs_used[4] = {true, true, true, true};
23
24static u8 *emit_code(u8 *ptr, u32 bytes, unsigned int len)
25{
26 if (len == 1)
27 *ptr = bytes;
28 else if (len == 2)
29 *(u16 *)ptr = bytes;
30 else {
31 *(u32 *)ptr = bytes;
32 barrier();
33 }
34 return ptr + len;
35}
36
37#define EMIT(bytes, len) \
38 do { prog = emit_code(prog, bytes, len); } while (0)
39
40#define EMIT1(b1) EMIT(b1, 1)
41#define EMIT2(b1, b2) EMIT((b1) + ((b2) << 8), 2)
42#define EMIT3(b1, b2, b3) EMIT((b1) + ((b2) << 8) + ((b3) << 16), 3)
43#define EMIT4(b1, b2, b3, b4) EMIT((b1) + ((b2) << 8) + ((b3) << 16) + ((b4) << 24), 4)
44
45#define EMIT1_off32(b1, off) \
46 do { EMIT1(b1); EMIT(off, 4); } while (0)
47#define EMIT2_off32(b1, b2, off) \
48 do { EMIT2(b1, b2); EMIT(off, 4); } while (0)
49#define EMIT3_off32(b1, b2, b3, off) \
50 do { EMIT3(b1, b2, b3); EMIT(off, 4); } while (0)
51#define EMIT4_off32(b1, b2, b3, b4, off) \
52 do { EMIT4(b1, b2, b3, b4); EMIT(off, 4); } while (0)
53
54#ifdef CONFIG_X86_KERNEL_IBT
55#define EMIT_ENDBR() EMIT(gen_endbr(), 4)
56#define EMIT_ENDBR_POISON() EMIT(gen_endbr_poison(), 4)
57#else
58#define EMIT_ENDBR()
59#define EMIT_ENDBR_POISON()
60#endif
61
62static bool is_imm8(int value)
63{
64 return value <= 127 && value >= -128;
65}
66
67static bool is_simm32(s64 value)
68{
69 return value == (s64)(s32)value;
70}
71
72static bool is_uimm32(u64 value)
73{
74 return value == (u64)(u32)value;
75}
76
77/* mov dst, src */
78#define EMIT_mov(DST, SRC) \
79 do { \
80 if (DST != SRC) \
81 EMIT3(add_2mod(0x48, DST, SRC), 0x89, add_2reg(0xC0, DST, SRC)); \
82 } while (0)
83
84static int bpf_size_to_x86_bytes(int bpf_size)
85{
86 if (bpf_size == BPF_W)
87 return 4;
88 else if (bpf_size == BPF_H)
89 return 2;
90 else if (bpf_size == BPF_B)
91 return 1;
92 else if (bpf_size == BPF_DW)
93 return 4; /* imm32 */
94 else
95 return 0;
96}
97
98/*
99 * List of x86 cond jumps opcodes (. + s8)
100 * Add 0x10 (and an extra 0x0f) to generate far jumps (. + s32)
101 */
102#define X86_JB 0x72
103#define X86_JAE 0x73
104#define X86_JE 0x74
105#define X86_JNE 0x75
106#define X86_JBE 0x76
107#define X86_JA 0x77
108#define X86_JL 0x7C
109#define X86_JGE 0x7D
110#define X86_JLE 0x7E
111#define X86_JG 0x7F
112
113/* Pick a register outside of BPF range for JIT internal work */
114#define AUX_REG (MAX_BPF_JIT_REG + 1)
115#define X86_REG_R9 (MAX_BPF_JIT_REG + 2)
116#define X86_REG_R12 (MAX_BPF_JIT_REG + 3)
117
118/*
119 * The following table maps BPF registers to x86-64 registers.
120 *
121 * x86-64 register R12 is unused, since if used as base address
122 * register in load/store instructions, it always needs an
123 * extra byte of encoding and is callee saved.
124 *
125 * x86-64 register R9 is not used by BPF programs, but can be used by BPF
126 * trampoline. x86-64 register R10 is used for blinding (if enabled).
127 */
128static const int reg2hex[] = {
129 [BPF_REG_0] = 0, /* RAX */
130 [BPF_REG_1] = 7, /* RDI */
131 [BPF_REG_2] = 6, /* RSI */
132 [BPF_REG_3] = 2, /* RDX */
133 [BPF_REG_4] = 1, /* RCX */
134 [BPF_REG_5] = 0, /* R8 */
135 [BPF_REG_6] = 3, /* RBX callee saved */
136 [BPF_REG_7] = 5, /* R13 callee saved */
137 [BPF_REG_8] = 6, /* R14 callee saved */
138 [BPF_REG_9] = 7, /* R15 callee saved */
139 [BPF_REG_FP] = 5, /* RBP readonly */
140 [BPF_REG_AX] = 2, /* R10 temp register */
141 [AUX_REG] = 3, /* R11 temp register */
142 [X86_REG_R9] = 1, /* R9 register, 6th function argument */
143 [X86_REG_R12] = 4, /* R12 callee saved */
144};
145
146static const int reg2pt_regs[] = {
147 [BPF_REG_0] = offsetof(struct pt_regs, ax),
148 [BPF_REG_1] = offsetof(struct pt_regs, di),
149 [BPF_REG_2] = offsetof(struct pt_regs, si),
150 [BPF_REG_3] = offsetof(struct pt_regs, dx),
151 [BPF_REG_4] = offsetof(struct pt_regs, cx),
152 [BPF_REG_5] = offsetof(struct pt_regs, r8),
153 [BPF_REG_6] = offsetof(struct pt_regs, bx),
154 [BPF_REG_7] = offsetof(struct pt_regs, r13),
155 [BPF_REG_8] = offsetof(struct pt_regs, r14),
156 [BPF_REG_9] = offsetof(struct pt_regs, r15),
157};
158
159/*
160 * is_ereg() == true if BPF register 'reg' maps to x86-64 r8..r15
161 * which need extra byte of encoding.
162 * rax,rcx,...,rbp have simpler encoding
163 */
164static bool is_ereg(u32 reg)
165{
166 return (1 << reg) & (BIT(BPF_REG_5) |
167 BIT(AUX_REG) |
168 BIT(BPF_REG_7) |
169 BIT(BPF_REG_8) |
170 BIT(BPF_REG_9) |
171 BIT(X86_REG_R9) |
172 BIT(X86_REG_R12) |
173 BIT(BPF_REG_AX));
174}
175
176/*
177 * is_ereg_8l() == true if BPF register 'reg' is mapped to access x86-64
178 * lower 8-bit registers dil,sil,bpl,spl,r8b..r15b, which need extra byte
179 * of encoding. al,cl,dl,bl have simpler encoding.
180 */
181static bool is_ereg_8l(u32 reg)
182{
183 return is_ereg(reg) ||
184 (1 << reg) & (BIT(BPF_REG_1) |
185 BIT(BPF_REG_2) |
186 BIT(BPF_REG_FP));
187}
188
189static bool is_axreg(u32 reg)
190{
191 return reg == BPF_REG_0;
192}
193
194/* Add modifiers if 'reg' maps to x86-64 registers R8..R15 */
195static u8 add_1mod(u8 byte, u32 reg)
196{
197 if (is_ereg(reg))
198 byte |= 1;
199 return byte;
200}
201
202static u8 add_2mod(u8 byte, u32 r1, u32 r2)
203{
204 if (is_ereg(r1))
205 byte |= 1;
206 if (is_ereg(r2))
207 byte |= 4;
208 return byte;
209}
210
211static u8 add_3mod(u8 byte, u32 r1, u32 r2, u32 index)
212{
213 if (is_ereg(r1))
214 byte |= 1;
215 if (is_ereg(index))
216 byte |= 2;
217 if (is_ereg(r2))
218 byte |= 4;
219 return byte;
220}
221
222/* Encode 'dst_reg' register into x86-64 opcode 'byte' */
223static u8 add_1reg(u8 byte, u32 dst_reg)
224{
225 return byte + reg2hex[dst_reg];
226}
227
228/* Encode 'dst_reg' and 'src_reg' registers into x86-64 opcode 'byte' */
229static u8 add_2reg(u8 byte, u32 dst_reg, u32 src_reg)
230{
231 return byte + reg2hex[dst_reg] + (reg2hex[src_reg] << 3);
232}
233
234/* Some 1-byte opcodes for binary ALU operations */
235static u8 simple_alu_opcodes[] = {
236 [BPF_ADD] = 0x01,
237 [BPF_SUB] = 0x29,
238 [BPF_AND] = 0x21,
239 [BPF_OR] = 0x09,
240 [BPF_XOR] = 0x31,
241 [BPF_LSH] = 0xE0,
242 [BPF_RSH] = 0xE8,
243 [BPF_ARSH] = 0xF8,
244};
245
246static void jit_fill_hole(void *area, unsigned int size)
247{
248 /* Fill whole space with INT3 instructions */
249 memset(area, 0xcc, size);
250}
251
252int bpf_arch_text_invalidate(void *dst, size_t len)
253{
254 return IS_ERR_OR_NULL(text_poke_set(dst, 0xcc, len));
255}
256
257struct jit_context {
258 int cleanup_addr; /* Epilogue code offset */
259
260 /*
261 * Program specific offsets of labels in the code; these rely on the
262 * JIT doing at least 2 passes, recording the position on the first
263 * pass, only to generate the correct offset on the second pass.
264 */
265 int tail_call_direct_label;
266 int tail_call_indirect_label;
267};
268
269/* Maximum number of bytes emitted while JITing one eBPF insn */
270#define BPF_MAX_INSN_SIZE 128
271#define BPF_INSN_SAFETY 64
272
273/* Number of bytes emit_patch() needs to generate instructions */
274#define X86_PATCH_SIZE 5
275/* Number of bytes that will be skipped on tailcall */
276#define X86_TAIL_CALL_OFFSET (11 + ENDBR_INSN_SIZE)
277
278static void push_r12(u8 **pprog)
279{
280 u8 *prog = *pprog;
281
282 EMIT2(0x41, 0x54); /* push r12 */
283 *pprog = prog;
284}
285
286static void push_callee_regs(u8 **pprog, bool *callee_regs_used)
287{
288 u8 *prog = *pprog;
289
290 if (callee_regs_used[0])
291 EMIT1(0x53); /* push rbx */
292 if (callee_regs_used[1])
293 EMIT2(0x41, 0x55); /* push r13 */
294 if (callee_regs_used[2])
295 EMIT2(0x41, 0x56); /* push r14 */
296 if (callee_regs_used[3])
297 EMIT2(0x41, 0x57); /* push r15 */
298 *pprog = prog;
299}
300
301static void pop_r12(u8 **pprog)
302{
303 u8 *prog = *pprog;
304
305 EMIT2(0x41, 0x5C); /* pop r12 */
306 *pprog = prog;
307}
308
309static void pop_callee_regs(u8 **pprog, bool *callee_regs_used)
310{
311 u8 *prog = *pprog;
312
313 if (callee_regs_used[3])
314 EMIT2(0x41, 0x5F); /* pop r15 */
315 if (callee_regs_used[2])
316 EMIT2(0x41, 0x5E); /* pop r14 */
317 if (callee_regs_used[1])
318 EMIT2(0x41, 0x5D); /* pop r13 */
319 if (callee_regs_used[0])
320 EMIT1(0x5B); /* pop rbx */
321 *pprog = prog;
322}
323
324static void emit_nops(u8 **pprog, int len)
325{
326 u8 *prog = *pprog;
327 int i, noplen;
328
329 while (len > 0) {
330 noplen = len;
331
332 if (noplen > ASM_NOP_MAX)
333 noplen = ASM_NOP_MAX;
334
335 for (i = 0; i < noplen; i++)
336 EMIT1(x86_nops[noplen][i]);
337 len -= noplen;
338 }
339
340 *pprog = prog;
341}
342
343/*
344 * Emit the various CFI preambles, see asm/cfi.h and the comments about FineIBT
345 * in arch/x86/kernel/alternative.c
346 */
347
348static void emit_fineibt(u8 **pprog, u32 hash)
349{
350 u8 *prog = *pprog;
351
352 EMIT_ENDBR();
353 EMIT3_off32(0x41, 0x81, 0xea, hash); /* subl $hash, %r10d */
354 EMIT2(0x74, 0x07); /* jz.d8 +7 */
355 EMIT2(0x0f, 0x0b); /* ud2 */
356 EMIT1(0x90); /* nop */
357 EMIT_ENDBR_POISON();
358
359 *pprog = prog;
360}
361
362static void emit_kcfi(u8 **pprog, u32 hash)
363{
364 u8 *prog = *pprog;
365
366 EMIT1_off32(0xb8, hash); /* movl $hash, %eax */
367#ifdef CONFIG_CALL_PADDING
368 EMIT1(0x90);
369 EMIT1(0x90);
370 EMIT1(0x90);
371 EMIT1(0x90);
372 EMIT1(0x90);
373 EMIT1(0x90);
374 EMIT1(0x90);
375 EMIT1(0x90);
376 EMIT1(0x90);
377 EMIT1(0x90);
378 EMIT1(0x90);
379#endif
380 EMIT_ENDBR();
381
382 *pprog = prog;
383}
384
385static void emit_cfi(u8 **pprog, u32 hash)
386{
387 u8 *prog = *pprog;
388
389 switch (cfi_mode) {
390 case CFI_FINEIBT:
391 emit_fineibt(&prog, hash);
392 break;
393
394 case CFI_KCFI:
395 emit_kcfi(&prog, hash);
396 break;
397
398 default:
399 EMIT_ENDBR();
400 break;
401 }
402
403 *pprog = prog;
404}
405
406/*
407 * Emit x86-64 prologue code for BPF program.
408 * bpf_tail_call helper will skip the first X86_TAIL_CALL_OFFSET bytes
409 * while jumping to another program
410 */
411static void emit_prologue(u8 **pprog, u32 stack_depth, bool ebpf_from_cbpf,
412 bool tail_call_reachable, bool is_subprog,
413 bool is_exception_cb)
414{
415 u8 *prog = *pprog;
416
417 emit_cfi(&prog, is_subprog ? cfi_bpf_subprog_hash : cfi_bpf_hash);
418 /* BPF trampoline can be made to work without these nops,
419 * but let's waste 5 bytes for now and optimize later
420 */
421 emit_nops(&prog, X86_PATCH_SIZE);
422 if (!ebpf_from_cbpf) {
423 if (tail_call_reachable && !is_subprog)
424 /* When it's the entry of the whole tailcall context,
425 * zeroing rax means initialising tail_call_cnt.
426 */
427 EMIT2(0x31, 0xC0); /* xor eax, eax */
428 else
429 /* Keep the same instruction layout. */
430 EMIT2(0x66, 0x90); /* nop2 */
431 }
432 /* Exception callback receives FP as third parameter */
433 if (is_exception_cb) {
434 EMIT3(0x48, 0x89, 0xF4); /* mov rsp, rsi */
435 EMIT3(0x48, 0x89, 0xD5); /* mov rbp, rdx */
436 /* The main frame must have exception_boundary as true, so we
437 * first restore those callee-saved regs from stack, before
438 * reusing the stack frame.
439 */
440 pop_callee_regs(&prog, all_callee_regs_used);
441 pop_r12(&prog);
442 /* Reset the stack frame. */
443 EMIT3(0x48, 0x89, 0xEC); /* mov rsp, rbp */
444 } else {
445 EMIT1(0x55); /* push rbp */
446 EMIT3(0x48, 0x89, 0xE5); /* mov rbp, rsp */
447 }
448
449 /* X86_TAIL_CALL_OFFSET is here */
450 EMIT_ENDBR();
451
452 /* sub rsp, rounded_stack_depth */
453 if (stack_depth)
454 EMIT3_off32(0x48, 0x81, 0xEC, round_up(stack_depth, 8));
455 if (tail_call_reachable)
456 EMIT1(0x50); /* push rax */
457 *pprog = prog;
458}
459
460static int emit_patch(u8 **pprog, void *func, void *ip, u8 opcode)
461{
462 u8 *prog = *pprog;
463 s64 offset;
464
465 offset = func - (ip + X86_PATCH_SIZE);
466 if (!is_simm32(offset)) {
467 pr_err("Target call %p is out of range\n", func);
468 return -ERANGE;
469 }
470 EMIT1_off32(opcode, offset);
471 *pprog = prog;
472 return 0;
473}
474
475static int emit_call(u8 **pprog, void *func, void *ip)
476{
477 return emit_patch(pprog, func, ip, 0xE8);
478}
479
480static int emit_rsb_call(u8 **pprog, void *func, void *ip)
481{
482 OPTIMIZER_HIDE_VAR(func);
483 ip += x86_call_depth_emit_accounting(pprog, func, ip);
484 return emit_patch(pprog, func, ip, 0xE8);
485}
486
487static int emit_jump(u8 **pprog, void *func, void *ip)
488{
489 return emit_patch(pprog, func, ip, 0xE9);
490}
491
492static int __bpf_arch_text_poke(void *ip, enum bpf_text_poke_type t,
493 void *old_addr, void *new_addr)
494{
495 const u8 *nop_insn = x86_nops[5];
496 u8 old_insn[X86_PATCH_SIZE];
497 u8 new_insn[X86_PATCH_SIZE];
498 u8 *prog;
499 int ret;
500
501 memcpy(old_insn, nop_insn, X86_PATCH_SIZE);
502 if (old_addr) {
503 prog = old_insn;
504 ret = t == BPF_MOD_CALL ?
505 emit_call(&prog, old_addr, ip) :
506 emit_jump(&prog, old_addr, ip);
507 if (ret)
508 return ret;
509 }
510
511 memcpy(new_insn, nop_insn, X86_PATCH_SIZE);
512 if (new_addr) {
513 prog = new_insn;
514 ret = t == BPF_MOD_CALL ?
515 emit_call(&prog, new_addr, ip) :
516 emit_jump(&prog, new_addr, ip);
517 if (ret)
518 return ret;
519 }
520
521 ret = -EBUSY;
522 mutex_lock(&text_mutex);
523 if (memcmp(ip, old_insn, X86_PATCH_SIZE))
524 goto out;
525 ret = 1;
526 if (memcmp(ip, new_insn, X86_PATCH_SIZE)) {
527 text_poke_bp(ip, new_insn, X86_PATCH_SIZE, NULL);
528 ret = 0;
529 }
530out:
531 mutex_unlock(&text_mutex);
532 return ret;
533}
534
535int bpf_arch_text_poke(void *ip, enum bpf_text_poke_type t,
536 void *old_addr, void *new_addr)
537{
538 if (!is_kernel_text((long)ip) &&
539 !is_bpf_text_address((long)ip))
540 /* BPF poking in modules is not supported */
541 return -EINVAL;
542
543 /*
544 * See emit_prologue(), for IBT builds the trampoline hook is preceded
545 * with an ENDBR instruction.
546 */
547 if (is_endbr(*(u32 *)ip))
548 ip += ENDBR_INSN_SIZE;
549
550 return __bpf_arch_text_poke(ip, t, old_addr, new_addr);
551}
552
553#define EMIT_LFENCE() EMIT3(0x0F, 0xAE, 0xE8)
554
555static void emit_indirect_jump(u8 **pprog, int reg, u8 *ip)
556{
557 u8 *prog = *pprog;
558
559 if (cpu_feature_enabled(X86_FEATURE_RETPOLINE_LFENCE)) {
560 EMIT_LFENCE();
561 EMIT2(0xFF, 0xE0 + reg);
562 } else if (cpu_feature_enabled(X86_FEATURE_RETPOLINE)) {
563 OPTIMIZER_HIDE_VAR(reg);
564 if (cpu_feature_enabled(X86_FEATURE_CALL_DEPTH))
565 emit_jump(&prog, &__x86_indirect_jump_thunk_array[reg], ip);
566 else
567 emit_jump(&prog, &__x86_indirect_thunk_array[reg], ip);
568 } else {
569 EMIT2(0xFF, 0xE0 + reg); /* jmp *%\reg */
570 if (IS_ENABLED(CONFIG_MITIGATION_RETPOLINE) || IS_ENABLED(CONFIG_MITIGATION_SLS))
571 EMIT1(0xCC); /* int3 */
572 }
573
574 *pprog = prog;
575}
576
577static void emit_return(u8 **pprog, u8 *ip)
578{
579 u8 *prog = *pprog;
580
581 if (cpu_feature_enabled(X86_FEATURE_RETHUNK)) {
582 emit_jump(&prog, x86_return_thunk, ip);
583 } else {
584 EMIT1(0xC3); /* ret */
585 if (IS_ENABLED(CONFIG_MITIGATION_SLS))
586 EMIT1(0xCC); /* int3 */
587 }
588
589 *pprog = prog;
590}
591
592/*
593 * Generate the following code:
594 *
595 * ... bpf_tail_call(void *ctx, struct bpf_array *array, u64 index) ...
596 * if (index >= array->map.max_entries)
597 * goto out;
598 * if (tail_call_cnt++ >= MAX_TAIL_CALL_CNT)
599 * goto out;
600 * prog = array->ptrs[index];
601 * if (prog == NULL)
602 * goto out;
603 * goto *(prog->bpf_func + prologue_size);
604 * out:
605 */
606static void emit_bpf_tail_call_indirect(struct bpf_prog *bpf_prog,
607 u8 **pprog, bool *callee_regs_used,
608 u32 stack_depth, u8 *ip,
609 struct jit_context *ctx)
610{
611 int tcc_off = -4 - round_up(stack_depth, 8);
612 u8 *prog = *pprog, *start = *pprog;
613 int offset;
614
615 /*
616 * rdi - pointer to ctx
617 * rsi - pointer to bpf_array
618 * rdx - index in bpf_array
619 */
620
621 /*
622 * if (index >= array->map.max_entries)
623 * goto out;
624 */
625 EMIT2(0x89, 0xD2); /* mov edx, edx */
626 EMIT3(0x39, 0x56, /* cmp dword ptr [rsi + 16], edx */
627 offsetof(struct bpf_array, map.max_entries));
628
629 offset = ctx->tail_call_indirect_label - (prog + 2 - start);
630 EMIT2(X86_JBE, offset); /* jbe out */
631
632 /*
633 * if (tail_call_cnt++ >= MAX_TAIL_CALL_CNT)
634 * goto out;
635 */
636 EMIT2_off32(0x8B, 0x85, tcc_off); /* mov eax, dword ptr [rbp - tcc_off] */
637 EMIT3(0x83, 0xF8, MAX_TAIL_CALL_CNT); /* cmp eax, MAX_TAIL_CALL_CNT */
638
639 offset = ctx->tail_call_indirect_label - (prog + 2 - start);
640 EMIT2(X86_JAE, offset); /* jae out */
641 EMIT3(0x83, 0xC0, 0x01); /* add eax, 1 */
642 EMIT2_off32(0x89, 0x85, tcc_off); /* mov dword ptr [rbp - tcc_off], eax */
643
644 /* prog = array->ptrs[index]; */
645 EMIT4_off32(0x48, 0x8B, 0x8C, 0xD6, /* mov rcx, [rsi + rdx * 8 + offsetof(...)] */
646 offsetof(struct bpf_array, ptrs));
647
648 /*
649 * if (prog == NULL)
650 * goto out;
651 */
652 EMIT3(0x48, 0x85, 0xC9); /* test rcx,rcx */
653
654 offset = ctx->tail_call_indirect_label - (prog + 2 - start);
655 EMIT2(X86_JE, offset); /* je out */
656
657 if (bpf_prog->aux->exception_boundary) {
658 pop_callee_regs(&prog, all_callee_regs_used);
659 pop_r12(&prog);
660 } else {
661 pop_callee_regs(&prog, callee_regs_used);
662 if (bpf_arena_get_kern_vm_start(bpf_prog->aux->arena))
663 pop_r12(&prog);
664 }
665
666 EMIT1(0x58); /* pop rax */
667 if (stack_depth)
668 EMIT3_off32(0x48, 0x81, 0xC4, /* add rsp, sd */
669 round_up(stack_depth, 8));
670
671 /* goto *(prog->bpf_func + X86_TAIL_CALL_OFFSET); */
672 EMIT4(0x48, 0x8B, 0x49, /* mov rcx, qword ptr [rcx + 32] */
673 offsetof(struct bpf_prog, bpf_func));
674 EMIT4(0x48, 0x83, 0xC1, /* add rcx, X86_TAIL_CALL_OFFSET */
675 X86_TAIL_CALL_OFFSET);
676 /*
677 * Now we're ready to jump into next BPF program
678 * rdi == ctx (1st arg)
679 * rcx == prog->bpf_func + X86_TAIL_CALL_OFFSET
680 */
681 emit_indirect_jump(&prog, 1 /* rcx */, ip + (prog - start));
682
683 /* out: */
684 ctx->tail_call_indirect_label = prog - start;
685 *pprog = prog;
686}
687
688static void emit_bpf_tail_call_direct(struct bpf_prog *bpf_prog,
689 struct bpf_jit_poke_descriptor *poke,
690 u8 **pprog, u8 *ip,
691 bool *callee_regs_used, u32 stack_depth,
692 struct jit_context *ctx)
693{
694 int tcc_off = -4 - round_up(stack_depth, 8);
695 u8 *prog = *pprog, *start = *pprog;
696 int offset;
697
698 /*
699 * if (tail_call_cnt++ >= MAX_TAIL_CALL_CNT)
700 * goto out;
701 */
702 EMIT2_off32(0x8B, 0x85, tcc_off); /* mov eax, dword ptr [rbp - tcc_off] */
703 EMIT3(0x83, 0xF8, MAX_TAIL_CALL_CNT); /* cmp eax, MAX_TAIL_CALL_CNT */
704
705 offset = ctx->tail_call_direct_label - (prog + 2 - start);
706 EMIT2(X86_JAE, offset); /* jae out */
707 EMIT3(0x83, 0xC0, 0x01); /* add eax, 1 */
708 EMIT2_off32(0x89, 0x85, tcc_off); /* mov dword ptr [rbp - tcc_off], eax */
709
710 poke->tailcall_bypass = ip + (prog - start);
711 poke->adj_off = X86_TAIL_CALL_OFFSET;
712 poke->tailcall_target = ip + ctx->tail_call_direct_label - X86_PATCH_SIZE;
713 poke->bypass_addr = (u8 *)poke->tailcall_target + X86_PATCH_SIZE;
714
715 emit_jump(&prog, (u8 *)poke->tailcall_target + X86_PATCH_SIZE,
716 poke->tailcall_bypass);
717
718 if (bpf_prog->aux->exception_boundary) {
719 pop_callee_regs(&prog, all_callee_regs_used);
720 pop_r12(&prog);
721 } else {
722 pop_callee_regs(&prog, callee_regs_used);
723 if (bpf_arena_get_kern_vm_start(bpf_prog->aux->arena))
724 pop_r12(&prog);
725 }
726
727 EMIT1(0x58); /* pop rax */
728 if (stack_depth)
729 EMIT3_off32(0x48, 0x81, 0xC4, round_up(stack_depth, 8));
730
731 emit_nops(&prog, X86_PATCH_SIZE);
732
733 /* out: */
734 ctx->tail_call_direct_label = prog - start;
735
736 *pprog = prog;
737}
738
739static void bpf_tail_call_direct_fixup(struct bpf_prog *prog)
740{
741 struct bpf_jit_poke_descriptor *poke;
742 struct bpf_array *array;
743 struct bpf_prog *target;
744 int i, ret;
745
746 for (i = 0; i < prog->aux->size_poke_tab; i++) {
747 poke = &prog->aux->poke_tab[i];
748 if (poke->aux && poke->aux != prog->aux)
749 continue;
750
751 WARN_ON_ONCE(READ_ONCE(poke->tailcall_target_stable));
752
753 if (poke->reason != BPF_POKE_REASON_TAIL_CALL)
754 continue;
755
756 array = container_of(poke->tail_call.map, struct bpf_array, map);
757 mutex_lock(&array->aux->poke_mutex);
758 target = array->ptrs[poke->tail_call.key];
759 if (target) {
760 ret = __bpf_arch_text_poke(poke->tailcall_target,
761 BPF_MOD_JUMP, NULL,
762 (u8 *)target->bpf_func +
763 poke->adj_off);
764 BUG_ON(ret < 0);
765 ret = __bpf_arch_text_poke(poke->tailcall_bypass,
766 BPF_MOD_JUMP,
767 (u8 *)poke->tailcall_target +
768 X86_PATCH_SIZE, NULL);
769 BUG_ON(ret < 0);
770 }
771 WRITE_ONCE(poke->tailcall_target_stable, true);
772 mutex_unlock(&array->aux->poke_mutex);
773 }
774}
775
776static void emit_mov_imm32(u8 **pprog, bool sign_propagate,
777 u32 dst_reg, const u32 imm32)
778{
779 u8 *prog = *pprog;
780 u8 b1, b2, b3;
781
782 /*
783 * Optimization: if imm32 is positive, use 'mov %eax, imm32'
784 * (which zero-extends imm32) to save 2 bytes.
785 */
786 if (sign_propagate && (s32)imm32 < 0) {
787 /* 'mov %rax, imm32' sign extends imm32 */
788 b1 = add_1mod(0x48, dst_reg);
789 b2 = 0xC7;
790 b3 = 0xC0;
791 EMIT3_off32(b1, b2, add_1reg(b3, dst_reg), imm32);
792 goto done;
793 }
794
795 /*
796 * Optimization: if imm32 is zero, use 'xor %eax, %eax'
797 * to save 3 bytes.
798 */
799 if (imm32 == 0) {
800 if (is_ereg(dst_reg))
801 EMIT1(add_2mod(0x40, dst_reg, dst_reg));
802 b2 = 0x31; /* xor */
803 b3 = 0xC0;
804 EMIT2(b2, add_2reg(b3, dst_reg, dst_reg));
805 goto done;
806 }
807
808 /* mov %eax, imm32 */
809 if (is_ereg(dst_reg))
810 EMIT1(add_1mod(0x40, dst_reg));
811 EMIT1_off32(add_1reg(0xB8, dst_reg), imm32);
812done:
813 *pprog = prog;
814}
815
816static void emit_mov_imm64(u8 **pprog, u32 dst_reg,
817 const u32 imm32_hi, const u32 imm32_lo)
818{
819 u8 *prog = *pprog;
820
821 if (is_uimm32(((u64)imm32_hi << 32) | (u32)imm32_lo)) {
822 /*
823 * For emitting plain u32, where sign bit must not be
824 * propagated LLVM tends to load imm64 over mov32
825 * directly, so save couple of bytes by just doing
826 * 'mov %eax, imm32' instead.
827 */
828 emit_mov_imm32(&prog, false, dst_reg, imm32_lo);
829 } else {
830 /* movabsq rax, imm64 */
831 EMIT2(add_1mod(0x48, dst_reg), add_1reg(0xB8, dst_reg));
832 EMIT(imm32_lo, 4);
833 EMIT(imm32_hi, 4);
834 }
835
836 *pprog = prog;
837}
838
839static void emit_mov_reg(u8 **pprog, bool is64, u32 dst_reg, u32 src_reg)
840{
841 u8 *prog = *pprog;
842
843 if (is64) {
844 /* mov dst, src */
845 EMIT_mov(dst_reg, src_reg);
846 } else {
847 /* mov32 dst, src */
848 if (is_ereg(dst_reg) || is_ereg(src_reg))
849 EMIT1(add_2mod(0x40, dst_reg, src_reg));
850 EMIT2(0x89, add_2reg(0xC0, dst_reg, src_reg));
851 }
852
853 *pprog = prog;
854}
855
856static void emit_movsx_reg(u8 **pprog, int num_bits, bool is64, u32 dst_reg,
857 u32 src_reg)
858{
859 u8 *prog = *pprog;
860
861 if (is64) {
862 /* movs[b,w,l]q dst, src */
863 if (num_bits == 8)
864 EMIT4(add_2mod(0x48, src_reg, dst_reg), 0x0f, 0xbe,
865 add_2reg(0xC0, src_reg, dst_reg));
866 else if (num_bits == 16)
867 EMIT4(add_2mod(0x48, src_reg, dst_reg), 0x0f, 0xbf,
868 add_2reg(0xC0, src_reg, dst_reg));
869 else if (num_bits == 32)
870 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x63,
871 add_2reg(0xC0, src_reg, dst_reg));
872 } else {
873 /* movs[b,w]l dst, src */
874 if (num_bits == 8) {
875 EMIT4(add_2mod(0x40, src_reg, dst_reg), 0x0f, 0xbe,
876 add_2reg(0xC0, src_reg, dst_reg));
877 } else if (num_bits == 16) {
878 if (is_ereg(dst_reg) || is_ereg(src_reg))
879 EMIT1(add_2mod(0x40, src_reg, dst_reg));
880 EMIT3(add_2mod(0x0f, src_reg, dst_reg), 0xbf,
881 add_2reg(0xC0, src_reg, dst_reg));
882 }
883 }
884
885 *pprog = prog;
886}
887
888/* Emit the suffix (ModR/M etc) for addressing *(ptr_reg + off) and val_reg */
889static void emit_insn_suffix(u8 **pprog, u32 ptr_reg, u32 val_reg, int off)
890{
891 u8 *prog = *pprog;
892
893 if (is_imm8(off)) {
894 /* 1-byte signed displacement.
895 *
896 * If off == 0 we could skip this and save one extra byte, but
897 * special case of x86 R13 which always needs an offset is not
898 * worth the hassle
899 */
900 EMIT2(add_2reg(0x40, ptr_reg, val_reg), off);
901 } else {
902 /* 4-byte signed displacement */
903 EMIT1_off32(add_2reg(0x80, ptr_reg, val_reg), off);
904 }
905 *pprog = prog;
906}
907
908static void emit_insn_suffix_SIB(u8 **pprog, u32 ptr_reg, u32 val_reg, u32 index_reg, int off)
909{
910 u8 *prog = *pprog;
911
912 if (is_imm8(off)) {
913 EMIT3(add_2reg(0x44, BPF_REG_0, val_reg), add_2reg(0, ptr_reg, index_reg) /* SIB */, off);
914 } else {
915 EMIT2_off32(add_2reg(0x84, BPF_REG_0, val_reg), add_2reg(0, ptr_reg, index_reg) /* SIB */, off);
916 }
917 *pprog = prog;
918}
919
920/*
921 * Emit a REX byte if it will be necessary to address these registers
922 */
923static void maybe_emit_mod(u8 **pprog, u32 dst_reg, u32 src_reg, bool is64)
924{
925 u8 *prog = *pprog;
926
927 if (is64)
928 EMIT1(add_2mod(0x48, dst_reg, src_reg));
929 else if (is_ereg(dst_reg) || is_ereg(src_reg))
930 EMIT1(add_2mod(0x40, dst_reg, src_reg));
931 *pprog = prog;
932}
933
934/*
935 * Similar version of maybe_emit_mod() for a single register
936 */
937static void maybe_emit_1mod(u8 **pprog, u32 reg, bool is64)
938{
939 u8 *prog = *pprog;
940
941 if (is64)
942 EMIT1(add_1mod(0x48, reg));
943 else if (is_ereg(reg))
944 EMIT1(add_1mod(0x40, reg));
945 *pprog = prog;
946}
947
948/* LDX: dst_reg = *(u8*)(src_reg + off) */
949static void emit_ldx(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off)
950{
951 u8 *prog = *pprog;
952
953 switch (size) {
954 case BPF_B:
955 /* Emit 'movzx rax, byte ptr [rax + off]' */
956 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xB6);
957 break;
958 case BPF_H:
959 /* Emit 'movzx rax, word ptr [rax + off]' */
960 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xB7);
961 break;
962 case BPF_W:
963 /* Emit 'mov eax, dword ptr [rax+0x14]' */
964 if (is_ereg(dst_reg) || is_ereg(src_reg))
965 EMIT2(add_2mod(0x40, src_reg, dst_reg), 0x8B);
966 else
967 EMIT1(0x8B);
968 break;
969 case BPF_DW:
970 /* Emit 'mov rax, qword ptr [rax+0x14]' */
971 EMIT2(add_2mod(0x48, src_reg, dst_reg), 0x8B);
972 break;
973 }
974 emit_insn_suffix(&prog, src_reg, dst_reg, off);
975 *pprog = prog;
976}
977
978/* LDSX: dst_reg = *(s8*)(src_reg + off) */
979static void emit_ldsx(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off)
980{
981 u8 *prog = *pprog;
982
983 switch (size) {
984 case BPF_B:
985 /* Emit 'movsx rax, byte ptr [rax + off]' */
986 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xBE);
987 break;
988 case BPF_H:
989 /* Emit 'movsx rax, word ptr [rax + off]' */
990 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xBF);
991 break;
992 case BPF_W:
993 /* Emit 'movsx rax, dword ptr [rax+0x14]' */
994 EMIT2(add_2mod(0x48, src_reg, dst_reg), 0x63);
995 break;
996 }
997 emit_insn_suffix(&prog, src_reg, dst_reg, off);
998 *pprog = prog;
999}
1000
1001static void emit_ldx_index(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, u32 index_reg, int off)
1002{
1003 u8 *prog = *pprog;
1004
1005 switch (size) {
1006 case BPF_B:
1007 /* movzx rax, byte ptr [rax + r12 + off] */
1008 EMIT3(add_3mod(0x40, src_reg, dst_reg, index_reg), 0x0F, 0xB6);
1009 break;
1010 case BPF_H:
1011 /* movzx rax, word ptr [rax + r12 + off] */
1012 EMIT3(add_3mod(0x40, src_reg, dst_reg, index_reg), 0x0F, 0xB7);
1013 break;
1014 case BPF_W:
1015 /* mov eax, dword ptr [rax + r12 + off] */
1016 EMIT2(add_3mod(0x40, src_reg, dst_reg, index_reg), 0x8B);
1017 break;
1018 case BPF_DW:
1019 /* mov rax, qword ptr [rax + r12 + off] */
1020 EMIT2(add_3mod(0x48, src_reg, dst_reg, index_reg), 0x8B);
1021 break;
1022 }
1023 emit_insn_suffix_SIB(&prog, src_reg, dst_reg, index_reg, off);
1024 *pprog = prog;
1025}
1026
1027static void emit_ldx_r12(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off)
1028{
1029 emit_ldx_index(pprog, size, dst_reg, src_reg, X86_REG_R12, off);
1030}
1031
1032/* STX: *(u8*)(dst_reg + off) = src_reg */
1033static void emit_stx(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off)
1034{
1035 u8 *prog = *pprog;
1036
1037 switch (size) {
1038 case BPF_B:
1039 /* Emit 'mov byte ptr [rax + off], al' */
1040 if (is_ereg(dst_reg) || is_ereg_8l(src_reg))
1041 /* Add extra byte for eregs or SIL,DIL,BPL in src_reg */
1042 EMIT2(add_2mod(0x40, dst_reg, src_reg), 0x88);
1043 else
1044 EMIT1(0x88);
1045 break;
1046 case BPF_H:
1047 if (is_ereg(dst_reg) || is_ereg(src_reg))
1048 EMIT3(0x66, add_2mod(0x40, dst_reg, src_reg), 0x89);
1049 else
1050 EMIT2(0x66, 0x89);
1051 break;
1052 case BPF_W:
1053 if (is_ereg(dst_reg) || is_ereg(src_reg))
1054 EMIT2(add_2mod(0x40, dst_reg, src_reg), 0x89);
1055 else
1056 EMIT1(0x89);
1057 break;
1058 case BPF_DW:
1059 EMIT2(add_2mod(0x48, dst_reg, src_reg), 0x89);
1060 break;
1061 }
1062 emit_insn_suffix(&prog, dst_reg, src_reg, off);
1063 *pprog = prog;
1064}
1065
1066/* STX: *(u8*)(dst_reg + index_reg + off) = src_reg */
1067static void emit_stx_index(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, u32 index_reg, int off)
1068{
1069 u8 *prog = *pprog;
1070
1071 switch (size) {
1072 case BPF_B:
1073 /* mov byte ptr [rax + r12 + off], al */
1074 EMIT2(add_3mod(0x40, dst_reg, src_reg, index_reg), 0x88);
1075 break;
1076 case BPF_H:
1077 /* mov word ptr [rax + r12 + off], ax */
1078 EMIT3(0x66, add_3mod(0x40, dst_reg, src_reg, index_reg), 0x89);
1079 break;
1080 case BPF_W:
1081 /* mov dword ptr [rax + r12 + 1], eax */
1082 EMIT2(add_3mod(0x40, dst_reg, src_reg, index_reg), 0x89);
1083 break;
1084 case BPF_DW:
1085 /* mov qword ptr [rax + r12 + 1], rax */
1086 EMIT2(add_3mod(0x48, dst_reg, src_reg, index_reg), 0x89);
1087 break;
1088 }
1089 emit_insn_suffix_SIB(&prog, dst_reg, src_reg, index_reg, off);
1090 *pprog = prog;
1091}
1092
1093static void emit_stx_r12(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off)
1094{
1095 emit_stx_index(pprog, size, dst_reg, src_reg, X86_REG_R12, off);
1096}
1097
1098/* ST: *(u8*)(dst_reg + index_reg + off) = imm32 */
1099static void emit_st_index(u8 **pprog, u32 size, u32 dst_reg, u32 index_reg, int off, int imm)
1100{
1101 u8 *prog = *pprog;
1102
1103 switch (size) {
1104 case BPF_B:
1105 /* mov byte ptr [rax + r12 + off], imm8 */
1106 EMIT2(add_3mod(0x40, dst_reg, 0, index_reg), 0xC6);
1107 break;
1108 case BPF_H:
1109 /* mov word ptr [rax + r12 + off], imm16 */
1110 EMIT3(0x66, add_3mod(0x40, dst_reg, 0, index_reg), 0xC7);
1111 break;
1112 case BPF_W:
1113 /* mov dword ptr [rax + r12 + 1], imm32 */
1114 EMIT2(add_3mod(0x40, dst_reg, 0, index_reg), 0xC7);
1115 break;
1116 case BPF_DW:
1117 /* mov qword ptr [rax + r12 + 1], imm32 */
1118 EMIT2(add_3mod(0x48, dst_reg, 0, index_reg), 0xC7);
1119 break;
1120 }
1121 emit_insn_suffix_SIB(&prog, dst_reg, 0, index_reg, off);
1122 EMIT(imm, bpf_size_to_x86_bytes(size));
1123 *pprog = prog;
1124}
1125
1126static void emit_st_r12(u8 **pprog, u32 size, u32 dst_reg, int off, int imm)
1127{
1128 emit_st_index(pprog, size, dst_reg, X86_REG_R12, off, imm);
1129}
1130
1131static int emit_atomic(u8 **pprog, u8 atomic_op,
1132 u32 dst_reg, u32 src_reg, s16 off, u8 bpf_size)
1133{
1134 u8 *prog = *pprog;
1135
1136 EMIT1(0xF0); /* lock prefix */
1137
1138 maybe_emit_mod(&prog, dst_reg, src_reg, bpf_size == BPF_DW);
1139
1140 /* emit opcode */
1141 switch (atomic_op) {
1142 case BPF_ADD:
1143 case BPF_AND:
1144 case BPF_OR:
1145 case BPF_XOR:
1146 /* lock *(u32/u64*)(dst_reg + off) <op>= src_reg */
1147 EMIT1(simple_alu_opcodes[atomic_op]);
1148 break;
1149 case BPF_ADD | BPF_FETCH:
1150 /* src_reg = atomic_fetch_add(dst_reg + off, src_reg); */
1151 EMIT2(0x0F, 0xC1);
1152 break;
1153 case BPF_XCHG:
1154 /* src_reg = atomic_xchg(dst_reg + off, src_reg); */
1155 EMIT1(0x87);
1156 break;
1157 case BPF_CMPXCHG:
1158 /* r0 = atomic_cmpxchg(dst_reg + off, r0, src_reg); */
1159 EMIT2(0x0F, 0xB1);
1160 break;
1161 default:
1162 pr_err("bpf_jit: unknown atomic opcode %02x\n", atomic_op);
1163 return -EFAULT;
1164 }
1165
1166 emit_insn_suffix(&prog, dst_reg, src_reg, off);
1167
1168 *pprog = prog;
1169 return 0;
1170}
1171
1172#define DONT_CLEAR 1
1173
1174bool ex_handler_bpf(const struct exception_table_entry *x, struct pt_regs *regs)
1175{
1176 u32 reg = x->fixup >> 8;
1177
1178 /* jump over faulting load and clear dest register */
1179 if (reg != DONT_CLEAR)
1180 *(unsigned long *)((void *)regs + reg) = 0;
1181 regs->ip += x->fixup & 0xff;
1182 return true;
1183}
1184
1185static void detect_reg_usage(struct bpf_insn *insn, int insn_cnt,
1186 bool *regs_used, bool *tail_call_seen)
1187{
1188 int i;
1189
1190 for (i = 1; i <= insn_cnt; i++, insn++) {
1191 if (insn->code == (BPF_JMP | BPF_TAIL_CALL))
1192 *tail_call_seen = true;
1193 if (insn->dst_reg == BPF_REG_6 || insn->src_reg == BPF_REG_6)
1194 regs_used[0] = true;
1195 if (insn->dst_reg == BPF_REG_7 || insn->src_reg == BPF_REG_7)
1196 regs_used[1] = true;
1197 if (insn->dst_reg == BPF_REG_8 || insn->src_reg == BPF_REG_8)
1198 regs_used[2] = true;
1199 if (insn->dst_reg == BPF_REG_9 || insn->src_reg == BPF_REG_9)
1200 regs_used[3] = true;
1201 }
1202}
1203
1204/* emit the 3-byte VEX prefix
1205 *
1206 * r: same as rex.r, extra bit for ModRM reg field
1207 * x: same as rex.x, extra bit for SIB index field
1208 * b: same as rex.b, extra bit for ModRM r/m, or SIB base
1209 * m: opcode map select, encoding escape bytes e.g. 0x0f38
1210 * w: same as rex.w (32 bit or 64 bit) or opcode specific
1211 * src_reg2: additional source reg (encoded as BPF reg)
1212 * l: vector length (128 bit or 256 bit) or reserved
1213 * pp: opcode prefix (none, 0x66, 0xf2 or 0xf3)
1214 */
1215static void emit_3vex(u8 **pprog, bool r, bool x, bool b, u8 m,
1216 bool w, u8 src_reg2, bool l, u8 pp)
1217{
1218 u8 *prog = *pprog;
1219 const u8 b0 = 0xc4; /* first byte of 3-byte VEX prefix */
1220 u8 b1, b2;
1221 u8 vvvv = reg2hex[src_reg2];
1222
1223 /* reg2hex gives only the lower 3 bit of vvvv */
1224 if (is_ereg(src_reg2))
1225 vvvv |= 1 << 3;
1226
1227 /*
1228 * 2nd byte of 3-byte VEX prefix
1229 * ~ means bit inverted encoding
1230 *
1231 * 7 0
1232 * +---+---+---+---+---+---+---+---+
1233 * |~R |~X |~B | m |
1234 * +---+---+---+---+---+---+---+---+
1235 */
1236 b1 = (!r << 7) | (!x << 6) | (!b << 5) | (m & 0x1f);
1237 /*
1238 * 3rd byte of 3-byte VEX prefix
1239 *
1240 * 7 0
1241 * +---+---+---+---+---+---+---+---+
1242 * | W | ~vvvv | L | pp |
1243 * +---+---+---+---+---+---+---+---+
1244 */
1245 b2 = (w << 7) | ((~vvvv & 0xf) << 3) | (l << 2) | (pp & 3);
1246
1247 EMIT3(b0, b1, b2);
1248 *pprog = prog;
1249}
1250
1251/* emit BMI2 shift instruction */
1252static void emit_shiftx(u8 **pprog, u32 dst_reg, u8 src_reg, bool is64, u8 op)
1253{
1254 u8 *prog = *pprog;
1255 bool r = is_ereg(dst_reg);
1256 u8 m = 2; /* escape code 0f38 */
1257
1258 emit_3vex(&prog, r, false, r, m, is64, src_reg, false, op);
1259 EMIT2(0xf7, add_2reg(0xC0, dst_reg, dst_reg));
1260 *pprog = prog;
1261}
1262
1263#define INSN_SZ_DIFF (((addrs[i] - addrs[i - 1]) - (prog - temp)))
1264
1265/* mov rax, qword ptr [rbp - rounded_stack_depth - 8] */
1266#define RESTORE_TAIL_CALL_CNT(stack) \
1267 EMIT3_off32(0x48, 0x8B, 0x85, -round_up(stack, 8) - 8)
1268
1269static int do_jit(struct bpf_prog *bpf_prog, int *addrs, u8 *image, u8 *rw_image,
1270 int oldproglen, struct jit_context *ctx, bool jmp_padding)
1271{
1272 bool tail_call_reachable = bpf_prog->aux->tail_call_reachable;
1273 struct bpf_insn *insn = bpf_prog->insnsi;
1274 bool callee_regs_used[4] = {};
1275 int insn_cnt = bpf_prog->len;
1276 bool tail_call_seen = false;
1277 bool seen_exit = false;
1278 u8 temp[BPF_MAX_INSN_SIZE + BPF_INSN_SAFETY];
1279 u64 arena_vm_start, user_vm_start;
1280 int i, excnt = 0;
1281 int ilen, proglen = 0;
1282 u8 *prog = temp;
1283 int err;
1284
1285 arena_vm_start = bpf_arena_get_kern_vm_start(bpf_prog->aux->arena);
1286 user_vm_start = bpf_arena_get_user_vm_start(bpf_prog->aux->arena);
1287
1288 detect_reg_usage(insn, insn_cnt, callee_regs_used,
1289 &tail_call_seen);
1290
1291 /* tail call's presence in current prog implies it is reachable */
1292 tail_call_reachable |= tail_call_seen;
1293
1294 emit_prologue(&prog, bpf_prog->aux->stack_depth,
1295 bpf_prog_was_classic(bpf_prog), tail_call_reachable,
1296 bpf_is_subprog(bpf_prog), bpf_prog->aux->exception_cb);
1297 /* Exception callback will clobber callee regs for its own use, and
1298 * restore the original callee regs from main prog's stack frame.
1299 */
1300 if (bpf_prog->aux->exception_boundary) {
1301 /* We also need to save r12, which is not mapped to any BPF
1302 * register, as we throw after entry into the kernel, which may
1303 * overwrite r12.
1304 */
1305 push_r12(&prog);
1306 push_callee_regs(&prog, all_callee_regs_used);
1307 } else {
1308 if (arena_vm_start)
1309 push_r12(&prog);
1310 push_callee_regs(&prog, callee_regs_used);
1311 }
1312 if (arena_vm_start)
1313 emit_mov_imm64(&prog, X86_REG_R12,
1314 arena_vm_start >> 32, (u32) arena_vm_start);
1315
1316 ilen = prog - temp;
1317 if (rw_image)
1318 memcpy(rw_image + proglen, temp, ilen);
1319 proglen += ilen;
1320 addrs[0] = proglen;
1321 prog = temp;
1322
1323 for (i = 1; i <= insn_cnt; i++, insn++) {
1324 const s32 imm32 = insn->imm;
1325 u32 dst_reg = insn->dst_reg;
1326 u32 src_reg = insn->src_reg;
1327 u8 b2 = 0, b3 = 0;
1328 u8 *start_of_ldx;
1329 s64 jmp_offset;
1330 s16 insn_off;
1331 u8 jmp_cond;
1332 u8 *func;
1333 int nops;
1334
1335 switch (insn->code) {
1336 /* ALU */
1337 case BPF_ALU | BPF_ADD | BPF_X:
1338 case BPF_ALU | BPF_SUB | BPF_X:
1339 case BPF_ALU | BPF_AND | BPF_X:
1340 case BPF_ALU | BPF_OR | BPF_X:
1341 case BPF_ALU | BPF_XOR | BPF_X:
1342 case BPF_ALU64 | BPF_ADD | BPF_X:
1343 case BPF_ALU64 | BPF_SUB | BPF_X:
1344 case BPF_ALU64 | BPF_AND | BPF_X:
1345 case BPF_ALU64 | BPF_OR | BPF_X:
1346 case BPF_ALU64 | BPF_XOR | BPF_X:
1347 maybe_emit_mod(&prog, dst_reg, src_reg,
1348 BPF_CLASS(insn->code) == BPF_ALU64);
1349 b2 = simple_alu_opcodes[BPF_OP(insn->code)];
1350 EMIT2(b2, add_2reg(0xC0, dst_reg, src_reg));
1351 break;
1352
1353 case BPF_ALU64 | BPF_MOV | BPF_X:
1354 if (insn->off == BPF_ADDR_SPACE_CAST &&
1355 insn->imm == 1U << 16) {
1356 if (dst_reg != src_reg)
1357 /* 32-bit mov */
1358 emit_mov_reg(&prog, false, dst_reg, src_reg);
1359 /* shl dst_reg, 32 */
1360 maybe_emit_1mod(&prog, dst_reg, true);
1361 EMIT3(0xC1, add_1reg(0xE0, dst_reg), 32);
1362
1363 /* or dst_reg, user_vm_start */
1364 maybe_emit_1mod(&prog, dst_reg, true);
1365 if (is_axreg(dst_reg))
1366 EMIT1_off32(0x0D, user_vm_start >> 32);
1367 else
1368 EMIT2_off32(0x81, add_1reg(0xC8, dst_reg), user_vm_start >> 32);
1369
1370 /* rol dst_reg, 32 */
1371 maybe_emit_1mod(&prog, dst_reg, true);
1372 EMIT3(0xC1, add_1reg(0xC0, dst_reg), 32);
1373
1374 /* xor r11, r11 */
1375 EMIT3(0x4D, 0x31, 0xDB);
1376
1377 /* test dst_reg32, dst_reg32; check if lower 32-bit are zero */
1378 maybe_emit_mod(&prog, dst_reg, dst_reg, false);
1379 EMIT2(0x85, add_2reg(0xC0, dst_reg, dst_reg));
1380
1381 /* cmove r11, dst_reg; if so, set dst_reg to zero */
1382 /* WARNING: Intel swapped src/dst register encoding in CMOVcc !!! */
1383 maybe_emit_mod(&prog, AUX_REG, dst_reg, true);
1384 EMIT3(0x0F, 0x44, add_2reg(0xC0, AUX_REG, dst_reg));
1385 break;
1386 }
1387 fallthrough;
1388 case BPF_ALU | BPF_MOV | BPF_X:
1389 if (insn->off == 0)
1390 emit_mov_reg(&prog,
1391 BPF_CLASS(insn->code) == BPF_ALU64,
1392 dst_reg, src_reg);
1393 else
1394 emit_movsx_reg(&prog, insn->off,
1395 BPF_CLASS(insn->code) == BPF_ALU64,
1396 dst_reg, src_reg);
1397 break;
1398
1399 /* neg dst */
1400 case BPF_ALU | BPF_NEG:
1401 case BPF_ALU64 | BPF_NEG:
1402 maybe_emit_1mod(&prog, dst_reg,
1403 BPF_CLASS(insn->code) == BPF_ALU64);
1404 EMIT2(0xF7, add_1reg(0xD8, dst_reg));
1405 break;
1406
1407 case BPF_ALU | BPF_ADD | BPF_K:
1408 case BPF_ALU | BPF_SUB | BPF_K:
1409 case BPF_ALU | BPF_AND | BPF_K:
1410 case BPF_ALU | BPF_OR | BPF_K:
1411 case BPF_ALU | BPF_XOR | BPF_K:
1412 case BPF_ALU64 | BPF_ADD | BPF_K:
1413 case BPF_ALU64 | BPF_SUB | BPF_K:
1414 case BPF_ALU64 | BPF_AND | BPF_K:
1415 case BPF_ALU64 | BPF_OR | BPF_K:
1416 case BPF_ALU64 | BPF_XOR | BPF_K:
1417 maybe_emit_1mod(&prog, dst_reg,
1418 BPF_CLASS(insn->code) == BPF_ALU64);
1419
1420 /*
1421 * b3 holds 'normal' opcode, b2 short form only valid
1422 * in case dst is eax/rax.
1423 */
1424 switch (BPF_OP(insn->code)) {
1425 case BPF_ADD:
1426 b3 = 0xC0;
1427 b2 = 0x05;
1428 break;
1429 case BPF_SUB:
1430 b3 = 0xE8;
1431 b2 = 0x2D;
1432 break;
1433 case BPF_AND:
1434 b3 = 0xE0;
1435 b2 = 0x25;
1436 break;
1437 case BPF_OR:
1438 b3 = 0xC8;
1439 b2 = 0x0D;
1440 break;
1441 case BPF_XOR:
1442 b3 = 0xF0;
1443 b2 = 0x35;
1444 break;
1445 }
1446
1447 if (is_imm8(imm32))
1448 EMIT3(0x83, add_1reg(b3, dst_reg), imm32);
1449 else if (is_axreg(dst_reg))
1450 EMIT1_off32(b2, imm32);
1451 else
1452 EMIT2_off32(0x81, add_1reg(b3, dst_reg), imm32);
1453 break;
1454
1455 case BPF_ALU64 | BPF_MOV | BPF_K:
1456 case BPF_ALU | BPF_MOV | BPF_K:
1457 emit_mov_imm32(&prog, BPF_CLASS(insn->code) == BPF_ALU64,
1458 dst_reg, imm32);
1459 break;
1460
1461 case BPF_LD | BPF_IMM | BPF_DW:
1462 emit_mov_imm64(&prog, dst_reg, insn[1].imm, insn[0].imm);
1463 insn++;
1464 i++;
1465 break;
1466
1467 /* dst %= src, dst /= src, dst %= imm32, dst /= imm32 */
1468 case BPF_ALU | BPF_MOD | BPF_X:
1469 case BPF_ALU | BPF_DIV | BPF_X:
1470 case BPF_ALU | BPF_MOD | BPF_K:
1471 case BPF_ALU | BPF_DIV | BPF_K:
1472 case BPF_ALU64 | BPF_MOD | BPF_X:
1473 case BPF_ALU64 | BPF_DIV | BPF_X:
1474 case BPF_ALU64 | BPF_MOD | BPF_K:
1475 case BPF_ALU64 | BPF_DIV | BPF_K: {
1476 bool is64 = BPF_CLASS(insn->code) == BPF_ALU64;
1477
1478 if (dst_reg != BPF_REG_0)
1479 EMIT1(0x50); /* push rax */
1480 if (dst_reg != BPF_REG_3)
1481 EMIT1(0x52); /* push rdx */
1482
1483 if (BPF_SRC(insn->code) == BPF_X) {
1484 if (src_reg == BPF_REG_0 ||
1485 src_reg == BPF_REG_3) {
1486 /* mov r11, src_reg */
1487 EMIT_mov(AUX_REG, src_reg);
1488 src_reg = AUX_REG;
1489 }
1490 } else {
1491 /* mov r11, imm32 */
1492 EMIT3_off32(0x49, 0xC7, 0xC3, imm32);
1493 src_reg = AUX_REG;
1494 }
1495
1496 if (dst_reg != BPF_REG_0)
1497 /* mov rax, dst_reg */
1498 emit_mov_reg(&prog, is64, BPF_REG_0, dst_reg);
1499
1500 if (insn->off == 0) {
1501 /*
1502 * xor edx, edx
1503 * equivalent to 'xor rdx, rdx', but one byte less
1504 */
1505 EMIT2(0x31, 0xd2);
1506
1507 /* div src_reg */
1508 maybe_emit_1mod(&prog, src_reg, is64);
1509 EMIT2(0xF7, add_1reg(0xF0, src_reg));
1510 } else {
1511 if (BPF_CLASS(insn->code) == BPF_ALU)
1512 EMIT1(0x99); /* cdq */
1513 else
1514 EMIT2(0x48, 0x99); /* cqo */
1515
1516 /* idiv src_reg */
1517 maybe_emit_1mod(&prog, src_reg, is64);
1518 EMIT2(0xF7, add_1reg(0xF8, src_reg));
1519 }
1520
1521 if (BPF_OP(insn->code) == BPF_MOD &&
1522 dst_reg != BPF_REG_3)
1523 /* mov dst_reg, rdx */
1524 emit_mov_reg(&prog, is64, dst_reg, BPF_REG_3);
1525 else if (BPF_OP(insn->code) == BPF_DIV &&
1526 dst_reg != BPF_REG_0)
1527 /* mov dst_reg, rax */
1528 emit_mov_reg(&prog, is64, dst_reg, BPF_REG_0);
1529
1530 if (dst_reg != BPF_REG_3)
1531 EMIT1(0x5A); /* pop rdx */
1532 if (dst_reg != BPF_REG_0)
1533 EMIT1(0x58); /* pop rax */
1534 break;
1535 }
1536
1537 case BPF_ALU | BPF_MUL | BPF_K:
1538 case BPF_ALU64 | BPF_MUL | BPF_K:
1539 maybe_emit_mod(&prog, dst_reg, dst_reg,
1540 BPF_CLASS(insn->code) == BPF_ALU64);
1541
1542 if (is_imm8(imm32))
1543 /* imul dst_reg, dst_reg, imm8 */
1544 EMIT3(0x6B, add_2reg(0xC0, dst_reg, dst_reg),
1545 imm32);
1546 else
1547 /* imul dst_reg, dst_reg, imm32 */
1548 EMIT2_off32(0x69,
1549 add_2reg(0xC0, dst_reg, dst_reg),
1550 imm32);
1551 break;
1552
1553 case BPF_ALU | BPF_MUL | BPF_X:
1554 case BPF_ALU64 | BPF_MUL | BPF_X:
1555 maybe_emit_mod(&prog, src_reg, dst_reg,
1556 BPF_CLASS(insn->code) == BPF_ALU64);
1557
1558 /* imul dst_reg, src_reg */
1559 EMIT3(0x0F, 0xAF, add_2reg(0xC0, src_reg, dst_reg));
1560 break;
1561
1562 /* Shifts */
1563 case BPF_ALU | BPF_LSH | BPF_K:
1564 case BPF_ALU | BPF_RSH | BPF_K:
1565 case BPF_ALU | BPF_ARSH | BPF_K:
1566 case BPF_ALU64 | BPF_LSH | BPF_K:
1567 case BPF_ALU64 | BPF_RSH | BPF_K:
1568 case BPF_ALU64 | BPF_ARSH | BPF_K:
1569 maybe_emit_1mod(&prog, dst_reg,
1570 BPF_CLASS(insn->code) == BPF_ALU64);
1571
1572 b3 = simple_alu_opcodes[BPF_OP(insn->code)];
1573 if (imm32 == 1)
1574 EMIT2(0xD1, add_1reg(b3, dst_reg));
1575 else
1576 EMIT3(0xC1, add_1reg(b3, dst_reg), imm32);
1577 break;
1578
1579 case BPF_ALU | BPF_LSH | BPF_X:
1580 case BPF_ALU | BPF_RSH | BPF_X:
1581 case BPF_ALU | BPF_ARSH | BPF_X:
1582 case BPF_ALU64 | BPF_LSH | BPF_X:
1583 case BPF_ALU64 | BPF_RSH | BPF_X:
1584 case BPF_ALU64 | BPF_ARSH | BPF_X:
1585 /* BMI2 shifts aren't better when shift count is already in rcx */
1586 if (boot_cpu_has(X86_FEATURE_BMI2) && src_reg != BPF_REG_4) {
1587 /* shrx/sarx/shlx dst_reg, dst_reg, src_reg */
1588 bool w = (BPF_CLASS(insn->code) == BPF_ALU64);
1589 u8 op;
1590
1591 switch (BPF_OP(insn->code)) {
1592 case BPF_LSH:
1593 op = 1; /* prefix 0x66 */
1594 break;
1595 case BPF_RSH:
1596 op = 3; /* prefix 0xf2 */
1597 break;
1598 case BPF_ARSH:
1599 op = 2; /* prefix 0xf3 */
1600 break;
1601 }
1602
1603 emit_shiftx(&prog, dst_reg, src_reg, w, op);
1604
1605 break;
1606 }
1607
1608 if (src_reg != BPF_REG_4) { /* common case */
1609 /* Check for bad case when dst_reg == rcx */
1610 if (dst_reg == BPF_REG_4) {
1611 /* mov r11, dst_reg */
1612 EMIT_mov(AUX_REG, dst_reg);
1613 dst_reg = AUX_REG;
1614 } else {
1615 EMIT1(0x51); /* push rcx */
1616 }
1617 /* mov rcx, src_reg */
1618 EMIT_mov(BPF_REG_4, src_reg);
1619 }
1620
1621 /* shl %rax, %cl | shr %rax, %cl | sar %rax, %cl */
1622 maybe_emit_1mod(&prog, dst_reg,
1623 BPF_CLASS(insn->code) == BPF_ALU64);
1624
1625 b3 = simple_alu_opcodes[BPF_OP(insn->code)];
1626 EMIT2(0xD3, add_1reg(b3, dst_reg));
1627
1628 if (src_reg != BPF_REG_4) {
1629 if (insn->dst_reg == BPF_REG_4)
1630 /* mov dst_reg, r11 */
1631 EMIT_mov(insn->dst_reg, AUX_REG);
1632 else
1633 EMIT1(0x59); /* pop rcx */
1634 }
1635
1636 break;
1637
1638 case BPF_ALU | BPF_END | BPF_FROM_BE:
1639 case BPF_ALU64 | BPF_END | BPF_FROM_LE:
1640 switch (imm32) {
1641 case 16:
1642 /* Emit 'ror %ax, 8' to swap lower 2 bytes */
1643 EMIT1(0x66);
1644 if (is_ereg(dst_reg))
1645 EMIT1(0x41);
1646 EMIT3(0xC1, add_1reg(0xC8, dst_reg), 8);
1647
1648 /* Emit 'movzwl eax, ax' */
1649 if (is_ereg(dst_reg))
1650 EMIT3(0x45, 0x0F, 0xB7);
1651 else
1652 EMIT2(0x0F, 0xB7);
1653 EMIT1(add_2reg(0xC0, dst_reg, dst_reg));
1654 break;
1655 case 32:
1656 /* Emit 'bswap eax' to swap lower 4 bytes */
1657 if (is_ereg(dst_reg))
1658 EMIT2(0x41, 0x0F);
1659 else
1660 EMIT1(0x0F);
1661 EMIT1(add_1reg(0xC8, dst_reg));
1662 break;
1663 case 64:
1664 /* Emit 'bswap rax' to swap 8 bytes */
1665 EMIT3(add_1mod(0x48, dst_reg), 0x0F,
1666 add_1reg(0xC8, dst_reg));
1667 break;
1668 }
1669 break;
1670
1671 case BPF_ALU | BPF_END | BPF_FROM_LE:
1672 switch (imm32) {
1673 case 16:
1674 /*
1675 * Emit 'movzwl eax, ax' to zero extend 16-bit
1676 * into 64 bit
1677 */
1678 if (is_ereg(dst_reg))
1679 EMIT3(0x45, 0x0F, 0xB7);
1680 else
1681 EMIT2(0x0F, 0xB7);
1682 EMIT1(add_2reg(0xC0, dst_reg, dst_reg));
1683 break;
1684 case 32:
1685 /* Emit 'mov eax, eax' to clear upper 32-bits */
1686 if (is_ereg(dst_reg))
1687 EMIT1(0x45);
1688 EMIT2(0x89, add_2reg(0xC0, dst_reg, dst_reg));
1689 break;
1690 case 64:
1691 /* nop */
1692 break;
1693 }
1694 break;
1695
1696 /* speculation barrier */
1697 case BPF_ST | BPF_NOSPEC:
1698 EMIT_LFENCE();
1699 break;
1700
1701 /* ST: *(u8*)(dst_reg + off) = imm */
1702 case BPF_ST | BPF_MEM | BPF_B:
1703 if (is_ereg(dst_reg))
1704 EMIT2(0x41, 0xC6);
1705 else
1706 EMIT1(0xC6);
1707 goto st;
1708 case BPF_ST | BPF_MEM | BPF_H:
1709 if (is_ereg(dst_reg))
1710 EMIT3(0x66, 0x41, 0xC7);
1711 else
1712 EMIT2(0x66, 0xC7);
1713 goto st;
1714 case BPF_ST | BPF_MEM | BPF_W:
1715 if (is_ereg(dst_reg))
1716 EMIT2(0x41, 0xC7);
1717 else
1718 EMIT1(0xC7);
1719 goto st;
1720 case BPF_ST | BPF_MEM | BPF_DW:
1721 EMIT2(add_1mod(0x48, dst_reg), 0xC7);
1722
1723st: if (is_imm8(insn->off))
1724 EMIT2(add_1reg(0x40, dst_reg), insn->off);
1725 else
1726 EMIT1_off32(add_1reg(0x80, dst_reg), insn->off);
1727
1728 EMIT(imm32, bpf_size_to_x86_bytes(BPF_SIZE(insn->code)));
1729 break;
1730
1731 /* STX: *(u8*)(dst_reg + off) = src_reg */
1732 case BPF_STX | BPF_MEM | BPF_B:
1733 case BPF_STX | BPF_MEM | BPF_H:
1734 case BPF_STX | BPF_MEM | BPF_W:
1735 case BPF_STX | BPF_MEM | BPF_DW:
1736 emit_stx(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn->off);
1737 break;
1738
1739 case BPF_ST | BPF_PROBE_MEM32 | BPF_B:
1740 case BPF_ST | BPF_PROBE_MEM32 | BPF_H:
1741 case BPF_ST | BPF_PROBE_MEM32 | BPF_W:
1742 case BPF_ST | BPF_PROBE_MEM32 | BPF_DW:
1743 start_of_ldx = prog;
1744 emit_st_r12(&prog, BPF_SIZE(insn->code), dst_reg, insn->off, insn->imm);
1745 goto populate_extable;
1746
1747 /* LDX: dst_reg = *(u8*)(src_reg + r12 + off) */
1748 case BPF_LDX | BPF_PROBE_MEM32 | BPF_B:
1749 case BPF_LDX | BPF_PROBE_MEM32 | BPF_H:
1750 case BPF_LDX | BPF_PROBE_MEM32 | BPF_W:
1751 case BPF_LDX | BPF_PROBE_MEM32 | BPF_DW:
1752 case BPF_STX | BPF_PROBE_MEM32 | BPF_B:
1753 case BPF_STX | BPF_PROBE_MEM32 | BPF_H:
1754 case BPF_STX | BPF_PROBE_MEM32 | BPF_W:
1755 case BPF_STX | BPF_PROBE_MEM32 | BPF_DW:
1756 start_of_ldx = prog;
1757 if (BPF_CLASS(insn->code) == BPF_LDX)
1758 emit_ldx_r12(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn->off);
1759 else
1760 emit_stx_r12(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn->off);
1761populate_extable:
1762 {
1763 struct exception_table_entry *ex;
1764 u8 *_insn = image + proglen + (start_of_ldx - temp);
1765 s64 delta;
1766
1767 if (!bpf_prog->aux->extable)
1768 break;
1769
1770 if (excnt >= bpf_prog->aux->num_exentries) {
1771 pr_err("mem32 extable bug\n");
1772 return -EFAULT;
1773 }
1774 ex = &bpf_prog->aux->extable[excnt++];
1775
1776 delta = _insn - (u8 *)&ex->insn;
1777 /* switch ex to rw buffer for writes */
1778 ex = (void *)rw_image + ((void *)ex - (void *)image);
1779
1780 ex->insn = delta;
1781
1782 ex->data = EX_TYPE_BPF;
1783
1784 ex->fixup = (prog - start_of_ldx) |
1785 ((BPF_CLASS(insn->code) == BPF_LDX ? reg2pt_regs[dst_reg] : DONT_CLEAR) << 8);
1786 }
1787 break;
1788
1789 /* LDX: dst_reg = *(u8*)(src_reg + off) */
1790 case BPF_LDX | BPF_MEM | BPF_B:
1791 case BPF_LDX | BPF_PROBE_MEM | BPF_B:
1792 case BPF_LDX | BPF_MEM | BPF_H:
1793 case BPF_LDX | BPF_PROBE_MEM | BPF_H:
1794 case BPF_LDX | BPF_MEM | BPF_W:
1795 case BPF_LDX | BPF_PROBE_MEM | BPF_W:
1796 case BPF_LDX | BPF_MEM | BPF_DW:
1797 case BPF_LDX | BPF_PROBE_MEM | BPF_DW:
1798 /* LDXS: dst_reg = *(s8*)(src_reg + off) */
1799 case BPF_LDX | BPF_MEMSX | BPF_B:
1800 case BPF_LDX | BPF_MEMSX | BPF_H:
1801 case BPF_LDX | BPF_MEMSX | BPF_W:
1802 case BPF_LDX | BPF_PROBE_MEMSX | BPF_B:
1803 case BPF_LDX | BPF_PROBE_MEMSX | BPF_H:
1804 case BPF_LDX | BPF_PROBE_MEMSX | BPF_W:
1805 insn_off = insn->off;
1806
1807 if (BPF_MODE(insn->code) == BPF_PROBE_MEM ||
1808 BPF_MODE(insn->code) == BPF_PROBE_MEMSX) {
1809 /* Conservatively check that src_reg + insn->off is a kernel address:
1810 * src_reg + insn->off > TASK_SIZE_MAX + PAGE_SIZE
1811 * and
1812 * src_reg + insn->off < VSYSCALL_ADDR
1813 */
1814
1815 u64 limit = TASK_SIZE_MAX + PAGE_SIZE - VSYSCALL_ADDR;
1816 u8 *end_of_jmp;
1817
1818 /* movabsq r10, VSYSCALL_ADDR */
1819 emit_mov_imm64(&prog, BPF_REG_AX, (long)VSYSCALL_ADDR >> 32,
1820 (u32)(long)VSYSCALL_ADDR);
1821
1822 /* mov src_reg, r11 */
1823 EMIT_mov(AUX_REG, src_reg);
1824
1825 if (insn->off) {
1826 /* add r11, insn->off */
1827 maybe_emit_1mod(&prog, AUX_REG, true);
1828 EMIT2_off32(0x81, add_1reg(0xC0, AUX_REG), insn->off);
1829 }
1830
1831 /* sub r11, r10 */
1832 maybe_emit_mod(&prog, AUX_REG, BPF_REG_AX, true);
1833 EMIT2(0x29, add_2reg(0xC0, AUX_REG, BPF_REG_AX));
1834
1835 /* movabsq r10, limit */
1836 emit_mov_imm64(&prog, BPF_REG_AX, (long)limit >> 32,
1837 (u32)(long)limit);
1838
1839 /* cmp r10, r11 */
1840 maybe_emit_mod(&prog, AUX_REG, BPF_REG_AX, true);
1841 EMIT2(0x39, add_2reg(0xC0, AUX_REG, BPF_REG_AX));
1842
1843 /* if unsigned '>', goto load */
1844 EMIT2(X86_JA, 0);
1845 end_of_jmp = prog;
1846
1847 /* xor dst_reg, dst_reg */
1848 emit_mov_imm32(&prog, false, dst_reg, 0);
1849 /* jmp byte_after_ldx */
1850 EMIT2(0xEB, 0);
1851
1852 /* populate jmp_offset for JAE above to jump to start_of_ldx */
1853 start_of_ldx = prog;
1854 end_of_jmp[-1] = start_of_ldx - end_of_jmp;
1855 }
1856 if (BPF_MODE(insn->code) == BPF_PROBE_MEMSX ||
1857 BPF_MODE(insn->code) == BPF_MEMSX)
1858 emit_ldsx(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn_off);
1859 else
1860 emit_ldx(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn_off);
1861 if (BPF_MODE(insn->code) == BPF_PROBE_MEM ||
1862 BPF_MODE(insn->code) == BPF_PROBE_MEMSX) {
1863 struct exception_table_entry *ex;
1864 u8 *_insn = image + proglen + (start_of_ldx - temp);
1865 s64 delta;
1866
1867 /* populate jmp_offset for JMP above */
1868 start_of_ldx[-1] = prog - start_of_ldx;
1869
1870 if (!bpf_prog->aux->extable)
1871 break;
1872
1873 if (excnt >= bpf_prog->aux->num_exentries) {
1874 pr_err("ex gen bug\n");
1875 return -EFAULT;
1876 }
1877 ex = &bpf_prog->aux->extable[excnt++];
1878
1879 delta = _insn - (u8 *)&ex->insn;
1880 if (!is_simm32(delta)) {
1881 pr_err("extable->insn doesn't fit into 32-bit\n");
1882 return -EFAULT;
1883 }
1884 /* switch ex to rw buffer for writes */
1885 ex = (void *)rw_image + ((void *)ex - (void *)image);
1886
1887 ex->insn = delta;
1888
1889 ex->data = EX_TYPE_BPF;
1890
1891 if (dst_reg > BPF_REG_9) {
1892 pr_err("verifier error\n");
1893 return -EFAULT;
1894 }
1895 /*
1896 * Compute size of x86 insn and its target dest x86 register.
1897 * ex_handler_bpf() will use lower 8 bits to adjust
1898 * pt_regs->ip to jump over this x86 instruction
1899 * and upper bits to figure out which pt_regs to zero out.
1900 * End result: x86 insn "mov rbx, qword ptr [rax+0x14]"
1901 * of 4 bytes will be ignored and rbx will be zero inited.
1902 */
1903 ex->fixup = (prog - start_of_ldx) | (reg2pt_regs[dst_reg] << 8);
1904 }
1905 break;
1906
1907 case BPF_STX | BPF_ATOMIC | BPF_W:
1908 case BPF_STX | BPF_ATOMIC | BPF_DW:
1909 if (insn->imm == (BPF_AND | BPF_FETCH) ||
1910 insn->imm == (BPF_OR | BPF_FETCH) ||
1911 insn->imm == (BPF_XOR | BPF_FETCH)) {
1912 bool is64 = BPF_SIZE(insn->code) == BPF_DW;
1913 u32 real_src_reg = src_reg;
1914 u32 real_dst_reg = dst_reg;
1915 u8 *branch_target;
1916
1917 /*
1918 * Can't be implemented with a single x86 insn.
1919 * Need to do a CMPXCHG loop.
1920 */
1921
1922 /* Will need RAX as a CMPXCHG operand so save R0 */
1923 emit_mov_reg(&prog, true, BPF_REG_AX, BPF_REG_0);
1924 if (src_reg == BPF_REG_0)
1925 real_src_reg = BPF_REG_AX;
1926 if (dst_reg == BPF_REG_0)
1927 real_dst_reg = BPF_REG_AX;
1928
1929 branch_target = prog;
1930 /* Load old value */
1931 emit_ldx(&prog, BPF_SIZE(insn->code),
1932 BPF_REG_0, real_dst_reg, insn->off);
1933 /*
1934 * Perform the (commutative) operation locally,
1935 * put the result in the AUX_REG.
1936 */
1937 emit_mov_reg(&prog, is64, AUX_REG, BPF_REG_0);
1938 maybe_emit_mod(&prog, AUX_REG, real_src_reg, is64);
1939 EMIT2(simple_alu_opcodes[BPF_OP(insn->imm)],
1940 add_2reg(0xC0, AUX_REG, real_src_reg));
1941 /* Attempt to swap in new value */
1942 err = emit_atomic(&prog, BPF_CMPXCHG,
1943 real_dst_reg, AUX_REG,
1944 insn->off,
1945 BPF_SIZE(insn->code));
1946 if (WARN_ON(err))
1947 return err;
1948 /*
1949 * ZF tells us whether we won the race. If it's
1950 * cleared we need to try again.
1951 */
1952 EMIT2(X86_JNE, -(prog - branch_target) - 2);
1953 /* Return the pre-modification value */
1954 emit_mov_reg(&prog, is64, real_src_reg, BPF_REG_0);
1955 /* Restore R0 after clobbering RAX */
1956 emit_mov_reg(&prog, true, BPF_REG_0, BPF_REG_AX);
1957 break;
1958 }
1959
1960 err = emit_atomic(&prog, insn->imm, dst_reg, src_reg,
1961 insn->off, BPF_SIZE(insn->code));
1962 if (err)
1963 return err;
1964 break;
1965
1966 /* call */
1967 case BPF_JMP | BPF_CALL: {
1968 u8 *ip = image + addrs[i - 1];
1969
1970 func = (u8 *) __bpf_call_base + imm32;
1971 if (tail_call_reachable) {
1972 RESTORE_TAIL_CALL_CNT(bpf_prog->aux->stack_depth);
1973 ip += 7;
1974 }
1975 if (!imm32)
1976 return -EINVAL;
1977 ip += x86_call_depth_emit_accounting(&prog, func, ip);
1978 if (emit_call(&prog, func, ip))
1979 return -EINVAL;
1980 break;
1981 }
1982
1983 case BPF_JMP | BPF_TAIL_CALL:
1984 if (imm32)
1985 emit_bpf_tail_call_direct(bpf_prog,
1986 &bpf_prog->aux->poke_tab[imm32 - 1],
1987 &prog, image + addrs[i - 1],
1988 callee_regs_used,
1989 bpf_prog->aux->stack_depth,
1990 ctx);
1991 else
1992 emit_bpf_tail_call_indirect(bpf_prog,
1993 &prog,
1994 callee_regs_used,
1995 bpf_prog->aux->stack_depth,
1996 image + addrs[i - 1],
1997 ctx);
1998 break;
1999
2000 /* cond jump */
2001 case BPF_JMP | BPF_JEQ | BPF_X:
2002 case BPF_JMP | BPF_JNE | BPF_X:
2003 case BPF_JMP | BPF_JGT | BPF_X:
2004 case BPF_JMP | BPF_JLT | BPF_X:
2005 case BPF_JMP | BPF_JGE | BPF_X:
2006 case BPF_JMP | BPF_JLE | BPF_X:
2007 case BPF_JMP | BPF_JSGT | BPF_X:
2008 case BPF_JMP | BPF_JSLT | BPF_X:
2009 case BPF_JMP | BPF_JSGE | BPF_X:
2010 case BPF_JMP | BPF_JSLE | BPF_X:
2011 case BPF_JMP32 | BPF_JEQ | BPF_X:
2012 case BPF_JMP32 | BPF_JNE | BPF_X:
2013 case BPF_JMP32 | BPF_JGT | BPF_X:
2014 case BPF_JMP32 | BPF_JLT | BPF_X:
2015 case BPF_JMP32 | BPF_JGE | BPF_X:
2016 case BPF_JMP32 | BPF_JLE | BPF_X:
2017 case BPF_JMP32 | BPF_JSGT | BPF_X:
2018 case BPF_JMP32 | BPF_JSLT | BPF_X:
2019 case BPF_JMP32 | BPF_JSGE | BPF_X:
2020 case BPF_JMP32 | BPF_JSLE | BPF_X:
2021 /* cmp dst_reg, src_reg */
2022 maybe_emit_mod(&prog, dst_reg, src_reg,
2023 BPF_CLASS(insn->code) == BPF_JMP);
2024 EMIT2(0x39, add_2reg(0xC0, dst_reg, src_reg));
2025 goto emit_cond_jmp;
2026
2027 case BPF_JMP | BPF_JSET | BPF_X:
2028 case BPF_JMP32 | BPF_JSET | BPF_X:
2029 /* test dst_reg, src_reg */
2030 maybe_emit_mod(&prog, dst_reg, src_reg,
2031 BPF_CLASS(insn->code) == BPF_JMP);
2032 EMIT2(0x85, add_2reg(0xC0, dst_reg, src_reg));
2033 goto emit_cond_jmp;
2034
2035 case BPF_JMP | BPF_JSET | BPF_K:
2036 case BPF_JMP32 | BPF_JSET | BPF_K:
2037 /* test dst_reg, imm32 */
2038 maybe_emit_1mod(&prog, dst_reg,
2039 BPF_CLASS(insn->code) == BPF_JMP);
2040 EMIT2_off32(0xF7, add_1reg(0xC0, dst_reg), imm32);
2041 goto emit_cond_jmp;
2042
2043 case BPF_JMP | BPF_JEQ | BPF_K:
2044 case BPF_JMP | BPF_JNE | BPF_K:
2045 case BPF_JMP | BPF_JGT | BPF_K:
2046 case BPF_JMP | BPF_JLT | BPF_K:
2047 case BPF_JMP | BPF_JGE | BPF_K:
2048 case BPF_JMP | BPF_JLE | BPF_K:
2049 case BPF_JMP | BPF_JSGT | BPF_K:
2050 case BPF_JMP | BPF_JSLT | BPF_K:
2051 case BPF_JMP | BPF_JSGE | BPF_K:
2052 case BPF_JMP | BPF_JSLE | BPF_K:
2053 case BPF_JMP32 | BPF_JEQ | BPF_K:
2054 case BPF_JMP32 | BPF_JNE | BPF_K:
2055 case BPF_JMP32 | BPF_JGT | BPF_K:
2056 case BPF_JMP32 | BPF_JLT | BPF_K:
2057 case BPF_JMP32 | BPF_JGE | BPF_K:
2058 case BPF_JMP32 | BPF_JLE | BPF_K:
2059 case BPF_JMP32 | BPF_JSGT | BPF_K:
2060 case BPF_JMP32 | BPF_JSLT | BPF_K:
2061 case BPF_JMP32 | BPF_JSGE | BPF_K:
2062 case BPF_JMP32 | BPF_JSLE | BPF_K:
2063 /* test dst_reg, dst_reg to save one extra byte */
2064 if (imm32 == 0) {
2065 maybe_emit_mod(&prog, dst_reg, dst_reg,
2066 BPF_CLASS(insn->code) == BPF_JMP);
2067 EMIT2(0x85, add_2reg(0xC0, dst_reg, dst_reg));
2068 goto emit_cond_jmp;
2069 }
2070
2071 /* cmp dst_reg, imm8/32 */
2072 maybe_emit_1mod(&prog, dst_reg,
2073 BPF_CLASS(insn->code) == BPF_JMP);
2074
2075 if (is_imm8(imm32))
2076 EMIT3(0x83, add_1reg(0xF8, dst_reg), imm32);
2077 else
2078 EMIT2_off32(0x81, add_1reg(0xF8, dst_reg), imm32);
2079
2080emit_cond_jmp: /* Convert BPF opcode to x86 */
2081 switch (BPF_OP(insn->code)) {
2082 case BPF_JEQ:
2083 jmp_cond = X86_JE;
2084 break;
2085 case BPF_JSET:
2086 case BPF_JNE:
2087 jmp_cond = X86_JNE;
2088 break;
2089 case BPF_JGT:
2090 /* GT is unsigned '>', JA in x86 */
2091 jmp_cond = X86_JA;
2092 break;
2093 case BPF_JLT:
2094 /* LT is unsigned '<', JB in x86 */
2095 jmp_cond = X86_JB;
2096 break;
2097 case BPF_JGE:
2098 /* GE is unsigned '>=', JAE in x86 */
2099 jmp_cond = X86_JAE;
2100 break;
2101 case BPF_JLE:
2102 /* LE is unsigned '<=', JBE in x86 */
2103 jmp_cond = X86_JBE;
2104 break;
2105 case BPF_JSGT:
2106 /* Signed '>', GT in x86 */
2107 jmp_cond = X86_JG;
2108 break;
2109 case BPF_JSLT:
2110 /* Signed '<', LT in x86 */
2111 jmp_cond = X86_JL;
2112 break;
2113 case BPF_JSGE:
2114 /* Signed '>=', GE in x86 */
2115 jmp_cond = X86_JGE;
2116 break;
2117 case BPF_JSLE:
2118 /* Signed '<=', LE in x86 */
2119 jmp_cond = X86_JLE;
2120 break;
2121 default: /* to silence GCC warning */
2122 return -EFAULT;
2123 }
2124 jmp_offset = addrs[i + insn->off] - addrs[i];
2125 if (is_imm8(jmp_offset)) {
2126 if (jmp_padding) {
2127 /* To keep the jmp_offset valid, the extra bytes are
2128 * padded before the jump insn, so we subtract the
2129 * 2 bytes of jmp_cond insn from INSN_SZ_DIFF.
2130 *
2131 * If the previous pass already emits an imm8
2132 * jmp_cond, then this BPF insn won't shrink, so
2133 * "nops" is 0.
2134 *
2135 * On the other hand, if the previous pass emits an
2136 * imm32 jmp_cond, the extra 4 bytes(*) is padded to
2137 * keep the image from shrinking further.
2138 *
2139 * (*) imm32 jmp_cond is 6 bytes, and imm8 jmp_cond
2140 * is 2 bytes, so the size difference is 4 bytes.
2141 */
2142 nops = INSN_SZ_DIFF - 2;
2143 if (nops != 0 && nops != 4) {
2144 pr_err("unexpected jmp_cond padding: %d bytes\n",
2145 nops);
2146 return -EFAULT;
2147 }
2148 emit_nops(&prog, nops);
2149 }
2150 EMIT2(jmp_cond, jmp_offset);
2151 } else if (is_simm32(jmp_offset)) {
2152 EMIT2_off32(0x0F, jmp_cond + 0x10, jmp_offset);
2153 } else {
2154 pr_err("cond_jmp gen bug %llx\n", jmp_offset);
2155 return -EFAULT;
2156 }
2157
2158 break;
2159
2160 case BPF_JMP | BPF_JA:
2161 case BPF_JMP32 | BPF_JA:
2162 if (BPF_CLASS(insn->code) == BPF_JMP) {
2163 if (insn->off == -1)
2164 /* -1 jmp instructions will always jump
2165 * backwards two bytes. Explicitly handling
2166 * this case avoids wasting too many passes
2167 * when there are long sequences of replaced
2168 * dead code.
2169 */
2170 jmp_offset = -2;
2171 else
2172 jmp_offset = addrs[i + insn->off] - addrs[i];
2173 } else {
2174 if (insn->imm == -1)
2175 jmp_offset = -2;
2176 else
2177 jmp_offset = addrs[i + insn->imm] - addrs[i];
2178 }
2179
2180 if (!jmp_offset) {
2181 /*
2182 * If jmp_padding is enabled, the extra nops will
2183 * be inserted. Otherwise, optimize out nop jumps.
2184 */
2185 if (jmp_padding) {
2186 /* There are 3 possible conditions.
2187 * (1) This BPF_JA is already optimized out in
2188 * the previous run, so there is no need
2189 * to pad any extra byte (0 byte).
2190 * (2) The previous pass emits an imm8 jmp,
2191 * so we pad 2 bytes to match the previous
2192 * insn size.
2193 * (3) Similarly, the previous pass emits an
2194 * imm32 jmp, and 5 bytes is padded.
2195 */
2196 nops = INSN_SZ_DIFF;
2197 if (nops != 0 && nops != 2 && nops != 5) {
2198 pr_err("unexpected nop jump padding: %d bytes\n",
2199 nops);
2200 return -EFAULT;
2201 }
2202 emit_nops(&prog, nops);
2203 }
2204 break;
2205 }
2206emit_jmp:
2207 if (is_imm8(jmp_offset)) {
2208 if (jmp_padding) {
2209 /* To avoid breaking jmp_offset, the extra bytes
2210 * are padded before the actual jmp insn, so
2211 * 2 bytes is subtracted from INSN_SZ_DIFF.
2212 *
2213 * If the previous pass already emits an imm8
2214 * jmp, there is nothing to pad (0 byte).
2215 *
2216 * If it emits an imm32 jmp (5 bytes) previously
2217 * and now an imm8 jmp (2 bytes), then we pad
2218 * (5 - 2 = 3) bytes to stop the image from
2219 * shrinking further.
2220 */
2221 nops = INSN_SZ_DIFF - 2;
2222 if (nops != 0 && nops != 3) {
2223 pr_err("unexpected jump padding: %d bytes\n",
2224 nops);
2225 return -EFAULT;
2226 }
2227 emit_nops(&prog, INSN_SZ_DIFF - 2);
2228 }
2229 EMIT2(0xEB, jmp_offset);
2230 } else if (is_simm32(jmp_offset)) {
2231 EMIT1_off32(0xE9, jmp_offset);
2232 } else {
2233 pr_err("jmp gen bug %llx\n", jmp_offset);
2234 return -EFAULT;
2235 }
2236 break;
2237
2238 case BPF_JMP | BPF_EXIT:
2239 if (seen_exit) {
2240 jmp_offset = ctx->cleanup_addr - addrs[i];
2241 goto emit_jmp;
2242 }
2243 seen_exit = true;
2244 /* Update cleanup_addr */
2245 ctx->cleanup_addr = proglen;
2246 if (bpf_prog->aux->exception_boundary) {
2247 pop_callee_regs(&prog, all_callee_regs_used);
2248 pop_r12(&prog);
2249 } else {
2250 pop_callee_regs(&prog, callee_regs_used);
2251 if (arena_vm_start)
2252 pop_r12(&prog);
2253 }
2254 EMIT1(0xC9); /* leave */
2255 emit_return(&prog, image + addrs[i - 1] + (prog - temp));
2256 break;
2257
2258 default:
2259 /*
2260 * By design x86-64 JIT should support all BPF instructions.
2261 * This error will be seen if new instruction was added
2262 * to the interpreter, but not to the JIT, or if there is
2263 * junk in bpf_prog.
2264 */
2265 pr_err("bpf_jit: unknown opcode %02x\n", insn->code);
2266 return -EINVAL;
2267 }
2268
2269 ilen = prog - temp;
2270 if (ilen > BPF_MAX_INSN_SIZE) {
2271 pr_err("bpf_jit: fatal insn size error\n");
2272 return -EFAULT;
2273 }
2274
2275 if (image) {
2276 /*
2277 * When populating the image, assert that:
2278 *
2279 * i) We do not write beyond the allocated space, and
2280 * ii) addrs[i] did not change from the prior run, in order
2281 * to validate assumptions made for computing branch
2282 * displacements.
2283 */
2284 if (unlikely(proglen + ilen > oldproglen ||
2285 proglen + ilen != addrs[i])) {
2286 pr_err("bpf_jit: fatal error\n");
2287 return -EFAULT;
2288 }
2289 memcpy(rw_image + proglen, temp, ilen);
2290 }
2291 proglen += ilen;
2292 addrs[i] = proglen;
2293 prog = temp;
2294 }
2295
2296 if (image && excnt != bpf_prog->aux->num_exentries) {
2297 pr_err("extable is not populated\n");
2298 return -EFAULT;
2299 }
2300 return proglen;
2301}
2302
2303static void clean_stack_garbage(const struct btf_func_model *m,
2304 u8 **pprog, int nr_stack_slots,
2305 int stack_size)
2306{
2307 int arg_size, off;
2308 u8 *prog;
2309
2310 /* Generally speaking, the compiler will pass the arguments
2311 * on-stack with "push" instruction, which will take 8-byte
2312 * on the stack. In this case, there won't be garbage values
2313 * while we copy the arguments from origin stack frame to current
2314 * in BPF_DW.
2315 *
2316 * However, sometimes the compiler will only allocate 4-byte on
2317 * the stack for the arguments. For now, this case will only
2318 * happen if there is only one argument on-stack and its size
2319 * not more than 4 byte. In this case, there will be garbage
2320 * values on the upper 4-byte where we store the argument on
2321 * current stack frame.
2322 *
2323 * arguments on origin stack:
2324 *
2325 * stack_arg_1(4-byte) xxx(4-byte)
2326 *
2327 * what we copy:
2328 *
2329 * stack_arg_1(8-byte): stack_arg_1(origin) xxx
2330 *
2331 * and the xxx is the garbage values which we should clean here.
2332 */
2333 if (nr_stack_slots != 1)
2334 return;
2335
2336 /* the size of the last argument */
2337 arg_size = m->arg_size[m->nr_args - 1];
2338 if (arg_size <= 4) {
2339 off = -(stack_size - 4);
2340 prog = *pprog;
2341 /* mov DWORD PTR [rbp + off], 0 */
2342 if (!is_imm8(off))
2343 EMIT2_off32(0xC7, 0x85, off);
2344 else
2345 EMIT3(0xC7, 0x45, off);
2346 EMIT(0, 4);
2347 *pprog = prog;
2348 }
2349}
2350
2351/* get the count of the regs that are used to pass arguments */
2352static int get_nr_used_regs(const struct btf_func_model *m)
2353{
2354 int i, arg_regs, nr_used_regs = 0;
2355
2356 for (i = 0; i < min_t(int, m->nr_args, MAX_BPF_FUNC_ARGS); i++) {
2357 arg_regs = (m->arg_size[i] + 7) / 8;
2358 if (nr_used_regs + arg_regs <= 6)
2359 nr_used_regs += arg_regs;
2360
2361 if (nr_used_regs >= 6)
2362 break;
2363 }
2364
2365 return nr_used_regs;
2366}
2367
2368static void save_args(const struct btf_func_model *m, u8 **prog,
2369 int stack_size, bool for_call_origin)
2370{
2371 int arg_regs, first_off = 0, nr_regs = 0, nr_stack_slots = 0;
2372 int i, j;
2373
2374 /* Store function arguments to stack.
2375 * For a function that accepts two pointers the sequence will be:
2376 * mov QWORD PTR [rbp-0x10],rdi
2377 * mov QWORD PTR [rbp-0x8],rsi
2378 */
2379 for (i = 0; i < min_t(int, m->nr_args, MAX_BPF_FUNC_ARGS); i++) {
2380 arg_regs = (m->arg_size[i] + 7) / 8;
2381
2382 /* According to the research of Yonghong, struct members
2383 * should be all in register or all on the stack.
2384 * Meanwhile, the compiler will pass the argument on regs
2385 * if the remaining regs can hold the argument.
2386 *
2387 * Disorder of the args can happen. For example:
2388 *
2389 * struct foo_struct {
2390 * long a;
2391 * int b;
2392 * };
2393 * int foo(char, char, char, char, char, struct foo_struct,
2394 * char);
2395 *
2396 * the arg1-5,arg7 will be passed by regs, and arg6 will
2397 * by stack.
2398 */
2399 if (nr_regs + arg_regs > 6) {
2400 /* copy function arguments from origin stack frame
2401 * into current stack frame.
2402 *
2403 * The starting address of the arguments on-stack
2404 * is:
2405 * rbp + 8(push rbp) +
2406 * 8(return addr of origin call) +
2407 * 8(return addr of the caller)
2408 * which means: rbp + 24
2409 */
2410 for (j = 0; j < arg_regs; j++) {
2411 emit_ldx(prog, BPF_DW, BPF_REG_0, BPF_REG_FP,
2412 nr_stack_slots * 8 + 0x18);
2413 emit_stx(prog, BPF_DW, BPF_REG_FP, BPF_REG_0,
2414 -stack_size);
2415
2416 if (!nr_stack_slots)
2417 first_off = stack_size;
2418 stack_size -= 8;
2419 nr_stack_slots++;
2420 }
2421 } else {
2422 /* Only copy the arguments on-stack to current
2423 * 'stack_size' and ignore the regs, used to
2424 * prepare the arguments on-stack for origin call.
2425 */
2426 if (for_call_origin) {
2427 nr_regs += arg_regs;
2428 continue;
2429 }
2430
2431 /* copy the arguments from regs into stack */
2432 for (j = 0; j < arg_regs; j++) {
2433 emit_stx(prog, BPF_DW, BPF_REG_FP,
2434 nr_regs == 5 ? X86_REG_R9 : BPF_REG_1 + nr_regs,
2435 -stack_size);
2436 stack_size -= 8;
2437 nr_regs++;
2438 }
2439 }
2440 }
2441
2442 clean_stack_garbage(m, prog, nr_stack_slots, first_off);
2443}
2444
2445static void restore_regs(const struct btf_func_model *m, u8 **prog,
2446 int stack_size)
2447{
2448 int i, j, arg_regs, nr_regs = 0;
2449
2450 /* Restore function arguments from stack.
2451 * For a function that accepts two pointers the sequence will be:
2452 * EMIT4(0x48, 0x8B, 0x7D, 0xF0); mov rdi,QWORD PTR [rbp-0x10]
2453 * EMIT4(0x48, 0x8B, 0x75, 0xF8); mov rsi,QWORD PTR [rbp-0x8]
2454 *
2455 * The logic here is similar to what we do in save_args()
2456 */
2457 for (i = 0; i < min_t(int, m->nr_args, MAX_BPF_FUNC_ARGS); i++) {
2458 arg_regs = (m->arg_size[i] + 7) / 8;
2459 if (nr_regs + arg_regs <= 6) {
2460 for (j = 0; j < arg_regs; j++) {
2461 emit_ldx(prog, BPF_DW,
2462 nr_regs == 5 ? X86_REG_R9 : BPF_REG_1 + nr_regs,
2463 BPF_REG_FP,
2464 -stack_size);
2465 stack_size -= 8;
2466 nr_regs++;
2467 }
2468 } else {
2469 stack_size -= 8 * arg_regs;
2470 }
2471
2472 if (nr_regs >= 6)
2473 break;
2474 }
2475}
2476
2477static int invoke_bpf_prog(const struct btf_func_model *m, u8 **pprog,
2478 struct bpf_tramp_link *l, int stack_size,
2479 int run_ctx_off, bool save_ret,
2480 void *image, void *rw_image)
2481{
2482 u8 *prog = *pprog;
2483 u8 *jmp_insn;
2484 int ctx_cookie_off = offsetof(struct bpf_tramp_run_ctx, bpf_cookie);
2485 struct bpf_prog *p = l->link.prog;
2486 u64 cookie = l->cookie;
2487
2488 /* mov rdi, cookie */
2489 emit_mov_imm64(&prog, BPF_REG_1, (long) cookie >> 32, (u32) (long) cookie);
2490
2491 /* Prepare struct bpf_tramp_run_ctx.
2492 *
2493 * bpf_tramp_run_ctx is already preserved by
2494 * arch_prepare_bpf_trampoline().
2495 *
2496 * mov QWORD PTR [rbp - run_ctx_off + ctx_cookie_off], rdi
2497 */
2498 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_1, -run_ctx_off + ctx_cookie_off);
2499
2500 /* arg1: mov rdi, progs[i] */
2501 emit_mov_imm64(&prog, BPF_REG_1, (long) p >> 32, (u32) (long) p);
2502 /* arg2: lea rsi, [rbp - ctx_cookie_off] */
2503 if (!is_imm8(-run_ctx_off))
2504 EMIT3_off32(0x48, 0x8D, 0xB5, -run_ctx_off);
2505 else
2506 EMIT4(0x48, 0x8D, 0x75, -run_ctx_off);
2507
2508 if (emit_rsb_call(&prog, bpf_trampoline_enter(p), image + (prog - (u8 *)rw_image)))
2509 return -EINVAL;
2510 /* remember prog start time returned by __bpf_prog_enter */
2511 emit_mov_reg(&prog, true, BPF_REG_6, BPF_REG_0);
2512
2513 /* if (__bpf_prog_enter*(prog) == 0)
2514 * goto skip_exec_of_prog;
2515 */
2516 EMIT3(0x48, 0x85, 0xC0); /* test rax,rax */
2517 /* emit 2 nops that will be replaced with JE insn */
2518 jmp_insn = prog;
2519 emit_nops(&prog, 2);
2520
2521 /* arg1: lea rdi, [rbp - stack_size] */
2522 if (!is_imm8(-stack_size))
2523 EMIT3_off32(0x48, 0x8D, 0xBD, -stack_size);
2524 else
2525 EMIT4(0x48, 0x8D, 0x7D, -stack_size);
2526 /* arg2: progs[i]->insnsi for interpreter */
2527 if (!p->jited)
2528 emit_mov_imm64(&prog, BPF_REG_2,
2529 (long) p->insnsi >> 32,
2530 (u32) (long) p->insnsi);
2531 /* call JITed bpf program or interpreter */
2532 if (emit_rsb_call(&prog, p->bpf_func, image + (prog - (u8 *)rw_image)))
2533 return -EINVAL;
2534
2535 /*
2536 * BPF_TRAMP_MODIFY_RETURN trampolines can modify the return
2537 * of the previous call which is then passed on the stack to
2538 * the next BPF program.
2539 *
2540 * BPF_TRAMP_FENTRY trampoline may need to return the return
2541 * value of BPF_PROG_TYPE_STRUCT_OPS prog.
2542 */
2543 if (save_ret)
2544 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8);
2545
2546 /* replace 2 nops with JE insn, since jmp target is known */
2547 jmp_insn[0] = X86_JE;
2548 jmp_insn[1] = prog - jmp_insn - 2;
2549
2550 /* arg1: mov rdi, progs[i] */
2551 emit_mov_imm64(&prog, BPF_REG_1, (long) p >> 32, (u32) (long) p);
2552 /* arg2: mov rsi, rbx <- start time in nsec */
2553 emit_mov_reg(&prog, true, BPF_REG_2, BPF_REG_6);
2554 /* arg3: lea rdx, [rbp - run_ctx_off] */
2555 if (!is_imm8(-run_ctx_off))
2556 EMIT3_off32(0x48, 0x8D, 0x95, -run_ctx_off);
2557 else
2558 EMIT4(0x48, 0x8D, 0x55, -run_ctx_off);
2559 if (emit_rsb_call(&prog, bpf_trampoline_exit(p), image + (prog - (u8 *)rw_image)))
2560 return -EINVAL;
2561
2562 *pprog = prog;
2563 return 0;
2564}
2565
2566static void emit_align(u8 **pprog, u32 align)
2567{
2568 u8 *target, *prog = *pprog;
2569
2570 target = PTR_ALIGN(prog, align);
2571 if (target != prog)
2572 emit_nops(&prog, target - prog);
2573
2574 *pprog = prog;
2575}
2576
2577static int emit_cond_near_jump(u8 **pprog, void *func, void *ip, u8 jmp_cond)
2578{
2579 u8 *prog = *pprog;
2580 s64 offset;
2581
2582 offset = func - (ip + 2 + 4);
2583 if (!is_simm32(offset)) {
2584 pr_err("Target %p is out of range\n", func);
2585 return -EINVAL;
2586 }
2587 EMIT2_off32(0x0F, jmp_cond + 0x10, offset);
2588 *pprog = prog;
2589 return 0;
2590}
2591
2592static int invoke_bpf(const struct btf_func_model *m, u8 **pprog,
2593 struct bpf_tramp_links *tl, int stack_size,
2594 int run_ctx_off, bool save_ret,
2595 void *image, void *rw_image)
2596{
2597 int i;
2598 u8 *prog = *pprog;
2599
2600 for (i = 0; i < tl->nr_links; i++) {
2601 if (invoke_bpf_prog(m, &prog, tl->links[i], stack_size,
2602 run_ctx_off, save_ret, image, rw_image))
2603 return -EINVAL;
2604 }
2605 *pprog = prog;
2606 return 0;
2607}
2608
2609static int invoke_bpf_mod_ret(const struct btf_func_model *m, u8 **pprog,
2610 struct bpf_tramp_links *tl, int stack_size,
2611 int run_ctx_off, u8 **branches,
2612 void *image, void *rw_image)
2613{
2614 u8 *prog = *pprog;
2615 int i;
2616
2617 /* The first fmod_ret program will receive a garbage return value.
2618 * Set this to 0 to avoid confusing the program.
2619 */
2620 emit_mov_imm32(&prog, false, BPF_REG_0, 0);
2621 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8);
2622 for (i = 0; i < tl->nr_links; i++) {
2623 if (invoke_bpf_prog(m, &prog, tl->links[i], stack_size, run_ctx_off, true,
2624 image, rw_image))
2625 return -EINVAL;
2626
2627 /* mod_ret prog stored return value into [rbp - 8]. Emit:
2628 * if (*(u64 *)(rbp - 8) != 0)
2629 * goto do_fexit;
2630 */
2631 /* cmp QWORD PTR [rbp - 0x8], 0x0 */
2632 EMIT4(0x48, 0x83, 0x7d, 0xf8); EMIT1(0x00);
2633
2634 /* Save the location of the branch and Generate 6 nops
2635 * (4 bytes for an offset and 2 bytes for the jump) These nops
2636 * are replaced with a conditional jump once do_fexit (i.e. the
2637 * start of the fexit invocation) is finalized.
2638 */
2639 branches[i] = prog;
2640 emit_nops(&prog, 4 + 2);
2641 }
2642
2643 *pprog = prog;
2644 return 0;
2645}
2646
2647/* Example:
2648 * __be16 eth_type_trans(struct sk_buff *skb, struct net_device *dev);
2649 * its 'struct btf_func_model' will be nr_args=2
2650 * The assembly code when eth_type_trans is executing after trampoline:
2651 *
2652 * push rbp
2653 * mov rbp, rsp
2654 * sub rsp, 16 // space for skb and dev
2655 * push rbx // temp regs to pass start time
2656 * mov qword ptr [rbp - 16], rdi // save skb pointer to stack
2657 * mov qword ptr [rbp - 8], rsi // save dev pointer to stack
2658 * call __bpf_prog_enter // rcu_read_lock and preempt_disable
2659 * mov rbx, rax // remember start time in bpf stats are enabled
2660 * lea rdi, [rbp - 16] // R1==ctx of bpf prog
2661 * call addr_of_jited_FENTRY_prog
2662 * movabsq rdi, 64bit_addr_of_struct_bpf_prog // unused if bpf stats are off
2663 * mov rsi, rbx // prog start time
2664 * call __bpf_prog_exit // rcu_read_unlock, preempt_enable and stats math
2665 * mov rdi, qword ptr [rbp - 16] // restore skb pointer from stack
2666 * mov rsi, qword ptr [rbp - 8] // restore dev pointer from stack
2667 * pop rbx
2668 * leave
2669 * ret
2670 *
2671 * eth_type_trans has 5 byte nop at the beginning. These 5 bytes will be
2672 * replaced with 'call generated_bpf_trampoline'. When it returns
2673 * eth_type_trans will continue executing with original skb and dev pointers.
2674 *
2675 * The assembly code when eth_type_trans is called from trampoline:
2676 *
2677 * push rbp
2678 * mov rbp, rsp
2679 * sub rsp, 24 // space for skb, dev, return value
2680 * push rbx // temp regs to pass start time
2681 * mov qword ptr [rbp - 24], rdi // save skb pointer to stack
2682 * mov qword ptr [rbp - 16], rsi // save dev pointer to stack
2683 * call __bpf_prog_enter // rcu_read_lock and preempt_disable
2684 * mov rbx, rax // remember start time if bpf stats are enabled
2685 * lea rdi, [rbp - 24] // R1==ctx of bpf prog
2686 * call addr_of_jited_FENTRY_prog // bpf prog can access skb and dev
2687 * movabsq rdi, 64bit_addr_of_struct_bpf_prog // unused if bpf stats are off
2688 * mov rsi, rbx // prog start time
2689 * call __bpf_prog_exit // rcu_read_unlock, preempt_enable and stats math
2690 * mov rdi, qword ptr [rbp - 24] // restore skb pointer from stack
2691 * mov rsi, qword ptr [rbp - 16] // restore dev pointer from stack
2692 * call eth_type_trans+5 // execute body of eth_type_trans
2693 * mov qword ptr [rbp - 8], rax // save return value
2694 * call __bpf_prog_enter // rcu_read_lock and preempt_disable
2695 * mov rbx, rax // remember start time in bpf stats are enabled
2696 * lea rdi, [rbp - 24] // R1==ctx of bpf prog
2697 * call addr_of_jited_FEXIT_prog // bpf prog can access skb, dev, return value
2698 * movabsq rdi, 64bit_addr_of_struct_bpf_prog // unused if bpf stats are off
2699 * mov rsi, rbx // prog start time
2700 * call __bpf_prog_exit // rcu_read_unlock, preempt_enable and stats math
2701 * mov rax, qword ptr [rbp - 8] // restore eth_type_trans's return value
2702 * pop rbx
2703 * leave
2704 * add rsp, 8 // skip eth_type_trans's frame
2705 * ret // return to its caller
2706 */
2707static int __arch_prepare_bpf_trampoline(struct bpf_tramp_image *im, void *rw_image,
2708 void *rw_image_end, void *image,
2709 const struct btf_func_model *m, u32 flags,
2710 struct bpf_tramp_links *tlinks,
2711 void *func_addr)
2712{
2713 int i, ret, nr_regs = m->nr_args, stack_size = 0;
2714 int regs_off, nregs_off, ip_off, run_ctx_off, arg_stack_off, rbx_off;
2715 struct bpf_tramp_links *fentry = &tlinks[BPF_TRAMP_FENTRY];
2716 struct bpf_tramp_links *fexit = &tlinks[BPF_TRAMP_FEXIT];
2717 struct bpf_tramp_links *fmod_ret = &tlinks[BPF_TRAMP_MODIFY_RETURN];
2718 void *orig_call = func_addr;
2719 u8 **branches = NULL;
2720 u8 *prog;
2721 bool save_ret;
2722
2723 /*
2724 * F_INDIRECT is only compatible with F_RET_FENTRY_RET, it is
2725 * explicitly incompatible with F_CALL_ORIG | F_SKIP_FRAME | F_IP_ARG
2726 * because @func_addr.
2727 */
2728 WARN_ON_ONCE((flags & BPF_TRAMP_F_INDIRECT) &&
2729 (flags & ~(BPF_TRAMP_F_INDIRECT | BPF_TRAMP_F_RET_FENTRY_RET)));
2730
2731 /* extra registers for struct arguments */
2732 for (i = 0; i < m->nr_args; i++) {
2733 if (m->arg_flags[i] & BTF_FMODEL_STRUCT_ARG)
2734 nr_regs += (m->arg_size[i] + 7) / 8 - 1;
2735 }
2736
2737 /* x86-64 supports up to MAX_BPF_FUNC_ARGS arguments. 1-6
2738 * are passed through regs, the remains are through stack.
2739 */
2740 if (nr_regs > MAX_BPF_FUNC_ARGS)
2741 return -ENOTSUPP;
2742
2743 /* Generated trampoline stack layout:
2744 *
2745 * RBP + 8 [ return address ]
2746 * RBP + 0 [ RBP ]
2747 *
2748 * RBP - 8 [ return value ] BPF_TRAMP_F_CALL_ORIG or
2749 * BPF_TRAMP_F_RET_FENTRY_RET flags
2750 *
2751 * [ reg_argN ] always
2752 * [ ... ]
2753 * RBP - regs_off [ reg_arg1 ] program's ctx pointer
2754 *
2755 * RBP - nregs_off [ regs count ] always
2756 *
2757 * RBP - ip_off [ traced function ] BPF_TRAMP_F_IP_ARG flag
2758 *
2759 * RBP - rbx_off [ rbx value ] always
2760 *
2761 * RBP - run_ctx_off [ bpf_tramp_run_ctx ]
2762 *
2763 * [ stack_argN ] BPF_TRAMP_F_CALL_ORIG
2764 * [ ... ]
2765 * [ stack_arg2 ]
2766 * RBP - arg_stack_off [ stack_arg1 ]
2767 * RSP [ tail_call_cnt ] BPF_TRAMP_F_TAIL_CALL_CTX
2768 */
2769
2770 /* room for return value of orig_call or fentry prog */
2771 save_ret = flags & (BPF_TRAMP_F_CALL_ORIG | BPF_TRAMP_F_RET_FENTRY_RET);
2772 if (save_ret)
2773 stack_size += 8;
2774
2775 stack_size += nr_regs * 8;
2776 regs_off = stack_size;
2777
2778 /* regs count */
2779 stack_size += 8;
2780 nregs_off = stack_size;
2781
2782 if (flags & BPF_TRAMP_F_IP_ARG)
2783 stack_size += 8; /* room for IP address argument */
2784
2785 ip_off = stack_size;
2786
2787 stack_size += 8;
2788 rbx_off = stack_size;
2789
2790 stack_size += (sizeof(struct bpf_tramp_run_ctx) + 7) & ~0x7;
2791 run_ctx_off = stack_size;
2792
2793 if (nr_regs > 6 && (flags & BPF_TRAMP_F_CALL_ORIG)) {
2794 /* the space that used to pass arguments on-stack */
2795 stack_size += (nr_regs - get_nr_used_regs(m)) * 8;
2796 /* make sure the stack pointer is 16-byte aligned if we
2797 * need pass arguments on stack, which means
2798 * [stack_size + 8(rbp) + 8(rip) + 8(origin rip)]
2799 * should be 16-byte aligned. Following code depend on
2800 * that stack_size is already 8-byte aligned.
2801 */
2802 stack_size += (stack_size % 16) ? 0 : 8;
2803 }
2804
2805 arg_stack_off = stack_size;
2806
2807 if (flags & BPF_TRAMP_F_SKIP_FRAME) {
2808 /* skip patched call instruction and point orig_call to actual
2809 * body of the kernel function.
2810 */
2811 if (is_endbr(*(u32 *)orig_call))
2812 orig_call += ENDBR_INSN_SIZE;
2813 orig_call += X86_PATCH_SIZE;
2814 }
2815
2816 prog = rw_image;
2817
2818 if (flags & BPF_TRAMP_F_INDIRECT) {
2819 /*
2820 * Indirect call for bpf_struct_ops
2821 */
2822 emit_cfi(&prog, cfi_get_func_hash(func_addr));
2823 } else {
2824 /*
2825 * Direct-call fentry stub, as such it needs accounting for the
2826 * __fentry__ call.
2827 */
2828 x86_call_depth_emit_accounting(&prog, NULL, image);
2829 }
2830 EMIT1(0x55); /* push rbp */
2831 EMIT3(0x48, 0x89, 0xE5); /* mov rbp, rsp */
2832 if (!is_imm8(stack_size)) {
2833 /* sub rsp, stack_size */
2834 EMIT3_off32(0x48, 0x81, 0xEC, stack_size);
2835 } else {
2836 /* sub rsp, stack_size */
2837 EMIT4(0x48, 0x83, 0xEC, stack_size);
2838 }
2839 if (flags & BPF_TRAMP_F_TAIL_CALL_CTX)
2840 EMIT1(0x50); /* push rax */
2841 /* mov QWORD PTR [rbp - rbx_off], rbx */
2842 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_6, -rbx_off);
2843
2844 /* Store number of argument registers of the traced function:
2845 * mov rax, nr_regs
2846 * mov QWORD PTR [rbp - nregs_off], rax
2847 */
2848 emit_mov_imm64(&prog, BPF_REG_0, 0, (u32) nr_regs);
2849 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -nregs_off);
2850
2851 if (flags & BPF_TRAMP_F_IP_ARG) {
2852 /* Store IP address of the traced function:
2853 * movabsq rax, func_addr
2854 * mov QWORD PTR [rbp - ip_off], rax
2855 */
2856 emit_mov_imm64(&prog, BPF_REG_0, (long) func_addr >> 32, (u32) (long) func_addr);
2857 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -ip_off);
2858 }
2859
2860 save_args(m, &prog, regs_off, false);
2861
2862 if (flags & BPF_TRAMP_F_CALL_ORIG) {
2863 /* arg1: mov rdi, im */
2864 emit_mov_imm64(&prog, BPF_REG_1, (long) im >> 32, (u32) (long) im);
2865 if (emit_rsb_call(&prog, __bpf_tramp_enter,
2866 image + (prog - (u8 *)rw_image))) {
2867 ret = -EINVAL;
2868 goto cleanup;
2869 }
2870 }
2871
2872 if (fentry->nr_links) {
2873 if (invoke_bpf(m, &prog, fentry, regs_off, run_ctx_off,
2874 flags & BPF_TRAMP_F_RET_FENTRY_RET, image, rw_image))
2875 return -EINVAL;
2876 }
2877
2878 if (fmod_ret->nr_links) {
2879 branches = kcalloc(fmod_ret->nr_links, sizeof(u8 *),
2880 GFP_KERNEL);
2881 if (!branches)
2882 return -ENOMEM;
2883
2884 if (invoke_bpf_mod_ret(m, &prog, fmod_ret, regs_off,
2885 run_ctx_off, branches, image, rw_image)) {
2886 ret = -EINVAL;
2887 goto cleanup;
2888 }
2889 }
2890
2891 if (flags & BPF_TRAMP_F_CALL_ORIG) {
2892 restore_regs(m, &prog, regs_off);
2893 save_args(m, &prog, arg_stack_off, true);
2894
2895 if (flags & BPF_TRAMP_F_TAIL_CALL_CTX) {
2896 /* Before calling the original function, restore the
2897 * tail_call_cnt from stack to rax.
2898 */
2899 RESTORE_TAIL_CALL_CNT(stack_size);
2900 }
2901
2902 if (flags & BPF_TRAMP_F_ORIG_STACK) {
2903 emit_ldx(&prog, BPF_DW, BPF_REG_6, BPF_REG_FP, 8);
2904 EMIT2(0xff, 0xd3); /* call *rbx */
2905 } else {
2906 /* call original function */
2907 if (emit_rsb_call(&prog, orig_call, image + (prog - (u8 *)rw_image))) {
2908 ret = -EINVAL;
2909 goto cleanup;
2910 }
2911 }
2912 /* remember return value in a stack for bpf prog to access */
2913 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8);
2914 im->ip_after_call = image + (prog - (u8 *)rw_image);
2915 emit_nops(&prog, X86_PATCH_SIZE);
2916 }
2917
2918 if (fmod_ret->nr_links) {
2919 /* From Intel 64 and IA-32 Architectures Optimization
2920 * Reference Manual, 3.4.1.4 Code Alignment, Assembly/Compiler
2921 * Coding Rule 11: All branch targets should be 16-byte
2922 * aligned.
2923 */
2924 emit_align(&prog, 16);
2925 /* Update the branches saved in invoke_bpf_mod_ret with the
2926 * aligned address of do_fexit.
2927 */
2928 for (i = 0; i < fmod_ret->nr_links; i++) {
2929 emit_cond_near_jump(&branches[i], image + (prog - (u8 *)rw_image),
2930 image + (branches[i] - (u8 *)rw_image), X86_JNE);
2931 }
2932 }
2933
2934 if (fexit->nr_links) {
2935 if (invoke_bpf(m, &prog, fexit, regs_off, run_ctx_off,
2936 false, image, rw_image)) {
2937 ret = -EINVAL;
2938 goto cleanup;
2939 }
2940 }
2941
2942 if (flags & BPF_TRAMP_F_RESTORE_REGS)
2943 restore_regs(m, &prog, regs_off);
2944
2945 /* This needs to be done regardless. If there were fmod_ret programs,
2946 * the return value is only updated on the stack and still needs to be
2947 * restored to R0.
2948 */
2949 if (flags & BPF_TRAMP_F_CALL_ORIG) {
2950 im->ip_epilogue = image + (prog - (u8 *)rw_image);
2951 /* arg1: mov rdi, im */
2952 emit_mov_imm64(&prog, BPF_REG_1, (long) im >> 32, (u32) (long) im);
2953 if (emit_rsb_call(&prog, __bpf_tramp_exit, image + (prog - (u8 *)rw_image))) {
2954 ret = -EINVAL;
2955 goto cleanup;
2956 }
2957 } else if (flags & BPF_TRAMP_F_TAIL_CALL_CTX) {
2958 /* Before running the original function, restore the
2959 * tail_call_cnt from stack to rax.
2960 */
2961 RESTORE_TAIL_CALL_CNT(stack_size);
2962 }
2963
2964 /* restore return value of orig_call or fentry prog back into RAX */
2965 if (save_ret)
2966 emit_ldx(&prog, BPF_DW, BPF_REG_0, BPF_REG_FP, -8);
2967
2968 emit_ldx(&prog, BPF_DW, BPF_REG_6, BPF_REG_FP, -rbx_off);
2969 EMIT1(0xC9); /* leave */
2970 if (flags & BPF_TRAMP_F_SKIP_FRAME) {
2971 /* skip our return address and return to parent */
2972 EMIT4(0x48, 0x83, 0xC4, 8); /* add rsp, 8 */
2973 }
2974 emit_return(&prog, image + (prog - (u8 *)rw_image));
2975 /* Make sure the trampoline generation logic doesn't overflow */
2976 if (WARN_ON_ONCE(prog > (u8 *)rw_image_end - BPF_INSN_SAFETY)) {
2977 ret = -EFAULT;
2978 goto cleanup;
2979 }
2980 ret = prog - (u8 *)rw_image + BPF_INSN_SAFETY;
2981
2982cleanup:
2983 kfree(branches);
2984 return ret;
2985}
2986
2987void *arch_alloc_bpf_trampoline(unsigned int size)
2988{
2989 return bpf_prog_pack_alloc(size, jit_fill_hole);
2990}
2991
2992void arch_free_bpf_trampoline(void *image, unsigned int size)
2993{
2994 bpf_prog_pack_free(image, size);
2995}
2996
2997void arch_protect_bpf_trampoline(void *image, unsigned int size)
2998{
2999}
3000
3001void arch_unprotect_bpf_trampoline(void *image, unsigned int size)
3002{
3003}
3004
3005int arch_prepare_bpf_trampoline(struct bpf_tramp_image *im, void *image, void *image_end,
3006 const struct btf_func_model *m, u32 flags,
3007 struct bpf_tramp_links *tlinks,
3008 void *func_addr)
3009{
3010 void *rw_image, *tmp;
3011 int ret;
3012 u32 size = image_end - image;
3013
3014 /* rw_image doesn't need to be in module memory range, so we can
3015 * use kvmalloc.
3016 */
3017 rw_image = kvmalloc(size, GFP_KERNEL);
3018 if (!rw_image)
3019 return -ENOMEM;
3020
3021 ret = __arch_prepare_bpf_trampoline(im, rw_image, rw_image + size, image, m,
3022 flags, tlinks, func_addr);
3023 if (ret < 0)
3024 goto out;
3025
3026 tmp = bpf_arch_text_copy(image, rw_image, size);
3027 if (IS_ERR(tmp))
3028 ret = PTR_ERR(tmp);
3029out:
3030 kvfree(rw_image);
3031 return ret;
3032}
3033
3034int arch_bpf_trampoline_size(const struct btf_func_model *m, u32 flags,
3035 struct bpf_tramp_links *tlinks, void *func_addr)
3036{
3037 struct bpf_tramp_image im;
3038 void *image;
3039 int ret;
3040
3041 /* Allocate a temporary buffer for __arch_prepare_bpf_trampoline().
3042 * This will NOT cause fragmentation in direct map, as we do not
3043 * call set_memory_*() on this buffer.
3044 *
3045 * We cannot use kvmalloc here, because we need image to be in
3046 * module memory range.
3047 */
3048 image = bpf_jit_alloc_exec(PAGE_SIZE);
3049 if (!image)
3050 return -ENOMEM;
3051
3052 ret = __arch_prepare_bpf_trampoline(&im, image, image + PAGE_SIZE, image,
3053 m, flags, tlinks, func_addr);
3054 bpf_jit_free_exec(image);
3055 return ret;
3056}
3057
3058static int emit_bpf_dispatcher(u8 **pprog, int a, int b, s64 *progs, u8 *image, u8 *buf)
3059{
3060 u8 *jg_reloc, *prog = *pprog;
3061 int pivot, err, jg_bytes = 1;
3062 s64 jg_offset;
3063
3064 if (a == b) {
3065 /* Leaf node of recursion, i.e. not a range of indices
3066 * anymore.
3067 */
3068 EMIT1(add_1mod(0x48, BPF_REG_3)); /* cmp rdx,func */
3069 if (!is_simm32(progs[a]))
3070 return -1;
3071 EMIT2_off32(0x81, add_1reg(0xF8, BPF_REG_3),
3072 progs[a]);
3073 err = emit_cond_near_jump(&prog, /* je func */
3074 (void *)progs[a], image + (prog - buf),
3075 X86_JE);
3076 if (err)
3077 return err;
3078
3079 emit_indirect_jump(&prog, 2 /* rdx */, image + (prog - buf));
3080
3081 *pprog = prog;
3082 return 0;
3083 }
3084
3085 /* Not a leaf node, so we pivot, and recursively descend into
3086 * the lower and upper ranges.
3087 */
3088 pivot = (b - a) / 2;
3089 EMIT1(add_1mod(0x48, BPF_REG_3)); /* cmp rdx,func */
3090 if (!is_simm32(progs[a + pivot]))
3091 return -1;
3092 EMIT2_off32(0x81, add_1reg(0xF8, BPF_REG_3), progs[a + pivot]);
3093
3094 if (pivot > 2) { /* jg upper_part */
3095 /* Require near jump. */
3096 jg_bytes = 4;
3097 EMIT2_off32(0x0F, X86_JG + 0x10, 0);
3098 } else {
3099 EMIT2(X86_JG, 0);
3100 }
3101 jg_reloc = prog;
3102
3103 err = emit_bpf_dispatcher(&prog, a, a + pivot, /* emit lower_part */
3104 progs, image, buf);
3105 if (err)
3106 return err;
3107
3108 /* From Intel 64 and IA-32 Architectures Optimization
3109 * Reference Manual, 3.4.1.4 Code Alignment, Assembly/Compiler
3110 * Coding Rule 11: All branch targets should be 16-byte
3111 * aligned.
3112 */
3113 emit_align(&prog, 16);
3114 jg_offset = prog - jg_reloc;
3115 emit_code(jg_reloc - jg_bytes, jg_offset, jg_bytes);
3116
3117 err = emit_bpf_dispatcher(&prog, a + pivot + 1, /* emit upper_part */
3118 b, progs, image, buf);
3119 if (err)
3120 return err;
3121
3122 *pprog = prog;
3123 return 0;
3124}
3125
3126static int cmp_ips(const void *a, const void *b)
3127{
3128 const s64 *ipa = a;
3129 const s64 *ipb = b;
3130
3131 if (*ipa > *ipb)
3132 return 1;
3133 if (*ipa < *ipb)
3134 return -1;
3135 return 0;
3136}
3137
3138int arch_prepare_bpf_dispatcher(void *image, void *buf, s64 *funcs, int num_funcs)
3139{
3140 u8 *prog = buf;
3141
3142 sort(funcs, num_funcs, sizeof(funcs[0]), cmp_ips, NULL);
3143 return emit_bpf_dispatcher(&prog, 0, num_funcs - 1, funcs, image, buf);
3144}
3145
3146struct x64_jit_data {
3147 struct bpf_binary_header *rw_header;
3148 struct bpf_binary_header *header;
3149 int *addrs;
3150 u8 *image;
3151 int proglen;
3152 struct jit_context ctx;
3153};
3154
3155#define MAX_PASSES 20
3156#define PADDING_PASSES (MAX_PASSES - 5)
3157
3158struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog)
3159{
3160 struct bpf_binary_header *rw_header = NULL;
3161 struct bpf_binary_header *header = NULL;
3162 struct bpf_prog *tmp, *orig_prog = prog;
3163 struct x64_jit_data *jit_data;
3164 int proglen, oldproglen = 0;
3165 struct jit_context ctx = {};
3166 bool tmp_blinded = false;
3167 bool extra_pass = false;
3168 bool padding = false;
3169 u8 *rw_image = NULL;
3170 u8 *image = NULL;
3171 int *addrs;
3172 int pass;
3173 int i;
3174
3175 if (!prog->jit_requested)
3176 return orig_prog;
3177
3178 tmp = bpf_jit_blind_constants(prog);
3179 /*
3180 * If blinding was requested and we failed during blinding,
3181 * we must fall back to the interpreter.
3182 */
3183 if (IS_ERR(tmp))
3184 return orig_prog;
3185 if (tmp != prog) {
3186 tmp_blinded = true;
3187 prog = tmp;
3188 }
3189
3190 jit_data = prog->aux->jit_data;
3191 if (!jit_data) {
3192 jit_data = kzalloc(sizeof(*jit_data), GFP_KERNEL);
3193 if (!jit_data) {
3194 prog = orig_prog;
3195 goto out;
3196 }
3197 prog->aux->jit_data = jit_data;
3198 }
3199 addrs = jit_data->addrs;
3200 if (addrs) {
3201 ctx = jit_data->ctx;
3202 oldproglen = jit_data->proglen;
3203 image = jit_data->image;
3204 header = jit_data->header;
3205 rw_header = jit_data->rw_header;
3206 rw_image = (void *)rw_header + ((void *)image - (void *)header);
3207 extra_pass = true;
3208 padding = true;
3209 goto skip_init_addrs;
3210 }
3211 addrs = kvmalloc_array(prog->len + 1, sizeof(*addrs), GFP_KERNEL);
3212 if (!addrs) {
3213 prog = orig_prog;
3214 goto out_addrs;
3215 }
3216
3217 /*
3218 * Before first pass, make a rough estimation of addrs[]
3219 * each BPF instruction is translated to less than 64 bytes
3220 */
3221 for (proglen = 0, i = 0; i <= prog->len; i++) {
3222 proglen += 64;
3223 addrs[i] = proglen;
3224 }
3225 ctx.cleanup_addr = proglen;
3226skip_init_addrs:
3227
3228 /*
3229 * JITed image shrinks with every pass and the loop iterates
3230 * until the image stops shrinking. Very large BPF programs
3231 * may converge on the last pass. In such case do one more
3232 * pass to emit the final image.
3233 */
3234 for (pass = 0; pass < MAX_PASSES || image; pass++) {
3235 if (!padding && pass >= PADDING_PASSES)
3236 padding = true;
3237 proglen = do_jit(prog, addrs, image, rw_image, oldproglen, &ctx, padding);
3238 if (proglen <= 0) {
3239out_image:
3240 image = NULL;
3241 if (header) {
3242 bpf_arch_text_copy(&header->size, &rw_header->size,
3243 sizeof(rw_header->size));
3244 bpf_jit_binary_pack_free(header, rw_header);
3245 }
3246 /* Fall back to interpreter mode */
3247 prog = orig_prog;
3248 if (extra_pass) {
3249 prog->bpf_func = NULL;
3250 prog->jited = 0;
3251 prog->jited_len = 0;
3252 }
3253 goto out_addrs;
3254 }
3255 if (image) {
3256 if (proglen != oldproglen) {
3257 pr_err("bpf_jit: proglen=%d != oldproglen=%d\n",
3258 proglen, oldproglen);
3259 goto out_image;
3260 }
3261 break;
3262 }
3263 if (proglen == oldproglen) {
3264 /*
3265 * The number of entries in extable is the number of BPF_LDX
3266 * insns that access kernel memory via "pointer to BTF type".
3267 * The verifier changed their opcode from LDX|MEM|size
3268 * to LDX|PROBE_MEM|size to make JITing easier.
3269 */
3270 u32 align = __alignof__(struct exception_table_entry);
3271 u32 extable_size = prog->aux->num_exentries *
3272 sizeof(struct exception_table_entry);
3273
3274 /* allocate module memory for x86 insns and extable */
3275 header = bpf_jit_binary_pack_alloc(roundup(proglen, align) + extable_size,
3276 &image, align, &rw_header, &rw_image,
3277 jit_fill_hole);
3278 if (!header) {
3279 prog = orig_prog;
3280 goto out_addrs;
3281 }
3282 prog->aux->extable = (void *) image + roundup(proglen, align);
3283 }
3284 oldproglen = proglen;
3285 cond_resched();
3286 }
3287
3288 if (bpf_jit_enable > 1)
3289 bpf_jit_dump(prog->len, proglen, pass + 1, rw_image);
3290
3291 if (image) {
3292 if (!prog->is_func || extra_pass) {
3293 /*
3294 * bpf_jit_binary_pack_finalize fails in two scenarios:
3295 * 1) header is not pointing to proper module memory;
3296 * 2) the arch doesn't support bpf_arch_text_copy().
3297 *
3298 * Both cases are serious bugs and justify WARN_ON.
3299 */
3300 if (WARN_ON(bpf_jit_binary_pack_finalize(prog, header, rw_header))) {
3301 /* header has been freed */
3302 header = NULL;
3303 goto out_image;
3304 }
3305
3306 bpf_tail_call_direct_fixup(prog);
3307 } else {
3308 jit_data->addrs = addrs;
3309 jit_data->ctx = ctx;
3310 jit_data->proglen = proglen;
3311 jit_data->image = image;
3312 jit_data->header = header;
3313 jit_data->rw_header = rw_header;
3314 }
3315 /*
3316 * ctx.prog_offset is used when CFI preambles put code *before*
3317 * the function. See emit_cfi(). For FineIBT specifically this code
3318 * can also be executed and bpf_prog_kallsyms_add() will
3319 * generate an additional symbol to cover this, hence also
3320 * decrement proglen.
3321 */
3322 prog->bpf_func = (void *)image + cfi_get_offset();
3323 prog->jited = 1;
3324 prog->jited_len = proglen - cfi_get_offset();
3325 } else {
3326 prog = orig_prog;
3327 }
3328
3329 if (!image || !prog->is_func || extra_pass) {
3330 if (image)
3331 bpf_prog_fill_jited_linfo(prog, addrs + 1);
3332out_addrs:
3333 kvfree(addrs);
3334 kfree(jit_data);
3335 prog->aux->jit_data = NULL;
3336 }
3337out:
3338 if (tmp_blinded)
3339 bpf_jit_prog_release_other(prog, prog == orig_prog ?
3340 tmp : orig_prog);
3341 return prog;
3342}
3343
3344bool bpf_jit_supports_kfunc_call(void)
3345{
3346 return true;
3347}
3348
3349void *bpf_arch_text_copy(void *dst, void *src, size_t len)
3350{
3351 if (text_poke_copy(dst, src, len) == NULL)
3352 return ERR_PTR(-EINVAL);
3353 return dst;
3354}
3355
3356/* Indicate the JIT backend supports mixing bpf2bpf and tailcalls. */
3357bool bpf_jit_supports_subprog_tailcalls(void)
3358{
3359 return true;
3360}
3361
3362void bpf_jit_free(struct bpf_prog *prog)
3363{
3364 if (prog->jited) {
3365 struct x64_jit_data *jit_data = prog->aux->jit_data;
3366 struct bpf_binary_header *hdr;
3367
3368 /*
3369 * If we fail the final pass of JIT (from jit_subprogs),
3370 * the program may not be finalized yet. Call finalize here
3371 * before freeing it.
3372 */
3373 if (jit_data) {
3374 bpf_jit_binary_pack_finalize(prog, jit_data->header,
3375 jit_data->rw_header);
3376 kvfree(jit_data->addrs);
3377 kfree(jit_data);
3378 }
3379 prog->bpf_func = (void *)prog->bpf_func - cfi_get_offset();
3380 hdr = bpf_jit_binary_pack_hdr(prog);
3381 bpf_jit_binary_pack_free(hdr, NULL);
3382 WARN_ON_ONCE(!bpf_prog_kallsyms_verify_off(prog));
3383 }
3384
3385 bpf_prog_unlock_free(prog);
3386}
3387
3388bool bpf_jit_supports_exceptions(void)
3389{
3390 /* We unwind through both kernel frames (starting from within bpf_throw
3391 * call) and BPF frames. Therefore we require ORC unwinder to be enabled
3392 * to walk kernel frames and reach BPF frames in the stack trace.
3393 */
3394 return IS_ENABLED(CONFIG_UNWINDER_ORC);
3395}
3396
3397void arch_bpf_stack_walk(bool (*consume_fn)(void *cookie, u64 ip, u64 sp, u64 bp), void *cookie)
3398{
3399#if defined(CONFIG_UNWINDER_ORC)
3400 struct unwind_state state;
3401 unsigned long addr;
3402
3403 for (unwind_start(&state, current, NULL, NULL); !unwind_done(&state);
3404 unwind_next_frame(&state)) {
3405 addr = unwind_get_return_address(&state);
3406 if (!addr || !consume_fn(cookie, (u64)addr, (u64)state.sp, (u64)state.bp))
3407 break;
3408 }
3409 return;
3410#endif
3411 WARN(1, "verification of programs using bpf_throw should have failed\n");
3412}
3413
3414void bpf_arch_poke_desc_update(struct bpf_jit_poke_descriptor *poke,
3415 struct bpf_prog *new, struct bpf_prog *old)
3416{
3417 u8 *old_addr, *new_addr, *old_bypass_addr;
3418 int ret;
3419
3420 old_bypass_addr = old ? NULL : poke->bypass_addr;
3421 old_addr = old ? (u8 *)old->bpf_func + poke->adj_off : NULL;
3422 new_addr = new ? (u8 *)new->bpf_func + poke->adj_off : NULL;
3423
3424 /*
3425 * On program loading or teardown, the program's kallsym entry
3426 * might not be in place, so we use __bpf_arch_text_poke to skip
3427 * the kallsyms check.
3428 */
3429 if (new) {
3430 ret = __bpf_arch_text_poke(poke->tailcall_target,
3431 BPF_MOD_JUMP,
3432 old_addr, new_addr);
3433 BUG_ON(ret < 0);
3434 if (!old) {
3435 ret = __bpf_arch_text_poke(poke->tailcall_bypass,
3436 BPF_MOD_JUMP,
3437 poke->bypass_addr,
3438 NULL);
3439 BUG_ON(ret < 0);
3440 }
3441 } else {
3442 ret = __bpf_arch_text_poke(poke->tailcall_bypass,
3443 BPF_MOD_JUMP,
3444 old_bypass_addr,
3445 poke->bypass_addr);
3446 BUG_ON(ret < 0);
3447 /* let other CPUs finish the execution of program
3448 * so that it will not possible to expose them
3449 * to invalid nop, stack unwind, nop state
3450 */
3451 if (!ret)
3452 synchronize_rcu();
3453 ret = __bpf_arch_text_poke(poke->tailcall_target,
3454 BPF_MOD_JUMP,
3455 old_addr, NULL);
3456 BUG_ON(ret < 0);
3457 }
3458}
3459
3460bool bpf_jit_supports_arena(void)
3461{
3462 return true;
3463}
3464
3465bool bpf_jit_supports_ptr_xchg(void)
3466{
3467 return true;
3468}
3469
3470/* x86-64 JIT emits its own code to filter user addresses so return 0 here */
3471u64 bpf_arch_uaddress_limit(void)
3472{
3473 return 0;
3474}