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1/*
2 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 platform PWM support
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#include <linux/clk.h>
17#include <linux/err.h>
18#include <linux/gpio.h>
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/of_device.h>
22#include <linux/platform_device.h>
23#include <linux/pwm.h>
24
25#include <asm/mach-jz4740/timer.h>
26
27#define NUM_PWM 8
28
29struct jz4740_pwm_chip {
30 struct pwm_chip chip;
31 struct clk *clk;
32};
33
34static inline struct jz4740_pwm_chip *to_jz4740(struct pwm_chip *chip)
35{
36 return container_of(chip, struct jz4740_pwm_chip, chip);
37}
38
39static int jz4740_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
40{
41 /*
42 * Timers 0 and 1 are used for system tasks, so they are unavailable
43 * for use as PWMs.
44 */
45 if (pwm->hwpwm < 2)
46 return -EBUSY;
47
48 jz4740_timer_start(pwm->hwpwm);
49
50 return 0;
51}
52
53static void jz4740_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
54{
55 jz4740_timer_set_ctrl(pwm->hwpwm, 0);
56
57 jz4740_timer_stop(pwm->hwpwm);
58}
59
60static int jz4740_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
61{
62 uint32_t ctrl = jz4740_timer_get_ctrl(pwm->pwm);
63
64 ctrl |= JZ_TIMER_CTRL_PWM_ENABLE;
65 jz4740_timer_set_ctrl(pwm->hwpwm, ctrl);
66 jz4740_timer_enable(pwm->hwpwm);
67
68 return 0;
69}
70
71static void jz4740_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
72{
73 uint32_t ctrl = jz4740_timer_get_ctrl(pwm->hwpwm);
74
75 /* Disable PWM output.
76 * In TCU2 mode (channel 1/2 on JZ4750+), this must be done before the
77 * counter is stopped, while in TCU1 mode the order does not matter.
78 */
79 ctrl &= ~JZ_TIMER_CTRL_PWM_ENABLE;
80 jz4740_timer_set_ctrl(pwm->hwpwm, ctrl);
81
82 /* Stop counter */
83 jz4740_timer_disable(pwm->hwpwm);
84}
85
86static int jz4740_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
87 int duty_ns, int period_ns)
88{
89 struct jz4740_pwm_chip *jz4740 = to_jz4740(pwm->chip);
90 unsigned long long tmp;
91 unsigned long period, duty;
92 unsigned int prescaler = 0;
93 uint16_t ctrl;
94 bool is_enabled;
95
96 tmp = (unsigned long long)clk_get_rate(jz4740->clk) * period_ns;
97 do_div(tmp, 1000000000);
98 period = tmp;
99
100 while (period > 0xffff && prescaler < 6) {
101 period >>= 2;
102 ++prescaler;
103 }
104
105 if (prescaler == 6)
106 return -EINVAL;
107
108 tmp = (unsigned long long)period * duty_ns;
109 do_div(tmp, period_ns);
110 duty = period - tmp;
111
112 if (duty >= period)
113 duty = period - 1;
114
115 is_enabled = jz4740_timer_is_enabled(pwm->hwpwm);
116 if (is_enabled)
117 jz4740_pwm_disable(chip, pwm);
118
119 jz4740_timer_set_count(pwm->hwpwm, 0);
120 jz4740_timer_set_duty(pwm->hwpwm, duty);
121 jz4740_timer_set_period(pwm->hwpwm, period);
122
123 ctrl = JZ_TIMER_CTRL_PRESCALER(prescaler) | JZ_TIMER_CTRL_SRC_EXT |
124 JZ_TIMER_CTRL_PWM_ABBRUPT_SHUTDOWN;
125
126 jz4740_timer_set_ctrl(pwm->hwpwm, ctrl);
127
128 if (is_enabled)
129 jz4740_pwm_enable(chip, pwm);
130
131 return 0;
132}
133
134static int jz4740_pwm_set_polarity(struct pwm_chip *chip,
135 struct pwm_device *pwm, enum pwm_polarity polarity)
136{
137 uint32_t ctrl = jz4740_timer_get_ctrl(pwm->pwm);
138
139 switch (polarity) {
140 case PWM_POLARITY_NORMAL:
141 ctrl &= ~JZ_TIMER_CTRL_PWM_ACTIVE_LOW;
142 break;
143 case PWM_POLARITY_INVERSED:
144 ctrl |= JZ_TIMER_CTRL_PWM_ACTIVE_LOW;
145 break;
146 }
147
148 jz4740_timer_set_ctrl(pwm->hwpwm, ctrl);
149 return 0;
150}
151
152static const struct pwm_ops jz4740_pwm_ops = {
153 .request = jz4740_pwm_request,
154 .free = jz4740_pwm_free,
155 .config = jz4740_pwm_config,
156 .set_polarity = jz4740_pwm_set_polarity,
157 .enable = jz4740_pwm_enable,
158 .disable = jz4740_pwm_disable,
159 .owner = THIS_MODULE,
160};
161
162static int jz4740_pwm_probe(struct platform_device *pdev)
163{
164 struct jz4740_pwm_chip *jz4740;
165
166 jz4740 = devm_kzalloc(&pdev->dev, sizeof(*jz4740), GFP_KERNEL);
167 if (!jz4740)
168 return -ENOMEM;
169
170 jz4740->clk = devm_clk_get(&pdev->dev, "ext");
171 if (IS_ERR(jz4740->clk))
172 return PTR_ERR(jz4740->clk);
173
174 jz4740->chip.dev = &pdev->dev;
175 jz4740->chip.ops = &jz4740_pwm_ops;
176 jz4740->chip.npwm = NUM_PWM;
177 jz4740->chip.base = -1;
178 jz4740->chip.of_xlate = of_pwm_xlate_with_flags;
179 jz4740->chip.of_pwm_n_cells = 3;
180
181 platform_set_drvdata(pdev, jz4740);
182
183 return pwmchip_add(&jz4740->chip);
184}
185
186static int jz4740_pwm_remove(struct platform_device *pdev)
187{
188 struct jz4740_pwm_chip *jz4740 = platform_get_drvdata(pdev);
189
190 return pwmchip_remove(&jz4740->chip);
191}
192
193#ifdef CONFIG_OF
194static const struct of_device_id jz4740_pwm_dt_ids[] = {
195 { .compatible = "ingenic,jz4740-pwm", },
196 { .compatible = "ingenic,jz4770-pwm", },
197 { .compatible = "ingenic,jz4780-pwm", },
198 {},
199};
200MODULE_DEVICE_TABLE(of, jz4740_pwm_dt_ids);
201#endif
202
203static struct platform_driver jz4740_pwm_driver = {
204 .driver = {
205 .name = "jz4740-pwm",
206 .of_match_table = of_match_ptr(jz4740_pwm_dt_ids),
207 },
208 .probe = jz4740_pwm_probe,
209 .remove = jz4740_pwm_remove,
210};
211module_platform_driver(jz4740_pwm_driver);
212
213MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
214MODULE_DESCRIPTION("Ingenic JZ4740 PWM driver");
215MODULE_ALIAS("platform:jz4740-pwm");
216MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
4 * JZ4740 platform PWM support
5 *
6 * Limitations:
7 * - The .apply callback doesn't complete the currently running period before
8 * reconfiguring the hardware.
9 */
10
11#include <linux/clk.h>
12#include <linux/err.h>
13#include <linux/gpio.h>
14#include <linux/kernel.h>
15#include <linux/mfd/ingenic-tcu.h>
16#include <linux/mfd/syscon.h>
17#include <linux/module.h>
18#include <linux/of.h>
19#include <linux/platform_device.h>
20#include <linux/pwm.h>
21#include <linux/regmap.h>
22
23struct soc_info {
24 unsigned int num_pwms;
25};
26
27struct jz4740_pwm_chip {
28 struct pwm_chip chip;
29 struct regmap *map;
30 struct clk *clk[];
31};
32
33static inline struct jz4740_pwm_chip *to_jz4740(struct pwm_chip *chip)
34{
35 return container_of(chip, struct jz4740_pwm_chip, chip);
36}
37
38static bool jz4740_pwm_can_use_chn(struct jz4740_pwm_chip *jz,
39 unsigned int channel)
40{
41 /* Enable all TCU channels for PWM use by default except channels 0/1 */
42 u32 pwm_channels_mask = GENMASK(jz->chip.npwm - 1, 2);
43
44 device_property_read_u32(jz->chip.dev->parent,
45 "ingenic,pwm-channels-mask",
46 &pwm_channels_mask);
47
48 return !!(pwm_channels_mask & BIT(channel));
49}
50
51static int jz4740_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
52{
53 struct jz4740_pwm_chip *jz = to_jz4740(chip);
54 struct clk *clk;
55 char name[16];
56 int err;
57
58 if (!jz4740_pwm_can_use_chn(jz, pwm->hwpwm))
59 return -EBUSY;
60
61 snprintf(name, sizeof(name), "timer%u", pwm->hwpwm);
62
63 clk = clk_get(chip->dev, name);
64 if (IS_ERR(clk)) {
65 dev_err(chip->dev, "error %pe: Failed to get clock\n", clk);
66 return PTR_ERR(clk);
67 }
68
69 err = clk_prepare_enable(clk);
70 if (err < 0) {
71 clk_put(clk);
72 return err;
73 }
74
75 jz->clk[pwm->hwpwm] = clk;
76
77 return 0;
78}
79
80static void jz4740_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
81{
82 struct jz4740_pwm_chip *jz = to_jz4740(chip);
83 struct clk *clk = jz->clk[pwm->hwpwm];
84
85 clk_disable_unprepare(clk);
86 clk_put(clk);
87}
88
89static int jz4740_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
90{
91 struct jz4740_pwm_chip *jz = to_jz4740(chip);
92
93 /* Enable PWM output */
94 regmap_set_bits(jz->map, TCU_REG_TCSRc(pwm->hwpwm), TCU_TCSR_PWM_EN);
95
96 /* Start counter */
97 regmap_write(jz->map, TCU_REG_TESR, BIT(pwm->hwpwm));
98
99 return 0;
100}
101
102static void jz4740_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
103{
104 struct jz4740_pwm_chip *jz = to_jz4740(chip);
105
106 /*
107 * Set duty > period. This trick allows the TCU channels in TCU2 mode to
108 * properly return to their init level.
109 */
110 regmap_write(jz->map, TCU_REG_TDHRc(pwm->hwpwm), 0xffff);
111 regmap_write(jz->map, TCU_REG_TDFRc(pwm->hwpwm), 0x0);
112
113 /*
114 * Disable PWM output.
115 * In TCU2 mode (channel 1/2 on JZ4750+), this must be done before the
116 * counter is stopped, while in TCU1 mode the order does not matter.
117 */
118 regmap_clear_bits(jz->map, TCU_REG_TCSRc(pwm->hwpwm), TCU_TCSR_PWM_EN);
119
120 /* Stop counter */
121 regmap_write(jz->map, TCU_REG_TECR, BIT(pwm->hwpwm));
122}
123
124static int jz4740_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
125 const struct pwm_state *state)
126{
127 struct jz4740_pwm_chip *jz = to_jz4740(chip);
128 unsigned long long tmp = 0xffffull * NSEC_PER_SEC;
129 struct clk *clk = jz->clk[pwm->hwpwm];
130 unsigned long period, duty;
131 long rate;
132 int err;
133
134 /*
135 * Limit the clock to a maximum rate that still gives us a period value
136 * which fits in 16 bits.
137 */
138 do_div(tmp, state->period);
139
140 /*
141 * /!\ IMPORTANT NOTE:
142 * -------------------
143 * This code relies on the fact that clk_round_rate() will always round
144 * down, which is not a valid assumption given by the clk API, but only
145 * happens to be true with the clk drivers used for Ingenic SoCs.
146 *
147 * Right now, there is no alternative as the clk API does not have a
148 * round-down function (and won't have one for a while), but if it ever
149 * comes to light, a round-down function should be used instead.
150 */
151 rate = clk_round_rate(clk, tmp);
152 if (rate < 0) {
153 dev_err(chip->dev, "Unable to round rate: %ld\n", rate);
154 return rate;
155 }
156
157 /* Calculate period value */
158 tmp = (unsigned long long)rate * state->period;
159 do_div(tmp, NSEC_PER_SEC);
160 period = tmp;
161
162 /* Calculate duty value */
163 tmp = (unsigned long long)rate * state->duty_cycle;
164 do_div(tmp, NSEC_PER_SEC);
165 duty = tmp;
166
167 if (duty >= period)
168 duty = period - 1;
169
170 jz4740_pwm_disable(chip, pwm);
171
172 err = clk_set_rate(clk, rate);
173 if (err) {
174 dev_err(chip->dev, "Unable to set rate: %d\n", err);
175 return err;
176 }
177
178 /* Reset counter to 0 */
179 regmap_write(jz->map, TCU_REG_TCNTc(pwm->hwpwm), 0);
180
181 /* Set duty */
182 regmap_write(jz->map, TCU_REG_TDHRc(pwm->hwpwm), duty);
183
184 /* Set period */
185 regmap_write(jz->map, TCU_REG_TDFRc(pwm->hwpwm), period);
186
187 /* Set abrupt shutdown */
188 regmap_set_bits(jz->map, TCU_REG_TCSRc(pwm->hwpwm),
189 TCU_TCSR_PWM_SD);
190
191 /*
192 * Set polarity.
193 *
194 * The PWM starts in inactive state until the internal timer reaches the
195 * duty value, then becomes active until the timer reaches the period
196 * value. In theory, we should then use (period - duty) as the real duty
197 * value, as a high duty value would otherwise result in the PWM pin
198 * being inactive most of the time.
199 *
200 * Here, we don't do that, and instead invert the polarity of the PWM
201 * when it is active. This trick makes the PWM start with its active
202 * state instead of its inactive state.
203 */
204 if ((state->polarity == PWM_POLARITY_NORMAL) ^ state->enabled)
205 regmap_update_bits(jz->map, TCU_REG_TCSRc(pwm->hwpwm),
206 TCU_TCSR_PWM_INITL_HIGH, 0);
207 else
208 regmap_update_bits(jz->map, TCU_REG_TCSRc(pwm->hwpwm),
209 TCU_TCSR_PWM_INITL_HIGH,
210 TCU_TCSR_PWM_INITL_HIGH);
211
212 if (state->enabled)
213 jz4740_pwm_enable(chip, pwm);
214
215 return 0;
216}
217
218static const struct pwm_ops jz4740_pwm_ops = {
219 .request = jz4740_pwm_request,
220 .free = jz4740_pwm_free,
221 .apply = jz4740_pwm_apply,
222};
223
224static int jz4740_pwm_probe(struct platform_device *pdev)
225{
226 struct device *dev = &pdev->dev;
227 struct jz4740_pwm_chip *jz;
228 const struct soc_info *info;
229
230 info = device_get_match_data(dev);
231 if (!info)
232 return -EINVAL;
233
234 jz = devm_kzalloc(dev, struct_size(jz, clk, info->num_pwms),
235 GFP_KERNEL);
236 if (!jz)
237 return -ENOMEM;
238
239 jz->map = device_node_to_regmap(dev->parent->of_node);
240 if (IS_ERR(jz->map)) {
241 dev_err(dev, "regmap not found: %ld\n", PTR_ERR(jz->map));
242 return PTR_ERR(jz->map);
243 }
244
245 jz->chip.dev = dev;
246 jz->chip.ops = &jz4740_pwm_ops;
247 jz->chip.npwm = info->num_pwms;
248
249 return devm_pwmchip_add(dev, &jz->chip);
250}
251
252static const struct soc_info jz4740_soc_info = {
253 .num_pwms = 8,
254};
255
256static const struct soc_info jz4725b_soc_info = {
257 .num_pwms = 6,
258};
259
260static const struct soc_info x1000_soc_info = {
261 .num_pwms = 5,
262};
263
264static const struct of_device_id jz4740_pwm_dt_ids[] = {
265 { .compatible = "ingenic,jz4740-pwm", .data = &jz4740_soc_info },
266 { .compatible = "ingenic,jz4725b-pwm", .data = &jz4725b_soc_info },
267 { .compatible = "ingenic,x1000-pwm", .data = &x1000_soc_info },
268 {},
269};
270MODULE_DEVICE_TABLE(of, jz4740_pwm_dt_ids);
271
272static struct platform_driver jz4740_pwm_driver = {
273 .driver = {
274 .name = "jz4740-pwm",
275 .of_match_table = jz4740_pwm_dt_ids,
276 },
277 .probe = jz4740_pwm_probe,
278};
279module_platform_driver(jz4740_pwm_driver);
280
281MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
282MODULE_DESCRIPTION("Ingenic JZ4740 PWM driver");
283MODULE_ALIAS("platform:jz4740-pwm");
284MODULE_LICENSE("GPL");